Into The Nano Era: Moore's Law Beyond Planar Silicon CMOS

Springer Series in MATERIALS SCIENCE 106 Springer Series in MATERIALS SCIENCE Editors: R. Hull R. M. Osgood, Jr. ...

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Springer Series in

MATERIALS SCIENCE

106

Springer Series in

MATERIALS SCIENCE Editors: R. Hull

R. M. Osgood, Jr.

J. Parisi

H. Warlimont

The Springer Series in Materials Science covers the complete spectrum of materials physics, including fundamental principles, physical properties, materials theory and design. Recognizing the increasing importance of materials science in future device technologies, the book titles in this series reflect the state-of-the-art in understanding and controlling the structure and properties of all important classes of materials. 98 Physics of Negative Refraction and Negative IndexMaterials Optical and Electronic Aspects and Diversified Approaches Editors: C.M. Krowne and Y. Zhang 99 Self-Organized Morphology in Nanostructured Materials Editors: K. Al-Shamery and J. Parisi 100 Self Healing Materials An Alternative Approach to 20 Centuries of Materials Science Editor: S. van der Zwaag 101 New Organic Nanostructures for Next Generation Devices Editors: K. Al-Shamery, H.-G. Rubahn, and H. Sitter 102 Photonic Crystal Fibers Properties and Applications By F. Poli, A. Cucinotta, and S. Selleri 103 Polarons in Advanced Materials Editor: A.S. Alexandrov

104 Transparent Conductive Zinc Oxide Basics and Applications in Thin Film Solar Cells Editors: K. Ellmer, A. Klein, and B. Rech 105 Dilute III-V Nitride Semiconductors and Material Systems Physics and Technology Editor: A. Erol 106 Into The Nano Era Moore’s Law Beyond Planar Silicon CMOS Editor: H.R. Huff 107 Organic Semiconductors in Sensor Applications Editors: D.A. Bernards, R.M. Ownes, and G.G. Malliaras 108 Evolution of Thin-Film Morphology Modeling and Simulations By M. Pelliccione and T.-M. Lu 109 Reactive Sputter Deposition Editors: D. Depla and S. Mahieu 110 The Physics of Organic Superconductors and Conductors Editor: A. Lebed

Volumes 50–97 are listed at the end of the book.

Howard R. Huff Editor

Into The Nano Era Moore’s Law Beyond Planar Silicon CMOS

With 136 Figures

Dr. Howard R. Huff 2116 Cumberland Hill Drive Henderson, NV 89052, USA E-mail: [email protected]

Series Editors: Professor Robert Hull

Professor Jürgen Parisi

University of Virginia Dept. of Materials Science and Engineering Thornton Hall Charlottesville, VA 22903-2442, USA

Universität Oldenburg, Fachbereich Physik Abt. Energie- und Halbleiterforschung Carl-von-Ossietzky-Strasse 9–11 26129 Oldenburg, Germany

Professor R.M. Osgood, Jr.

Professor Hans Warlimont

Microelectronics Science Laboratory Department of Electrical Engineering Columbia University Seeley W. Mudd Building New York, NY 10027, USA

Institut für Festkörperund Werkstofforschung, Helmholtzstrasse 20 01069 Dresden, Germany

Springer Series in Materials Science ISSN 0933-033X ISBN 978-3-540-74558-7

e-ISBN 978-3-540-74559-4

Library of Congress Control Number: 2008925374 © Springer-Verlag Berlin Heidelberg 2009 This work is subject to copyright. All rights are reserved, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilm or in any other way, and storage in data banks. Duplication of this publication or parts thereof is permitted only under the provisions of the German Copyright Law of September 9, 1965, in its current version, and permission for use must always be obtained from Springer-Verlag. Violations are liable to prosecution under the German Copyright Law. The use of general descriptive names, registered names, trademarks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. Typesetting: Data prepared by VTEX using a Springer TEX macro package Cover concept: eStudio Calamar Steinen Cover production: WMX Design GmbH, Heidelberg SPIN: 12112692 57/3180/VTEX Printed on acid-free paper 987654321 springer.com

This snapshot of the IC industry and several opportunities for enhanced growth in the coming nanotechnology era is dedicated, in memoriam, to Robert Cahn and Fred Seitz, who passed away during the preparation of this book. Robert Cahn (1924–2007), FRS, University of Cambridge, and Fred Seitz (1912–2008), Rockefeller University, President, Emeritus and National Academy of Sciences, Past President

Foreword Silicon and Electronics

The readership of this monograph, Into The Nano Era – Moore’s Law Beyond Planar Silicon CMOS may be surprised to find that there was a time when silicon materials did not reign supreme. While silicon was utilized both before and during World War I for coded wireless detectors, it was quickly replaced by Vacuum Tube Electronics in the late 1910s and 1920s. The ham radio proponents often preferred to use galena (PbS) in the 1920s, a naturally occurring mineral which was much less expensive than polycrystalline silicon. In the late 1930s and with the advent of World War II, however, silicon became the preferred material for radar detectors. Silicon has continued to be the dominant (and pre-eminent) material during the rest of the twentieth century (although germanium and silicon transistors were commercialized during the 1950s). During the last several decades, we have come from the electronics revolution initiated by the transistor in the late 1940s to the microelectronics revolution, exemplified by the integrated circuit (IC) that was invented in the late 1950s, to today where we are on the verge of the nano-technology Revolution. Of course, many other materials are utilized in today’s most advanced ICs and surely this will be the case in the nano-technology of the future; yet, the base still appears to include silicon. Howard Huff and his authors have developed this monograph to guide us into the nano-technology era by focusing on some current aspects of silicon materials relevant to the fabrication of ICs and several potential opportunities in the nano era. The importance of defects and their control, both in the as-grown silicon and during the chip-making process, is emphasized. Indeed, the admonition to make certain that the quality of the silicon used in chips should be examined carefully before rather than after making the chips repeats one of the basic principles that we discovered during World War II. That is, we found by using metallurgical-grade (polycrystalline) silicon in the 1940s that the erratic behavior and irreproducibility of the electronic characteristics of detectors was dependant on the prior history of the sili-

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con material utilized. This monograph not only stirs up old memories of the earlier days but brings me to further appreciate the fabrication of today’s opto-electronic devices. And such also appears to be the case with the “bottom-up” fabrication technology in the nano era. Indeed, it appears that the drive to miniaturization is finally approaching the stage where quantum effects will become of the essence, which is quite an achievement when I recall the ham radio years of the 1920s and the earliest silicon materials utilized for radar in the late 1930s and early 1940s. I wish Howard Huff and the personnel involved in the creation of this monograph and its readership well in the exciting and never-ending journey towards the next revolution in information and communications technology – the nano era. New York, March 2008

Fred Seitz (deceased March 2008)

Foreword Silicon and the III–V’s: Semiconductor Electronics (Electron, Hole, and Photon) Forever

Without silicon and the III–V semiconductors, today’s world of electronics does not exist, would not exist, likely could not exist. There is no substitute for the semiconductor, Si ranking at the top. I learned about transistors and semiconductors from John Bardeen, and then about diffused Si devices, in their inception, with John Moll (and Carl Frosch and the oxide) before learning further from work, colleagues, meetings, and journal articles. Very early, for example, it was a trick of junction assembly of my Si tunnel diodes that revealed phonon-assisted tunneling so strikingly (1959), the first unambiguous experiment showing inelastic tunneling, which made it possible for R.H. Hall and me to introduce into solid-state science and technology (via Si!) the now-universal tunneling spectroscopy. Why deviate from Si, why go off exploring the III–V’s, when Si proved to be so rich and wondrous – with Bell Labs’ oxide and diffused device technology at its pinnacle; indeed, the very technology that, moving west, spawned the “chip” and Silicon Valley? And what about Si, and its further role? Can we now be so bold (so rude) and commit the sin of even asking the question? At the 1962 Institute of Radio Engineers (I.R.E., now the I.E.E.E.) Solid State Device Research Conference, Art D’Asaro and I engaged in a friendly argument with Bob Noyce in which we defended the case for the III–V’s (light emitters) while Bob argued for a still greater future for Si. Bob knew that Art and I, at Bell Labs, knew about Si from the beginning. Why leave it? We, and Noyce, were both right and both wrong! The two, Si and the III–V’s, are complementary. We need both. We need the electron, hole, and photon, the three so unique in performance and tied together so incestuously across the energy gap. Recall: no energy gap, no semicon-

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ductor, no electron and hole, no transistor, no light emitter, no solar cell! What else is like this, and technologically so tractable? Nothing approaches the uniqueness of the semiconductor in what it does and in how it allows us to impose, to render amazing tiny sub-microscopic connected active-device geometries in a crystalline substance, in a nano-ordered substance, and as a consequence realize unbelievable electronic functions – the “chip.” We can now properly ask: When we were shown in John Moll’s group (Bell Labs, 1954–1955) a bag full of DuPont Si needles – nano-rods, as it were – should we have tried to attack at such an opportune moment nano-assembly? To, say, assemble at once active microscopic circuitry? Or should we have proceeded, as happened, to grow crystals from the needles (i.e., “self-assemble” bulk crystalline Si atom-byatom) and proceed bit-by-bit to the “chip”? To be sure, should we have proceeded, Oh, so slowly but, Oh, so successfully? Who could have predicted, in the beginning, all that would be needed to make today’s Si “chip”? And now, in contrast, where and what is the science and technology of direct nano-assembly? Is it, say, an ultra-tiny complex system that must take on great variety and form and not be just the bland simple atom-stacking of crystal growth? Is this (a complex system) even possible without invoking some form of sorcery, i.e., without facing the abyss of total guessing or outright chicanery? Does it make sense and in what substance? Do we wish to abandon Si? If so, why? We not only build in Si, it teaches us. For example, it is the Si p–n–p–n switch, in its successful form as the thyristor, that teaches us why a CMOS element in a “chip” breaks down or why a III–V transistor laser switches and exhibits negative resistance. As a matter of fact, it was the p–n–p–n switch that took Si to “Silicon Valley.” It is Si that we have most studied and understand best, and that informs us further in how to realize a still smaller and more sophisticated “chip.” If there is anything past the integrated circuit, the “chip,” it is Si that guides us towards it. From the standpoint of the III–V semiconductor, heterostructures and direct energy gaps, and quantum wells, we see silicon’s strengths and weaknesses. We see, in comparison with III–V’s, better and worse choices, what can be done profitably and what can not. Silicon, from 1-ton single crystal ingots to the tiniest integrated circuits, is so valuable and such a perfect guide to what is possible in the construction of ultra-small devices, that we must continue to study it. We cannot afford not to, and thus owe a considerable debt to our colleagues Howard Huff and his authors for exposing us to more Si science and technology as we enter the nanotechnology era. The most questionable topic is that of device self-assembly. We know it works for crystal growth, even in the case of a 1-ton Si crystal, but does it work for the most intricate and tiniest integrated circuits? Note that carbon self-assembles into diamond, but we polish and pattern to develop the mirror facets that make diamond an attractive and expensive jewel. When Si self-assembles, it is too simple. We pattern and process it, at increasingly tiny size, into a more complex and useful form, into an integrated circuit, a “chip.” Now how small can it be, or do we look for other ways (heterojunctions, quantum wells, etc.) to obtain higher performance? Concern-

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ing “self-assembly,” where and what is the science to make it real and not merely a wish or just a name? I consider Si and its study, with the aid and added perspective of the III–V semiconductor (and quantum wells), as holding the answer to whether “self-assembly” makes sense. We all get old studying the abundantly rich and fertile semiconductor, but the semiconductor itself, because of the gift of the electron, hole, and photon, and their amazingly connected performance, does not weaken or age. It is not going away. We have no choice but to study Si and the III–V family of materials. Nothing else has worked so well in electronics or promises so much more. There is reason for the semiconductor to prevail, and for us to welcome this new book of Howard Huff and his authors. Urbana, April 2008

Nick Holonyak, Jr.

Preface

The revolutionary impact of the discovery of transistor action by John Bardeen and Walter Brattain of Bell Labs in December 1947 was not anticipated. Similarly, the importance of William Shockley’s invention at Bell Labs in January 1948 of the junction transistor (which was not experimentally demonstrated until 1950, although proof-of-concept using a non-colinear configuration was shown in 1949) was not recognized immediately. The transistor’s potential was only recognized after it became evident during the 1950s that the transistor – with its much lower power dissipation – could be used to do significantly more than simply mimic vacuum tube electronics in solid-state. It was the invention of the Integrated Circuit (IC) by Jack Kilby of Texas Instruments in 1958 (germanium in the mesa configuration) and, independently, by Bob Noyce of Fairchild in 1959 (silicon in the planar configuration, built upon Jean Hoerni’s research at Fairchild in late 1957), that initiated the microelectronics revolution. Even then, however, the implications were barely perceived. The bipolar IC entered into high-volume production in the mid-to-late 1960s, followed by the MOSFET IC in the early 1970s. Patrick Haggerty’s vision at Texas Instruments in the early 1960s of the pervasiveness of the silicon microelectronics revolution, based on the concept of the “learning curve” (i.e., the concomitant reduction in the cost of fabrication with the increased volume of production) and market elasticity, was one of immeasurable significance to the fledging IC industry. Concurrently, Gordon Moore at Fairchild Semiconductor in 1965 made a remarkably prescient assessment of memory component growth, based initially on bipolar and then on MOS memory density trends: A semi-log graph of the number of memory bits in an IC versus the date of initial production was a straight line, representing almost a doubling each year. Moore’s observation (updated at Intel in 1975 to about 18 months per doubling and subsequently re-affirmed in 1995) showed that a viable market was indeed practical, and gave impetus to the industry. His analysis became enshrined as Moore’s law and set the cadence for technology advancement, e.g., as laid out in the International Technology Roadmap for Semiconductors (ITRS). These

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business-oriented considerations, moreover, combined with Bob Dennard’s invention of the one-transistor/one-capacitor dynamic random access memory cell (DRAM) at IBM in 1968 and the related transistor scaling methodologies introduced by Dennard and colleagues at IBM in 1972, established the paradigm for the progression of IC fabrication technology (from a minimum feature size of about 10 μm in the early 1970s, to sub-35 nm in the present era) that has facilitated the explosive growth and application of the MOSFET IC (and subsequently the CMOS IC) during the past 35 years. The myriad of new electronic products and the creation of new market segments was not (and perhaps could not be) foreseen by the researchers involved. Indeed, Robert Lucky noted in Engineering Tomorrow (edited by J. Fouke, T.E. Bell, and D. Dooling, IEEE Press, 2000) that “there is no a priori way to determine what will tip a market. It’s a fundamental instance of chaos in group dynamics. And that makes it fundamentally difficult to predict future societal behaviors in the adoption of technologies.” More than luck is involved; nevertheless, the next application is often a surprise. And here we are, on the brink of the 50th anniversary of the invention of the IC, in the nano-technology era, wherein critical dimensions on an IC chip, such as the physical channel length, is less than 35 nm. Will silicon continue to be the preeminent active semiconductor material, and will Moore’s law continue unabated, albeit in a broader economic venue? Indeed, are we wiser now in comprehending that fundamental research, per se, inevitably will lead to new material and device configurations as well as new market opportunities, barely (if at all) perceived at the present time? The research agenda is yet our best opportunity to spawn new innovations to sustain industry expansion to the next major set(s) of global applications. In that regard, this monograph addresses these questions by reflecting upon the scientific and technological breakthroughs that enabled the microelectronics era, providing a firm foundation for ensuing research, and offering a glimpse of what is to come in the nano-technology era. Accordingly, a review and assessment of topics fundamental to silicon materials and MOSFET device structures is presented, to identify potential nano-technology research directions and possible nano-technology applications. The monograph is divided into three sections, similar to the format of the Spring 2005 issue of INTERFACE (published by The Electrochemical Society) from which this book has its genesis. The first section reviews aspects of the historical foundations of our industry. The second section proceeds to examine the silicon material and device structures that are the foundation for state-of-the art IC technology. The third section then presents perspectives of future directions for the nano-technology era. Interestingly, the authors do not anticipate that the current silicon materials/IC industry infrastructure will simply dissolve. The global captains of industry, in-point-offact, would not allow this. Rather, the initial new applications in the nano-technology era may indeed come about via integration and merging of new materials with (leading edge) IC structures, forging new applications that may be presently envisioned, even as the IC industry drives towards the sub 10 nm physical MOSFET channel

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length. It is the anticipation of what comes next, however, that will require our most creative perceptions and, most probably, will produce the greatest surprise(s). Historical Background Silicon, and more recently, related group-IV material systems such as silicon-germanium, have been utilized (with silicon) for IC fabrication over the past ∼45 years or so. While silicon and group-IV material systems are anticipated to continue to be utilized in future IC products, the group III–V materials may also concurrently be adopted in order to achieve continued improvement in the device active channel characteristics and related IC performance. Robert Cahn presents an historical perspective of silicon and the silicon revolution in an enchanting introduction titled Silicon: Child and Progenitor of Revolution. The phenomenal growth of the IC industry is discussed in a decidedly upbeat fashion by Dan Hutcheson in The Economic Implications of Moore’s Law. Perhaps Gordon Moore described it best when he recently noted that “. . . you are once again reminded that this is no longer just an industry, but an economic and cultural phenomenon, a crucial force at the heart of the modern world.” Moore further noted that “no exponential is forever; but ‘forever’ can be delayed.” Indeed, we will depend on a new generation of research personnel to maintain and, perhaps, extend Moore’s law into the nano-technology world and the next group of big applications. State-of-the-Art The characterization, annihilation, and selective utilization of defects to achieve superior IC performance, yield, and reliability is a cornerstone of the IC industry. Because many of the phenomena discussed are structure-sensitive, the “processstructure-property” approach is used to describe the characteristics of modern electronic/opto-electronic ICs which utilize III-V compounds in conjunction with silicon (and germanium again). Specifically, the fabrication process determines the material structure, which in turn determines the subsequent material properties and, therefore, the IC characteristics. Jim Chelikowsky notes that “computers built with silicon can be used to solve for the electronic properties of silicon itself.” Chelikowsky reviews these computational approaches from first principles in Using Silicon to Understand Silicon. Stefan Estreicher continues this first-principles study of point defects in silicon in Theory of Defects in Si: Past, Present and Challenges. These theoretical considerations, in combination with microscopic experiments, have led to an understanding of silicon that is incomparable to that of any other material studied in the technological era. The selective utilization of defects, as grown in the silicon crystal as well as process-induced during device/IC fabrication, and their mutual interactions, has achieved superior IC performance. Andrei Istratov, Tonio Buonassisi, and Eicke Weber pursue several aspects of these phenomena and, in particular, indicate the viability of such an approach for the rapidly expanding defectengineered silicon photovoltaics initiative (with quantities of silicon usage fast approaching that of the IC industry) in Structural, Elemental, and Chemical Complex

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Defects in Silicon and Their Impact on Silicon Devices. Materials science and engineering will continue to be critical but it appears that the art and science wherein properties of materials may be dictated not as much by what atoms the materials consist of (taking some liberty here) but rather how they are arranged together will be the sine qua non of opto-electronic devices and circuits in the nano-era. The theme of defects and their control may be further extended by realizing that the surface itself may be considered a giant defect, as noted by H.C. Gatos of M.I.T. and others in the 1960s. The characterization and control of the silicon surface is a fundamental requirement for stable device and IC characteristics. Martin Frank and Yves Chabal present our current understanding of surfaces and interfaces as well as their unique position in silicon micro-electronics, in Surface and Interface Chemistry for Gate Stacks on Silicon. This section concludes with two device-focused articles. Patricia Mooney presents a summary of current trends in silicon-based nano-electronics – in particular the enhancement of carrier mobilities – in Enhanced Carrier Mobility for Improved CMOS Performance. The use of variously configured, sequential compositions and combinations of strained silicon-germanium (utilizing carbon as appropriate) to produce strain at the silicon channel surface for various MOSFET configurations permits electron and hole mobilities higher than predicted by the universal mobility curves. Further materials opportunities are noted, wherein an NMOS [PMOS] transistor exhibits optimal electron [hole] mobility for the (100) [(110)] silicon wafer orientation (in the 110 direction for both surfaces). Methods of fabricating substrates to enhance both NMOS and PMOS performance are described as a hybrid orientation technology (HOT), and a simplified hybrid orientation technology (SHOT). Finally, Tsu-Jae King Liu and Leland Chang discuss a host of silicon-based advanced transistor structures and associated materials, based on the conventional “top-down” IC fabrication methodology in Transistor Scaling to the Limit. They note that these efforts are expected to extend the ITRS to a physical channel length in the single-digits, consistent with IC leakage current, power-supply voltage, and power-delay product specifications. Future Directions The final section of this monograph covers several evolving opportunities for future nano-technology. Ted Kamins discusses the alternative “bottom-up” approach for device fabrication in the nano-world in Beyond CMOS Electronics: Self-Assembled Nanostructures. Here we see the concept of “self-assembly,” introduced by way of an example in the fabrication of in-plane nanowires (5 nm in diameter by several hundred nm in length) for connections between active circuit components to enhance IC performance. Indeed, we are still basically using silicon and its myriad fabrication process technologies in conjunction with the self-assembly concept. Mircea R. Stan, Garrett S. Rose, and Matthew M. Ziegler then discuss Hybrid CMOS / Molecular Integrated Circuits. The authors look to further the pervasiveness of silicon technology by “piggy-backing” the nano-technology world onto the ever-shrinking IC devices on a chip. In these initial nano-technology applications,

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the authors suggest that the (nano) molecular assembled structure will be electrically connected to the upper surface of a programmable logic array (PLA), based on majority-carrier logic, with appropriate wiring schemas. It is anticipated that a nanotechnology single-electron transistor can be operated in conjunction with a CMOS logic IC at room temperature (an extremely important requirement), thereby enhancing the performance of advanced logic CMOS devices beyond what they could achieve on their own. Delving further into the nano-world, Andre DeHon notes that at the current stage of the micro/nano-electronics revolution, we no longer have the orders of magnitude difference between the size of the IC and the constituent atoms, which previously allowed the crafting of large collections of atoms into “perfect” devices. Accordingly, Andre notes that circuit designers and architects now need to take some of the responsibility for dealing with truly atomic-scale imperfections and uncertainty in Sublithographic Architecture: Shifting the Responsibility for Perfection. Finally, David P. DiVincenzo discusses Quantum Computing. Besides the potential realization of fabricating qubits (quantum bits) in Josephson junction circuits and ion traps, the author discusses the role of semiconductor quantum dots. He notes that III–V heterostructures might indeed facilitate the fabrication of a quantum computer. Interestingly, the scientific literature is also discussing the utilization of an isolated silicon double quantum dot as a qubit. The author notes at the end of his article: “It may be hoped that in ten years the details of this chapter will be thoroughly obsolete, and completely new and unanticipated effects will have been seen and controlled in such a way that it makes the path to a quantum computer clear. We will see.” Indeed, we shall see more clearly as we enter the nano-technology era to identify the next big technologies that can be wrought from the nano-world for the betterment of humankind. Finally, we are fortunate to have four additional brief contributions to the monograph rounding out this perspective of Into The Nano Era: Moore’s Law Beyond Planar Silicon CMOS. Fred Seitz leads off with a brief introductory comment, Silicon and Electronics, about the evolution of electronics over the past 75 years. This is followed by Nick Holonyak’s reflections on Silicon and The III–V’s: Semiconductor Electronics (Electron, Hole, and Photon) Forever. We conclude with two afterwords by the Nobel Prize awardees Herb Kroemer and Horst Stormer. Herb Kroemer’s contribution is titled Nano-Whatever: Do We Really Know Where We Are Heading?, reprinted from Phys. Stat. Sol. (a) 202, No. 6, 957–964 (2005). Horst Stormer’s afterword is titled Silicon Forever! Really?, from the 2006 issue of Solid-State Electronics, 50, No. 4, 516–519 (2006). Clearly, we will all have benefited by these colleagues sharing their perspectives with us as we enter the nano-technology era. Acknowledgments We appreciate the contributions of Len Feldman and Konstantin Likharev for their participation in the earlier version of this endeavor, published by The Electrochemical Society in the Spring 2005 issue (14, No. 1) of INTERFACE. We also appreciate Mary Yess, Deputy Executive Director of The Electrochemical Society, for her

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fine assistance during the development of the original INTERFACE issue. Appreciation and thanks are due to Claus Ascheron, Physics Editorial IV, Executive Editor Physics and Ms. Adelheid Duhm, Associate Editor Physics, of Springer-Verlag for their strong interest and guidance throughout the development and production of this book. Finally, this book is dedicated to Robert Cahn and Fred Seitz, both of whom passed away during the preparation of Into the Nano Era: Moore’s Law Beyond Planar Silicon CMOS. Henderson, NV, April 2008

Howard R. Huff

Contributors’ Acknowledgement

This volume would not have come into existence without the unrelenting efforts of Howard Huff and his dedicated wife Helen. Howard Huff succeeded to describe in the Preface the whole history of the semiconductor revolution of the last 60 years, but he left out one important person: Huff, as he likes to be called, himself. First, he promoted the field through his own research at Fairchild, later National Semiconductors. Later, his work had even more impact in the field, we can say Huff’s contributions were key for the Si IC technology following the (accelerated) Moore’s law. This became especially obvious during his years at Sematech where he was instrumental in establishing the ITRS Si roadmap. He went on to make sure that regular, very carefully worked-out updates were created, mainly by consensus of the members of the different task teams. This careful work made the Si roadmap immensely valuable for all planning processes, especially of the equipment supplier industry. Recently, his interest was specifically focused on issues related to the gate stack and the search for new gate dielectrics. In addition, he was responsible for the big Si conferences organized each four years for more than 40 years with the Electrochemical Society, the proceedings of which contain an impressive body of knowledge in the field of Si materials science and technology, and continue to be frequently cited. Huff kept saying in the last decade of the last millennium that the Si roadmap is only layed out till 2010 as he will be dead afterwards and thus does not care beyond that date. Well, Huff, in this single instant we might prove you wrong, we expect to have you with us beyond 2010, and the ITRS Si roadmap of course stretches by now far beyond 2010.

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Contributors’ Acknowledgement

It has been a special honor for all of us to work closely with Huff in this book project, and we look forward to exciting initiatives in this important field from Huff in the years to come! Tonio Buonassisi, Patricia Cahn, Yves J. Chaba, Leland Chang, Jim Chelikowsky, Andre DeHon, David P. DiVincenzo, Stefan K. Estreicher, Martin M. Frank, Nick Holonyak, Jr., Dan Hutcheson, Andrei Istratov, Ted Kamins, Herbert Kroemer, Tsu-Jae King Liu, Patricia M. Mooney, Garrett S. Rose, Fred Seitz, Mircea R. Stan, Horst L. Stormer, Eicke R. Weber, Matthew M. Ziegler

Contents

Foreword: Silicon and Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Foreword: Silicon and the III–V’s: Semiconductor Electronics (Electron, Hole, and Photon) Forever . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii List of Contributors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxvii Part I Historical Background 1 Silicon: Child and Progenitor of Revolution R.W. Cahn† . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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2 The Economic Implications of Moore’s Law G.D. Hutcheson . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Moore’s Law: A Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 The History of Moore’s Law . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 The Microeconomics of Moore’s Law . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 The Macroeconomics of Moore’s Law . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Moore’s Law Meets Moore’s Wall: What Is Likely to Happen . . . . . . . . 2.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11 11 12 12 23 30 32 35 36 38

† Deceased.

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Part II State-of-the-Art 3 Using Silicon to Understand Silicon J.R. Chelikowsky . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 The Electronic Structure Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 The Empirical Pseudopotential Method . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Ab Initio Pseudopotentials and the Electronic Structure Problem . 3.3 New Algorithms for the Nanoscale: Silicon Leads the Way . . . . . . . . . . 3.4 Optical Properties of Silicon Quantum Dots . . . . . . . . . . . . . . . . . . . . . . . 3.5 Doping Silicon Nanocrystals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 The Future . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

41 41 42 42 47 50 52 55 58 58

4 Theory of Defects in Si: Past, Present, and Challenges S.K. Estreicher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 From Empirical to First-Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 First-Principles Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 First-Principles Theory at Non-zero Temperatures . . . . . . . . . . . . . . . . . . 4.5 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

61 61 63 66 70 73 74

5 Structural, Elemental, and Chemical Complex Defects in Silicon and Their Impact on Silicon Devices A.A. Istratov, T. Buonassisi, E.R. Weber . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Defect Interactions in Single-Crystalline Silicon . . . . . . . . . . . . . . . . . . 5.3 Precipitation Behavior, Chemical State, and Interaction of Copper with Extended Defects in Single-Crystalline and Multicrystalline Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Precipitation Behavior, Chemical State, and Interaction of Iron with Extended Defects in Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Pathways for Metal Contamination in Solar Cells . . . . . . . . . . . . . . . . . 5.6 Effect of Thermal Treatments on Metal Distributions and on Device Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 Discussion: Chemical States of Metals in mc-Si . . . . . . . . . . . . . . . . . . . 5.8 Discussion: Interactions between Metals and Structural Defects . . . . . 5.9 Discussion: Engineering of Metal-Related Nanodefects by Altering the Distributions and Chemical States of Metals in mc-Si . . . . . . . . . . . 5.10 Summary and Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

79 79 80

84 91 96 99 101 104 106 108 109

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6 Surface and Interface Chemistry for Gate Stacks on Silicon M.M. Frank, Y.J. Chabal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Introduction: The Silicon/Silicon Oxide Interface at the Heart of Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Current Practices and Understanding of Silicon Cleaning . . . . . . . . . . . 6.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 Silicon Cleans Leading to Oxidized Silicon Surfaces . . . . . . . . 6.2.3 Si Cleans Leading to Hydrogen-Terminated Silicon Surfaces . 6.2.4 Microscopic Origin of Silicon Oxidation . . . . . . . . . . . . . . . . . . 6.2.5 Initial Oxidation of Hydrogen-Terminated Silicon . . . . . . . . . . . 6.3 High-Permittivity (“High-k”) Gate Stacks . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 Silicon Surface Preparation and High-k Growth: The Impact of Thin Oxide Films on Nucleation and Performance . . . . . . . . 6.3.3 Post-Treatment of the High-k Layer: Nitridation . . . . . . . . . . . . 6.3.4 The pFET Threshold Voltage Issue: Oxygen Vacancies . . . . . . 6.3.5 Threshold Voltage Control: Oxygen and Metal Ions . . . . . . . . . 6.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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113 113 115 115 116 124 136 137 147 147 148 156 157 158 161 161

7 Enhanced Carrier Mobility for Improved CMOS Performance P.M. Mooney . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 7.2 Enhanced Carrier Mobility in Si under Biaxial Tensile Strain . . . . . . . . 169 7.2.1 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 7.2.2 Strain-Relaxed SiGe Buffer Layers . . . . . . . . . . . . . . . . . . . . . . . 171 7.2.3 SGOI and SSOI Substrates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 7.2.4 Defect-Free (Elastic) Strain Relaxation . . . . . . . . . . . . . . . . . . . . 178 7.3 Enhanced Hole Mobility via Biaxial Compressive Strain . . . . . . . . . . . 181 7.4 Other Methods to Increase Carrier Mobility for Si CMOS Applications 183 7.4.1 Hybrid Crystal Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 7.4.2 Uniaxial Strain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 7.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 8 Transistor Scaling to the Limit T.-J.K. Liu, L. Chang . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Planar Bulk MOSFET Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Thin-Body Transistor Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.1 Ultra-Thin Body (UTB) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . 8.3.2 Double-Gate (DG) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.3 Tri-Gate (TG) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.4 Back-Gated (BG) MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Fundamental Scaling Limit and Ultimate MOSFET Structure . . . . . . .

191 191 193 196 197 199 205 205 207

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8.5 Advanced Gate-Stack Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.1 High-k Gate Dielectrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.2 Metallic Gate Electrode Materials . . . . . . . . . . . . . . . . . . . . . . . . 8.6 Performance Enhancement Approaches . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.1 Enhancement of Carrier Mobilities . . . . . . . . . . . . . . . . . . . . . . . 8.6.2 Reduction of Parasitic Components . . . . . . . . . . . . . . . . . . . . . . . 8.6.3 Alternative Switching Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

209 209 210 213 213 215 216 216 217

Part III Future Directions 9 Beyond CMOS Electronics: Self-Assembled Nanostructures T.I. Kamins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.1 Conventional “Top-Down” Fabrication . . . . . . . . . . . . . . . . . . . . 9.1.2 “Bottom-Up” Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Strain-Induced Nanostructures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 Metal-Catalyzed Nanowires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.1 Catalyst Nanoparticles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.2 Nanowire Growth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.3 Germanium and Compound-Semiconductor Nanowires . . . . . . 9.3.4 Doping Nanowires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.5 Connecting Nanowires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.6 Comparison of Semiconducting Nanowires and Carbon Nanotubes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4 Potential Applications of Metal-Catalyzed Nanowires . . . . . . . . . . . . . . 9.4.1 Field-Effect Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.2 Field-Effect Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.3 Interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Hybrid CMOS/Molecular Integrated Circuits M.R. Stan, G.S. Rose, M.M. Ziegler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.1 Top-Down Fabrication vs. Bottom-Up Assembly . . . . . . . . . . 10.1.2 Typical Molecular Device Characteristics . . . . . . . . . . . . . . . . . 10.2 MolMOS: Integrating CMOS and Nanoelectronics . . . . . . . . . . . . . . . 10.2.1 The CMOS/Nano Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.2 CMOS/Nano Co-design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 The Crossbar Array for Molecular Electronics . . . . . . . . . . . . . . . . . . . 10.3.1 Molecular Memory Structures . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.2 Programmable Logic via the Crossbar Array . . . . . . . . . . . . . .

227 227 227 228 229 235 235 238 241 243 244 250 251 251 252 252 253 254 257 257 257 258 259 260 262 264 265 267

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10.3.3 Signal Restoration at the Nanoscale: The Goto Pair . . . . . . . . 10.3.4 Hysteresis and NDR based Devices in Programmable Logic . 10.4 MolMOS Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.1 The CMOS Interface & I/O Considerations . . . . . . . . . . . . . . . 10.4.2 Augmenting the PMLA with CMOS . . . . . . . . . . . . . . . . . . . . . 10.4.3 Array Access for Programmability . . . . . . . . . . . . . . . . . . . . . . 10.4.4 A More Complete Picture of the Overall Architecture . . . . . . 10.5 Circuit Simulation of MolMOS System . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.1 Device Modeling for Circuit Simulation . . . . . . . . . . . . . . . . . . 10.5.2 Functional Verification of a Stand-Alone Nanoscale PMLA . 10.6 Conclusions and Future Directions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

268 270 272 272 272 273 274 276 276 276 278 279

11 Sublithographic Architecture: Shifting the Responsibility for Perfection A. DeHon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Revising the Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Bottom-Up Feature Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 Regular Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 Statistical Effects Above the Device Level . . . . . . . . . . . . . . . . . . . . . . 11.4.1 Defect and Variation Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.2 Differentiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5 NanoPLA Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.6 Defect Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.6.1 Wire Sparing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.6.2 Crosspoint Defects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.6.3 Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.6.4 Roundup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.7 Testing and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.8 New Abstraction Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.8.1 Lessons from Data Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.8.2 Abstraction Hierarchy for Computation . . . . . . . . . . . . . . . . . . 11.9 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

281 281 282 283 283 283 284 285 288 288 290 291 291 292 293 293 293 295 295

12 Quantum Computing D.P. DiVincenzo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 What Is Quantum Computing? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4 Quantum Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5 Realizing a Quantum Computer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 Physical Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6.1 Josephson Junction Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6.2 Semiconductor Quantum Dots . . . . . . . . . . . . . . . . . . . . . . . . . .

297 297 298 299 301 303 306 306 308

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12.6.3 Ion Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 12.6.4 Outlook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 Part IV Afterwords 13 Nano-Whatever: Do We Really Know Where We Are Heading? Phys. Stat. Sol. (a) 202(6), 957–964 (2005) H. Kroemer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1 Introduction: “Nano-Talk = Giga-Hype?” . . . . . . . . . . . . . . . . . . . . . . . 13.2 From Physics and Technology to New Applications . . . . . . . . . . . . . . 13.2.1 Kroemer’s Lemma of New Technology . . . . . . . . . . . . . . . . . . 13.2.2 Three Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.3 Lessons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3 Roots of Nano-Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4 Back to the Future: Beyond a Single Degree of Quantization . . . . . . . 13.4.1 Quantum Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.2 Quantum Dots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5 More Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5.1 Lithography Alternatives for the Nanoscale . . . . . . . . . . . . . . . 13.5.2 “Loose” Nanoparticles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6 “Other” Quantization Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.1 Charge Quantization and Coulomb Blockade . . . . . . . . . . . . . . 13.6.2 Magnetic Flux Quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.6.3 Spintronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7 Meta-Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.8 Research vs. Applications Re-visited . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

317 317 317 317 318 319 320 320 320 321 322 322 322 323 323 323 324 324 325 326 326

14 Silicon Forever! Really? Solid-State Electr. 50(4), 516–519 (2006) H.L. Stormer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.1 The End of Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.2 The “Beginning” of Architecture . . . . . . . . . . . . . . . . . . . . . . . . 14.2.3 Silicon Stands Tall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.4 The Silicon Wart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.5 Beyond Lithography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4 Acknowledgements and Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5 Citations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

327 327 327 328 329 330 331 332 333 333

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

List of Contributors

Tonio Buonassisi Assistant Professor of Mechanical Engineering Massachusetts Institute of Technology 77 Massachusetts Avenue, 35-213 Cambridge MA 02139, USA [email protected] Robert W. Cahn† Yves J. Chabal Department of Materials Science and Engineering University of Texas at Dallas 800 W. Campbell Rd., M/S RL10 Richardson, TX 75080, USA [email protected] Leland Chang Manager, Design and Technology Solutions IBM T.J. Watson Research Center P.O. Box 218 Yorktown Heights NY 10598, USA [email protected]

James R. Chelikowsky Institute for Computational Engineering and Sciences (ICES) (C0200) ACES Building, Room 4.324 201 East 24th Street ACES 1 University Station University of Texas at Austin Austin, TX 78712, USA [email protected] Andre DeHon University of Pennsylvania Department of Electrical and Systems Engineering 200 S. 33rd Street Philadelphia, PA 19104, USA [email protected] David P. DiVincenzo IBM T.J. Watson Research Center P.O. Box 218 Yorktown Heights, NY 10598, USA [email protected] Stefan K. Estreicher Paul Whitfield Horn Professor Physics Department - ms 1051 Texas Tech University Lubbock, TX 79409, USA [email protected]

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Martin M. Frank IBM T.J. Watson Research Center Room 5-117 1101 Kitchawan Road Yorktown Heights, NY 10598, USA [email protected]

Garrett S. Rose Dept. of ECE Polytechnic University Five MetroTech Center Brooklyn, NY 11021, USA [email protected]

Dan Hutcheson VLSI Research, Inc. 2880 Lakeside Drive, Suite 350 Santa Clara, CA 95054, USA [email protected]

Fred Seitz Rockefeller University President Emeritus New York, NY 10065, USA

Andrei Istratov 9635 NW Shadywood Ln. Portland, OR 97229, USA andrei.istratov@ silitronic.com Ted Kamins Hewlett-Packard Laboratories 1501 Page Mill Road - M/S 1123 Palo Alto, CA 94304-1100, USA [email protected] Herbert Kroemer ECE Department University of California Santa Barbara, CA 93106-9560, USA [email protected] Tsu-Jae King Liu 42063 Benbow Drive Fremont, CA 94539, USA [email protected] Patricia M. Mooney Professor and Canada Research Chair in Semiconductor Physics Physics Department Simon Fraser University 8888 University Drive Burnaby, BC V5A 1S6, Canada [email protected]

Mircea R. Stan Dept. of ECE, University of Virginia, 351 McCormick Road Charlottesville, VA 22904, USA [email protected] Horst L. Stormer Dept. Physics Columbia University 704 Pupin Hall (Mail Code 5255) 538 West 120th Street New York, NY 10027, USA [email protected] Eicke R. Weber Fraunhofer-Institut für Solare Energiesysteme ISE Heidenhofstr. 2 79110 Freiburg, Germany eicke.weber@ ise.fraunhofer.de Matthew M. Ziegler IBM T.J. Watson Resaerch Center 1501 Kitchawan Road, P.O. Box 218 Yorktown Heights, NY 10598, USA [email protected]

Part I

Historical Background

1 Silicon: Child and Progenitor of Revolution R.W. Cahn

Antoine Lavoisier, the pioneering French chemist who (together with Joseph Priestley in England) identified oxygen as an element and gave it its name, in 1789 concluded that quartz was probably a compound with an as-yet undiscovered but presumably extremely common element. That was also the year in which the French Revolution broke out. Five years later, the Jacobins accused Lavoisier of offences against the people and cut off his head, thereby nearly cutting off the new chemistry. It was not until 1824 that Jöns Berzelius in Sweden succeeded in confirming Lavoisier’s speculation by isolating silicon. Argument at once broke out among the scientific elite as to whether the newly found element was a metal or an insulator. It took more than a century to settle that disagreement decisively: As so often, when all-or-nothing alternatives are fiercely argued, the truth turned out to be neither all nor nothing. Silicon and oxygen are in fact the most abundant elements in the earth’s crust and are also very common in our galaxy. Why in particular is silicon so common? Our modern understanding of nucleosynthesis got under way at about the same time as the invention of the transistor. The great British astronomer Fred Hoyle in 1946 [1] took the first steps in working out how hydrogen first fused to generate helium and how multiple helium nuclei might then fuse to produce carbon, which in turn would fuse with more helium nuclei to progressively generate heavier elements (all of which astronomers simply call ‘metals’). An apparently insoluble energy barrier turned up against the combination of beryllium and helium to generate carbon; Hoyle proposed a possible way around this roadblock and in one of the great triumphs of modern astronomy he combined with several American colleagues to prove in detail that this escape route was indeed correct [2]. The synthesis of elements up to silicon and iron proceed in the interior of stars at temperatures exceeding 109 K. Further nucleosynthesis, of heavier elements, mostly takes place in supernovas which are even hotter. Silicon is one of the stablest elements against both fusion and fission, which is very appropriate for an element that has proved so crucial for humanity. Silicon R.W. Cahn is deceased.

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is in fact often used by astronomers as a reference standard when they estimate the cosmic abundances of different elements. Nucleosynthesis is today sometimes utilised for the improvement of semiconducting devices. The minority silicon isotope 30 Si can be transmuted into 31 P by bombardment at ambient temperature with thermal neutrons. This was first discovered by Lark-Horowitz in 1951 [3] and later applied to practical devices requiring extremely uniform phosphorus doping: the recent history of this approach, with its benefits and drawbacks, is set out by Wilkes [4]. Towards the end of the nineteenth century, silicon found a growing role as an alloying element for iron. The British metallurgist Robert Hadfield discovered some interesting properties in iron–silicon alloys with a few mass per cent of silicon and very little carbon. Systematic experiments at the end of the century by William Barrett in Dublin, Ireland, culminated in the single-phase iron–silicon alloys that for more than a century have been used for transformer laminations, saving significant money because transformers made with this alloy had very low core losses. The American metallurgist T.D. Yensen (who later introduced the use of vacuum melting for these alloys) estimated as early as 1921 [5] that in the first 15 years of silicon– iron, the use of this alloy family had returned savings in electrical power generation and transmission sufficient to finance the building of the Panama Canal – and this was before the mastery of crystallographic textures further improved the performance of silicon–iron transformer laminations. This early use of silicon thus foreshadowed the extraordinary financial savings and untold applications resulting from the introduction of transistors and integrated circuits, half a century later. A detailed account of the development of silicon-iron was written by J.L. Walter of the GE (Central) Research Laboratory [6]. The electrical uses of silicon began hesitatingly. Crystal rectification, making use of cat’s whisker counter-electrodes, developed into early detectors for wireless telegraphy, and coarse-grained silicon of merely “metallurgical-grade purity” (99%) was used until World War I when vacuum tubes began to take over the role of detectors. According to a brilliant historical overview of electronic developments involving silicon [7], Jürgen Rottgardt in Germany in 1938 reported on extensive research into the possible use of cat’s whisker crystal rectifying junctions in the microwave region, which was becoming important for the incipient development of radar. Rottgardt concluded that the combination silicon–tungsten was particularly promising as a detector in this wavelength range. This was developed into a practical detector by Herbert Skinner in Britain during World War II, and independently by Russell Ohl and George Southworth at the Bell Telephone Laboratories in America. This approach gradually gained ground against the devotees of vacuum tubes due to its higher operating frequency; each advance in this field was fiercely resisted by the exponents of the preceding orthodoxy. Seitz and Einspruch [7] tell us that in 1941 Skinner wrote a bitter little poem, which included the words: “And so alone / we, fighting every inch of the way, / against those ingrained elephants of inertia / against. . . prejudice and hardened pride. . . / we fought (through forests thick with self-satisfaction) / to shorter electromagnetic wavelengths.”

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A proper understanding of the electrical properties of silicon was slow in coming. The term “semiconductor” appears to have been first used by Alexander Volta in 1782. Humphry Davy in London, in 1840, first established that ordinary metals become poorer conductors as they heat up, while a few years later, Michael Faraday, working in the same laboratory as Davy, discovered a number of compounds which conducted electricity better as they became warmer. Attention soon focused on silver sulphide, Ag2 S, and this was thoroughly studied; this compound is today known to exhibit a semiconductor–metal transition. In the early days it proved impossible to get good reproducibility, and it became the orthodoxy that semiconductors must be impure to function as such and, ipso facto, were not respectable materials because impurities necessarily vary from one sample to another. Until the end of the 1930s, most physicists looked down their noses at semiconductors and kept clear of them; some, like Wolfgang Pauli, expressed themselves in positively violent terms: a semiconductor, declared Pauli, is a “Schweinerei”.

Sir Alan Herries Wilson, 1905–1995. Photograph by Godfrey Wilson, collection of the National Portrait Gallery, London, reproduced with permission

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The man who changed all this was Alan Herries Wilson, a theoretical physicist in Cambridge, who as a young man spent a sabbatical with Werner Heisenberg in Leipzig and applied the brand-new field of quantum mechanics to issues of electrical conduction, first in metals and then in semiconductors, as reported in two Royal Society papers in 1931 [8, 9]. When he returned to Cambridge, Wilson urged that attention be paid to germanium but, as he expressed it long afterwards in a retrospective essay [10], “the silence was deafening” in response. He was told that devoting attention to semiconductors, those messy entities, was likely to blight his career among physicists. He ignored these dire warnings and in 1939 he brought out his famous book, Semi-conductors and Metals [11], which interpreted semiconductor properties, including the much-doubted phenomenon of intrinsic semiconduction, in terms of electronic energy bands. His academic career does indeed seem to have been blighted, because despite his intellectual distinction he was not promoted in Cambridge. At the end of World War II, he abandoned his university functions (a cousin of mine was his last research student) and embarked on a long and notably successful career as an industrialist, culminating in his post of chief executive of a leading pharmaceutical company. He kept clear of electronics. It was only in the 1940s that n and p-type domains in silicon were observed and their nature identified, by the metallurgists Jack Scaff and Henry Theuerer at the Bell Laboratories, collaborating with Ohl and Southworth. They determined that the sense of rectification in point-contact mode was opposite either side of a p/n junction. Many years later, Scaff published an account of these early researches [12]. The recognition that the way forward for transistor technology lay in the use of single crystals did not come until the early 1950s. Gordon Teal at the Bell Laboratories was the visionary who pushed this recognition through against fierce opposition. Teal, incidentally, was a devoted admirer of Wilson’s great book. The process of silicon crystal growth was enhanced by W.C. Dash in 1958/59 in a way that got rid of almost all dislocations and their associated electrical effects. The role of various defects, including dislocations, and more generally the role of materials science in microelectronics “past, present and future” has been surveyed by Mahajan [13, 14]. The other recognition that came in the 1950s was the imperative need for extreme purity, in germanium and in silicon. True, the material for transistors had to be doped to create controlled n and p-type domains, but such doping only worked if it was applied to ultrapure starting material. In those early days, the essential approach was zone-refining, invented at the Bell Laboratories by a chemical engineer, William Pfann: It involved the passage of successive narrow molten zones along an ingot, gradually sweeping impurities to one end. For a decade at least, zone-refining was the inescapable technique for achieving ultrapure, crystalline germanium, at a time when this semiconductor was the material of choice for transistors. However, this technique was not applicable to silicon owing to its reactivity with the walls of the zone-refining chamber material at silicon’s melting point of 1414◦ C. For silicon, thereafter, chemical purification using silicon halides and silane was used. It seems that zone-refining is still used today with germanium intended for radiation detectors. Students of electronics today may not sufficiently appreciate the importance of zone-

1 Silicon: Child and Progenitor of Revolution

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refining, without which the age of solid-state electronics, including microcircuits and nanocircuits, would have been substantially delayed. The developments which I have very concisely sketched here are beautifully treated at length in an outstanding book by Riordan and Hoddeson [15]. After the long years during which semiconductors, including silicon, were widely held in contempt, silicon has now become the most studied element in the periodic table, having overtaken iron nearly 40 years ago. The physics, chemistry and processing technology of silicon captivate a ceaseless procession of highly skilled scientists and engineers. The methods developed for shaping silicon monocrystals on an ultrafine scale, making use of controlled etching, oxidation and vacuum deposition, have recently led to some unexpected applications. The whole field of microelectromechanical systems (MEMS) is based on this technology; materials issues in MEMS have recently been reviewed [16]. MEMS already has some mass applications, including acceleration sensors for automotive airbags and tire monitoring systems, but the newest uses have some way to go before mass application. A recent study describes the microfabrication of a high-pressure bipropellant rocket engine, starting with a stack of single-crystal silicon wafers. The engine, weighing 1.2 g and generating just 1 N of thrust at a thrust power rating of 750 W, might be used “on future generations of spacecraft including microsatellites and very small launch vehicles” and be used for “‘servicing existing satellites” [17]. A parallel study describes the design of a silicon micro-turbo-generator [18]. Such a “micro-engine” is intended to be able to produce 50 W of electrical power in a device measuring less than a cubic centimetre while consuming 7–8 g of jet fuel per hour; it would achieve more than ten times the power and energy density of current batteries, at a reasonable cost. As a contribution to this form of design, the fracture strength of silicon on a very fine scale has been systematically examined in relation to factors such as the etching technique used for shaping MEMS [19]. Silicon is used in these futuristic designs not because, in mechanical engineering terms, it is the ideal material (it clearly is not), but because it can be shaped with the extreme precision needed, using techniques perfected in the microelectronics industry. I have pointed out that silicon is sometimes used as a reference element in assessing the abundances of different elements in the galaxy. This is by no means the only such use of silicon. As long ago as 1956, the International Union of Crystallography resolved to organise a project on the precision measurement of lattice parameters. 16 laboratories worldwide took part, all measuring the same batches of silicon and tungsten powders, and mostly using photographic diffraction methods; the results were published in 1960 [20]. Agreement was only about one part in 104 , including random and systematic errors. This was disconcertingly poor. Thirty years later [21], techniques had greatly improved, and in fact a silicon powder known unromantically as SRM640B was certified by the National Bureau of Standards (re-named as the National Institute of Science and Technology) to have a lattice parameter determined over 100 times more precisely than the 1960 measurement. In the interim, another completely different approach to measuring the lattice parameter of silicon, this time

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in the form of a single crystal, was invented by Bonse and Hart [22]. This made use of an X-ray interferometer which came to be known as an “Ångström ruler” [23]. This device is cut from a single highly perfect silicon crystal. X-ray interference produces a series of fringes, the spacing of which is measured by a separate, backlash-free moving crystal and the motion of which is measured by means of an optical (light) interferometer. The X-ray wavelength does not need to be known. The outcome is that the lattice parameter of silicon can be measured in terms of an optical wavelength which is in fact the modern international length standard, and thereby single-crystal silicon became a reliable secondary length standard. The latest projected use of electronic-grade silicon, the most unexpected of all, is as a tool in one of the last great unsolved problems in metrology: the science of ultimate standards. Of the seven base units of the International System of Units (the SI) – the meter, kilogram, second, ampere, kelvin, mole and candela – only the kilogram is still defined in terms of a material, the standard kilogram, made of platinum-iridium alloy and kept under conditions of extraordinary care, in a vault in Paris. Three of the base units, the ampere, mole and candela, require reference to the kilogram. Metrologists the world over are now engaged in an extremely demanding research program to replace the metal standard with another standard based upon an “invariant of nature”. Two alternative approaches are being examined: the watt balance and the X-ray crystal density (XRCD) method using silicon. The watt balance involves balancing the gravitational pull on a metal mass against an electromagnetic force derived from a coil immersed in a magnetic field: the outcome is to relate the kilogram to Planck’s constant, h. ¯ The XRCD method relies on measuring a large-scale mass in terms of the mass of a silicon atom. This method is deeply linked to Avogadro’s constant. Silicon has been chosen because the microelectronics industry has shown how to make a monocrystal of unique perfection and purity. Such a crystal is shaped into a sphere weighing nominally one kilogram, and polished to a sphericity so perfect that if it were expanded to the size of the earth, the highest mountain would be about 7 meters in height. The diameter of the sphere is measured by laser interferometry, and the number of atoms in the sphere is deduced from the lattice parameter, itself measured by means of X-ray interferometry (the Ångström ruler introduced above). The benefit of using a “perfect” sphere is that a single-size measurement (the diameter) suffices to determine the volume of the crystal. The essentials of both methods, the watt balance and XRCD, and the implications of each for metrology, are set out accessibly in a recent article [24]. These implications are analysed in great depth in two very recent papers [25, 26]; its title is “Redefinition of the kilogram: a decision whose time has come”. However, nobody in the metrology community appears to be willing just yet to express a positive preference between the two approaches – the matter is just too delicate. At present, there is a mysterious mismatch between the results of the two approaches [27]. Both methods have been examined in several countries; the chase is firmly international. Thus, the current silicon sphere has been produced in Australia. Scientists in Germany, USA, Britain, Belgium and Russia are engaged in this enterprise. The next objective is for a Russian team to produce a sufficient amount of silicon en-

1 Silicon: Child and Progenitor of Revolution

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riched to 99.99% in the majority isotope, 28 Si, to manufacture a sphere in which the atomic weight is known to a higher precision than for natural silicon. The hope is that such a sphere will reduce the uncertainty of measuring Avogadro’s constant (on the basis of the present standard kilogram) to better than one part in 107 , or alternatively (on the basis of the accepted value of Avogadro’s Constant) allow a standard kilogram of silicon to be reproduced with this kind of precision. This whole approach is only possible because of the devoted labours of generations of microelectronics specialists. My title for this introduction – Silicon: Child and Progenitor of Revolution – indicates that while the identification of silicon in a certain sense derives from a political revolution, its modern study has generated one scientific revolution after another. These revolutions all stem from the world of microelectronics, which itself involves successive revolutions.

References 1. F. Hoyle, Mon. Not. R. Astron. Soc. 106, 343 (1946) 2. F. Hoyle, E.M. Burbidge, G.R. Burbidge, W. Fowler, Rev. Mod. Phys. 29, 547 (1957) 3. K. Lark-Horowitz, in Proc. Conf. Semiconducting Materials, Reading, UK (Butterworth, London, 1951), p. 47 4. J.G. Wilkes, in Processing of Semiconductors, ed. by K.A. Jackson. Materials Science and Technology (ed. by R.W. Cahn et al.), vol. 16 (VCH, Weinheim, 1996), p. 19 5. T.D. Yensen, Elec. J. (March 1921) 6. J.L. Walter, in The Sorby Centennial Symposium on the History of Metallurgy, ed. by C.S. Smith (Gordon and Breach, New York, 1965), p. 519 7. F. Seitz, N.G. Einspruch, Electronic Genie: The Tangled History of Silicon (University of Illinois Press, Urbana, 1998) 8. A.H. Wilson, Proc. R. Soc. Lond. A 133, 458 (1931) 9. A.H. Wilson, Proc. R. Soc. Lond. A 134, 277 (1931) 10. A.H. Wilson, Proc. R. Soc. Lond. A 371, 39 (1980) 11. A.H. Wilson, Semi-conductors and Metals (Cambridge University Press, Cambridge, 1939) 12. J.H. Scaff, Metall. Trans. 1, 561 (1970) 13. S. Mahajan, K.S. Sree Harsha, Principles of Growth and Processing of Semiconductors (McGraw-Hill, Boston, 1999) 14. S. Mahajan, Prog. Mat. Sci. 49, 487 (2004) 15. M. Riordan, L. Hoddeson, Crystal Fire: The Birth of the Information Age (W.W. Norton, New York, 1997) 16. S.M. Spearing, Acta Mater. 48, 179 (2000) 17. A.P. London, A.A. Ayón, A.H. Epstein, S.M. Spearing, T. Harrison, Y. Peles, J.L. Kerrebrrock, Sens. Actuators A 92, 351 (2001) 18. K.-S. Chen, S.M. Spearing, N.N. Nemeth, AIAA J. 39, 720 (2001) 19. K.-S. Chen, A. Ayon, S.M. Spearing, J. Am. Ceram. Soc. 83, 1476 (2000) 20. W. Parrish, Acta Cryst. 13, 838 (1960) 21. M. Hart, R.J. Cernik, W. Parrish, H. Toraya, J. Appl. Cryst. 23, 286 (1990) 22. U. Bonse, M. Hart, Appl. Phys. Lett. 6, 155 (1965)

10 23. 24. 25. 26. 27.

R.W. Cahn M. Hart, Brit. J. Appl. Phys. (J. Phys. D) Ser. 21, 1405 (1968) I. Robinson, Phys. World 17, 31 (May 2004) I.M. Mills, P.J. Mohr, T.J. Quinn, B.N. Tayloer, E.R. Williams, Metrologia 42, 71 (2005) R.S. Davis, Philos. Trans. R. Soc. Lond. A 363, 2249 (2005) P. Becker, H. Bettin, H.-U. Danzebrink, M. Gläser, U. Kuetgens, A. Nicolaus, D. Schiel, P. de Bièvre, S. Valkiers, P. Taylor, Metrologia 40, 271 (2003)

2 The Economic Implications of Moore’s Law G.D. Hutcheson

2.1 Introduction One hundred nanometers is a fundamental technology landmark. It is the demarcation point between microtechnology and nanotechnology. The semiconductor industry crossed it just after the second millennium had finished. In less than 50 years, it had come from transistors made in mils (one-thousandth of an inch or 25.4 microns); to integrated circuits which were popularized as microchips; and then as the third millennium dawned, nanochips. At this writing, nanochips are the largest single sector of nanotechnology. This, in spite of many a nanotechnology expert’s prediction that semiconductors would be dispatched to the dustbin of science – where tubes and core memory lie long dead. Classical nanotechnologists should not feel any disgrace, as pundits making bad predictions about the end of technology progression go back to the 1960s. Indeed, even Gordon Moore wondered as he wrote his classic paper in 1965 if his observation would hold into the 1970s. Semiconductors owe their amazing resilience to Moore’s law. To truly understand their greater impact, one must understand Moore’s law. Moore’s law is predicated on shrinking the critical features of the planar process: The smaller these features, the more bits that can be packed into a given area. The most critical feature size is the physical gate length; as shrinking it not only makes the transistor smaller, it makes it faster. But we are fast approaching the limits of what can be done by scaling. What changes are needed to keep the silicon miracle going, especially as we approach the nano era? This book examines these changes from a technical standpoint because barriers to Moore’s law have always been solved with new technology. However, these barriers are ultimately expressed economically and have important ramifications far beyond the industry itself. Moore’s law is not only an expression of a powerful engine for economic growth in the industry, but also for the economy as a whole. This chapter reviews Moore’s law and the economic implications that it poses. It shows how the continuation of Moore’s law provides

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a foundation for future economic growth and as such, sets the stage for a technical treatise on the nano era.

2.2 Moore’s Law: A Description Looking back thirty years after Gordon E. Moore first published his observations which would become known as Moore’s law, he mused “The definition of ‘Moore’s Law’ has come to refer to almost anything related to the semiconductor industry that when plotted on semi-log paper approximates a straight line” [1]. Indeed, this abuse of the meaning of Moore’s law has led to a great deal of confusion about what it exactly is. Simply put, Moore’s law [2] postulates that the level of chip complexity that can be manufactured for minimal cost is an exponential function that doubles in a period of time. So for any given period, the optimal component density would be: Ct = 2 · Ct−1 ,

(2.1)

where Ct = Component count in period t, Ct−1 = Component count in the prior period. This first part would have been of little economic import had Moore not also observed that the minimal cost of manufacturing a chip was decreasing at a rate that was nearly inversely proportional to the increase in the number of components. Thus, the other critical part of Moore’s law is that the cost of making any given integrated circuit at optimal transistor density levels is essentially constant in time. So the cost per component, or transistor, is cut roughly in half for each tick of Moore’s clock: Mt−1 , (2.2) 2 where Mt = Manufacturing cost per component in period t, Mt−1 = Manufacturing cost component in the prior period. These two functions have proven remarkably resilient over the years as can be seen in Fig. 2.1.1 The periodicity, or Moore’s clock cycle, was originally set forth as a doubling every year. In 1975, Moore gave a second paper on the subject. While the plot of data showed the doubling each year had been met, the integration growth for MOS logic was slowing to a doubling every year-and-a-half [3]. So in this paper he predicted that the rate of doubling would further slow to once every two years. He never updated this latter prediction. Between 1975 and 2006, the average rate between MPUs and DRAMs ran right at a doubling every two years. Mt =

2.3 The History of Moore’s Law Moore’s law is indelibly linked to the history of our industry and the economic benefits that it has provided over the years. Gordon Moore has tried repeatedly to dismiss 1 The forces behind the law were still strongly in effect when Gordon Moore retired in 2001,

leading him to quip to the author that “Moore’s law had outlived Moore’s career.”

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Fig. 2.1. Five decades of Moore’s law

the notion that it was law, but instead just an observation. It was actually Carver Mead who first called the relationship “Moore’s law.” Either way, the term became famous because Moore had proved amazingly perceptive about how technology would drive the industry and indeed the world. Moore’s observations about semiconductor technology are not without precedent. As early as 1887, Karl Marx, in predicting the coming importance of science and technology in the twentieth century, noted that for every question science answered, it created two new ones; and that the answers were generated at minimal cost in proportion to the productivity gains made [4]. His observation was one of the times, referring to mechanics for which the importance of the industrial age’s development had been largely questioned by economists up to that point [5] (much like the productivity gains of computers in the latter twentieth century are still debated today) [6]. More important was Marx’s observation that science and engineering had proved to be a reasonably predictable way of advancing productivity. Moreover, investments in science and engineering led to technology, which paid off in a way that grew economies, not just military might. Today, no one questions that science was at the heart of the industrial age, as it led to important inventions like the cotton gin, the steam engine, the internal combustion engine, and the fractional horsepower electric motor, to name a few. Nevertheless, it is the exponential growth of scientific “answers” that led to these, as well as to the invention of the transistor in 1947, and ultimately the integrated circuit in 1958, which led to

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Moore’s observation that became known as a law, and in turn launched the information revolution.2 The progress of science into the twentieth century would ultimately lead to the invention of the transistor, which is really where the story of the information revolution from the semiconductor perspective starts. Like all great inventions, it relied on the prior work of others. The solid-state amplifier was conceptualized by Julius Edgar Lilienfeld. He filed for a patent on October 8, 1926 and it was granted on January 28, 1930 (U.S. patent No. 1745175). While Lilienfeld didn’t use the term Field Effect Transistor (FET), Oskar Heil did in British Patent No. 439457, dated March 2, 1934. Heil became the first person to use the term semiconductor. While neither ever gained from these patents, these works established the basis of all modern day MOS technology, even though neither author was cognizant of the concept of an inversion layer [7]. That is, the technology was not there to build it. Soon after World War II, figuring out how to make a solid state switch would become the Holy Grail of research as vacuum tube and electromechanical relay-based switching networks and computers were already proving too unreliable. John Bardeen, Walter Brattain and William Shockley were in pursuit of trying to make workable solid state devices at Bell Labs in the late 1940s when Bardeen and Brattain invented the point-contact semiconductor amplifier (i.e., the point-contact transistor) on December 16, 1947 [7]. It was Brattain and Bardeen who discovered transistor action, not Shockley. Shockley’s contribution was to invent injection and the p–n junction transistor. Bardeen, Brattain and Shockley, nevertheless, all properly shared the 1956 Nobel Prize in physics. It was these efforts that would set the stage for the invention of the integrated circuit in 1958 and Moore’s observation seven years later. The story of the integrated circuit centers on the paths of two independent groups, one at Fairchild and the other at Texas Instruments (TI), who in their collision created the chain reaction that created the modern semiconductor industry. It is more than a story of technology. It is a story about the triumph of human endeavor and the victory of good over bad management. It begins with the “Traitorous Eight” leaving Shockley Transistor in 1957 to start Fairchild Semiconductor (the eight were Julius Blank, Victor Grinich, 2 These observations are often imitated as well. For example, Monsanto’s 1997 annual report proclaimed Monsanto’s Law, which is “the ability to identify and use genetic information is doubling every 12 to 24 months. This exponential growth in biological knowledge is transforming agriculture, nutrition, and health care in the emerging life sciences industry.” Its measure is the number of registered genetic base pairs, which grew from nil to almost 1.2 billion between 1982 and 1997. Magnetic memory has seen a similar parallel to Moore’s law as it shrinks the size of a magnetic pixel. Life sciences gains are a direct result of increased modeling capability of ever more powerful computers. Magnetic memory’s gains are a direct result of chip manufacturing methodologies being applied to this field. Both are a direct result of the benefits gained from Moore’s law. Indeed, Paul Allen of Microsoft fame has credited his observation that there would be a need for more increasingly powerful software as a direct result of learning about Moore’s law. He reasoned that this would be the outcome of ever more powerful chips and computers and then convinced Bill Gates there was a viable future in software – something no major systems maker ever believed until it was too late.

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Jean Hoerni, Eugene Kliener, Jay Last, Gordon Moore, Robert Noyce and Sheldon Roberts). They had been frustrated at Shockley because they wanted to move away from the four-layer device (thryristor) that had been developed at Bell Labs, and use lithography and diffusion to build silicon transistors with what would be called the mesa process. Fairchild was the first company to specialize exclusively in making its transistors out of silicon. Their expertise for pulling this off was a rare balance: Bob Noyce and Jay Last on litho and etch, Gordon Moore and Jean Hoerni on diffusion, Sheldon Roberts on silicon crystal growing and Gene Kliener on the financial side. The mesa process was named because cross-sectional views of the device revealed the steep sides and flat top of a mesa (it mounted the base on top of the collector). Debuted in 1958, it was the immediate rage throughout the industry, because transistors could be uniformly mass-produced for the first time. But the mesa process would not survive because its transistors were not reliable due to contamination problems. They were also costly due to their labor intensity, as the contacts were hand-painted. It was Jean Hoerni who – in seeking a solution to these problems – came up with the planar process, which diffused the base down into the collector. It was flat and it included an oxide passivation layer. So the interconnect between the base, emitter and collector could be made by evaporating aluminum (PVD) on oxide and etching it. This was a revolutionary step that, with the exception of the damascene process, is the basis for almost all semiconductor manufacturing today. It is so important that many consider Jean Hoerni the unknown soldier whose contributions were the real seed for the integrated circuit (IC). This is because the aluminum layer would make it easy to interconnect multiple transistors. The planar process was the basis for Fairchild’s early success and was considered so important that it was kept secret until 1960. Its process methodology was not revealed until after the IC had been invented. At the time, however, it was only viewed as an important improvement in manufacturing. The first work to actually interconnect transistors to build an IC was actually occurring halfway across the United States. Jack Kilby joined TI in May of 1958 and had to work through its mass vacation in July. A new employee, with no vacation time built-up, he was left alone to ruminate over his charge of working on microminiaturization. It was then that he came up with the idea of integrating transistors, capacitors and resistors onto a single substrate. It could have been a repeat of what happened at Shockley Semiconductor. Kilby’s bosses were skeptical. But instead of chasing him off, they encouraged him to prove his ideas. TI already had a mesa transistor on the market, which was made on germanium slices (TI used to call “die and wafers” “bar and slices”). Jack took one of these slices and cut it up into narrow bars (which may be why TI called chips “bars” versus the more commonly used word “die”). He then built an integrated phase-shift oscillator from one bar with a germanium mesa transistor on it and another with a distributed RC network. Both were bonded to a glass substrate and connected with a gold wire. He then built a flip-flop with multiple mesa transistors wire-bonded together, proving the methodology was universal in October of 1958. This was the first integrated circuit ever made. It was unveiled in March 1959 at the Institute of Radio Engineers show.

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Back at Fairchild, during January of 1959, Bob Noyce entered in his notebook a series of innocuous ideas about the possibility of integrating circuits using Hoerni’s planar process, by isolating the transistors in silicon with reversed biased p–n junctions, and wiring them together with the PVD-Litho-Etch process using an adherent layer of Al on the SiO2 . This was then put away until word of Jack Kilby’s invention rocked the world later in March 1959. While many derided Kilby’s work as a technology that would never yield, with designs that were fixed and difficult to change, Noyce sat up and took notice. Putting it all together, Noyce and his team at Fairchild would architect what would become the mainstream manufacturing process for fabricating integrated circuits on silicon wafers.3 Transistors, capacitors, and resistors could now be integrated onto a single substrate. The reasons why this method was so important would be codified in Moore’s 1965 paper. In 1964, Electronics Magazine asked Moore, then at Fairchild Semiconductor, to write about what trends he thought would important in the semiconductor industry over the next ten years for its 35th anniversary issue. He and Fairchild were at the forefront of what would be a revolution with silicon. However, when Moore sat down to write the paper that would become so famous for its law, ICs were relatively new – having been commercialized only a year or two earlier. Many designers didn’t see a use for them and worse, some still argued over whether transistors would replace tubes. A few even saw ICs as a threat: If the system could be integrated into an IC, who would need system designers? Indeed even Moore may have been skeptical early on. Robert Graham recalled that in 1960, when he was a senior Fairchild sales and marketing executive, Moore had told him, “Bob, do not oversell the future of integrated circuits. ICs will never be as cheap as the same function implemented using discrete components” [8]. In fact, Moore actually didn’t notice the trend until he was writing the paper [9]. Nevertheless, by 1964 Moore saw the growing complexity and lowered cost and this understanding of the process convinced him that ICs would come to dominate. Fairchild was trying to move the market from transistors to ICs. Moore was also convinced that ICs would play an important role and he was writing the paper that would convince the world. 3 Ironically, Kilby’s method for integrating circuits gets little credit for being what is now widely viewed as one of the most important paths into the future. In practice, his invention was what would be renamed as hybrid circuits, which would then be renamed Multi-Chip Modules (MCM), then Multi-Chip Packages (MCP), and now System In a Package (SIP). It is clear today that System-On-a-Chip (SOC) is limited by the constraints of process complexity and cost; and so Jack Kilby’s original integrated circuit is finally becoming a critical mainstream technology. Unfortunately, while he gets credit for the invention of the IC, few give him credit for inventing a method that had to wait 40 years to become critical in a new millennium. Most give both Jack Kilby and Bob Noyce credit as co-inventors of the IC because of these differences; they both came up with similar ideas independently and it was Jack Kilby that prodded Bob Noyce into action. TI would go on to become an industry icon. Fairchild’s early successes would turn to failure under bad management and suffer a palace revolt, similar to the one at Shockley, in 1967. It was called the Fairchild brain drain and resulted in the founding of 13 start-ups within a year. Noyce and Moore would leave to start-up Intel in 1968. But that’s another story.

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Titled “Cramming More Components into Integrated Circuits,” Moore’s paper was published by Electronics Magazine in its April 19, 1965 issue on page 114. Its subtitle was “With unit cost falling as the number of components per circuit rises, by 1975 economics may dictate squeezing as many as 65,000 components on a single chip of silicon.” This issue’s contents exemplify how so few really understood the importance of the IC. Ahead of it was the cover article by RCA’s legendary David Sarnoff who, facing retirement, reminisced about “Electronics’ first 35 years” with a look ahead. Behind this were articles titled “The Future of Electronics in 1930 – Predictions from Our First Issue” and “A Forward Look at Electronics – Looking Farther into the Future” (both written by the magazine’s authors). Then there appeared an article from Motorola, by Dan Noble titled “Wonderland for Consumers – New Electronic Products Will Make Life Easier.” All these papers were before Moore’s paper. Indeed, Moore’s paper would have been at the back of the magazine had it not been for what would prove to be mundane papers titled “Changing the Nature of Research for Space,” “Light on the Future of the Laser,” “More and Faster Communications” and “Computers to Run Electric Utility Plants.” At the time Electronics Magazine was the most respected publication covering the industry and it had assembled the best visionaries possible. Yet, with the exception of Moore’s paper, it was mostly classic forecasting “through the rear-view mirror.” His paper would be the only thing remembered from this issue. In fact, those who entered the industry in the 1990s wouldn’t even recognize the magazine as it is now defunct, not surviving the Moore’s law article it contained. Moore’s law paper proved so long-lasting because it was more than just a prediction. The paper provided the basis for understanding how and why ICs would transform the industry. Moore considered user benefits, technology trends, and the economics of manufacturing in his assessment. Thus he had described the basic business model for the semiconductor industry – a business model that lasted through the end of the millennium. From a user perspective, Moore’s major points in favor of ICs were that they had proven to be reliable, they lowered system costs and they often improved performance. He concluded, “Thus a foundation has been constructed for integrated electronics to pervade all of electronics.” This was one of the first times the word “pervade” was ever published with respect to semiconductors. During this time frame the word “pervade” was first used by both Moore and Patrick Haggerty of TI. Since then, the theme of increasing pervasiveness has been a feature of almost all semiconductor forecasts.4 From a manufacturing perspective, Moore’s major points in favor of ICs were that integration levels could be systematically increased based on continuous improvements in largely existing manufacturing technology. The number of circuits that could be integrated at the same yield had already been systematically increas4 Pervasiveness is another misused word. Many have used it during boom times to argue that the semiconductor industry would no longer be cyclical and thus, not have a downturn. While semiconductors have been increasingly pervasive since the dawn of the industry, this fact has not been a factor in alleviating the industry’s inherent cyclicality.

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ing for these reasons. He saw no reason to believe that integration levels of 65,000 components would not be achieved by 1975 and that the pace of a doubling each year would remain constant. He pointed to multilayer metalization and optical lithography as key to achieving these goals. Multilayer metalization meant that single transistors could be wired together to form ICs. But of far greater import was the mention of optical lithography. Prior to the invention of the planar process, the dominant device was known as a mesa transistor. It was made by hand painting black wax over the areas to be protected from etchant. While the tool was incredibly inexpensive (a 10-cent camel’s hair brush), the process was incredibly labor intensive [10].5 The introduction of optical lithography meant transistors could be made simultaneously by the thousands on a wafer. This dramatically lowered the cost of making transistors. This was done to the degree that, by the mid-1960s, packaging costs swamped the cost of making the transistor itself. From an economics perspective Moore recognized the business import of these manufacturing trends and wrote, “Reduced cost is one of the big attractions of integrated electronics, and the cost advantage continues to increase as the technology evolves toward the production of larger and larger circuit functions on a single semiconductor substrate. For simple circuits, the cost per component is nearly inversely proportional to the number of components, the result of the equivalent package containing more components.” As important as these concepts proved to be, it was still not clear that the arguments would stand the test of time. Package costs now overwhelmed silicon processing costs. These costs were not subject to Moore’s law and technical efforts were shifting to lowering them. Fairchild was reducing packaging costs, which were still highly labor intensive, by moving its assembly lines offshore. Texas Instruments and Motorola among others were developing and building automatic assembly equipment. Many, even those at Fairchild, were still struggling with how to make a profitable business out of ICs. While transistors could be integrated, designing and marketing circuits that customers could easily use proved more complicated. The industry had no design standards. Fairchild had developed circuits with Resistor–Transistor Logic (RTL), but customers were using Diode–Transistor Logic (DTL). Plus, Fairchild was undergoing major internal turmoil as political battles raged throughout the company. Many start-up companies were spinning out of it as senior executives left. The most famous of these spin-offs was Intel, for which its lead founders included no lesser than Robert Noyce and Gordon Moore. Lacking the packaging infrastructure of Fairchild and having the cream of its research capability, Intel’s strength was in its founders’ ability to build complex circuits and their deep understanding of Moore’s law. They leveraged this by focusing on memories, which Moore believed had huge market potential and could be more easily integrated – both in terms of putting large numbers of transistors on silicon and in integrating 5 See also [11, Chap. 3, pp. 53–56].

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them into customers’ designs.6 He was also convinced that the only way to compete effectively was by making the silicon more valuable than the package, offsetting the natural advantage in packaging that Fairchild, Motorola and TI had. The strategy worked. Intel became the memory IC market leader in the early 1970s. They had started with the SRAM (Static Random Access Memory) and soon invented the DRAM (Dynamic Random Access Memory), which proved to be very integrable and was much more cost effective than the ferrite core memories used by computer makers at the time. It was at this point that Moore’s law began to morph into the idea that the bits were doubling every year or two. Transistors were now old fashioned. Few argued the practicality of ICs. It was important to move on and use Moore’s law as a way to demonstrate the viability of the emerging memory market. At the time, there was more to the marketing of Moore’s law than most ever understood. The strategies taken would become a critical competitive advantage for Intel – enough of an advantage to keep it ahead of TI, who also focused on memories and had much more manufacturing infrastructure. Bob Graham, another Intel founder, recalled7 that there was a problem with Moore’s law: it was too fast. Its cycle called for a doubling every year, but systems designers needed more than a doubling to justify a new design. They typically fielded a new design every three-to-four years. Graham’s strategy to harness the power of Moore’s law was to match the chip design cycle to the system designers’. The difference between the nodes of Moore’s clock cycles and these memory nodes would lead to much confusion. But according to Graham, Intel used this confusion to keep competitors at bay when Intel’s early memory strategies were plotted. It was considered highly confidential and a big secret that the real generational nodes were based on a quadrupling, not a doubling. Moore’s law in his view was also a marketing head fake. Intel introduced each new generation of memories with a 4× increase in bits about every three years. Each of its generations was closely matched to customers’ design cycles. Other competitors fell behind because they followed the letter of Moore’s law. They tried to get ahead by introducing new chips with every 2× increase. But interim generations failed. They failed from the first 64-bit memory introduced by Intel to the 64 M-bit memory. This cycle, with every 4× increase in bits, was not broken until the 128 M-bit DRAM came to market three decades later in the early 2000s. Tax law and capital depreciation also played a critical role in determining the pacing of nodes. The United States’ MACRS (Modified Accelerated Cost Recovery Systems) tax code for capital depreciation specified that computers be fully depreciated over a six-year length of time. If systems makers had designed new systems every year, there would have been six generations of computers per depreciation cycle – clearly too many for customers. Customers would have over-bought and had to write-off equipment that was not fully depreciated, the annual market size would have been split into a sixth of its potential, or some compromise between the two 6 See also [11, pp. 181–185]. 7 Private conversations with the author.

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G.D. Hutcheson Table 2.1. Average months to double device complexity Year 1959–1965 1966–1975 1976–1985 1986–1995 1996–2005 1976–2005

Overall 12 17 22 32 27 24

MPU

DRAM

33 22 38 26 24

17 25 25 22 24

would have happened. Early on, systems makers paced designs so that at least one half of potential customers would replace their systems every two-to-three years. It is likely that the competitive reasons accounted for the more rapid cycling of system designs in the early 1960s. The computer market was still highly competitive then. It consolidated during the latter 1960s and IBM emerged as the dominant supplier. There are no technical reasons to explain why the node pacing slowed. But from a market perspective, the pace should have slowed naturally as IBM sought to leverage its dominance to extend the life of designs, hence having greater amortization of these costs and enhancing profitability. IBM was sued for monopolist trade practices and one of the claims was that it intentionally slowed technology. Whatever the reason, node pacing slowed to a rate of one design node every three years. Moore’s clock was roughly half that. In 1975, Moore wrote an update to the 1965 paper and revised his predictions. While technically his prediction of 65,000 components had come true, it was based on a 16 K-bit CCD memory – a technology well out of the mainstream. The largest memory in general use at the time – the 16 K-bit DRAM, which contained less than half this amount – would not be in production until 1976. Between 1965 and 1975 the pace had actually slowed to a doubling every 17 months or roughly every year-anda-half. Later, Moore’s law was widely quoted by others as being every 18 months. But, despite being widely referenced as the source, this is a periodicity that Moore never gave. The 1975 paper actually predicted the periodicity would be a doubling every two years [3]. This would turn out to be extremely accurate, though seldom quoted with any accuracy. Contrary to what many have thought, the finer points of the accuracy of Moore’s law never really mattered. The real import of Moore’s law was that it had proved a predictable business model. It gave confidence in the industry’s future because it was predictable. One could plan for it and invest in it on the basis that the integration scale would always rise in a year or two, obsolescing the electronics that were out there and creating new demand because the unobtainable and confusing would become affordable and easy to use. This then fed back to reinforce it, as engineers planned for it and designed more feature-rich products or products that were easier to use. As Moore later put it, Moore’s law “had become a self-fulfilling prophecy [9]”. But as a result, heavy international competition and technical issues would loom in the future.

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It was at about this time that Japan seized on Moore’s law as a planning mechanism. Without it, the industry appeared to go in random directions. But Moore’s law made it easy to plan and it had been clearly proven by 1975. The DRAM explosion was already in place at TI, AMD, IBM, Intel, and Mostek. Moore’s law made it all understandable. Now believers in Moore’s law, they saw that since memory demand and device type were very predictable it would play to their strengths. Moreover, cost of manufacturing was critical to success – one of their key strategic strengths. Moore’s law was the basis of the arguments that prompted them to start their government-funded effort called the VLSI program in 1976, for which the goal was to build a working 64K-bit DRAM. They believed that if the VLSI program could do this, their semiconductor industry could lever off the results to build their own. Japan was already successful in 4 K-bit DRAMs and their potential with 16 K-bit DRAMs looked promising. One of the keys to their success was that they implemented multiple development teams. Each team worked on the same generation, walking it from research, through development, and into manufacturing. In contrast, the west had highly stratified walls between these three areas. Research departments threw their results over the wall to development, and so forth into manufacturing. Often, manufacturing used few of these efforts because they were seldom compatible with manufacturing. Instead they built designs coming directly from marketing because they knew they would sell. Japan got the edge because they could get new designs to manufacturing faster and their cost of manufacturing was fundamentally lower. They had lower labor rates and their line workers typically stayed with a company for several times longer. This combined with the Japanese penchant for detail. TI had a facility in Japan and this facility consistently yielded higher than its American facilities for these reasons.8 The Japanese also had newer equipment, having invested heavily in the late 1970s. Capital was tough to get in the late 1970s for American chipmakers. They had cut their investments to low levels, which would ultimately give Japan another source of yield advantage. But the real shocker came in 1980, when Hewlett-Packard (HP) published an internal study comparing quality between American- and Japanese-made DRAMs. It showed Japan to have higher quality DRAMs. American chipmakers cried foul – that this was tested-in quality and that Japanese suppliers sent HP more thoroughly tested parts. Indeed, independent studies did later show that Japanese-made DRAM’s obtained on the open market were of no higher quality than American ones. However, it was too late to change the perception that HP’s announcement had created (a perception that remains to this day). Whether or not the quality was tested-in, the one clear advantage the Japanese had was yield. It was typically 10–15% higher than equivalent American fabs and this gave the Japanese a fundamental cost advantage. When the downturn hit in 1981, these yield differences allowed Japanese companies to undercut American companies on 16-Kbit DRAMs. This, combined with the downturn, caused American producers to make further cuts in capital investment, and put them further behind. At 8 Conversations with Howard Moss, a Board Member of Texas Instruments at the time, 1985.

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the time, the Chairman of NEC noted that they had no fab older than five years. The average American fab was 8 years old. So by the early 1980s, Japan came to dominate 64-Kbit memories. By 1985, America’s giants were bleeding heavily. Intel was among the worst when it came to manufacturing memories. It was forced out of memories. The technical issues with the 64-Kbit DRAM proved to be enormous. The most commonly used lithography tool of the day, the projection aligner, would not make it to this generation because it lacked the overlay alignment capability. Something new had to be developed and the industry was not ready. The transition to stepping aligners proved much more traumatic than anyone expected. Steppers had the potential for very high yields. But unless the reticle was perfect and had no particles, yield would be zero because the stepper would repeat these defects. The result was a three-year hiatus in Moore’s law. 64-Kbit DRAMs did not enter volume production until 1982 – a full three years after they should have arrived – taking a full six years to pass from the 16-Kbit node. Another transition occurred in the early 1980s that favored Intel. NMOS began to run out of steam and couldn’t scale well below one micron. Some even predicted that we had hit Moore’s wall. But the industry escaped this by transitioning to CMOS. One of the benefits of CMOS was that performance also scaled easily with shrinks. An engineer in Intel’s research organization observed this and recognized its importance to microprocessors. Moreover, having exited memories it was important that Intel not lose the brand value of Moore’s law it had, having its discoverer as chairman of the company. So marketing morphed Moore’s law a second time. It had started as the number of transistors doubling, then the number of bits, and now it was speed, or more comprehensively, performance. This new form would serve Intel and the industry well. In the early 1990s, the pace of integration increased again. There were several factors driving this change. It could be argued that the manufacturing challenges of the early 1980s had been overcome. Yet there was significant fear that new hurdles looming in the near future would be insurmountable. America’s semiconductor industry had just instituted the roadmap process for planning and coordinating semiconductor development. As it turned out, this focused pre-competitive research and development like it had never been before. Instead of hundreds of companies duplicating efforts, it allowed them to start from a common understanding. The result was an increased pace of technology development. At the same time, efforts to reinvigorate competitiveness led companies to adopt time-to-market measures of effectiveness. This naturally accelerated the pace of development. Also, the shift from mainframe and minicomputers to personal computers had dramatically altered the competitive landscape in the 1980s. IBM had quickly come to dominate the PC market in the early 1980s. Unlike all earlier IBM computers, the PC had been designed with an open architecture. Their dominance might never have been challenged. However on August 2, 1985, the IBM senior executives who ran and had developed its PC business violated a major corporate rule and boarded Delta Airlines flight 191 to Dallas, Texas. The flight encountered wind-shear and crashed on landing. IBM’s understanding of how

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the market was evolving as well as its leadership capability in the still-emerging PC market perished. Unlike all earlier IBM computers, the PC had been designed with an open architecture, which meant it could be easily cloned. Outside of this small group, IBM really didn’t understand how to respond to the hoards of clone makers who had entered the market. Applied to pricing and self-obsolescence, the clone hoard’s slash-and-burn strategies made IBM’s defenses about as useful as France’s Maginot line in World War II. As they lost their leadership, the pace of technical change accelerated again to limits set primarily by technical developments. At the 1995 Semiconductor Industry Association (SIA) forecast dinner, Gordon Moore gave a retrospective on 30 years of Moore’s law. He claimed to be more surprised than anyone that the pace of integration had kept up for so long. He had given up on trying to predict its end, but commented that it was an exponential and all exponentials had to end. While it did not stop the standing ovation he received, he concluded that “This can’t go on indefinitely – because by 2050. . . we’re everything.”

2.4 The Microeconomics of Moore’s Law The essential economic statement of Moore’s law is that the evolution of technology brings more components and thus greater functionality for the same cost. This cost reduction is largely responsible for the exponential growth in transistor production over the years. Lower cost of production has led to an amazing ability to not only produce transistors on a massive scale, but to consume them as well. Each year’s new production alone amounts to roughly 40% of the total transistors ever produced in every year before it. It has crossed 12 orders of magnitude since the industry’s inception. By comparison, auto production did not cross a single order of magnitude over this period. The other amazing aspect of this is that anomalies such as the millennial boom have no effect on production. In any given year since the industry’s birth, the production of transistors has averaged 41% of the cumulative total ever produced up until then. So what makes Moore’s law work? The law itself only describes two variables in the equation: transistor count and cost. Behind these are the fundamental technological underpinnings that drive these variables and make Moore’s law work. There are three primary technical factors that make Moore’s law possible: reductions in feature size, increased yield, and increased packing density. The first two are largely driven by improvements in manufacturing and the latter largely by improvements in design methodology. Design methodology changes have been significant over the years. They have come as both continuous and step function improvements. The earliest step function improvements were the reduction in transistor counts to store memories. The industry started with 6-transistor memories. In the late 1960s, designers quickly figured how to reduce this to four, then two, and, finally, the 1-transistor/1-capacitor DRAM cell, developed by R.H. Dennard [12]. While this did not affect Moore’s law as measured in transistors, it did when measured in bits, because a 4-Kbit memory (with a 6-T

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Fig. 2.2. Worldwide transistor production (all, including foundry, merchant, and captive producers)

cell) needed 24-K transistors and could now be made with only 4-K transistors with a 1 T/ 1 capacitor cell. This was an enormous advance. Cost-per-bit plummeted and it further added to the mythical proportions of Moore’s law, as customers saw little real difference between transistors and bits. What they were most interested in was reductions in cost-per-function and designers had delivered. There were less wellknown additions as well. The development of Computer-Aided Design (CAD) in the early 1980s was a significant turning point. Now with Electronic Design Aids (EDA), CAD’s first contribution was to prevent the ending of Moore’s law. As the industry progressed from MSI to LSI levels of integration, the number of transistors to be wired together was becoming too large for humans to handle. Laying out the circuit diagram and cutting the rubylith9 for wiring 10,000 transistors (with three connections each) together, with 3-connections each, by hand had to have been a daunting task. The 64-Kbit DRAM loomed large in this picture as the decade turned. With just over 100,000 K transistors, it would be the first commercial VLSI grade 9 In those days, masks were made by drawing the circuit out on a large piece of paper that

sometimes covered the floor of a large room. Then a laminated piece of Mylar called rubylith was used to make the initial mask pattern. Rubylith was made of two Mylar films, one clear and one red. A razor-edged knife was used to cut strips of the red Mylar away. Initially this was done by hand. One had to be careful not to cut the clear Mylar underneath so the red Mylar could be pulled away, leaving the final mask pattern. This pattern was then reduced to circuit dimensions to make a mask master.

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Table 2.2. Integration scale measures used in the 1970s SSI MSI LSI VLSI

Small Scale Integration Medium Scale Integration Large Scale Integration Very Large Scale Integration

<100 Transistors 101–1,000 Transistors 1,001–10,000 Transistors >100,000 Transistors

chip produced in volume – and it was a point of hot competition. So being able to automate this process would be a great leap forward. The next step for design was to improve the layout capability of these tools. This improved the packing density. Early layout tools were fast, but humans could lay out a circuit manually in 20–30% of the area. Today, no one would manually lay out an entire circuit with millions of transistors. Even today, EDA tools do not offer the most efficient packing density. Designers who want the smallest die will “handcraft” portions of a circuit. This is still commonly done when a market is large and the die-size reduction can justify the cost of handcrafting. Performance improvements are another way that design has directly affected Moore’s law. It is particularly important to the third version of Moore’s law, which measures the gain in circuit performance over time. Scaling theory states that transistor switching speed increases at a rate that is inversely proportional to the reduction in physical gate length. However, a designer can improve on this by using the switching of transistors more efficiently. These transistors switch with the clock of the circuit. Early processor architecture required several clock cycles per instruction. So a 1-GHz clock might only perform at a rate of 300 Millions of Instructions Per Second (MIPS). Using techniques like parallel processing, pipelining, scalar processing, and fractional clocks, designers have systematically improved this so that three-to-five instructions per clock cycle can be achieved. Thus, a processor with a 1-GHz clock can exhibit run rates of 3,000-to-5,000 MIPS. Considering 1-MIP was considered state-of-the-art for a circa-1980 mainframe processor, subsequent architectural gains have been quite significant. Design tools are having further impacts today; one is their ability to improve testing. Without these tools test costs would explode or worse, the circuits would be untestable, making further gains in integration scale pointless. Another impact is the ability to automatically lay out the patterns needed to make reticles with optical proximity correction and phase-shifting. This substantially reduces feature sizes. But, it is important to realize that none of these gains would have been possible without ever more powerful cost-effective computers. All of these benefits were made possible by Moore’s law. Hence, instead of running down, Moore’s law is a self-fulfilling prophecy that runs up. Indeed, many of the manufacturing improvements since the 1980s have come only because Moore’s law had made computing power so cheap that it could be distributed throughout the factory and in the tools, be used to design the tools, and even perform the engineering and economic analysis to make more efficient decisions.

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Fig. 2.3. Five decades of critical dimension shrinks (in nanometers)

Reductions in feature sizes have made the largest contributions by far, accounting for roughly half of the gains since 1976. Feature sizes are reduced by improvements in lithography methods. These enable smaller critical dimensions (CDs, which are also known as Minimum Feature Sizes or MFSs) to be manufactured. If the dimensions can be made smaller, then transistors can be made smaller and hence more can be packed into a given area. This is so important that Moore’s first paper relied entirely on it to explain the process. Improvements in lithography have been the most significant factor responsible for these gains. These gains have come from new exposure tools; resist processing tools and materials; and etch tools. The greatest change in etch tools was the transition from wet to dry etching. In etching, most of the older technology is still used today. Wet chemistries used for both etching and cleaning are the most prominent of these. Improvements in resist processing tools and materials have generally been incremental. Resist processing tools have remained largely unchanged from a physical perspective since they became automated. The changes have mostly been in incremental details changed to improve uniformity and thickness control. Resist chemistries have changed dramatically, but these changes are easy to overlook. Moreover etch and resist areas have relatively small effects on cost. Exposure tools have gone through multiple generations that followed the CD reductions. At the same time they have been the most costly tools and so generally garner the most attention when it comes to Moore’s law. Moreover, without improvements in the exposure tool, improvements elsewhere would not have been needed. Exposure tools were not always the most costly tools in the factory. The camel’s hair brush, first used in 1957 to paint on hot wax for the mesa transistors, cost little more than 10 cents. But since that time prices have escalated rapidly, increasing roughly an order of magnitude every decade-and-a-half. By 1974, Perkin–Elmer’s newly introduced projection aligner cost well over $100,000. In 1990, a state-of-the-

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Table 2.3. Evolution of lithography technology used to manufacture semiconductors Year first used in manufacturing

CD (microns)

Lithography technology

Etch

1957 1958 1959 1964 1972 1974 1982 1984 1988 1990 1997 2003

254.000 127.000 76.200 16.000 8.000 5.000 2.000 1.500 1.000 0.800 0.250 0.100

Camel’s hair brush, hand painting Silk screen printer Contact printer W/emulsion plates Contact printer W/chrome plates Proximity aligner Projection aligner g-line (436 nm) stepper

Wet etching

Barrel plasma Planar plasma Reactive ion etching High density plasma

i-line (365 nm) stepper 248 nm scanner 193 nm scanner

Fig. 2.4. History of average cost to build & equip a wafer fab

art i-line stepping aligner cost just over $1 million. When this was first written in 2002, 193-nm ArF excimer laser scanning aligners were about to enter manufacturing and they cost a shocking $10 million each. As of this writing in late 2006, they cost upwards of $50 million. Over the decades, these cost increases have been consistently pointed to as a threat to the continuance of Moore’s law. Yet the industry has never hesitated to

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adopt these new technologies. It is a testimony to the power of this law that these costs have been absorbed with little effect. Lithography tools have become more productive to offset these increases. Moreover, they are only part of the rising cost picture. The increase in the cost of semiconductor factories had been a recurring theme over the years. In fact it was first noted in 1987 that there was a link between Moore’s law and wafer fab costs [13]. Between 1977 and 1987, wafer fab costs had increased at a rate of 1.7× for every doubling of transistors. In the 1980s, the cost of factories was offset primarily by yield increases. So rising tool costs were offset by lower die costs. However, this relationship stalled in the 1990s, when the rise in tool prices began to be offset by increases in productivity. So as effective throughputs rose, the unit volumes of tools in a fab needed to produce the same number of wafers declined. This did change somewhat with the introduction of 300 mm wafers. However, the doubling in fab costs, shown above starting in 2004, is due to the fact that the typical output of a fab in wafers doubled. When normalized for output, fab costs have been constant since the 1990s and really have ceased to be an issue. In any case, Moore’s law governs the real limit to how fast costs can grow. According to the original paper given in 1965, the minimal cost of manufacturing a chip should decrease at a rate nearly inversely proportional to the increase in the number of components. So the cost per component, or transistor, should be cut roughly in half for each tick of Moore’s clock (see (2.1) and (2.2)). However, since this paper was first given, it has generally been believed that industry growth will not be affected if the cost per function drops by at least 30% for every doubling of transistors. This 30% drop would allow the manufacturing cost per unit area of silicon to rise by 40% per node of Moore’s law (or by twice the cost-per-function reduction ratio requirement) (Appendix A). This includes everything from the fab cost to materials and labor. However it does not take yield or wafer size into account. Thus if cost per function needs to drop by 30% with each node, wafer costs can also theoretically increase by 40%, assuming no yield gains (see Appendix A for proof). Yield is a function of die size and so is directly dependent on component counts and CD reductions. There are many equations for calculating yield, the most basic of which is the classic Poisson probability exponential function: Y = exp −(ADN ), where A = die area, D = defect density per mask layer, N = number of masks. Note that this equation also accounts for increased process complexity as component counts rise. It would seem that this effect would be the most significant costreducing factor. In the early days of the industry, it was. In the 1970s, yield typically started at 15% when a device was introduced and peaked at 40% as the device matured. Gains of two-to-three times were typical over the life of a chip and gains of four-to-five times were not uncommon for devices that had long lives. Improvement in manufacturing methods increased these gains dramatically during the 1980s and 1990s. This was primarily due to better equipment and cleanroom technology. For example, the switch to VLSI equipment technology such as steppers and plasma

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etchers caused initial yields for the 64-Kbit DRAM to come in at 40% in 1982. It matured at 75% three years later. Today, devices typically enter production at 80%; rise to 90% within six months; and can achieve close to 100% at maturity. But at best the gain is only a quarter of initial yields. Wafer size has been another cost-reducing factor used over the yields. Larger wafers have typically cost only 30% more to process and yet have had an area increase of 50-to-80%. The move to 300 mm wafers from 200 mm will yield an area increase of 125%! Larger wafers have always brought a yield bonus because of their larger “sweet spot” – yielding a relatively larger number of good chips in the inner regions of the wafer – and the fact that they require a new generation of higher-performing equipment. Like the sweet spot of a tennis racket, wafers tend to have the lowest defect density at their centers and highest at their edges where they are handled most. In addition, process chamber uniformity tends to suffer the most at the edges of the wafer. There are also gains in manufacturing efficiency that occur over time. The result is a continued decrease in manufacturing costs per die. However, the continuation of Moore’s law via reduction in CDs, increased yields, larger wafer sizes, and manufacturing improvements has taken its toll in other areas. Costs have risen significantly over time as seen in the rise of wafer fab costs. Moreover, the CD reductions have caused a need for increasing levels of technical sophistication and the resultant costs. For example, the camel’s hair brush used for lithography in the 1950s cost only 10 cents; early contact aligners cost $3,000–5,000 in the 1960 and $10,000 by the 1970s; a projection aligner in the late 1970s cost $250,000; and the first steppers cost $500,000 in the early 1980s. By 2000, a 193-nm (using an ArF excimer laser) stepper cost $10 million and the latest tools can cost upward of $50 million. That is an increase of more than eight orders of magnitude over five decades. Moreover, the cost increases are prevalent throughout the fab. Increased speeds have forced a transition from aluminum to copper wiring. Also, silicon-dioxide insulation no longer works well when millions of transistors are switching at 2 GHz, necessitating a switch to interlevel dielectrics with lower permittivity. At the gate level, silicon-dioxide will no longer be useful as a gate dielectric. Scaling has meant that fewer than ten atomic thicknesses will be used and it will not be long before they fail to work well. The solution is to replace them with high-k dielectrics so that physical thicknesses can be increased, even as the electrical thickness decreases. These new materials are also causing costs to escalate. An evaporator, which could be bought for a few thousand dollars in the early 1970s, now costs $4–5 million. Even diffusion furnaces cost $1 million per tube. As costs have risen, so has risk. There has been a tendency to over-spec requirements to ensure a wide safety margin. This has added to cost escalation. At some point the effect of these technologies translating into high costs will cause Moore’s law to cease. As Gordon Moore has put it, “I’ve learned to live with the term. But it’s really not a law; it’s a prediction. No exponential runs forever. The key has always been our ability to shrink dimensions and we will soon reach atomic dimensions, which are an absolute limit.” But the question is not if,

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it’s when will Moore’s wall appear? “Who knows? I used to argue that we would never get the gate oxide thickness below 1000 angstroms and then later 100. Now we’re below 10 and we’ve demonstrated 30-nm gate lengths. We can build them in the 1000’s. But the real difficulty will be in figuring out how to uniformly build tens of millions of these transistors and wire them together in one chip” [14]. In fact, we routinely build them today in cutting-edge manufacturing. In the end, it is more likely that economic barriers will present themselves before technical roadblocks stop progress [15].

2.5 The Macroeconomics of Moore’s Law Moore’s law was more than a forecast of an industry’s ability to improve, it was a statement of the ability for semiconductor technology to contribute to economic growth and even the improvement of mankind in general. It has a far richer history than the development of semiconductors, which to some extent explains why Moore’s law was so readily accepted. This history also explains why there has been an insatiable demand for more powerful computers no matter what people have thought to the contrary. The quest to store, retrieve, and process information is one task that makes humans different from other animals. The matriarch in a herd of elephants may be somewhat similar to the person in early tribes who memorized historical events by song. But no known animal uses tools to store, retrieve, and process information. Moreover the social and technological progress of the human race can be directly traced to this attribute. More recent writers have pointed to this as a significant driving force in the emergence of western Europe as the dominant global force in the last millennium [16]. Man’s earliest attempts to store, retrieve, and process information date back to prehistoric times when humans first carved images in stone walls. Then in ancient times, Sumerian clay tokens developed as a way to track purchases and assets. By 3000 B.C. this early accounting tool had developed into the first complete system of writing on clay tablets. Ironically, these were the first silicon-based storage technologies and would be abandoned by 2000 B.C. when the Egyptians developed papyrus-based writing materials. It would take almost four millennia before silicon would stage a comeback as the base material, with the main addition being the ability to process stored information. In 105 A.D. a Chinese court official named Ts’ai Lun invented wood-based paper. But it wasn’t until Johann Gutenberg invented the movable-type printing press around 1436 that books could be reproduced cost effectively in volume. The first large book was the Gutenberg Bible, published in 1456. Something akin to Moore’s law occurred, as Gutenberg went from printing single pages to entire books in 20 years. At the same time, resolution also improved, allowing finer type as well as image storage. Yet, this was primarily a storage mechanism. It would take at least another 400 years before retrieval would be an issue. In 1876, Melvil Dewey published his classification system that enabled libraries to store and retrieve all the books that were being made by that time. Alan Turing’s “Turing Ma-

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Fig. 2.5. Average price and cost per transistor for all semiconductors (in nanodollars)

chine,” first described in 1936, was the step that would make the transformation from books to computers. So Moore’s law can be seen to have a social significance that reaches back more than five millennia. The economic value of Moore’s law is also understated, because it has been a powerful deflationary force in the world’s macro-economy. Inflation is a measure of price changes without any qualitative change. So if price per function is declining, it is deflationary. Interestingly, this effect has never been accounted for in the national accounts that measure inflation adjusted gross domestic product (GDP). The main reason is that if it were, it would overwhelm all other economic activity. It would also cause productivity to soar far beyond even the most optimistic beliefs. This is easy to show, because we know how many devices have been manufactured over the years and what revenues have been derived from their sales. Probably the best set of data to use for analyzing the economic impact of Moore’s law is simply price and cost per transistor. It is exceptionally good because it can easily be translated into a universal measure of value to a user: transistors. Transistors are a good measure because in economic terms they translate directly into system functionality. The more transistors, the greater the functionality of the electronic products consumers can buy. This data is shown in Fig. 2.5. This data includes both merchant and captive production, so it is a complete measure of industry production. The constancy of this phenomenon is so stunning that even Gordon Moore has questioned its viability. The implications of this data are even more stunning: Since a transistor’s price in 1954 was 64 million times more than it is as of this writing, the economic value the industry has brought to the world is unimaginable. If we take 2006’s market and adjust for inflation, the value of to-

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day’s integrated circuit production would be 13 peta-dollars – or $13,000 trillion. That is far larger than Gross World Product, which measures the value of output of all the world’s economies. Moreover, that doesn’t include the value of all semiconductors! So it is hard to understate the long-term economic impact of the semiconductor industry.

2.6 Moore’s Law Meets Moore’s Wall: What Is Likely to Happen Moore’s law meets Moore’s wall and then the show stops, or the contrary belief that there will be unending prosperity in the twenty-first century buoyed by Moore’s law, have been recurring themes in the media and technical community since the mid1970s. The pessimists are often led by conservative scientists who have the laws of physics to stand behind. The optimists are usually led by those who cling to “facts” generated by linear extrapolation. The problem with the optimists is that the issues that loom are not easily amenable to measurement by conventional analysis. Eventually real barriers emerge to limit growth with any technology. Moreover, as Moore himself has often quipped, “No exponential goes on forever.” But so far, the optimists have been right. The problem with the pessimists is that they typically rely too much on known facts and do not allow for invention. They don’t fully account for what they don’t know, leaving out the “what they don’t know” pieces when assembling the information puzzle. Yet it is the scientific community itself that expands the bounds of knowledge and extends Moore’s law beyond what was thought possible. History is replete with many really good scientists and engineers who have come up with new things to constantly expand the boundaries of our knowledge, and as noted above, this is not likely to stop. When anyone asks me about Moore’s wall, my first response is “Moore’s wall is in Santa Clara, just outside Intel’s Robert Noyce building. If you look closely, you will find the engraved names of people who made career-limiting predictions for the end of Moore’s law.” This has certainly been the case for those who have predicted the coming of Moore’s wall in a five-or-ten-year span over the years. Yet, Moore himself said in 1995 that the wall should be finished and in place somewhere around 2040, when he poignantly pointed out that otherwise, “we’ll be everything” if things continue at historical growth rates. Herein lies the real dilemma. If our industry continues to grow unbounded, it really will become as large as the global economy in the first half of the twenty-first century. This leads to the historical view that as this occurs our industry’s growth will become bounded by macroeconomic growth. However, if you look at history, it dispels this idea. At the beginning of this millennium rapid advances in agricultural techniques did not slow economic growth. Instead, they buoyed it as they freed-up human resources to work on other things, which in turn kicked off the High Middle Ages. Ultimately, this made possible the industrial age in the latter part of the millennium. As industry grew to be a larger part of the economy it did not slow to the 1% annual economic growth of agricultural economies. While it did slow, it also pushed economic growth up to an average of about 3%. Mechanized transportation

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allowed centralized manufacturing, so factories could achieve greater economies of scale. This combined with the mechanization of the factory and greatly improved productivity; thus allowing greater non-inflationary growth levels. Since the latter half of the 1990s, the United States has been able to achieve regular non-inflationary growth of 4–5%. It is non-inflationary because of productivity gains. These gains are made possible by information technology. Another factor driving the non-inflationary growth potential of the economy is that information technology tends to be energy saving as well. One of the real limits to the agricultural age was the fact that the primary fuel was wood. Entire forests were decimated in the Middle East and then Greece and Italy. The industrial age was prompted with the discovery of fossil fuels. This stopped deforestation to a great degree, but from an economic perspective, it also allowed for greater growth potential. Fossil fuels were easier to transport and use, so they too increased productivity. This, combined with the ability to transport materials to centralized manufacturing locations and then back out with trains, led to massive improvements in productivity. The information age takes the next step and relies on electricity. More important, it replaces the need to transport people, materials, and products with information. For example, video teleconferencing allows people to meet without traveling great distances. The voice and image information at both ends is digitized into information packets and sent around the world so that people can communicate without being physically near. At the same time, products can be designed in different places around the world and the information can be sent so products can be produced either in low-cost areas or, where transportation costs are high, locally. For example, for semiconductors being designed in the United States in close cooperation with a customer in Europe it is now a daily event to have the designs sent over the Internet to Texas for reticles to be made, to California for test programs, then to Taiwan to convert wafers into ICs, then to Korea for packaging, and finally the product is shipped to the customer in Europe. In the case of beer, transporting liquids is far too expensive. So a company in Europe can license its process to brewers in the United States and Japan, where they are manufactured locally. Using the Internet, the original brewer can monitor production and quality with little need to leave the home factory. The productivity effect seen in the transition from the agricultural to the industrial age is really happening as we move into the information age. It can be argued that macroeconomic growth could rise to as high as 8% while creating a similar growth cap for our industry. What happens when this occurs? It is inevitable that the semiconductor industry’s growth will slow from the 15–20% range it has averaged over its history in the last half of the twentieth century. The barriers that will limit it will be economic not technical, as Moore’s law is a statement of powerful economic forces [15]. Technology barriers first show up as rising costs that go beyond the bounds of economic sense. Transportation speed limits could exceed the speed of sound. But economic limits make private jet ownership unattainable for all but a very few. Economic limits make the automobile the most commonly used vehicle in major industrialized countries and the bicycle in others. But even here, the economic limits of building infrastructure limit average speed to less than 20 MPH in

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Fig. 2.6. Ford motor company’s equivalent to Moore’s law (the early years of the auto industry)

industrial countries (which is one reason why the bicycle has become such a popular alternative). If we look to the auto industry for guidance, similar declines in cost during its early years can be found. At the turn of the century, cars were luxury items, which typically sold for $20,000. They were the main frames of their day, and only the ultra-rich could afford them. Henry Ford revolutionized the auto industry with the invention of the assembly line. Ford’s efforts resulted in a steady reduction in costs, quickly bringing the cost of manufacturing a car to under $1000. But even Ford’s ability to reduce costs had bottomed out by 1918, when the average hit a low of $205 (see Fig. 2.6, which has not been adjusted for inflation). While these efforts pale in comparison to gains made in semiconductors, the lesson to be learned is that cost gains made on pushing down one technical river of thought will eventually lead to a bottom, after which costs rise. Science and engineering can only push limits to the boundaries of the laws of physics. Costs begin to escalate as this is done because the easy problems are solved and making the next advance is more difficult. At some point, little gains can be made by taking the next step, but the cost is astronomical. In the case of automobiles, the gains were made by the development and improvement of assembly line technology. In the case of semiconductors it has largely been lithography where the gains were made. These are not “economies of scale” as taught in most economics classes, where increased scale drives cost down to a minimum – after which, costs rise. Instead, technology is driving cost. These are economies of technology and are some of the

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most important underlying factors that make Moore’s law possible and will ultimately result in its demise when gains can no longer be made. Similar things are happening in semiconductors. Fab equipment prices have risen steadily at annual rates above 10%. This was fine as long as yields rose, giving added economic boost to the cost of steadily shrinking transistors to stay on Moore’s curve. But yields cannot go up much further, so gains will have to come from productivity improvements. It is important to note that as these economic barriers are hit, it does not mean the end of the semiconductor industry. The industry has lived with Moore’s law so long that it is almost of matter of faith, as exemplified in the term “show stopper.” The term has been used extensively to highlight the importance of potential limits seen in the industry’s “road mapping” of future technologies. Yet it is unlikely that the show will stop when the show stoppers are finally encountered. Just think of the alternatives. Moreover, the auto industry has been quite healthy in the eight decades since it hit its show stoppers. People did not go back to horses as a means of regular transport. As the gains from automation petered out, auto manufacturers shifted their emphasis from low-cost one-size-fits-all vehicles to many varieties – each with distinct levels of product differentiation. The other hallmarks of the industrial age trains and planes also found ways to go on after they hit technical and economic limits. For this to happen in semiconductors, it means manufacturing will have to be more flexible and design will continue to become more important.

2.7 Conclusion Moore’s law has had an amazing run as well as an unmeasured economic impact. While it is virtually certain that we will face its end sometime in this century, it is extremely important that we extend its life as long as possible. However well these barriers may be ultimately expressed economically, barriers to Moore’s law have always been overcome with new technology. It may take every ounce of creativity from the engineers and scientists who populate this industry, but they have always been up to the task. Moore’s law is predicated on shrinking critical features. Since the 1970s, it has always seemed that we are fast approaching the limits of what can be done, only to find someone had come up with a new idea to get around the barrier. The “red brick wall” has proved more imaginary that real – it’s real effect having been to spur innovation. So what advice would Gordon give us? I had the chance to ask him several years ago on the day he entered retirement.10 One thing he wanted to point out was that he never liked the term Moore’s law: “I’ve learned to live with the term. But it’s really not a law; it’s a prediction. No exponential runs forever. The key has always been our ability to shrink dimensions and we will soon reach atomic dimensions, which are an absolute limit.” But the question is not if, it’s when will Moore’s wall appear? “Who knows? I used to argue that we would never get the gate oxide thickness below 10 Personal conversations with Dr. Gordon Moore and the author, May 24, 2001.

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1000 angstroms and then later 100. Now we’re below 10 and we’ve demonstrated 30nm gate lengths. We can build them in the 1000’s. But the real difficulty will be in figuring out how to uniformly build ten’s of millions of these transistors and wire them together in one chip.” The key is to keep trying. Keep trying we did: As of this writing 30-nm gates are just making it to production. Gordon felt that any solution must champion manufacturing because “there is no value in developing something that cannot be built in volume. Back at Fairchild the problem was always in getting something from research into manufacturing. So at Intel we merged the two together.” He advised, “Always look for the technical advantage (in cost). I knew we could continue to shrink dimensions for many years, which would double complexity for the same cost. All we had to do was find a product that had the volume to drive our business. In the early days that was memories. We knew it was time to get out of memories when this advantage was lost. The argument at the time was that you had to be in memories because they were the technology driver. But we saw that DRAMs were going off in a different technical direction because problems in bit storage meant they had to develop all these difficult capacitor structures.” He also pointed to the need to avoid dependency on specific products. “I’ve never been good at forecasting. I’ve been lucky to be in the right place at the right time and know enough to be able to take advantage of it. I always believed in microprocessors but the market wasn’t big enough in the early days. Ted Hoff showed that microprocessors could be used for calculators and traffic lights and the volume could come in what we now call embedded controllers. I continued to support it despite the fact that for a long time the business was smaller than the development systems we sold to implement them. But just when memories were going out, microprocessors were coming into their own. Success came because we always sought to use silicon in unique ways.” So what did Gordon have to say about his contribution and the future of our industry: “I helped get the electronics revolution off on the right foot . . . I hope. I think the real benefits of what we have done are yet to come. I sure wish I could be here in a hundred years just to see how it all plays out.” The day after this discussion with Gordon, I knew it was the first day of a new era, one without Gordon Moore’s oversight. I got up that morning half-wondering if the sun would rise again to shine on Silicon Valley. It did – reflecting Gordon Moore’s ever-present optimism for the future of technology. As has Moore’s law, which continues to plug on, delivering benefits to many who will never realize the important contributions of this man and his observation.

Appendix A Moore’s law governs the real limit to how fast costs can grow. Starting with the basic equations (2.1) and (2.2), the optimal component density for any given period is: Ct = 2 · Ct−1 ,

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where Ct = Component count in period t, Ct−1 = Component count in the prior period (Also please note the “−1” here and below is symbolic in nature and not used mathematically.) According to the original paper given in 1965, the minimal cost of manufacturing a chip should decrease at a rate that is nearly inversely proportional to the increase in the number of components. So the cost per component, or transistor, should be cut roughly in half for each tick of Moore’s clock: Mt−1 2 = 0.5 · Mt−1 ,

Mt =

where Mt = Manufacturing cost per component in period t, Mt−1 = Manufacturing cost component in the prior period. However, since this paper was first given, it has generally been believed that industry growth will not be affected if the cost per function drops by at least 30% for every doubling of transistors. Thus: Mt = 0.7 · Mt−1 since, Tdct and, Ct Tdct−1 = , Ct−1

Mt = Mt−1

where Tdct = Total die cost in period t, Tdct−1 = Total die cost in the prior period. Thus, Tdct 0.7 · Tdct−1 = , Ct Ct−1 Tdct 0.7 · Tdct−1 = , 2 · Ct−1 Ct−1 2 · Ct−1 · 0.7 · Tdct−1 Tdct = Ct−1 Simplified it reduces to: 2 · 0.7 · Ct−1 · Tdct−1 , Ct−1 Tdct = 1.4Tdct−1 .

Tdct =

If the cost-per-function reduction ratio is different than 0.7, then Tdct = 2 · Cpfr · Tdct−1 ,

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where: Cpfr = Cost-per-function reduction ratio for every node as required by the market. In general, the manufacturing cost per unit area of silicon can rise by 40% per node of Moore’s law (or by twice the cost-per-function reduction ratio requirement. This includes everything from the fab cost to materials and labor. However, it does not take yield or wafer size into account. Adding these two: Twct = 2 · Cpfr · Twct−1 . So, Tdct =

Twct 2 · Cpfr · Twct−1 = , Dpwt · Yt W · Dpwt−1 · Yr · Yt−1

where Twct = Total wafer cost requirement in period t, Twct−1 = Total wafer cost in the prior period, Dpwt = Die-per-wafer in period t, Yt = Yielded die-per-wafer in period t, W = Ratio of die added with a wafer size change, Dpwt−1 = Die-perwafer in the prior period, Yr = Yield reductions due to improvements with time. Yt−1 = Yielded die-per-wafer in the prior period.

References 1. G.E. Moore, Lithography and the future of Moore’s law. SPIE 2440, 2–17 (1995) 2. G.E. Moore, The future of integrated electronics. Fairchild Semiconductor (1965). This was the original internal document from which Electronics Magazine would publish “Cramming more components into integrated circuits,” in its April 1965 issue celebrating the 35th anniversary of electronics 3. G.E. Moore, Progress in digital integrated electronics, in International Electron Devices Meeting (IEEE, New York, 1975) 4. K. Marx, Capital (Progress, Moscow, 1978). Chap. 15, Sect. 2 5. J.S. Mill, Principles of Political Economy (London, 1848) 6. G. Ip, Did greenspan push high-tech optimism on growth too far?. The Wall Street Journal, December 28, 2001, pp. A1, A12 7. H.R. Huff, John Bardeen and transistor physics, in Characterization and Metrology for ULSI Technology 2000. AIP Conference Proceedings, vol. 550 (American Institute of Physics, New York, 2001), pp. 3–29 8. G.D. Hutcheson, The chip insider. VLSI Research Inc., September 17, 1998 9. Scientific American Interview: Gordon Moore, in Scientific American, September 1997 10. W.R. Runyan, K.E. Bean, Semiconductor Integrated Circuit Processing Technology (Addison-Wesley, Reading, 1990), p. 18 11. C.E. Spork, Spinoff (Saranac Lake, New York, 2001) 12. R.H. Dennard, IBM – field-effect transistor memory. US Patent 3,387,286, Issued June 4, 1968 13. G.D. Hutcheson, The VLSI capital equipment outlook. VLSI Research Inc., 1987 14. G.D. Hutcheson, The chip insider. VLSI Research Inc., May 25, 2001 15. G.D. Hutcheson, J.D. Hutcheson, Technology and economics in the semiconductor industry. Sci. Am. 274, 54–62 (January, 1996) 16. J. Diamond, Guns, Germs, and Steel (W.W. Norton, New York, 1997)

Part II

State-of-the-Art

3 Using Silicon to Understand Silicon J.R. Chelikowsky

3.1 Introduction Silicon is the material of our time. We live in the age of silicon; it is all around us in terms of electronic gadgets and computers. However, it has not always been that way. There was a time before silicon. In the 1940s, transistors did not exist at all and in the early 1950s, transistors were made of germanium, not silicon. These germanium transistors were not very reliable; in particular they were difficult to package and process, and worked over a very limited temperature range. This changed by the mid-1950s. On May 10, 1954, Texas Instruments announced the invention of the silicon transistor: A revolutionary new electronic product – long predicted and awaited – became a reality today with the announcement by Texas Instruments Incorporated of the start of commercial production on silicon transistors. By using silicon instead of germanium, the initial commercial silicon transistor immediately raises power outputs and doubles operating temperatures! The potential application of this entirely new transistor is so great that major electronics firms have been conducting silicon experiments for some time. – Texas Instruments Press Release.1 Within ten years after the invention of the silicon transistor, a silicon chip containing over 2000 transistors was constructed. In contrast, the current Pentium-4 processor made by Intel contains 42 million transistors. By the end of this decade, we should see a processor containing one billion transistors. Today’s silicon-based computers are capable of teraflop performance2 and the next generation will be exhibiting improvements of several orders of magnitude. One can contrast this with the computers available before transistor computers were developed. At best, vacuum tube computers were capable of several kiloflops, or were roughly six orders of magnitude slower than contemporary computers! This 1 http://www.ti.com/corp/docs/company/history/siltransproduction.shtml. 2 A “teraflop” corresponds to one trillion floating point operations per second.

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increase in computing speed of about an order of magnitude every decade coincides with Moore’s law, which states the number of transistors per integrated circuit will double every 18 months [1]. This is an amazing and unprecedented progression of technology, which has affected all of science. A revolution in our understanding of the theory of materials has accompanied this technological revolution. Silicon technology has provided a material for serving both as a testing ground material and as the basic material for computational tools to study the properties of materials [1]. One measure of scientific impact is to examine the technical literature. Suppose we examine the number of scientific papers on silicon published since the discovery of the silicon chip. A quick search of the scientific and engineering literature suggests that over a quarter of a million papers have been written over the last 30 years that mention silicon [1]. Of course, many of these papers are not directly related to silicon technology or silicon science, but a good fraction of them are. For anyone interested in electronic materials research, this is a “treasure trove” of information. Specifically, this vast database can be used to test and benchmark theoretical methodology and approximations. This is an imperative activity as the quantum theory of materials deals with extraordinarily complex systems. In a macroscopic crystal of silicon, one has 1023 electrons and nuclei. In principle, the application of the known laws of quantum mechanics would allow one to predict all physical and chemical properties of such a system. However, given the astronomical number of particles and corresponding degrees of freedom, it is absolutely hopeless to extract physically meaningful results without some dramatic approximations. What approximations will work and how well? One avenue to help resolve this question is to test methods using the silicon database as a reference. This has been the route used by most condensed matter theorists, at least those interested in the electronic properties of solids (and liquids). The confluence of these two megatrends (advances in materials and computing power), both resulting from the study of silicon, has resulted in the ability of materials physicists to apply new concepts, which can be tested against the silicon database, and to invent new algorithms, which can be implemented on high performance computing platforms. The combination of new ideas and new avenues for computing allows us to predict the properties of materials solely from theoretical constructs. While few would argue that such approaches will replace experimentation in the near term, it possible to use computers to predict some properties more accurately than experimentation can.

3.2 The Electronic Structure Problem 3.2.1 The Empirical Pseudopotential Method The first realistic energy bands for electronic materials were constructed using silicon spectroscopic data, i.e., reflectivity and photoemission data. In particular, the energy bands were fixed using the solution of a one-electron Schrödinger equation

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Fig. 3.1. Pseudopotential model of a solid. The ion cores (nucleus plus core electrons) are chemically inert. The pseudopotential accurately reproduces the electronic states of the valence electrons

[2, 3]. These band diagrams established a framework that allowed one to interpret and understand transport and optical properties of semiconductors. In order to solve for the energy bands of silicon, the electronic interactions have to be accurately described. When the first energy bands were constructed, the understanding of these interactions was limited and was not amenable to calculations from “first principles.” Several approximations were required. One approximation was to assume that the many-electron problem could be mapped on a one-electron problem. This approximation was justified by the Hartree approximation [3]. Another approximation was to separate the chemically active valence states from the chemically inert core electrons. This resulted in the so-called “pseudopotential” approximation. The pseudopotential model of solids is illustrated in Fig. 3.1. In the 1960s, these pseudopotentials were developed and applied to silicon and related materials such as other semiconductors and simple metals [2]. Establishing the accuracy of these potentials was a key test and the results were strikingly successful [3, 4]. One could accurately replicate the experimental results with just a few parameters. Pseudopotentials can be formally justified by the Phillips–Kleinman cancellation theorem [5], which states that the orthogonality requirement of the valence states to the core can be translated into an effective kinetic term in the potential. This repulsive term cancels the strong attractive part of the Coulomb potential. The resulting pseudopotential can be written as a Fourier expansion in plane waves: Vpa (G)S(G) exp(iG · r), (3.1) Vp (r) = G

Vpa (G)

where is the atomic form factor or the Fourier coefficients of the pseudopotential, S(G) is the structure factor, and G is a reciprocal lattice vector. The form

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Fig. 3.2. Diamond crystal structure

factors are functions only of the magnitude of the reciprocal vector, provided one assumes a spherical pseudopotential, Vpa (r), centered on each atom. For the silicon in the diamond crystal (see Fig. 3.2), the structure factor is given by S(G) = cos(G · τ ) where τ = a(1, 1, 1)/8 is the basis vector and a is the lattice parameter. For Si, a = 5.43 Å. For a semiconductor such as silicon, the sum over reciprocal lattice vector converges so rapidly that only three unique form factors are required to define the potential. The form factors can be extracted from model potentials based on atomic spectra and then fitted to the experiment. The experimental data available greatly exceeds the number of form factors and it is not possible to obtain an arbitrary band configuration. The band structure method, which requires fitting the form factors to the experiment is called the “empirical pseudopotential method” or EPM [2–4]. Most of our understanding of the electronic structure of semiconductors is derived from this method. One of the first applications of the EPM was to determine the energy bands of silicon. The three form factors required were Vp (G2 = 3, 8, 11) where G is in units of 2π/a. As an example, typical values for the form factors are Vp (G2 = 3, 8, 11) = −0.112, 0.028, 0.036 atomic units,3 respectively. A plane wave basis in Bloch form is commonly used: αn (k, G) exp i(k + G) · r (3.2) ψn,k (r) = G

where k is the wave vector, and n is the band index. Pseudopotentials for a semiconductor such as Si require no more than about 50 G-vectors for a converged solution. A matrix of this size is diagonalized to extract the energy bands as a function of k: 1 2 (3.3) det (k + G) − En (k) δG,G + Vp |G − G | S(G − G ) = 0, 2 3 In atomic units (a.u.), e = h = m = 1. Energies are given in hartrees (1 Eh = 27.2 eV) ¯

and the atomic unit of length is the bohr unit (1 a0 = 0.529 Å).

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Fig. 3.3. Energy band structure of crystalline silicon. Two different band structures are illustrated, corresponding to two different pseudopotentials. See Cohen and Chelikowsky [2] for details

where atomic units are used. Equation (3.3) can easily be solved on a laptop computer. In Fig. 3.3, an energy band structure for silicon is illustrated for two different pseudopotentials. The energy bands are similar near the gap, but the valence band width is different. The procedure is empirical because the potentials can be modified to bring the energy bands into agreement with the experiment. Given the wave functions and energy bands, it is possible to determine the optical response of the system. A simple approach is to use the Ehrenreich–Cohen dielectric function [6]: 2 4π 2 2 δ ωcv (k) − ω Mcv (k) d3 k, (3.4) 2 (ω) = 3ω2 cv (2π)3 BZ where the sum is over all transitions from the filled valence band (v) to the empty conduction bands (c), ωcv (k) = Ec (k) − Ev (k), and the integration is over all k points in the Brillouin zone. The dipole matrix element is given by |Mcv (k)|2 = |ck|∇|vk|2 . The real part of the dielectric function, 1 is determined by causality, i.e., by a Kramers–Kronig transformation. Given the dielectric function: = 1 + i2 one can write the normal incident reflectivity in terms of the complex index of refraction, N , where N 2 = as N (ω) − 1 2 . (3.5) R(ω) = N (ω) + 1 Owing to the quasi-continuous nature of energy bands, reflectivity spectra for solids are not highly structured. This situation is in strong contrast with respect to atomic

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Fig. 3.4. Modulated reflectivity spectra of silicon. Top panel is experiment from Zucca and Shen [51]. The bottom panel gives two theoretical spectra corresponding to the band structures in Fig. 3.3

spectra, which are highly structured with discrete absorption and emission lines. However, it is possible to enhance structural features in the spectra of solids by taking the numerical derivative of the spectra with respect to an external parameter or to the wavelength of the light. Such “modulated” spectra show structures associated with the band structure van Hove singularities [2]. In Fig. 3.4, the wavelength modulated reflectivity spectrum of silicon is illustrated along with the calculated spectrum. Overall the agreement is satisfactory, especially with respect to the peak positions. The EPM calculations do not include spin–orbit coupling, which in the case of silicon is small. The “doublet” peak in the experimental spectrum around 3.4 eV is from spin–orbit effects. Also, the Ehrenreich–Cohen dielectric function does not include local fields [2], nor does it include excitonic effects, i.e., electron–hole interactions. Excitons play only a small role in silicon in terms of altering the band gap, but may have profound effects on the spectral line shape, especially near the threshold. This likely accounts for the “sharpness” of the reflectivity spectrum at low energies.

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Values for the form factors for other semiconductors can be found in the literature [2–4]. The EPM does equally well, if not better, in describing the optical features of semiconductors other than Si. It is not unusual for the energy bands to agree with the experiment to within ∼0.25 eV over a ∼15 eV range, or within a few percent. Suppose the EPM had failed the “Si test” and not yielded an accurate energy band description for this well-known material? Such a failure would have had profound ramifications; it would have suggested that a one-electron description of semiconducting materials was not possible. 3.2.2 Ab Initio Pseudopotentials and the Electronic Structure Problem While “empirical pseudopotentials” can be used for systems with high symmetry, their use for complex systems becomes problematic. The lack of symmetry means that the number of forms factors can be quite large; too large to be fixed by experiment. While it is possible to fix a model potential and extract form factors for an arbitrary reciprocal lattice vector, the transferability of such potentials is often uncertain. The effect of charge transfer and hybridization is not present in empirical pseudopotentials, save for the system for which the pseudopotentials were fit. As an extreme example, Na and Cl pseudopotentials fit to the standard states of Na (a metal) and Cl (a gas composed of covalent molecules), will not likely result in an accurate description of crystalline NaCl (a ionic solid). In most contemporary work, electronic potentials have been fixed not by experiment, but from “first principles.” These first principles pseudopotentials often rely on density functional theories, which are “exact” in principle, but in practice rely on a variety of approximations such as the local density approximation. A solution to the electronic structure is obtained in this approach from the Kohn–Sham equation [7, 8]: 2 2 −h¯ ∇ p (3.6) + Vion (r) + VH (r) + Vxc (r) ψn (r) = En ψn (r), 2m p

where Vion is the ion-core pseudopotential, VH is the Coulomb or Hartree potential and Vxc is the effective exchange-correlation potential. The Hartree potential is obtained by solving a Poisson equation: ∇ 2 VH (r) = −4πeρ(r),

(3.7)

where ρ is the charge density given by ρ(r) = −e

ψn (r)2 .

(3.8)

occup,n

The summation is over all occupied states. Within the local density approximation, the Vxc potential is functional of the charge density: Vxc = Vxc [ρ]. Solving the Kohn–Sham problem corresponds to the construction of a selfconsistent screening potential (VH plus Vxc ) based on the charge density. The ioncore pseudopotential is based on an atomic calculation, which is easy to implement

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Fig. 3.5. All electron and pseudopotential wave function for the 3s state in silicon. The all electron 3s state has nodes which arise because of an orthogonality requirement to the 1s and 2s core states

[9–11]. In the case of silicon, the ion-core pseudopotential corresponds to the nuclear charge plus the screening potential from the core electrons (1s 2 2s 2 2p 6 ). The ion-core pseudopotential when so screened by the valence charge will yield the same solution as the all-electron potential, save for the charge density near the core region. A variety of methods exist to construct pseudopotentials [9]. Almost all these methods are based on “inverting” the Kohn–Sham equation. As a simple example, suppose we consider an atom, where we know the valence wave function, ψv and the valence energy, Ev . Let us replace the true valence wave function by an approximate p pseudo-wave function, φv . Then the ion-core pseudopotential is given by p

p

Vion =

h¯ 2 φv − VH − Vxc + Ev . 2m p

(3.9)

The charge density in this case is ρ = |φv |2 , from which VH and Vxc can be calcup lated. The key aspect of this inversion is choosing φv to meet several criteria, e.g., p φv = ψv outside the core radius, rc . In Fig. 3.5, the “all-electron” wave function for the silicon 3s state is shown and compared to the “pseudo” 3s state. Unlike the all-electron potential, pseudopotentials are not simple functions of position. For example, the pseudopotential is state dependent, or angular momentum dependent, i.e., in principle one has a different potential for s, p, d, . . . states. Details can be found in the literature [9, 11].

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Fig. 3.6. Total electronic energy for polymorphs of crystalline silicon. The volume is normalized by the experimental value. The absolute energy scale is set by the details of the pseudopotential [12]

Once the Kohn–Sham equation is solved, the total electronic energy of the system can be obtained from knowledge of the energy levels and wave functions: 1 En − (3.10) Etotal = VH ρ d3 r + (Exc − Vxc )ρ d3 r + Eion-ion . 2 occup,n The sum is over all occupied states. The second term subtracts off the double counting terms. The third term subtracts off the exchange-correlation potential and adds in the correct energy density functional. The last term is the ion–ion core repulsion term. Silicon played a crucial role in assessing the validity of this approach, which has proved to be reasonably accurate for electronic materials. Typically, bond lengths can be calculated to within a few percent, although chemically accurate bond energies are more problematic. Initial applications of first principles pseudopotentials constructed within the local density approximation included studies of silicon polymorphs under pressure [12]. Specifically, Yin and Cohen [12] were the first to show the accuracy of the local density approximation for the total electronic energy of silicon in various crystalline forms. Their work is illustrated in Fig. 3.6. They found that the lowest energy structure calculated was for silicon in the diamond structure, as expected. This work produced some rather remarkable predictions. For example, pseudopotential studies predicted that some high-pressure forms of silicon would be superconducting [13]. This prediction was later confirmed by experiment. More recently, the first molecular dynamics simulations using quantum forces were done on

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silicon, including the first theoretical studies to examine the electronic and structural properties of liquid silicon and amorphous silicon [14, 15]. While the theoretical background for calculating ground state properties of manyelectron systems is now well established, excited state properties such as optical spectra present a challenge for density functional theory. Recently developed linear response theory within the time-dependent density-functional formalism provides a new tool for calculating excited states properties [16–20]. This method, known as the time-dependent local density approximation (TDLDA), allows one to compute the true excitation energies from the conventional, time-independent Kohn–Sham transition energies and wave functions. Within the TDLDA, the electronic transition energies Ωn are obtained from the solution of the following eigenvalue problem [18, 19]:

2 ωij σ δik δj l δσ τ + 2 fij σ ωij σ Kij σ,klτ fklτ ωklτ F n = Ωn2 F n (3.11) where ωij σ = j σ − iσ are the Kohn–Sham transition energies, fij σ = niσ − nj σ are the differences between the occupation numbers of the i-th and j -th states, the eigenvectors F n are related to the transition oscillator strengths, and Kij σ,klτ is a coupling matrix given by:

∂vσxc (r) 1 ∗ ∗ + φkτ (r )φlτ Kij σ,klτ = φiσ (r)φj σ (r) (r ) dr dr , (3.12) |r − r | ∂ρτ (r ) where i, j, σ are the occupied state, unoccupied state, and spin indices respectively, φ(r) are the Kohn–Sham wave functions, and v xc (r) is the LDA exchange-correlation potential. Some of the first applications of TDLDA were made to silicon clusters and quantum dots [21].

3.3 New Algorithms for the Nanoscale: Silicon Leads the Way The Kohn–Sham problem, cast within the pseudopotential-density functional formalism, is fairly easy to solve for simple elemental crystals such as silicon. For crystalline materials, the number of degrees of freedom is dramatically reduced by symmetry, i.e., the use of Bloch wave functions where k is a good quantum number [10, 11]. However, for systems that lack symmetry the Kohn–Sham problem remains quite difficult. Confined systems such as fragments of the bulk crystal, or extended systems such as an amorphous solid or a liquid are examples of such systems. In these cases, a solution of the Kohn–Sham equation involves many degrees of freedom and often scales poorly with the number of electrons in the system. Any solution of this complex problem must be handled by making several numerical and physical approximations [10, 11]. Computing the electronic structure of a known material such as silicon can test these approximations. A popular algorithm for describing the electronic structure of a localized system is based on a real space description. This algorithm solves the Kohn–Sham equation on a grid in real space [22, 23]. This method was first tested against traditional solutions for silicon clusters and quantum dots. The real space approach has become

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popular and several groups have implemented different variations of this general approach [24–27]. We illustrate a particular version of real space approaches based on high-order finite differencing [22, 23, 27]. This approach overcomes many of the complications involved with non-periodic systems such as replicating the vacuum, and although the resulting matrices can be larger than with other methods such as plane waves, the matrices are sparse. Real space methods are also easier to parallelize than plane wave methods. Even on sequential machines, we find that real space methods can be an order of magnitude faster than plane wave methods [22, 23, 27]. Real space algorithms avoid the use of fast Fourier Transforms (FFTs) by performing all calculations in real space instead of Fourier space. A benefit of avoiding FFTs is that the new approaches have very few global communications. A key aspect to the success of the finite difference method is the availability of high-order finite difference expansions for the kinetic energy operator [28]. High-order finite difference methods significantly improve convergence of the eigenvalue problem when compared with standard finite difference methods. If one imposes a simple, uniform grid on our system where the points are described in a finite domain by (xi , yj , zk ), we approximate: M ∂2 Ψ (x , y , z ) ≈ C(n)Ψ (xi + nh, yj , zk ) + O h2M+2 , i j k 2 ∂x

(3.13)

n=−M

where h is the grid spacing, C(n) are expansion coefficients, and M gives the number of neighboring points. The expansion approximation for the Laplacian is accurate to O(h2M+2 ) given the assumption that Ψ can be accurately approximated by a power series in h. This is a good assumption if pseudopotentials are used, as the resulting wave functions are smoothly varying. Algorithms are available to compute the coefficients for arbitrary order in h [28]. With the kinetic energy operator expanded as in (3.14), one can set up the Kohn– Sham equation over a grid. A typical uniform grid configuration is illustrated by examining the electronic structure of a localized system in Fig 3.7. In this illustration, a cluster is shown. Outside a given domain the wave functions must vanish. A uniform grid is not a requirement for this procedure, but the problem is considerably more difficult to implement when the grid is non-uniform. For example, if the atoms are moved, the grid should be re-optimized. Moreover, the convergence of the eigenvalue problem is no longer dependent on one grid parameter, but may require an optimization in a multi-parameter space. Ψn is computed on the grid by solving the eigenvalue problem: −h¯ 2 2m

M

C(n1 , n2 , n3 )Ψn (xi + n1 h, yj + n2 h, zk + n3 h) n1 ,n2 ,n3 =−M p + Vion (xi , yj , zk ) + VH (xi , yj , zk ) + Vxc (xi , yj , zk ) Ψn (xi , yj , zk )

= En Ψn (xi , yj , zk ).

(3.14)

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Fig. 3.7. Schematic of a real space grid for calculating the electronic structure of a localized system. The system of interest is placed in a large domain on which a uniform grid is set down. The wave functions of the system are constrained to vanish outside the domain

There are a number of difficulties which emerge when solving the (discretized) eigenproblems, besides the sheer size of the matrices. The first, and biggest, challenge is that the number of required eigenvectors is proportional to the number of atoms in the system. This number can grow up to thousands, if not more for systems such as quantum dots. In addition to storage issues, maintaining the orthogonality of these vectors can be very demanding. Usually, the most computationally expensive part of diagonalization codes is orthogonalization. Second, the relative separation of the eigenvalues decreases as the matrix size increases and this has an adverse effect on the rate of convergence of the eigenvalue solvers. Preconditioning techniques attempt to alleviate this problem. Real space codes benefit from savings brought about by not needing to store the Hamiltonian matrix, although this benefit may be offset by the need to store large vector bases.

3.4 Optical Properties of Silicon Quantum Dots The TDLDA formalism is easy to implement in real space within the higher-order finite difference pseudopotential method [29]. The real space pseudopotential code represents a natural choice for implementing TDLDA due to the real space formulation of the general theory. With other methods, such as the plane wave approach, TDLDA calculations typically require an intermediate real space basis. After the original plane wave calculation has been completed, all functions are transferred into that basis, and the TDLDA response is computed in real space [30]. The additional basis complicates calculations and introduces an extra error. The real space approach

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Fig. 3.8. Model of hydrogenated silicon quantum dot. The dot’s surface is passivated with hydrogen atoms to remove electronically active dangling bond states

simplifies implementation and allows us to perform the complete TDLDA response calculation in a single step. One of the first applications of TDLDA centered on hydrogenated silicon clusters and quantum dots. Crystalline silicon is not a very effective optical material. The optical gap in silicon is indirect, i.e., the valence band maximum and conduction band minimum do not occur at the same wave vector k. This does not allow a direct optical transition as wave vector momentum cannot be conserved without invoking lattice vibration contributions or phonons. However, as the size of the system approaches that of the electron–hole interaction, Bloch’s theorem ceases to hold. At this point, silicon is transformed to an optically active material. This occurs at length scales on the order of a few nanometers. Porous silicon is an example of an optically active form of silicon owing to the quantum confinement of the electron–hole pairs [31–34]. Silicon nanocrystals are another form of silicon where the optical properties can be strongly modified. An example of such a system is given in Fig. 3.8. In this example, a nanocrystal of silicon is hydrogenated to remove the electronically active states. A variety of methods have been developed to examine the role of optical confinement in silicon. Tight binding [35, 36], empirical pseudopotentials [37–39], quantum Monte Carlo [40], and density functional methods, including time-dependent density functional theory [21, 41, 42]. In the tight binding and empirical pseudopotential methods, parameters from crystalline silicon are extrapolated or scaled to the nano-size regime. This represents a drawback of these theories as it is problematic as to how the electron–hole and sur-

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Fig. 3.9. The theoretical optical gap for nanocrystalline silicon as a function of size. Results from tight binding (TB) [35, 52], quasi-particle excitations from density functional theory (QP-LDA) [34], time-dependent local density approximation (TDLDA) [21] and empirical pseudopotential method (EPM) [53]. With the notable exception of the EPM results, the predicted gaps are in good agreement

face terms should be scaled. Quantum Monte Carlo (QMC) methods are in principle exact, but do not generate an optical spectra and, as such, are quite limited in giving insights into higher excited states. They yield the lowest energy excitations, but current QMC implementations do not provide the oscillator strength. Density functional theory approaches can be used in the static limit. The optical gap is calculated in two steps. First, the energy to create a non-interacting electron–hole pair is calculated by finding the electron affinity (A) and the ionization energy (I ). The difference, I − A, yields the “quasi-particle” gap. This quantity cannot be compared to the optical gap for small dots without including excitonic energies. A simple approach is to compute the electron–hole coulombic energy and add this to the quasi-particle gap. However, it is difficult to include properly the electron–hole interaction. Some attempts have been made along these lines by evaluating the dielectric matrix within density functional theory [43]. In principle, time-dependent density functional theory captures the collective response of the system. The only additional approximation besides that within the local density approximation is that the system follows the applied field adiabatically [44], i.e., within TDLDA the interactions are assumed to be local in space and time. This assumption may not properly reproduce the excitonic interactions and there have been concerns raised as to whether the method scales properly with size [44, 45]. Despite these reservations, the agreement between the various methods is quite satisfactory as illustrated in Fig. 3.9. All show a strong blue shift of the absorption edge as the size of the dot is decreased. This trend can be obtained by simple “particle in a box” arguments, i.e., as the size of the box shrinks, the energy levels increase in size and separation. Although this argument is not quite correct in that it assumes

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an infinite potential barrier outside the dot, it is qualitatively correct. Typically, the gaps scale as R −n where n ≈ 1.5. The difference between the EPM and the other methods in Fig. 3.9 may arise from an incorrect transfer of parameters related to the electron–hole interactions in the crystal to the quantum do. Also, in this particular approach, quantum and classical electrostatic terms are combined in an ad hoc manner. The experimental situation is complex as a number of different synthesis methods have been used to produce nanocrystals, e.g., see [33, 46]. However, these methods yield gaps that agree in general with those shown in Fig. 3.9.

3.5 Doping Silicon Nanocrystals In nanocrystals or quantum dots, where the motion of electrons (or holes) is limited in all three dimensions, one expects that both electronic and optical properties will be affected as well. For example, in bulk semiconductors, shallow donors (or acceptors) are crucial in determining the transport properties required to construct electronic devices [47]. However, these properties are significantly altered in highly confined systems such as quantum dots. Important questions arise as to whether dopants will continue to play a role similar to that in bulk semiconductors in the nano-size regime. As is typical for electronic materials these questions have been explored in small fragments of silicon, typically passivated with hydrogen atoms. In Fig. 3.8, we illustrate such a system containing over a hundred silicon atoms. To examine the role of a dopant atom, one can consider such a dot doped with a single phosphorous atom. In such a system, the binding environment of the phosphorous–silicon bond can be strongly modified, resulting in a large change in the electron ionization energy of the phosphorous donor electron. We can calculate the electron affinity and ionization energy by calculating the total electronic energy of the system (as from (3.10) in different charge states): I = Etotal (N − 1) − Etotal (N ), A = Etotal (N ) − Etotal (N + 1),

(3.15)

where there are N electrons in the neutral system. In this situation, the electron affinity and ionization energy correspond to ground state properties for neutral and charged systems. In contrast to plane wave methods, which use super-cells, real space methods require no special assumptions to accommodate charge systems [11, 22]. In a crystal, one can calculate the binding energy of an electron to the donor atom by finding the energy difference in ionizing the phosphorous atom relative to adding an electron to the intrinsic crystal. The donor energy, Ed , is given by Ed = A(Si) − I (P : Si),

(3.16)

where I (P : Si) represents the ionization energy of the doped crystal and A(Si) represents the energy of the undoped crystal. For a crystal, Ed is typically a few

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Fig. 3.10. The affinity and ionization energies for Si quantum dots doped with P. The ionization energies for doped and undoped dots are illustrated

meV, which accounts for the ionization of donors at normal operating temperatures. The extent of the interaction can be estimated by the Bohr orbit (in a.u.): aSi = /m∗e . A rough estimate can be made using = 15 and m∗e = 0.5me [48], or aSi = 30 a.u. or 3 nm. We expect quantum dots of silicon with a diameter less than ∼6 nm to exhibit significant changes in the doping properties owing to quantum confinement. We plot ionization and affinity energies as a function of quantum dot radius, R, shown in Fig. 3.10. The ionization energies for undoped hydrogenated Si nanocrystals are also given for comparison. The most striking feature in Fig. 3.10 is that the ionization energy for the doped dot shows a very weak dependence on the size of the dot. The size dependence of ionization energy is different from the behavior of the ionization energy in undoped Si quantum dots where this quantity is very large at small radii and gradually decreases, scaling as R −1.1 . This dependence of the ionization energy on the radius is weaker than the R −2 law predicted by effective mass theory, as previously noted. It is, nevertheless, a consequence of spatial confinement of electrons (holes) within the quantum dot. The absence of a strong dependence of the ionization energy in the doped dot is largely due to the weak screening present in quantum dots and the physical confinement of the donor electron within the dot. The donor energy, Ed , is on the order of several eV, not several meV as for the bulk crystal. In this sense, phosphorous is not a shallow donor in nanoscale silicon dots. Figure 3.11 illustrates the charge density along a line through the P atom in the Si quantum dot. This plot shows the square of the wave function for the highest occupied state. This plot confirms the localization of the charge around the phosphorous atom. Given the charge distribution of the dopant electron, one can evaluate the isotropic hyperfine parameter and the corresponding hyperfine splitting (HFS), which is determined by the contact interaction between the electron and defect nuclei [49]. The method by Van de Walle and Blöchl allows one to extract the isotropic hyperfine parameter and the resulting HFS from knowledge of the charge density at the nuclear

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Fig. 3.11. Charge density for the dopant electron associated with P along the [100] direction in a silicon quantum dot. The extent of the dot along this direction is indicated by the arrows

Fig. 3.12. Calculated (•) and experimental () isotropic hyperfine parameter A vs. dot’s radius R. The solid line is the best fit to calculations (bulk value of hyperfine parameter 42 G was used to obtain this fit). The Inset shows experimental data of Fujii et al. [49] together with the fit to results of calculations. Two sets of experimental points correspond to the average size of nanocrystals (×) and the size of nanocrystals () estimated from comparison of photoluminescence energies for doped and undoped samples

site [50]. The calculated HPS for a P atom positioned in the dot center is given in Fig. 3.12. At small sizes, the HFS is very large owing to strong localization of the electron around impurity. As the radius increases, the value of the splitting decreases. Our calculated results scale with the radius of the dot as R −1.5 (effective mass theory

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gives R −3 ) [50]. In Fig. 3.12, we also present experimental data [49]. The measured values of the HFS fall on the best fit to calculated results with the limit of the fit constructed to approach the bulk value. When this study was completed, computational limitations prevented a comparison directly to the experimental size regime [54]. It should be emphasized that we found no strong dependence on the choice of the P site. We examined other sites by replacing one of the Si atoms in each shell with a P atom while retaining the passivating hydrogen atoms. We found that the ionization and binding energies were unchanged to within 10%, independent of the impurity atom position, save for the surface site. Our work illustrates how computational work can be used to describe doping in silicon nanostructures. Other work on these quantum dots includes extensive studies of the optical properties and recent studies on nanowires composed of silicon.

3.6 The Future Will silicon continue to play such an important role in understanding the electronic properties of materials? One suspects it will. For example, recent developments in algorithms for nanoscale systems with thousands of atoms are focusing on silicon atoms. As long as Moore’s law holds for silicon technology, workers will continue to work on understanding the fundamental properties of this material. As such, I see no reason why silicon will not continue to be the testing ground for new theoretical tools.

References 1. J.R. Chelikowsky, Mater. Res. Bull. 27, 951 (2002) 2. M.L. Cohen, J.R. Chelikowsky, Electronic Structure and Optical Properties of Semiconductors, 2nd edn. (Springer, Berlin, 1989) 3. J.R. Chelikowsky, M.L. Cohen, Phys. Rev. B 14, 556 (1976) 4. M.L. Cohen, T.K. Bergstresser, Phys. Rev. 141, 789 (1965) 5. J.C. Phillips, L. Kleinman, Phys. Rev. 116, 287 (1959) 6. H. Ehrenreich, M.H. Cohen, Phys. Rev. 115, 786 (1959) 7. P. Hohenberg, W. Kohn, Phys. Rev. 136, B864 (1964) 8. W. Kohn, L.J. Sham, Phys. Rev. 140, A1133 (1965) 9. N. Troullier, J.L. Martins, Phys. Rev. B 43, 1993 (1991) 10. W. Pickett, Comput. Phys. Rep. 9, 115 (1989) 11. J.R. Chelikowsky, M.L. Cohen, in Handbook of Semiconductors, 2 edn., ed. by T.S. Moss, P.T. Landsberg (Elsevier, Amsterdam, 1992) 12. M.T. Yin, M.L. Cohen, Phys. Rev. Lett. 45, 1004 (1980) 13. K.J. Chang, M.M. Dacorogna, M.L. Cohen, J.M. Mignot, G. Chouteau, G. Martinez, Phys. Rev. Lett. 54, 2375 (1985) 14. R. Car, M. Parrinello, Phys. Rev. Lett. 55, 2471 (1985) 15. R. Car, M. Parrinello, Phys. Rev. Lett. 60, 204 (1988) 16. E.K.U. Gross, W. Kohn, Phys. Rev. Lett. 55, 2850 (1985) 17. E.K.U. Gross, W. Kohn, Adv. Quantum Chem. 21, 255 (1990)

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18. M. Casida, in Recent Advances in Density-Functional Methods, Part I, ed. by D. Chong (World Scientific, Singapore, 1995), p. 155 19. M. Casida, in Recent Developments and Applications of Modern Density Functional Theory, ed. by J. Seminario (Elsevier, Amsterdam, 1996), p. 391 20. H. Appel, E.K.U. Gross, K. Burke, Phys. Rev. Lett. 90, 043005 (2003) 21. I. Vasiliev, S. Ö˘güt, J.R. Chelikowsky, Phys. Rev. B 65, 115416 (2002) 22. J.R. Chelikowsky, N. Troullier, Y. Saad, Phys. Rev. Lett. 72, 1240 (1994) 23. J.R. Chelikowsky, Y. Saad, S. Ogut, I. Vasiliev, A. Stathopoulos, Phys. Stat. Sol. (b) 217, 173 (2000) 24. E.L. Briggs, D.J. Sullivan, J. Bernholc, Phys. Rev. B 52, R5471 (1995) 25. J.E. Pask, B.M. Klein, P.A. Sterne, C.Y. Fong, Comput. Phys. Commun. 135, 1 (2001) 26. G. Zumbach, N.A. Modine, E. Kaxiras, Solid State Commun. 99, 57 (1996) 27. T.L. Beck, Rev. Mod. Phys. 74, 1041 (2000) 28. B. Fornberg, D.M. Sloan, Acta Numer. 94, 203 (1994) 29. J.R. Chelikowsky, J. Phys. D: Appl. Phys. 33, R33 (2000) 30. X. Blase, A. Rubio, S.G. Louie, M.L. Cohen, Phys. Rev. B 52, R2225 (1995) 31. J.P. Proot, C. Delerue, G. Allan, Appl. Phys. Lett. 61, 1948 (1992) 32. L.T. Canham, Appl. Phys. Lett. 57, 1046 (1990) 33. M.V. Wolkin, J. Jorne, P.M. Fauchet, G. Allan, C. Delerue, Phys. Rev. Lett. 82, 197 (1999) 34. S. Ogut, J.R. Chelikowsky, S.G. Louie, Phys. Rev. Lett. 79, 1770 (1997) 35. N.A. Hill, K.B. Whaley, Phys. Rev. Lett. 76, 3039 (1996) 36. C. Delerue, M. Lannoo, G. Allan, Phys. Rev. Lett. 84, 2457 (2000) 37. L.W. Wang, A. Zunger, J. Phys. Chem. 98, 2158 (1994) 38. L.W. Wang, A. Zunger, J. Phys. Chem. 100, 2394 (1994) 39. A. Franceschetti, L.W. Wang, A. Zunger, Phys. Rev. Lett. 83, 1269 (1999) 40. A.J. Williamson, J.C. Grossman, R.Q. Hood, A. Puzder, G. Galli, Phys. Rev. Lett. 89, 196803 (2002) 41. B. Delley, E.F. Steigmeier, Phys. Rev. B 47, 1397 (1993) 42. L.E. Ramos, J. Furthmüller, F. Bechstedt, Phys. Rev. B 71, 035328 (2005) 43. S. Ogut, R. Burdick, Y. Saad, J.R. Chelikowsky, Phys. Rev. Lett. 90, 127401 (2003) 44. G. Onida, L. Reining, A. Rubio, Rev. Mod. Phys. 74, 601 (2002) 45. L. Reining, V. Olevano, A. Rubio, G. Onida, Phys. Rev. Lett. 88, 066404 (2002) 46. J. von Behren, T. van Buuren, M. Zacharias, E.H. Chimowitz, P.M. Fauchet, Solid State Commun. 105, 317 (1998) 47. D. Melnikov, J.R. Chelikowsky, Phys. Rev. Lett. 92, 046802 (2004) 48. S.M. Sze, Semiconductor Devices, Physics and Technology, 2nd edn. (Wiley, New York, 2002) 49. M. Fujii, A. Mimura, S. Hayashhi, Y. Yamamoto, K. Murakami, Phys. Rev. Lett. 89, 206805 (2002) 50. C.G.V. de Walle, P.E. Blöchl, Phys. Rev. B 47, 4244 (1993) 51. R.R.L. Zucca, Y.R. Shen, Phys. Rev. B 1, 2668 (1970) 52. N.A. Hill, K.B. Whaley, Phys. Rev. Lett. 75, 1130 (1995) 53. F.A. Reboredo, A. Franceschetti, A. Zunger, Phys. Rev. B 61, 13073 (2000) 54. T.-L. Chan, M.L. Tiago, E. Kaxiras, J.R. Chelikowsky, Nano Lett. 8, 596 (2008)

4 Theory of Defects in Si: Past, Present, and Challenges S.K. Estreicher

4.1 Introduction Defects greatly affect the mechanical, electrical, optical, and magnetic properties of materials, especially semiconductors [1, 2]. There are many different types of defects, ranging from extended structures (e.g., grain boundaries, interfaces, dislocations, and precipitates), to complexes, to isolated native defects or impurities. The focus in this chapter is on localized defects such as vacancies, self-interstitials, isolated impurities, pairs and small complexes. These nanometer-size defects play many important roles and are the building blocks of larger defect structures. Understanding the properties of defects begins at this scale. There are many examples of the beneficial or detrimental roles of defects. Oxygen and nitrogen pin dislocations in Si and allow wafers to undergo a range of processing steps without breaking [3]. Small oxygen precipitates provide internal gettering sites for transition metals, but some oxygen clusters are unwanted donors which must be annealed out [4]. Shallow dopants are often implanted. They contribute electrons to the conduction band or holes to the valence band. Native defects, such as vacancies or self-interstitials, promote or prevent the diffusion of selected impurities, in particular dopants. Self-interstitial precipitates may release selfinterstitials, which in turn promote the transient enhanced diffusion of dopants [5]. Transition metal (TM) impurities – and especially the aggregates of TMs – are associated with electron–hole recombination centers. Hydrogen, almost always present at various stages of device processing, passivates the electrical activity of dopants and of many deep-level defects or forms extended defect structures known as platelets [6]. Mg-doped GaN must be annealed at rather high temperatures to break up the {Mg, H} complexes which suppress p-type doping [7]. Magnetic impurities such as Mn can render a semiconductor ferromagnetic. The list goes on. In the past, approximate (but sufficient) defect control has been achieved by educated guesses; for example, changing the order of the processing steps, hightemperature anneals, and a variety of such manipulations. Today, sophisticated tech-

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niques allow the manufacture of thin layers, virtually defect-free, protected from impurities in the bulk by a buried oxide [8]. The dimensions of the active volume of today’s devices are often measured in nm. Defect control at the atomic scale is increasingly required. This in turn implies the need for understanding the basic properties of defects at the atomic level: equilibrium sites; charge states and electrical activity; activation energies for reorientation, diffusion, or dissociation; interactions with common impurities such as hydrogen, carbon, oxygen, or dopants; and so on. Many defects are found in more than one configuration and/or charge state; many of their properties are affected by the position of the Fermi level, exposure to bandgap light, thermal annealing, irradiation, and other external factors. Much of the microscopic information about defects comes from electrical, optical, and/or magnetic experimental probes. The electrical data is often obtained from capacitance techniques such as deep-level transient spectroscopy (DLTS). The sensitivity of DLTS is very high and the presence of defects in concentrations as low as 1011 cm−3 can be detected. However, even in conjunction with uniaxial stress experiments, this data provides little or no elemental and structural information and, by itself, is insufficient to identify the defect responsible for electrical activity. Local vibrational mode (LVM) spectroscopy, that is, Raman and Fourier-transform infrared absorption (FTIR), often gives sharp lines characteristic of the Raman- or IR-active LVMs of impurities lighter than the host atoms. When uniaxial stress, annealing, and isotope substitution studies are performed, the experimental data provides a wealth of critical information about a defect. This information can be correlated, for example, with DLTS annealing data. However, the sensitivity of LVM techniques is relatively low as compared to DLTS. In the case of Raman, over 1017 cm−3 defect centers must be present in the sub-surface layer exposed to the laser. In the case of FTIR, some 1016 cm−3 defect centers are needed, although much higher sensitivities have been obtained from multiple-internal reflection FTIR [9]. Photoluminescence (PL) is much more sensitive, sometimes down to 1011 cm−3 , but the spectra can be more complicated to interpret [10]. Finally, magnetic probes such as electron paramagnetic resonance (EPR) [11–13] and electron–nuclear double resonance (ENDOR) [14], are wonderfully detailed and a lot of defect-specific data can be extracted: identification of the element(s) involved in the defect and its immediate surroundings, symmetry, spin density maps, etc. However, the sensitivity of EPR is also low compared to that of PL or DLTS, that is, of the order of 1016 cm−3 EPR-active centers are needed. Further, localized gap levels in semiconductors often prefer to be empty or doubly occupied as most defect centers in semiconductors are unstable in a spin 12 state. The sample must be illuminated in order to create an EPR-active version of the defect under study [11–13]. There are very few defects for which electrical, optical, and magnetic information is available. One example is interstitial hydrogen [12, 13, 15, 16]. Such a fortunate situation is the exception, not the rule. In the overwhelming majority of cases, only a fraction of the information desired can be obtained from an experiment. Then theoretical input is required. Until a decade ago or so, the predictive power of theory was limited. In recent years, however, it has become much more quantitative and first-principles theory is now a full-time partner of experiment. The energetics

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and vibrational spectra of defects, for example, are predicted reliably. On the other hand, the locations of their electrically-active gap levels are calculated with error bars that are generally too large to allow defect identification based on electrical activity alone. In contrast to experiment, which measures the properties of an unknown defect, theory begins with an assumed defect structure and predicts its properties. Then the measured and calculated properties of the defect can be compared. Following an overview of the evolution of the theory in the past few decades [17] (Sect. 4.2), I will discuss the theoretical approach most commonly used by theorists today (Sect. 4.3). Then selected recent theory developments will be highlighted (Sect. 4.4). The chapter concludes with a brief discussion (Sect. 4.5).

4.2 From Empirical to First-Principles When semiconductor technology emerged during and immediately following World War II, the most pressing issue was to understand doping. Effective mass theory (EMT) [18] described shallow-level impurities as weak perturbations to the perfect crystal. The idea was to write the Schrödinger equation for the nearly-free charge carrier, trapped very close to a parabolic band edge, in hydrogenic form with an effective mass determined by the curvature of the band. The calculated binding energy of the charge carrier is that of a hydrogen atom but reduced by the square of the dielectric constant. As a result, the associated wave function is substantially delocalized, with an effective Bohr radius some 100 times larger than that of the free H atom. A number of refinements to EMT have been proposed [19]. EMT provided a basic understanding of doping. However, it could not be extended to defects that have gap levels “far” from a band edge. These defects are not weak perturbations to the crystal and often involve substantial relaxations and distortions of the crystal, thus significantly disrupting its periodicity. The first such defects to be studied were the byproducts of radiation damage, a hot issue in the early days of the Cold War. EPR data became available for the vacancy [11, 20] and the divacancy [21] in silicon (but not the Si self-interstitial, which has never been detected). Many TM impurities, which are often very active recombination centers, have also been studied by EPR [22]. The EPR studies showed that the vacancy and the divacancy undergo symmetrylowering Jahn–Teller distortions. Interstitial oxygen, the most common impurity in Czochralski-grown Si, was known to reside at a puckered bond-centered site [23, 24]. Yet it was not realized at first how much energy is involved in such relaxations and distortions. It was believed that the physics and chemistry of defects in semiconductors are properly described (in first order) when assuming that the impurities reside at high-symmetry, undistorted, lattice sites. Defects were thought to exist in a stiff host crystal. Lattice relaxations and/or symmetry-lowering distortions were assumed to be small corrections to the energy. The important issue then was to correctly predict trends in the spin densities and electrical activities of specific defects centers in order to explain the EPR and electrical data (see, e.g., [25, 26]). The critical impor-

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tance of carefully optimizing the geometry around defects and the magnitudes of the relaxation energies were not fully appreciated until the 1980s [27, 28]. Green’s functions [1, 29–32] were the first theoretical tools used to describe localized defects in semiconductors. These calculations begin with the Hamiltonian H0 of the perfect crystal. Its eigenvalues give the band structure and the eigenfunctions are Bloch or Wannier functions. In principle, the defect-free host crystal is perfectly described. The localized defect is represented by a Hamiltonian H which includes the defect potential V . The Green’s function is G(E) = 1/(E − H ). The perturbed energies E coincide with its poles. The new eigenvalues include the gap levels of the defect and the corresponding eigenfunctions are the defect wave functions. In principle, Green’s functions provide an ideal description of the defect in its crystalline environment. In practice, there are many difficulties associated with the Hamiltonian, the construction of perfect-crystal eigenfunctions that can be used as a basis set for the defect calculation [33, 34], and the construction of the defect potential itself. The first successful Green’s functions calculations for semiconductors date back to the late 1970s [35–39]. They were used to study charged defects [38, 39] and to calculate forces [40–42], total energies [43, 44], and LVMs [45, 46]. These calculations also provided important clues about the role of native defects in impurity diffusion [47]. However, while Green’s functions provide an excellent description of the defect in a crystal, the technique is not very intuitive and are difficult to implement. Clusters or supercells are much easier to use and provide a physically and chemically appealing description of the defect and its immediate surroundings. Green’s functions have mostly been abandoned since the mid-1980s, but a rebirth within the GW formalism [48] is now taking place [49]. In 1967, in order to describe the distortions around a vacancy, Friedel et al. [50] completely ignored the host crystal. They limited their description to rigid linear combinations of atomic orbitals (LCAO) surrounding the defects. Messmer and Watkins [51, 52] expanded this approach to linear combinations of dangling-bond states. These simple quantum-chemical descriptions provided a much-needed insight and a correct, albeit qualitative, explanation of the EPR data. Here, the defect was assumed to be so localized that the entire crystal could be ignored in 0th order. The natural extension of this work was to include a few host atoms around the defect, thus defining a cluster. The calculations were performed in real space with basis sets consisting of localized functions such as Gaussians or LCAOs. The dangling bonds on the surface atoms had to be tied up in some way, most often with H atoms. Without the underlying crystal and its periodicity, the band structure is missing and the defect’s energy eigenvalues cannot be placed within the energy gap. Further, the small size of the cluster used at the time (a dozen atoms or so) artificially confined the wave functions. This affects mostly charged defects, as the charge tends to distribute itself on the surface of the cluster. However, the covalent nature of the local interactions was often well described. A cluster and the defect it contains form a large molecule. Its Schrödinger equation can be solved using any one of many electronic structure methods. The early work heavily borrowed from quantum chemistry, including extended Hückel theory

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[53, 54] and then self-consistent semiempirical Hartree–Fock, of the “NDO” type (neglect of differential, or diatomic, overlap): CNDO [55], MNDO [56], MINDO [57]. Geometries could be optimized, albeit often with symmetry assumptions. However, the methods suffered from a variety of problems such as cluster size and surface effects, basis set limitations, and lack of electron correlation. But the main problem was the use of semiempirical parameters. Their values are normally fitted to atomic or molecular data, and transferability to defects in crystals is questionable. DeLeo and co-workers extensively used the scattering-Xα method in clusters [58, 59] to study trends for interstitial TM impurities and hydrogen-alkali metal complexes. The results provided useful but qualitative insight into these issues. Ultimately, their method proved difficult to bring to self-consistency and the rather arbitrarily defined muffin-tin spheres rendered it poorly suited to the calculation of total energies vs. atomic positions. In order to bypass the surface problem, cyclic clusters have been designed, mostly in conjunction with semiempirical Hartree–Fock. Cyclic clusters can be viewed as clusters to which Born–von Karman periodic boundary conditions are applied [60, 61]. These boundary conditions can be difficult to handle, in particular when 3- and 4-center interactions are included [62]. The method of Partial Retention of Diatomic Differential Overlap [63, 64] (PRDDO) was first used for defects in diamond and silicon in the mid-1980s. It is self-consistent, contains no semiempirical parameters, and allows geometry optimizations to be performed without symmetry assumptions. These calculations scale as N 3 , where N is the total number of one-electron orbitals in the basis set. In contrast, the true ab initio Hartree–Fock methods scale as N 4 . However, PRDDO is a minimal basis set technique and ignores electron correlation. Its earliest success was to demonstrate [27, 28] the stability of bond-centered hydrogen in c-C and Si. At the time, it was not expected that an impurity as light as H could force a Si–Si bond to stretch by as much as 1.5 to 1.6 Å. PRDDO has been used to study cluster size and surface effects [65] and to describe many defects [66, 67]. The method provides good input geometries for single-point ab initio Hartree–Fock calculations [68]. However, it suffers from the problems associated with all Hartree–Fock techniques, such as unreasonably large gaps and inaccurate LVMs. A number of research groups have used Hartree–Fock and post-Hartree–Fock techniques [69–71] to study defects in clusters, but these efforts have now been mostly abandoned. Density-functional (DF) theory [72–75] with local basis sets [76]. in large clusters allows more quantitative predictions. A DF-based ab initio code developed at the University of Exeter, AIMPRO [77, 78], uses Gaussian basis sets and has been applied to many defect problems (this code handles periodic supercells as well). In addition to geometries and energetics, rather accurate LVMs for light impurities can be predicted [79, 80]. Large clusters have been used [81, 82] to study the distortions around a vacancy or divacancy in Si. However, all clusters suffer from the surface problem and lack of periodicity. Substantial progress in the theory of defects in semiconductors occurred in the mid-1980s with the combination of periodic supercells to represent the host crystal, ab-initio-type pseudopotentials [83–85] for the core regions, DF theory for the va-

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lence regions, and (classical) ab initio molecular dynamics (MD) simulations [86, 87] for nuclear motion. This combination is now referred to as “first-principles” in opposition to “semiempirical.” The parameters in the theory (size of the supercell, k-point sampling, size and type of one-particle basis set, pseudopotential) are not fitted to an experimental database but are determined self-consistently, calculated from first principles, obtained from high-level atomic calculations, or selected by the user. Note that the first supercell calculations were done in the 1970s in conjunction with approximate electronic structure methods [88–90].

4.3 First-Principles Theory First-principles methods have proven to be powerful and versatile tools to predict quantitatively some key properties of defects. The key features of the theory are as follows. The host crystal is represented by a large unit cell (“supercell”), which is reproduced periodically in all directions of space. The cell contains the defect under study, and the calculations are performed in a single cell. In order to obtain reliable energies, it is necessary to sample the Brillouin zone of the cell. A common scheme is to use a Monkhorst–Pack sampling [91] usually 2 × 2 × 2 or larger. The early supercells were quite small, often 16 or 32 atoms. Today, 64 host atoms is considered rather small and many authors use cells containing up to a couple hundred atoms. The nuclei are treated classically using MD simulations [92]. Semiempirical MD simulations are very approximate and very fast. They are appropriate for the study of very large systems [93–96]. Ab initio simulations, much more accurate but much slower, are used for more quantitative predictions. Very fast methods whose computational speed varies linearly with the size of the problem, so-called Order(N) methods, are being developed [97, 98], but their use in the context of defects in semiconductors has so far been limited. First-principles theory relies on ab initio MD simulations of the Car and Parrinello type [86]. They developed a method for coupling the approximation of stationary states of a huge basis eigenvalue problem with the associated ion dynamics. The method is generally applied to plane wave basis sets because of the great speed of fast Fourier transforms. One of the early applications to defects in silicon was the diffusion of bond-centered hydrogen [99]. An alternative ab initio approach to MD simulations, based on a tight-binding perspective, was proposed by Sankey and co-workers [87]. Their basis sets consist of pseudo-atomic orbitals with s, p, d, . . . symmetry. The wave functions are truncated beyond some radius and renormalized. The early version of this code was not self-consistent and was restricted to minimum basis sets (a single atomic-like function for each valence orbital). The next version [100] was self-consistent and could accommodate expanded and polarized basis sets. This is also the case for the flexible SIESTA code (Spanish Initiative for the Electronic Structure with Thousands of Atoms) [97, 101, 102]. The basis sets consist of local orbitals (typically, LCAOs). The method is highly intuitive and allows population analysis and other chemical

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information to be calculated. When an atom such as Si is given two sets of 3s and 3p functions plus a set of 3d orbitals, the basis set is sufficient to describe quite well virtually all the chemical interactions of this element, as the contribution of the n = 4 shell of Si is exceedingly small, except under extreme conditions that ground-state theories are not capable of handling anyway. However, proving that the basis set has converged is more cumbersome with local than with plane-wave basis sets. Classical MD simulations begin with the Born–Oppenheimer approximation to separate the electrons from the nuclei. For a given configuration of the nuclei at a time t, the DF electronic energy is calculated. The Hellmann–Feynman theorem [103, 104] gives the force on each nucleus, hence its acceleration. Newton’s laws of motion are solved, giving the positions and velocities of each nucleus at the time t +t. The nuclei are moved to their new positions, assigned their new velocities, and the electronic problem is solved again. The time step t (typically, one femtosecond) needs to be short relative to the fastest oscillation in the system. The temperature of the cell is defined from the kinetic energy of the nuclei. The electrons remain in their ground state. MD simulations performed at the nuclear temperature T = 0 K force the geometry to converge toward the nearest minimum of the potential energy. When a sufficient range of a priori plausible initial configurations for a defect are used, such “conjugate gradients” calculations provide all the stable and metastable minima of the potential energy. It is also possible to start at some high (nuclear) temperature and then use simulated quenching to explore the potential energy surface. The internuclear volume is divided into core regions close to the nuclei and a much larger valence region. The electrons near the core are removed from the calculation using norm-conserving, angular-momentum dependent ab initio pseudopotentials [105]. The choice of pseudopotential is dictated by the basis set for the singleparticle states. For example, most plane-wave packages use ultra-soft pseudopotentials [106] while SIESTA users prefer pseudopotentials in the Kleinman–Bylander form [107]. The electrons in the valence region are treated using first-principles DF theory, most commonly within the local-density or general gradient approximations [75]. Both approximations involve local exchange, resulting in a calculated band gap about half the experimental value. Non-local contributions to electron exchange [108] (of the ab initio Hartree–Fock type) produce a much better band gap but substantially increase the computational cost as the method is no longer ∼N 3 but ∼N 4 , where N is the size of the basis set. In all these calculations, the theorists must worry about supercell and basis set size [109, 110], k-point sampling [111], pseudopotentials, time steps, and other user inputs. There have been too many applications to even attempt a complete list here. Examples include complexes [112, 113], diffusion coefficients [114], formation energies [115], defect reactions and formation dynamics [116, 117], accurate LVMs [118], and even extended defects [119]. Some of the approximations inherent to the method will obviously resolve themselves as computer power increases, but others are more fundamental. First, the host crystal is a periodic supercell of finite size. Today, typical cells contain some 100 atoms, which means defect concentrations of the order of one atomic percent. This is much higher than in typical experimental situations. Since the defect is peri-

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odic, defect levels become defect bands. In cells containing fewer than 64 host atoms, defect bands can be several tenths of an eV wide. Such defect band widths are an artifact of the calculation. Second, the Brillouin zone of the supercell differs from that of the primitive cell of the crystal. The k-point sampling is finite, which does affect total energy differences, especially in cells containing fewer than 100 atoms or so. Third, the optimization of the pseudopotentials resembles an art more than a science. The predictions do depend on how well the core radii and other pseudopotential parameters have been determined. Fourth, the electronic problem is solved in the electronic ground state, with finite basis sets and within the local density or general gradient approximations. There is no information about excited states, and the non-local contributions to electron exchange are ignored. Fifth, the nuclei are treated as classical particles. This works very well for heavy nuclei, but quantum behavior has been observed for interstitial hydrogen in Si, for example [120]. Sixth, even though the zero-point energies associated with selected LVMs can be added [121], the total zero-point energy differences are missing. Finally, the energies of charged defects are not accurately calculated. Even though the supercell is always neutral owing to a neutralizing background charge, the charge distribution in the cell is not uniform. The periodicity of the defect implies that a spurious Madelung energy term is included in the total energy. This term must be removed. Point-charge type calculations [122] show that this correction may be as large as 0.3 eV for a localized charge in a Si 64 host-atoms cell. This error bar affects formation energies [123]. It also affects the calculated positions of defect-related gap levels which have yet to be quantitatively predicted on a systematic basis. This issue is compounded by the fact that calculations using local exchange (that includes LDA and GGA) seriously underestimate the energy gap. An interesting way to bypass the charged defect and band gap problems involves scaling the calculated ionization energies and electron affinities using a known “marker” defect. But there is no universal marker and the accuracy is of the order of 0.1 to 0.2 eV [124]. Progress in this area is being made [125]. Despite these approximations, the theory accurately predicts a number of important defect properties. Conjugate gradient optimizations provide equilibrium geometries in the stable and metastable states, which connects theory to experimental information obtained, for example, from EPR or uniaxial-stress FTIR. The energetics are in general quite accurate. This means the relative energies between stable and metastable configurations, formation, migration, reorientation, and binding energies. However, the total energy at a minimum of the potential energy surface is more accurate than at a saddle point, and the identification of the saddle point itself is no trivial matter [126–129]. These energetics connect the theory to all sorts of annealing data. Spin densities are also well predicted. This includes hyperfine parameters [130], which offer a direct link to EPR experiments. Calculating the change in energy associated with small atomic displacements allows the prediction of specific normal-mode frequencies of impurities lighter than the host atoms [131–133]. Some of these LVMs are Raman or FTIR active. Finally, constant-temperature MD simulations sometimes allow the study of defect diffusion or reaction [134, 135].

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It is most useful to calculate the complete dynamical matrix of the supercell [118]. Its eigenvalues are the normal-mode frequencies ωs of the system. The orthos (i = x, y, z) give the relative displacements of the nuclei α normal eigenvectors eαi for each mode s. A quantitative measure of how localized a specific mode is on one s )2 + (es )2 + (es )2 vs. atom or a group of atoms is provided by a plot of L2{α} = (eαx αy αz s or ωs . {α} may be a single atom (e.g., an isolated impurity) or a sum over a group of atoms (e.g., its host atom nearest neighbors). Such a localization plot allows the identification of all the local and pseudolocal vibrational modes in the cell (LVMs and pLVMs, respectively) as well as the resonant modes associated with a specific defect. A local mode is an impurity-associated mode with frequency above the highest normal mode of the crystal, the phonon. A pseudolocal mode is a localized mode located below the phonon. Such modes are sometimes visible as phonon sidebands in PL spectra [136, 137]. Resonant modes occur when a defect-related strain in the crystal locally disturbs host crystal modes resulting in a host-atom oscillation close to the phonon. Figure 4.1 shows the localized modes associated with bond-centered hydrogen [27, 28] H+ bc in Si. The calculated asymmetric stretch is the LVM at 2004 cm−1 (measured [15] at 1998 cm−1 ). The wag modes are a doublet pLVM at 264 cm−1 , and the symmetric stretch of the two Si NNs to H is at 409 cm−1 . The knowledge of all the normal modes of the supercell also allows one to prepare a supercell in thermal equilibrium at any temperature for constant temperature MD runs without thermalization or thermostat. Then, it is possible to calculate vibrational lifetimes and decay channels from first principles [138–140]. Finally, the knowledge of all the normal modes also allows the construction of the phonon den-

Fig. 4.1. Localization plot L2{α} of H+ bc in the Si64 supercell, with α = H (2004 and 264 lines)

or its two Si NNs (409 line). The dotted line near 540 cm−1 shows the calculated phonon

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sity of states g(ω). We obtain this function by evaluating the dynamical matrix at about 90 k points in the Brillouin zone of the supercell. Then, the Helmholtz vibrational free energy Fvib is straightforward to calculate [141], as discussed in the next section. All these issues are reviewed in detail elsewhere [142].

4.4 First-Principles Theory at Non-zero Temperatures So far, the discussion has centered around the calculation of (spin and charge) densities and electronic total energies. Of interest are total energy differences since one needs the relative energy of two metastable configurations of some defect, a formation energy relative to some chemical potential, a binding energy (energy difference between a bound complex and its dissociation products at their equilibrium sites), etc. The energetics discussed so far were potential energy differences U , calculated in the ground electronic state at T = 0 K. But the real world exists at nonzero temperatures. Most devices function at or above room temperature. Samples undergo thermal anneals, are implanted and exposed to light, etc. The behavior of defects is temperature-dependent, which is obvious when one observes diffusion, association or dissociation reactions, and other phenomena where the temperature is crucial. One approach to this issue involves thermodynamic integration [143], a method which requires extensive Monte Carlo or MD runs. A more direct approach involves calculating explicitly the various contributions to free energy differences Fvib + Fe/h + Frot + · · · as well as the configurational entropy term T Sconfig . In most cases, the electronic potential energy difference Uelec is obtained from first-principles DF theory. The vibrational free energy difference Fvib = Uvib is discussed below. Fe/h , the free energy associated with charge carriers, refers only to the difference in the number of carriers for different configurations of a defect. This does not include the background (dopant-related) free carriers: Only the change induced by the different electrical activities of different configurations of a localized defect survive the energy difference. This term has been shown to be very small in all but the most extreme cases [141]. The next term, Frot , occurs when the defect is a (nearly) free rotator, as for the interstitial H2 molecule in Si [144]. This contribution can be calculated [141] analytically from the partition function and will not be discussed here. There may be additional free energy terms associated with magnetic or spin degrees of freedom. However, high spin multiplicities are rare for impurities in Si. Finally, Sconfig is the difference in configurational entropy. It can be very small or even zero when comparing metastable configurations of a defect, but it can also be very important when discussing dissociation and association reactions. At high temperatures, this term often dominates the interactions. The processes taking place at non-zero temperatures almost always occur at constant pressure and the Gibbs free energy is the relevant quantity. As the lattice con-

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stant changes, the bond lengths change and so do the normal mode frequencies, which in turn affect the vibrational free energy. However, in crystalline semiconductors that have a high melting point, such as Si, working at constant volume rather than constant pressure is appropriate up to several hundred degrees Celsius. In Si, the thermal expansion coefficient is 4.68 × 10−6 K−1 at room temperature and the phonon frequencies shift slowly with T . Indeed, the difference between the constantpressure and constant-volume specific heats [145] CP −CV is 0.0165 J/molK at room temperature, a correction of only 0.08% to CP = 20 J/molK. This implies that the constant volume approximation is likely to work very well at low temperatures and gradually become worse at high temperatures. Therefore, we focus here on the Helmholtz free energy in the harmonic approximation and restrict ourselves to the temperature range where the use of the phonon density of states g(ω) calculated once and for all at T = 0 K is appropriate. This greatly simplifies the calculations. In fact, it renders them possible since calculating temperature-dependent anharmonic phonon densities of state is a formidable task. The phonon densities of states of defect-free crystals are normally calculated from the dynamical matrix of the primitive unit cell evaluated at thousands of q points in the Brillouin zone of the lattice. However, when studying defects, large supercells must be used and their Brillouin zones are distinct from that of the primitive unit cell. The eigenvalues of the dynamical matrix only provide a small number of normal mode frequencies, and the phonon density of states extrapolated from those few hundred frequencies lead to rather poor g(ω)s. However, evaluating the dynamical matrix at about 90 q points in the Brillouin zone of a Si64 supercell works very well and the calculated g(ω) closely matches [142] the measured data [146]. In the harmonic approximation, the Helmholtz free energy is given by ∞ Fvib (T ) = kB T ln sinh(h¯ ω/2kB T ) g(ω) dω, (4.1) 0

where kB is the Boltzmann constant. In the perfect cell, the integration is carried out up to the phonon. With a defect in the supercell, the integral extends up to the highest normal mode of the cell (perturbed phonon) and becomes a discrete sum for the high-frequency LVMs. Fvib (T = 0) is the total zero-point energy of the supercell. Once Fvib is calculated, the vibrational entropy and specific heat at constant volume are given by 2 ∂Fvib ∂ Fvib Svib = − , CV = −T . (4.2) ∂T V ∂T 2 V The latter can be compared to the measured CP in order to determine the temperature up to which the constant-volume and harmonic approximations are appropriate. For c-C, Si, Ge, and GaN [147–149], the approximations work very well up to 600– 700 K. At low temperatures, the agreement is excellent with even the finest features: Theory accurately predicts the temperature at which C/T 3 exhibits a small peak, the height of the peak, and the isotope splitting at the peak [147–150]. For defects, Fvib (T ) is generally a slowly increasing function of T . Except at very low temperatures, it is a linear function of T and the slope depends on the

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defect under consideration [141]. For example, the CH∗2 complex has two configurations in Si: Cs –Hbc · · · Si–Hab and Si–Hbc · · · Cs –Hab , where the subscript s means substitutional, and “ab” and “bc” stand for anti-bonding and bond-centered, respectively. Fvib is 0.007 eV at 300 K and 0.014 eV at 500 K, in favor of Si–Hbc · · · Cs – Hab . The numbers are somewhat larger when comparing the two interstitial hydrogen dimers in Si: the H2 molecule and the H∗2 complex (Si–Hbc · · · Si–Hab ). Here, Fvib is 0.041 eV at 300 K and 0.070 eV at 500 K, in favor of H2 . These energies appear small, but the corresponding Boltzmann terms are substantial. The role of the configuration entropy is most important when considering the formation and dissociation of complexes, that is when calculating binding free energies [151]. If a complex {A, B} has dissociation products A and B, there are often vastly different numbers of configurations in the crystal for the dissociated species and the complexes, sometimes leading to surprisingly large values for Sconfig . The calculation cannot be done in a supercell. Instead, one must use realistic concentrations of the species involved. The details of the calculation depend on the specific situation. An example is discussed below. The difference in configurational entropy per complex is Sconfig = (kB /[{A, B}]) ln(Ωpair /Ωnopair ), where [{A, B}] is the number of complexes, and Ωpair and Ωnopair are the number of configurations with all possible complexes forming and with all complexes dissociated, respectively. One can refine the calculation by introducing a capture radius rc : {A, B} is “dissociated” when no B species is within a sphere of radius rc of any A. The results are not very sensitive to the actual value of rc . However, Sconfig changes substantially when the concentrations of the various species involved change. Thus, samples containing large or small concentrations of one of the same species can have very different configurational entropy terms. Indeed, if A and/or B are abundant, there are many configurations resulting in pairs and relatively few configurations with A far away from B. On the other hand, when both A and B are scarce, there are far fewer ways to make pairs but a great number of dissociated configurations. As a result, the binding free energy of a specific complex at a specific temperature is different in samples containing different concentrations of the species involved. An example recently discussed in detail [151] involves the binding free energies of two boron–oxygen complexes in Si. Each of them contains one B atom and one interstitial oxygen dimer: {Bs , Oi , Oi } and {Bi , Oi , Oi }. The structure and chemistry of these two complexes are comparable, as are their dissociation products and binding energies at 0 K (about 0.5 and 0.6 eV, respectively). However, the first complex involves a very abundant species, substitutional boron (Bs ), while the second involves the much rarer interstitial boron (Bi ). Assuming the concentrations 1019 cm−3 for Bs , 1014 cm−3 for {Oi , Oi } and for Bi , combinatorial analysis yields Sconfig = −0.515 meV/K for {Bs , Oi , Oi } and −1.538 meV/K for {Bi , Oi , Oi }. In both cases, the contribution of Fvib can be ignored. Plots of Eb (T ) = Uelec + Fvib − T Sconfig yield straight lines with very different slopes. The {Bs , Oi , Oi } complex remains bound up to high temperatures, but the binding free energy of {Bi , Oi , Oi } becomes 0 at 400 K. Bi and {Oi , Oi } repel each other above that temperature. The critical temperature T0 at which the binding

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free energy becomes 0 depends on Uelec and on the slope, which is determined by the concentrations of the species involved and the number of sites available. If T0 is below the melting point of the material, then the complex will dissociate readily above T0 . It is interesting to note that measurements of the dissociation reaction of an {A, B} complex in a crystal is often analyzed using Arrhenius plots. If R is a dissociation rate, one often assumes the temperature dependence to be R exp{−Eb /kB T }. A plot of the (natural) logarithm of this function vs. inverse temperature provides the binding energy (slope) and the logarithm of the rate (intercept). However, Eb is a linear function of T with a coefficient approximately equal to the difference of configurational entropy between the bound and dissociated species. Thus, R exp{−Eb /kB T } = R exp{Sconfig /kB } exp{−Eb (0)/kB T }. Thus, an Arrhenius plot really yields a straight line with slope −Eb (0)/kB (binding energy at 0 K) and intercept (ln R + Sconfig /kB ). Thus, Arrhenius plots of the dissociation of an {A, B} complex in samples containing different concentrations of A and/or B should produce parallel lines since the slopes are the same but the intercepts differ. This suggests a way to measure configurational entropies. If we take R = 1011 s−1 and Sconfig = −0.5 or −1.0 meV/K, the intercepts will be at 25.3 − 5.8 = 19.5 or 25.3 − 11.6 = 13.7, a measurable change. In fact, an experimental study of the dissociation of substitutional/interstitial carbon pairs in Si did yield different dissociation rates in different samples [152].

4.5 Discussion In the past half-century, the theory of defects in semiconductors has progressed to the point that experimentalists now seek theoretical support to better explain their data. Today’s theory is almost always of the first-principles type, and the predictions are quantitative in many respects. The geometry of a defect is expected to be correct, the binding and various activation energies close to the measured ones, the hyperfine parameters accurate, and the LVMs within a few percent of experiment. However, even though the theoretical approach does not contain parameters that are fitted to an experimental database, it still contains numerous approximations. These are discussed in great detail elsewhere [153]. Some approximations will disappear as computer power increases. These include supercell size, k-point sampling, basis set size, short real times in MD simulations, and the Madelung energy correction for charged defects. The problems associated with the underestimation of the energy gap and the calculation of defect-related gap levels are being addressed by various groups. Density-functional theory is a ground state theory by construction, and precious little can be said about excited states. The description of electrons in the conduction band and of electron-hole recombination at defect levels are problems which will require a different level of theory. Progress has been achieved in expanding first-principles theory to non-zero temperatures. The method of thermodynamic integration is used more often now than in

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the past [143]. Direct calculations of free energies at constant volume can be done routinely. Actual numbers for vibrational, rotation, free carrier, and other free energy contributions have been published [141]. The critical role of the configurational entropy in processes involving the formation and dissociation of complexes has also been highlighted [151]. These issues are very significant when discussing issues such as the dynamics of thermal donor appearance and disappearance with temperature and time or the dynamics of self-assembly. If the progress achieved by theorists in the past few decades continues at a comparable pace, many of the open questions will be addressed and solved in the coming years. Such developments would be most welcome as the sizes of devices shrink to the point where the relevant samples are too small for detailed experimental analysis. Although this brief review has focused on recent progress in the supercell densityfunctional approach, other powerful theoretical tools are being developed. One such tool, only casually mentioned in this chapter, involves Green’s functions. This is mathematically and computationally more difficult but the host crystal is in principle perfectly described. The difficulties associated with finding the appropriate defect potential and allowing for geometry optimizations are being discussed [49]. A tool which was not discussed at all here is Quantum Monte Carlo [154]. Another method which is rapidly gaining popularity involves combining very fast semiempirical MD techniques with the much more accurate first-principles method in order to study large defects in supercells containing many thousands of atoms. The trick is to describe at a high level of theory the relatively small regions of a huge supercell which are affected by the dynamics while treating at an approximate level those regions that do not change much [155]. One example of such an approach is the “learn-on-the-fly” MD study of crack propagation [156]. The difficulty lies in matching the first-principles/semiempirical boundary, an especially difficult task in MD simulations when atoms enter or leave the first-principles region and/or when the number of atoms treated at the first-principles level changes with time. The theory of defects in materials is a rapidly evolving field. We live in interesting times.

Acknowledgments This work was supported in part by the National Renewable Energy Laboratory and the R. A. Welch Foundation.

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131. S. Limpijumnong, C.G. Van de Walle, Phys. Rev. B 68, 235203 (2003) 132. A.F. Wright, C.H. Seager, S.M. Myers, D.D. Koleske, A.A. Allerman, J. Appl. Phys. 94, 2311 (2003) 133. A. Carvalho, R. Jones, J. Coutinho, P.R. Briddon, J. Phys.: Condens. Matter 17, L155 (2005) 134. S.K. Estreicher, J.L. Hastings, P.A. Fedders, Phys. Rev. B 57, R12663 (1998) 135. S.K. Estreicher, J.L. Hastings, P.A. Fedders, Phys. Rev. Lett. 82, 815 (1999) 136. S.K. Estreicher, D. West, J. Goss, S. Knack, J. Weber, Phys. Rev. Lett. 90, 035504 (2003) 137. S.K. Estreicher, D. West, M. Sanati, Phys. Rev. B 72, R121201 (2005) 138. D. West, S.K. Estreicher, Phys. Rev. Lett. 96, 115504 (2006) 139. K.K. Kohli, G. Davies, N.Q. Vinh, D. West, S.K. Estreicher, T. Gregorkiewicz, K.M. Itoh, Phys. Rev. Lett. 96, 225503 (2006) 140. D. West, S.K. Estreicher, Phys. Rev. B 75, 075206 (2007) 141. S.K. Estreicher, M. Sanati, D. West, F. Ruymgaart, Phys. Rev. B 70, 125209 (2000) 142. S.K. Estreicher, M. Sanati, in Theory of Defects in Semiconductors, ed. by D. Drabold, S.K. Estreicher (Springer, Berlin, 2006), p. 95 143. E.R. Hernández, A. Antonelli, L. Colombo, P. Ordejón, in Theory of Defects in Semiconductors, ed. by D. Drabold, S.K. Estreicher (Springer, Berlin, 2006), p. 115 144. S.K. Estreicher, Acta Phys. Pol. A 102, 403 (2002) 145. P. Flubacher, A.J. Leadbetter, J.A. Morrison, Philos. Mag. 4, 273 (1959) (‘cal/g atom’ should read ‘cal/mol’, or the numbers be divided by the atomic mass of Si) 146. F. Widulle, T. Ruf, M. Konuma, I. Silier, M. Cardona, W. Kriegseis, V.I. Ozhogin, Solid State Commun. 118, 1 (2002) 147. M. Cardona, R.K. Kremer, M. Sanati, S.K. Estreicher, T.R. Anthony, Solid State Commun. 133, 465 (2005) 148. R.K. Kremer, M. Cardona, E. Schmitt, J. Blumm, S.K. Estreicher, M. Sanati, M. Bockowski, I. Grzegory, T. Suski, A. Jezowski, Phys. Rev. B 72, 075209 (2005) 149. M. Sanati, S.K. Estreicher, M. Cardona, Solid State Commun. 131, 229 (2004) 150. W. Schnelle, E. Gmelin, J. Phys.: Condens. Matter 13, 6087 (2001) 151. M. Sanati, S.K. Estreicher, Phys. Rev. B 72, 165206 (2005) 152. G. Davies, K.T. Kun, T. Reade, Phys. Rev. B 44, 12146 (1991) 153. R.M. Nieminen, in Theory of Defects in Semiconductors, ed. by D. Drabold, S.K. Estreicher (Springer, Berlin, 2006), p. 29 154. R.J. Needs, in Theory of Defects in Semiconductors, ed. by D. Drabold, S.K. Estreicher (Springer, Berlin, 2006), p. 141 155. G. Csányi, G. Moras, J.R. Kermode, M.C. Payne, A. Mainwood, A. De Vita, in Theory of Defects in Semiconductors, ed. by D. Drabold, S.K. Estreicher (Springer, Berlin, 2006), p. 193 156. G. Csányi, T. Albaret, M.C. Payne, A. De Vita, Phys. Rev. Lett. 93, 175503 (2004)

5 Structural, Elemental, and Chemical Complex Defects in Silicon and Their Impact on Silicon Devices A.A. Istratov, T. Buonassisi, and E.R. Weber

5.1 Introduction The electrical properties of silicon are intimately related to the defects and impurities it contains. A hypothetical piece of perfectly pure and defect-free silicon would be a highly resistive material that would not find many practical applications before adding impurities to dope it n-type or p-type. In practice, besides intentionally introduced impurities (dopants), silicon always contains native defects (self-interstitials and vacancies) and unintentional contaminants (oxygen, carbon, transition metals) and may contain structural defects such as voids, stacking faults, dislocations, or, in the case of multicrystalline silicon, grain boundaries. The inherent difficulty in understanding the properties and mechanisms of defect formation is that any silicon wafer is a complicated system in which native defects, dopants, unintentional impurities, and structural defects can interact with each other and affect each other in a variety of ways. Making sense of this complicated system requires a combination of approaches, including the isolated study of individual defects in well-defined, simplified structures, combined with the study of defects within the complex environment of the actual silicon wafer. The final goal is to identify, characterize, and control the defects that are most detrimental to silicon-based device performance. Often, the study of one defect can elucidate the behavior of others. In this chapter, we will show several examples from the literature of how one type of defect can be engineered or understood through control over the other types of defects and provide examples from our own work on understanding and engineering nanoscale transition metal defects in silicon. Many of these examples come from photovoltaics, a rapidly growing silicon industry which may in a few years surpass in revenues the integrated circuits industry if the current growth rate of up to 30% per year is sustained.

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5.2 Defect Interactions in Single-Crystalline Silicon Many defect reactions in silicon are affected by the native defects – vacancies, selfinterstitials, and their complexes. The origin of A-defects (now interpreted as clusters of silicon self-interstitials); D-defects (clusters of silicon vacancies); oxidationinduced stacking fault (OSF) rings (rings formed during thermal oxidation of silicon wafers at the boundary that separates the vacancy-rich area near the center of the wafer and the interstitial-rich area near its edges); swirl defects (microscopic dislocation loops arranged in swirl-like patterns), and crystal-originated pits (COPs, which are voids formed through agglomeration of vacancies) have been important research topics in the past, when it was found that these defects could affect gate oxide integrity and device performance, yield, and reliability. Starting from the early report of Seeger and Chik [1], it eventually became clear that all these defects are either complexes of vacancies or self-interstitials, or formed via interaction of vacancies and self-interstitials with oxygen; and that their formation is determined by the growth conditions of the ingot (such as pulling speed and temperature gradients). Progress in understanding the properties of native defects was hindered by the small equilibrium concentrations of native defects at room temperature (although at high temperatures their concentration may reach 1013 –1015 cm−3 ) and by the lack of experimental techniques for their direct detection. Therefore, data on the properties of native defects had to be extracted from indirect studies (such as the analysis of defects in ingots grown using different pulling parameters, kinetics of diffusion of shallow dopants, heavy metals, and precipitation of oxygen), combined with theoretical modeling. A good historical perspective is given by Bergholz and Gilles [2]. The 1982 study of Voronkov [3] established that the growth parameter V /G (where V is the crystal growth velocity and G is the temperature gradient near the melt–solid interface) determines whether the crystal is grown with vacancies or with silicon selfinterstitials as the dominant native point defect. Typically, for a given pulling rate, the thermal gradient varies from the center to the edges of an ingot, and so does the V /G ratio; consequently, an ingot may contain both vacancy-rich and interstitial-rich areas, which lead to the formation of an OSF ring. Falster et al. [4, 5] modeled the defect equilibrium between vacancies and self-interstitials and identified the crystal growth conditions required to grow relatively defect-free ingots with slight predominance of vacancies, which made it possible then to suppress the formation of the OSF ring and reduce the density of native defect clusters. The understanding of the properties of native defects in silicon, gained over many years, led to the development of crystal growth techniques which enable one to engineer distribution of defects in silicon ingots. For example, one can grow vacancyrich, interstitial-rich, or ingots in which silicon self-interstitials and vacancies are balanced in such a way that the ingot contains no COPs and no interstitial/vacancy clusters with sizes above the detection threshold of the analytical equipment used in the semiconductor industry. Likewise, solutions to the long-standing problem of controlling the oxygen precipitation behavior in silicon were found through silicon native defects engineering. Oxygen is easily incorporated into silicon and extremely difficult to remove because of its near-unity segregation coefficient from the melt. It

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is usually introduced into Czochralski (CZ) grown silicon from a quartz crucible as the latter is slowly etched away by the silicon melt. Interstitial oxygen does not significantly affect the electrical properties of the material. However, a large fraction of the total oxygen concentration incorporated into the crystal in concentrations close to its solid state solubility in silicon (typically in the 1017 –1018 cm−3 range) precipitates out during cooling of the ingot or during subsequent anneals of the wafers. Oxygen precipitates in the bulk of the silicon wafer provide sinks for transition metals (internal gettering sites), thus keeping the metals away from the devices [6]. On the other hand, oxygen precipitates formed in the near-surface area of the wafers (in the device area) are detrimental for the device yield. Hence, it is important to enhance oxygen precipitation in the bulk and simultaneously prevent the formation of oxygen precipitates in the near-surface layers of the wafers. In the past, this was achieved by controlled out-diffusion of oxygen from the near-surface areas of the wafers achieved by a high temperature anneal in inert gas. However, it was often difficult to achieve a reproducible formation of the denuded zone with the desired thickness because the formation of oxygen precipitates depends on many factors, including the oxygen content of the ingot, its growth conditions, and thermal history. Additionally, the cost of such heat treatment was substantial, and throughput of the annealing furnaces was low. The key to engineering oxygen precipitation was in understanding the defect reactions which are involved in nucleation of oxygen precipitation. Falster et al. [7] have shown that the kinetics of nucleation of oxygen precipitates is, to a large extent, determined by the local vacancy concentration. They suggested the use of short anneals in a controlled ambient followed by a rapid cool to facilitate the formation of a vacancy profile in the wafer which stimulates nucleation of oxygen precipitates in the bulk (high local vacancy concentration), but suppresses oxygen precipitation in the near-surface areas (low local vacancy concentration). This technique, called “magic denuded zones,” gives highly reproducible results and depends neither on oxygen concentration in the wafers nor on growth conditions of the ingot. It takes advantage of the facts that [7] (a) the equilibrium concentration of vacancies at high temperatures is higher than that of interstitials, (b) recombination and generation of vacancies and interstitials is much faster at the wafer surfaces than in the bulk. Transition metals and their complexes, precipitates, and inclusions are another type of defect that is a continuous cause of concerns for the semiconductor industry. These defects can reduce the efficiencies of silicon-based devices in a variety of ways, e.g., via “spiking” [8–10] or completely shunting [11, 12] pn-junctions, increasing bulk recombination [13, 14], compromising gate oxide integrity [15–17], and increasing pn-junction leakage currents [18–20]. Note that the onset of the latter three phenomena can be caused by minute quantities of impurities, e.g., interstitial transition metal concentrations as low as 1010 –1011 cm−3 (i.e., in the parts-pertrillion range). Due to their high diffusivity and solubility in silicon (see [21, 22]), transition metals such as copper and nickel can easily diffuse through the wafer to integrated circuit (IC) devices. The devices contain heavily n-type and p-type doped regions and may include areas with high local strain, which makes them attractive precipitation or segregation sites for metals. Since the device area thickness (in a

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range of a micron) is significantly less than the wafer thickness (500–800 microns), agglomeration of metals dissolved in the wafer at the preferred precipitation sites in the device area can lead to an increase in their local concentration in the device area by several orders of magnitude (proportionally to the ratio of the thicknesses of the wafer and the device area). The task of engineering the distribution of transition metals in the wafer by trapping them at intentionally formed sinks away from the devices is generally referred to as “gettering” [6, 23]. Since gettering sites have to compete with devices for metals [24], the efficiency of the gettering sites and optimization of the gettering treatments is an important issue. Extended defects, such as dislocations, generally cannot be tolerated in the device area for reasons similar to those discussed above for transition metals. With modern technology and proper seeding, single crystals can be grown dislocationfree. However, dislocations can nucleate at strained areas and interfaces in the device area during processing. Likewise, dislocations often nucleate at metal precipitates. Prevention of nucleation and propagation of dislocations in the device area was a serious problem in the 1960–1980s. Eventually, this problem was controlled by the improved quality of silicon wafers, improved device design, and lower temperature budgets utilized in device processing. Implementing strained silicon structures and continuing the reduction of device dimensions have led to renewed interest in the nucleation and propagation of dislocations. Relaxation of strain occurs via propagation of dislocations. The impact of various wafer parameters, such as doping level and impurity content (e.g., oxygen, carbon, and nitrogen) on the nucleation and propagation of misfit dislocations has yet to be fully understood. Understanding the interactions of dislocations with various impurities is very important for two reasons. First, impurities (such as oxygen) trapped at dislocation cores may arrest their propagation. Second, metal impurities segregated or precipitated at dislocations can dramatically increase their recombination activity [25–27]. In the last few years, silicon photovoltaics (PV) has become a major test ground for more extensive studies of defect reactions in silicon and has motivated many research teams to embark on the analysis of fundamental physical properties of metalrelated defects and their interactions with dislocations and grain boundaries in silicon. There are two reasons for the increase in importance of the photovoltaic-related research. The first reason is economic: up until the mid-1990s, the PV industry was in a fledgling status, and many of the technologies for growing and processing solar cell devices were borrowed directly from the microelectronics industry. The PV silicon supply would often consist of unwanted “silicon scrap” material, including the upper and lower parts of ingots. However, booming growth rates of the photovoltaic industry (20–45% annually) in the last few years has made it an important player on the silicon market. The amount of electronic-grade silicon consumed by the solar cell industry has become comparable with the needs of the IC industry. Estimates based on the current growth rate of the silicon photovoltaics predict that the solar energy market may surpass the value of the IC market within the next 10–15 years. The second reason is the unique combination of the relative simplicity of the solar cell as a device with the complexity of the defect interactions within the ma-

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terial, which could not be adequately understood without state-of-the-art analytical tools and innovative approaches. A solar cell is a flat p–n junction with geometric dimensions typically from 10 × 10 to 20 × 20 cm2 . Photovoltaic companies face the challenge of ensuring that all incident light is absorbed by the silicon and that the largest possible fraction of light-generated electrons and holes is collected by the p–n junction rather than recombining at interfaces and defects within the solar cell. Since the solar cell industry has to compete on the commodity market with fossil-fuelbased power generators, these problems have to be solved at a minimal possible cost. A 16% efficient solar cell translates into an upper limit of $0.50 per gram of fullyprocessed silicon. For comparison, a Pentium-class microprocessor contains roughly 150–200 mg of silicon and sells at a price from $150–$500, which is equivalent to $2000 per gram of fully-processed silicon. This 4000-factor difference in selling price severely limits the commercial viability of expensive, microelectronics-grade silicon purification techniques, cleanroom processing, and high-purity chemicals for solar cell applications. In order to reduce the material costs, many photovoltaic companies have chosen to use multicrystalline silicon (mc-Si) or upgraded metallurgical silicon (umg-Si), which may contain a high density of structural defects (dislocations, grain boundaries) along with oxygen and carbon [28–30], and transition metals [31–33]. Transition metals are undoubtedly one of the main culprits of undesirable carrier recombination in the bulk of the cells. Unlike single crystalline CZ and FZ wafers used for integrated circuits and power devices, in mc-Si metals are predominantly not found in the interstitially or substitutionally dissolved form, but rather in tiny (often tens or hundreds of nanometers in size) precipitates or agglomerates. The density of these nanoscale metal-rich particles is usually too low to be detected by conventional analytical techniques, and yet their removal, passivation, or defect engineering is extremely important for making solar energy economically competitive. Additionally, due to an abundance of structural defects and other impurities, transition metals in multicrystalline silicon solar cells can no longer be considered independent of other impurities, silicon native defects (interstitials and vacancies) and structural defects (such as grain boundaries and dislocations); instead, the complex defect reactions have to be taken into account. In the rest of this chapter, we will show that silicon solar cells offer a unique opportunity to investigate complex reactions involving the formation of detrimental metal-related defects, the dissolution of these defects during heat treatments, and the precipitation of metals at structural defects in silicon. Furthermore, we will present examples how novel analytical tools can be used to access the properties of nanoscale metal precipitates in silicon. While the majority of the results presented below were obtained on multicrystalline silicon used for solar cells, the conclusions are of fundamental physical nature and are not specific to PV only. The experimental methods that enabled us to analyze metal-rich particles in solar cells are synchrotron radiation-based X-ray microprobe techniques. These techniques were first applied to solar cells in the late 1990s by McHugo, Thompson, et al. [34–37]. They used an ultra-bright, synchrotron-produced X-ray beam, a few square microns or less in size, focused onto a sample mounted on an X–Y stage near an X-ray fluorescence (XRF) detector. The X-ray fluorescence microscopy (μ-XRF)

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technique enabled one to study the spatial distribution and elemental composition of metal-rich particles as small as hundreds or even tens of nm in size. The chemical states of these metal-rich particles (e.g., to distinguish if a certain particle is composed of iron oxide, silicide, silicate, metal, etc.) can be determined by utilizing the X-ray absorption microspectroscopy (μ-XAS) technique [36, 38, 39]. Finally, one can use the X-ray beam induced current technique (XBIC) [40, 41] to in situ (simultaneously with μ-XRF mapping) characterize the recombination activity of metal-related defects. Applications of these techniques allowed us to understand the preferred chemical state, distribution, and origins of iron and copper contamination in solar cells and shed light on interaction of these metals with structural defects in silicon. While all metal contaminants are detrimental for solar cells, Cu, Fe, and Ni are the most common contaminants and are usually found in higher concentrations in mc-Si than any other metal. Our X-ray microscopy experiments were performed at the Advanced Light Source (ALS) beamlines 10.3.1 and 10.3.2 at Lawrence Berkeley National Laboratory, and at the Advanced Photon Source (APS) beamlines 2-ID-D and 20-ID-B at Argonne National Laboratory. At the time of measurement, the focusing optics of ALS Beamlines 10.3.1 and 10.3.2 respectively were adjusted to achieve optimum spot sizes (spatial resolutions) of 2 × 3 μm2 and 5 × 7 μm2 , at fluxes of ∼1 × 109 photons/s. The zone plate optics of APS Beamline 2-ID-D achieved a spot size of 200 nm in diameter, with a flux ∼1010 photons/s. Further details of the experimental techniques can be found in [42–44]. A summary of deliverables of X-ray microscopy techniques used in this study is presented in Table 5.1.

5.3 Precipitation Behavior, Chemical State, and Interaction of Copper with Extended Defects in Single-Crystalline and Multicrystalline Silicon Our discussion will start with copper. Copper is a ubiquitous contaminant in siliconbased device technology that can be easily introduced into the bulk of silicon wafers. According to the existing data on solubility and diffusivity of Cu in Si [22, 45, 46], at only 425◦ C the equilibrium solubility of Cu in Si is as high as 1013 cm−3 , and the diffusivity is such that Cu can traverse 220 μm of single crystalline p-type silicon in under 10 seconds. While interstitial copper is a shallow donor with relatively benign electrical activity [14, 47], copper-rich precipitates are known to severely reduce the minority carrier diffusion length by forming bands of states within the silicon bandgap, thereby providing very effective pathways for recombination [48–52]. The precipitation of copper is unfavorable in structurally perfect p-type silicon because of the significant lattice strains involved in the formation of copper-rich precipitates [53], compounded with the energy required to change the charge state of Cu upon precipitation [47]. Copper precipitation in bulk p-type silicon can occur if the Cu contamination level is sufficiently high and the chemical driving force (electrochemical potential) for precipitation is sufficient to overcome the barrier for precipitation [50, 51, 54–56]. More importantly, even in low concentrations copper readily segregates to or precipitates in the presence of heterogeneous nucleation

Example

Deliverables

Acronym Technique name(s) Sub-technique(s)

Elemental composition, size, morphology, depth, and spatial distribution of metal-rich particles. Grain boundary structure from elastically scattered peak

μ-SXRF: Scanning μ-XRF. Often used interchangeably with μ-XRF

μ-XRF X-ray fluorescence microscopy

Dependent on local unoccupied density of states (function of local bonding)

XANES: X-ray absorption near-edge spectroscopy Structural info: Distances and # of electrons of nearest neighbor atoms

EXAFS: Extended X-ray absorption fine structure

μ-XAS X-ray absorption microspectroscopy

Recombination activity map, analogous to simple LBIC

(Traditional) XBIC

Minority carrier diffusion length map, analogous to spectrally resolved LBIC

SR-XBIC: Spectrally resolved XBIC

XBIC X-ray beam induced current

Table 5.1. Summary of synchrotron-based analytical microprobe techniques, from [44]

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sites, such as stacking faults or certain types of dislocations [57–59]. It is also known that metal-rich particles can be incorporated into structural defects during crystal growth [60]. Multicrystalline silicon (mc-Si) typically contains high transition metal concentrations combined with a high density and variety of structural defects. Not surprisingly, copper-rich particles have been observed at structural defects in poorlyperforming regions of some types of mc-Si solar cell material [33, 34, 38, 61, 62], complementing neutron activation analysis (NAA) data reporting Cu concentrations in mc-Si as high as 1015 cm−3 [31]. While Cu-rich clusters are undoubtedly not the only type of defect responsible for reducing the efficiencies of mc-Si solar cells, their known recombination activity and repeated observation in poorly-performing regions indicate they most certainly can be a contributing factor. The chemical states of these Cu-rich particles have wide-reaching implications for predicting the stability of these defects, and ultimately, their impact upon mc-Si solar cell devices [39, 63]. For example, it is much more difficult to dissolve and getter copper from copper oxide or copper silicate particles than from copper silicide due to the higher binding energy of the metal atoms to the silicides [39]. Previous studies that have attempted to determine the chemical state of Cu-rich particles in Si were largely restricted to TEM-based energy dispersive X-ray spectroscopy (EDX) and diffraction analyses of copper precipitates in samples prepared by in-diffusion of unusually high Cu concentrations, or grown from a heavily Cu-contaminated melt [64–69]. In those studies, a species of copper silicide, η-Cu3 Si, was the predominantly observed phase. The question arises as to whether copper-rich particles in intentionally contaminated samples are of a phase identical to that found in samples containing lower Cu concentrations, representative of what one might encounter in silicon without intentional contamination. For instance, the feasibility of interaction of Cu with oxygen during crystal growth with the formation of copper-oxide particles has long been an open question. To address this issue, we compared several samples with varying copper and oxygen concentrations, including a low-oxygen multicrystalline float zone (mc-FZ, [70]) sample heavily doped with copper during growth, a silicon/silicon germanium heterostructure intentionally contaminated with copper after growth, CZ with oxygen precipitates contaminated after growth, and samples of ingot-grown mc-Si extracted from near the bottom of the ingot without intentional Cu contamination, but with oxygen concentrations as high as 1018 cm−3 . Intentional contamination was performed by depositing a thin layer of metal on the surface of a sample and diffusing it at sufficiently high temperature. The metal contamination level was determined by the equilibrium solubility of metal at the diffusion temperature. The distribution of Cu in each Si sample was mapped using μ-XRF. The noteworthy observations from each of the samples are as follows: (1) For FZ-Si heavily doped with Cu during crystal growth, irregularly distributed Cu particles were observed at structural defects (grain boundaries and dislocations), as shown in Fig. 5.1(a). This irregular Cu decoration is expected for slow-

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Fig. 5.1. (a) Cu-Kα X-ray fluorescence microscopy and (b) X-ray beam induced current maps of float zone silicon contaminated with (3–4) × 1016 Cu cm−3 during crystal growth. Notice the strong correlation between the presence of copper-rich particles (a) and the decrease of current collection efficiency (b)

cooled samples, wherein supersaturated Cu can diffuse to preferred precipitation sites [59]. The observed Cu-rich particles were strongly recombination-active, as revealed by XBIC in Fig. 5.1(b). (2) Cu-rich precipitates were observed along misfit dislocations in the Si0.98 Ge0.02 /Si heterostructure. From the Cu-Kα fluorescence map (Fig. 5.2), one can clearly see the copper contamination along the network of 60◦ misfit dislocations parallel to the surface, which intersect at 90◦ angles in agreement with literature observations [25, 71, 72]. The recombination-activity of these precipitates has been well-established by electron beam induced current (EBIC) and XBIC measurements [25, 73, 74]. (3) In the CZ-Si sample containing 106 cm−3 oxygen precipitates, ∼1.1 × 106 cm−3 density of copper particles are observed (Fig. 5.3), which is close to the density of oxygen precipitates (1 × 106 cm−3 ). (4) In the as-grown cast mc-Si material, Cu-rich particles were located at a grain boundary in the material, together with similar amounts of Ni and less abundant Fe, although no intentional contamination was performed. The μ-XRF map in Fig. 5.4 shows the Cu distribution along a representative region of the grain boundary. Although the particle sizes were smaller than the X-ray beam spot size

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Fig. 5.2. Cu-Kα X-ray fluorescence microscopy map of a Cu-contaminated Si0.98 Ge0.02 /Si heterostructure. The misfit dislocations parallel to the surface, intersecting at 90◦ , are heavily decorated with Cu-rich particles, confirming the tendency of Cu to precipitate in the vicinity of structural defects

Fig. 5.3. Cu-Kα X-ray fluorescence microscopy map of Cu-contaminated Czochralski silicon with ∼106 oxygen precipitates per cm3 . Elliptical Cu-rich particles can be observed, oriented along preferred crystallographic orientations. The density of Cu particles matches the density of oxygen precipitates

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Fig. 5.4. Cu-Kα X-ray fluorescence microscopy map along a grain boundary of as-grown cast multicrystalline silicon. Despite the absence of intentional contamination, Cu-rich particles are present

of 200 nm, the number of Cu atoms per particle was determined to fall within the range of (3 ± 1.5) × 107 . Were all these Cu atoms contained within one large spherical Cu3 Si particle, the diameter of these particles would be approximately 100 ± 15 nm. However, it is also possible that these Cu3 Si molecules are distributed among a colony of nanoparticles as reported in TEM studies of intentionally-contaminated monocrystalline Si [69]. Cu K-edge μ-XANES scans of the copper-rich particles in all four samples yielded strikingly similar spectra to Cu3 Si standard material (Fig. 5.5(b,c)). It is interesting that although the X-ray absorption spectra of Cu precipitates found in mc-Si are distinctively different from those of Cu2 O standard, the Cu K-edge absorption onset energy of Cu3 Si matches that of the Cu2 O standard, and is shifted as compared to that of metallic Cu standard. The Cu K-edge absorption energy shift of Cu3 Si relative to Cu metal is not typical for all metal silicides. Iron metal and silicides, for example, have identical Fe K-edge X-ray absorption onset energies, unlike oxidized iron species that have K-edge onsets shifted to higher energies by amounts proportional to the Fe charge state [36, 75]. This behavior of Cu appears to stem from the unique electronic properties of Cu in Si. Copper dissolved in p-type silicon is well-known to diffuse predominantly as Cu+ i [45]. Recent ab initio Hartree–Fock calculations published by Estreicher [47] 10 0 indicate that Cu+ i will not diffuse as a compact [Ar]3d 4s sphere, but rather, it will promote some its electrons from the 3 d to the 4 sp orbitals to form weak covalent bonds with nearby silicon atoms. Similarly, copper atoms precipitated at certain internal voids are predicted to promote a small fraction of their electrons to 4 sp orbitals for covalent overlap with neighboring silicon atoms [47]. Macroscopic studies on and models of the properties of copper silicides have also indicated a hybridization of the valence Cu and Si orbitals [65, 76–78]. The increased delocalization of Cu valence electrons can qualitatively explain the Cu–K absorption edge shift to higher energies: as they are photo-excited out of the atom, Cu 1 s core electrons experience a greater Coulombic attraction with the Cu nucleus due to reduced electron screening, and thus require higher X-ray energies for photoionization.

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Fig. 5.5. μ-XANES showing the spectra of standard materials (a), and then the excellent match of Cu-rich particles in a variety of silicon materials with the Cu3 Si standard (b, c, taken at different beamlines)

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5.4 Precipitation Behavior, Chemical State, and Interaction of Iron with Extended Defects in Silicon It is known that even minute concentrations of iron can drastically reduce the minority carrier diffusion length in silicon. Just ∼2 × 1012 cm−3 of interstitial Fe (Fei ) or ∼2 × 1013 of iron–boron (Fei –Bs ) pairs in p-type single-crystalline silicon can reduce the minority carrier diffusion length to 50 μm (τ ∼ 1 μs), which is lower than the desirable value for most PV devices of reasonable efficiencies [79] and certainly unacceptable for the IC industry. Despite this fact, recent neutron activation analysis (NAA) data on several commercially-available mc-Si solar cell materials reveal Fe concentrations as high as 1014 to 1016 cm−3 ([32, 33]). The question naturally arises as to how mc-Si solar cells can contain so much iron yet manage to achieve reasonable operating efficiencies. DLTS or μ-PCD measurements [80–83] typically reveal only 1011 –1013 cm−3 of interstitial iron (or FeB pairs) in mc-Si. Hence, the majority of iron should be in agglomerates or precipitates, which must then be less detrimental (per iron atom) to solar cell performance than interstitial iron. Synchrotron-based microprobe techniques were used to systematically characterize iron-rich precipitates and inclusions affecting two very different types of mcSi solar cell materials: directionally-solidified cast mc-Si and SiliconFilm™ sheet material. Directionally solidified mc-Si material [84] can take days to cool down after being cast in a typical 200–300 kg ingot. SiliconFilm™ sheet material [85–87] is grown by a different process, involving lower-quality feedstock and high crystal growth rates, which produces 600–800 μm-thick sheets of mc-Si material. A typical cooling time from the silicon melting point to room temperature is measured in minutes. While such a high throughput and low-cost process has the potential to significantly reduce the price of PV [88], it also results in higher densities of structural defects [89] and increased impurity content in the material, including carbon- and oxygen-related defects [81, 87] and transition metals [33, 87]. XBIC maps revealed certain grain boundaries with exceptionally high recombination activity in both material processed into solar cells (Fig. 5.6(a)) and unprocessed material (Fig. 5.7(a)). Multiple iron-rich particles were detected by μ-XRF at these locations, as the maps in Fig. 5.6(b) and Fig. 5.7(b) demonstrate. These ironrich particles populating grain boundaries can be divided into two distinct types, with distinct physical properties. First, while the vast majority of iron-rich particles are small (e.g., P1, P3, and P4 in Fig. 5.6(b) and all particles in Fig. 5.7(b)), some rare particles have nearly two orders of magnitude higher μ-XRF Fe counts (e.g., P2 in Fig. 5.6(b); note the log scale of Fe concentration). An analysis by μ-XAS reveals that the particles with smaller Fe counts are composed of iron-silicide (FeSi2 ), while the particles with much larger Fe counts are composed of oxidized iron (Fe2 O3 ), as shown in Fig. 5.8(a) and Fig. 5.8(b), respectively. The average sizes of these two types of iron-rich particle, tabulated in Table 2, indicate that the FeSi2 particles are indeed smaller than the Fe2 O3 particles (Fig. 5.6(b)). The compositions of these particles also differ, as determined by the μ-XRF point scans. While the Fe2 O3 particles show appreciable amounts of other contaminants such as Cr, Mn, and Ca (Fig. 5.9(b)), the smaller FeSi2 particles show none of these

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Fig. 5.6. (a) Typical XBIC image of a cast mc-Si sample extracted from a fully-processed vertically-oriented (i.e., parallel to the growth direction of the ingot) wafer near the bottom of the ingot. The arrow in (a) points to a recombination-active grain boundary, a region of which was analyzed by μ-XRF in (b). Fe-rich particles are found along the grain boundary, highlighted by the arrow and the dotted line in (b). Properties of the Fe-rich particles labeled “P1” through “P4” are summarized in Table 5.2

Fig. 5.7. (a) Large area XBIC and (b) high-resolution μ-XRF map of the iron distribution at a grain boundary in as-grown cast mc-Si. Several FeSi2 nanoprecipitates are observed. Although some clustering is evident on a micron-scale, on a larger scale these FeSi2 nanoprecipitates are distributed rather homogeneously

above the μ-XRF detection limit (Fig. 5.9(a)). Only in as-grown material can Ni and Cu be found precipitated in the immediate vicinity of FeSi2 in detectable quantities, but not Cr, Mn, Ti, or Ca. The distributions of these particles also differ. While the large Fe2 O3 particles are inhomogeneously distributed, the smaller FeSi2 particles appear to be more regularly spaced. Taking into account the attenuation length of the Fe–Kα fluorescence in Si, one calculates a FeSi2 precipitate density of (1.5–2) × 106 per cm2 of grain boundary surface area in Fig. 5.7, resulting in an average spacing between precipitates of 7–8 μm along the grain boundary. The typical number of iron atoms in each of these nanoprecipitates at the grain boundaries was determined to be (2.9–3.6) × 106 .

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Fig. 5.8. μ-XAS data discern two types of Fe-rich particle in cast mc-Si material: (a) smaller iron silicide (FeSi2 ) and (b) larger iron oxide (Fe2 O3 ). Data labels (P1, P2, . . .) correspond to precipitates viewed in the μ-XRF image Fig. 5.6(b). The parameters of these precipitates can be found in Table 5.2

Fig. 5.9. Typical μ-XRF point scans for the two types of Fe-rich particle in cast mc-Si: (a) smaller FeSi2 particles without detectable quantities of other metals, and (b) larger Fe2 O3 particles wherein iron is accompanied by other elements reminiscent of ceramics, dirt, and furnace components

μ-XRF point spectra (not shown) taken on sheet material reveal Fe present at both grain boundaries and at localized intragranular defects, with a small contribution from Cr in the case of certain intragranular defects. High-resolution μ-XRF maps reveal that the intragranular defects are irregular in shape and consist of an agglomeration of many nanoparticles, as shown in Fig. 5.10. In the spaces between intragranular defects, where the XBIC signal is higher, no Fe-rich particles were detected. These intragranular defects may consist of iron precipitated at voids and their associated dislocation bunches, which are known to exist in this material [87, 90]. The grain boundaries were also decorated by Fe-rich nanoparticles, as shown in Fig. 5.10(c). The chemical states of these particles were measured by μ-XAS; by comparison with standard material, it was deduced that Fe is most likely to be in the form of iron silicide, as shown in Fig. 5.10(d).

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Fig. 5.10. (a, b) μ-XRF maps of the Fe distribution within typical intragranular defects in sheet material, noted by points of lower minority carrier lifetime. These defects consist of irregularly-shaped, micron-sized clusters of Fe nanoprecipitates. (c) μ-XRF map of Fe nanoprecipitates (radii ∼23 ± 5 nm) within a typical grain boundary, shown in 3D and in 2D projection. Despite the small size of individual Fe nanoprecipitates, they are estimated to contain a considerable fraction of the total Fe content in this sample due to their high spatial density. (d) The chemical state of the Fe nanoparticles shown in (a–c) is revealed by μ-XAS to be most similar to FeSi2

Some of the Fe-rich particles identified by μ-XRF mapping deviated significantly from the others in terms of morphology, composition, and chemical state. Large, (Fe+Cr+Ni)-rich clusters of particles containing iron in a chemical state most similar to iron silicide and in proportions reminiscent of stainless steel were observed (Fig. 5.11). Additionally, a large Fe-rich particle measuring up to 25 μm in diameter could be observed (Fig. 5.12(a)); this particle contained no Cr or Ni above the detection limit. In addition, the μ-XAS spectrum of this particle clearly indicates the presence of Fe2 O3 (Fig. 5.12(b)). The overall density of these particles is believed to be rather low, given the sighting of only one such particle in a scan area of several mm2 . To summarize, two distinct classes of Fe-rich particles have been observed in mc-Si materials: (1) iron silicide nanoprecipitates, present in higher densities at grain boundaries and intragranular defect clusters, and (2) a lower density of micron-sized

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Fig. 5.11. (a) Normalized μ-XRF point spectra of Cr/Fe/Ni-rich particles in the front and back sides of an as-grown sheet material sample. The similar composition of these particles is noted, although the particle on the back surface yields a larger XRF signal, indicating more metals are present. (b) The chemical state of the Fe in such particles found on both the back and front surfaces of the sample is revealed by μ-XAS to be FeSi2 . The coincidence of these three metals in the observed proportions suggests contamination by stainless steel; one can conclude from the μ-XAS spectra that these particles were likely introduced in metallic form and not as oxides. A high-resolution μ-XRF map of the Fe, Ni, and Cr distributions within one such particle is shown below

Fig. 5.12. (a) μ-XRF and (b) μ-XAS of an oxidized iron particle in as-grown sheet material. Note the large size of this particle relative to the iron silicide nanoprecipitates (Fig. 5.7(b), Fig. 5.10(a–c)). Such a particle, with large size and oxidized chemical state, is most likely to be an inclusion

particles, either consisting of elements suggestive of stainless steel (Fe+Cr+Ni), or oxidized iron.

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5.5 Pathways for Metal Contamination in Solar Cells Based on experimental evidence obtained in our own studies and on other reports in the literature, we were able to define five non-exclusive pathways for incorporating metals into the mc-Si material at high temperatures. These pathways are presented in Fig. 5.13: (a) direct incorporation of incompletely dissolved foreign metal-rich particles into the crystal as inclusions, (b) direct precipitation of locally supersaturated impurities from the melt, (c) segregation of metals dissolved in the melt to structural defects, (d) incorporation of dissolved metals in the melt into single-crystalline regions of the material as metal point defects, and (e) diffusion of metals from the growth surfaces into the solidified crystal, which is still at sufficiently high temperature for rapid diffusion of metals. The latter two mechanisms (d and e) are rather limited in their potential to introduce large amounts of metals into most mc-Si materials. Mechanism (e) only affects the border regions of the crystal [91]. For ribbon or sheet materials only fractions of a millimeter thick, however, this may be a motive of concern as the impurity species is more likely to diffuse through the entire thickness of the material. As far as mechanism (d) is concerned, simple equilibrium segregation models alone cannot account for the fact that 1014−16 cm−3 Fe ([33]) is present in mc-Si materials. Were the amount of Fe incorporated into the final crystal determined simply by the segregation of iron from the melt into single-crystalline regions (as defined by kSi = 8 × 10−6 ,

Fig. 5.13. Graphic representation of non-exclusive contamination pathways for iron in mc-Si, demonstrating the origins of Fe contamination in mc-Si, the physical mechanisms responsible for incorporating large amounts of Fe into the mc-Si material when warm (i.e., temperatures at which impurity atoms are mobile), and the formation mechanisms of the Fe-rich particles one observes in mc-Si material

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Table 5.2. Dimensions and chemical states of various Fe-rich particles detected by μ-XRF along a strongly recombination-active grain boundary in cast mc-Si material. Dimensions “X” and “Y” are perpendicular to the crystal growth direction of the directionally-solidified cast multicrystalline silicon ingot, while “Z” is parallel to the growth direction. Dimensions were determined by the full-width half-maximum of the Fe concentration extracted from highresolution μ-XRF line scans, while chemical states were measured with μ-XAS. Notice the elongation of FeSi2 particles along the crystal growth direction (Z-dimension). Particles P1 through P4 are shown in Fig. 5.6(b). Note also that the beam spot size is roughly 200 nm, thus dimensions given as 200–300 nm may in reality be much smaller Particle label P1 P2 P3 P4 P5 P6

Chemical state FeSi2 Fe2 O3 FeSi2 FeSi2 Fe2 O3 FeSi2

X-diameter (nm) 290 1250 ≤200 275 ∼1450 ≤200

Z-diameter (nm) 547 892 710 772 ∼1800 570

i.e., the ratio of Fe solubilities in single crystalline silicon and in the melt, [92]), this would imply that the melt at the solid–liquid interface contained as much as 0.01–1% Fe! If in fact this much Fe were present, instability in the solid–liquid interface would arise, and certainly columnar crystal growth with centimeter-sized grains would not proceed as desired in the case of cast mc-Si. The first three mechanisms (a, b, and c) can account for large amounts (parts per billion/million) of iron being incorporated into mc-Si. Evidence for mechanism (a), the inclusion of foreign particles, is provided by the μ-XRF observations of a few metal-rich particles of unusually large sizes (typically ≥1 μm, see Fig. 5.6(a), Fig. 5.12, and Table 5.2). All of these large particles observed have one or both of the following additional characteristics: (i) the coincidence of iron with large amounts of other (often slowly-diffusing) metal species (e.g., Ca, Ti, Cr, Mn, Ni), the relative proportions of which allude to certain steels or ceramics (e.g., Fig. 5.9(b) and Fig. 5.11) and (ii) an oxidized chemical state (e.g., Fig. 5.8(b), Fig. 5.12(b), and Table 5.2). This last point is a significant indicator of foreign particles being included in the melt, as it is currently believed that oxidized iron compounds are not thermodynamically favored to form under equilibrium conditions within silicon, since the ironoxygen binding energy is much weaker than that of silicon-oxygen, and thus iron cannot “out-compete” silicon for the oxygen (see the discussion below). However, an Fe2 O3 particle inserted into the silicon melt should retain its structural integrity for a limited time, as the melting temperature of Fe2 O3 is approximately 1565◦ C, about 150◦ C above the melting temperature of Si. Nevertheless, because molten Si is a reactive environment, it is extremely likely that these particles will, over time, be etched away by the melt and lead to the formation of smaller, more distributed iron silicide particles. If a limited amount of iron dissolves from iron oxide particles, then it is likely that an even greater amount of iron should dissolve from large metallic iron and iron sili-

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cide particles, given that (a) the melting temperatures of iron-silicon alloys are below that of silicon [93], and (b) the binding energy of iron atoms to a metallic iron or an iron silicide particle is weaker than to an iron oxide particle [38]. The large, micronsized (Fe+Cr+Ni)-rich clusters observed by μ-XRF in sheet material (Fig. 5.11), the compositions of which are very similar to stainless steel, were determined by μ-XAS to be composed of FeSi2 . One can conclude that this iron was most likely introduced into the melt as metallic stainless steel particles, given that oxide particles are expected to survive the rapid crystallization process. It thus seems very plausible that Fe can dissolve from the micron-sized, unoxidized (Fe+Cr+Ni)-rich clusters during crystal growth and subsequent processing, contaminating nearby structural defects. During crystal growth, foreign particles in the melt can become trapped at interruptions in the solid–liquid interface causing structural defects such as grain boundaries, instead of being pushed forward in the melt by a uniformly advancing solidification front. Faster growth velocities tend to trap larger particles [94]. Thus, stainless steel and iron oxide inclusions in fast-grown sheet material (Fig. 5.11) are typically much larger than those found in slowly-grown cast mc-Si (Fig. 5.6(b), Table 5.2). As iron-rich particles in contact with the melt dissolve, the dissolved iron content in the melt increases. Furthermore, as crystal growth progresses, the segregation of metals from solid to liquid silicon causes an increase of the metal content in the melt, more noticeably at the solid–liquid interface (depending on convective flows in the melt) [95, 96]. When high metal contents are present in the melt, mechanisms (b) and (c), described above, can result in the incorporation of large amounts of iron into the final crystal. The direct precipitation of iron from the melt, pathway (b), can only occur in special conditions, namely, when the impurity concentration in the melt reaches a critical level, as to promote the onset of a second phase. It is known that when the convective flows in the melt are not sufficient, the impurity concentration at the solid–liquid interface increases as impurities are rejected from the crystal into the melt. Once the impurity concentration at the interface reaches a critical level, any small perturbation of the interface can result in the precipitation of the metal silicide directly into the crystal [60, 95]. While the convective flows within the melt during the casting process are not likely to allow impurities to reach critical levels at the planar interface, this might not be the case near grain boundaries. It is known from the work of Abrosimov et al. [97] that a grain boundary reaching the solid–liquid interface causes a localized distortion (dip) to occur at the solid–liquid interface. It is conceivable that impurities within this dip may be more sheltered from the convective flow of the melt, wherein they may be able to reach critical concentrations and precipitate directly. The last mechanism, pathway (c), enabling large amounts of iron to be incorporated into mc-Si is the segregation of metals to structural defects. It is known that the solubility of metals in polysilicon is much higher than in single-crystalline silicon, especially at lower temperatures [98, 99]. This can be explained by the interaction of metals with dangling or reconstructed silicon bonds in structural defects (e.g., grain boundaries), as well as the reduction of strain energy from impurities settling in a distorted silicon lattice near the structural defects [98, 100–102]. Iron incorporated via this mechanism could either remain homogeneously distributed along grain

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boundaries, below the detection limit of μ-XRF, or could perhaps diffuse along grain boundaries and form iron silicide nanoprecipitates. This hypothesis is consistent with the observation of ∼1014 Fe cm−3 distributed as silicide nanoprecipitates along grain boundaries in cast mc-Si, which is the same amount of iron estimated to atomically segregate to grain boundaries at higher temperatures [103]. During sample cooling, supersaturated dissolved metals tend to precipitate at existing defect clusters or form new ones [66, 104, 105]. The actual processes leading to precipitate formation during cooling are complex and not entirely understood, but available data [98] suggests that metals supersaturate faster (i.e., have a stronger temperature dependence of solubility) within regions of the material with fewer structural defects compared to regions with elevated amounts of structural defects. Therefore, a strong driving force exists for supersaturated metals within single crystalline regions to accumulate at grain boundaries and other structural defects during sample cooling. With slow cooling rates and high metal concentrations, a few ”large” (tens of nm dia.) metal silicide precipitates are expected to form. On the other hand, faster cools offer less time for supersaturated metals to diffuse and form large particles, thus favoring a more homogeneous distribution of metals along structural defects, either atomically or as smaller precipitates [106]. While impeding the introduction of metals into the melt via the feedstock, production equipment, and/or growth surfaces will undoubtedly lead to improved materials, often there are certain limits imposed by economics, materials suppliers, or crystal growth conditions. Other strategies must be developed in parallel to limit the impact of metals on device performance. These require a fundamental understanding of how metals behave during thermal treatments and solar cell processing.

5.6 Effect of Thermal Treatments on Metal Distributions and on Device Performance In the experiment described below we monitored the effect of emitter diffusion processing temperature on the distribution of metals and its effect on the electrical properties of the material. Three adjacent vertical slices of the mc-Si ingot, with virtually identical initial crystal structure, were selected for this analysis. The first wafer was left unprocessed and was used as a reference. The second and the third wafers were processed into solar cells using different temperatures for emitter diffusion from a phosphorus spin-on source; these tasks were performed by colleagues at the Fraunhofer Institute for Solar Energy Systems in Freiburg, Germany. The second wafer was processed at 860◦ C for 120 seconds while the third wafer was processed at 1000◦ C for 20 seconds. Different annealing times were chosen to obtain comparable emitter depths. The average cooling rate after the end of RTP annealing was approximately 100◦ C/s. No anti-reflection coating was deposited, as to minimize the effect of hydrogen passivation in these experiments. The solar cell fabricated using low-temperature (860◦ C) RTP was found to be 20% (rel.) more efficient than the cell fabricated using high-temperature (1000◦ C) RTP. Most of this change in efficiency was linked to an increase of the minority

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Fig. 5.14. Laser beam induced current (LBIC) maps of minority carrier diffusion length in (a) a Low-T RTP (860◦ C, 120 sec.) solar cell and (b) a High-T (1000◦ C, 20 sec.) RTP cell. The Low-T RTP sample is 20% (rel.) more efficient than the High-T RTP sample. Note the different minority carrier diffusion length scales in (a) and (b)

carrier diffusion length Leff , as shown in the laser-beam induced current (LBIC) maps in Fig. 5.14. A characteristic region of material was extracted for synchrotron-based analytical studies from the same location in all three sister wafers. Medium-resolution μ-XRF scans were performed over the same grain boundary in all three samples, as shown in Fig. 5.15. Average metal content per metal precipitate is plotted in Fig. 5.16. Comparison of these samples led us to the following observations: (1) In the as-grown material, multiple iron-rich particles can be seen decorating the grain boundary. μ-XAS analyses (not shown) revealed the chemical state of iron in these precipitates to be most similar to iron silicide. Some copper and nickel precipitates were also observed, although in lower spatial densities. The copper was determined by μ-XAS to be in the form of copper silicide. Some similarly large particles were observed in intragranular locations, probably coinciding with dislocations. (2) In the “low-temperature RTP” sample, some large FeSi2 precipitates remain, with the same count rate (i.e., number of metal atoms per precipitate) as in the as-grown material. However, while faint traces of Ni-rich precipitates can still be detected, the number of nickel atoms per precipitate is much reduced in amount relative to the as-grown sample. Cu3 Si precipitates are no longer detectable. (3) In the “high-temperature RTP” sample, FeSi2 precipitates are detected, but they contain on average 50% fewer iron atoms than as-grown material, giving evidence for iron silicide precipitate dissolution. No Cu- or Ni-rich precipitates are above the detection limits. These results indicate that low-temperature RTP effectively dissolves most Cuand Ni-rich precipitates, while FeSi2 precipitates are largely undisturbed. This effect is due to solubilities and diffusivities of Cu and Ni that are orders of magnitude higher relative to Fe. On the other hand, high-temperature RTP not only completely dissolves the Cu- and Ni-rich precipitates, but it also partially dissolves

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Fig. 5.15. Synchrotron-based analysis of the metal content and distribution at grain boundaries in three sister wafers: (a) Unprocessed material (as-grown), (b) High-T RTP (1000◦ C, 20 sec.), and (c) Low-T RTP (860◦ C, 120 sec.). μ-XRF reveals that while some large FeSi2 precipitates remain after Low-T RTP, High-T RTP reduces the average metal content of FeSi2 precipitates by 50%, as discussed in the text. The recombination activity of intragranular regions increases with decreasing Fe content at structural defects, as seen in XBIC images and Fig. 5.14, suggesting the dissolved iron contaminates nearby regions

the FeSi2 precipitates. Higher temperatures greatly enhance the solubility and diffusivity of iron, allowing it to diffuse away from the precipitates at structural defects and contaminate the intragranular regions of the material. This effect can be seen by comparing XBIC images in Fig. 5.15: while the as-grown sample exhibits denuded (i.e., metal-lean) zones around the grain boundaries and other structural defects, the high-temperature RTP sample shows exactly the opposite, i.e., grain boundary “bleeding” into the grains. The observation of material degradation due to high temperature anneals (especially followed by fast cools) as reported in the literature [107–111] is now understood in terms of metal silicide precipitate dissolution.

5.7 Discussion: Chemical States of Metals in mc-Si The metal-rich particles in all materials analyzed in this study can be divided into two distinct classes: (a) the metal silicide (e.g., FeSi2 , NiSi2 , Cu3 Si) precipitate,

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Fig. 5.16. Average metal content per precipitate analyzed by high-resolution μ-XRF in reference material (Ref), Low-T RTP (860◦ C, 120 sec.), and High-T RTP (1000◦ C, 20 sec.). Nickel and copper silicide precipitates are nearly entirely dissolved during both RTP treatments. High-T RTP reduces the average iron silicide precipitate size by nearly 50% while low-T RTP dissolves iron silicide precipitates to a much lesser extent

typically up to several tens of nanometers in diameter, most often associated with structural defects, and (b) the occasional larger particle – up to several microns in diameter – which is frequently oxidized, found within the grains, and/or composed of multiple slowly-diffusing metal species reminiscent of foreign material inclusions (e.g., coming from stainless steels, furnace material). Metal silicide nanoprecipitates are the more frequently observed type of metalrich particle and are likely to have formed from metals incorporated in the crystal in solid solution. Although most classes of metal silicide compounds can be synthesized in the laboratory (e.g., Fe3 Si, FeSi, FeSi2 ), only the most silicon-rich metal silicides (e.g., FeSi2 , Cu3 Si, NiSi2 ) are observed in mc-Si materials. This observation is consistent with the assumption that these precipitates are formed in a silicon-rich environment through precipitation of initially-dissolved metal atoms either in the crystal or the Si melt. In the past, it has been suggested that oxidized metallic precipitates may form within silicon because many species of metal atom, e.g., Cu and Fe, have higher binding energies to oxidized compounds such as silicates and oxides than to silicides [36, 39, 63]. While it is true that metals bond strongly to oxygen, the same can also be said for silicon, and thus an analysis of whether a metallic oxide, silicate, or silicide will form should take this competitive oxidation potential into consideration. It is known that oxygen can form a very stable and electrically inactive interstitial complex with silicon (Oi ), not to mention SiO2 . Table 5.3 reproduces the enthalpy of formation per oxygen atom (the figure of merit in a balanced equation) from individual elements for a selection of oxidized species, demonstrating that when [Si] [O] > [Cu], equilibrium thermodynamics predicts that silicon will be the predominant oxidized species.

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Table 5.3. The enthalpies of formation per mol per oxygen atom at 298.15 K for various oxidized metal species in vacuum. It is shown that the binding energy of oxygen to silicon is far greater than that of oxygen to iron or to copper. The same is not true for all metals, e.g., hafnium. Data are from [130] Compound 1/2 HfO2 1/2 ZrO2 1/2 TiO2 1/2 SiO2 1/4 Fe2 SiO4 1/4 Fe3 O4 1/3 Fe2 O3 Cu2 O CuO

Δ f H◦ (kJ/mol) −572.4 −550.3 −472.0 −455.4 −370.0 −279.6 −274.7 −168.6 −157.3

While the precise values of enthalpies of formation cited in Table 5.3 do not reflect the additional detailed calculations necessary to account for the formation of a species within a cooling silicon lattice, this treatment provides the conceptual framework from which to analyze the prospect of a metal forming an oxidized species. In the presence of silicon, a strong competitor for oxygen, Cu will likely be reduced or remain unoxidized. This has been demonstrated on a macroscopic level, via the observation that an oxidizing Cu3 Si layer will first form Cu2 O on Cu3 Si, then progress to a final state of SiO2 on Cu3 Si after annealing [77]. Microscopic calculations predict that although Cui is attracted to Oi because it fits nicely into the void at the interstitial site near the Oi , no covalent Cu–O bonding occurs [112], again confirming that Si wins out over Cu when competing for oxygen. Based on these observations and our μ-XAS measurements, it is concluded that Cu in the presence of Si with [O] [Si] will not tend to form stable chemical bonds with oxygen, and thus will likely either form non-oxidized precipitates, out-diffuse, or remain dissolved if solubility permits. This treatment can be generalized to other metal and metal-oxide or metal-silicate species. For example, the values in Table 5.3 would suggest that Hf would form strong bonds to oxygen even if the heat of formation of hafnium silicide were considered, as was experimentally observed by Murarka and Chang [113]. On the other hand, it appears unlikely that iron will form oxidized precipitates within the silicon bulk, if [Si] [O] > [Fe], as confirmed by multiple identifications of sub-micron FeSi2 inclusions in mc-Si in this study. Alternative pathways are likely to exist for the introduction of oxidized metal species into mc-Si material. Large oxidized iron particles could be introduced into the melt, survive the crystal growth process, and become trapped, e.g., between grain boundaries during mc-Si growth. For example, iron in stainless steel readily oxidizes at temperatures above 1000◦ C [75], and the melting temperature of Fe2 O3 is 150◦ C higher than that of silicon. While molten silicon would invariably attack these foreign particles and reduce their size, the observation by McHugo et al. [36] of partially-

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oxidized Fe inside a Fe+Ni+Cr particle cluster >15 μm in diameter seems to suggest this contamination pathway may indeed occur. The same pathway is not predicted to occur for oxidized Cu particles, as the low melting temperatures of both Cu2 O (1235◦ C) and CuO (1326◦ C) imply that such particles would quickly dissolve in molten silicon (1414◦ C). Experimental evidence up to this point has shown no evidence for oxidized Cu-rich particles inside silicon crystals. Ensuing from the above discussion, metal-rich particles over 1 μm in size, especially those containing oxidized and/or slowly-diffusing species, are believed to be incorporated directly from the melt during crystal growth.

5.8 Discussion: Interactions between Metals and Structural Defects In almost all materials analyzed in our experiments, metal silicide precipitates were detected at structural defects in multicrystalline silicon or multilayer structures, especially two-dimensional defect surfaces such as grain boundaries and voids, in agreement with previous studies [60, 97, 114, 115]. The appearance of metal-rich particles at structural defects is likely due to a combination of processes. First, impurity atoms in solution (i.e., dissolved) in the crystal at high temperatures supersaturate upon cooling and seek the most energetically favorable sites [116] for second-phase (e.g., metal silicide) precipitate nucleation. Second, impurity atoms such as iron [99] and copper [98] have been observed to segregate to structural defects even at elevated temperatures; upon cooling, these metals will form precipitates when they reach a supersaturated state. Third, if metals are present in locally high concentrations in the melt, they can precipitate directly from the melt at structural defects that perturb the solidification front, e.g., grain boundaries, when a locally high metal content exists at the liquid solid interface [60, 97]. Such perturbations of the solidification front are also believed to favor the incorporation of foreign particles (e.g., oxidized Ti or Fe) in the melt as inclusions [94]. The end result of all these processes is the accumulation of metals at structural defects in mc-Si. Different growth techniques result in materials with different predominant structural defects: different grain sizes, different preferred orientations of grain and twin boundaries, different dislocation densities, and different densities of intragranular defects. All these factors affect the availability and spatial distribution of preferred precipitation sites, thus contributing to determine the size and spatial distribution of metal-rich particles. Several studies [117–119] indicate that each type of structural defect has its own capacity for transition metals, which affects the ability for the segregated metals to aggregate at the defect and eventually form precipitates during crystal cool-down. Evidence for this is shown in Fig. 5.17, which compares grain boundary decoration in ribbon and in cast mc-Si samples. The grain boundary locations were determined by the intensity of the elastically scattered X-ray beam in the direction of the detector (a function of grain orientation). In the cast mc-Si sample, metal silicide precipitates

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Fig. 5.17. μ-XRF maps of iron distributions in ribbon and directionally-solidified mc-Si, using the elastically scattered X-ray beam peak intensity to determine grain structure. Metal silicide nanoprecipitates are detected along certain structural defects in the ingot mc-Si, whereas in ribbon materials no metal-rich particles are detected. This difference can stem from two possible (non-exclusive) phenomena: (a) the faster cooling rate of ribbon mc-Si and a low metal concentration favor the formation of smaller precipitates below the current detection limits of μ-XRF, and (b) the structural defects in ribbon (especially 60◦ twin boundaries) have less capacity for metals than the high-angle twin and random grain boundaries of cast mc-Si and sheet materials

are detected at some grain boundaries but not at others, while no metal-rich particles are detected in ribbon. While differences in grain boundary metal decoration between cast and ribbon materials are also influenced by other factors (namely crystal cooling rates), differences within the same material (e.g., cast) can be explained only by differences in grain boundary character. The spatial density and character of structural defects are influenced by crystal growth variables, and thus vary considerably between different mc-Si materials.

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Likewise, the nature and the degree of metal-structural defect interactions also vary. Large-angle and random grain boundaries common to sheet [120, 121] and cast mcSi are the easiest for precipitate nucleation, given current model defect studies [117, 119]. This is supported by the greater abundance of metal nanoprecipitates detected by μ-XRF at these defect types (e.g., Fig. 5.10). Such structural defects with large capacities for impurities will also act as internal gettering sites, reducing the metal point defect concentration [81] and increasing the minority carrier diffusion length within the grains. On the other hand, 60◦ twin boundaries common to both cast mc-Si and ribbon [29, 30, 122] offer fewer segregation and nucleation sites for metals. Metal precipitates are seldom observed by μ-XRF at those locations in these materials.

5.9 Discussion: Engineering of Metal-Related Nanodefects by Altering the Distributions and Chemical States of Metals in mc-Si The diffusivity and solubility of interstitial transition metals increase exponentially with temperature [22]. Thus, any process during which high temperatures are used has the potential to change the distribution, and even the chemical state, of metals within the wafer. This same exponential temperature dependence also signifies that metal atoms quickly become supersaturated as the sample is cooled. The degree of supersaturation and the temperature can influence the precipitation behavior of these metals. Thus, the temperature profile during cooling, both during crystal growth and during subsequent device processing, has a strong impact on the final distribution of metals within mc-Si. Very fast cooling rates result in a homogeneous distribution of predominantly dissolved metals and their complexes, and lower the minority carrier diffusion length. Slower cools result in lower spatial densities of larger particles, enhancing minority carrier diffusion length. In as-grown mc-Si material, one must conceive of iron precipitates at grain boundaries and intragranular structural defects as effective reservoirs of metals. When metal atoms accumulate at these reservoirs, the metal defect concentration elsewhere is reduced, improving the diffusion lengths in those regions. On the other hand, when metal silicide precipitates are partially dissolved during processing, metals can diffuse from these reservoirs and contaminate neighboring regions, effectively increasing the bulk minority carrier trap density and reducing the bulk diffusion lengths, as seen in Fig. 5.14. This effect is most pronounced for cast mc-Si, in which slowcooling during crystal growth promotes the formation of larger metal silicide precipitates (and a reduction in metal point defects) in as-grown material. With a better understanding of the chemical nature and distribution of metals in mc-Si, as well as their evolution during processing, it becomes clear that the following four paths are available to reduce their impact on minority carrier lifetime: (1) Decrease the total impurity content. This is an obvious solution widely used in IC technology. However, extensive purification of silicon feedstock and growth surfaces, and elaborate cleanroom facilities, may not always be economically viable for the solar cell industry.

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(2) Remove impurities after crystal growth via gettering. While gettering has proven to be effective in this study and numerous others, and while there is definitely room for further improvement and optimization that take new understanding [123] into account, there are physical [29, 124] and economic limitations to gettering which make it difficult to remove all metals. (3) Passivate the defects. Although hydrogen passivation is generally agreed to be very effective overall [29, 124–126], some regions of mc-Si do not improve with passivation, [29, 124], especially those with high densities of structural defects [127, 128]. (4) Reduce the density of metal-related defects via intelligent crystal growth, processing, and defect engineering. Although often overlooked, this alternative can provide another boost to material performance, and can be employed in combination with the other alternatives listed previously. While it is not uncommon that the majority of metals are contained in micron-sized inclusions, the average distances between these particles are very large, so they cannot have a significant direct impact on minority carrier diffusion length. Unlike these large inclusions, smaller metal-rich particles and interstitial metals are present in significantly higher spatial densities and are much more dangerous to solar cell device performance. These observations lead us to the conclusion that to maximize the minority carrier diffusion length without changing the total metal concentration, all metals must be completely contained in large, micron-sized clusters separated by several hundreds of microns, thus minimizing the interaction between metal atoms and charge-carrying electrons. To test this hypothesis, we purposely engineered different metal distributions within heavily contaminated mc-Si material, and compared these directly to the minority carrier diffusion length. We found that metal impurity distributions can be predictably engineered, for example, by controlling the sample cooling rate from high temperatures [129]. Three samples of high purity mc-Si samples grown by FZ technique were heavily contaminated with copper, nickel, and iron at 1200◦ C (the concentration of the metals was determined by their solubility at the diffusion temperature) to mimic the high metal content which is likely to be found in the future solar grade Si material, and were subjected to different cooling rates: quench (200◦ C/s cooling rate), slow cool (3–8◦ C/s), and quench to room temperature followed by a re-anneal at 655◦ C terminated by slow cool. The metal nanodefect distributions in these three samples were mapped using μ-XRF, and the minority carrier diffusion lengths were determined by SR-XBIC. Very fast cooling rates result in a homogeneous distribution of predominantly dissolved metals and their complexes. The histogram labeled “quench” in Fig. 5.18 shows a narrow distribution of minority carrier diffusion lengths under 10 μm, unacceptable for solar cell devices. The sample quenched and subsequently re-annealed exhibits a fine distribution of nanodefect clusters, tens of nanometers in size, with lower spatial densities than in the quenched sample. Simultaneously, the minority carrier diffusion length increases almost two-fold (Fig. 5.18). Finally, a low density of micron-sized defect clusters was observed in the slowly-cooled sample, which

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Fig. 5.18. Effect of the distribution of metal defects on material performance. Material performance (minority-carrier diffusion length histograms, left) in three differently cooled samples (quench, quench and re-anneal, slow cool) is compared with size and spatial distributions of metal defects (high-resolution μ-XRF maps, right), XRF copper counts per second plotted against x and y coordinates in μm). The material with microdefects in lower spatial densities clearly outperforms materials with smaller nanodefects in higher spatial densities despite the fact that all materials contain the same total amount of metals

has a maximum minority carrier diffusion length higher than the quenched sample by a factor of four. These results provide direct evidence for the correlation between changes in metal defect distribution and enhancement of material performance.

5.10 Summary and Conclusions Silicon wafers are complex environments, with varying concentrations of intrinsic point defects, non-metallic impurities such as oxygen, metallic impurities such as iron and copper, and structural defects such as dislocations and grain boundaries. These different defect types cannot be viewed in complete isolation, but as interacting with the others as well as the crystal growth and device processing conditions. Thus, understanding the physical properties of transition metal precipitates in silicon, the interaction of metals with structural defects, and the effects of processing opens ways both for mitigation of their detrimental impact on device performance and for engineering metals in solar cells and integrated circuits.

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6 Surface and Interface Chemistry for Gate Stacks on Silicon M.M. Frank and Y.J. Chabal

6.1 Introduction: The Silicon/Silicon Oxide Interface at the Heart of Electronics The silicon metal-oxide-semiconductor field-effect transistor (MOSFET) has been at the heart of the information technology revolution. During the past four decades, we have witnessed an exponential increase in the integration density of logic circuits (“Moore’s law” [1]), powered by exponential reductions in MOSFET device size. Despite these changes, silicon oxide, usually grown by simple exposure to oxygen gas or water vapor at elevated temperatures, until recently remained the gate insulator of choice. Its success has been based on the wonderful properties of the silicon/silicon dioxide interface. This interface has only about 1012 cm−2 electrically active defects. And after a simple passivating hydrogen exposure, 1010 cm−2 defects remain – only one defect for every 100,000 interface atoms! If silicon oxide (SiO2 ) is such an excellent insulator and has served us well for decades, why would we even consider replacing it? Continued “scaling” of the MOSFET gate length has required simultaneous scaling of other geometrical and electronic device parameters, such as gate insulator thickness, threshold and supply voltages, and body doping (“Dennard’s scaling theory” [2]). During the past decade, sustaining this historical complementary MOS (CMOS) scaling trend has become increasingly challenging [3, 4]. Voltage scaling slowed down dramatically as supply voltages approached 1 V, due to constraints on the threshold voltage needed to limit source-to-drain leakage in the transistor “off” state. In addition, SiO2 or silicon oxynitride (SiON) gate dielectric scaling has all but stopped at thicknesses close to 10 Å, as the gate leakage currents due to quantum mechanical tunneling through this “insulator” have reached values of >100 A/cm2 in transistors aimed at highperformance applications, e.g., in servers. This causes computer chips to generate heat with power densities of 100 W/cm2 or more, making chip cooling technologically challenging and costly. Scaling of the gate oxide in low-power circuits, e.g., for

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cell phones, has reached its limits already near 20 Å, to ensure substantially lower gate leakage and thereby sufficient battery life. To sustain continued density and performance increases, much of the attention has turned to modified device structures [4] and to new materials, among them highpermittivity (“high-k”) gate dielectrics such as hafnium oxide (HfO2 ) to replace SiO2 or SiON [5–7] and metal gate electrodes to replace doped polycrystalline silicon (poly-Si) [5]. High-k gate insulators offer two main benefits, enabled by their increased relative permittivity compared to SiO2 (e.g., kSiO2 = 3.9; kHfO2 ∼ 20–25). This becomes apparent when visualizing the gate stack as a parallel plate capacitor. First, in a short channel transistor, a high-k dielectric more strongly confines the electrical field generated by the gate electrode to within the gate dielectric than an SiO2 layer of similar physical thickness and therefore similar gate leakage. This improves control of the gate electrode over the band bending in the channel. In the transistor off state, that translates into lower source-to-drain leakage, which in turn allows further shrinking of the gate length at a given off-state current specification. High-k dielectrics thus enable continued scaling according to Moore’s and Dennard’s laws. Second, switching speed of a high-k device is expected to be higher than with an SiO2 insulator of the same thickness t. This is due to the higher inversion charge Qinv in the channel at a given gate voltage Vgate , when the permittivity k and therefore the capacitance Cgate of the gate stack is increased: Qinv = Cgate · Vgate , with Cgate ∼ k/t. A higher inversion charge results in higher on-state currents that can flow in the channel [8]. It is convenient to define a “capacitance equivalent thickness” (CET) of the high-k layer as the physical thickness of an SiO2 layer with the same areal capacitance, i.e., Cgate ∼ khigh-k /thigh-k = kSiO2 /CET → CET = thigh-k · kSiO2 /khigh-k . Maximizing gate capacitance thus is equivalent to minimizing CET. With the advent of high-k dielectrics, it may seem that SiO2 will soon be a material of the past. However, all material changes must be made in such a way that the outstanding degree of electrical perfection achieved with SiO2 is preserved. With continued scaling to CET values near and below 10 Å, the starting surface plays an ever more critical role in terms of perfection, flatness, and cleanliness. Growth of the gate dielectric is becoming a more and more delicate process requiring atomic control. And high-k/silicon interface structure and electrical quality in the fully processed device must be tuned to an optimum. Since the silicon/silicon oxide interface is of such remarkably high quality, it will likely survive even in high-k gate stacks as a subnanometer layer between the silicon channel and the high-k dielectric, either grown intentionally or formed during high-k oxide deposition. It is thus clear that we need to gain an ever deeper understanding of silicon oxide films and the silicon/silicon oxide interface on the atomic scale. This chapter therefore describes the fundamental silicon surface science associated with the continued progress of nanoelectronics. We shall focus on the ultrathin oxide films encountered during silicon cleaning and high-k gate stack fabrication. In Sect. 6.2, we review the current practices and understanding of silicon cleaning. In Sect. 6.3, we describe the fabrication of high-k gate stacks, focusing on the continued importance of the silicon/silicon oxide interface.

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6.2 Current Practices and Understanding of Silicon Cleaning 6.2.1 Introduction Aqueous treatment of silicon surfaces is the first step to control the interfaces for further processing [9]. It typically involves a basic and/or an acidic solution treatment mixed with H2 O2 , the basis of the RCA Standard Clean developed by Kern in 1965, [10] sometimes with an HF etch in between (modified RCA clean). This cleaning procedure is effective to remove (1) particles by basic solutions that simultaneously oxidize and etch the surface (e.g., NH4 OH/H2 O2 /H2 O, referred to as SC-1), and (2) metal and hydrocarbon impurities by acid/peroxide solutions (e.g., HCl/H2 O2 /H2 O, referred to as SC-2, and H2 SO4 /H2 O2 /H2 O, referred to as piranha clean). This process leaves 6–15 Å of hydroxylated oxide on the Si surface which prevents carbon recontamination of the Si. For applications requiring a stable surface with no interfacial oxide, an “HF last” step is performed to dissolve the surface oxide completely in HF acid. The early electronic measurements of Buck and McKim (1958) [11] demonstrated the high degree of passivation of HF-treated Si surfaces, which are now known to be oxide-free and passivated with H. The H-terminated surfaces are hydrophobic in nature and are not wetted by aqueous solutions. Given the enormous practical importance of wet chemical treatment of silicon wafers during processing, each aspect of the process has been studied extensively, [9] and will be described in more detail in the next sections. The chemically grown oxides exhibit a more complex chemical composition than the high-quality stoichiometric, thermally grown SiO2 (standards for gate oxides). The importance of understanding these chemical oxides cannot be overstated, since they provide the foundation of SiO2 -based gate oxides as well as for high-k gate stacks. As the CET of high-k gate stacks decreases to ∼10 Å or less, the chemical oxides grown during preclean make up a large fraction of the total thickness and can, therefore, influence the overall performance of the dielectric. In addition, the deposition of high-k materials by atomic layer deposition (ALD) can be influenced by the nature of the chemical oxide growth (see Sect. 6.3). The mechanism leading to hydrogen passivation of silicon surfaces by HF etching is now well understood [12]. As discussed in the next section, the strong polarization of the Si–Si back-bonds of a surface Si–F species leads to removal of that surface atom as SiF4 , leaving behind a more neutral (less polar, i.e., more stable) hydrogenterminated surface. Hydrogen-passivated surfaces are remarkably stable in oxygen, nitrogen, and water vapor [13]. They only get slowly oxidized in air due to radicalmediated reactions. In solutions, hydrogen-passivated surfaces can also remain stable unless dissolved oxygen is present; or more aggressive oxidizing agents are used, such as peroxides. The degree and completeness of oxidation varies depending on the exact reagents. Among the four main methods (SC1, SC2, piranha, and nitric acid), [9] the piranha (sulfuric acid/peroxide mix, SPM) treatment leads to the most homogeneous, thinnest, and hydrogen-free oxide [14]. Starting with hydrogen-free oxides is important because some aspects of hydrogen within device structures can cause problems (reliability, etc.), although in other cases hydrogen can provide surface state passivation.

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An important aspect of wet processing is the potential control of the surface morphology via preferential etching. Indeed, the microstructural state of the surface has been shown to affect subsequent device properties [15, 16]. For instance, surface roughness can cause degradation of the breakdown field strengths of thin gate oxides [15, 17], as well as decreased channel mobilities [15, 16]. Both hydrophilic and hydrophobic surface cleans can affect the morphology of the Si surface. Chemically grown oxides are non-crystalline, limiting the information obtained from diffraction and imaging techniques. In contrast, HF etching leads to H-termination of the crystal surfaces and can be studied in greater detail by spectroscopic techniques. For instance, interesting differences are observed between the surface structures of Si(100) and Si(111) wafers after HF etching. Under specific pH conditions (e.g., pH ∼8), preferential etching of Si itself takes place, favoring the formation of (111) facets resulting in atomically flat monohydride-terminated Si(111) surfaces [18] and atomically rough, multi-hydride-terminated Si(100) surfaces (see Sect. 6.2.3). Similar behavior is observed for etching H-terminated silicon in hot water [19] and in KOH solutions [20]. Contamination is also an important issue for any cleaning or passivation process because trace amounts of impurities can drastically influence the properties of subsequently fabricated devices. Contaminants can be intrinsic (e.g., H, OH, H2 O, O2 , S, Cl, F) or extrinsic (e.g., C, Fe, Ni, Cr, Cu) to the solutions used. The contamination and the associated resulting loss of passivation of H-terminated surfaces are briefly discussed below. 6.2.2 Silicon Cleans Leading to Oxidized Silicon Surfaces All oxidizing aqueous cleans, including the RCA Standard Clean [21] leave 6–15 Å of hydroxylated oxide on the Si surface that prevents recontamination of the Si. Such surfaces are hydrophilic in nature and are easily wetted by aqueous solutions. The chemical composition of the Si surface subsequent to a clean is fundamental to its passivation. The chemically grown oxides exhibit a more complex chemical composition than the high quality stoichiometric SiO2 grown thermally. Chemical Composition of Oxidized Surfaces The properties of chemically grown oxides produced by the various integrated circuit (IC) cleaning techniques are quite similar and have been reviewed by Deal [22]. These techniques include sulfuric acid-hydrogen peroxide mixture (SPM), standard clean 1 (SC-1), or standard clean 2 (SC-2). The oxides tend to be ∼6–15 Å thick, depending on the process temperature as well as the solution chemistry used [23, 24]. These films are largely stoichiometric but, because they are so thin, exhibit properties with many of the characteristics of the interfacial transition regions of thicker, thermally grown oxides. The large suboxide content characteristic of these chemically grown oxides is shown in the Si 2p X-ray photoelectron spectroscopy (XPS) data of Sugiyama et al. [25] in Fig. 6.1. For two different chemical preparations, the spectra are dominated by the Si crystal substrate and by stoichiometric SiO2 , Si4+ . There

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Fig. 6.1. X-ray photoelectron spectra, with spin orbit splitting removed, of the Si 2p3/2 core level associated with native oxides on Si formed by immersion in (top) HNO3 at 45–50◦ C for 5 min, and (bottom) 4:1:1 H2 O:H2 O2 :NH4 OH at 63–80◦ C for 10 min. The dashed lines are the result of a spectral deconvolution performed by assuming that the chemical shifts and the values of FWHM (full width half maximum) for the various components are the same as for the Si4+ , which is associated with stoichiometric SiO2 [25]

is, however, a relatively strong and unambiguous Si2+ contribution corresponding to an interfacial transition region similar to that observed for the thermal oxides. In this case, the Si2+ contribution is 10–20% that of the Si4+ , indicating that the transition region is a large fraction of the surface layer. Besides the Si2+ , the presence of varying degrees of other suboxides depends on the exact surface treatment used [25, 26] and is not discussed here. Dangling bond defects at the Si/SiO2 interface have been quantified using minority carrier lifetime measurements to extract the surface recombination velocity and surface defect density [27]. Defect densities on the order of 1013 cm−2 are typical for these clean, unannealed native oxides, placing these surfaces at a level one-to-two orders of magnitude higher than for thermal oxides. Chemical oxidation involves species other than Si and O. All aqueous solutions, of course, are predominantly composed of H2 O and are, therefore, sources of H2 O, OH, and H. Thus, these chemical species must be incorporated in the oxide layer to some extent. Hydrogen bonding is common to all aqueous solutions and is intimately related to the heat of solvation, as well as to the hydrophilic nature of oxidecovered Si surfaces. Hydrogen-bonded O–H is observed on all chemically grown oxides, as shown for instance by the infrared (IR) absorption spectrum in Fig. 6.2 where a H-terminated Si surface was chemically oxidized using the SC-2 step of the RCA clean. The spectra presented in Fig. 6.2 are obtained by subtracting the spec-

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Fig. 6.2. Infrared absorption spectra of Si wafer chemically oxidized in a 4:1:1 solution of H2 O:H2 O2 :HCI at 80◦ C for 10 min. The ratio of the spectra lines was compared to the corresponding spectra of the H-terminated Si by etching in a buffered HF solution [29]. A multiple internal reflection geometry was used with 75 reflections at a 45◦ internal angle of incidence, as shown in the inset

trum of H-terminated Si surfaces, and therefore display a negative absorption for the Si–H stretch bands (2100 cm−1 ). The H-bonded OH stretching vibration peak is at ∼3300 cm−1 and is ∼400 cm−1 wide (FWHM) with an asymmetric line shape. It is quite difficult to distinguish between Si–O–H and H2 O in these spectra without access to the 1600–1700-cm−1 spectral region where the characteristic scissor (i.e., deformation) mode of the H2 O molecule is located. The intensity difference observed between the spectra taken in s- and p-polarization indicates that the OH groups must reside in or on the oxide layer. Although it is unclear from these spectra, one knows in very general terms that most of the IR signal comes from H2 O on the surface of the oxide, since gentle heating (100◦ C) decreases the OH/H2 O absorption substantially. The surface OH concentration is extremely important in determining the initial reaction rate for many high-k growth reactions [28], and can be varied with the chemical treatment chosen. Ozone (O3 ) treatments are the most oxidizing, producing the lowest amount of OH on the surface. SC-1 solutions, on the other hand, produce larger quantities of OH units on the surface and within the films. It appears that the OH concentration is related to the degree to which the cleaning solutions produce SiO2 . More OH-terminated groups are formed when the oxide formation is less complete and vice versa. It is also apparent that Si–H units remain after the growth of chemical oxides [25, 26]. The first convincing evidence came from the IR spectra of Ogawa et al. (1992) [24] shown in Fig. 6.3, where Si–H stretching vibrations are identified at ∼2260 cm−1 . Si–H stretches in that region of the spectrum originate from Si–H where the surface Si atom is back-bonded to O atoms [30]. This evidence clearly indicates that the Si–H resides within the oxide matrix. The area density is estimated

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Fig. 6.3. Infrared absorption spectra of six different native oxides on Si wafers: (a) “H2 SO4 ” corresponds to a 10-min treatment in 4:1 H2 SO4 :H2 O2 at 85–90◦ C, (b) “HCl” 10 min in 4:1:1 H2 O:H2 O2 :HCl at 37–65◦ C, (c) “NH4 OH,” 10 min in 4:1:1 H2 O:H2 O2 :NH4 OH at 63– 80◦ C, (d) “NH4 OH + hot HNO3 ” in “NH4 OH” followed by “hot HNO3 ” (e) “boil HNO3 ” in HNO3 at 115–125◦ C, and (f) “hot HNO3 ” 5 min in HNO3 at 45–60◦ C. The absorption (indicated by the arrow), which peaks at ∼2260 cm−1 , arises from Si–H stretches where the Si is back-bonded to O (i.e., Si–H inside SiO2 or on the upper surface of the oxide) [24]

to be 2–3 × 1013 cm−2 . X-ray photoelectron spectroscopy data from the same group suggests that these Si–H units are actually localized near the upper surface of the oxide. If this is indeed the case, these units may be residual Si–H bonds from the original H-terminated hydrophobic surface before the chemical oxidation. This kind of picture agrees well with the idea that oxidation proceeds via O atom insertion between the Si–Si back-bonds of the surface and is consistent with the observations of Nagasawa et al. (1990) on the initial stages of oxidation of hydrophobic surfaces [31]. Also observed in the spectra of Fig. 6.3 are Si–H stretches in the range of 2080 cm−1 , which are best explained by H-atoms bonded to unoxidized parts of the surface (i.e., to Si back-bonded to Si atoms rather than to O atoms). The high-frequency shoulder of this band (∼2140 cm−1 ) is most likely associated to Si–H stretches where some of the Si back-bonds are attached to only one O atom. If the mode at 2080 cm−1 does arise from Si–H at the Si/SiO2 interface, an interesting direction for future studies will be to determine its formation mechanism.

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Structure and Morphology of Oxidized Surfaces The work of Hahn and Henzler [32], Heyns et al. [17], and Ohmi et al. [15] has correlated electronic device properties with surface structural properties. While surface roughness is intuitively detrimental to semiconductor devices at some scale, the main contribution of this early work was to define at what scale surface roughness is important to device yield and reliability. Degradation of thin gate oxide breakdown field strengths and of channel mobilities with surface roughness on a microscopic scale is now a parameter taken into account by the industry. The morphology that a surface exhibits tends to be a function of the complete processing history experienced by the wafer; it is therefore quite complicated. The initial surface polish processes, chemical cleaning processes, thermal oxidation processes, and etching processes, all influence the surface morphology. This section begins with a discussion of substrate wafers, including chemical mechanical polishing (CMP) and epitaxy. It then considers the effects of chemical cleaning on surface morphology. Finally, future trends in controlling oxidation and interfacial structure are briefly discussed. Near atomic perfection is achieved in surface CMP. Commercial wafers exhibit a typical surface roughness on the order of 2 Å RMS (root mean square) and surface finishes produced in the laboratory have approached 1 Å RMS [33]. A scanning tunneling microscope (STM) image of such a surface is shown in Fig. 6.4. Although STM images can characterize surface roughness on length scales covering the range from 1 to 1000 Å, these surfaces are also characterized with a variety of other techniques, such as diffraction methods, spanning lengths up to 1 mm with good correlation observed on all scales [33]. The post-CMP STM image shown in Fig. 6.4 was taken subsequent to HF removal of surface oxidation, and the surface is hydrophobic and H-terminated [34]. The process to produce H-terminated surfaces is now well understood and will be discussed briefly in Sect. 6.2.3.

Fig. 6.4. Scanning tunneling microscope image of a polished Si(100) surface exhibiting 1.2 Å RMS roughness. The image was taken immediately following a HF dip. Courtesy of P.O. Hahn, Wacker-Chemitronic GmbH, Germany [35]

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Fig. 6.5. Typical scanning tunneling microscope images of Si(100) surfaces taken before (top) and after (bottom) an RCA Standard Clean (SC-1 and SC-2). Images taken after a newly developed buffered HF treatment (BHF) where the authors observed minimal increases in Si surface roughness due to the BHF [15]

Hydrogen-terminated surfaces are not as stable as oxide-terminated surfaces, and thus it is not surprising that wafer suppliers ship wafers in the hydrophilic (oxidecovered) state. Supplier polish and clean recipes are proprietary, but presumably the wafers receive something akin to an RCA clean before they are shipped. Another technique that provides atomically “perfect” surfaces uses Si molecular beam epitaxy [36], although this technique has not yet been commercialized. Under proper conditions, also surfaces formed during commercial Si epitaxial growth by chemical vapor deposition (CVD) are smoother than chemically cleaned surfaces. In 2005, asreceived CZ (Czochralski) Si and epitaxial Si substrates seemed to exhibit a surface roughness of ∼2 Å RMS [37]. The consensus is that the acidic peroxide cleans (SPM etch or SC-2) do not cause a substantial increase in the microscopic roughness of as-received wafers. The SC-1 clean (typically 5:1:1 H2 O:H2 O2 :NH4 OH at 80◦ C) on the other hand, has been found to substantially increase the surface roughness [38]. A comparison of the surface roughness of a control wafer and a wafer cleaned in a standard SC-1 process is shown in the STM images of Fig. 6.5 [15]. Control wafers exhibit a RMS roughness of

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2 Å. The SC-1 treatment more than doubles the observed roughness and repetitive SC-1 cycles can increase it by as much as a factor of 5, approaching 10 Å RMS. This roughness has been shown to decrease breakdown field strengths by as much as 30% [39] and to degrade channel mobilities by factors of 2–3 times [40]. The mechanism leading to the roughening in the basic peroxide solution is not completely understood but is related to the slow but finite Si etch rate in the SC-1 solution (∼8 Å/min at full strength at 80◦ C) [15]. The acidic peroxides, on the other hand, do not etch SiO2 and hence do not roughen the oxide surface. A proposed solution to the basic peroxide roughening problem is to reduce the etch rate by reducing the concentration of NH4 OH in the SC-1 solution [38]. The etch rate drops to 1 Å/min if the concentration of NH4 OH is decreased by a factor of 100 times. Figure 6.6 shows a plot of the measured RMS roughness as a function of NH4 OH concentration [41]. One might wonder why the industry is working so hard to keep the standard SC-1 solution when it is clearly detrimental to the surfaces. The reason is simple: SC-1 is one of the most efficient particle removal agents known. Further, the fact that the basic peroxide solution slightly etches both SiO2 and Si may be precisely why it is such an efficient particle remover. This phenomenon is being investigated in the hopes that an optimum concentration can be found to minimize damage and retain particle removal efficiency [15]. The microscopic mechanism by which the etching roughens the surface is also being investigated. It should be mentioned that etching alone does not necessarily mean that the surface roughness will be increased. Non-uniform etching is the true culprit. For example, Verhaverbeke et al. (1991) have found that the Ca concentration in SC-1 dramatically changes the degree to which the surface roughens [42]. Similar studies are needed to fully understand the mechanism of surface roughness and are the direction of future work. The exact molecular structure of these chemically grown Si/SiO2 interfaces is very difficult to deduce. Native oxide growth has been shown to occur in an extremely controlled manner [43, 44], leading to atomically ordered interfaces under the right conditions. This phenomenon appears in fact to be more general. In very careful XPS studies of surface O concentration as a function of time, layer-by-layer initial oxidation of Si has been observed [45, 46]. Layer-by-layer oxidation, of course, requires that the previous layer finish before the next layer begins oxidation and leads by necessity to the conclusion that some form of order must exist at the Si/SiO2 interface. Contamination Issues Associated with Oxidized Surfaces One of the main objectives of the development of the RCA clean was to remove organic and metal contaminants from the surface of Si wafers [21]. Although the RCA clean was developed over 40 years ago, it has functioned extremely well and is still the main clean used prior to gate oxidation as well as the initial clean in some manufacturing lines. Residual trace metal contamination at 1010 cm−2 is observed after RCA cleaning and is dependent on the quality of the chemicals used. These metals can lead to surface roughening due to a couple of different mechanisms. Metals can enhance oxidation rates and therefore increase surface etching rates non-uniformly, leading to surface roughening. Another mechanism is related to bubble formation

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Fig. 6.6. Surface roughness plotted as a function of NH4 OH concentration in a 10-min NH4 OH/H2 O2 solution treatment at 85◦ C [41]

that blocks surface reactions, again leading to increases in surface topography. Also, metals can get trapped in the oxide formed during the SC-1/SC-2 cleaning process which subsequently leads to leaky junctions and to yield and reliability problems in gate oxides [46, 47]. Ozone oxidation, sometimes with the addition of HCl, avoids metal contamination from the RCA chemicals and has been found to be an excellent way in which to grow passivating chemical oxides. Ozonated H2 O can be produced in extremely high purity and has been shown to result in high quality gate dielectrics. Another common contaminant on these oxide-covered surfaces is carbon. It is most likely incorporated in or on these surfaces in the form of hydrocarbons and can come from the chemicals, H2 O used to rinse the wafers, or from the air in the laboratory environment. Trace hydrocarbons have not proven to be detrimental to gate oxides. A predominant sentiment in the industry is that the hydrocarbons get burnt off in the O-rich high-temperature environment of the oxidation furnace. If handled improperly, however, SiC precipitates can cause weak spots in the oxides being grown [48]. Hydrocarbon contamination is much more of a concern for surface preparation prior to epitaxial growth of Si. In this case, surfaces that are completely free of contamination are needed to grow defect-free Si and C-contamination is of critical concern. The technique of desorbing the oxide at elevated temperature prior to epitaxy was first discussed by Henderson [49] in which the results showed that atomically clean surfaces with only a small amount of C residue could be obtained after the RCA standard clean. Ishizaka, Nakagawa, and Shiraki [50] reduced the level of C entrained in the oxide by repetitively immersing the wafers in boiling HNO3 acid followed by HF, ending with a concentrated SC-2 type of clean (4:1:1 HCl:H2 O2 :H2 O at 90–100◦ C). Another efficient technique to remove hydrocarbons is exposure to UV/O3 (ultraviolet/ozone) [51].

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Some contaminants, such as S and Cl, can originate directly from the solution used during the chemical oxidation. Sulfur and Cl have been observed from the SPM and SC-2 cleaning solutions, respectively. Fluorine, on the other hand, has been observed when the chemical oxidation is preceded by a HF treatment. In this case, F is found to segregate at the Si/SiO2 interface [52]. 6.2.3 Si Cleans Leading to Hydrogen-Terminated Silicon Surfaces Mechanism of Hydrogen Termination The original belief that HF etching leads to F termination of the Si was based on the stability of the Si–F bonds and the accepted explanation of the mechanism for SiO2 dissolution leading to F-terminated Si. In its simplest form, the dissolution of SiO2 by HF can be depicted by the following reaction: SiO2 + 4HF → SiF4 + 2H2 O.

(6.1)

Notice that the above reaction involves HF molecules and not F− ions in the solution. HF is a weak acid with an equilibrium constant such that it does not dissociate readily in concentrated solutions [53]. Moreover, Judge [53] showed that, even if F− ions are available, they give an etching rate which is negligible compared to HF and HF2− species. Thus, only HF in its associated form needs to be considered in the dissolution mechanism. HF molecules attack Si–O bonds by inserting themselves between the Si and O atoms. This reaction is depicted schematically in Fig. 6.7(a) as if it were the last Si–O bond to be broken before reaching the Si substrate. This insertion occurs with a low activation barrier because the reaction is highly exothermic and conserves the number of broken and reformed bonds. The reaction is also greatly facilitated by the highly polar nature of the Si–O bond, which the highly polar HF molecule can use to its advantage during attack. The Coulomb attraction naturally leads to having the positively charged H ion associated with the negatively charged O ion, and the negatively charged F ion associated with the positively charged Si ion of the Si–O bond. This liberates H2 O into the solution and leaves Si–F in its place on the surface (Fig. 6.7(b)). The Si–F bond (∼6 eV) is the strongest single bond known in chemistry. In comparison, the bond strength of the Si–H is only ∼3.5 eV so that, based on these thermodynamic considerations, the F-terminated surface must be more stable than the H-terminated surface. Ubara, Imura, and Hiraki (1984) were the first to recognize that the Si–F bond must be highly polar because of the large electronegativity difference between these atoms. Hence, the Si–F bond causes bond polarization of the associated Si–Si backbond allowing HF attack of the back-bond, as illustrated in Fig. 6.7(c). This kinetically favorable pathway results in the release of stable SiFx species into the solution, leaving Si–H behind on the surface as shown in Fig. 6.7(d). The validity of this proposed pathway was confirmed using first principles molecular orbital calculations of the activation energies of these types of reactions on model compounds by Trucks et al. [12]. In these calculations, an activation energy of ∼1.0 eV was found for reactions shown in Fig. 6.7(c). The reaction barrier is lowered by the charge transfer

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Fig. 6.7. Schematic representation of Si etching and H passivation by HF

between the Si and F atoms, as originally suggested by Ubara et al. [54]. In the absence of charge transfer, as is the case for the nonpolar Si–H bonds, the activation energy of the Si–Si back-bond attack is 1.6 eV, which is 0.6 eV higher in energy than for that of fluorinated Si species. The impact of the Coulomb interaction could also be observed by inverting the HF molecule, making the attack occur in opposition to the Coulomb force. In that case, an activation energy of 1.4 eV is obtained. In summary, HF attacks polar species very effectively but is much less effective against nonpolar species. The attack requires a specific orientation of the reactant atom to take advantage of the Coulomb interaction between the positively and negatively charged atoms. These concepts provide a basis to understand why H (and not F) terminates the Si dangling bonds after HF solution etching and why HF dissolves oxide so readily but leaves the Si relatively untouched. The preceding arguments give a basic understanding of HF etching. In reality, however, the situation is much more complex because (a) HF, HF2− , F− , H3 O− , OH− , and NH4 F species may coexist together in solution, in chemical equilibrium with one another; (b) steric constraints can play a role at the surface; and (c) solvation effects can affect reaction kinetics. The calculations mentioned above were performed for molecules in “free space” and thus can only accurately describe gas phase reactions. In vapor processes, however, H2 O vapor is needed to initiate SiO2 etching reactions with anhydrous HF [55]. In general, the main effect of placing the polar HF molecule into H2 O is to surround it, on the average, with H2 O molecules in the proper orientation to minimize the Coulomb energy. This, in turn, weakens the HF bond, facilitating all HF reactions that must break the HF bond. Therefore, it is reasonable to assume that solvation simply lowers the activation energy barriers that exist for the gas phase reactions described above. For instance, HF dissolution of SiO2 has an activation energy of approximately 0.35 eV [53] compared with the 0.55 eV calculated for the gas phase reaction [12]. The heat of solvation to place an HF molecule into solution is ∼0.4 eV, which is consistent with the observed 0.2 eV lowering of the energy barrier. This reasoning rationalizes the HF and HF2− etching behavior observed by Judge (1971) [53]. HF2− can be thought of as a more highly solvated form of HF with a weaker bond strength that explains the lower activation energy for SiO2 dissolution (0.31 eV) as well as the increased rate of dissolution

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(factor of 4–5). The role of steric hindrance at the surface is also important. Consequently, the chemical trends discussed above provide a guide, but cannot be used to obtain exact activation energies, since modifications due to steric constraints or solvation can be expected. HF solution chemistry is also affected by the OH− concentration [18]. Experiments show that H2 O rinsing alone can remove dihydride species at steps [18, 56], leading to monohydride termination on Si(111) surfaces [56]. This observation is consistent with the fact that samples etched in HF remain hydrophobic even after boiling in H2 O for extended periods of time [57]. Similarly, CMP Si wafers (polished in slurries with pH ∼13) are hydrophobic and are terminated with H [34]. These observations suggest that Si surface reactions with OH− can also lead to hydrophobic H-terminated Si surfaces once the surface oxide is removed and that HF and OH− chemistry can remove Si atoms bonded to electronegative elements by back-bond attack of the polarized Si–Si bond. It is also interesting to note that HF and OH− in solution may have similarities in their reaction pathways at the surface. Structure and Morphology of Hydrogen-Terminated Silicon Surfaces Hahn and Henzler [32] in 1984 first provided information on the morphology of H-terminated Si(100) and Si(111) using low energy electron diffraction (LEED). Next, Grundner and Schulz [58] used electron energy loss spectroscopy (EELS) on HF-treated Si(111) and Si(100) to investigate the nature of the H-termination. They found that Si(100) was dihydride terminated (with a characteristic SiH2 scissor vibration at 900 cm−1 ) and Si(111) was monohydride terminated. This finding together with the observation of a LEED pattern [35] led to the conclusion that a uniform dihydride phase was obtained. For HF-etched Si(111) surfaces, the strong Si–H stretch loss at 2080 cm−1 together with the high quality 1 × 1 LEED pattern [35], suggested that the surface was ideally monohydride-terminated. A weak loss at 900 cm−1 was attributed to dihydride at steps. Soon thereafter, high-resolution IR reflection absorption spectroscopy revealed that, contrary to the conclusions drawn from EELS, Si(100) and Si(111) surfaces are atomically rough after similar etching treatments, as evidenced by complex IR absorption spectra with contributions from mono-, di-, and tri-hydrides, as schematically shown in Fig. 6.8. The spectra of Si(100) surfaces also show that the HF-etched surfaces are much more complex than atomically flat, Hterminated surfaces. Structural information was extracted by providing complete assignments of the observed bands, using isotopic substitution experiments combined with force constant normal mode analyses on model compounds [59]. In summary, etching in dilute HF leads to atomically rough surfaces. Mono-, di-, and trihydrides coexist on both Si(100) and Si(111) surfaces. STM images of Si(111) [60] show structures of 10–20 Å diameter and 3 Å in height, accounting for about 50% of the surface (i.e., ∼50% remains monohydride terminated) consistent with the IR data.

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Fig. 6.8. Schematic representation of possible surface structures on the Si(111) surface with their associated H termination. The ideal monohydride and trihydride termination are possible for an atomically flat (111) plane. The “horizontal” dihydride (D) terminates the corner of a small adstructure where an isolated monohydride (M ) may exist. Both the “vertical” dihydride (D ) and coupled monohydride (M) can terminate larger structures of the type shown here. These are all the possible structures that do not involve surface reconstruction [59]

Si(100) Etched in Buffered HF Solutions Buffered HF (BHF) is composed of various mixtures of 50 wt% HF in H2 O and 40 wt% NH4 F in H2 O. A common mixture used in the industry is 7:1 buffered HF, which has a pH = 4.5 and is composed of 7 parts of NH4 F and 1 part of HF. The main difference between aqueous HF and buffered HF is the solution pH, which is the object of the following discussion. Raising the pH of the HF solution increases the etch rate of the H-terminated Si surfaces. Infrared absorption data clearly show that the morphology of chemically prepared Si(100) surfaces changes as the pH of the etching solution varies from 2–8 [61]. For a pH = 2, the IR absorption spectra are dominated by dihydrides with other hydrides present, consistent with an atomically rough surface. In buffered HF (pH ∼5), the spectrum sharpens and is dominated by coupled monohydrides, suggesting the formation of (111) microfacets on the Si(100) surface [18, 61]. For higher pH values, the etching proceeds quickly, as evidenced by the gas bubbles forming at the sample surface. After etching in a NH4 F solution (pH = 7.8), dihydride contributions are again dominant. However, the polarization of this mode is quite different from the pH = 2 spectra. In this case, the symmetric stretch (2105 cm−1 ) is polarized normal to the surface and the anti-symmetric stretch (2112 cm−1 ) is polarized parallel to the surface. Although these polarizations would be correct for terrace dihydrides, these surfaces are not believed to be atomically flat because of the existence of strong spectral contributions from mono- and tri-hydrides. Furthermore, the monohydride spectrum is now centered at ∼2085 cm−1 , indicating the growth of (111) facets. After several etching cycles, the evolution of the IR spectra suggests that (111) facets develop in solutions of high pH. Both isolated and coupled monohydrides

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Fig. 6.9. Atomic force microscope images of (a) a CMP Si(100) control wafer (∼2 Å RMS) and (b) a Si(100) wafer etched in 7:1 buffered HF solution for 10 min (∼5 Å RMS) [J. Sapjeta, unpublished]

have symmetric stretches pointing away from the normal of the macroscopic surface plane. In contrast, the dihydride modes are characteristic of dihydrides with their axes pointing along the surface normal. The simplest atomic arrangement consistent with these observations is a distribution of tent-like structures with a row of dihydrides at the rooftop, (111) facets terminated with ideal monohydrides on the sides and coupled monohydrides at the periphery of the facets. Since the facets are small, the concentration of coupled monohydrides is as high as that of ideal monohydrides. The use of buffered HF may be ill advised in attempting to prepare atomically flat (100) surfaces, since (111) facets develop upon etching. Increased surface roughness has been directly observed after buffered HF etching using atomic force microscopy (AFM) [41]. As shown in Fig. 6.9, a control wafer is relatively smooth with ∼2 Å RMS roughness, whereas a wafer treated in buffered HF is characterized by ∼5 Å RMS roughness. To improve the atomic flatness of Si(100) surfaces, a thermal oxidation treatment is highly desirable because it is known to result in high-quality Si/SiO2 interfaces. In summary, Si(100) surfaces are microscopically rough when treated in either dilute or concentrated HF. These surfaces are macroscopically roughened by buffered HF solutions due to (111) facet formation. To date, little is known about the nature of such surfaces and its impact on IC device performance. The potential impact on the quality of subsequent interfaces formed after further processing will motivate future work in this area. Si(111) Etched in Buffered HF Solutions For the Si(111) surfaces, increasing the pH of the solution makes it possible to flatten the surface on an atomic scale thanks to preferential etching of the H-terminated surfaces [18], as reflected in the IR absorption spectra. For instance, Fig. 6.10 shows the difference between a Si(111) surface etched in dilute HF and buffered (pH ∼8) HF solutions (i.e., 40 wt% NH4 F). While the dilute HF etched surface is atomically rough (Fig. 6.10(a)) with all forms of hydrides, the surface etched in a 40 wt% NH4 F

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Fig. 6.10. P-polarized IR absorption spectra of Si(111) after (a) etching in dilute HF (pH = 2), and (b) a 40% NH4 F solution (pH = 7.8) [61, 65, 66]

solution is characterized by a single sharp infrared absorption line at 2083.7 cm−1 , polarized perpendicular to the surface (Fig. 6.10(b)). The obvious implication is that atomically flat surfaces have been obtained with ideal monohydride termination. The measured linewidth, ν of ∼0.9 cm−1 , is the narrowest line ever measured for a chemisorbed atom or molecule on a surface at room temperature [18]. A substantial contribution to the width is due to thermal broadening. Low temperature measurements have shown that most of the linewidth measured at room temperature was thermally induced, due to an harmonic coupling of the Si–H stretch mode to surface Si phonons [62]. At present, the best samples are characterized by an extremely small (0.05 cm−1 ) inhomogeneous broadening [63, 64]. The LEED patterns obtained after careful introduction into UHV show a 1 × 1 pattern with resolution limited integral order spots and a background below the detection limit of conventional LEED systems (Fig. 6.11). This unreconstructed and ideally H-terminated surface is often referred to as the H/Si(111) (1 × 1). STM images [67, 68], such as the one shown in Fig. 6.12, have confirmed that the surface is nearly contamination free (<1 ML), atomically flat, and well ordered with 1 × 1 (3.84 Å) periodicity. The electronic structure obtained from (dl/dV ) measurements displays no states in the gap, as expected for a H-covered surface. Further support for the bulk-like character and the ideal monohydride termination comes from electron-stimulated desorption experiments [69] showing the formation of the π-bonded chains (2 × 1) reconstruction after the H is desorbed. This surface has also been imaged with an atomic force microscope (AFM), confirming the 1 × 1 periodicity [70]. EELS studies of the H/Si(111) (1 × 1) show a very high specular beam intensity and a low background [72]. The dispersion of both the Si phonons and the H vibrations has been measured [65, 73] in good agreement with the calculated values for an unreconstructed surface [74].

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Fig. 6.11. Photographs of LEED patterns of Si(111) surface after NH4 F treatment: (a) 82 eV, and (b) 125 eV [67]

Fig. 6.12. STM images of Si(111) surfaces miscut by 0.3◦ toward the (112) direction: (a) Surface etched in buffered HF for 2 min under ambient conditions. This morphology reflects the roughness of the original Si/SiO2 interface. (b) Surface etched in quiescent 40 wt% NH4 F (aq) in a N2 ambient. (c) Surface etched in stirred 40 wt% NH4 F (aq) in an O2 ambient. Dissolved O2 leads to increased pit nucleation and rougher etched surface (after [71])

High-resolution IR absorption spectra recorded at low temperatures (<50 K) have also been used to characterize the extent of the perfect 1 × 1 domains [63, 64]. Below 50 K, both the line broadening due to lifetime (∼0.005 cm−1 ) [75] and phonons (<0.001 cm−1 ) [62] are negligible compared to the measured linewidth (0.07 cm−1 ) (Fig. 6.13). After deconvolution of the resolution function (0.04 cm−1 ), the natural linewidth (0.05 cm−1 ) and the line shape are obtained and can be related directly to surface inhomogeneities. In considering the line shapes, Jakob et al. [63] pointed out that a distribution of point defects leads to a symmetrical broadening (such as Lorentzian or Gaussian), whereas the presence of finite domains leads to an asymmetric broadening. Effects associated with dipole coupling between the H atoms dominate this asymmetry. For a finite domain containing N atoms, there are N normal modes. The strongest IR active mode is the in-phase normal mode. This normal mode is at the highest frequency,

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Fig. 6.13. P-polarized IR absorption spectra of H/Si(111) (1 × 1) prepared by: (a) thermal oxidation followed by etching in buffered HF (pH ∼5) for 2 min and subsequent etching in 40 wt% NH4 F for 4 min, and (b) chemical oxidation followed by etching in a 40 wt% NH4 F solution for 6 min. Both samples were thoroughly rinsed in deionized (DI) H2 O after the last etching step [64]

and this frequency increases with domain size because Si–H is oriented perpendicular to the surface. The other normal modes have a weaker IR cross-section (∼3–5% of the in-phase mode) leading to a low-frequency tail to the absorption band. Furthermore, the measured absorption associated with a distribution of domain sizes is proportional to P (N) × N, where P (N) is the distribution function (the larger domains contribute more to the absorption). Therefore, a symmetric distribution of domain sizes leads to an asymmetric absorption line shape, characterized by a lowfrequency tail for the Si–H system. When both effects are taken into account, the line shape of Fig. 6.13(a) can be well fit with N = 2 × 104 Si–H units distributed with a 30% spread of domain sizes [63]. STM images show that the average linear terrace size is 500 Å on Si(111) surfaces in excellent agreement with the IR absorption line shape analysis (∼600 Å) [76]. STM images of NH4 F-etched Si(111) surfaces show a wide variation in pit densities. The origin of these variations was first elucidated by Wade and Chidsey [77], who showed that a low concentration (∼ppm, parts per million) of dissolved O2 in the etchant would lead to etch pit nucleation. Once nucleated, these pits grow and lead to rougher etched surfaces characterized by equilateral triangular pit shapes. In a pure O2 ambient, dissolved O2 leads to pronounced roughening as shown in Fig. 6.12(c) [78]. The sensitivity of the IR absorption technique makes it possible to investigate various preparation procedures, such as the influence of oxidation prior to HF etching. For instance, a comparative study of (a) stripping the thick thermal oxide in buffered HF (pH = 5) followed by immersion into a 40 wt%-NH4 F solution for 4 min, and (b) stripping a chemical oxide prepared by SC-2 followed by immersion into 40 wt%-NH4 F solution for 6 min shows a measurable difference in perfection,

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as summarized in Fig. 6.13. Thermally grown oxides result in a smoother interface than chemically grown oxides. It is well known that, when a thick thermal oxide (∼1000 Å) is grown with postannealing in an inert gas at the growth temperature of ∼1050◦ C, a very smooth Si/SiO2 interface is formed [16, 32, 44, 79]. The nature of the interface can be investigated further by treatment in concentrated HF since etching of the H-terminated Si is minimized. For instance, dissolution of the above oxide in concentrated HF produces a H-terminated Si(111) surface, characterized by a multimode spectrum, which indicates atomic roughness, as shown in Fig. 6.14, top (a). As shown in Fig. 6.14, top (b), this roughness disappears upon rinsing, which is evidenced by the dominance of the monohydride peak afterwards. In contrast, the rough Si(111) surface produced by HF etching of a chemical oxide is not removed upon simple rinsing. These observations confirm that the thermally grown oxide has a smoother interface than the chemically grown oxide and suggests that H2 O rinsing alone can remove small surface defects preferentially. Identical experiments were also performed on Si(100) surfaces and are shown in Fig. 6.14, bottom spectra. As discussed earlier, the multi-mode spectra imply that the surfaces are atomically rough. However, certain spectral changes do occur after rinsing. The monohydride modes decrease in strength while the dihydride modes increase. Preferential etching by H2 O, resulting in flat H-terminated Si(111) surfaces, has been demonstrated by Watanabe et al. [56]. These authors studied the effects of H2 O rinsing as a function of H2 O temperature, finding that hot H2 O (100◦ C) increases the rate of removal of (111) surface defects while maintaining the H-termination. The spectrum obtained is shown in Fig. 6.15. A single mode, polarized perpendicular to the surface, dominates the spectrum. However, using the analysis developed by Jakob et al. [63], the spectra indicate that the average domain size is 20 Å, a factor of 15 smaller than for the sample presented in Fig. 6.13(a). It is surprising that boiling H2 O rinsing did not lead to the growth of a surface oxide. A possible mechanism is discussed in the following section. Mechanism of Preferential Etching A solution of concentrated HF dissolves SiO2 efficiently and passivates the Si surface with H. Once H-passivation is achieved, etching stops. As a result, the morphology of the original Si/SiO2 interface is preserved. The data presented in the previous section indicates that dilution of concentrated HF with H2 O or buffering with NH4 F induces a slow etching reaction of the H-passivated Si surfaces. The overall etching rate increases with the pH of the solution, as evidenced by the increasing formation of small H2 bubbles as the pH is raised. The H2 bubbles are probably formed during oxidation of the surface by OH− , according to the following reaction: ≡Si–H + OH− → Si–O− + H2 .

(6.2)

Once oxidized, the surface is subject to HF attack through HF insertion into the Si–O bond, according to the schematic reaction:

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Fig. 6.14. Top: P-polarized IR absorption spectra of thermally oxidized Si(111) after (a) etching in concentrated HF, and (b) subsequent rinsing in DI H2 O. Bottom: P-polarized IR absorption spectra of thermally oxidized Si(100) after (a) etching in a concentrated HF solution, and (b) subsequent rinsing in DI H2 O

≡Si–O− + HF → Si–F + HO−

(6.3)

with subsequent removal of the surface Si atom (now labeled Si* to distinguish it from the underlying bulk Si atoms), and passivation of the second layer Si atoms by H, according to the mechanism proposed above: (3Si) ≡ Si∗ –F + 3HF → 3(Si–H) + Si∗ F4 .

(6.4)

In these processes, the last two steps are fast compared to the initial oxidation of the H-passivated surface. As a result, the surface is always H-terminated. The role of OH− is clearly a key ingredient in the attack and etching of Hterminated Si surfaces. It is also important to note that Si can be etched without HF. Silicon can also be etched with alkaline solutions, such as KOH or NaOH [80, 81] and even with H2 O [56]. These observations indicate that, once oxidized, the Si surface can be attacked by OH− . A plausible reaction pathway involves the Si back-bond attack by OH− :

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Fig. 6.15. Polarized IR absorption spectra of a chemically oxidized Si(111) sample after etching in 1.5 wt% HF solution and subsequent boiling in Dl H2 O at 100◦ C for 10 min. The resolution is 0.5 cm−1 [56]

(3Si) ≡ Si∗ –O− + OH− + 2H2 O → (3Si–H) + Si∗ (OH)2 O2 2− .

(6.5)

Confirmation and quantification of the above reaction steps should be possible using first principles cluster calculations, as was done to understand H-passivation of Si [82, 12]. In addition, the influence of surface charges on the anisotropic etching of Si needs to be understood [83]. The key point in considering preferential etching is to realize that oxidation of the H-terminated Si surface is extremely slow and is the rate-determining step. It takes many collisions between OH− ions and the surface Si–H to effect a reaction because the reaction barrier is large. When this is the case, relatively minor factors may affect the reaction probabilities greatly. For instance, if some surface structures are strained, they may be more easily attacked because the reaction barrier is lowered (even a small change is important because it is in the exponential term). Alternatively, if a surface structure is more accessible for the OH− ion in solution, it may be attacked faster because of an increased reaction probability (larger prefactor). To understand and quantify the etch rates of various surface structures, the chemical etching of stepped Si(111) surfaces was studied by Jakob and Chabal [63] by utilizing IR absorption spectroscopy and STM images to characterize the surface structures after each chemical treatment. The results are summarized in the schematic drawing of Fig. 6.16 [84]. At low pH (pH = 1–3), the HF solutions do not modify substantially the original Si/SiO2 interface, which usually displays a fair degree of atomic roughness. The (111) terraces have many small adstructures and the more extended steps are wandering with a high density of kinks. As the pH is increased (pH = 5–6), the small adstructures and steps present on the (111) terraces are etched away, leaving atomically flat, ideally monohydride-terminated (111) terraces. The step edges, however, remain rough on an atomic scale with a high concentration of

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Fig. 6.16. Schematic picture of the changes of the Si(111) surface morphology as the etch rate is increased by increasing the pH of the etching solution: (a) pH < 3, (b) pH = 5–6, and (c) pH = 6.6. A total etch time of 3 min, including the removal of approximately 10 Å SiO2 , is assumed. A pH higher than 6.6 leads to step bunching, and therefore to the formation of multiple steps and facets (not shown here) [84]

kinks. Solutions of higher pH (pH ∼ 6.6) are needed to remove kinks and generate atomically straight steps. After 3 min of etching at room temperature in a solution of pH = 6.6, for instance, the steps are observed to be straight with ∼1% of the step sites with kinks, which is probably accounted for by the imperfection in the azimuth of the miscut. The above observations indicate a step flow etching mechanism [68]. The etching of stepped surfaces increases drastically as the pH is increased beyond 7.0. This is evidenced by a large formation of bubbles. The surface then roughens, partly because of step bunching [81] and partly because of the more inhomogeneous conditions at the surface (bubbles, fluctuation in the concentrations of various chemical species, etc.). The result is the formation of large, three-dimensional roughness as evident in STM images [76]. The site-specificity of NH4 F etching reactions was quantified using a combination of infrared spectroscopy, scanning tunneling microscopy, and kinetic Monte Carlo simulations [20]. As expected, this analysis confirms that NH4 F is a highly anisotropic etchant, which attacks all defect sites (e.g., step sites) at least 5000 times more rapidly than terrace sites (i.e., sites on the flat terraces). The most reactive site, the kink site, is at least 107 times more reactive than the least reactive site, the terrace site. The correlation between the structure and reactivity of the various sites provides insight into the reaction mechanism. The observed trends in reactivity are consistent with a reaction that is rate-limited by a pentavalent transition state, as first proposed by Hines et al. [85]. For example, the rigid, tetrahedral geometry of the terrace and monohydride step sites leads to a

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relatively low etch rate. In contrast, the highly strained kink site, which is held in a near-pentavalent geometry, reacts much more rapidly. In short, the reactivity of the surface appears to be dominated by structural considerations. The chemistry on these surfaces is obviously complex. The simple mechanisms described above are meant only to give a framework in which to address the problem. The etching reactions are also surprisingly sensitive to inhomogeneities in the etchant [86], as well as ppm levels of contamination. The kinetics and reactions of HF etching are highly dependent on the substrate. For instance, for germanium surfaces, it has not been possible to date to prepare atomically flat H-terminated Ge(111) surfaces, probably due to unfavorable etching kinetics. 6.2.4 Microscopic Origin of Silicon Oxidation The previous sections have dealt with oxidized or H-terminated surfaces. It is important to understand how oxides are formed if the nature of ultra thin oxides is to be controlled. This section addresses the process of oxygen incorporation into silicon for a variety of starting surfaces, including perfectly clean, unpassivated surfaces (prepared in ultra-high vacuum) and H-terminated surfaces, when exposed to aqueous solutions, air, or controlled gaseous environments. Oxidation Regimes for Si Surfaces with and without Termination of the Surface Dangling Bonds Many factors influence the oxidation of clean and H-terminated silicon surfaces (i.e., with and without dangling bonds): thermodynamic drive for oxygen agglomeration, kinetic barriers to oxygen surface and bulk diffusion, pathways for oxygen decomposition, and strain of silicon oxide in the vicinity of crystalline silicon. It is, therefore, not surprising that several regimes can be identified, even for the simple oxidation of clean silicon in an ultra-high vacuum environment. Regime 1: Oxygen Insertion into Near Surface Silicon Layer (Top Two Silicon Layers) Both O2 and H2 O oxidation of clean, unpassivated silicon have been studied. The reactants readily dissociate: O2 into a silanone configuration [87] and H2 O into OH and H [88], forming metastable structures. Annealing studies clearly show that there is a thermodynamic driving force for oxygen to insert into the back-bonds of the surface silicon atoms and to agglomerate into atomic scale clusters with three oxygen atoms bound to a surface silicon atom. The presence of hydrogen atoms in the case of H2 O dissociation only affects the kinetics of migration [89]. Oxidation of deeper layers (below the top two layers) requires higher activation energies. Consequently, the first regime of oxidation is characterized by a highly inhomogeneous process, driven by thermodynamics and controlled by kinetic (and chemical) factors. Oxidation of hydrogen-passivated silicon surfaces is emerging as an industrially critical area [90]. In general, the barriers for oxygen insertion are much higher, particularly for H2 O oxidation [13, 89], and the surface oxide structures are stabilized by

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hydrogen in a manner similar to the case of H2 O oxidation of clean Si. But the nature of the oxidation is similar, with formation of highly oxygen-coordinated structures involving only the top two layers, as discussed in the next section. For both clean and H-terminated silicon oxidation, the complete layer growth is achieved by two-dimensional oxide island nucleation [91]. As the oxidation nears completion, strain begins to play a role and affect the nature of the oxidation at the Si/SiO2 interface. Regime 2: Layer-by-Layer Oxidation (Beyond the Top Two Si Layers) After the surface oxide layer on unpassivated silicon becomes continuous (∼5 Å thick), Hattori has shown using high resolution XPS that there is a periodic variation of the observed silicon oxidation state as oxidation proceeds with a period ∼7 Å [90]. This observation indicates that oxidation occurs at the Si/SiO2 interface and proceeds layer-by-layer. This behavior extends at least to the first 20 Å of oxide, a depth accessible to XPS. Diffusion of oxygen to the Si/SiO2 interface with subsequent oxidation has been unambiguously demonstrated by medium energy ion scattering (MEIS) studies [92] using isotopic markers (18 O). If a thin oxide involving only 16 O (i.e., Si16 O2 ) is further oxidized using only 18 O, the isotopic species 18 O is only found at the Si/SiO2 interface (and a small amount at the upper surface) with no detectable 18 O inside the original oxide film, confirming the oxygen diffusion through the oxide and reaction only at the lower interface. The presence of a small amount of 18 O at the upper surface may simply reflect isotopic exchange or point to surface reaction as a requirement for subsequent atomic oxygen diffusion. In this ultra-thin oxide film regime, the pressure dependence of the evolution of the 18 O peaks in MEIS is found to be distinctly slower than the linear dependence observed for the thicker oxide film regime, characterized by a Deal–Grove behavior. 6.2.5 Initial Oxidation of Hydrogen-Terminated Silicon We focus here on the initial oxidation of H-terminated Si surfaces (regime 1). This regime is particularly important to understand because epitaxially grown Si and SiGe source/drains, introduced into manufacturing for the 90-nm node, require Hpassivations that not only cover 100% of the surface but survive long enough to meet manufacturing queue time requirements at various stages of processing. Much of the material below summarizes the content of a previous review article [93]. The barriers to oxidation of H-passivated surfaces are higher than for clean (dangling bond terminated) surfaces. In environments of pure O2 , N2 , or H2 O, the surface is characterized by a low reactivity requiring high exposures and relatively high temperatures to initiate oxidation. To study the oxidation mechanism, it is therefore important to determine the impact of (a) chemical and structural surface defects, and (b) impurities in the reactant, as such imperfections might lead to dramatically higher reactivity. These issues have been addressed by using (a) surfaces with different defect types and densities, and (b) high purity reactants.

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We first summarize results on the interaction of H/Si with liquid H2 O, since a H2 O rinse is an inherent part of Si processing. Also, comparison of wet and dry reactivity of H/Si will ultimately aid in a full mechanistic understanding of oxidation. We then highlight high-purity gas phase studies involving O2 and H2 O, which are the most relevant oxidants in high-κ gate oxide processes. Kinetics and activation energy barriers extracted from these studies can then be invoked to model oxidation and ALD growth. We include a brief review of ambient oxidation studies. Such results are not only important to assess the impact of H/Si contact with clean room environments, but on a fundamental level also help to understand the mechanistic impact of impurities such as H2 O in O2 vapor. Aqueous Chemistry of Hydrogen-Terminated Silicon and the Role of Dissolved Oxygen The aqueous chemistry of H/Si depends on Si surface orientation, on H2 O pH, and on the concentration of dissolved O2 , as reviewed by Henderson [94]. We only outline here the cooperative effects involving H2 O and O2 , as this may aid in the understanding of gas-phase oxidation. Ultrapure H2 O (UPW), containing only ppb (parts per billion) amounts of O2 , can etch oxide-free Si surfaces. Etching likely occurs via successive hydroxylation of Si atoms until they are dissolved in the form of Si(OH)4 [95, 96]. Hydroxide (OH− ) ions probably play the dominant role in the hydroxylation/oxidation process, [97] similar to the case of HF(aq) and NH4 F(aq) etching of Si surfaces [98]. For H2 O at room temperature and neutral pH, quantum chemical calculations indicate that a H/Si(100) surface site is at least 1018 times more likely to react with OH− than with H2 O [99]. Ultimately, etching by boiling H2 O results in atomically flat H/Si(111) with triangular etch pits (likely due to continued oxidation by trace O2 ) [95, 96], and in substantially rougher H/Si(100) with pits exposing (111) facets [100]. These differences in morphology have been attributed to preferential OH− attack of the more polarizable Si atoms of Si–H2 and Si–H3 structures at kinks and steps [97, 100]. In view of the proposed etching mechanism, oxidation by OH− should determine the overall etching rate. However, in the presence of dissolved O2 , the relative reaction rates depend on the relative concentrations of O2 and of OH− , and thus on pH [97]. At O2 concentrations in the ppm regime, the oxidation rate exceeds the etch rate, and hence SiO2 grows [45, 101, 102]. The detailed mechanism of H2 O-induced oxidation is not fully understood. However, there is some evidence for a cooperative (e.g., catalytic) effect between the H2 O and the dissolved O2 . In a study utilizing isotopically marked oxygen in H2 O, it was shown that at least 85% of the O incorporated into a 5–7-Å-thick oxide formed at room temperature originates from the H2 O and not from the dissolved O2 . This was taken as an indication that O2 activates the H/Si surface or acts as a catalyst for H2 O oxidation of Si, rather than oxidizing substantial amounts of Si itself. The possibility of isotopic exchange between H2 18 O and 16 O2 or Si16 O2 formed from 16 O2 was not discussed. Rather, the authors proposed that the role of the dissolved OH− /O2 couple is to anodically polarize the

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electrode, driving the H2 O oxidation reaction [103]. Water-induced oxidation of Pdoped n+ -Si proceeds dramatically faster than for n− or p+ -Si, supporting a surface electric-field-assisted oxidation mechanism [45, 101]. However, at doping levels of 1020 atoms/cm3 , chemical effects (e.g., catalysis) due to the dopant atoms may also have to be considered. A very detailed mechanistic picture of the initial stage of H/Si oxidation by O2 -containing H2 O has been proposed by Cerofolini et al. [104]. They suggest that H2 O rapidly attacks the low concentration of F impurities on HF-etched Si, thus forming OH groups. It is speculated that such sites then trap thermal excitons, i.e., bond electron–hole pairs, leading to Si–Si back-bond cleavage and thus to the formation of surface Si− and subsurface Si+ . The subsurface Si+ then bonds molecular H2 O in the form of a Lewis acid-base adduct, while the surface Si− ionizes dissolved O2 and reacts with it, forming SiOO− . Proton transfer from the H2 O adduct to the SiOO− results in Si–OH (silanol) and Si–OOH [104]. In this largely speculative model, O2 acts as a necessary ingredient for subsurface hydroxylation, and thus ultimately for the formation of Si–O–Si bridges via silanol condensation. However, direct evidence for these reaction steps is not available. In conclusion, O2 -enhanced oxidation appears to occur through a cooperative effect involving H2 O and/or OH− and O2 . As discussed below, similar phenomena may be operative in gas-phase oxidation of H/Si. Details of the mechanism are still unclear, however, largely for lack of in situ studies. Oxygen and Air Interaction with Hydrogen-Terminated Silicon Surfaces Early experimental studies of H/Si oxidation by O2 were done in ultra-high vacuum (UHV), i.e., in the low-pressure adsorption regime. At temperatures below the onset of recombinative H2 desorption (∼600 K) on H/Si(100) [105], there is no noticeable reaction at exposures in the Langmuir regime (1 Langmuir = 1 L = 10−6 Torr-sec). Work performed on a number of H/Si surfaces prepared in UHV by atomic H exposure of well-defined Si reconstructions, e.g., for mono- and dihydride H/Si(100), both flat and vicinal, and for H/Si(311) surfaces [105, 106], showed that room temperature O2 exposures in the 1000-L regime did not result in observable OH formation or in the formation of any oxide film exceeding an estimated 0.7 Å in thickness. There is no observable reactivity enhancement by steps. Dangling bonds appear to be needed for oxidation in this exposure regime. The initial room temperature sticking coefficient of O2 on HF-etched Si(100) was determined to be 10−12 , according to Westermann et al. [107] and Kawamura et al. [108]. Even lower sticking coefficients emerge from studies by Morita et al. [45], who detected less than 1 Å SiO2 after 1 week of 4:1 N2 :O2 exposure at 1 Torr (∼1014 L O2 ); and by Niwano et al. [109], who found that complete surface oxidation in 1 Torr O2 required an exposure of 1015 L, as detected by in situ IR spectroscopy. All these results point to the potential role of impurities, such as H2 O, in initial surface oxidation of H-terminated surfaces.

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As is the case for H2 O oxidation, atomic-scale information on the O2 oxidation mechanism is scarce. Only Cerofolini et al. speculated on an oxidation scheme by O2 or dry air [104]. They argued that O2 molecules dissolved in the water used to rinse HF-etched Si can react with Si− sites that are negatively polarized through interaction with H2 O. On longer time scales, reaction was also suggested to occur through O2 ionization by Si− , which is created by trapping of a thermally generated exciton. This would explain why the apparent activation energy for oxidation in the initial stage is close to the exciton energy and hence to the Si band gap of ∼1 eV. Photoinduced mechanisms have also been considered. Photon-stimulated H desorption [110] and formation of reactive O radicals in the O2 gas [111] have been identified as relevant H/Si oxidation channels in the presence of UV light. Using intense ultrashort laser pulses, even visible or near-IR light can accelerate oxidation of H/Si(111) [112], suggesting that electron–hole pairs play a key role in promoting oxidation. The H/Si reactivity to O2 is clearly higher at elevated temperatures more relevant for ALD growth of gate oxides. A comprehensive investigation by in situ IR spectroscopy and XPS [90, 113] showed that only ∼109 L dry O2 was required to almost completely oxidize atomically flat H/Si(100) (2 × 1) (prepared by a H2 anneal) and H/Si(111) (1 × 1) (from a NH4 F wet etch). On H/Si(111), the growth was predominantly lateral in nature, while on H/Si(100) both lateral and vertical growth occurred and the area density of oxide patches was higher. An in situ microscopic study in UHV has brought mechanistic insight into how the initial ML oxidation may proceed at elevated temperatures [114]. The H/Si(100) (2 × 1) is characterized by rows of H–Si–Si–H (monohydride) dimers (Fig. 6.17). It appears that even a small concentration of isolated dangling bonds is sufficient to facilitate substantial oxidation. At these sites, oxide stripes as long as 15 dimer units were observed after O2 exposures of only 10 L at 530 K (Fig. 6.17). In these experiments performed at elevated temperature, the hydrogen termination is preserved during oxidation with O insertion in the Si–Si back-bonds [90, 113, 114]. First principle calculations (using mostly Density Functional Theory) have addressed O2 interaction with H/Si. If residual dangling bonds are present, O2 preferentially dissociates at such sites (even with only one dangling bond per dimer) and initiates oxidation, which proceeds along dimer rows via H migration, as experimentally observed [114]. At low temperatures, the theory confirms that only a physisorbed state can be stabilized [115]. If a reaction is forced to occur, O insertion into Si–Si back-bonds is energetically favorable over insertion into Si–H bonds [116], consistent with the observation of Si–H and the absence of any hydroxyl (Si– OH) at the surface. Given the large O2 exposures (109 –1015 L) required to oxidize H/Si surfaces, cleanliness issues due to impurity-mediated reactions are expected to come into play. Notably, air oxidation of H/Si(100) and H/Si(111) clearly accelerates with increasing humidity [45, 101, 117–119]. But a two-step mechanism is required to model time-dependent oxidation data [118–120]: a slow nucleation followed by a faster subsurface oxidation adjacent to previously reacted sites. The nucleophilic at-

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Fig. 6.17. Filled state STM images of a H-terminated Si(100)-(2 × 1) with isolated dangling bonds (a) before, and (b) after exposure to 10 L of O2 molecules at 530 K, performed at room temperature with a sample bias voltage of −2.0 V and tunneling current of 20 pA. The bright ball-like feature denoted by an arrow is a dangling bond. Note the irregular oxidized region (“wire”)

tack of back-bonds polarized by subsurface O may facilitate oxidation, resulting in 2-dimensional island growth. The rate constants for H/Si(111) were found to scale with humidity, indicating that H2 O is responsible for initial surface modification. The newly formed hydrophilic sites then promote physisorption of additional H2 O. The dependence on O2 only becomes important after this initial water-induced oxidation [118, 119]. Both for air [118–120] and O2 oxidation [108] at room temperature, the reaction appears to accelerate as soon as a complete incorporation of O into the back-bonds has taken place (labeled H/SiOx ). This observation suggests a reaction mechanism involving physisorbed precursor molecules (O2 or H2 O) that diffuse across the surface initially made up of H/Si and H/SiOx areas. These molecules can either desorb or react with the surface. If the desorption barriers are lower for H/Si than for H/SiOx , then the residence time of the precursor molecules on the H/SiOx areas would lead to faster oxidation as soon as O incorporation is complete. The role of dopants in the Si substrate has also been shown to influence H/Si oxidation rates. For instance, oxidation of n+ -Si proceeds much faster than for n− or p+ -Si, indicating that substrate electrons affect reactivity [45, 101]. The initial oxidation rate also appears to scale with surface roughness [120] (although some authors disagree [117]). This finding was taken as an indication that oxidation starts from steps or defects and continues 2-dimensionally (e.g., via Si back-bond polarization and nucleophilic attack) until the first ML is completed [120]. In the absence of defects, an atomically flat H/Si surface can remain perfectly oxide-free in humid air for at least 15 min [121].

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Finally, ambient contaminants other than H2 O, such as organics or radicals, cannot be disregarded. For instance, the presence of organic species has been invoked to account for changes in the electrical surface properties of H/Si [122]. Such species may also affect the oxidation rate. While all air oxidation studies implicitly assumed that other contaminants were either absent or did not influence oxidation, experiments utilizing high-purity O2 /H2 O mixtures have helped show that this is not the case, as shown below. In situ IR measurements have been performed to study O2 interaction with various H/Si surfaces and to unravel the oxidation mechanisms [13, 123]. These studies use high-purity O2 and focus on comparing technologically relevant HF-etched Si(100) to structurally well-defined model surfaces, such as atomically flat H/Si(100) (3 × 1) prepared in UHV [124] and flat and stepped H/Si(111) prepared by an NH4 F wet etch [29, 59, 125]. Structural and chemical information is readily available from the Si–H stretch modes and direct detection of Si–O modes is usually done using transmission geometries. Figure 6.18(a) shows the Si–H stretch spectrum of a H/Si(111) surface miscut at 9◦ in the direction exposing steps terminated by dihydrides (Si–H2 ). Ter-

Fig. 6.18. Multiple internal reflection IR spectra for H/Si(111) 9◦ miscut along (112) (dihydride steps) exposed to 0.02 mTorr O2 at 573 K, subsequently annealed to 693 K, and exposed to O2 at the same temperature. (a) Absorbance of starting surface; spectral reference: H/Si(111) oxidized by O2 at 693 K. (b) Difference spectra for the subsequent processing steps; the spectrum of the starting surface is used as a spectral reference, i.e., negative absorbance indicates the loss of species from the surface. C1 , C2 , and C3 are modes related to step dihydrides. An exposure of 1 min corresponds to a dose of 9 × 105 L O2 [127]

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race monohydrides (∼2083 cm−1 ) are clearly distinguished from the step modes characterized by three distinct vibrations at C1 = 2095 cm−1 , C2 = 2102 cm−1 , C3 = 2136 cm−1 [126]. Figure 6.18(b) shows that the step modes react much faster than the terrace monohydride upon O2 exposure at 573 K, a temperature typical of ALD growth. In the above example, the disappearance of the Si–H stretch modes in the 2000 cm−1 range may be due to the reaction of H with O (to form OH, for instance), but the OH intermediate cannot be detected because it is not stable at such exposure temperatures (∼575–600 K). Oxygen is rapidly incorporated into the silicon surface (Si–Si back-bonds), resulting in a large Si–H stretch blue shift [123]. For instance, as a flat surface is oxidized, modes corresponding to monohydrides with singly, doubly, and triply oxidized Si atoms, are observed at 2150, 2200, and 2250 cm−1 (not shown) [13]. In all cases, there is no measurable absorption in the 3650–3750-cm−1 range corresponding to hydroxyls on attached to Si atoms with varying degrees of oxidation. Similar kinetic experiments have been performed for a variety of surfaces, including flat H/Si(111) and for H/Si(111) with monohydride steps [13, 123]. Figure 6.19 shows, for example, the oxidation kinetics for monohydride on Si(111) terraces compared to those of mono- and dihydrides at steps. The oxidation rate is highest on dihydride steps, lower on monohydride steps, and lowest on monohydride terraces. Comparison of flat (100) and (111) surfaces [127] shows that, for comparable substrate orientation, the reaction rates increase according to: terrace monohydride < step monohydride < dihydride < trihydride (by up to one order of magnitude). Based on all the available data [123], the following conclusions about oxidation can be drawn: (a) Oxidation occurs by direct insertion of O into Si–Si backbonds, i.e., without H removal or OH formation; (b) The activation energies are ap-

Fig. 6.19. Kinetics of the Si–H peak decay on flat and stepped H/Si(111) surfaces for terrace H, step monohydride (on (112) miscut surface), and step dihydride (on (112) miscut surface) in 1.3 mTorr O2 at 573 K. An exposure of 1 min corresponds to a dose of 6 × 107 L O2 [13]

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proximately 1.6–1.7 eV, i.e., lower than typical Si–Si bond energies (e.g., 2.31 eV), indicating that oxidation occurs without Si–Si bond-breaking prior to O insertion; (c) Differences in reaction rate of mono-, di-, and trihydrides are most likely due to different activation energies resulting from variations in steric hindrance; (d) Variations in reaction rate are largely consistent with differences in accessibility of the back-bonds to O2 and thus higher reactivity is found for the highly accessible backbonds of strained, tilted dihydrides at H/Si(111) steps and for back-bonds on rough surfaces in general, when comparing the same type of hydride on different substrates; (e) A minor effect in some cases might be a lowering of the activation energy at strained sites, e.g., for strained mono- and dihydrides on Si(100) (3 × 1), leading to an increased reactivity; and (f) O-hopping immediately after insertion (dissipating the high free energy of oxidation) is a possible cause for the observed enhancement of terrace oxidation by nearby steps/defects and the absence of Si–H stretch observed with a single oxygen atom in its back-bond. It was further shown that the oxidation mechanism observed in the low pressure regime is applicable to atmospheric pressures [127]. For atmospheric conditions, IR data yield a rate constant of 0.052 min−1 , fairly close to a value of 0.029 min−1 extrapolated from the kinetic data discussed above, obtained at much lower pressures. This indicates that the same oxidation mechanism applies across five orders of magnitude and a temperature range of 240 K. Further extrapolating the kinetics at atmospheric pressure to room temperature leads to a value of ∼10−13 for the reactive sticking coefficient of O2 on H/Si(111) [127]. This number is in the range of values obtained in other studies on H/Si(100), namely ∼10−12 to 10−15 [45, 108, 117, 128], again suggesting that the same oxidation mechanism may apply. Water Vapor Interaction with Hydrogen-Terminated Silicon Surfaces The reactivity of UPW at H/Si surfaces is dominated by OH− . In the vapor phase, such (neutral or ionic) species formed by H2 O dissociation clearly cannot play a role: Provided that photo-induced fragmentation of H2 O is insignificant, the concentration of OH groups in the gas phase is ∼10−45 at 573 K as determined by the Boltzmann factor. Molecular O2 , on the other hand, may be present in H2 O vapor, since the liquid H2 O reservoir contains substantial amounts of dissolved O2 after contact with atmospheric air. Therefore, special care must be taken to reduce the O2 content in the liquid bath by bubbling with inert gases or chemical purification [129, 130]. Takagi et al. first demonstrated the low reactivity of H/Si exposed to H2 O vapor [131]. In a UHV environment and at room temperature, no detectable H2 O adsorption on H/Si(100) (2 × 1) was observed with exposures in the Langmuir regime. At low temperatures (e.g., 90 K), H2 O is physically adsorbed forming ice clusters, and desorbs below room temperature without reacting with the substrate. At least 5 × 107 L H2 O had to be supplied to H/Si(111) at room temperature [132] in order to reach an oxide thickness of about 2 Å. The H termination was preserved during the formation of such thin SiO2 films, similarly to the case of O2 oxidation discussed above. The generation of activated Si–Si back-bonds was invoked as the rate-limiting

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step for these relatively lower temperatures. Initial oxidation is slow at 598 K and increases rapidly at higher temperatures (e.g., a 3 Å SiO2 film is formed above 723 K). In this higher temperature regime, the oxidation rate is limited by thermal desorption of the H over layer from the Si substrate [132]. This is in line with the findings of Kim et al. [133], who reported that a long (also unspecified) H2 O exposure of H/Si(100) in an ALD reactor at up to 573 K results in 1–1.5 Å SiO2 , while at 623 K and above, much thicker oxide films are formed. These observations confirm that no reaction should occur below 573 K. Zaïbi et al. [134], utilizing photoemission yield spectroscopy, also found a reaction threshold at 623 K, at which temperature they indirectly inferred that a substantial OH concentration was present on H/Si(111) for H2 O doses as low as 50 L. A number of theoretical studies have addressed the interaction of H2 O with H/Si. The physisorption energies on H/Si(100) and H/Si(111) are estimated at −0.16 eV [135] and −0.13 eV [136], respectively. For hydroxylation via: Si3 –Si–H + H2 O → Si3 –Si–O–H + H2

(6.6)

overall reaction enthalpies of −0.70 eV [137], −0.75 eV [138], and −0.59 to −0.69 eV [139] are reported with corresponding barrier heights of 2.13, 1.60, and 1.85–2.05 eV. There is experimental evidence that trihydride configurations are hydroxylated more easily than dihydride structures [139]. For all configurations, however, hydroxylation requires substantial thermal energy to occur and is therefore improbable at room temperature. Recent IR absorption studies of H2 O vapor interaction with H/Si have focused on ensuring a low O2 concentration by extended bubbling of the H2 O with ultrapure N2 . Such precaution is essential in view of the potential influence of O2 in the H2 O vapor on oxidation. Most experiments were performed under typical ALD conditions (e.g., 573 K) in a home-built ALD reactor [140]. For such spectroscopic experiments, it is convenient to use D2 O instead of H2 O to separate surface reaction from possible fluctuation due to residual H2 O vapor in the spectrometer, while leaving the oxidation chemistry unaffected [140]. The main result, as illustrated in Fig. 6.20, is the stability of H/Si surfaces under exceedingly high concentrations of H2 O exposures at relatively high temperatures. Whether the surface is ideally H-terminated, Fig. 6.20(a), or atomically rough with several types of hydrides, Fig. 6.20(b), the Si–H stretch modes remain unchanged after D2 O exposure in the 108 L regime at 573 K [140], except for a few-percent isotopic H–D exchange. On the surface of H2 O-exposed H/Si(111), there is no evidence of H bonded to oxidized Si atoms (On –Si–H, 2130–2300 cm−1 ) [113], isolated OH groups (Si–OD, 2700–2760 cm−1 ), or SiO2 phonon signals (∼1000–1200 cm−1 ) [141]. Therefore, oxidation or hydroxylation of H/Si(111) is insignificant under the reaction conditions studied. On H2 O-exposed H/Si(100), there is evidence for some oxidation and for isolated OD groups but only on oxidized Si sites (2760 cm−1 ), as shown in Fig. 6.20(b). By using proper references (5.5-Å SiO2 film prepared by wet chemical oxidation [142], and a half monolayer of OH prepared in UHV by H2 O dissociation on

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Fig. 6.20. Transmission IR spectra of (a) H/Si(111), and (b) H/Si(100) measured before and after exposure to 1–5 × 108 L D2 O (10 mTorr) in N2 carrier gas (1 Torr) at a sample temperature of 573 K. Reference spectrum in oxide phonon and O–D stretching regions: H-terminated Si. Note that due to Si–H bending modes of the H/Si(100) reference surface, a signal at ∼920 cm−1 has been removed for clarity. Reference spectrum in Si–H stretching region: Si with native oxide. For comparison, we show IR spectra of well-known oxide and hydroxyl over layers described in the text [143]

Si(100)(2 × 1)), the amount of oxide is estimated at 0.1 Å (5 × 1013 O ions cm−2 ) and the coverage of OD at 2% ML (1.3 × 1013 OD cm−2 ) [143]. Comparing the reactivity of structurally and chemically defective H/Si(100) to that of completely passivated flat H/Si(111), hydroxylation is found to occur only at certain defects present in low concentration, such as oxide or specific step sites. Therefore, in the 108 L exposure regime, well beyond exposures relevant to ALD processes, O2 -depleted H2 O does not oxidize H/Si(100) and H/Si(111) at 573 K to any significant extent. In conclusion, in situ IR studies have shown that H/Si surfaces react more slowly with H2 O vapor at 573 K than with O2 . Assembling all available evidence, the reactivity of H/Si between room temperature and 573 K appears to increase in the order: H2 O < O2 < humid air. This surprising finding may indicate that there is a cooperative effect of H2 O and O2 , such as a two-step oxidation mechanism in which one species opens up the surface while the other is needed for substantial oxidation. Alternatively, the reactivity of ambient air might be due to impurity species not yet considered; for example, hydrocarbons, O3 , or radicals. In order to come to a conclusive answer, high-purity gas experiments utilizing O2 /H2 O mixtures and impurity additions to O2 or H2 O will be required, and quantum chemical calculations should be coupled to these experiments.

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6.3 High-Permittivity (“High-k”) Gate Stacks 6.3.1 Introduction Hafnium-based dielectrics have emerged as the main high-k materials for the first generation of high-k-based logic chip products. However, dielectrics based on metals other than Hf have also been under consideration. Zirconium (Zr) has featured most prominently, as its properties are very similar to those of Hf. Other candidate materials include LaAlO, LaLuO, DyScO, or SrTiO (note that stoichiometric indices are often omitted, since composition may vary, in particular in amorphous ternary oxide films). Interest in such materials is often fueled by their higher dielectric constants. They therefore have the potential for even higher gate stack capacitance, i.e., lower effective electrical thickness, than what is achievable with Hf-based dielectrics. This may be attractive for implementation in later generations of high-k-based logic chips. In this section, we concentrate on Hf-based “mainstream” dielectrics. However, the gate stack issues we address, such as interfacial layer thickness scaling, mobility degradation, and threshold voltage control apply also to other dielectrics, though to different extents. The fabrication of Hf-based stacks often proceeds along the following lines, where steps may be added, modified, or omitted, depending on the specific application: • Wet pre-clean of the silicon surface: This process may form a chemical oxide or a hydrogen passivation layer. Sometimes other functional groups such as methoxy groups have been investigated. • Optional surface oxidation, oxy-nitridation, or nitridation, e.g., in a thermal or a plasma process. • Deposition of a high-k layer: Layers commonly used include HfO2 , HfZrO, HfSiO, HfSiON, HfAlO, and HfLaO, often deposited by ALD or chemical vapor deposition (CVD). • Optional post-treatment of the high-k layer: This frequently involves thermal or plasma nitridation and/or thermal annealing steps. • Optional deposition of an additional “capping” layer: Such layers have been employed to tune threshold voltages of high-k gate stacks towards their desired values. Materials under consideration include: Al2 O3 and AlN for pFET and La2 O3 , MgO, or Dy2 O3 , for nFET. • Deposition of the gate electrode: For low-power applications with their relatively thick gate stacks, poly-Si is still used sometimes. More frequently, metal gate electrodes are employed to maximize gate stack capacitance in inversion and thereby drive current. Most metal gate work has recently concentrated on thin (∼20–200 Å) layers of metal nitrides or carbides such as TiN, TaN, or TaC, optionally with additional incorporation of other species, e.g., to form TiSiN. These thin metal layers are capped with thick layers of poly-Si, which may serve to make electrical contact in the fully processed device (unless a replacement gate integration scheme is used; see below).

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• Patterning of the gate lines and further processing of the device and circuit: These processes may modify the properties of the gate stack, e.g., by hydrogen or oxygen in- or out-diffusion The two basic requirements any acceptable gate dielectric stack needs to meet are (a) sufficient electrical insulation of the gate electrode from the channel, and (b) sufficient total gate stack capacitance. Requirement (a) translates into a need for continuous (non-islanded) deposited metal oxide layers. Requirement (b) means that any interfacial “native” silicon oxide between the channel and the high-k material should be as thin as possible (though we shall see that there may be a tradeoff between capacitance and carrier mobility in the channel [144]). To meet these needs, surface and interface chemistry need to be understood and optimized. In the following, we discuss how gate stack interface and structure formation can be tuned by choosing appropriate processes and materials, and how this affects electrical quality, with a focus on the importance of the silicon channel interface. We concentrate on the stages of device fabrication up to gate dielectric and optional cap layer deposition. 6.3.2 Silicon Surface Preparation and High-k Growth: The Impact of Thin Oxide Films on Nucleation and Performance Silicon surface preparation prior to high-k deposition serves a dual purpose. Of course, the pre-clean has to ensure that the wafers are free from metals, particles, or other contaminants. However, pre-clean and optional oxidation or nitridation treatments also have a major impact on the structure and performance of the final high-k gate stack. These processes therefore require careful optimization. In this section, we focus on the latter aspect. The most important fundamental issues in high-k growth concern film nucleation and interfacial oxidation. To illustrate the dramatic impact of surface preparation on gate stack structure, we focus on ALD growth of the binary high-k oxides HfO2 , ZrO2 , and Al2 O3 . Similar considerations apply to CVD growth, and to other, more complex high-k oxides. Atomic layer deposition is a particularly attractive technique for high-k gate dielectric growth in that it is designed to provide a higher degree of film uniformity, conformity, and thickness control than other chemical growth techniques. Atomic layer deposition was first introduced in the 1980s and has since been used in various thin film applications, most importantly in electroluminescent display technology and in microelectronics. Ritala and Leskelä have thoroughly reviewed the ALD technique, precursors, and applications [145]. Atomic layer deposition is based on self-saturating surface reactions. Molecular precursors are brought to the sample surface, e.g., the silicon wafer in alternating pulses and separated by an inert gas purge. Each reactant undergoes a selfterminating surface reaction, depositing a monolayer of material or less. Atomic layer deposition can thus be regarded as “pulsed CVD” under self-saturating conditions. For example, HfO2 is often grown from the metal precursor A = HfCl4

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Fig. 6.21. Idealized scheme of the first HfO2 ALD cycle on hydroxylated SiO2 using HfCl4 and water

and the oxygen precursor B = H2 O, as illustrated by Fig. 6.21. The surface is thus exposed to a pulse series according to A–N2 –B–N2 –A–· · · . For growth on a hydroxylated SiO2 /Si surface, an idealized growth scheme is as follows: The first HfCl4 pulse reacts with the surface hydroxyl (–OH) groups, releasing HCl until all reactive sites have been consumed and the reaction stops. A water pulse then transforms the surface Hf–Cl groups into hydroxyl (Hf–OH) groups, again releasing HCl. In this way, the chemical ingredients to form a monolayer of HfO2 are deposited, exposing reactive sites available for the second pulse cycle. According to this scheme, it should be possible to deposit a compound (or an element [145]) on a substrate in a highly conformal fashion, with a maximum growth rate of one monolayer per pulse and with thickness and uniformity control at the angstrom level. For ZrO2 and Al2 O3 growth, ZrCl4 and Al(CH3 )3 (trimethylaluminum, TMA have been particularly popular metal precursors, respectively, with H2 O frequently serving as an oxygen precursor. However, many other precursors are in use as well. Metal precursor choice is guided by requirements such as thermal stability, vapor pressure, reactivity, and impurity content. For example, HfO2 may instead be grown from metal-organic Hf precursors. As a stronger oxidizer, ozone (O3 ) is frequently employed. Non-Idealities in High-k Gate Dielectric Growth on Silicon The idealized picture of ALD we described above clearly neglects a number of potentially important phenomena, such as reaction of the metal-organic precursor with more than one hydroxyl group, incomplete hydroxyl consumption, steric hindrance, or crosslinking of metal ions through oxygen bridges. In fact, such crosslinking is clearly necessary to form a continuous oxide film. Herein, we concentrate on two non-idealities encountered frequently in high-k applications on silicon: Non-linear (i.e., non-layer-by-layer) growth and substrate oxidation. The first of these two non-idealities, non-linear growth, was first discovered when attempts were made to fabricate atomically sharp Si/high-k interfaces by depositing the high-k dielectric onto oxide-free hydrogen-terminated Si. This is exemplified by Fig. 6.22. For Al2 O3 , HfO2 , and ZrO2 deposition onto such substrates at the common ALD temperature of 300◦ C, using the popular precursor systems introduced above, the amount of high-k oxide deposited (as quantified by the areal density of

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Fig. 6.22. Top: Areal density of metal ions as a function of the number of ALD cycles for high-k growth on hydrogen-terminated Si(100) at 300◦ C (the dotted line approximately indicates the density expected for well-nucleated films); bottom: TEM images from the same growth systems. Left: Al2 O3 from Al(CH3 )3 + H2 O (areal density data from [146]/TEM image from [147]); center: HfO2 from HfCl4 +H2 O ([148]/[149]); right: ZrO2 from ZrCl4 +H2 O ([147]/[150])

metal ions) is initially not proportional to the number of ALD cycles (Fig. 6.22, top). Instead, initial growth proceeds much more slowly until a linear growth regime is reached after ∼50 cycles. The first ALD cycles thus deposit fewer metal-containing groups on the hydrogen-terminated surface than they do once a metal oxide film has been formed. Such delayed nucleation is characteristic of undesirable island growth, as confirmed by transmission electron microscopy (TEM) (Fig. 6.22, bottom). Such discontinuous high-k films cannot be expected to serve as acceptable gate insulators. Indeed, very high leakage currents flow between channel and gate electrode, e.g., for the case of HfO2 grown on hydrogen-terminated Si [149]. To improve ALD nucleation, oxidized/hydroxylated silicon surfaces may be used instead of inert, hydrogen-terminated Si. In most cases, growth then proceeds nearly linearly (Fig. 6.23), indicating nucleation everywhere on the substrate [142, 148]. Continuous high-k layers are thus formed at thicknesses as low as ∼20 Å (Fig. 6.23, right), and proper gate insulation can be achieved [149]. Interestingly, a detailed comparison of different Si oxidation processes shows that, e.g., for HfO2 growth from HfCl4 and water the initial growth rate increases according to H/Si thermally grown SiO2 /Si < wet-chemically grown SiO2 /Si [148]. This indicates that nucleation correlates with hydroxyl group density on the substrates and supports the notion that such hydroxyl groups are the primary reaction sites for incoming HfCl4 (Fig. 6.21). While Si oxidation improves nucleation, it also reduces gate stack capacitance, reducing the benefit of implementing high-k dielectrics. However, even when oxygenfree, hydrogen-terminated Si is chosen as a starting surface, as-grown gate stacks often exhibit an interfacial SiO2 layer between the high-k dielectric and the channel. This is exemplified by the TEM images in Fig. 6.22 (bottom), where thin interlayers

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Fig. 6.23. Areal density of metal ions as a function of the number of ALD cycles for high-k growth on oxidized Si(100) at 300◦ C. Left: Al2 O3 from Al(CH3 )3 + H2 O (data from [146]); right: HfO2 from HfCl4 + H2 O (data from [148]). Far right: TEM image for HfO2 growth on thermal oxide [149]

between the high-k islands and the Si channel are visible in all cases. It is tempting to attribute such inadvertent oxidation of the silicon simply to interaction of the first water pulse with the H-terminated surface. However, in the absence of metals, even very long water pulses do not significantly oxidize or hydroxylate H-terminated Si at 300o C, as has been demonstrated by in situ transmission infrared spectroscopy [140, 142]. Also, if such oxidation indeed took place during the first water pulse, linear growth characteristics would be expected from the subsequent metal precursor pulse onwards, in conflict with the data (Fig. 6.22, top). We conclude that water-induced oxidation takes place only where metal is present on the surface or where the metal precursor pulse otherwise removes the passivating hydrogen. Interfacial SiO2 thus forms underneath the growing high-k islands. Indeed, gradual removal of hydrogen with concomitant SiO2 formation has been detected during cyclic ALD growth of Al2 O3 from Al(CH3 )3 and H2 O, again using in situ infrared spectroscopy (see H coverage data in Fig. 6.24 below) [140, 142]. To resolve the nucleation issue on hydrogen-terminated Si, instead of H2 O the more reactive oxygen precursor O3 is sometimes used. In that case, substantial Si oxidation occurs even during the first growth cycles, enhancing nucleation and thereby resulting in more continuous high-k films. However, this of course comes at the expense of ultimately thicker interfacial SiO2 layers than with H2 O [151, 152]. Improving the Nucleation-Scaling Trade-Off As we have seen, ALD growth of high-k layers on hydrogen-terminated Si substrates does not always result in the desired layer properties. Growth often suffers from poor nucleation resulting from a surface reactivity that is too low, while at the same time interfacial SiO2 can grow resulting from a surface reactivity that is too high. Requirements for high-k film continuity and interface scaling may thus seem to be mutually exclusive. However, the nucleation-scaling trade-off can be improved. Three such approaches are (i) growing the high-k layers at lower temperatures (e.g., near room temperature), kinetically suppressing desorption of the precursor, its diffusion across

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Fig. 6.24. Left: In situ transmission infrared spectra of H-terminated Si(100) (a) before, (b)–(f) after the specified number of TMA and water exposures at 50◦ C, (g) after subsequent inert anneal to 300◦ C, and (h) after a final water exposure at 300◦ C. The reference surface for oxide phonon and C–H stretch regions was H-terminated Si (as no independent reference surface is available for spectrum (a) from H-terminated Si in these spectral regions, the ideal spectrum is indicated with a dotted line) and for Si–H stretching region was SiO2 /Si. Right: Si–H stretch mode intensity as a function of the number of Al2 O3 and HfO2 ALD cycles performed at the specified temperatures [H-terminated Si = 1]. After [153]

the surface, and Si oxidation [153]; (ii) employing a metal precursor that is more reactive towards H-terminated Si, facilitating attachment to the substrate [153]; or (iii) starting from nitrided (or oxynitrided) silicon substrates, increasing the dielectric constant of the interfacial layer and reducing its thickness while maintaining good nucleation [154]. (i) Growth at moderate temperatures, e.g., near room temperature, can prevent interfacial silicon oxidation during atomic layer deposition of high-k gate dielectrics on hydrogen-terminated Si. For example, during Al2 O3 growth from Al(CH3 )3 and H2 O at 50◦ C, the hydrogen layer stays completely intact, preventing any significant SiO2 formation [153]. Corresponding in situ transmission infrared spectra are shown in Fig. 6.24. The infrared spectrum of the starting surface, i.e., wet-chemically H-terminated Si(100) (Fig. 6.24 left, a) exhibits a structured Si–H stretching band (∼2110 cm−1 ), reflecting the fact that the H/Si(100) surface is atomically rough on the double-layer scale [59]. The first TMA exposure at 50◦ C (Fig. 6.24 left, b) causes the rise of modes due to Al–CH3 bonding (–CH3 umbrella mode at 1220 cm−1 and C–H stretching mode at 2940 cm−1 ) [155–157]. A Si–CH3 minority species (1270 cm−1 ) is formed as well [158, 159], indicating some transfer of methyl groups to Si substrate defect sites. However, attack of the H termination is insignificant: The Si–H signal intensity originating from O-free surface sites (2085–2135 cm−1 ) is undiminished (Fig. 6.24 left, b and Fig. 6.24, right) and essentially full H coverage is therefore maintained. A slight broadening indicates perturbation of the Si–H vibrational modes by interaction with the partially oxidized Al(CH3 )x film physisorbed on

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Fig. 6.25. Schematic picture of interface formation during ALD of Al2 O3 (Al(CH3 )3 + H2 O) on H-terminated Si at conventional (300◦ C, top) and low (50◦ C, bottom) temperatures

top of the H/Si layer. The subsequent water pulse (Fig. 6.24 left, c) fully oxidizes the Al and causes the loss of most Al-bonded methyl groups, as expected for a good ALD growth. Infrared signals originating from Si–H remain undiminished. Also, there is no evidence of H bonded to oxidized Si atoms (On –Si–H, 2130–2300 cm−1 ) [113] or of SiO2 phonon signals (ca. 1000–1200 cm−1 ) [141]. Based on phonon intensity calibration using SiO2 films of known thickness [140, 143], we find that the average SiO2 thickness is substantially lower than 1 Å. This shows that the water pulse leaves both the hydrogen layer and the Si-bonded methyl groups fully intact, and Si oxidation is negligible. The remarkable stability of the H layer at 50◦ C becomes even more evident when following Al2 O3 growth during subsequent ALD cycles: Even after 8.5 ALD cycles (Fig. 6.24 left, f), the interface remains H-passivated and oxide-free. At 50◦ C, thick Al2 O3 films can thus be grown on H/Si while leaving the protective H layer intact. In contrast, Al2 O3 growth at 300◦ C results in near-complete H removal after 2 ALD cycles (Fig. 6.24, right) and in the formation of 4 Å interfacial SiO2 underneath thick Al2 O3 [140]. The differences in interface formation between 300◦ C and 50◦ C growth of Al2 O3 from Al(CH3 )3 and H2 O are schematically illustrated in Fig. 6.25. During HfO2 growth from Hf(NC2 H5 CH3 )4 (tetrakis(ethylmethylamido)hafnium, TEMAH) and H2 O at 100◦ C, the hydrogen layer is partially preserved, resulting in an interface composed of H-terminated silicon atoms and Si–O–Hf bridges, but again not containing any SiO2 [153]. Film continuity is expected to be improved at reduced growth temperatures, due to slower diffusion of precursor molecules across the H-terminated surface. Unfortunately, little experimental data is available so far to confirm this prediction for H-terminated substrates. However, we note that improved nucleation at reduced temperatures has been observed for growth on oxidized silicon [160]. (ii) Metal precursors with higher reactivity than HfCl4 may be expected to interact more strongly with H-terminated Si, resulting in better nucleation. Higher reactivity can be achieved, for example, by replacing the metal-halide (Hf–Cl) bonds

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by the significantly weaker metal-nitrogen (Hf–N) bonds of metal alkylamides such as TEMAH [160]. Indeed, HfO2 growth from TEMAH and H2 O on H-terminated silicon is nearly linear, indicating that near-continuous films are formed [153, 161, 162]. (iii) Silicon nitridation has arguably been the most important path to manufacturable thinner high-k/silicon interfaces. Silicon nitride (Si3 N4 ) layers in the thickness range of ∼4 to 10 Å chemically passivate the silicon surface against oxidation during ALD growth and during thermal processing of the device. In addition, Si3 N4 increases interface permittivity over SiO2 , since Si3 N4 itself is a high-k material with a dielectric constant k ∼7–8, compared to SiO2 with k = 3.9 (though we note that the effective dielectric constant of thin nitride films is often found to be somewhat lower). This aids capacitance scaling. In an intermediate approach, silicon oxynitride (SiON) with varying composition is frequently employed. Regarding ALD growth of high-k dielectrics, such nitride-based interfaces often are good nucleation layers [149, 163], similar to silicon oxide. Capacitance enhancement by nitrogen has been demonstrated, for example, using interfacial Si(O)N layers fabricated by H/Si anneal in NH3 at, e.g., 650◦ C to form thin Si3 N4 [163, 164], optionally followed by an oxidizing anneal, e.g., in NO gas [154]. Poly-Si/CVD HfSiO stacks on such high nitrogen content films exhibit lower electrical oxide thickness (EOT) than on 11 Å low N content SiON control substrates, even in cases where physical thickness of the high-N-content interface layer is higher [154]. The main obstacle to implementation of high nitrogen content interfacial layers has been carrier mobility loss [154, 164]. This is illustrated by Fig. 6.26, which shows nFET electron mobility curves for two poly-Si/CVD HfSiO/Si3 N4 gate stacks. With interfacial Si3 N4 (8–9 Å, ∼2 × 1015 N/cm2 ), high-field mobility is degraded

Fig. 6.26. Electron mobility as a function of inversion layer charge in nMOSFETs with a polySi/30 Å HfSiO gate stack on thermally grown SiON (11 Å, 7 × 1014 N/cm2 ) and Si3 N4 (NH3 anneal at 650◦ C; 8–9 Å, ∼2 × 1015 N/cm2 ) interface layers [154]

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by 20–25% compared to low N content interfacial SiON layers. Even upon introduction of O into the nitride, mobility recovers only marginally [154]. When interpreting such data, it is noteworthy that high nitrogen concentrations usually reduce mobility even with conventional SiON gate dielectrics [165]. Coulomb scattering by fixed charges in the Si(O)N layer [166, 167] likely is the main mechanism of mobility loss in both cases [154]. In addition, interfacial nitrogen in high-k gate stacks increases the areal density of slow interface states and creates sites for charge trapping [154]. These latter phenomena exacerbate the mobility loss due to fixed charge. Interfacial SiO2 : Required for Optimum Performance? Interestingly, atomically sharp Si/high-k interfaces may in fact not be desirable for fundamental reasons [144]. The high dielectric constant of high-k insulators is due to their relatively soft metal-oxygen bonds which give rise to a large ionic polarizability. Such soft bonds also give rise to low-energy optical phonon modes in the dielectric. These phonon modes can interact with carriers in the MOSFET inversion layer, reducing carrier mobility, a phenomenon that is often referred to as “remote optical phonon scattering” [144]. Indeed, reduced carrier mobility with high-k gate dielectrics has often been observed experimentally (even in the absence of nitrogen) [5]. This is usually attributed to remote optical phonon scattering and/or remote Coulomb scattering off fixed or trapped charges in the gate dielectric. Independent of the physical mechanism, interfacial SiO2 layers have been argued to reduce scattering by increasing the distance between the channel carriers and the high-k dielectric, thereby increasing mobility [144]. Indeed, mobility improvements close to those predicted by theory are observed experimentally [168]. Interfacial SiO2 layers in the thickness range of ∼5 to 12 Å are therefore frequently employed to optimize carrier mobility with high-k dielectrics. Summary To summarize this section, hydrogen-terminated Si and silicon oxide, nitride, and oxynitride films have been the most important substrates for high-k growth towards logic applications. Such substrates can be prepared quickly and cost-effectively with conventional manufacturing equipment. For high-k gate dielectric ALD onto Hterminated Si, employing the popular trimethyl or tetrachloride metal precursors, trade-offs have to be made between continuity of the gate oxide layer and sharpness of the Si/high-k interface. The nucleation-scaling trade-off can be improved, e.g., by growing the high-k layers at reduced temperatures, kinetically enhancing nucleation and reducing Si oxidation; by employing a metal precursor that is more reactive towards hydrogen-terminated Si, improving nucleation; or by starting from nitrided (or oxynitrided) silicon substrates, increasing the dielectric constant of the interfacial layer and reducing its thickness while maintaining good nucleation. High nitrogen concentrations (>1015 cm−2 ) cause fixed charge and, in turn, carrier mobility loss by Coulomb scattering. By careful tuning of SiON composition, oxidation resistance

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can be enhanced over SiO2 while mitigating mobility loss. Even with nitrogen-free, sharp Si/high-k interfaces, mobility loss due to phonon and/or Coulomb scattering is a concern. Interfacial SiO2 or SiON layers in the ∼5–12 Å thickness range help recover good carrier mobility. 6.3.3 Post-Treatment of the High-k Layer: Nitridation High-k layers sometimes receive additional treatments prior to cap layer or gate electrode deposition. In particular, nitridation by gas or plasma exposures has frequently been reported. Such nitridation, e.g., of HfSiO layers, has a number of potential scaling and stability benefits: • High-k capacitance scaling: Nitrogen incorporation can moderately increase the permittivity of the HfSiO. • Interface scaling: Nitrogen incorporation may slightly reduce interfacial SiO2 formation during thermal processing of the device, which may involve temperatures in excess of 1000◦ C for dopant activation. • Preventing boron penetration: Undesirable boron dopant penetration from polySi gate electrodes into the channel during thermal processing is more effectively prevented by HfSiON than by HfSiO [169, 170]. This benefit of nitridation becomes irrelevant when metal gate electrodes are employed. • Preventing high-k crystallization: Pure HfO2 films crystallize into predominantly monoclinic polycrystalline films at 300–500◦ C [149, 171–173]; HfSiO is thermally more stable, but after extended 900–1000◦ C anneals it may still crystallize and decompose into HfO2 and SiO2 [169–171, 173, 174]; while crystallization at 1000◦ C can be completely suppressed by forming HfSiON [169]. A number of reasons, often speculative, have been put forward for aiming to keep high-k dielectrics amorphous: Heterogeneous grain orientations could give rise to spatially varying electric fields in the channel, causing carrier scattering and degrading mobility. (b) Grains could cause device-to-device variations in, e.g., leakage or threshold voltage. (c) Grains could increase effective line edge roughness after gate etch. (d) Grain boundaries have been claimed to be responsible for localized unoccupied gap states [175], e.g., observed ∼0.2–0.3 eV below the conduction band edge if and only if HfO2 is crystalline [176]; such gap states may explain undesirable charge trapping or gate leakage with HfO2 [177]. However, it is important to point out that, to our knowledge, no clear proof exists that crystallized high-k layers are fundamentally unable to meet technology specifications. The main concerns with HfSiO nitridation are carrier mobility loss and negative flatband/threshold voltage shifts due to positive fixed charge, similar to the case of high-k/Si interface nitridation. However, experimental studies show that mobility and threshold voltage impact is greatest if nitridation conditions allow N to permeate the entire HfSiO film and penetrate into the interfacial SiO2 layer. By contrast, nearsurface nitridation preserves mobility [169]. Surface nitridation can be achieved, for example, by appropriate low-temperature plasma nitridation conditions. This is exemplified by Fig. 6.27, which shows good carrier mobility at nitrogen contents as

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Fig. 6.27. Electron mobility as a function of inversion layer charge in poly-Si gated nMOSFETs with 30 Å top-nitrided HfSiON with (N/(N + O)) ∼21%, compared to low N content SiON [5, 154]

high as (N/(N + O)) ∼21% [5, 154]. Nitrogen-induced flatband or threshold voltage shifts were <0.02 V, a clear sign that no nitrogen, or only very little nitrogen, reached the channel interface where it would create a highly detrimental positive fixed charge. Summarizing this section, N incorporation into HfSiO helps optimize thermal stability and electrical thickness. However, N near the channel, in particular in the bottom interfacial SiO2 layer, reduces carrier mobility through Coulomb scattering by fixed charges. Therefore N incorporation near the top of the HfSiO is the method of choice. 6.3.4 The pFET Threshold Voltage Issue: Oxygen Vacancies Threshold (Vt ) and flatband (Vfb ) voltages of poly-Si-gated devices incorporating Hf-based gate dielectrics usually deviate from the ideal values achieved with polySi/SiO(N) gate stacks, unless special precautions are taken during fabrication. Similarly, threshold voltages for metal-gated high-k devices fabricated in a high-temperature process usually deviate from values predicted based on tabulated vacuum work functions of the metals involved. In all cases, the absolute value of the threshold voltage is higher than expected, i.e., higher gate voltages are required to turn on the device. This has been the most serious issue delaying implementation of high-k dielectrics in CMOS logic technologies. Interestingly, oxygen and the bottom interfacial Si/SiO2 interface play a major role in causing and resolving these issues. For brevity, we shall concentrate on poly-Si gated devices. Many of the issues and potential solutions are similar with metal gate electrodes. With poly-Si gate electrodes on Hf(Si)O(N)-type high-k dielectrics, nFET Vt is usually found to be more positive than expected by ∼0.2 V, while pFET Vt is more negative by ∼0.6 V [178–181]. Threshold voltages can be tuned to their optimum values through device engineering, e.g., by appropriate choice of halo implant de-

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sign or by counter doping. This way, nFET devices can likely be designed to offset the materials-induced shift of ∼0.2 V. By contrast, given the much larger ∼0.6 V shift for pFET devices, one cannot rely on implant engineering alone in order to fabricate Hf-based poly-Si/high-k devices with good performance, as device performance degrades with excessive tuning. The gate stack itself must be understood and modified. It is quite remarkable that laboratories worldwide, using a wide variety of process equipment, chemicals, and integration schemes, have reported nearly identical pFET Vt shifts of ∼0.6 V from the target value. This suggests that a fundamental physical or chemical phenomenon is responsible. Experimental evidence indicates a prominent role of oxygen. In fact, oxidation of the poly-Si/high-k stack by lateral indiffusion of oxygen can alleviate the pFET Vt shift of transistor devices with channel lengths below ∼1 μm, though accompanied by detrimental SiO2 formation at the poly-Si gate electrode interface [182]. Similarly, pFET Vt of metal gate/high-k stacks can vary by as much as 0.75 V, depending on O2 partial pressure and temperature during post-deposition gas anneals [183]. In the first detailed discussions of the pFET Vt shift with Hf-based high-k materials [179–181], it was suggested that oxygen-deficient Hf-Si bonds at the highk/poly-Si interface may cause Fermi-level pinning just below the poly-Si conduction band. However, defect levels and fixed charge in the Hf-based gate dielectric itself may likewise cause Vt shifts. It has been reported, for example, that oxygen vacancy formation in HfO2 is energetically favorable when the HfO2 is in contact with pdoped poly-Si or with a high work function metal gate, since such defect states are stabilized by the transfer of two electrons to the gate electrode [184–187]. By contrast, such transfer would be energetically unfavorable in contact with an n-doped poly-Si gate. Positive fixed charge would thus be created inside the HfO2 , shifting the pFET Vt to more negative values, which provides an explanation for the experimentally observed Vt behavior. Indeed, positively charged oxygen vacancies are currently considered the most likely origin of the Vt shifts. However, more physical characterization experiments are required in order to conclusively distinguish such defects from interfacial Hf–Si bonds. 6.3.5 Threshold Voltage Control: Oxygen and Metal Ions From a technological perspective, it is critical to determine whether the pFET Vt can be shifted closer to the target value by choosing appropriate processing conditions. While lateral oxidation of the high-k layer, likely filling O vacancies, brings partial relief for short channel devices, concomitant SiO2 growth at the poly-Si gate electrode interface, and possibly at the Si channel interface, degrades capacitance [182]. Also, O indiffusion and thus Vt are channel length dependent, which must be taken into account in circuit design. Finally, it is unclear whether the O content of the gate stack can be maintained at all during the entire device fabrication process. Introduction of Si into the Hf-based layer only has a very limited impact on Vt /Vfb . As expected, when utilizing HfSiO with increasing Si content, Vfb gradually approaches the value observed with SiO2 [179, 181, 188–190]. However, in order to

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Fig. 6.28. Schematic of a cap layer approach to poly-Si/high-k pFET Vt control [193–195]. During dopant activation anneals, ions from such caps can interdiffuse with the underlying Hf-based dielectric and down to the bottom SiO2 or SiON layer

bring Vt to within less than 0.3 V from the target value, Hf contents below ∼20% are required. At such compositions, the dielectric constant is only marginally higher than for SiON, making implementation unattractive. More substantial pFET Vt improvements by up to 0.4 V have been achieved by Al incorporation during deposition of the Hf-based dielectric [191]. This suggests that separation of the high-k dielectric from the poly-Si is irrelevant, lending support to the supposition that O vacancies in the Hf-based dielectric, not interfacial Hf–Si bonds, are responsible for the Vt issue. Admixed foreign atoms such as Al appear to create negative fixed charges [192] and/or chemical dipoles in the Hf-based gate stack that modify Vfb /Vt . The chemical nature of these charges or dipoles is a matter of speculation. A larger number of studies, often motivated by the Hf–Si bond theory, have concentrated on thin dielectric cap layers inserted between the Hf-based dielectric and the poly-Si electrode. Success with this approach has been mixed, again weakening the Hf–Si bond theory. For example, Si3 N4 [188–190], SiC:H [190] and HfON [196] cap layers lead to only minor Vt improvement. Unacceptably thick ∼10 Å SiO2 caps are required for improvement by 0.3 V [197] (though dissimilar results have been reported [190]). For physically and electrically thinner Al2 O3 caps, reported improvements scatter widely around 0.3 V, from 0.1 to 0.7 V [188, 195, 198–201], indicating process control issues. Compared to Al incorporation during deposition of the Hfbased dielectric, the cap layer approach has the advantage of a potentially easier integration path for selective implementation in pFETs, improving pFETs without nFET degradation as shown schematically in Fig. 6.28. Recently, AlN, Al2 O3 , and nitrided Al2 O3 capping layers for poly-Si/HfSiO pFET Vt improvement were evaluated in detail [193–195]. It was shown that AlN can reproducibly ensure sufficient Vt improvement by ∼0.3 V at very low cap thickness (4–5 Å) and high effective permittivity (keff ∼ 15, i.e., ∼1 Å electrical thickness) (Fig. 6.29, left). In the context of this chapter it is important to note that both AlN

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Fig. 6.29. Left: Near-symmetric pFET and nFET split C–V characteristics for poly-Si/4 Å AlN/20–30 Å HfSiO, with AlN removed from the nFETs, on SiO2 and SiON interfaces compared to non-capped HfSiO and to 25 Å SiON. Center: TEM image from poly-Si/4 Å AlN/30 Å HfSiO/SiON after 1070◦ C, 1 s, anneal. Right: TEM electron energy loss spectroscopy (TEMEELS) depth profiles from the same sample; “Si(O)” = Si bonded to O. AlN caps interdiffuse with HfSiO, accompanied by partial crystallization [193–195]

and Al2 O3 capping layers completely interdiffuse with the HfSiO during dopant activation anneals (Fig. 6.29, center and right). Al and N ions thus are incorporated at the high-k/SiON interface or in the interfacial SiON layer itself. Interestingly, such interdiffused stacks employing AlN caps reduce hole mobility only slightly, while Al2 O3 caps caused more severe mobility loss (though good performance with Al2 O3 caps has been demonstrated in other studies [198, 199]). To rationalize better mobility with AlN than with Al2 O3 , it was speculated that Al and N in an appropriate chemical state may deactivate each other in terms of fixed charge formation in/near the SiO(N) channel interface layer, reducing Coulomb scattering. Thin dielectric underlayers, inserted between the Hf-based dielectric and the silicon channel, are yet another related option to tune threshold voltages. This approach has rarely been discussed in the literature. However, for HfO2 –Al2 O3 or HfO2 –Y2 O3 bilayer stacks, the bottom oxide in contact with the interfacial SiO2 layer was recently shown to determine Vfb /Vt , provided that interdiffusion is prevented [202]. This result has important implications for the previously discussed strategies of Al incorporation into the Hf-based dielectric and of Al-based capping layers: Likely, substantial amounts of Al need to come into contact with the interfacial SiO2 layer to achieve the desired Vt improvement. As discussed above, in-diffusion of Al-based capping layers indeed occurs during dopant activation anneals (Fig. 6.29, right) [194, 195]. Recently, it was shown quite conclusively for stacks composed of bilayers of HfO2 , Al2 O3 , and Y2 O3 that the bottom layer in contact with the interfacial SiO2 determines Vfb /Vt [202]. It thus appears that Al introduction into the Hf-based gate stack is effective in reducing pFET Vt , provided that the Al comes into contact with the bottom interfacial SiO2 layer in the fully processed device. There, the relatively electronegative Al appears to create negative charges or dipoles that shift device characteristics to more positive voltages. Interestingly, when using electropositive metals such as La, Dy, or Mg instead, device characteristics shift in the opposite direction, beneficial for nFET Vt . This has been demonstrated using both metal oxide cap layers [203–205]

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and metal introduction into the Hf-based dielectric itself [206, 207]. Again, electrical characteristics are likely determined by the metal ions that come into contact with the bottom SiO2 interface layer after thermal processing. However, the exact chemical state of the metal ions that induce the electrical shift so far remains unknown.

6.4 Conclusion The silicon surface and thin silicon oxide films have been the subject of a tremendous research effort for several decades, driven by the technological and economic success of the MOSFET. Using the powerful techniques of surface science, fascinating structural and chemical details underlying silicon cleaning and oxidation have thus been revealed. True scientific understanding is thus available to guide the development of novel wafer processing techniques and tools for chip manufacturing. The recent advent of high-k gate dielectrics has added an entirely new dimension to silicon/silicon oxide research: How do metal precursors interact with the surface during growth? What is the atomic structure of the silicon oxide/high-k interface? What is the thermal behavior of this interface? Can we understand the electrical impact of metal atoms in contact with or inside the interfacial silicon oxide layer based on fundamental chemical concepts? Silicon and silicon oxide research will continue to go hand in hand with continued scaling of the MOSFET. And even once MOSFET scaling finally has to stop, and when entirely new device concepts (“beyond Moore”) are needed to further increase circuit functionality and performance, silicon will remain the basic material of information technology. This ensures that silicon and silicon oxide will pose exciting new scientific challenges for decades to come.

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193. M.M. Frank, V.K. Paruchuri, V. Narayanan, N. Bojarczuk, B. Linder, S. Zafar, E.A. Cartier, E.P. Gusev, P.C. Jamison, K.-L. Lee, M.L. Steen, M. Copel, S.A. Cohen, K. Maitra, X. Wang, P.M. Kozlowski, J.S. Newbury, D.R. Medeiros, P. Oldiges, S. Guha, R. Jammy, M. Ieong, G. Shahidi, in 2005 IEEE VLSI-TSA, International Symposium on VLSI Technology (VLSI-TSA-Tech), Proceedings of Technical Papers, 2005, p. 97 194. K.L. Lee, M.M. Frank, V. Paruchuri, E. Cartier, B. Linder, N. Bojarczuk, X. Wang, J. Rubino, M. Steen, P. Kozlowski, J. Newbury, E. Sikorski, P. Flaitz, M. Gribelyuk, P. Jamison, G. Singco, V. Narayanan, S. Zafar, S. Guha, P. Oldiges, R. Jammy, M. Ieong, in VLSI Technology Digest, 2006, print edition p. 202, online edition p. 160 195. M.M. Frank, K.-L. Lee, V. Narayanan, B.P. Linder, E.A. Cartier, V.K. Paruchuri, P.C. Jamison, M.W. Copel, N.A. Bojarczuk, P.L. Flaitz, M.A. Gribelyuk, R. Jammy, S. Guha (to be published) 196. T. Sakoda, M. Yamaguchi, H. Minakata, M. Nakamura, M. Fukuda, Y. Sugiyama, Y. Nara, in International Workshop on Dielectric Thin Films for Future ULSI Devices, 2004 197. M. Miyamura, K. Masuzaki, H. Watanabe, N. Ikarashi, T. Tatsumi, Jpn. J. Appl. Phys. Pt. 1 43, 7843 (2005) 198. H.-S. Jung, J.-H. Lee, S.K. Han, Y.-S. Kim, H.J. Lim, M.J. Kim, S.J. Doh, M.Y. Yu, N.-I. Lee, H.-L. Lee, T.-S. Jeon, H.-J. Cho, S.B. Kang, S.Y. Kim, I.S. Park, D. Kim, H.S. Baik, Y.S. Chung, in Symposium on VLSI Technology Digest of Technical Papers, 2005, p. 232 199. H.-S. Jung, S.K. Han, H. Lim, Y.-S. Kim, M.J. Kim, M.Y. Yu, C.-K. Lee, M.S. Lee, Y.-S. You, Y. Chung, S. Kim, H.S. Baik, J.-H. Lee, N.-I. Lee, H.-K. Kang, in VLSI Technology Digest, print edition, 2006, p. 204 200. W.S. Kim, S. Kamiyama, T. Aoyama, H. Itoh, T. Maeda, T. Kawahara, K. Torii, H. Kitajima, T. Arikado, in IEDM Technology Digest, 2004, p. 833 201. H.J. Li, M.I. Gardner, IEEE Electron Device Lett. 26, 441 (2005) 202. K. Iwamoto, A. Ogawa, Y. Kamimuta, Y. Watanabe, W. Mizubayashi, S. Migita, Y. Morita, M. Takahashi, H. Ito, H. Ota, T. Nabatame, A. Toriumi, in VLSI Technology Digest, 2007, p. 70 203. V. Narayanan, V.K. Paruchuri, N.A. Bojarczuk, B.P. Linder, B. Doris, Y.H. Kim, S. Zafar, J. Stathis, S. Brown, J. Arnold, M. Copel, M. Steen, E. Cartier, A. Callegari, P. Jamison, J.-P. Locquet, D.L. Lacey, Y. Wang, P.E. Batson, P. Ronsheim, R. Jammy, M.P. Chudzik, M. Ieong, S. Guha, G. Shahidi, T.C. Chen, in VLSI Technology Digest, 2006 204. H.N. Alshareef, H.R. Harris, H.C. Wen, C.S. Park, C. Huffman, K. Choi, H.F. Luan, P. Majhi, B.H. Lee, R. Jammy, D.J. Lichtenwalner, J.S. Jur, A.I. Kingon, in VLSI Technology Digest, 2006 205. H.N. Alshareef, M. Quevedo-Lopez, H.C. Wen, R. Harris, P. Kirsch, P. Majhi, B.H. Lee, R. Jammy, D.J. Lichtenwalner, J.S. Jur, A.I. Kingon, Appl. Phys. Lett. 89, 232103 (2006) 206. X.P. Wang, C. Shen, M.-F. Li, H.Y. Yu, Y. Sun, Y.P. Feng, A. Lim, H.W. Sik, A. Chin, Y.C. Yeo, P. Lo, D.L. Kwong, in VLSI Technology Digest, 2006 207. X.P. Wang, M.F. Li, A. Chin, C.X. Zhu, J. Shao, W. Lu, X.C. Shen, X.F. Yu, R. Chi, C. Shen, A.C.H. Huan, J.S. Pan, A.Y. Du, P. Lo, D.S.H. Chan, D.-L. Kwong, Solid State Electron. 50, 986 (2006)

7 Enhanced Carrier Mobility for Improved CMOS Performance P.M. Mooney

7.1 Introduction The amazing advancements achieved to date in complementary metal- oxide-silicon (CMOS) technology have come primarily from scaling, i.e., from reducing the critical dimensions of the transistors. Today’s microprocessor chips, for example, have more than 100 million transistors, with gate lengths smaller than 100 nm. This has been accomplished by advances in photolithography, innovations in the fabrication processes, and the use of new materials such as copper interconnections instead of aluminum and novel high dielectric constant materials for the gate insulator. Because it has become increasingly difficult to further reduce critical dimensions such as gate oxide thickness, alternative methods of improving transistor performance are also being employed. One important approach is to increase the electron and hole mobility. Various ways of achieving enhanced carrier mobility in CMOS technology are discussed in this chapter. Space limitations do not allow a comprehensive review; therefore, only a few examples are given to illustrate the different approaches. Research on materials and device structures leading to demonstrations of enhanced carrier mobility in Si, Ge, and Si1−x Gex under biaxial strain is presented first. This work includes both methods where the strain is global, i.e., over the entire wafer surface, and others which result in tiny strained islands that are defined lithographically. Other methods of achieving enhanced carrier mobility in CMOS devices, including recent implementations of local uniaxial strain, are discussed in the final section.

7.2 Enhanced Carrier Mobility in Si under Biaxial Tensile Strain The carrier mobility in a semiconductor derives from the band structure of the material; thus a modification of the semiconductor band structure usually changes the

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mobility of one or both charge carriers. Theoretical calculations predict higher mobility for both electrons and holes in silicon under biaxial tensile strain [1–6]. Biaxial tensile strain removes the 6-fold degeneracy in the conduction band, lowering the energy of the two Δ valleys having electrons with a lower in-plane effective mass with respect to the four Δ valleys having electrons with a higher in-plane effective mass. This energy splitting reduces intervalley scattering resulting in higher electron mobility. Biaxial tensile strain also removes the valence band degeneracy at the Gamma-point and shifts the spin-orbit band, thus increasing the hole mobility. When a thin layer of one material is grown epitaxially on a substrate having the same crystal structure but a slightly different lattice constant, the lattice constant of the thin layer expands or contracts to match that of the underlying substrate. Thus the epitaxial layer is under biaxial strain in the plane of the wafer. Provided the thickness of the epitaxial layer is less than the critical thickness for the introduction of misfit dislocations, the layer is said to be pseudomorphic to the substrate, i.e., it is fully strained and essentially defect-free. However, when the layer thickness exceeds the critical thickness, 60◦ misfit dislocations that relieve the strain in the epitaxial layer are formed at the interface between the film and the substrate. The degree of strain relaxation is proportional to the misfit dislocation density. A fully strain-relaxed epitaxial layer has the in-plane lattice constant of a bulk crystal of the same material and it has the full symmetry of the bulk crystal. The misfit dislocations lying at the layer/substrate interface terminate in threading arms that extend to the surface of the epitaxial layer. Unfortunately, the very high threading dislocation density in mismatched layers that are substantially relaxed often makes them unsuitable for device applications. In order to achieve pseudomorphic (defect-free) strained layer structures suitable for device applications, both a substrate and an epitaxial layer having the required lattice mismatch and the required band offsets for the particular application must be available. In the case of Si and Ge, for example, the lattice mismatch is about 4%, too large to achieve a planar pseudomorphic film of Ge on a Si substrate or vice versa. Thus, to grow a planar strained Si or Ge layer, we need a Si1−x Gex substrate, which has a lattice constant varying between that of pure Si and that of pure Ge as the Ge fraction of the alloy is varied. Unfortunately, high-quality crystalline Si1−x Gex for use as substrates is not available. Therefore extensive research has been done on Si1−x Gex “virtual substrates”, i.e., strain-relaxed Si1−x Gex buffer layers grown on Si substrates [7]. For example, a strain-relaxed Si0.75 Ge0.25 buffer layer or “virtual substrate” has an in-plane lattice parameter about 1% larger than that of Si. Thus a Si layer under biaxial tensile strain of about 1% can be grown on such a substrate. The cross section of a pseudomorphic Si layer grown on a strain-relaxed SiGe buffer layer is shown schematically in Fig. 7.1. 7.2.1 Devices Both modulation-doped field-effect transistors (MODFETs) [8, 9] and metal- oxidesilicon field-effect transistors (MOSFETs) [10–17] have been fabricated from Si layers under biaxial tensile strain. As shown in Fig. 7.2(a), significant electron mobility

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Fig. 7.1. Schematic diagram showing the cross section of a strained Si layer grown on a strainrelaxed Si1−x Gex buffer layer

enhancement has been found in MOSFETs at low strain, a factor of 1.5–2.3 for strain in the range of 0.4–1.9% [11, 12]. As shown in Fig. 7.2(b), hole mobility enhancement factors are somewhat lower than for electrons, 1.0–1.4 for tensile strain in the range 1.0–1.9% [12, 13]. Tensile strain of at least 1% is required to overcome hole mobility degradation, which was not predicted by theory. The advantages of strained Si have been combined with the advantages of silicon-on-insulator (SOI) substrates. Strained Si devices fabricated on strain-relaxed SiGe-on-insulator (SGOI) substrates have been demonstrated [14, 15]. Similarly enhanced electron and hole mobility was observed for strained Si devices on strained-silicon-on-insulator (SSOI) wafers fabricated by transferring the strained Si layer from the virtual substrate using wafer bonding methods [16, 17]. 7.2.2 Strain-Relaxed SiGe Buffer Layers The achievements described above are the result of many years of device research as well as even more years of materials research. The latter includes research from the 1970s through the 1990s on the epitaxial growth of Si and SiGe alloys and on the behavior of the misfit dislocations that are introduced to relieve the lattice mismatch strain between the epitaxial film and the substrate. Values of the low temperature electron mobility in a modulation-doped strained Si layer in the range 1– 5 × 105 cm2 /volt-sec were first reported in the early 1990s [18–22]. The room temperature electron mobility in similar modulation-doped strained Si structures was found to be 2800 cm2 /volt-sec, five times higher than the value in Si inversion lay-

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Fig. 7.2. Effective mobility for (a) electrons, and (b) holes in MOSFETs fabricated from Si under biaxial tensile strain vs. strain or equivalent Ge fraction in a fully relaxed SiGe buffer layer [13] (© 2003 IEEE)

ers in MOSFET structures [23]. A key factor in achieving these extraordinarily high values was the development of compositionally graded, strain-relaxed SiGe buffer layers having a low (<108 cm−2 ) threading dislocation density [7, 24–26]. The modulation-doped structures were grown by various epitaxial methods, including molecular beam epitaxy (MBE), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD) and low-pressure chemical vapor deposition (LPCVD). Both the growth temperature and the grading rate (the layer thickness over which the alloy composition was increased) depended

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on the epitaxial growth method; and both step-wise and linearly graded structures were used. Although the microstructure of the material changes with growth temperature [27], the value of the low-temperature electron mobility achieved is insensitive to the growth parameters, provided the threading dislocation density is sufficiently low. In order to achieve a high degree of strain relaxation with a low density of threading dislocations, graded buffer layers are typically 2–4 μm thick. Because Si1−x Gex has a lower thermal conductivity than Si, self-heating effects are observed in strained Si CMOS devices fabricated on step-graded buffer layers [28, 29]. Graded buffer layers also have a cross-hatch surface pattern that is created by the surface steps associated with the 60◦ misfit dislocations. A typical value for the RMS surface roughness measured by atomic force microscopy is ∼6 nm when the Ge fraction is 15%, but it increases significantly as the Ge fraction is increased. The surface of the relaxed Si1−x Gex buffer layer can be planarized prior to the growth of the active device layers using chemical–mechanical polishing methods. However, the polishing step adds to the cost of fabrication, as does the growth of such a thick Si1−x Gex buffer layer. For these reasons, alternative methods to achieve a much thinner relaxed Si1−x Gex buffer layer have been investigated. Dislocation multiplication, the nucleation of multiple dislocations from a single nucleation source, occurs in graded buffer layers, which are grown under very clean conditions [24–26, 30]. This suggests that there are relatively few dislocation nucleation sources present and that thinner layers would relax to a greater degree if additional dislocation nucleation sources could be introduced [31]. One approach, using MBE, employs a special low temperature (∼200◦ C) growth step that introduces defects which are dislocation nucleation sources [32–36]. Another approach, also using MBE, employs plasma cleaning prior to growth [37]. Ion-implantation of hydrogen or helium has also been used to introduce dislocation nucleation sources in a controlled way [38–44]. In this method, a metastable pseudomorphic Si1−x Gex layer is first grown on Si(001) at low temperature (500– 600◦ C). The layer must be thin enough that no strain relaxation occurs during growth, but thick enough to exceed the critical thickness for strain relaxation at higher temperatures. Hydrogen or helium is then implanted at or below the Si1−x Gex /Si interface. After annealing at ∼800◦ C in a He ambient, both spherical defects in the implanted region and a network of misfit dislocations at the interface, which relieve the strain in the Si1−x Gex layer, are observed. The degree of implantation-induced strain relaxation depends upon the layer thickness, as shown in Fig. 7.3. The strain relaxation mechanism depends on the He dose and implantation energy, i.e., the depth of the He atoms below the SiGe/Si interface [40]. Choosing optimum He implantation conditions results in a regular array of misfit dislocations after annealing, as shown in the transmission electron micrograph (TEM) in Fig. 7.4, as well as a low (≤1 × 107 cm−2 for the optimum He implant dose) threading dislocation density that is homogeneous across the wafer [42, 43]. Because only a few dislocations are nucleated at each implantation-induced defect, large dislocation pile-ups are not observed and the surface is smooth with a cross-hatch pattern as shown in Fig. 7.5. Typical root

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Fig. 7.3. Strain relaxation of pseudomorphic Si0.8 Ge0.2 layers grown in different reactors, as indicated by squares, circles, and triangles. Samples were annealed at 800◦ C or 850◦ C for at least 10 min. Open symbols are areas of the wafer that were not implanted. Solid symbols are areas that were implanted with 1 × 1016 cm−2 helium ions at a depth of 140–200 nm below the SiGe/Si interface [42]

Fig. 7.4. Dark field plan view TEM showing both the regular array of misfit dislocations running in perpendicular 110 directions at the SiGe/Si interface of a 104 nm-thick Si0.8 Ge0.2 layer and the He-induced defects (round features) lying below the interface [44]

mean square roughness values measured by atomic force microscopy are 0.2–0.6 nm [42], about one-tenth that found for graded buffer layers having a similar in-plane lattice parameter. Both MODFETs [45] and MOSFETS [46, 47] fabricated with implanted and annealed Si1−x Gex buffer layers have characteristics comparable to those of devices fabricated with graded buffer layer substrates. Although the wafer surfaces were somewhat rougher after growth of a second SiGe layer and a strained Si layer,

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Fig. 7.5. AFM image of the surface of an implanted/annealed Si1−x Gex layer. The long straight-line features, steps on the wafer surface resulting from misfit dislocation glide, run in perpendicular 110 directions. The image is 15 μm × 15 μm [42]

the roughness is still 3–4 times less than for comparable graded buffer layers [47]. MOSFETs having enhanced mobility and low off current have been fabricated on both H-implanted [46] and He-implanted buffer layers [47]. The latter work included short channel (as low as 0.05 μm) devices having a linear drain current 1.8 times larger than that of control bulk Si devices and an excellent yield of devices having low subthreshold leakage current. These device results demonstrate the excellent quality of implanted-annealed SiGe layers. 7.2.3 SGOI and SSOI Substrates The advantages of Si under biaxial tensile strain can be combined with those of SOI substrates by fabricating SGOI and SSOI substrates. Several different methods to fabricate SGOI from a relaxed SiGe buffer layer have been implemented. One group fabricated SGOI substrates by means of a SIMOX-like process, i.e., implantation of oxygen below the surface of the SiGe buffer layer and then annealing at high temperature (>1300◦ C) to form a layer of SiO2 [48, 49]. Apparently this method works only for SiGe buffer layers having low (∼10%) Ge. Another approach uses dry oxidation at high temperature (1000–1300◦ C) after deposition of a pseudomorphic SiGe layer with low Ge content [50–52]. During oxidation, part of the SiGe layer is consumed to form SiO2 . The Ge atoms are rejected from the oxide, thus increasing the Ge fraction of the remaining SiGe layer. The strain in the SiGe layer is partially relaxed during oxidation without introducing a significant number of dislocations. Raman spectroscopy shows that a strained Si cap layer grown on such a structure has about 1% tensile strain. The quality of these substrates is demonstrated by the characteristics of MOSFETs fabricated with them [14, 51]. Wafer bonding and layer transfer is another very promising method to fabricate SGOI substrates with higher Ge content, since they are fabricated from strain-

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Fig. 7.6. Diagram showing fabrication steps for bonded SGOI substrates [53]. © 2001 AIP, reprinted with permission

relaxed, graded Si1−x Gex buffer layers [53, 54]. The fabrication sequence, shown schematically in Fig. 7.6, is similar to the so-called “smart cut” method. Process steps include implantation of hydrogen into the strain-relaxed Si1−x Gex buffer layer, then bonding the implanted wafer to a Si wafer with a SiO2 layer on top, then annealing to split the SiGe layer and strengthen the bonded interface, and finally epitaxial growth of the strained Si device layers on the bonded SGOI substrate. Key process steps not shown explicitly in Fig. 7.6 include chemical–mechanical polishing to planarize the surface of the relaxed SiGe buffer layer and subsequent cleaning of the polished surface prior to bonding the SiGe buffer layer and again after layer splitting before growing the device layers. Temperature dependent Hall effect measurements performed on modulation-doped structures grown simultaneously on a polished SiGe buffer layer and on a polished SGOI substrate having the same SiGe alloy composition show the presence of a two-dimensional electron gas and identical electron mobility, ∼2000 cm2 /Vsec at room temperature [53]. This indicates that the quality of the bonded SGOI wafer is the same as the relaxed SiGe buffer layer from which the SGOI wafer was fabricated. Grind and etch-back processes have also been implemented to fabricate bonded SGOI substrates [54]. Etch-stop layers are used in this method rather than polishing to control the final thickness of the bonded SGOI layer.

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A planarization step prior to the growth of the layers to be transferred is needed to achieve a sufficiently smooth surface for wafer bonding [54]. MOSFETs fabricated on SGOI also show mobility enhancement which is similar to that found for strained Si devices on bulk strain-relaxed SiGe buffer layers [15, 55]. The effective electron mobility was enhanced by 50% in strained Si MOSFETS fabricated on a bonded SGOI substrate having 15% Ge [55], which is comparable to the results for strained Si MOSFETs on thick relaxed SiGe buffer layers on bulk Si substrates [11, 12]. Hole mobility enhancements of 15–20% were found at low vertical field in MOSFETs fabricated on bonded SGOI substrates having 25% Ge [55]. However, at high vertical field there is negligible mobility enhancement, indicating that SGOI wafers with higher Ge content are needed, just as they are for devices on bulk strain-relaxed SiGe buffer layers. An advantage of this method is that a Si1−x Gex layer of any alloy composition can in principle be transferred to fabricate SGOI substrates. Strained Si layers directly on SiO2 (SSOI) were fabricated using a process in which the strained Si layer is grown prior to wafer bonding. After layer transfer, all the SiGe is removed by selective etching [16, 54, 56]. Since the transferred strained Si layer is very thin, these substrates allow for the fabrication of fully-depleted MOSFETs [17, 57]. We note that, since the transferred layers are grown on strain-relaxed SiGe buffer layers, their defect density is the same as that of the original SiGe buffer layer grown on the bulk Si substrate. Although significant enhancements of MOSFET characteristics from increased electron and hole mobility have been demonstrated, there are still challenges for very large scale integration (VLSI) applications. Device fabrication with strained Si wafers is a major challenge, since some fabrication processes require temperatures exceeding 1000◦ C. Provided the Si layer is thin enough, it will remain fully strained. However, if the Si layer thickness exceeds the critical thickness, misfit dislocations are easily formed at the strained Si/SiGe buffer layer interface during growth of the strained Si layer [20, 21] or during high-temperature processing steps [58] by glide of threading dislocations originating in the SiGe buffer layer. While the misfit dislocation density may be low enough that only a small fraction of the strain is relaxed, these defects can reduce the carrier mobility [20, 21, 59] and device yield [60]. The higher the Ge fraction of the substrate, the thinner the strained Si layer must be, and thus the process window narrows significantly as the strain increases. These constraints determine the maximum biaxial strain that can be achieved, and thus the corresponding mobility enhancement. A further difficulty is that the diffusion of ntype dopant atoms is enhanced in Si1−x Gex . The degree of enhancement increases as the Ge fraction of the alloy increases and n-type dopant diffusion is therefore very difficult to control in very small strained Si devices. The latter problem is avoided when SSOI substrates are used [16, 17, 54, 56]. From the device results cited above, it is clear that the defect density in these different types of experimental wafers is below the threshold for mobility degradation in test devices [59]. However, to achieve the necessary device yield for VLSI applications, a major challenge has been to further reduce the density of threading dislocations and to achieve a uniform defect density over the entire wafer surface

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by eliminating dislocation pile-ups (regions of high threading dislocation density) in strain-relaxed buffer layers and SGOI substrates. This is more easily achieved when the Ge fraction, x, of the Si1−x Gex alloy is <0.25, corresponding to strain of <1% in the Si layer. It was pointed out recently that stacking faults are also often present in strain-relaxed SiGe layers [61, 62]. The best graded buffer layers evaluated had a threading dislocation density in the 105 cm−2 range, a density of planar defects (stacking faults) in the 102 cm−2 range, and dislocation pile-ups below the detection limit (<5 cm−2 ); the best SGOI wafers investigated had a threading dislocation density in the 106 cm−2 range and both planar defects and dislocation pileups were below the detection limit of the measurement, i.e., <5 cm−2 [52, 62]. 7.2.4 Defect-Free (Elastic) Strain Relaxation All the examples discussed above involve plastic strain relaxation in which strain is relieved by the introduction of misfit dislocations. Several novel methods for producing strained Si layers by means of elastic strain relaxation, without defect introduction, have been proposed recently. One method utilizes a so-called “compliant substrate” that has an upper layer that can expand or contract to accommodate the different lattice constant of the epitaxial layer to create islands of Si under tensile strain [63–65]. In this method a compressively strained SiGe layer grown pseudomorphically on a Si substrate was transferred to a compliant film of borophosphorosilicate glass (BPSG) deposited on a Si substrate by wafer bonding using the methods described above. The SiGe layer was then patterned into arrays of square islands. Upon heating the bonded wafer to ∼800◦ C, the SiGe islands relaxed elastically, i.e., the viscous compliant layer allowed defect-free relaxation of the strain in the SiGe islands. While buckling was a problem for larger islands, smaller ones remained flat. A tensile strained Si cap layer was then grown on the strain-relaxed SiGe islands to form SGOI structures. To form SSOI structures, the initial pseudomorphic strained SiGe layer was capped with an unstrained Si layer. The wafer was then bonded and patterned to form Si/SiGe islands. During annealing, the SiGe/Si structure relaxed elastically to the lattice parameter of the thicker SiGe layer, thus straining the thinner Si layer. The SiGe layer (the top layer after bonding) was then removed, leaving the SSOI island. Fully depleted SSOI n-channel MOSFETs with 60% mobility enhancement, comparable to that achieved on conventional strained Si substrates having a strain-relaxed SiGe x = 0.15 layer, were fabricated with these structures [65]. Another method for fabricating strained Si structures by means of elastic strain relaxation is the growth of a SiGe layer by UHVCVD on an array of Si slabs, each supported by a single SiO2 pedestal, that were fabricated from an SOI wafer [66, 67]. A single crystal SiGe layer grows epitaxially on the exposed surfaces of the Si slab as well as on the exposed surface of the Si substrate. The resulting SiGe/Si/SiGe slab is essentially free-standing (Fig. 7.7), and thus the strain relaxation can be described by a linear elastic model in which a force balance between the Si and SiGe layers of the structure is determined by their lattice mismatch and relative thickness [67]. Because of the vertical symmetry of the layer structure, bending of the slab can be

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Fig. 7.7. A Si0.8 Ge0.2 layer grown on a Si slab supported by an SiO2 pedestal. The faceting of the SiGe at the edges of the slab and at the base of the pedestal indicates single crystal growth [66]

Fig. 7.8. 004 triple-axis X-ray map showing the Bragg angle of lattice planes parallel to the wafer surface. The larger Bragg angles for the SiGe and Si layers of the free-standing slab compared to the SiGe on the substrate and the Si substrate indicate that the slab layers have a smaller out-of-plane lattice constant and therefore a larger in-plane lattice constant. These data show that the strain in the SiGe slab layer has largely relaxed and the Si slab layer is under tensile strain [66]

neglected. X-ray diffraction measurements of arrays of identical features (Fig. 7.8) show the shift of the Bragg angles of the SiGe and Si layers of the free-standing slab relative to those of the SiGe layer on the substrate and the Si substrate. The Si layer of the slab is in biaxial tension and the biaxial compression of the SiGe on the slab

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Fig. 7.9. (a) The blanket Si/SiGe/Si film is first patterned into isolated regions by etching down to the buried oxide. (b) The buried oxide layer is etched to form a free-standing Si/SiGe/Si slab supported at the center by a single SiO2 pedestal [68]

Fig. 7.10. SEM image of the free-standing Si/SiGe/Si slabs supported by a SiO2 pedestal, shown schematically in Fig. 7.9(b) [68]

is reduced compared to that of the SiGe layer on the substrate. The magnitude of the strain in both layers is in agreement with that predicted by the model [67]. Alternatively, arrays of elastically relaxed SiGe/Si/SiGe structures were fabricated by first growing a metastable pseudomorphic SiGe layer and a Si cap layer on a thin SOI wafer. The wafer was patterned to form Si/SiGe/Si islands, as shown in Fig. 7.9(a) and most of the buried oxide layer was then removed to form Si/SiGe/Si slabs supported by a narrow SiO2 pedestal, as shown in Figs. 7.9(b) and 7.10 [68]. These structures relax elastically during etching while the buried oxide is removed. Just as for growth of SiGe on free-standing Si, the resulting relaxation of the SiGe layers depends on the relative thickness of the two materials, as shown in Fig. 7.11 [67, 68]. To fabricate SGOI structures, the strain relaxed Si/SiGe/Si slabs were then oxidized and re-attached to the substrate by depositing amorphous Si to fill the space between the slab and the exposed substrate. Finally, the upper Si and SiGe layers were removed, leaving islands of SSOI [68]. Si layers having tensile strain of ∼0.0065 formed by this method are stable at device fabrication temperatures, as shown by Raman spectroscopy measurements in Fig. 7.12 The same metastable layer structures were also used to fabricate strained Si on Si (SSOS) wafers. It was found that when the SiO2 layer is entirely removed, the slab remains bonded-in-place to the substrate [69]. Annealing at 800◦ C forms a strong bond at the strained Si/Si substrate interface. Subsequent removal of the upper Si and SiGe layers leaves a strained Si layer on bulk Si as confirmed by Raman spectroscopy measurements, which also show that the strained Si slab is stable upon further rapid thermal annealing to a peak temperature of 1000◦ C [69]. These in-place bonded structures are ideal for fabricating bulk strained Si MOSFETs, since both the strain relaxation induced defects and the processing issues related to the presence of the SiGe “virtual substrate” are eliminated. Another advantage of patterned structures compared to blanket strained Si wafers is that strained Si can be used only for the

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Fig. 7.11. Percent strain relaxation of the Si1−x Gex layer in symmetric tri-layer free-standing Si/SiGe/Si features (open symbol) with data for SiGe grown on free-standing Si slabs and calculation from the force balance model [68]

Fig. 7.12. Raman spectra showing the Si–Si vibrational mode for bulk Si (dashed curve) and for SSOI islands. The shift in the peak position from the bulk Si value is proportional to the strain in the Si layer. In order of increasing intensity the strained Si samples are: as-fabricated after removal of the upper Si and SiGe layers, heated to 1070◦ C, and heated to 1000◦ C [68]

n-channel MOSFETs, thus avoiding degradation of the performance of the p-channel MOSFETs at low tensile strain.

7.3 Enhanced Hole Mobility via Biaxial Compressive Strain An important advantage of strain-relaxed graded Si1−x Gex buffer layers is that the in-plane lattice parameter of the “virtual substrate” can be adjusted over the entire

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alloy composition range between that of pure Si and pure Ge. Therefore in parallel with the development of strained Si devices, enhanced hole mobility in structures fabricated from both Ge-rich Si1−x Gex and pure Ge layers under biaxial compressive strain was also investigated. One motivating factor is that compressive strain was found to enhance hole mobility in Si and Si-rich Si1−x Gex [1]. Another is that the lighter effective mass in Ge leads to room temperature hole mobility more than three times the value in Si. Although the defect densities in graded Si1−x Gex buffer layers tend to be significantly higher at high Ge content, they remain below the threshold value that degrades hole mobility. Hole mobility of 55,000 cm2 /Vsec at 4.2 K was initially reported in modulation-doped strained Ge grown by MBE on a Si0.3 Ge0.7 graded buffer layer [70]. MODFETs having a maximum extrinsic transconductance of 125 mS/mm at room temperature were fabricated on similar MBE-grown layer structures having room temperature hole mobility of 1300 cm2 /Vsec [71]. In another example, enhanced mobility up to 1050 cm2 /Vsec at room temperature was reported for UHVCVD-grown strained Si0.6 Ge0.8 on a Si0.7 Ge0.3 graded buffer layer, the same graded SiGe buffer layer employed for strained Si devices [72]. MODFETs having a maximum extrinsic transconductance of 258 mS/mm and fT of 70 GHz were fabricated from the latter layer structures [73]. MODFETs fabricated from UHVCVD-grown strained Ge on relaxed Si0.4 Ge0.6 structures with room temperature hole mobility of 1750 cm2 /Vsec had a transconductance of 488 mS/mm, fT of 42 GHz and fmax of 86 GHz [74]. A double channel structure having both a Si layer under tensile strain for electron transport and a compressively strained Ge-rich Si1−x Gex layer for hole transport was proposed [75]. MOSFETs having compressively strained Si0.4 Ge0.6 [76] and Ge [77, 78] channels on graded buffer layers have also been fabricated. In the latter devices, hole mobility up to six times the value in bulk Si devices was reported and both hole mobility and drive current were three times higher than in strained Si devices grown on the same graded buffer layer [77]. Similarly strained Ge MOSFETs on SGOI substrates [79, 80] and strained Ge directly on Si [81, 82] were also demonstrated. Various schemes have been proposed to combine both n- and p-MOSFETs on the same strain-relaxed SiGe buffer layer or “virtual substrate”. A dual channel layer scheme consisting of a compressively strained SiGe or Ge layer capped with a Si layer under tensile strain has been implemented for MOSFETS [76, 83, 84]. An alternative approach uses patterning and selective epitaxy to fabricate n- and p-MOSFETs on different regions of the same substrate [79, 80, 85]. The presence of a strained Si cap layer simplifies device fabrication, since it allows the use of standard gate dielectrics. Devices having a buried Ge channel performed better than surface channel devices, presumably because there is less interface scattering with a buried channel structure [78]. The development of new, high dielectric constant gate insulator materials opens the door for device fabrication without the necessity of a Si cap layer to facilitate the formation of the gate oxide. With these new gate insulators and the availability of larger area bulk Ge substrates and Ge-on-insulator (GOI) substrates, the use of Ge instead of Si or strained Si or strained Ge for the fabrication of MOSFETs has also been investigated [78, 86–91]. As cited above, the hole mobility in bulk Ge is

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more than a factor of three greater than in bulk Si and the electron mobility is 2.6 times greater as well, thus making Ge attractive for both n- and p-channel devices. Space limitations do not permit a detailed discussion of this work here; nevertheless, we mention this as another approach to improved CMOS performance by using a material with higher electron and hole mobility. We note that the hole mobility in many of the strained Ge devices cited above was greater than that reported for devices fabricated in bulk Ge. Similarly, the development of new high dielectric constant gate insulator materials has also spurred the investigation of GaAs and other highmobility III–V semiconductors for field-effect transistor applications [92, 93].

7.4 Other Methods to Increase Carrier Mobility for Si CMOS Applications The availability of graded SiGe buffer layers and the SGOI and SSOI substrates derived from them and also fabricated by other methods has enabled numerous demonstrations of enhanced device performance by means of biaxially strained Si, Ge, or Ge-rich Si1−x Gex layers. However, this approach has not yet been implemented for manufacturing VLSI circuits, even for strained Si. One reason is the many materials and fabrication challenges, some of which have been described above. Another difficulty is finding a simple scheme to fabricate strained layer devices that allows for both enhanced electron and hole mobility on the same wafer. Perhaps more importantly, several other recently proposed approaches provide significant mobility enhancement and are technically simpler and therefore cost-effective to implement [94]. 7.4.1 Hybrid Crystal Orientation As mentioned above, the mobility of electrons and holes in a semiconductor derives from the band structure of the material. Due to the crystal symmetry of Si, the mobility of electrons and holes varies with the direction of the applied electric field. Therefore, the performance of MOSFETs fabricated in Si depends on the crystal orientation of the substrate. The standard crystal orientation used for CMOS technology is Si(100) where the highest electron mobility is found. However, the highest hole mobility is observed when devices are fabricated in Si(110) substrates. These mobilities are both for current flow in the 110 direction. Values lower than the maximum values are found for both holes and electrons using Si(111) substrates [95]. For example, the drive current for p-MOSFETs fabricated on bulk Si(110) substrates was increased by 45% compared to control devices fabricated on Si(100) [96]. Experimental values are consistent with recent theoretical calculations of the variation of hole mobility with crystal orientation that account for phonon-assisted scattering and surface roughness [97]. In order to obtain the highest mobility for both electrons and holes, hybrid crystal orientation substrates, as shown schematically in Fig. 7.13, were fabricated using wafer bonding and selective epitaxy methods [95, 96]. First, an SOI substrate was

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Fig. 7.13. Schematic drawing (cross section) of one type of hybrid crystal orientation substrate. The p-MOSFET is fabricated in the Si(110) regions and the n-MOSFET is fabricated in the epitaxial Si(100) regions. The shallow trench isolation (STI) and the buried oxide (BOX) are SiO2 [94]

fabricated by wafer bonding and transfer of a Si(110) layer. The wafer was then patterned and the Si(110) and SiO2 layers were removed in some regions of the wafer. Si was then grown by selective epitaxy on the exposed Si(100) regions of the bulk Si substrate to produce a planar structure. Subsequently n-MOSFETS were fabricated on the bulk Si(100) regions and p-MOSFETs were fabricated on Si(110)on-insulator regions of the wafer [95, 96]. Ring oscillators were demonstrated with gate delay reduced by 21% [95]. Although there are major design and integration challenges for combining bulk and SOI devices on the same wafer, hybrid crystal orientation technology (HOT) is very promising because the fabrication processes are compatible with current VLSI technology and no new materials are introduced to complicate fabrication processes. A simplified hybrid crystal orientation technology (SHOT) with independently oriented channels for pMOS and nMOS devices has also been demonstrated [98]. 7.4.2 Uniaxial Strain Another approach to achieve strained Si is by the local application of stress to the Si under the gate of the MOSFET [99–104]. Si under uniaxial tensile strain has been achieved by the deposition of stressed silicon nitride films over the gate structure during device processing [99–102]. More recently SiGe grown selectively in the source and drain regions of the MOSFET (see Fig. 7.14) has been shown to compress the Si under the gate and hole mobility enhancement of 50% [102]. Devices having transport along 100 are apparently more robust than devices having transport in the standard 110 direction [103]. Controlled wafer bending experiments show that larger hole mobility enhancement at low strain and high vertical field than has been demonstrated with Si under biaxial strain is possible with uniaxial compressive strain [104]. Similarly, growing silicon carbon alloys that have about 1.3% carbon results in horizontal tensile strain in the channel region [105]. A major advantage of these methods is that both tensile and compressive strain can be implemented locally on the same wafer during device fabrication. Although the magnitude of the local strain that can be achieved, and thus the performance enhancement, is limited, strain is additive and it has been demonstrated that several mobility enhancement techniques

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Fig. 7.14. Schematic drawing (cross section) of a p-MOSFET in which epitaxial SiGe is grown selectively in the source and drain regions. The lattice constant of SiGe is larger than that of Si, and thus the SiGe exerts a compressive force on the Si under the gate (G), as indicated by the arrows [94]

can be combined to achieve greater improvements in device performance with than a single method alone [103, 106, 107].

7.5 Summary It is now well established that simple scaling, the reduction of critical device dimensions, is not sufficient to maintain the performance improvements of CMOS technology required by the International Technology Roadmap for Semiconductors (ITRS) guidelines. Therefore, novel approaches and new materials are needed. An overview of the research leading to increased electron and hole mobility as a way to improve the performance of CMOS devices has been presented in this chapter. The reported performance enhancements are based primarily on the use of “new materials” such as strained Si and Ge channels that are achieved by means of engineered structures, usually employing SiGe alloys. In some approaches these structures are developed as novel substrates using methods including low temperature epitaxial techniques for the growth of blanket films as well as whole wafer bonding and layer transfer techniques. An initial concern with these approaches was that the observed performance enhancements would be lost at channel lengths below 100 nm, because of elastic strain relaxation of the gate. However, it has recently been demonstrated that the dependence of the performance enhancement on channel length is only moderate and it can therefore be sustained in future technology nodes [103]. In other approaches, e.g., to achieve Si under uniaxial compressive strain or Ge under biaxial compressive strain, fabrication processes such as selective epitaxial growth are integrated into the processing sequence for device fabrication using standard bulk crystal Si or SOI substrates. Although many of the structures discussed above may never be employed in VLSI circuits, the learning from this entire body of research is currently being applied to enhance our knowledge of semiconductor physics, to fabricate prototype

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devices that provide even better performance, and also to develop processes that are more compatible with CMOS processes already utilized in production. This body of research has clearly demonstrated the importance of strain to enhance both electron and hole mobility for CMOS applications. The local strain methods for achieving enhanced carrier mobility discussed here have already been implemented in commercial high performance CMOS integrated circuits. Specifically, the approaches involving local uniaxial strain through the use of stressed nitride films as the source of tensile strain and strained SiGe layers in the source and drain region for applying compressive strain are employed in current products. For example, Intel utilizes local uniaxial tensile strain for nMOS devices and local uniaxial compressive strain for pMOS devices in 90 nm and 65 nm high-performance single and dual core microprocessors. And both IBM and AMD have introduced strained Si with SOI technology in their 90 nm high performance microprocessors including IBM’s PowerPC 970FX chips and the multi-core AMD64 processors.

Acknowledgement The author would like to acknowledge the work of many colleagues at IBM’s Semiconductor Research and Development Center, where much of the research reviewed here was carried out.

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99. S. Tiwari et al., in IEEE International Electron Devices Meeting Tech. Dig., 1997, p. 939 100. A. Shimizu, K. Hachimine, N. Ohki, H. Ohta, M. Koguchi, Y. Nonaka, H. Sato, F. Ootsuka, in IEEE International Electron Devices Meeting Tech. Dig., 2001, p. 433 101. V. Chan et al., in International Electron Devices Meeting Tech. Dig., 2003, p. 77 102. S.E. Thompson et al., IEEE Electron Device Lett. 25, 191 (2004) 103. Q. Ouyang, M. Ieong, M. Fischetti, S. Panda, D. Boyd, K. Rim, J.A. Ott, in IEEE International Electron Devices Meeting Tech. Dig., 2004, p. 27 104. S. Thompson, G. Sun, K. Wu, J. Lim, T. Nishida, in IEEE International Electron Devices Meeting Tech. Dig., 2004, p. 221 105. K.W. Ang, K.J. Chui, V. Bliznetsov, A. Du, N. Balasubramanian, M.F. Li, G. Samudra, Y.-C. Yeo, in IEEE Electron Devices Meeting Digest, 2004, p. 7.8.1 106. J. Cai, K. Rim, A. Bryant, K. Jenkins, C. Ouyang, D. Singh, Z. Ren, K. Lee, H. Yin, J. Hergenrother, T. Kanarsky, A. Kumar, X. Wang, S. Bedell, A. Reznicek, H. Hovel, D. Sadana, D. Uriarte, R. Mitchell, J. Ott, D. Mocuta, P. O’Neil, A. Mocuta, E. Leobandung, R. Miller, W. Haensch, M. Ieong, in IEEEE International Electron Devices Meeting Tech. Dig., 2004, p. 7.3.1 107. Z. Lou, Y.F. Chong, J. Kim, N. Rovedo, B. Greene, S. Panda, T. Sato, J. Holt, D. Chidambarrao, J. Li, R. Davis, A. Madan, A. Turansky, O. Gluschenkov, R. Lindsay, A. Ajmera, J. Lee, S. Mishra, R. Amos, D. Schepis, H. Ng, K. Rim, in IEEE International Electron Devices Meeting Dig., 2005, p. 489

8 Transistor Scaling to the Limit T.-J.K. Liu and L. Chang

8.1 Introduction The steady miniaturization of the metal-oxide-semiconductor field-effect transistor (MOSFET) with each new generation of complementary-MOS (CMOS) technology has yielded continual improvements in integrated-circuit performance and cost per function for more than 40 years. Until recently, transistor scaling generally followed simple rules [1] with slight modification (Table 8.1) [2, 3] to provide for improvements in circuit speed and density with reduction in power consumption per function, while maintaining reliability and electrostatic integrity (gate voltage control of the source-to-channel potential barrier) of the device itself. As a result, MOSFET scaling was able to progress at an exponential rate [4], yielding commensurate improvements in integration, cost, and performance, with revolutionary impact to usher in the Information Age. While the basic concepts proposed in [1] have not changed, fundamental limits have imposed new boundary conditions for transistor scaling in the sub-100 nm regime, resulting in an impending power crisis and projected slowdown in the rate of transistor gate length (Lg ) reduction [3, 5]. In particular, sub-threshold leakage current considerations have caused threshold voltage (VT ) scaling to slow down dramatically below ∼0.3 volts [3, 5], which in turn has slowed the scaling of the supply voltage Vdd below 1 volt. This is because significant gate overdrive (Vdd − VT ) is needed to achieve large drive currents (for high performance) and to minimize variations in propagation delay [6] and also because Vdd should be at least ∼3× larger than |VT | for reasonable noise/variability margins to guarantee proper operation of conventional CMOS (vs. sub-threshold CMOS) circuits. As a result, active power dissipation per unit area has increased by ∼1.3× with each new generation of CMOS technology [5]. This is not the worst of it, however; due to gate-oxide thickness (Tox ) and VT scaling, passive power dissipation (due to transistor leakage currents) per unit area has increased much faster, by ∼3× with each new generation [5]. This is because the gate-oxide direct tunneling current density increases exponentially with

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Table 8.1. Guidelines for MOSFET scaling (adapted from [1, 2]). The key MOSFET design parameters are gate length Lg , equivalent gate oxide (SiO2 ) thickness Tox , source/drain extension junction depth Xj , and channel width W . ox is the permittivity of SiO2 . κ is a scaling constant > 1, historically ∼1.4. Constant electric-field (E-field) scaling was followed for MOSFET miniaturization to Lg ∼ 0.13 μm. Due to the non-scalability of transistor threshold voltage (VT ) and pn-junction built-in potential, generalized scaling (in which the electric field is allowed to increase, but the shape of the potential profile within the scaled device is conserved) has been followed for deep-sub-micron CMOS technologies. α is a different scaling constant, ∼1.15 [5]. Note that for constant-Vdd scaling, α = κ Device and circuit parameters

Constant E-field scaling: Multiplicative factors 1/κ κ 1/κ 1 1/κ 1/κ 2 1/κ 1/κ 1/κ 2 1

Device dimensions (Lg , Tox , Xj , W ) Body doping concentration (NB ) Supply voltage (Vdd ) Electric field (E) Transistor current (I ) Area (A) Capacitance (C = ox A/Tox ) Intrinsic delay (τ ∼ CVdd /I ) Power dissipation (P ∼ I Vdd ) Power density (P /A)

Generalized scaling: Multiplicative factors 1/κ ακ α/κ α α/κ 1/κ 2 1/κ 1/κ α 2 /κ 2 α2

decreasing gate-oxide physical thickness, and the source-to-drain OFF-state leakage current (IOFF ) increases exponentially with decreasing VT : IOFF ∝ 10−VT /S ,

(8.1)

where the sub-threshold swing S is the inverse slope of the transistor current IDS plotted on a logarithmic scale vs. gate-to-source voltage VGS on a linear scale: S≡

∂(log10 IDS ) ∂VGS

−1 .

(8.2)

S is typically <100 mV/decade and is fundamentally limited to be no less than (kT /q) × ln(10), which is 60 mV/decade at room temperature (kT /q is the thermal voltage.) Since direct tunneling current through the gate oxide has become a significant component of transistor leakage, Tox has not been reduced from the 90 nm to 65 nm (minimum half-pitch) CMOS technology nodes [7]. Furthermore, parasitic resistances and capacitances have increased in relative proportion to the intrinsic resistance and capacitance of the transistor and therefore are restricting gains in circuit performance [8], exacerbating the power vs. delay trade-off. Finally, increased variability in transistor performance with each new generation of CMOS technology has begun to affect manufacturing yield [9] and, ultimately, cost. Thus, continued transistor scaling will not be as straightforward in the future as it has been in the past not only because of fundamental materials and process limits [10], but also because of increasing variability. Indeed, reports on sub-35 nm Lg planar bulk

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CMOSFETs [11–15] confirm that the performance targets specified in the International Technology Roadmap for Semiconductors (ITRS) [16] will be difficult to meet using conventional transistor structures and materials. New materials and processes and non-classical transistor structures will be necessary in order to extend MOSFET scaling to sub-10 nm gate lengths. Balancing power consumption, performance, and variability will be the key challenge to sustaining the rapid growth of the semiconductor industry in order to usher in a new age of ambient intelligence and ubiquitous computing. This chapter first reviews challenges for continued planar bulk MOSFET scaling and then discusses how improvements in transistor design and advancements in materials and process technology can address these challenges to enable scaling of the MOSFET to the fundamental limit (beyond which gate control of sub-threshold leakage current is practically lost).

8.2 Planar Bulk MOSFET Scaling While it is possible to scale traditional planar bulk-like (including partially-depleted silicon-on-insulator, “PD-SOI”) MOSFET structures (Fig. 8.1(a)) down to 10 nm gate length [14], suppression of short-channel effects (manifested in increasing OFFstate leakage with increasing drain bias and with decreasing gate length) becomes very difficult and is invariably achieved at the cost of degraded ON-state performance. Design trade-offs must be made in order to maintain strong gate capacitive control of the channel relative to the other transistor terminals. As a measure of transistor scalability, the “scale length” for the conventional bulk structure has been derived empirically [17, 18]: lbulk = 0.1 Å

−1/3

2 Tox Xdep Xj

1/3

,

(8.3)

where Tox , Xdep , and Xj are the equivalent gate oxide (SiO2 ) thickness, channel depletion depth, and source/drain extension junction depth (all in Å), respectively. In order for short-channel effects (SCE) to be adequately suppressed, the transistor gate length Lg should be several times larger than the scale length. Since Tox reduction is limited due to direct tunneling leakage, bulk devices will exhibit an increasing reliance on channel engineering (e.g., “halo” or super-steep retrograde channel doping) to reduce Xdep and advanced doping techniques to form ultra-shallow source/drain junctions. Heavy (>1018 cm−3 ) doping is necessary to eliminate leakage paths far from the gate-dielectric interface and to increase body/back-gate control of the channel. For sub-100 nm gate length devices, halo doping near the source/drain regions (illustrated in Fig. 8.1(a)) is generally used to reduce the lateral extent of drain-induced electric-field penetration into the channel region and ensure that the gate voltage (rather than the drain voltage) controls the height of the source-to-channel potential barrier. A benefit of halo doping is that it provides for increasing average channel doping concentration (due to increasing overlap of the source-side and drain-side

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Fig. 8.1. Simplified schematic cross-sections of MOSFET structures: (a) conventional planar bulk, (b) ultra-thin body (UTB), (c) double-gate (DG). In practice, the source/drain regions are physically deeper or thicker away from the gate edges to reduce parasitic series resistance

halo doping profiles), hence decreasing Xdep , with decreasing gate length; this mitigates SCE and therefore variation in VT with process-induced variations in gate length. Doping concentrations approaching 1019 cm−3 will be needed to suppress SCE in bulk MOSFETs with gate lengths ≤25 nm [19]. For transistors with channel doping profiles that are fairly uniform as a function of depth, this results in significantly degraded field-effect carrier mobilities due to enhanced Coulombic scattering (in weak inversion) and enhanced phonon scattering (in strong inversion) due to the high effective transverse electric field seen by the inversion layer [20], so that incommensurate improvements in transistor drive current with gate length scaling will result [21]. In addition, leakage power will increase due to larger inverse sub-threshold slope and enhanced band-to-band tunneling junction leakage. Gains in circuit performance will be limited further due to increased pn-junction depletion capacitances. The use of gradual/uniform channel doping inevitably leads to random dopant fluctuation concerns [22]. Due to line-edge roughness and random dopant fluctuation effects, random variability in VT can become overwhelming in extremely scaled (<20 nm gate lengths) bulk-like devices [23]. The use of a super-steep retrograde channel doping profile mitigates the issues of mobility degradation due to impurity scattering and VT variation due to random dopant fluctuations (RDF) [24, 25]. (It does not mitigate the mobility degradation due to high effective transverse electric field, however.) A pulse-shaped or delta-shaped doping profile is ideal: doping is light (preferably 1017 cm−3 or less) in the surface region to provide for reasonably high carrier mobilities; heavy (>1019 cm−3 ) in a sub-surface region to suppress SCE; and moderate (<1019 cm−3 ) below the depth of the source/drain extension junctions to avoid excessive band-to-band tunneling junction leakage and depletion capacitance. Such a doping profile can be achieved by selective epitaxial growth of the lightly doped (or undoped) channel region [26–31]. The thickness of the lightly doped surface region, TSi , should be less than ∼30% of the electrical channel length, Leff , in order for SCE to be adequately suppressed [32]. As mentioned previously, accelerated scaling of Xdep will become necessary as practical limits for Tox (and Xj ) are reached, per our current understanding. Such aggressive reduction in Xdep can be achieved with the aid of forward body biasing. Device simulations have shown that even for Lg = 10 nm, a forward body bias

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can reduce Xdep substantially (by 7 nm for a forward body bias of 0.6 volts) [33]. The benefit of forward body biasing for bulk MOSFET scaling can be understood by considering the equation for VT . For the case of an n-channel MOSFET with a uniform channel doping profile, √ 2s qNB (2ϕB − VB ) 6(2ϕB − VB )Tox = VFB + 2ϕB + , (8.4) VT = VFB + 2ϕB + Cox Xdep where s is the dielectric permittivity of silicon, NB is the body dopant concentration, Cox is the gate-oxide area capacitance, ϕB is the difference between the intrinsic Fermi level and the Fermi level in the body, VFB is the flat-band voltage, and VB is the body bias. For the case of an ideal step- or rectangular-pulse-shaped profile, VT is given by [28] 3(2ϕB − VB )Tox . (8.5) VT = VFB + 2ϕB + Xdep From the above equations for VT , it can be seen that aggressive reduction in Xdep (required for gate length scaling) will make it difficult to achieve small VT (required for high-performance applications) unless forward body biasing (VB > 0 volts, for an n-channel MOSFET) is used to reduce the term (2ϕB − VB )Tox /Xdep . Note that to achieve a target VT value, Xdep for an ideal channel doping profile can be smaller than that for a uniform doping profile, which allows for scaling to shorter gate lengths. The combination of forward body biasing and super-steep retrograde channel doping can adequately suppress SCE to allow the planar bulk MOSFET structure to be scaled down to 10 nm Lg (at least, for high-performance applications which have less stringent IOFF requirements). It should be noted that a practical limit for the forward body bias is ∼0.6 volts in consideration of drain leakage due to the parasitic bipolar transistor. (CMOS latch-up is not considered to be an issue because future supply voltages will be lower than the latch-up holding voltage.) Also, supersteep retrograde channel doping is necessary to maintain a high body effect factor, γ ≡ |dVT /dVB | ∼ 0.15 for deeply scaled MOSFETs [33]. Again, a pulse-shaped channel doping profile (wherein the channel/body doping falls to a moderate level below the depth of the source/drain extension junctions) is preferable to minimize the increase in junction capacitance with forward body biasing. Reduction of the source/drain extension junction depth (Xj ) directly decreases capacitive coupling of the drain to the channel and thereby decreases drain-induced barrier lowering (DIBL) for improved short-channel control. In order to achieve ultra-shallow dopant profiles by conventional ion implantation, very low implant energies (<1 keV) or higher-mass implant species (e.g., decaborane for boron [34]) must be utilized. To improve process throughput, plasma doping [35–38] or infusion doping processes [39] may ultimately be necessary. The implanted source/drain dopants must be activated with minimal diffusion so that ultra-shallow junctions with ultra-steep doping gradients can be realized in order to achieve good shortchannel control [19]. Therefore, advanced annealing techniques such as flash-lamp annealing [40–42, 14] or pulsed-laser annealing [43–46] will likely be necessary. Coimplantation of species such as germanium (Ge) [47, 48], fluorine (F) [49–51], and/or

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carbon (C) [52–55] can help to minimize diffusion and can also enhance dopant activation, which will become increasingly important for minimizing parasitic series and contact resistances. All in all, precise (to within ∼1 nm) engineering of vertical and lateral doping profiles in the channel/body and source/drain regions will be required in order to scale the conventional bulk MOSFET structure toward 10 nm gate length. Process and materials engineering innovations will be needed to achieve sufficiently tight control of these doping profiles in a CMOS manufacturing process to allow for tuning of the trade-off between leakage power and performance with acceptable variability.

8.3 Thin-Body Transistor Structures The need for precisely controlled vertical channel and source/drain doping profiles to suppress SCE can be circumvented by physically limiting the thickness of the semiconductor. Thin-body transistor structures (Figs. 8.1(b) and 8.1(c)) can have low IOFF if the body thickness (TSi ) is less than the electrical channel length (Leff ), because this ensures that the effective channel conduction path in the OFF-state is in close proximity to the gate electrode so that its potential is strongly coupled capacitively to the gate potential (vs. the drain potential) [56, 57]. IOFF generally decreases exponentially with decreasing TSi [58]. Since leakage current can be controlled by TSi , heavy doping in the channel/body is not necessary to scale down Lg . The use of a lightly doped (≤1017 cm−3 ) channel is beneficial for minimizing VT variation due to statistical dopant fluctuations and for enhancing carrier mobilities (hence transistor drive currents) as a result of the lower effective transverse electric field in the channel inversion layer [20]. Thin-body transistors are therefore promising for achieving superior circuit performance (e.g., reduced fan-out 4 inverter delay) over traditional bulk MOSFETs [59]. The benefits improve with gate length scaling and are greater for low power technologies which have more stringent leakage specifications (Fig. 8.2). The adoption of thin-body devices in a CMOS manufacturing process presents a new set of challenges for transistor design optimization and fabrication. Foremost is the need for precise control of the physical body thickness, since leakage current varies exponentially with TSi . For TSi less than ∼5 nm, quantum confinement (energy quantization) effects make VT (hence leakage current) even more sensitive to variations in body thickness [60–62]. High levels of dopant activation (to minimize parasitic series resistance) and abrupt lateral doping profiles (to minimize statistical dopant fluctuation effects [63]) may prove to be more difficult to achieve with good control in a thin layer of semiconductor as compared with a bulk semiconductor. Careful selection and control of the doped source/drain extension lengths is necessary to optimize the trade-off between parasitic series resistance and parasitic gate capacitance, which is more significant for thin-body transistors because of the need for raised-source/drain (also known as “elevated-source/drain”) contact regions to minimize contact resistance. Finally, approaches other than channel doping (e.g., gate work function engineering [64–67] or channel length engineering [68, 69]) must

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Fig. 8.2. Comparison of fan-out 4 inverter delay (obtained through mixed-mode simulation using realistic device structures based on ITRS specifications) for various MOSFET technologies [70]. No carrier mobility enhancement is assumed

be developed to allow for VT adjustment to meet performance specifications for various applications. The specific requirements and challenges vary among the various thin-body FET designs – ultra-thin body (UTB), double-gate (DG), back-gate (BG), and tri-gate (TG). In this section, general issues are discussed for each thin-body device type. 8.3.1 Ultra-Thin Body (UTB) MOSFET The most straightforward realization of a thin-body MOSFET structure is a siliconon-insulator (SOI) device built in a very thin silicon film (Fig. 8.1(b)). This preserves the planar nature of traditional CMOS devices while providing enhanced short-channel control. From [32], an estimate of the scale length for such a device structure is Si Tox TSi , (8.6) lUTB = ox where and T refer to the dielectric constants and thicknesses of the gate oxide and silicon films, respectively. While the simple analysis in [32] neglects certain effects such as two-dimensional drain electric field penetration through the buried oxide (illustrated in Fig. 8.1(b)), it shows that the scale length can be reduced to any desired level by scaling down the silicon body thickness. As the gate length is scaled below 18 nm (beyond the 45 nm half-pitch technology node), the silicon film thickness requirement for short-channel control falls to below 5 nm. (Approximately, TSi should be less than Leff /3 [71].) In this range, fundamental issues such as source/drain series resistance, quantum mechanical shifts in threshold voltage [60], and carrier mobility degradation [72, 73] become concerns.

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Fig. 8.3. Ultra-thin body MOSFET structure with raised (or “elevated”) source/drain contact regions for reduced parasitic series resistance

Series resistance in the source and drain regions of a UTB MOSFET can be minimized by employing a raised (elevated) source/drain structure (Fig. 8.3). Such a structure can be formed by selective epitaxial growth or deposition techniques, which can result in thick source/drain regions made of crystalline silicon [74], polycrystalline silicon [71], or germanium [75]. With this approach, however, the resistance of the source/drain extension regions beneath the gate sidewall spacers is unaffected, and the parasitic capacitance between the gate electrode and the drain (i.e., the Miller capacitance) is increased, resulting in degraded circuit performance. An alternative approach for reducing series resistance is to use metallic source/ drain regions. Thin-body MOSFETs with fully silicided source/drain regions and gate lengths down to 15 nm have been reported [76], but with relatively low drive currents due to significant Schottky barrier heights (>0.2 eV) at the metal-semiconductor junctions. In order to achieve drive currents that meet ITRS trends, very low Schottky barriers (≤0.1 eV) are needed [77]. This is difficult to achieve in practice, particularly for n-channel devices, due to Fermi-level pinning by interface gap states, as evidenced with high-permittivity gate dielectrics (although improved processes can negate their effect). Also, OFF-state leakage current due to quantum-mechanical tunneling through the Schottky barrier is a fundamental issue [78] that precludes the use of Schottky-source/drain devices in low-power applications. To circumvent these issues, doped source/drain extensions – narrow and heavily doped in order to minimize series resistance and variation due to random discrete dopants [63] – will be necessary for metallic-source/drain structures. For TSi in the sub-5 nm range, the energy eigenstates of both holes and electrons in the quantum well formed by the physically thin SOI layer can be dramatically altered [60]. Quantum confinement reduces the density of states so that the device threshold voltage increases and becomes a very sensitive function of TSi . Since the VT shift is dependent upon the specific value of TSi , threshold voltage variability will be determined by the degree of manufacturing control over this dimension. Techniques for achieving uniformly thin films with atomically smooth surfaces/interfaces will be necessary to achieve tight VT distributions and also to minimize degradation in carrier mobilities due to surface roughness scattering. The reliable formation of ultrathin (<5 nm thick) SOI layers can be challenging, but has been demonstrated in the

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literature [71, 74, 75]. An alternative approach is to form the ultra-thin Si channel by epitaxial growth so that thickness control can be as fine as a single atomic layer, as in the “Silicon-on-Nothing” fabrication process developed by STMicroelectronics [79]. Recent experimental data and theoretical studies [72, 73] have shown that carrier mobility is degraded when the silicon film thickness is reduced significantly below 10 nm, due in large part to enhanced interface roughness scattering. While shifts in carrier subband occupancy due to quantum confinement can counteract this effect somewhat by reducing the average conductivity effective mass [80], very thin silicon films can be expected to have significantly degraded mobility [81]. All in all, the issues of series resistance, mobility degradation (which limit gains in transistor drive current) and quantum confinement effects (which make VT control difficult) intensify with gate-length scaling, so that it will be difficult to scale the UTB FET structure to gate lengths below 15 nm. 8.3.2 Double-Gate (DG) MOSFET The DG MOSFET (Fig. 8.1(c)) improves upon the UTB MOSFET by adding a second gate electrode at the opposite side (i.e., the back side) of the thin silicon body. This enhances gate control of the channel potential and therefore relaxes the body thinness requirement, so that quantum confinement effects and mobility degradation due to surface scattering can be mitigated. From [82], a simple expression for the scale length of a DG MOSFET is ox TSi Si 1+ Tox TSi , (8.7) lDG = 2ox 4Si Tox where and T refer to the dielectric constants and thicknesses of the gate dielectric and silicon films, respectively. From a comparison of the expressions for lDG and lUTB , it is clear that the DG MOSFET can have a larger TSi as compared with a UTB MOSFET to achieve the same scale length. It should be noted that the DG MOSFET provides nearly ideal sub-threshold swing, i.e., 60 mV/dec at room temperature. This occurs because the gate electrodes are tied together so that there is no capacitive voltage divider effect across the channel (from the front-side to the back-side of the body), i.e., the potentials at the front-side and back-side of the body are modulated together. Though the superior scalability of the DG MOSFET structure has been recognized for a long time [83], it has yet to be adopted in the manufacture of integrated circuits because it presents significant fabrication challenges. The most straightforward implementation is a modification of the planar bulk MOSFET (Fig. 8.4(a)). The second gate can be formed underneath the channel, e.g., within the buried oxide layer of a SOI wafer [84]. While such a device is simple to envision, the fabrication process required to achieve it is complex, requiring wafer bonding or selective epitaxial silicon growth (which is expensive, but will become less so as it becomes a mature process for integrated-circuit manufacture) [85–87]. Even with these exotic process steps, it is still difficult to perfectly align the front and back gates without

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Fig. 8.4. Double-gate MOSFET structures: (a) traditional planar structure, (b) vertical structure obtained by rotating the planar structure 90◦ about an axis parallel to the gate line, (c) vertical structure obtained by rotating the planar structure 90◦ about an axis parallel to the current flow direction (after [88])

introducing substantial parasitic resistive and capacitive elements. In addition, the process flow required to fabricate these device structures deviates substantially from traditional bulk MOSFET processes so that the integration of high-permittivity gate dielectrics and/or metallic gate electrodes (to reduce Tox and thereby further improve scalability) could be a major challenge. Rotation of the planar DG device structure out of the wafer plane can provide for easier fabrication. Rotation by 90◦ out of the wafer plane about an axis parallel to the gate line (Fig. 8.4(b)) results in a vertical structure through which current flows normal to the wafer surface [89]. In this structure, the gate length is determined by a deposited film thickness, which can be more controllable than a lithographydefined feature size. However, this also places a severe constraint on circuit design by offering only a single gate length on a wafer. FinFET If the planar DG device structure is instead rotated by 90◦ about an axis parallel to the direction of current flow (Fig. 8.4(c)), a conventional process flow sequence can be used to fabricate DG MOSFETs with perfectly aligned front and back gates as follows: First, a SOI substrate is patterned to form narrow Si body regions (“fins”) by conventional lithography and etch techniques. Note that a thick dielectric layer can be used as a hard mask for the fin in this process. Afterwards, the gate-dielectric and gate-electrode layers are formed over the fins. Then, the gate layer is patterned to form linear gate electrodes that straddle the fins, gating the vertical sidewalls. If there is not a thick dielectric hard mask layer on the top surfaces of the fins, then the top surfaces are also gated; in this case, the resultant transistor structures are commonly referred to as “multi-gate” (MuG) FETs. In order to maximize carrier mobilities and device reliability, a sacrificial oxidation step can be used to remove residual etch damage at the surfaces and high-temperature annealing and/or hydrogen annealing

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Fig. 8.5. (a) FinFET structure, and (b) exemplary layout of a multiple-fin FinFET (with large effective channel width), depicting its similarity to a conventional transistor layout

can be used to smoothen the fin sidewalls (and to round the corners, in the case of a MuGFET) [90–92]. The “FinFET” structure (Fig. 8.5(a)) [93–95] offers the superior scalability of the DG MOSFET structure together with a process flow and layout similar to that of the conventional planar MOSFET. Its relative ease of fabrication has led to successful demonstrations at gate lengths well below 10 nm [96–98] with good control of SCE, so that the FinFET (and its variants, e.g., the MuGFET and Omega-FET [99, 100]) has emerged as the most promising non-classical MOSFET structure proposed to date. The effective channel width (Weff ) of a single-fin FinFET (Fig. 8.5(a)) is 2 × Hfin (where Hfin is the fin height). (This is the case even if the top fin surface is gated, because volume inversion occurs within the narrow, lightly doped fin in the ON state, so that gating of the top fin surface does not significantly increase the transistor drive current [101].) FinFETs of various effective channel widths can be practically achieved by using multiple fins in parallel [93], as shown in Fig. 8.5(b), but with variations limited to increments of 2 × Hfin . Note that if a conventional lithography process of minimum pitch P is used to define the fins, Hfin must be ≥P /2 in order to achieve a layout efficiency (effective channel width per unit layout area) at least as good as that of a planar bulk MOSFET, i.e., Weff ≥ P . Considering that the minimum gate length Lg,min has been ∼P /4 historically, this means that Hfin ≥ 2 × Lg,min ≥ 3 × Wfin . In other words, the fin aspect ratio Hfin /Wfin must be ≥3. (This simplistic analysis assumes that the source/drain contact-to-gate spacing in a FinFET is the same as for a planar bulk MOSFET, so that their source/drain areas are comparable. A more detailed analysis [102] concludes that higher fin aspect ratios are actually required for the FinFET to have layout efficiency comparable to that of a planar bulk MOSFET.) Taller fins allow for improved layout efficiency, but with a trade-off not only in process control (since it is more difficult to achieve taller fins with vertical sidewalls) but also in design flexibility. Assuming that Hfin /Wfin = 3, Weff is limited to an integer number of 4×Lg,min increments. If a spacer lithography process [103] is used to define fins with tighter pitch, then the fin aspect ratio can be proportionately reduced (or, alternatively, the layout area efficiency can be improved). Note, however, that the maximum tilt angle for source/drain ion implantation (to avoid shadowing

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by an adjacent fin) decreases with decreasing fin pitch, although the fin height is proportionately reduced. In order to minimize short-channel effects, the distance between the source and drain (S/D) junctions should be uniform from the top of the fin to the bottom of the fin (i.e., the electrical channel length, Leff , should be uniform along the width of the channel). Ideally, then, the S/D dopants should be introduced at a 90◦ angle into the sidewalls of the fin. Since multiple fins are required to achieve a wide-channel FinFET, tilted ion implantation is limited to angles <60◦ to avoid shadowing, assuming that the fin height (Hfin ) is sufficiently tall to achieve a layout efficiency at least as good as that of a planar bulk MOSFET. Alternative doping techniques such as plasma doping [35–38] may ultimately be required to achieve more conformal doping of the fin sidewalls for optimal performance. Indeed, high-performance p-channel MuGFETs with source/drain extensions formed by pulsed plasma doping (PLAD) have recently been demonstrated [104]. The primary challenge for FinFET manufacture is the formation of fins with uniform and narrow width. The fin width (Wfin ) must be uniform from the top to the bottom of the fin, i.e., the fin sidewalls should be perfectly vertical; otherwise, SCE control will be degraded [105] – unless the gate electrode extends beneath the fin, as in an Omega FET [99, 100]. Wfin (which is effectively the body thickness TSi ) generally must be smaller than Lg to adequately suppress OFF-state leakage current. (Typically, TSi should be less than ∼2Leff /3 for a DG-MOSFET [95].) This places extra demands on the lithography process, which historically has been pushed to the limit to define gate electrodes of minimum controllable gate length (Lg,min ) for maximum performance. If the fins are to be defined by conventional lithography, then Lg cannot be scaled down as aggressively. A possible solution is to employ an alternative pattern-definition technique to yield fins of sub-lithographic width (i.e., smaller than Lg,min defined by conventional lithography). An example of such a technique is spacer lithography, which is advantageous for defining fine-line features (lines and spaces) with small pitch and tight line-width distribution [103]. Sub-100 nm Lg FinFETs with spacer-defined fins of 40 nm width have been demonstrated with excellent short-channel control (S < 70 mV/dec and DIBL <50 mV/V) [106]. Functional MuGFET devices and SRAM cells with spacer-defined fins of sub-20 nm width and 50 nm pitch have been demonstrated recently [107]. Another solution is to alter the device structure itself to relax the fin width (Wfin ) requirement. For example, the fin height (Hfin ) of a MuGFET can be shortened such that the portion of the gate along the top of the fin exerts adequate control over the channel potential to suppress SCE, i.e., it serves effectively as a third-gate electrode [108, 109]. This concept can be further extended to various degrees of gate electrode wrapping around the fin achieved by etching the buried oxide beneath the patterned SOI prior to gate-stack formation [110]. The culmination occurs in a surround-gate or “gate-all-around” (GAA) MOSFET [111–113] in which the gate electrode is wrapped completely around the transistor channel. In order to avoid problems due to incomplete dry-etching of the gate material from underneath the fin in the source/drain extension regions of a surround-gate device, the fin cannot be very wide. A circular cross section (i.e., a wire-like channel) provides for the best electrostatic integrity [114] and hence al-

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lows for the largest minimum channel dimension (width or height); however, if conventional lithography is used to pattern the channel, such a “wire FET” has poorer layout efficiency than a planar bulk MOSFET, because the effective channel width is π × TSi , which is generally smaller than the wire pitch P (since TSi < Lg,min ). Again, spacer lithography can be used to double the wire pitch for improved layout efficiency. Nanowire FETs with 5 nm Lg [97] or 5 nm body diameter [115] have been successfully fabricated using conventional process flows. High-performance twin-nanowire FETs with <5 nm body diameter have been demonstrated using a more complex fabrication process [116, 117]. A potential issue for FinFET technology is parasitic source/drain series resistance [118] and contact resistance [119], which can severely limit performance for sub-30 nm gate lengths [118–120]. Selective epitaxial growth or deposition to laterally thicken the source/drain contact regions (and to merge the fins in the source/drain contact regions of multi-fin devices) is necessary to mitigate this problem and provides for optimal trade-off between parasitic resistance and parasitic gate capacitance [121, 122]. While it is simplest to build a FinFET on an SOI substrate, a bulk substrate can be used if proper measures are taken to provide: (i) oxide isolation between devices, and (ii) heavy channel doping at the base of the gated fin to suppress OFF-state leakage due to bulk punch-through [123]. This allows for reduced substrate costs, which can be especially important for cost-sensitive applications such as dynamic memory (DRAM). The use of a bulk substrate has additional benefits such as improving heat transfer and providing a weak body contact. Note that fins with higher aspect ratio must be formed if a bulk substrate is used to provide for (recessed) shallow trench isolation (STI) in-between devices. By selectively adjusting the recess depth of the STI oxide (e.g., by using a masked etch), the effective channel width can be finely adjusted with minimal impact on the device layout area [124]. In fact, this feature allows bulk-FinFETs to be easily co-fabricated with planar bulk MOSFETs [125], e.g., for embedded FinFET-based memories [124]. (The STI oxide can simply be protected by patterned photoresist during the recess etch step(s), in the regions where planar bulk MOSFETs are to be fabricated.) This is another advantage of bulk-FinFET technology over SOI-FinFET technology. Although the FinFET was originally proposed for logic applications, its superior electrostatic integrity makes it particularly attractive for memory applications, which have more stringent leakage and variability requirements. Also, it can provide for smaller cell layout area, since memory cells generally employ minimum-width transistors. The issues of transistor leakage current (static power dissipation) and device-to-device variability (reduced noise margin [126]) pose serious challenges for scaling conventional static memory (SRAM) technology beyond the 45 nm node. These issues can be alleviated by using FinFETs rather than planar bulk MOSFETs in the memory cells [127]. Similarly, FinFETs have been found to be advantageous for DRAM application [128] and are projected to be used for sub-50 nm half-pitch DRAM technologies [129, 130]. FinFET SONOS (silicon-oxide-nitrideoxide-silicon) non-volatile memory devices have excellent retention and acceptable endurance characteristics [131, 132] and have been demonstrated with multi-level

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storage at 20 nm gate length [133]. MugFET SONOS flash memory cells with gate lengths down to 20 nm and multi-level storage also have been successfully demonstrated [134, 135]. Thus, FinFET cell designs may potentially be used to scale flash memory technology to sub-30 nm half-pitch flash memory technologies [130]. Note that because the effective gate-dielectric thickness of the ONO stack is relatively large (∼10 nm), the body thickness (i.e., the fin width) of a FinFET SONOS memory device must be even smaller than for a FinFET logic device, in order to adequately suppress leakage current [131]. Optimization of FinFET Layout Orientation The transconductance of a FinFET is dependent on its layout orientation due to carrier mobility anisotropy in crystalline silicon [136]. The channel surfaces of a FinFET lie in a {110} crystallographic plane when the fin is oriented parallel or perpendicular to the wafer flat or notch of a standard (001) wafer (Fig. 8.6). Hole mobility is enhanced while electron mobility is degraded for a {110} Si surface as compared with a {100} Si surface [137]. For optimal transistor drive currents, then, {100} fin sidewall surfaces for n-channel (NMOS) FinFETs and {110} fin sidewall surfaces for p-channel (PMOS) FinFETs are desirable. This can be achieved by orienting the PMOS fins to be either perpendicular or parallel to the flat or notch of a (001) wafer and orienting the NMOS fins to be rotated at a 45◦ angle (Fig. 8.6). Non-Manhattan layout geometry may pose a yield issue for sub-wavelength lithography, however.

Fig. 8.6. Dependence of fin sidewall surface crystalline orientation on layout orientation. Fins oriented either parallel or perpendicular to the wafer flat have sidewalls along {110} crystallographic planes, which is best for high hole mobility. Fins with layout orientation rotated by 45◦ have sidewalls along {100} crystallographic planes, which is best for high electron mobility

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An alternative approach is to use a (110) wafer to allow the optimal CMOS FinFET sidewall surface orientations to be achieved with Manhattan layouts. From a reliability standpoint, {100} fin sidewall surfaces are preferred. Due to the higher density of interface states for {110} surfaces vs. {100} surfaces, negative bias temperature instability (NBTI) is worse for {110} FinFETs [138, 139]. 8.3.3 Tri-Gate (TG) MOSFET As alluded to previously, a wider fin can be employed in a MuGFET if the height of the fin (Hfin ) is sufficiently short so that the portion of the gate along the top of the fin serves effectively as a third-gate electrode. The TG SOI MOSFET structure was first proposed by researchers at Intel [109, 140] to be advantageous from a manufacturability standpoint, because it alleviates the need for either an ultra-thin body or a very narrow fin to suppress SCE. A variant of this structure is the PiGate FET [110] in which the sidewall gate electrodes extend beneath the channel for improved electrostatic integrity. For sub-20 nm gate lengths, VT variation due to statistical dopant fluctuation effects becomes significant [23], so that heavy channel/body doping for VT control is undesirable. Also, body doping should be low to avoid corner effects [141]. If the body of a TG-MOSFET is lightly doped or undoped, then the fin height (Hfin ) and fin width (Wfin ) must each be less than Lg in order to adequately suppress SCE [101]. The optimal lightly doped TG-MOSFET design has Wfin and Hfin that are only ∼1.4× larger than Wfin for the FinFET and Hfin for the UTB MOSFET, respectively. This yields poor layout efficiency, since Weff = Wfin + 2 × Hfin < 2 × Lg,min < P (assuming that the minimum gate length Lg,min ∼ P /4). This is the main drawback of the TG-MOSFET structure. 8.3.4 Back-Gated (BG) MOSFET A variant of the DG MOSFET structure is the BG thin-body MOSFET, in which the two gate electrodes are electrically isolated (Fig. 8.7). The threshold voltage of the MOSFET controlled (switched on/off) by the front-gate electrode can be modulated

Fig. 8.7. BG-MOSFET structures: (a) Planar UTB/DG-like structure, and (b) FinFET-like structure

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by adjusting the bias on the back-gate electrode. The scale length lBG of a BG MOSFET is a function not only of the front-gate oxide thickness (Tox ), the back-gate oxide thickness (TBox ), and the body thickness (TSi ), but also the back-gate bias (VBG ). If VBG is “reverse biased” such that the back-channel surface is in accumulation, then the effective leakage path in the OFF state is moved closer to the front-channel surface, resulting in improved front-gate control of the leakage path and hence smaller lBG . Thus, SCE are reduced with reverse back-gate biasing [142–144], which allows for the body thinness requirement to be relaxed (to ∼2Leff /3, as for a DG MOSFET). More important, back-gate biasing allows for dynamic VT control to optimize the power vs. delay trade-off and can also be used to compensate process-induced VT variations for improved parametric yield. The performance of a BG MOSFET is poorer than that of a DG MOSFET, however, due to the capacitive voltage divider effect across the channel that increases the sub-threshold swing S and the increased transverse electric field in the channel which reduces carrier mobilities [145]. Nevertheless, the BG-MOSFET structure is a viable candidate for scaling CMOS technology to sub-10 nm gate lengths because it offers dynamic tunability to mitigate the challenges of increasing power density and variability, in contrast to DG/MuG/TGMOSFET structures. Electrical isolation of the two gate electrodes is most easily accomplished for a planar structure (Fig. 8.7(a)), since the back-gate electrode is fabricated in a separate plane than the front-gate electrode [146, 147]. The bottom-gate electrode can span many devices, resulting in a minimal layout area penalty for the additional gate contact. Since it is difficult to fabricate a back-gate electrode that is perfectly aligned to the front gate, however, larger parasitic capacitance (due to large back-gate-tosource/drain overlap to allow for lithographic misalignment, as shown in Fig. 8.7(a)) may substantially degrade device switching performance if TBox is very thin. The vertical FinFET structure can be modified into a BG MOSFET by removing the gate electrode material over the top of the fin to separate the front- and back-gate electrodes [148–151]. This could be accomplished, for example, by planarization of the gate layer or with a masked etch. The use of the FinFET-like structure allows for perfectly self-aligned front and back gates, which reduces parasitic elements. However, the device layout can be more complex (i.e., require more area) than for a planar structure due to the need for extra back-gate contacts and gate-level routing. For optimal BG-MOSFET performance (smallest switching delay), TBox should be thicker than Tox to balance the trade-off between parasitic source/drain capacitance and electrostatic integrity [152]. For a planar BG-MOSFET structure, this can be achieved simply by adjusting the buried oxide thickness. For a vertical (FinFETlike) structure, techniques such as selective (tilted) ion implantation of nitrogen [153, 154], oxygen [155], or argon [154] to simultaneously grow gate oxides of different thicknesses can be used. Electrical isolation of the front and back gate electrodes in a DG-MOSFET structure can also be beneficial for memory applications. For example, separate biasing of the two gates can be used to implement a capacitorless DRAM cell in which information is stored at the back-channel surface near to the source in the form of charge in the body region [156]. Since the electrically floating body region (where

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the charge is stored) is induced by back-gate biasing rather than by heavy body doping, this cell design avoids dopant fluctuation effects and hence is more scalable than a single-gate PD-SOI cell design [157, 158] for future high-density memories.

8.4 Fundamental Scaling Limit and Ultimate MOSFET Structure If the distance between the source and drain regions is so small that carriers can easily tunnel through the source-to-channel potential barrier, the gate(s) cannot be used effectively to shut off the transistor. Thus, quantum mechanical tunneling of carriers from the source to the drain (“S/D tunneling”) (Fig. 8.8) sets a fundamental limit for scaling the OFF-state electrical channel length (Leff ) of a MOSFET. Source/drain tunneling is significant for Leff < 15 nm and dominates the OFF-state leakage current for Leff below ∼8 nm [159]. It is more serious in transistors with poor electrostatic integrity (e.g., a DG MOSFET with a thicker body) because of drain-induced barrier thinning, which increases tunneling. Depending upon the leakage current specification, supply voltage, and electrostatic integrity of the transistor design, the lower limit for Leff can be as small as ∼5 nm [159, 160]. Note that this is not necessarily the lower limit for gate length (Lg ) scaling, however, since Lg can be smaller than Leff . Indeed, it has been reported that a gate-underlapped structure (in which the source/drain junctions are not located beneath the gate electrodes, so that Leff is larger than Lg ) is optimal for maximizing circuit performance for sub-20 nm Lg [161]. Given that each alternative to the planar bulk MOSFET structure has its associated issues/challenges, which is the most likely MOSFET design that will be used to scale CMOS logic technology well into the sub-10 nm Lg regime? To arrive at the answer(s) to this question, it is helpful to review the requirements (listed below in order of importance) for the “ultimate MOSFET”:

Fig. 8.8. Partial energy band diagram of an n-channel MOSFET in the OFF state, showing that quantum mechanical tunneling from the source to the drain is significant if the width of the potential barrier is small, e.g., if the electrical channel length (Leff ) is less than 15 nm, for a silicon MOSFET

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Immunity to random dopant fluctuation effects, Electrostatic integrity superior to that of the planar bulk MOSFET, Relative ease of manufacture, Means for dynamic adjustment of threshold voltage, and Layout efficiency comparable to or better than that of the planar bulk MOSFET.

To satisfy the first requirement, the channel doping concentration must be low. To fulfill the second requirement, a multiple-gate structure is necessary. To meet the third requirement, sub-5 nm channel thickness or high-aspect-ratio features (e.g., fins with height-to-width ratio >3) should be avoided. To achieve the fourth requirement, an independent back gate or a direct body contact is needed. Although the fifth requirement is not crucial, it favors a transistor structure that provides for large effective channel width per pitch. Of all the aforementioned thin-body transistor structures, only the planar BG MOSFET (with appropriate back-gate biasing) can meet all of these requirements, though it does not provide for the best possible circuit performance (due to its larger parasitic capacitances as compared with the DG MOSFET). A BG TG MOSFET can in principle meet all of the requirements except for the layout efficiency, although it has weak back-gate effect [162]. However, a practical issue for BG MOSFET technology is the availability and cost of SOI substrates with very thin (<10 nm thick) and uniform buried oxide layers. Another pathway for continued CMOS technology scaling is evolution of the conventional planar bulk MOSFET into a multiple-gate structure [163]. This can be done by segmenting the channel region into parallel stripes of equal width and wrapping the gate electrode around the upper portion of each stripe, as shown in Fig. 8.9. (In practice, such a corrugated gate electrode structure can be achieved by recessing the isolation oxide in-between the stripes prior to gate-stack formation, as is done in a bulk-FinFET fabrication process.) Super-steep retrograde channel doping (located at the base of the gated stripe region) should be used to suppress subsurface leakage and to mitigate VT variation due to RDF. Because the gate electrode wraps around the channel, the amount of depletion charge (due to ionized channel dopants) per unit channel width is smaller than for a planar bulk device, so that VT variation due to RDF is reduced. The use of a virtual “ground plane” structure [32] allows the TG bulk MOSFET to achieve electrostatic integrity superior to that of the TG SOI MOSFET, because drain electric field penetration through the buried

Fig. 8.9. Schematic diagrams illustrating the TG bulk MOSFET structure (n-channel) [163, 164]

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oxide is eliminated. It also allows for dynamic VT control via body biasing. Good short-channel control can be achieved with a stripe width (WSTRIPE ) that is greater than Lg (to ease lithography requirements) if the height of the gated stripe region (HSTRIPE ) is less than ∼2Lg /3 [164]. Thus, the layout efficiency of the TG bulk MOSFET (i.e., the effective channel width per stripe) is substantially better than that of the TG SOI MOSFET. If a patterning technique such as spacer lithography or multiple patterning is used to form the stripes with very fine pitch (e.g., stripe spacing WSPACING < WSTRIPE ), then the layout efficiency of the TG bulk MOSFET can be comparable to (or even better than) that of the planar bulk MOSFET. Note that the channel stripes have aspect ratio <1, and that only very shallow trench isolation (VSTI) is required in-between them. The VSTI depth (XVSTI ) can be much shallower (by ∼10×) than the STI used to isolate individual transistors. (In order to suppress source-to-drain leakage current underneath the VSTI, XVSTI should be deeper than the source/drain extension junction depth, Xj .) Thus, only fins with relatively small aspect ratio (XVSTI /WSTRIPE < 2) need to be formed. Tri-gate bulk MOSFETs can be fabricated using a process that is nearly identical to that for planar bulk MOSFETs, except that a corrugated substrate (comprised of fins isolated by VSTI) is used as the starting material [164]. Thus, the TG bulk MOSFET can be the ultimate MOSFET. It is important to note that the TG bulk MOSFET design provides for lower parasitic source/drain resistance (RSD ) than a thin-body MOSFET, because it neither requires a UTB or very narrow fin. As compared with the planar bulk MOSFET, it provides more source/drain surface area relative to channel surface area and hence lower RSD without a significant increase in parasitic gate capacitance (due to the VSTI oxide in-between the stripes, which is much thicker than Tox ). Since parasitic resistance and capacitance will increasingly limit transistor performance [165], this is a significant advantage of the TG bulk MOSFET design. Also, the avoidance of a UTB or very narrow fin is beneficial for suppressing ON-state and OFF-state current variation due to statistical dopant fluctuation effects [63].

8.5 Advanced Gate-Stack Materials 8.5.1 High-k Gate Dielectrics Scaling of conventional (SiO2 -based) gate oxide films has slowed for sub-90 nm CMOS technology nodes because of gate leakage current and reliability limits (especially since Vdd scaling has slowed). Alternative gate-dielectric materials with higher permittivity than SiO2 (“high-k dielectrics”) can be physically thicker (by a factor equal to the ratio of the relative permittivities, high-k /SiO2 ) for a given Tox , and thus can provide for lower gate leakage current to allow further Tox scaling. Hafnium-based oxides, including HfO2 and HfSiOx , have emerged as the most promising high-k gate dielectric materials because of their excellent thermal stability with silicon and will likely be used in the most advanced planar CMOS technologies beginning at the 45 nm node [166]. A detailed review and a summary of recent advances and remaining challenges for high-k gate dielectric technology can be found

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in [167] and [168], respectively. Since a reduction in Tox is beneficial for reducing the MOSFET scale length (see (8.3)), the adoption of high-k gate dielectrics can help to extend the scalability of the conventional planar bulk MOSFET (to ∼10 nm, depending on the leakage current requirement). A reduction in Tox is also beneficial for improving ON-state current, if field-effect mobility is not significantly degraded. For a given gate dielectric layer, the gate leakage current density is lower in a (lightly doped) thin-body MOSFET than in a planar bulk MOSFET because of the lower transverse electric field [169]. Thus, the adoption of high-k gate dielectric materials could be delayed (to shorter gate length, i.e., a more advanced CMOS technology node) if a thin-body MOSFET structure were used. Integration of highk gate dielectrics with advanced MOSFET structures is relatively straightforward. FinFETs and MuGFETs with Hf-based gate dielectric already have been demonstrated with good performance characteristics [170–173]. Since direct tunneling current becomes an even more sensitive function of the electric field with increasing dielectric thickness, the reduction in gate current density provided by a (physically thicker) high-k gate dielectric material is greater for thin-body MOSFETs than for planar bulk MOSFETs [169]. Thus, Tox can be scaled down more aggressively for thin-body devices to facilitate CMOS technology scaling to the fundamental limit. It should be noted that the gate-sidewall spacers, which are used to offset the gate from the source/drain contact regions (see Figs. 8.3 and 8.9), should ideally be formed of the same high-k material as in the gate-dielectric stack for optimal ON/OFF-current ratio if the gate stack is physically thin (∼5 nm or less) such that fringing-induced barrier lowering is not significant [174]. To minimize parasitic gate capacitance, the sidewall high-k layer should be thin. For example, a composite spacer comprised of a thin high-k layer + a thick low-k layer can be used. 8.5.2 Metallic Gate Electrode Materials A conventional heavily doped polycrystalline-silicon (poly-Si) gate electrode is depleted of mobile carriers near to the gate-oxide interface when the MOSFET is biased in the ON state. The depletion region serves to increase the effective thickness of the gate oxide (Tox ), typically by ∼6 Å [175]. The use of a metallic gate electrode eliminates the gate depletion effect, and therefore provides for smaller Tox to improve control of short-channel effects and facilitate transistor scaling. Thermal stability issues for high-k gate dielectrics in contact with poly-Si gate material, which make it difficult to achieve proper VT values (especially for PMOS devices), provide additional motivation to adopt a metal gate technology [176]. A key parameter of a MOSFET gate material is its effective work function, ΦM . For planar and TG bulk MOSFETs, ΦM should be similar to that of heavily doped poly-Si (∼4.1 eV for n-channel MOSFETs and ∼5.2 eV for p-channel MOSFETs) to ensure surface-channel operation for improved short-channel control [177]. This means that different gate materials must be used for NMOS vs. PMOS devices, so that CMOS process complexity is significantly increased for a metal-gate technology

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as compared to a poly-Si-gate technology. This is because extra lithography and etch steps are needed to pattern at least one of the deposited metal gate layers so different gate materials are in contact with the gate dielectric in the NMOS vs. PMOS device regions. Metal gate integration approaches include “gate-first” (for example, as in [178]) and “gate-last” (or “replacement-gate”) [179–181] processes. In a gate-first process, the gate electrodes are formed prior to the source/drain regions, as in a conventional poly-Si gate process; the gate materials must be readily etched with good selectively to the gate dielectric, and the gate stack must have good thermal stability to be able to withstand the source/drain annealing process. In a gate-last process, dummy gate electrodes (e.g., poly-Si) are formed and then selectively removed after formation of the source/drain regions; the metallic gate materials are then sequentially deposited and patterned to form the actual gate electrodes. The gate dielectric can also be replaced together with the metal gate after the source/drain regions are formed. The advantage of the more complicated gate-last process is that it minimizes thermal exposure of the high-k/metal gate stacks, which helps to minimize interface-dipole and defect formation and thereby provides for improved device performance and reliability. As mentioned previously, an undoped channel/body is desirable for immunity to threshold voltage variations due to statistical dopant fluctuations in the channel and for the highest possible carrier mobilities to achieve high ON-state current. For lightly doped thin-body MOSFETs, ΦM should be near midgap (∼4.7 eV ± 0.2 eV), as shown in Fig. 8.10. Note that this requirement is different than that for planar and TG bulk MOSFETs, so that different metal gate material(s) will be required. In other words, if there is to be a changeover to thin-body MOSFET structures, then the metal-gate technology must be changed as well. Since the difference between NMOS and PMOS gate work functions is relatively small for thin-body MOSFETs, a single gate material with tunable work function could potentially be used to achieve the proper VT values. Examples of tunable-ΦM gate materials are molybdenum (Mo) and fully nickel-silicided poly-Si (“FUSI”). Mo is compatible with a conventional (gatefirst) fabrication process [182]; it can be deposited by sputtering or chemical vapor deposition and patterned by conventional reactive ion etching. Nitrogen (N) implantation followed by thermal annealing to form a Mo nitride layer at the gate-oxide interface has been shown to be an effective way to controllably lower the effective ΦM of a Mo gate electrode on a SiO2 gate dielectric from 5 eV–4.4 eV [183]. Care must be taken to avoid Mo+ diffusion [184] and gate-oxide damage during sputter deposition [185]; the Mo gate film thickness and N implant energy must be carefully co-optimized to minimize damage (due to implant straggle) to the underlying gate dielectric. The work function of a fully silicided gate material can be adjusted via doping of the precursor Si gate material [186]. Researchers have demonstrated that ΦM for a FUSI NiSi gate on a SiO2 gate dielectric can be tuned over a significant range [187] (from 4.5 eV–4.9 eV for dopant implant doses up to ∼3 × 1015 cm−2 [118]) and have successfully applied this gate technology to fabricate CMOS FinFETs with nearly symmetrical VT s [67]. The NiSi is formed at low temperature (≤500◦ C) and

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Fig. 8.10. Simulated threshold voltages for NMOS and PMOS DG MOSFETs as a function of the gate work function. In order to achieve low and symmetric threshold voltages without significant body doping (so as to minimize VT variation due to random dopant fluctuation effects), gate work functions near the silicon midgap will be required [70]

cannot withstand high annealing temperature; hence, silicidation should be the last significant thermal processing step in the transistor fabrication process. The intrinsic tensile stress (∼0.8 GPa) in a NiSi gate induces tensile strain in the Si channel for narrow-width SOI FETs, which enhances both electron and hole carrier mobilities and hence drive current [188]. It should be noted that ΦM for a metal gate electrode can vary significantly with the gate-dielectric material [189]. In addition, process integration challenges will change with the gate-dielectric material: Ni atoms in a FUSI NiSi gate can penetrate HfO2 during the silicidation process, leading to yield and reliability problems [190]; N implanted into a Mo gate can easily penetrate HfO2 during subsequent annealing steps and degrade the oxide-silicon interface and hence transistor performance [170]. Therefore, a metal-gate technology must be tailored specifically to the gate-dielectric material. For HfO2 , FUSI HfSi is a promising tunable-ΦM gate material (with ΦM tunable in the range 4.23 eV–4.87 eV) that is stable at high temperatures and, therefore, compatible with a conventional (“gate-first”) planar CMOS fabrication process [191]. For compact circuit layouts such as those used in SRAM cells, it may not be possible to separately implant the gate electrodes in the NMOS and PMOS regions if the FinFET structure is employed, because the gate layer fills the entire region in-between the n-channel and p-channel fins (Fig. 8.11). Thus, a single gate work function must be used, and another means for adjusting VT is needed. Leff engineering is an approach that is relatively simple to implement, to allow a single mid-gap-ΦM gate material (e.g., TiN) to be used with undoped (or lightly doped) channels [68, 69, 192].

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Fig. 8.11. Schematic cross-section of a FinFET CMOS inverter. If the separation between NMOS and PMOS fins (which is less than the minimum half pitch, e.g. less than 40 nm at the 45 nm CMOS technology node) is less than twice the gate thickness, the gate completely fills the region in-between the fins so that it is difficult to separately tune the gate work functions for NMOS vs. PMOS FinFETs

8.6 Performance Enhancement Approaches The ON-state current per unit channel width (ION ) of a nanometer-scale MOSFET in saturation mode is proportional to the inversion-layer areal charge density (Qsource ) and carrier velocity (vinj ) at the point of injection into the channel: 1−r ox , (8.8) ION = Qsource vinj B = Cox (VGS − VT )vinj B = q (Vdd − VT )vinj Tox 1+r where r is the channel backscattering coefficient [193], (VGS − VT ) is the gate overdrive, and B = ( 1−r 1+r ) is the ballistic efficiency. Due to increased transverse electric field resulting in reduced field-effect mobilities (hence lower vinj ) and imperfect ballistic efficiency (∼65% for state-of-the-art MOSFETs) [194], gains in ION with gate-length scaling have become less straightforward to achieve for sub-100 nm CMOS technologies. Increasing parasitic (source/drain and contact) resistance and (fringing and sidewall-to-contact) capacitance relative to intrinsic (channel) resistance and (gate) capacitance further restrict gains in circuit performance with scaling. Approaches to enhance carrier velocities and reduce parasitic components are therefore required for continued improvements in circuit performance with transistor scaling. 8.6.1 Enhancement of Carrier Mobilities Techniques for increasing the average velocity of carriers in the channel – without significantly impacting cost and device reliability – have become necessary in order for the semiconductor industry to maintain its historic 17%-per-year performance improvement rate [16, 194, 195]. Mobility enhancement approaches include the use of a strained layer overlying (encapsulating) the MOSFET [196], a strained gate electrode [197, 198], strained source/drain regions (epitaxially grown Si1−x Gex [199] or Si1−y Cy [200] embedded in the source/drain regions, or silicide [201]), a relaxed Si1−x Gex underlayer [202], and optimization of the channel surface crystallographic plane and current flow direction [203]. Indeed, some of these methods are already used in state-of-the-art CMOS products today and in combination show promise for boosting ION (for a given IOFF ) by more than 50% [204–206]. These techniques

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should be easily adapted to the non-classical transistor structure(s) that will ultimately replace the planar bulk MOSFET with manageable device-parameter dependencies (i.e., variation with MOSFET channel length and width, source/drain length, and device spacing) for effective circuit design. Otherwise, the advanced transistor structure(s) would provide no performance improvement over the classical MOSFET with enhanced mobility, and hence should not be adopted. Various mobility enhancement techniques have already been shown to be effective for enhancing the performance of UTB MOSFETs [207–210] and MuGFETs [171, 172, 208, 211–213]. Alternative channel materials such as strained Si1−x Gex [214–222], Ge [223– 236], and III–V compound semiconductors such as GaAs [237–243] have been investigated because they offer significantly higher carrier mobilities than silicon [244]. Although they are alluring for higher performance, FETs made using Ge and GaAs are not as scalable as silicon FETs. The reasons for this are multiple. First, higher mobility implies lower conductivity effective mass and associated tunneling effective mass (meff ). Since direct √ tunneling current is a sensitive function of meff (increasing nonlinearly with e− meff ), direct tunneling of carriers from the source to the drain in the OFF state (as well as tunneling of electrons from the channel through the gate dielectric [226]) is increased dramatically, so that the lower limit for Leff will be much larger for high-mobility channel materials than for silicon. Second, Ge and GaAs have higher dielectric permittivity than Si and will have more severe short-channel effects (e.g., poorer sub-threshold swing, increased drain-induced barrier lowering and drain-induced barrier thinning). Thus, they will require the use of non-classical MOSFET structures sooner (i.e., at longer gate lengths) for good electrostatic integrity, with much smaller channel height and/or width relative to the gate length. Third, energy quantization, which reduces the gate capacitance in inversion and the effective density of states (and hence Qsource ), is more significant in highmobility channel materials so that ION (as well as IOFF ) at sub-10 nm gate lengths for a given supply voltage Vdd would actually be worse for these materials than for silicon [245]. It should be noted that fundamental challenges exist for implementation of high-performance CMOS circuitry in Ge or GaAs: Ge NMOSFETs have poor field-effect mobility due to high interface trap density [246], and larger parasitic source/drain resistance due to low solid solubility of n-type dopants; GaAs has lower hole mobility than for Si, and its larger bandgap (1.424 eV) makes it more difficult to achieve low-contact resistances (e.g., specific contact resistivities <10−8 cm2 , needed for source/drain contacts in nanometer-scale MOSFETs). For Ge [236] and even GaAs [242], an interfacial layer of Si is needed to achieve a high-quality gate-dielectric interface, which effectively increases Tox and hence degrades shortchannel behavior (i.e., scalability). In sum, Si-based CMOS technology is the most scalable and as such it is unlikely to be surpassed in performance. Continued improvements in CMOS performance are best achieved by scaling Si-based MOSFETs (which encompass Si/Si1−x Gex /Si-channel devices) to the limit, rather than replacing Si with an alternative channel material altogether and prematurely abandoning transistor scaling.

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8.6.2 Reduction of Parasitic Components The source/drain extension junction depth, source/drain contact area, and the spacing between the gate electrode and source/drain contact plugs are each scaled down with transistor gate length so that parasitic source/drain, contact resistances, and parasitic gate capacitance increase. (The height of the contact plug, which affects gate sidewall capacitance, is not scaled commensurately.) At the same time, channel resistance and intrinsic gate capacitance are each decreased with transistor scaling. Thus, parasitic components can become dominant and restrict performance gains as CMOS technology is scaled to sub-32 nm nodes [165]. If gate-length scaling slows due to increasing challenges for planar bulk MOSFET scaling, but device-to-device spacing (i.e., minimum half-pitch) continues to scale at the historical pace, then the gate-to-contact plug spacing will decrease at a faster pace to exacerbate the parasitic capacitance issue [247]. The height of the gate electrode above the channel surface should therefore be minimized to reduce parasitic capacitance. To reduce parasitic resistance for high-performance applications, the source/drain extensions should be predominantly metallic, i.e., mostly comprised of silicide. The primary challenge for a purely metallic (Schottky) source/drain technology is achieving sufficiently low (≤0.1 eV [77]) Schottky barrier height ΦB to meet ITRS ION specifications. Techniques proposed for lowering ΦB include passivation of extrinsic interface states [248], straining the Si channel [249, 250], and doping the semiconductor very heavily at the silicide interface [251]. Such heavily doped, narrow extensions can be formed by silicidation-induced impurity segregation [252, 253] or an “implant to/through silicide” (ITS)’ process [254, 255]. The use of dual silicide technology (near-band-edge silicides such as ErSi2 and PtSi for NMOS and PMOS devices, respectively) is beneficial for further lowering ΦB (hence contact resistance) to improve the ON-state current of metallic-source/drain transistors. However, this technology increases process complexity and cost. For low-power applications which require much lower IOFF (but have lower ION requirements), wider and less heavily doped regions (i.e., similar to a conventional source/drain extension design) are necessary to adequately reduce tunneling leakage current components [256]. In this case, the specific contact resistivity (resistance per unit area) would be higher, so that contact resistance between the silicide and silicon can significantly limit ION for a metallic-source/drain structure. Thus, a more conventional doped source/drain structure may be optimal for low-power applications. (For a thin-body MOSFET, the raised-source/drain structure (ref. Fig. 8.3) should be used to provide more silicide-to-silicon contact area and thereby lower contact resistance [256].) To achieve the lowest possible contact resistances, Si1−x Gex should be used at the (germano) silicide interface to lower the specific contact resistivities to below 10−8 -cm2 [257]. For an NMOS device, this contact layer should have Ge content preferably less than 40%, since n-type dopant activation dramatically decreases for Ge content >40% [258]. For a PMOS device, this layer should have higher Ge content. However, for ease of processing, the Ge content at the source/drain surface should be less than 70%; otherwise, it will etch easily in oxidizing solutions or plasmas [258].

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8.6.3 Alternative Switching Devices As demand for mobile, battery-powered consumer electronic devices grows, power consumption becomes an increasingly important issue. To reduce operating power, the supply voltage (Vdd ) must be scaled down, e.g., to 0.5 volts [16]. In order to meet the OFF-state leakage current specification (Isd,leak ), VT cannot be arbitrarily low: IVT , (8.9) VT ≥ S log Isd,leak where IVT is the current at threshold (VGS = VT ). Aggressive scaling of Vdd to below VT has been proposed for ultra-low-energy applications, but with dramatic reduction in circuit performance, commensurate with reduction in energy [259]. Lg cannot be scaled as easily for sub-VT CMOS circuits due to their increased sensitivity to VT variations. Therefore, we do not consider it further here. For conventional CMOS circuits, VT should not exceed ∼Vdd /3. Thus, it can be seen that there is an approximate lower limit for Vdd : IVT . (8.10) Vdd ≥ 3S log Isd,leak For low standby power (LSTP) applications such as mobile electronics, Isd,leak should be ∼105 times smaller than the current at threshold [16] so that Vdd should be ≥15 × S. Given that S for a MOSFET has a fundamental lower limit of 60 mV/dec, Vdd cannot be easily scaled much below 0.9 volts if low standby power is required. It is important to note that the 60 mV/dec limit applies to any channel material, so that the adoption of high-mobility channel materials will not facilitate Vdd scaling, assuming that similar noise margins are required. The key to Vdd scaling is S reduction. Various alternative devices have been proposed to achieve steeper than 60 mV/dec sub-threshold swing [260–262]. Among these, tunneling field effect transistors (TFETs) show the most promise for lowvoltage operation, although high ON-state current (comparable to that of a MOSFET) has been elusive [263]. Opportunities remain for device design improvements and further innovations to alleviate the power crisis.

8.7 Summary Advances in materials (e.g., high-k gate dielectrics, metal gate electrodes, metallic source/drain regions), processes (e.g., to induce strain and thereby enhance carrier mobilities), and structures (e.g., multiple-gate FETs) will be necessary to suppress short-channel effects and improve ON-state current to achieve steady performance improvement with continued MOSFET scaling in the Nano Era. Because the order of importance of the various requirements for MOSFET scaling is dependent upon the application, there may be a divergence in optimal transistor design (e.g., for logic vs. memory applications) so that future integrated circuits may concurrently

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Fig. 8.12. Silicon MOSFET scaling scenario. Advanced materials (such as metal/high-k gate stacks), process technologies (such as strained-Si to boost ON-state current without increasing OFF-state current), and circuit innovations (such as active body biasing to improve MOSFET scalability and allow for dynamic tuning of the trade-off between performance and power consumption) will allow planar bulk-Si MOSFET scaling to reach ∼10 nm gate length. Multiplegate transistor structures will be needed to scale silicon-based MOSFETs to the ultimate (quantum mechanical) limit, which is well below the 10 nm gate length

incorporate variegated transistor structures. The fundamental limit for Leff scaling, at which direct tunneling of carriers from the source to the drain in the OFF state becomes prohibitively large, is less than 10 nm for a silicon MOSFET. Since Lg can be smaller than Leff , the silicon-based MOSFET can be scaled to gate lengths well below 10 nm. The pace of MOSFET scaling may slow in the future, however, depending upon the degree to which doping profiles and channel dimensions can be precisely controlled/defined in a cost-effective manufacturing process. Alternative channel materials such as Ge or GaAs are less scalable and therefore are unlikely to provide improvements in MOSFET performance beyond the limits of silicon. Because of the fundamental 60 mV/dec limit for MOSFET sub-threshold swing, alternative devices with steeper turn-on characteristics will be needed in complement with MOSFETs to meet ultra-low power requirements for the rapidly growing mobile consumer electronics market. Clearly, opportunities abound for innovations by technologists and device designers alike to sustain the silicon revolution.

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Part III

Future Directions

9 Beyond CMOS Electronics: Self-Assembled Nanostructures T.I. Kamins

9.1 Introduction When the first transistors were built in the late 1940s, few could predict their widespread adoption and the capabilities of the integrated circuits (ICs) that would evolve from those initial discoveries. Although the concept of a field-effect transistor controlled by an external gate electrode had been conceived [1] two decades before the first observation of transistor action, the first practical transistors were bipolar transistors, rather than field-effect transistors; adequate control of the interface between the semiconductor and the gate insulator needed for a practical field-effect transistor was lacking. Extensive efforts throughout the 1960s finally provided the interface control needed for practical use of the presently dominant, insulated-gate, field-effect transistors built using the metal-oxide-semiconductor (MOS) system based on silicon and thermally grown silicon dioxide. 9.1.1 Conventional “Top-Down” Fabrication Since the 1960s clever processing – especially lithography – has allowed ever increasing complexity of ICs. This increasing complexity has been achieved primarily by using smaller dimensions of each individual transistor to increase the number of transistors on the chip. While the chip size has only increased moderately from a few millimeters on a side to a maximum of approximately 2 cm on a side, the number of transistors has increased from a few to a few hundred million. This functionality has increased approximately exponentially with time, as described by “Moore’s law,” an extrapolation of observed data, which has described progress in IC technology for four decades. Because the chip size increases only slowly, the exponential increase in functionality arises primarily from an exponentially decreasing feature size.

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Recently, Moore’s law has become a self-filling prophecy; companies use projections of the exponentially changing feature size to determine their technology goals and spend the required funds to meet these goals. These costs, unfortunately, also tend to increase rapidly, limiting the number of companies that can participate in further advances in IC technology. The rapid increase in costs has two components: (1) research and development costs, and (2) the cost of the manufacturing or fabrication facilities (“fabs”). As the R&D costs increase beyond what most companies can individually afford, cooperation between companies is becoming common through numerous alliances, industrial consortia, and university/industry organizations. The cost of the manufacturing facilities is also increasing rapidly to achieve the perfect circuits needed for conventional IC designs. Although the cost per chip can decrease, the huge capital investment needed for a large fabrication facility can be justified by only a few companies, leading many to have their ICs built by “foundries,” which justify the cost of the facility by efficient manufacturing for a large number of customers who design the circuits. The small dimensions of today’s ICs have been primarily achieved by using shorter wavelengths of the exposing light. Today, 193 nm radiation is used for advanced circuits. The resolution of the exposure tool can be increased somewhat by introducing a medium with higher refractive index between the lens and the substrate in place of air. To obtain smaller, “sub-wavelength” features, complex structures are used on the masks, increasing the mask cost toward the million-dollar range. However, using shorter wavelengths to continue the progression to finer features is difficult; the materials used for lenses do not readily transmit light with shorter wavelengths. Lithography using wavelengths approaching the X-ray regime is being developed; at these “extreme ultraviolet” (EUV) wavelengths (typically 13.6 nm), however, obtaining light sources with adequate intensity can be limiting. As an alternative to conventional lithography, techniques for physically imprinting the features into a polymer layer are being explored [2, 3]. A mold is pressed into a soft polymer and then the polymer is hardened. Such “nanoimprint lithography”(NIL) is not limited by the wavelength of light and can form features on the order of 10 nm. In addition, many features are formed at the same time, avoiding the serial nature of techniques such as electron-beam lithography. The polymer can be hardened either thermally or by ultraviolet light. The latter avoids difficulties with differing thermal coefficients of expansion of the mold and substrate, but requires that either the mold or the substrate be transparent to the ultraviolet light. Although nanoimprint lithography can form very fine features, it is a 1:1 pattern transfer technique; consequently, features of the same size must first be formed on the mold. The mold is generally built using expensive electron-beam lithography, but it can be replicated and reused many times. Finer lines and spaces can be defined with a mold made from the edge of a differentially etched stack of layers, but the technique is expensive and generally limited to arrays of lines. 9.1.2 “Bottom-Up” Fabrication Although great progress continues to be made in pattern definition by these topdown approaches, the complexity of the processing and the associated costs con-

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tinue to increase. Today, the physical and economic limitations of conventional and non-conventional top-down technologies are being widely recognized, and alternative bottom-up techniques are being considered. With these techniques, a basic physical or chemical mechanism is used to form the small features. The critical dimensions are formed by the choice of materials and the deposition kinetics (socalled “self-assembly”), rather than by fine-scale lithography; coarser lithography can be used to position the devices or arrays of devices (“directed assembly”). In general, the locations and sizes of self-assembled features are less predictable than those of features formed by “deterministic,” top-down techniques; therefore, using self-assembled nanostructures requires reconsidering circuits and architectures to accommodate these limitations [4]. Two classes of bottom-up, self-assembled nanostructures are discussed here: (1) three-dimensional island structures formed by lattice mismatch strain (briefly), and (2) metal-catalyzed nanowires (in more detail).

9.2 Strain-Induced Nanostructures When one crystalline material is deposited on another crystalline material under suitable conditions, the atoms of the depositing material can position themselves above low-energy locations of the substrate (i.e., epitaxially). When the lattice parameter of the deposited material differs from that of the substrate, the strain energy in the system from the lattice mismatch increases as the layer becomes thicker. When the thickness of the deposited layer exceeds a “critical thickness,” irregularities can be generated in the layer, in the substrate, or at the interface, limiting the thickness of a defect-free, planar, two-dimensional strained layer. The increasing strain energy can be relieved in one of two ways: (1) Crystal defects can form to provide the space needed to reduce the strain. Quite often, one-dimensional defects form along the interface between the substrate and the epitaxial layer. Such “misfit dislocations” can extend macroscopic distances (e.g., centimeters) along the interface. They are often electrically benign, except at the ends of the dislocations. A more electrically detrimental defect forms when two misfit dislocations propagating in orthogonal directions along the interface interact to create a “threading dislocation” extending perpendicular to the interface and into the growing layer. (2) Under suitable conditions the energy of the materials system can be reduced without creating dislocations if the depositing material expands into the third dimension, forming characteristic, island-like nanostructures [5]. For large lattice mismatch all the deposited material is contained within the islands, and the substrate material is exposed between islands (Volmer–Weber growth). For moderate lattice-mismatch, the three-dimensional structures are surrounded by a thin, two-dimensional “wetting layer” of the material being deposited (Stranski–Krastanow growth). The lattice parameter of the wetting layer matches that of the substrate. If the lattice mismatch is the same in two orthogonal, in-plane directions, the three-dimensional structures are equi-axed islands extending above the wetting layer, as shown in Fig. 9.1. Island formation is observed for a number of materials systems, including the well-studied

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Fig. 9.1. Ge islands grown on Si by physical vapor deposition and imaged in situ by scanningtunneling microscopy. (a) Pyramid bounded by {105} facets formed with ∼6 equivalentmonolayers1 (eq-ML) of deposited Ge. (b) Multi-faceted dome formed with ∼12 eq-ML of deposited Ge. Reproduced with permission from [8]. Copyright 1999 Am. Chem. Soc.

Ge/Si(001) system [5–8] and the InAs/GaAs system [9, 10]. The Ge/Si(001) system has been studied in most detail because deposition of a single-component material is more controllable than deposition of a compound semiconductor and because Ge is compatible with Si IC technology. Because the island formation is controlled by lattice strain – i.e., thermodynamics – the islands can be formed by a number of different deposition techniques, including both physical vapor deposition (PVD) and chemical vapor deposition (CVD). Because the surface mobility of the depositing atoms must be high to form the nanostructures, the environment must be very pure for either PVD or CVD. The purity can be achieved in an ultra-high vacuum (∼10−8 Pa) or in a very high-purity (ppb impurity content) gaseous ambient at a moderate (e.g., 1 kPa) pressure. The atom movement needed to form the islands can occur during deposition or during annealing after deposition. To obtain maximum information, the atomic-scale structure of the islands deposited by physical vapor deposition in ultra-high vacuum can be studied by in situ scanning-tunneling microscopy, while the statistics can be investigated by studying larger areas containing islands formed by chemical vapor deposition and subsequently measured by ex situ atomic-force microscopy. The stages of island formation are illustrated for the Ge/Si system in Fig. 9.1. Ge has a lattice parameter approximately 4% larger than that of Si. This lattice mismatch determines the size of the islands; for systems with a larger mismatch, the island sizes are smaller. For Ge layers less than about 3–4 monolayers (ML) thick,1 the strain energy is low, and the deposited Ge forms a uniform, two-dimensional wetting layer. After the strain energy somewhat exceeds the value corresponding to island formation (∼3 ML thermodynamically, but ∼5 ML if kinetic barriers impede nucleation of the islands), the characteristic pyramidal islands shown in Fig. 9.1(a) form. These islands are bounded by {105} crystal planes and have a base dimen1 1 monolayer (ML) = 6.27×1014 Ge atoms cm−2 . When islands form, the average number

density of atoms on a surface containing many islands is described by the number of “equivalent monolayers” (eq-ML).

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sion about 10 times their height; the smallest islands have a base dimension of about 20 nm for the Ge/Si system. As more Ge is deposited, the sizes of the islands grow, but their shape remains the same. Because their heights are small, the islands cannot readily relax by deformation of their upper portions, and the strain energy increases as their size increases. When the base of the islands exceeds about 70 nm, taller islands become more energetically favorable, and the islands abruptly transform to the well-defined, multi-faceted characteristic shape shown in Fig. 9.1(b), with a height about 1/3 of the base width. (Because the facets are sometimes difficult to see by conventional atomic-force microscopy, the islands can appear to have a dome-like shape and are often called “domes.”) A dome is fully strained at its base, but because of its significant height, it can relax elastically near its top to some extent. The transition between the two island shapes can be predicted by considering the total energy of the system of islands, including the energies of the atoms within the islands, on the surfaces, at the layer/substrate interfaces, and at the edges of the islands (i.e., the intersections of surface facets). The energy ΔE of an island containing N atoms (compared to the same number of atoms in a uniform two-dimensional layer) can be represented by the equation [7] (9.1) ΔE = CN + BN 2/3 + AN 1/3 ln ac /N 1/3 , where C (C < 0) corresponds to the volume strain energy, B (B < 0 or >0) corresponds to the facet energy, A (A > 0) corresponds to the edge energy, and ac is a constant. An island transforms from a pyramid to a dome when the energy per atom in the pyramid plus the surrounding excess Ge atoms on the wetting layer exceeds the energy per atom in a dome. Unlike a pyramid, the base of a dome does not continue growing as more Ge is deposited. As more Ge atoms are added to the dome, the strain energy and the resulting barrier to atom attachment increase, and the diameter and height of each dome approach a limiting value. It is energetically unfavorable to add additional atoms to a dome. The bimodal distribution of varying size pyramids and nearly constant size domes is illustrated in Fig. 9.2. Eventually, the excess Ge atoms in the wetting layer overcome the energy barrier to atom attachment to a dome, and that island expands rapidly, often with defect formation in the island or in the underlying substrate. The diameters and heights of the remaining domes do not increase significantly because the excess Ge atoms within a surface diffusion length are readily incorporated into the large, defective island. After significant additional heat treatment, however, the distribution of islands coarsens [12] as Ge atoms detach from the smaller islands and diffuse to larger islands by well-known Ostwald ripening [13, 14] modified to apply to surfaces [15, 16]. (See [17] for a review paper.) In addition, Si from the substrate can diffuse into the Ge islands, changing the composition and reducing the stress in an island [18]. When a significant number of dopant atoms are added to the island during deposition, the strain energy can be changed enough that the island shapes and sizes are different than those of undoped islands with the same amount of deposited Ge [19, 20]. To be especially useful, the islands should be small, of uniform size, and regularly spaced or aligned to a previously formed feature. The size of the islands is

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Fig. 9.2. Distribution of island heights and diameters, showing varying size and constant shape of smaller (pyramidal) islands and nearly constant diameter and height of larger (domeshaped) islands. Samples were grown at 600◦ C. Reused with permission from [11], Copyright 1997, American Institute of Physics

best controlled by varying the strain energy by choosing materials with appropriate lattice mismatch. The island volume decreases as 1/ 6 , where = (alayer − asubstrate )/asubstrate is the normalized mismatch of the lattice parameter a [8, 21]; consequently, the size varies rapidly as the lattice mismatch increases. Because the domes are minimum-energy configurations, they have a more uniform size distribution than do pyramids. In theory [22], a uniformly spaced array island materials of islands can be obtained by stacking pairs of island layers and two-dimensional layers of another material (e.g., Ge islands and two-dimensional Si intermediate layers in the case being discussed here), as schematically illustrated in Fig. 9.3(a). When the two-dimensional layers between island layers are of the optimal thickness, the strain created by one layer of islands influences the position of an island in the next island layer. The island in the upper layer tends to be positioned approximately above the island in the lower layer, but slightly offset in the direction that makes the island spacing more uniform. After a very large number of layer pairs are deposited, the spacing is predicted to become uniform. However, as suggested in Fig. 9.3(b), the number of pairs required is large, and other factors, such as thermally induced interdiffusion of the island materials with the intermediate two-dimensional layers, may prevent a uniform island distribution from being realized. The position of islands can also be influenced by irregularities in the underlying substrate (“directed self-assembly”). A raised Si feature of micrometer-scale dimensions formed by conventional lithography can influence the position of Ge islands [24–26], as shown in Fig. 9.4. The islands tend to be located adjacent to irregularities in the surface; in this case, near the intersection of two facets formed in the Si substrate. The positioning may be caused by differences in strain near the features previously formed on the substrate compared to the strain on a flat surface. When the raised Si feature is wider than twice the surface diffusion length during deposition or

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Fig. 9.3. (a) Schematic cross section of multilayer stack of islands, showing predicted trend toward uniform spacing in upper layers [22]. (b) Top-view atomic-force micrograph of a multilayer stack of 10 pairs of Ge pyramidal islands and 10 nm Si intermediate layers (“interlayers”), with multilayer island structure covered by a 25 nm Si cap (horizontal axis: 1 μm full scale). Adapted from [23]

Fig. 9.4. Ge islands positioned at edges of raised pattern in Si substrate (“directed selfassembly”). (a) Schematic cross section. (b) Perspective atomic-force micrograph. Reused with permission from [24], Copyright 1997, American Institute of Physics

annealing, Ge atoms deposited near the center of the line cannot diffuse to the edges, and the islands near the center of the line are positioned randomly. The islands are small structures with electrical properties potentially useful in various small electronic devices that operate by classical principles, such as Coulombblockade devices, and in quantum-confined devices, where the small size changes the properties of the materials and devices. The islands can be randomly arranged on the surface of the substrate or selectively positioned (as shown in Fig. 9.4). Because an island forms heterojunctions with the surrounding material, charge carriers are influenced by the bandgaps of the island and the surrounding material and by the relative alignment of the conduction- and valence-band edges of the materials. With proper band alignment, both electrons and holes are preferentially confined in the island. When the densities of the carriers exceed their equilibrium values (i.e., pn > n2i , where p and n are the concentrations of free holes and elec-

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trons, respectively, and ni is the intrinsic carrier concentration), the excess carriers recombine efficiently in the island because they remain in proximity to each other for a longer time than they would if they were free to move throughout the crystal. This carrier confinement can be used beneficially if the carriers emit light as they recombine. Such emission enhancement increases the efficiency of some lattice mismatched light-emitting diodes (LEDs) [27, 28] and lasers [29, 30]. In addition to enhancing the efficiency, the small size of the confined region can change the allowed energy levels and, therefore, the emission wavelength. For the Ge/Si system, the lattice mismatch and the strain are the same in the two orthogonal major surface directions, and the islands are equi-axed. When the lattice mismatch, and hence the strain in the system, is anisotropic, the islands are no longer equi-axed, but are narrower in the high-strain direction than in the low-strain direction. The strain is anisotropic for a number of rare-earth silicides on Si; for example, ErSi2 (Fig. 9.5) and DySi2 on Si(001) [31–33]. The lattice mismatch between ErSi2 and Si is 6.5% in one direction and only 1.3% in the orthogonal direction. The “nanowires” formed on the surface can be very small (e.g., a few nm) in one direction and much longer (e.g., hundreds of nanometers) in the orthogonal direction. The structure of these in-plane nanowires has been studied by in situ scanning-tunneling microscopy [31–33]. Conduction along such in-plane, self-assembled nanowires exhibits quantum effects [34] and is somewhat lower than in the bulk, presumably being limited by surface scattering. Because the nanowires are very thin, their electrical resistance is high, but they can be used as an etch mask to define a thicker, underlying layer, which can have lower resistance. In this section we have examined the influence of strain energy from lattice mismatch between an epitaxially deposited layer and the underlying substrate. We saw that islands and one-dimensional nanostructures can be formed. However, obtaining

Fig. 9.5. Scanning-tunneling micrographs of ErSi2 on Si(001), showing the elongated structures formed because of the anisotropic lattice mismatch between ErSi2 and the Si substrate. (a) Reused with permission from [31], Copyright 2000, American Institute of Physics. (b) Reprinted from [33], Copyright 2003, with permission from Elsevier

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these structures requires that the underlying material be crystalline, limiting their use for many potential applications.

9.3 Metal-Catalyzed Nanowires An alternative method of forming self-assembled nanowires offers more possibilities for integration. Briefly, nanowires are grown by interaction of a depositing material with a catalyst nanoparticle. Typically, metal catalyst nanoparticles are first formed on a substrate. The material forming the nanowires (often a semiconductor) is then transported to the nanoparticles. Atoms of the nanowire material precipitate preferentially between the nanoparticles and the substrate, pushing the nanoparticles away from the substrate and forming columns of material (i.e., nanowires) of approximately the same diameter as the nanoparticles. Nanowires have been grown with diameters ranging from about 5 nm to hundreds of nanometers, as shown in Fig. 9.6. The details of the growth processes are discussed below. 9.3.1 Catalyst Nanoparticles To grow the nanowires, catalyst nanoparticles (often containing metallic atoms) are first formed on the substrate. The substrate can be crystalline or amorphous. Because the diameter of the nanowires depends on the size of the nanoparticles, controlling their properties is important. First, we consider the material that is being used as the catalyst. Choice of the appropriate catalyst material is strongly influenced by the intended use of the nanowires. To be compatible with silicon technology, we don’t want the catalyst material to negatively impact the properties of the nanowire. The solid solubility of the catalyst material in Si should be low so that virtually all of the catalyst remains in the nanoparticle to continue the catalytic reaction. With a low solid solubility, only trace quantities of the catalyst material are incorporated into the nanowire. If the material is a dopant, the magnitude of the conductance and the conductivity type of a lightly doped nanowire can be changed by the incorporated catalyst atoms. However, when

Fig. 9.6. The nanowire diameter can be varied over a wide range – at least 5–200 nm – by controlling the diameter of the catalyzing nanoparticle and the nanowire growth conditions. (a) Ti catalyst; (b) Au catalyst

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other dopant atoms are purposely introduced into the nanowire, the required dopant concentration is expected to be fairly high in order to be useful with the small dimensions of a nanowire; consequently, the fractional change in conductance by the incorporated catalyst may be small. Many metals introduce deep energy levels within the semiconductor bandgap, and the behavior of the semiconductor devices can be degraded by unwanted recombination and generation (R–G) recombination–generation of free carriers through these levels. Rapid recombination removes the “excess” carriers that enable bipolar transistor action, and rapid generation of carriers causes excessive leakage current in p–n junctions. The latter is increasingly important in advanced devices with shallow p–n junctions. The rate U of recombination and generation can be expressed through the Shockley–Read–Hall (SRH) equation [35]: U=

pn − n2i , (p + n + 2ni cosh[(Et − Ei )/(kT )])τ0

(9.2)

where Et − Ei is the energy difference between an allowed “deep” level at energy Et and the intrinsic Fermi level Ei near the middle of the energy bandgap. A positive value of U corresponds to net recombination, while a negative value represents generation. As shown in (9.2), the amount of R–G through the deep levels increases approximately exponentially as the allowed energy levels provided by these R–G centers approach midgap. In addition to small quantities of centers with allowed levels near midgap causing rapid carrier generation and recombination, concentrations similar to the carrier density can immobilize free carriers, making them unavailable to participate in the conduction process. As discussed below, Au nanoparticles are very effective in catalyzing nanowire growth. However, as indicated in Fig. 9.7, Au introduces a deep level very close to the middle of the Si bandgap, making it questionable for use in critical applications. The solid solubility of Au in Si at the nanowire growth temperature might be low enough that the R–G current is acceptable for selected applications. However, compatibility with subsequent processing needs to be considered. For example, stray Au may diffuse into the nanowire and the semiconductor substrate during a moderate-

Fig. 9.7. Electron energy-band diagram of Si, showing allowed deep energy levels introduced by several materials that can act as catalysts for nanowire growth

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temperature thermal oxidation of the nanowire. In addition, the possibility of migration of the catalyst material from the equipment used to process the nanowires into other equipment in a fabrication facility will probably require segregation of the equipment used to grow and further process the nanowires from equipment used for other processing if the catalyst material introduces deep levels into the semiconductor nanowire or the substrate. A wide variety of other catalyst materials have been investigated, including Ni, Pd, Pt, Ti [36], and Ga [37]. Ti serves as an effective catalyst for nanowire growth, as shown in Fig. 9.6(a) and is especially interesting because it is already used in IC production to form the silicide widely used on the source, drain, and gates of MOS transistors. Other silicide-forming metals have also been investigated as potential catalyst materials for nanowire growth; Pt, Pd, and Ni have been considered. All have deep levels within the Si bandgap (Fig. 9.7). Because the deep level introduced by Ti is about 0.34 eV above midgap and Ti has a low solid solubility, it does not create significant R–G current. The deep levels introduced by Pt, Pd, and Ni are displaced from midgap by more than 0.15 eV. Although not as far from midgap as the deep levels formed by Ti in Si, these levels are likely to be acceptable because of the rapid (nearly exponential) decrease in R–G current as the separation of the allowed levels from midgap increases. After the catalyst material is selected, it must be formed into nanoparticles of the desired size on the substrate. Because the nanowire diameter is similar to that of the catalyzing nanoparticle, controlling the size and size uniformity of the nanoparticles is critical to control the nanowire diameter and its distribution [38]. One of several different techniques can be used to form the nanoparticles. They can be formed independently of the substrate and then deposited on the substrate. For example, they can be formed by gas-phase condensation and then deposited in situ on the substrate in the same reactor without contamination by intermediate air exposure; by precipitation in a liquid-phase reaction and supplied in a colloid suspension, which is dispersed on the substrate; or by a liquid-phase chemical reaction directly on the substrate. They can also be formed by CVD directly on the substrate, followed by in situ nanowire growth, again avoiding possible contamination during air exposure between nanoparticle deposition and nanowire growth and also allowing in situ substrate cleaning before nanoparticle deposition. The most common technique used to form the catalyst nanoparticles in a research setting is the deposition of a very thin (<1 nm) metal layer on a substrate followed by annealing at an elevated temperature. Because the layer is very thin, surface energy can cause the deposited layer to agglomerate into isolated nanoparticles, with the size of the nanoparticles being influenced by the amount of material deposited and the annealing conditions. Figure 9.8 shows the variation of nanoparticle sizes that can be obtained [39]. For a fixed annealing temperature of 670◦ C, a bimodal distribution of nanoparticles is obtained when 3 nm of Au is deposited on Si and annealed, while a monodisperse array of small nanoparticles is obtained when only 0.2 nm is deposited. Although this technique is straightforward, native oxide on the substrate or on the metal can limit control of the agglomeration needed to form the nanoparticles.

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Fig. 9.8. Nanoparticle distributions after annealing at 670◦ C: (a) with 3 nm of deposited Au, and (b) with 0.2 nm of deposited Au. Adapted from [39], Fig. 1. Copyright Springer-Verlag, 2005

9.3.2 Nanowire Growth Once the nanoparticles are fabricated on the substrate, the material forming the nanowire can be supplied by one of several different techniques. Physical vapor deposition, such as pulsed laser deposition (PLD) [40], can be used, as can chemical vapor transport [41–43] and chemical vapor deposition [44, 45]. We focus our discussion on CVD because it forms the nanowires in a well-controlled manner and is widely applicable; we illustrate the growth process by discussing the deposition of Si because of the extensive work on Si nanowires and their potential for integration with conventional technology. We then briefly discuss Ge nanowires and nanowires composed of compound semiconductors, which are especially intriguing because of their potential integration onto Si substrates to form optoelectronic systems. To form the nanowires by CVD, the substrate with metal nanoparticles on its surface is exposed at an elevated temperature to a gas containing Si, usually under conditions where Si does not normally deposit at an appreciable rate (e.g., at lower temperatures than those used for normal Si deposition on Si). The catalyst nanoparticles accelerate the decomposition of the Si-containing gas so that Si atoms and byproduct atoms form on the surfaces of the nanoparticles. The byproducts desorb

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into the gas phase. (Under conditions typically used for nanowire growth, the uncatalyzed deposition of Si is often limited by desorption of the reaction byproducts, so the catalyst probably promotes the reaction by aiding desorption of the byproduct.) The Si diffuses through or around the nanoparticle and precipitates between the nanoparticle and the substrate, pushing the nanoparticle away from the substrate and forming a nanowire. Various Si-containing precursor gases can be used, including disilane (Si2 H6 ), silane (SiH4 ), dichlorosilane (SiH2 Cl2 ), and silicon tetrachloride (SiCl4 ), in order of decreasing reactivity; a higher temperature is needed to form nanowires from the less reactive species. The catalyst nanoparticles can be either in the liquid phase or the solid phase during nanowire growth. The former is more common, and whisker or wire growth by this “vapor–liquid–solid” (VLS) process has been well known (albeit at larger dimensions) for more than four decades [41, 46, 47]. More recently, it was extended to the nanoscale [44, 48, 45]. As discussed above, Au is a commonly used catalyst material because it effectively catalyzes growth of nanowires of a number of different semiconductors. For bulk materials, the Au–Si eutectic temperature is ∼360◦ C. Silicon nanowires are typically grown over the range from 500◦ C – 800◦ C, so the nanoparticles are in the liquid phase during nanowire growth. (The eutectic temperature is reduced somewhat below the bulk value because of the small size of the nanoparticles [49, 50]). As discussed above, Ti is also a suitable catalyst for Si nanowire formation. If the nanowires are grown on Si, Ti reacts with Si from the substrate during the heat treatment before growth to form a titanium silicide, probably TiSi2 . The lowest bulk eutectic temperature of the Ti–Si system is above 1300◦ C. Even with moderate reduction of the eutectic temperature because of the small size of the nanoparticles, the Ti nanoparticles are probably in the solid phase during nanowire growth. The details of the growth process using a solid-phase catalyst nanoparticle are analogous to, but somewhat different from, those discussed above for Au. The major difference is expected to be the diffusion of Si atoms from reaction sites on the nanoparticle surface to sites at the nanoparticle/nanowire interface where the Si atoms precipitate [45]. Diffusion through a liquid nanoparticle is many orders of magnitude faster than diffusion through a solid nanoparticle. For a solid nanoparticle, diffusion along the surface of the nanoparticle may become more important than diffusion through the bulk of the nanoparticle. Nanoparticles of other selected silicide-forming metals, such as Pt, Pd, and Ni, are probably also in the solid phase during Si nanowire growth [36]. The shape of the nanowire is usually determined by the ratio of catalyzed growth along the axis of the nanowire to uncatalyzed growth on its sides. If the ratio is low, the nanowire is tapered, with a larger diameter at its base than at its tip. This tapered shape may be useful in selected applications; for example, if the nanowires are used as field emitters, the tip should have a very small radius of curvature to enhance the local electric field, while the body of the nanowire should be broader to decrease series resistance. However, in most applications, a nanowire with constant diameter along its length is desired.

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Fig. 9.9. Scanning electron micrographs of Si nanowires, showing (a) tapered shape when the deposition ambient contains only SiH4 and H2 during growth, and (b) constant diameter when HCl is added to the deposition ambient. (L/D is the ratio of nanowire length to its base diameter.) Adapted from [51]

To obtain a uniform-diameter nanowire, the ratio of uncatalyzed growth on the sides of the nanowire to catalyzed axial growth should be small. The relative growth rates can be controlled by passivating the sides of the nanowires with a species that suppresses uncatalyzed deposition while not severely decreasing the axial growth rate at the catalyst nanoparticle. When CVD is used to grow the nanowires, the ratio can be decreased by controlling the gas-phase species. For Si nanowires, adding a Clcontaining species such as HCl to the gas phase or using a Cl-containing precursor such as SiH2 Cl2 or SiCl4 changes the gas-phase chemistry and the adsorbed species on the sides of the nanowires [51]. Adding HCl to a SiH4 -containing ambient allows independent control of the Cl:Si ratio. Chlorine greatly suppresses the uncatalyzed deposition rate on the Si sides of the nanowires, while only moderately decreasing the catalyzed axial growth rate. Figure 9.9 shows how the shape of the nanowire can be varied from (a) tapered with no Cl added, to (b) uniform diameter with a 1:1 Cl:Si ratio in the gas phase. Nanowires as thin as 6 nm have been grown, approaching the range where the Si bandgap starts to increase with decreasing physical size of the structure and quantization effects become noticeable. Analogous control of the nanowire shape is possible for InP nanowires [52]. When the nanowire is grown on a crystalline substrate, the growing nanowire can continue the substrate crystal structure so that the nanowire grows epitaxially on the substrate; that is, the nanowire growth direction with respect to the substrate is determined by its preferred crystalline growth axis and the orientation of the corresponding directions in the substrate. For such epitaxial growth to occur, the catalyst nanoparticle must be in intimate contact with the substrate; contamination between the catalyst nanoparticle and the substrate can prevent such contact. When the catalyst forms a liquid alloy with the substrate, movement of substrate atoms into

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Fig. 9.10. Germanium nanowires growing epitaxially on Si, showing that the nanowires preferentially grow along continuations of the 111 directions of the Si substrate. (a) On Si(001), with the 111 directions at 54.7 ◦ from the substrate normal. (The nanowires that appear vertical actually extend into or out of the plane of the paper, and complete the set of four equivalent 111 directions.) (b) On Si(111)-4 ◦ , with the 111 directions nearly normal to the substrate. Reproduced with permission from [54]. Copyright 2004 Am. Chem. Soc.

the nanoparticle helps provide a clean substrate/nanoparticle interface on which the nanowire can grow. The nanowires often grow along 111 directions. If they are aligned epitaxially during growth, they grow along directions that continue the 111 directions of the substrate. When the technologically important Si(001) orientation is used as the substrate, the nanowires grow in four equivalent directions at approximately 54.7 ◦ from the substrate normal, as shown in Fig. 9.10(a). When Si(111) is used, the nanowires can grow nearly perpendicular to the substrate [Fig. 9.10(b)], as is critical for selected applications. 9.3.3 Germanium and Compound-Semiconductor Nanowires Germanium nanowires [53, 54] can also be grown by similar metal-catalyzed techniques on a Si substrate (Fig. 9.10); however, Si nanowires often form more readily. The catalysts useful for growing Ge nanowires are much more limited, with reported work focusing almost exclusively on Au. Ge nanowires can be grown in the low300◦ C temperature range. Although this temperature is below the bulk Au–Ge eutectic temperature (∼360◦ C – nearly the same as for Au–Si), the eutectic temperature is expected to be reduced somewhat because of the small size of the nanoparticles. Therefore, Ge nanowire growth is likely to occur by the VLS mechanism. Below a critical temperature, nanowire growth abruptly ceases, again supporting a growth mechanism involving a liquid catalyst nanoparticle.

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Nanowires of compound semiconductors (e.g., GaAs [55] and ZnO [56]) can also be formed by metal-catalyzed growth techniques, widening potential applications to optoelectronic, as well as electronic, devices. In addition to nanowires formed by a single semiconducting material, nanowire heterostructures can be formed by sequentially depositing different semiconductors [57, 58]. If deposition of both semiconductor materials is catalyzed by the same metal nanoparticles, segments of different materials can be grown along the axis of a nanowire by sequentially changing the gaseous precursors, creating heterojunctions between the adjacent segments. These heterostructures can be especially useful in optically active devices made from compound semiconductors, where different segments along the length of the nanowire can have different optical properties. Systems can then be tailored for specific optoelectronic applications; for example, some segments can emit light while others do not [57]. The small area of the boundary between nanowire segments of different materials avoids an inherent difficulty with most heteroepitaxial growth. Two-dimensional layer growth of one semiconductor on another is limited by differences in the lattice parameters of the two materials and also by differences in thermal expansion coefficient and crystal structure. As discussed in Sect. 9.2, strain energy in the heteroepitaxial system increases as the deposited layer becomes thicker. When the strain energy exceeds that needed to form crystal defects, the quality of the layer degrades as misfit dislocations and other defects form. When the area of the deposit is limited, as it is for nanowires, the small diameter allows the lattice planes to distort in the lateral direction to relieve much of the strain arising from even highly lattice mismatched materials, permitting growth of high-quality, single-crystal nanowires containing segments of lattice mismatched materials. In addition, any defects that form at the interface may propagate at an angle to the nanowire growth axis and terminate at the sides of the nanowire, preventing their extended propagation in the axial direction. However, the transition from one semiconductor material to another during nanowire growth limits the possible useful combinations of semiconductors [59]. Significant amounts of the semiconductor elements can be in the molten catalyst nanoparticle during nanowire growth. When the incoming, gas-phase species are changed, the corresponding transition of materials within the nanoparticle may take significant time (corresponding to a significant length of nanowire growth) so that the spatial transition from one material to another along the length of the nanowire is not abrupt. In other cases, atoms of the element that is being decreased have high vapor pressure and rapidly escape from the nanoparticle into the gas phase when the gas-phase partial pressure is reduced, allowing a spatially abrupt transition between segments of the growing nanowire. In addition to forming axial segments of different semiconductors, a “core-shell” nanowire heterostructure can be formed. A nanowire of one semiconductor is first formed by metal-catalyzed grown; the growth conditions are then changed so that a layer of a different semiconductor is grown by uncatalyzed CVD on the sides of the nanowire to form the core-shell structure. For example, a Si shell can be grown around a Ge nanowire [60] to create a structure that confines holes away from the

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surface of the composite nanowire because of the valence-band offset between Si and Ge. The heteroepitaxial growth of nanowires can be extended to growth of Ge or compound semiconductor nanowires on a Si substrate, again avoiding strain-induced defects because of the small cross-sectional area of the boundary between the substrate and the nanowire [61]. Such combinations of materials offer the possibility of integrating efficient optoelectronic devices with Si ICs to form integrated systems with both efficient optoelectronic components and complex electronic functions. The small area of the boundary between the nanowire and the substrate also avoids another difficulty that can occur when polar compound semiconductor layers are grown on a non-polar Si substrate: The compound semiconductor is formed by two elements, either of which can form the first layer deposited on the Si substrate. “Domains” with different stacking sequences can nucleate nearby on the surface. For two-dimensional growth, “domain boundaries” (or “antiphase domain boundaries”) form when these domains impinge during continued deposition and degrade the quality of the deposited layer. The cross-sectional area of the nanowire can be smaller than the size of a domain so that no domain boundaries form. Several recent studies have reported the growth of nanowires of different materials on Si, showing that the lattice misfit can be efficiently accommodated. Germanium nanowires have been grown on Si, which has a ∼4% lattice mismatch with Ge, as shown in Fig. 9.10 [54]. When one semiconductor is grown on a different semiconductor, the initiation of the growth process is more complex than for a homoepitaxial structure. For example, at the beginning of Ge nanowire growth on a Si substrate, a liquid Au–Si eutectic alloy is present. As Ge atoms are introduced into the alloy, they create a more complex ternary alloy system. However, the Au–Ge eutectic temperature is nearly the same as the Au–Si eutectic temperature, possibly reducing the complexity of the mechanisms involved. In addition to single-element semiconductor nanowires, compound semiconductor nanowires can also be grown on Si substrates. Epitaxial growth of oriented GaP (less than 0.4% lattice mismatch), GaAs, and InP (8.1% lattice mismatch) nanowires on Si(111) substrates has been reported [61, 62]. High-resolution TEM has shown the high crystalline quality of GaP nanowires grown on Si [61] and InP nanowires on Si [62]. Although high-quality compound semiconductors can be grown on Si, there is no guarantee that the electrical connection between them will be useful. The band alignments between the Si substrate and the compound semiconductor nanowire must be considered in detail. The different electron affinities and bandgaps of different semiconductors may create a barrier even at a crystallographically ideal interface. Interface states may also change the electrical properties. 9.3.4 Doping Nanowires For use in electronic devices, dopant atoms can be added to the nanowires. Several different doping regimes are of potential interest: (1) Lightly doped, so that the depletion region width is greater than the nanowire diameter. This case is of potential

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interest when carriers are to be induced by a radial electric field so that the conductance of the nanowire is initially low and is increased by the electric field. For the small dimensions of interest in nanostructures (∼10–100 nm), this case corresponds to dopant concentrations (in Si) less than ∼1017 –1018 cm−3 . (2) Moderately doped, so that the depletion region occupies only a fraction of the nanowire diameter and the conductance can be decreased or increased by modulating the radial electric field. This region corresponds to dopant concentrations ∼1018 –1019 cm−3 . (3) Heavily doped, so that the depletion region is much smaller than the nanowire diameter and an external radial electric field cannot significantly modulate the conductance of the nanowire. This case is of interest when the nanowires are used to interconnect active devices. For thicker (∼100 nm diameter) Si nanowires grown by CVD, the dopant can conveniently and effectively be added from a gas-phase species during nanowire growth. The p-type dopant boron and the n-type dopant phosphorus can readily be incorporated into the nanowires during growth by adding diborane B2 H6 or phosphine PH3 , respectively, to the H2 /SiH4 /HCl ambient in the deposition chamber. Current-voltage measurements between two electrodes confirm that the carrier concentration increases with increasing B2 H6 partial pressure in the deposition ambient. These electrical measurements and the dimensions of the nanowires indicate boron concentrations in the low-1018 cm−3 range in the nanowires. This concentration is of the same magnitude as that found for epitaxial silicon deposited on a plane silicon surface, indicating that controllably doping thicker nanowires is feasible. The details of the doping process during catalyzed growth of nanowires may differ significantly from those during uncatalyzed growth. However, if the doping process is limited by desorption of hydrogen from the surface, the catalyst may increase the rate of dopant incorporation, as well as the axial nanowire growth rate. Doping a thinner nanowire is expected to be more complex because of the close proximity of the atoms in the nanowire to the surface and the statistically small number of dopant atoms in a nanowire a few nanometers in diameter. The dopant atoms might segregate to the surface of the nanowire during or after growth (especially for n-type dopants), or the number of dopant atoms might be so small that the potential fluctuates along the length of the nanowire, impeding current flow. Omitting the dopant atoms during growth and adding dopant (if needed) to the exposed surface of the nanowire after growth might provide better process control in thin nanowires. 9.3.5 Connecting Nanowires Isolated nanowires have potentially useful properties. However, the full benefit of nanowires cannot be realized until they are integrated with other nanowires and mechanically and/or electrically connected to other components and a supporting substrate. Two fundamentally different approaches are being explored to integrate the nanowires. First, the nanowires can be grown on the substrate on which they will be used. Second, the nanowires can be grown independently and then assembled onto a substrate. We explore each of these techniques below.

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Fig. 9.11. Current–voltage characteristics of p–n junctions grown (a, b) at nanowire-substrate interface, and (c) within the nanowire, as indicated in the insets. Reproduced with permission from [63]. Copyright 2005, The Electrochemical Society

For devices that rely on current flow through a nanowire, good electrical connections must be made to both ends of the nanowire so that it can perform useful electronic or optoelectronic functions. Metal contacts can be placed on the nanowire, but the ends of the nanowire must be heavily doped or the work function of the nanowire/metal combination must be carefully selected and interface properties must be carefully controlled. The ability to grow the nanowires on a substrate offers the possibility of forming a low-resistance, direct semiconductor-to-semiconductor connection during growth, which could lead to novel devices, as well as reliable electrical connections. As discussed in Sect. 9.3.2 and shown in Fig. 9.10, nanowires can be grown epitaxially oriented on a Si substrate with a continuous crystal structure across the interface [45]. Because of this continuous crystal structure, a high-quality electrical connection between the nanowire and the substrate is expected. When doped Si nanowires are grown on a Si substrate of the same conductivity type, the current flow through the structure appears to depend linearly on voltage [63]. These results indicate that the grown connection between the nanowire and the substrate is ohmic (i.e., the current is not limited by contact resistance), as is reasonable because of the intimate epitaxial connection formed between the nanowire and the substrate. When the nanowire is doped with the opposite type dopant from the substrate dopant, a rectifying junction is obtained, as shown in Figs. 9.11(a) and (b). In addition, the dopant type can be changed from one conductivity type to the other after a portion of the nanowire is grown, creating a p–n junction with a rectifying characteristic within the nanowire itself [Fig. 9.11(c)]. These observations demonstrate the possibility of making one electrical connection to the nanowire through the substrate on which it is grown, possibly connecting the nanowire to other circuitry already present in the substrate. A single connection to a nanowire can be useful for specialized devices. For example, a nanowire fieldemitter only requires one electrical connection to the nanowire [64, 65]. Electrons emitted from the nanowire travel across a vacuum and are collected by a separate electrode. Devices that rely on the mechanical properties of the nanowires can also be useful with one connection to the nanowire to form a cantilever structure with a high mechanical resonant frequency [66, 67]. However, most devices require connection to both ends of a nanowire. Contacting the other end of the nanowire is less straightforward, but is possible using the

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directional growth of the nanowire. As discussed above, nanowires often grow in 111 directions and perpendicular to {111} surfaces. This behavior can be used to obtain firm connections to both ends of a nanowire by forming two nearby vertical Si{111} surfaces and then growing the nanowire between them. Vertical Si{111} surfaces can be conveniently formed by well-known, anisotropic wet chemical etching of a (110)-oriented Si layer [68]. The Si layer can be either a bulk Si wafer or the top Si layer of a silicon-on-insulator (SOI) substrate. This orientation of Si has two sets of {111} planes perpendicular to the surface. A pattern is first formed in an overlying masking layer, such as SiO2 . The Si layer is then etched with an anisotropic etchant, such as KOH, which attacks Si{111} planes much less rapidly than other planes, so that the structure formed is bounded by vertical Si{111} planes. This procedure can be used to form trenches in a bulk wafer or electrically isolated electrodes on an SOI substrate. Catalyst nanoparticles are then formed on the sides of one or both of the parallel, vertical Si{111} surfaces, and nanowires are grown. The nanowires grow perpendicular to the Si{111} surfaces on which the catalyst has been placed; that is, laterally, parallel to the substrate surface and across the gap toward the second {111} surface [69, 70]. When a nanowire reaches the second electrode, it physically touches the electrode. Continued deposition forms additional material that essentially “welds” or bonds the nanowire to the second surface, as shown in Fig. 9.12. This “bridging” nanowire growth can be achieved with either liquid or solid-phase catalyst (e.g., Au or Ti, respectively). After the nanowire is connected to the second surface, some of the catalyst can migrate along the surface of the second electrode. If the deposi-

Fig. 9.12. Schematic diagrams and corresponding scanning electron micrographs of bridging nanowires growing laterally across a trench etched into a Si(110) substrate and bounded by Si{111} planes. The nanowires make mechanical and electrical connection when they impinge on the opposing wall of the trench. Adapted from [69], reused with permission. Copyright 2004, IOP Publishing Ltd.

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tion process continues, a secondary nanowire can nucleate at this catalyst and grow back toward the first surface, forming another bridging nanowire. As for nanowires grown on a planar surface, the diameter of the bridging nanowires can be changed by controlling the diameter of the catalyst nanoparticles. Bridging nanowires with diameters spanning the range from less than 20 nm to more than 200 nm have been formed. Both connections of the nanowire to the Si surfaces are mechanically strong. When the structure is stressed to failure, the failure usually occurs along the length of the nanowire away from either end. Detailed, high-resolution, transmission electron microscopy of the impinging connection of Au-catalyzed Si nanowires [71] shows that the connection of the nanowire to the sidewall forms a Si–Si interface. The lattice appears to be continuous across the interface, and no Au is detected at the interface. The Si nanowire appears to bond directly to the small amount of Si growing epitaxially on the second sidewall. (The epitaxial Si on the second sidewall probably grows through gaps in the native oxide on the etched surface of the sidewall; the quality of the connection can be improved by optimizing the process to minimize native oxide.) The liquid Au–Si eutectic is squeezed out of the interface region and diffuses along the sidewall. The Au on the sidewall catalyzes further Si deposition there, forming a disk surrounding the end of the nanowire (Fig. 9.13), with the Au remaining at the top of the catalyzed, disk-shaped deposit. When p-type electrodes are formed from an SOI structure and the nanowires are doped with boron during growth, the current–voltage characteristic between the two electrodes is generally linear, suggesting that the nanowires make good electrical connection to the electrodes during growth. Figure 9.14 shows the linear currentvoltage characteristics between electrode pairs connected by different numbers of bridging nanowires. The current scales approximately linearly with the number of nanowires between a pair of electrodes. The conductance between the electrodes can also be changed by varying the partial pressure of the B2 H6 dopant gas introduced

Fig. 9.13. After the nanowire joins the second surface, Au diffusing on the sidewall catalyzes further Si deposition and forms a disk of Si covered with Au on the sidewall surrounding the end of the nanowire. Reused with permission from [69]. Copyright 2004, IOP Publishing Ltd.

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Fig. 9.14. (a) Schematic diagram, and (b) scanning electron micrograph of electrically isolated structure with bridging nanowires connecting electrodes formed from an SOI substrate. (c) Current flowing between electrodes spaced 10 μm apart and connected by 6, 4, or 1 nanowires with diameters in the range of 100–150 nm. Adapted from [70], Figs. 8 and 10. Copyright Springer-Verlag, 2005

during nanowire growth. Both observations indicate that the conductance between electrodes is dominated by the nanowires, again suggesting that the nanowires make good electrical contact to the electrodes during growth and that the current is not significantly limited by contact resistance between the nanowires and the electrodes. In addition to Si nanowires, InP nanowires have also been grown in the bridging configuration between two vertical Si(111) surfaces separated by a gap [62]. As in the case of Si nanowires, the InP nanowires grow from one Si surface across the gap and attach to the Si surface at the opposite side of the gap. As discussed earlier, the small contact area between the Si surface and the InP nanowire allows a high-quality, compound-semiconductor nanowire to grow on the Si surface of the electrode. This type of heterostructure may be useful for combining the optoelectronic functions possible in compound semiconductors with conventional Si circuitry formed in the Si substrate. Bridging nanowires can also be grown in a vertical configuration. For example, one of the electrically isolated electrodes can be the substrate, and the other can be a portion of the Si layer of an SOI structure. The gap is formed by laterally etching the oxide layer between the two Si surfaces to form a recess. The nanowire is then grown from the top of the Si substrate across the recess to the bottom of the Si layer. While growing the nanowires on the substrate on which they will be used avoids extra processing to assemble the nanowires after growth, it has some limitations. For example, the nanowire growth temperature might be higher than can be tolerated by

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the substrate on which it is being grown. Si nanowires can be grown at temperatures as low as 400◦ C [44]; however, their properties are better controlled when the nanowires are grown at higher temperatures. If the nanowires are to be grown onto a conventional Si IC, the growth temperature is limited to approximately 400–450◦ C for conventional metalization systems and to even lower temperatures if the metal layers on the IC are isolated by low-permittivity dielectrics with limited thermal stability. The use of other substrates may restrict the allowable temperature range during nanowire growth even further. Germanium nanowires can be grown at lower temperatures than Si nanowires (as low as ∼300◦ C), making them more compatible with advanced ICs. However, temperature constraints limit the flexibility of choosing the nanowire material and the subsequent processing used to fabricate nanowire devices and to control the device characteristics. The alternative approach of first growing the nanowires and subsequently transferring them to the device substrate removes this temperature constraint, at the cost of additional processing. The nanowires can be grown on a substrate that is compatible with the growth process or on an arbitrary surface in the deposition chamber and then mechanically removed from the substrate. The nanowires can then be individually manipulated into the correct position on a substrate, for example, one containing electrodes. Nanomanipulators, often based on atomic-force microscope techniques, can be used to allow imaging during manipulation. Alternatively, the nanowires can be randomly dispersed on an unpatterned surface and observed by scanning electron microscopy. The scanning electron microscope can then be used to expose resist to define electrodes at the ends of the nanowires that were just observed. While these individual assembly techniques are useful for studying the properties of the nanowires and exploring their use in novel devices [72], they are not suitable for mass fabrication. In one technique potentially leading toward a more manufacturable method of assembling nanowires after growth, the nanowires are be placed in suspension in a liquid after they are removed from the surface on which they are grown. Some of the fluid is placed on the surface of the substrate, and nanowires are randomly dispersed on the surface. A predetermined electrode pattern can then be added. Alternatively, the electrodes can be formed first, and then the nanowires can be randomly dispersed. The number of nanowires connecting the electrodes is statistically determined. However, the technique can be useful if the number of nanowires between electrodes is √ large because the fractional difference between devices decreases as 1/ N, where N is the number of nanowires between the electrodes. A refinement of this technique uses “fluidic” self- or directed-assembly, which is being explored as a practical means of positioning nanowires on a substrate [73]. After the nanowires are removed from the growth substrate and placed in suspension in a fluid, the fluid is allowed to flow across the surface of the substrate, again depositing some of the nanowires on the surface. To place the nanowires in selected areas, micro-channels can be etched into the surface of the substrate before the nanowires are added; the nanowires are most likely to be deposited in these channels, rather than in the higher surrounding regions where the force from the moving fluid is greater. Similarly, areas of the substrate can be treated so that nanowires preferen-

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tially adhere to these regions as the fluid flows across the substrate. Repeated use of “fluidic assembly” can create more complex structures. Although fluidic assembly techniques can be used to deposit the nanowires in selected regions of arbitrary substrates, the density is again statistically controlled and depends on the concentration of the nanowires in the liquid, the conditions under which the fluid flows, and the attractive force of the selected regions of the substrate on the nanowires. Electric fields between pre-formed electrodes can also be used to position nanowires in selected locations [74]. However, applying electric fields during processing of complex patterns is difficult. 9.3.6 Comparison of Semiconducting Nanowires and Carbon Nanotubes Nanowires can be formed from a number of different materials, with semiconductors being most widely studied. They are often compared to the analogous onedimensional carbon nanotubes (CNTs). Carbon nanotubes [75] are unique structures formed by wrapping the “chicken-wire” lattice structure of the two-dimensional graphite lattice into a cylinder, as indicated in Fig. 9.15. Single-wall nanotubes have walls only one-atomic layer thick and usually have diameters of about 1.4 nm. Multiwall nanotubes are composed of concentric graphite-like shells and can have diameters much larger than single-wall nanotubes. The electrical properties of the nanotubes depend strongly on how the ends of the lattice are joined when it is rolled and connected to form the cylindrical nanotube. This “chirality” determines whether the nanotube is metallic or semiconducting. To date, many attempts have been made to obtain pure metallic or pure semiconducting sets of nanotubes either during growth or by selection after growth, but with limited practical results. However, if the nanotubes can be reproducibly controlled to be semiconducting, the extremely small amount of material comprising the nanotube should make modulating the carrier density and conductance in a CNT field-effect transistor very efficient [76, 77]. Because of the essentially two-dimensional nature of the walls of the nanotubes, few dangling bonds exist, and the nanotubes do not readily react with nearby materials. While this lack of reactivity allows for nearly ideal surface properties, the lack of reactivity can be a drawback for some applications. For example, forming low-resistance connections to a nanotube is difficult [78], and most transistors made using CNTs as the channel are limited by Schottky-barrier contacts. The lack of

Fig. 9.15. Carbon nanotubes are formed by rolling the hexagonal graphite lattice into a cylinder. Single-wall nanotubes are one atomic-layer thick. Multi-wall nanotubes contain concentric shells of carbon atoms

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bonding sites also inhibits forming a well-bonded insulator on a nanotube to create a field-effect structure and complicates selective functionalization for sensors. Progress has been made to create defects along a nanotube to act as sites where other atoms or molecules can be controllably attached. In addition to CNTs, nanotubes of boron nitride or mixtures of boron nitride and carbon have been formed. In contrast to the unique properties of CNTs, the properties of semiconductor nanowires are similar to those of the corresponding bulk materials (at least for larger diameters). The nanowires are solid so that more material is present than in a nanotube. When the nanowire diameter is small, the properties are likely to depart from the bulk properties. For example the effective bandgap is expected to increase, with resulting changes in the electrical and optical properties; these changes can be predicted, at least qualitatively. Silicon and Ge nanowires with diameters greater than about 5–10 nm exhibit bulk properties; the transition diameter is expected to be somewhat greater for the compound semiconductors with their lower carrier effective masses. The surfaces of the nanowires resemble those of well-studied semiconductor surfaces, and surface passivation procedures are expected to be similar. However, the presence of different crystallographic orientations around the circumference of a nanowire will affect the number of surface states present.

9.4 Potential Applications of Metal-Catalyzed Nanowires 9.4.1 Field-Effect Transistors Because of their small diameters and controlled electrical properties, nanowires can serve as the channels of field-effect devices. In these devices the conductance of the nanowires is modulated by an external electric field applied perpendicular to the nanowire axis. The device can be a field-effect transistor, with the field created by a gate electrode deposited on the surface of an insulating layer surrounding the nanowire. Nanowire transistors made from Si have been considered in most detail, and initial attempts have been made to efficiently connect nanowires [79]. Transistors made from Ge nanowires have also been demonstrated [80]. In these Ge devices, the poor-quality native oxide on the surface of the Ge nanowire is removed and replaced by a high-permittivity dielectric formed by atomic-layer, chemical vapor deposition (ALD). Most of the work on nanowire field-effect transistors has used nanowires that were individually positioned on a substrate after growth or by using fluidic alignment [79]. However, field-effect transistors have been fabricated using Si nanowires connected to the substrate on which they were grown [63, 81]. Vertical nanowire field-effect transistors of other semiconductors, such as ZnO [82] have also been fabricated. In any field-effect device that depends on depletion of mobile carriers to modulate the conductance of the nanowire, there are interrelated constraints on the diameter and doping of the nanowire. If either the diameter or the dopant concentration is too large, the entire diameter cannot be depleted of mobile carriers to reach the OFF state of the device. The limited thickness of the depletion region sets an upper bound

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on the dopant concentration for a given nanowire diameter. On the other hand, if unmodulated portions of the nanowire are to be used as interconnections between active elements, a high conductance is needed to avoid voltage drops along the nanowire and to allow rapid charging of devices. Thus, a trade-off must be made between the ability to modulate the conductance of the nanowire and the interconnection resistance. For the maximum dopant concentration that can be depleted, the resistance of a nanowire is of the order of 100 K for a 1 μm length of nanowire with 20 nm diameter. This high resistance can limit the switching speed of devices that must be charged through the nanowire. 9.4.2 Field-Effect Sensors In addition to forming transistors, nanowire field-effect devices can be used to sense nearby species. If the gate electrode of a nanowire field-effect structure is omitted, the conductance is sensitive to charge near the surface of the nanowire. When a “functional” coating that interacts only with selected species is added to the nanowire surface, the device can be an efficient nanosensor. Such sensors can be used to detect dangerous species or analyze materials such as DNA [83]. For example, a probe DNA species can be added to the surface of the nanowire. When exposed to a fluid containing DNA, only complementary DNA binds to the probe DNA. Because DNA is negatively charged, additional positive charge is induced in the nanowire when complementary DNA binds to the probe DNA, modulating the conductance of the nanowire. When only non-complementary DNA is present, appreciable binding does not occur, and the conductance of the nanowire is substantially unchanged. Similarly, other charged target species can be detected by using a suitable probe molecule on the surface of the nanowire. Because the electrodes of the nanowire sensors can be formed by conventional lithography, the nanosensors can be integrated with conventional electronics in the surrounding Si regions to form a sensor array. When nanowires between different electrode pairs are functionalized to be sensitive to different species, an efficient chemical or biological sensor system can be constructed. The small signals from the individual sensors can be compared to a reference signal and amplified in the nearby conventional circuitry and then converted to digital form for further processing. The signals from different nearby sensors can be multiplexed and transported to further processing circuitry and transfer off the chip. 9.4.3 Interconnections One of the major limitations of conventional electronics is interconnecting the active electronic components. Both nanowires and carbon nanotubes have been proposed as the vertical interconnecting elements between layers of horizontal inter-

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connections [84]. For this application, process compatibility is critical because the nanostructures will probably need to be grown at specific locations on the partially fabricated underlying circuit. In particular, most conventional ICs are fabricated on Si(001). Consequently, developing techniques that can grow nanowires in 100 directions (i.e., perpendicular to {100} surfaces) is especially important. Alternatively, pre-formed nanostructures can be placed on the circuit to serve as vertical or horizontal interconnections, rather than growing the interconnecting nanowires in place.

9.5 Summary Self-assembled nanostructures offer a potential route to mitigate the physical and economic limits of conventional top-down fabrication. Combining these bottomup approaches with the extensively developed top-down approaches may extend Moore’s law of exponentially increasing functionality beyond that currently envisioned. Strain-induced nanostructures and metal-catalyzed nanowires are two classes of nanostructures formed by self assembly, with the latter offering a better-defined path toward process integration and applications. The stress in lattice-mismatched heteroepitaxial layers can be relieved by expanding into the third dimension to form small islands or quantum dots, which may take characteristic, low-energy shapes. When the strain is anisotropic, the islands can form long, narrow quantum wires on the substrate surface. Metal-catalyzed nanowires extending out of the substrate plane are grown when a catalytically active nanoparticle is exposed to a precursor containing the nanowire material. Selecting a suitable catalyst and forming the nanoparticles are critical because the nanowire diameter is usually similar to the diameter of the nanoparticle. The nanoparticle can be either in the liquid or solid phase during nanowire growth. Nanowires can be grown epitaxially on a substrate. Because of the small contact area, the nanowire material can have a different lattice parameter than that of the substrate, potentially allowing integration of compound semiconductors on a Si IC. Connecting nanowires to form a practical system remains a challenge. Growing the nanowires between pre-formed electrodes is a useful technique to form connections to both ends of a nanowire. p–n junction diodes have been fabricated within nanowires and at nanowire/substrate interfaces; field-effect transistors and sensors have been formed by inducing charge in nanowires to modulate their conductance.

Acknowledgement The author thanks Dr. R. Stanley Williams of the Information and Quantum System Laboratory at Hewlett-Packard Laboratories, Drs. S. Sharma and G. MedeirosRibeiro formerly at QSR (now at Spansion, Inc, Sunnyvale, CA, and LNLS, Campinas, Brazil, respectively), as well as numerous others actively working in the field

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of self-assembled nanostructures. The nanowire studies at Hewlett-Packard are partially supported by the Hewlett-Packard, U. S. Defense Advanced Research Projects Agency (DARPA) and the Province of Alberta through the Canadian National Institute of Technology.

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10 Hybrid CMOS/Molecular Integrated Circuits M.R. Stan, G.S. Rose, and M.M. Ziegler

10.1 Introduction Despite revolutionary advances enabled by process scaling in the past few decades, CMOS silicon technology is likely to run out of steam in the next 10–15 years [1]. The prospect of nanoelectronics offers many potential alternatives; single electron tunneling (SET) devices, resonant tunneling diodes (RTD), rapid single flux quantum logic (RSFQ), spin devices, quantum dots, and molecular electronics are just a few of the novel alternatives being actively investigated [2]. Of these technologies, molecular electronics has preliminary results that promise high device densities and fast switching speeds. Molecular nanotechnology may represent the physical limit of circuit scaling. At this level, devices and wires may consist of a single or just a few molecules. The first foreseeable application of this technology will most likely be memory; however, our work is mainly focused on the information processing capabilities of molecular electronics. A few of the most promising molecular technologies include: carbon nanotubes, ErSi2 , and polyphenylene-based molecules. Molecular and other nanoscale technologies show significant promises but it is unlikely that they will completely replace CMOS, at least not in the near term; hence, there is a need to explore the opportunities for integrating CMOS and nanotechnology to enhance and complement one another in order to sustain the historical advances in the semiconductor industry. 10.1.1 Top-Down Fabrication vs. Bottom-Up Assembly Achieving device densities targeted by many molecular electronic systems, e.g., as many as 1012 devices/cm2 [3], may require a significant change in fabrication philosophy. One key differentiating feature of a nanotechnology is whether the underlying fabrication approach is a “top-down” subtractive method or a “bottom-up” selfassembly process. Many nanotechnologies using top-down approaches, such as silicon and heterojunction RTDs, show good performance. However, the physical dimensions of these devices will be limited by the resolution of the top-down process,

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Fig. 10.1. General assumptions that are typically attributed to top-down fabrication and bottom-up assembly

e.g., lithography. On the other hand, the size limits of bottom-up self-assembly could be much smaller, since assembly can be self-controlled on the atomic or molecular scale. Other general assumptions are that bottom-up assembly approaches will be cheaper, yet may have higher defect rates. Figure 10.1 gives a general overview of common assumptions associated with the top-down and bottom-up fabrication approaches. This chapter focuses on nanotechnologies that employ bottom-up methods, such as chemical self-assembly. Bottom-up approaches typically cannot replicate the complex arbitrary structures achieved by top-down fabrication methods. Thus, bottom-up molecular circuits are presently restricted to either randomly assembled structures or regular, periodic structures. Although methods for obtaining functional circuits from randomly assembled molecular structures have been proposed [4], the success of a non-deterministic circuit paradigm at the system level requires further investigation. On the other hand, a circuit paradigm based on regular, programmable structures does not entail such a drastic departure from conventional deterministic circuit methodologies. Bottom-up regular circuit paradigms can be divided into two subclasses [5]: deterministic regular structures that require the location of all devices and interconnections to be resolved during fabrication, and quasi-regular structures that enforce a regular structure, but allow some randomness in the location of devices in portions of the circuit. 10.1.2 Typical Molecular Device Characteristics Considered in this chapter are nanoelectronic circuits based primarily on two types of molecular devices, each of which are shown in Fig. 10.2. The first device type of interest, the I –V curve of which is shown on the left of Fig. 10.2, is hysteretic switch that can be programmed to function in one of two possible conductivity states. These devices change state only when a voltage applied across them is greater in magnitude than either a positive or negative threshold. If the applied voltage is greater than the positive threshold, the device is forced into the high conductivity state (logic 1).

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Fig. 10.2. Generic I –V characteristics of a programmable molecular switch (left) and a device exhibiting NDR (right). Also shown in the center of the figure is an illustration of a SAM molecular device

Likewise, a voltage less than the negative threshold forces the circuit into the low conductivity state (logic 0). The second type of nanoscale device utilized in some of the circuits explored here is based on a property known as negative differential resistance (NDR). Shown on the right of Fig. 10.2, NDR is a non-classical characteristic where the current through the device decreases as the voltage increases. As will be discussed in Sect. 10.3.3, NDR devices can be used for providing signal restoration in cases where only two-terminal devices are available. Devices exhibiting the characteristics described and shown in Fig. 10.2 have been fabricated using various technologies, including solid-state structures, spintronics, and molecular electronics. In fact, the property of hysteresis observed so commonly in molecular electronics seems to be a typical characteristic of several emerging nanotechnologies, for example magnetoresistive random access memory (MRAM). With that, it is worth pointing out that the circuits and architectures described here could be implemented using any one of a variety of nanoelectronic paradigms. The remainder of this paper, however, considers a class of molecular electronics based on self-assembled monolayers (SAM) of molecules that has been shown to include devices of each of the types described in Fig. 10.2. Included in the center of Fig. 10.2 is an illustration of what such a SAM-based device might look like.

10.2 MolMOS: Integrating CMOS and Nanoelectronics Nanoelectronics is promising, given the expected high device densities, but may be limited in various ways, including how such circuitry interfaces with the external world. This leads to the need to interface nanotechnology with more conventional electronics (i.e., silicon-based technologies) for I/O, as well as the need to overcome any technology-based limitations. For the rest of the chapter, for brevity, conventional silicon electronics, including future variations of silicon MOSFET-based electronics, is referred to as “CMOS”. Likewise, the term “nano” is used in reference to novel nanoscale electronics. Previously proposed nanoarchitectures suggest mixing different molecular nanotechnologies on the same surface in order to achieve computation [6, 7]. While such

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Fig. 10.3. Proposed design paradigm involving nanoelectronics on a CMOS IC

solutions may be achievable in the long term, integration challenges significantly increase manufacturing complexity. Keeping in mind the difficulties in fabricating a molecular electronic technology alone, integrating such circuits on top of a prefabricated CMOS IC, as shown in Fig. 10.3, should be more feasible in the near term, while also providing a robust computing paradigm. Since the focus of the work presented here is on the integration of molecular electronics and CMOS, this design paradigm is referred to as MolMOS [8–10]. 10.2.1 The CMOS/Nano Interface The interface between CMOS and nano is particularly important as the physical properties at the interface create a number of fabrication challenges. However, there are also higher-level issues when considering the CMOS/nano interface. Previous nano interface suggestions include nano decoder designs that are stochastic [11] or require nanoscale patterning resolution [12]. These CMOS/nano interface designs attempt to achieve the following two goals: Pitch Reduction – Communicating signals from the wire pitch in the CMOS technology, i.e., the microwire pitch (Pmicro ), to the nanoscale pitch in the nanotechnology, i.e., the nanowire pitch (Pnano ). Decoding – The ability to address a large code space in the nanowire crossbar with a smaller number of CMOS wires. For the purpose of decoding, researchers have made several proposals including: (1) programmable decoding within a regular array of molecular devices [8], (2) using nanowire transistors gated by microwires [7], and (3) direct connections from CMOS to nano wherein decoders are entirely implemented within the CMOS layer [13]. While decoding is an important component of the CMOS/nano interface, all of the

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Fig. 10.4. Pitch reduction scheme for a self-assembly or nanoimprinting paradigm. Two triangular masks are used for patterning the nanowire ends at an angle (the nanowire mask in the upper-left half) and the microwire ends (the microwire mask in the lower-right half)

suggested proposals require an interface between the two technologies for complete pitch reduction. Figure 10.4 illustrates a potential solution for pitch reduction and for interfacing lithographic microwires to nanowires. The scenario assumes a bottom-up assembly approach where the nanowires can only be assembled into regular structures, such as in [14]. As shown in Fig. 10.4, this approach begins with parallel nanowires perpendicularly overlapping an equal number of parallel microwires. Two masks are then used to remove portions of the nanowires and microwires along a diagonal. This process assumes that the nanowires and microwires can be etched separately. The reliance on nanoscale pattern resolution is shifted to mask alignment precision. Using the rule of thumb that alignment will be equal to approximately one-third of the line width, this approach should be able to increase the nanoscale pitch Pnano to at least the microwire line width (Wmicro ), as depicted in Fig. 10.4. Additional mask alignment accuracy as well as a number of other variations to this scheme should allow Pnano to be even smaller [8]. The critical factor in the approach of Fig. 10.4 is that the wires are cut along an angle α in such a way that the pitches of the two technologies align. This same technique is proposed for the implementation of a design known as CMOL by Likharev and Strukov [13, 15]. For these approaches, the angle can be obtained from the two

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pitches by α = arcsin(Pnano /Pmicro ). While the original proposal for use of this angle was for cutting the wires to match the pitches [8], in the CMOL design it is proposed that the entire nanoscale array be rotated by α [13, 15]. 10.2.2 CMOS/Nano Co-design The CMOS/nano paradigm allows for significant design versatility. A number of design scenarios can be envisioned depending on the physical characteristics of the specific nanotechnology. One extreme case is having CMOS act as the primary computation medium while the nano layer on top is used as a supplement to better achieve integration goals. For example, the nano crossbar could act as memory or as large logic arrays. Likewise, at the other extreme, the nano portion would be primary while the underlying CMOS would be used simply to provide signal gain, latching capabilities, and I/O. A more balanced approach would use both mediums for primary computation with portions of the circuit being allocated either to CMOS or nano at a finer grain [8]. New design methodologies are needed for mixed CMOS/nano circuits. The possibility of high device densities for nano combined with the present challenges of CMOS design point towards a highly automated methodology. Figure 10.5 shows a generic design methodology for a CMOS/nano circuit. This is an adapted version of a typical ASIC design methodology and targets scenarios where portions of the circuit can be allocated to either CMOS or nano at a fine grain. The key feature in the figure is the partitioning that occurs after register transfer level (RTL) synthesis. Figure 10.5 also shows the proposed partitioning procedure in expanded detail. The partitioning procedure requires information about the CMOS process characteristics, such as a high-level description of the standard cell library, including gate delay, area, and power estimates for the cells. In addition to functionality, delay, area, power, and defect densities also need to be included in the nanotechnology characterization. Another important metric is the overhead associated with interfacing the CMOS and nano portions of the circuit. A lack of gain in the crossbar technology requires periodic interfacing to CMOS circuitry to restore signal integrity. Signal restoration circuitry may consist of the equivalent of a sense amplifier and a buffer to drive the next crossbar. Thus switching design mediums and restoring nano signals would come with an overhead. Using the CMOS/nano technology characterization and the logic level representation obtained from synthesis, the partitioning procedure goes through four phases of allocation: Pass 1) Default Allocation – This pass allocates to CMOS the portions of the circuits that cannot be implemented in nano. If, for example, the nanoscale is limited to regular arrays, this step would include all analog and amplification portions of the design. Pass 2) Global Allocation – Taking the design constraints and objectives as an input, this pass allocates the portions of the design that are inherently suitable to one of the technologies. For example, the critical path of the circuit may be allocated to the technology that can perform faster computation. Many nanoscale crossbar

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Fig. 10.5. Generic CMOS/nano design methodology (adapted ASIC methodology) and expanded allocation procedure between CMOS and nano

technologies are predicted to perform at slower switching speeds than CMOS, thus the critical path of the circuit will be implemented in CMOS. On the other hand, these same nanotechnologies are predicted to consume less power than CMOS, so large regular structures, such as RAM, will be suited for implementation in nano. In general, it is expected that the I/O, built-in-self-test (BIST), control logic, and sequential processing are better suited for CMOS implementation, while parallel processing and memory are more suitable for implementation at the nanoscale. Pass 3) Local Allocation – This pass uses the interface cost as an aid to determine if circuitry near the previously allocated portions should be located on the same medium. Pass 4) Final Allocation – The remaining portions of the circuit are allocated based on the remaining available resources while trying to optimize the desired figure of merit; for example, area, power, or performance.

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While the first allocation pass occurs only once, the second, third, and fourth allocation passes can iterate until an optimal solution is located. Following the partitioning procedure, the generic CMOS/nano co-design methodology performs technology mapping. The CMOS portion of the design follows a typical ASIC technology mapping flow. On the other hand, the nano portion requires a new method for technology mapping.

10.3 The Crossbar Array for Molecular Electronics Following the high-level description of what goes into the design of a hybrid CMOS/ nano system, the next obvious consideration is just what the nanoelectronics portion might look like. In this section, possible nanoelectronic structures are explored with particular emphasis on what is known as “the crossbar array.” Figure 10.6 shows an abstract representation of such a crossbar structure, consisting of two sets of parallel nanowires crossing perpendicularly. At each junction in this array, there are programmable bistable molecules that can be set into one of two possible conductivity states. Such molecular devices have been fabricated by several groups, including researchers at Hewlett-Packard [16], CalTech [17], Yale [18], and the University of Virginia [19], to name a few. In general, crossbar-based architectures have several advantages, such as programmability, the potential for low-cost fabrication, and high device densities. However, there are also several potential drawbacks associated with most crossbars employing two-terminal devices, especially the lack of signal restoration and the lack of an inverting function [20]. In addition, the regularity of the crossbar nearly inhibits the optimization of parasitics along critical paths, since wire lengths are not determined individually. Furthermore, self-assembled crossbars may also have a propensity for high defect-rates. All things considered, the potential for high device densities, ease of fabrication, low-power operation, and fault-tolerance make the programmable crossbar array an

Fig. 10.6. The crossbar paradigm consists of perpendicular sets of parallel wires with bistable junctions at each wire crossing

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attractive structure for future nanoelectronic computation. Given the programmable nature of the molecular devices considered, one obvious application of the crossbar array is to use it as a nanoscale memory. This nanomemory could be fabricated onchip in a hybrid CMOS/nano system to provide advantages such as reduced access time latency due to the close proximity to the CMOS fabric. Also, a crossbar array of programmable devices could be used for the implementation of logic in the form of a programmable logic array (PLA). Thus, the versatility and potential applications of such crossbar structures have led to great interest in exploring them for nanoelectronics. 10.3.1 Molecular Memory Structures Using molecular switches for memory seems natural since they are essentially tunable devices that can be set into one of two possible conductivity states, one representing logic 1 and the other logic 0. A device can be programmed by applying a large magnitude voltage across it where exceeding a positive threshold will force the device into the logic 1 state and a large negative threshold will write a logic 0. Reading can be achieved simply by applying a voltage smaller than the thresholds and measuring the output current (Iout ). An important metric for such a memory is the ratio of the output currents for logic 1 and logic 0, referred to here as the 1/0 current ratio (F1/0 = Iout1 /Iout0 ). Device Reverse Bias Current and Array Size To effectively read data from the nanoscale memory, the output 1/0 current ratio (F1/0 ) must be as large as possible and must always be greater than one. When this ratio is too small, difficulty arises in trying to distinguish a logic 1 from a logic 0. Since it is desirable that F1/0 be as large as possible, the exploration of any device and circuit-level factors affecting this ratio is an important endeavor. One device characteristic directly affecting F1/0 is the ratio between the forward and reverse bias currents (Ff/r ) or rectification ratio. The closer Ff/r is to one, the closer the device behavior is to that of a resistor. Likewise, device behavior is like that of a diode for Ff/r 1. Thus, it is this ratio that determines the amount of current that flows through parts of the array that are not selected for reading. This can be understood by considering that, as the device is more diode-like (Ff/r 1), the circuit paths in Fig. 10.6, that are parallel to the device being read, are essentially cut-off due to the reverse bias of the diodes. Looking at it another way, one could model the devices that are reverse-biased with a higher resistance than those that are forward-biased. By modeling the devices simply as resistors, a resistor network is obtained consisting of the device being read (Rrd ) in parallel with an equivalent resistance for the unselected devices (Runsel ). If the ratio Ff/r is close to one, the resistance Runsel is closer to and may exceed Rrd of the selected bit. From this perspective, it can be seen that for a large sized array, many devices in the unselected circuit path are in parallel, such that Runsel becomes small. In fact, there is a minimum array size at which Rrd ≈ Runsel , leading to a 1/0

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Fig. 10.7. Maximum array size limited by On/Off ratio of molecular switches

ratio F1/0 ≈ 1. For larger arrays where Rrd < Runsel , the current representing logic 0 becomes greater than that representing logic 1. The point at which the output currents representing logic 1 and logic 0 become indistinguishable can be seen in Fig. 10.7. In this figure, the output ratio F1/0 is plotted against the array size. For the simulation leading to the generation of this plot, the ratio between on and off device currents is about 10. The first point to be noticed from this plot is that F1/0 is smaller for larger-sized arrays, suggesting a limit on array size. These results assume that all unselected rows and columns are left floating while a bias is applied only to the row and column of the selected device. If the unselected rows and columns are grounded, this plot will show a larger maximum array size. It is also worth mentioning that for larger Ff/r , the ratio F1/0 is improved for large arrays, thus allowing for a larger maximum array size. Thus, one way to improve the maximum allowed size of a crossbar memory array is to increase the device property Ff/r . Noise Considerations Important components in any memory architecture are the row and column decoders used to address the individual memory bits for both reading and writing. In a hybrid CMOS/nano system, much of this decoder overhead would be implemented in CMOS. In fact, regardless of how much of the actual decoders are CMOS, the data to and from the nanoscale memory array must at some point be communicated through the CMOS layer. This suggests that an important consideration for the design of such nanoscale memories is the interface between the CMOS and nano layers. Interface in this case would include the row and column decoders as well as any sense amplifiers required for reading and writing the memory from the CMOS layer.

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The first form of decoder explored is based on pass gates or pass transistors such that the unselected rows and columns are left floating. Implementing the circuit in this way leads to a limited array size as described above. As it was noted earlier, many of these limitations can be overcome by grounding the unselected lines. Such a solution would require a decoder based on something other than pass gates or pass transistors. Not entirely different from using decoders that ground the unselected lines, another approach for increasing array size is via banking or building one large memory out of several smaller ones. What this does is separate the unselected devices into multiple groups so that the device being read (of resistance Rrd ) is in parallel with fewer devices composing a larger resistance Runsel . By making use of a banking scheme in this way, the output current depends more on the selected device even for a large overall memory. Of course, the drawback in this is that banking requires decoders not only for selecting the rows and columns of a single crossbar array but also for addressing a particular memory bank within the overall memory. Thus, the design of a nanoscale memory must take into account the necessary overhead required in CMOS for implementing a sufficiently large memory. The suggestion here, however, is that any nanoscale memory should not rely entirely on banking or any other scheme for improved performance, but should utilize a combination of such approaches in order to maximize the possible array size while also minimizing the necessary overhead of the circuit. 10.3.2 Programmable Logic via the Crossbar Array When multiple inputs are addressed simultaneously, the result is an array where each output is a logical function of all inputs connected through the “on” devices. For example, consider an output column connected to two input rows via molecular switches in the high conductivity state. If either input is high, the output column connected through the “on” devices is high. This output column is only low when both inputs are low. Thus, the circuit acts as a logical OR gate. Similarly, the crossbar array can be programmed to act as logical AND gates. Cascading arrays functioning as both AND and OR planes leads to sum-of-products logic functionality where the OR gates are functions of the outputs of the AND gates. The resulting circuit is a programmable logic array or PLA [20]. While conventional microelectronics employ a multi-level logic representation that provides many options for design trade-offs, crossbars may not be inherently suited for such a representation. In particular, crossbars relying on diode-like junctions and other such devices without gain may incur significant penalties in terms of signal strength when implementing multi-level logic. As logic propagates through many levels of a PLA system, the voltage drop across the devices in each level will eventually lead to non-negligible loss of signal strength. Since gain is not a natural feature of a crossbar array of molecular switches, some additional circuitry is required for this purpose. Furthermore, external circuitry must also have the ability to provide inversion for all inputs, since inverters are also not included in the crossbar structure. Both gain and inversion could be provided from a CMOS layer, leading

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to an important consideration when designing such a system. However, as density is expected to increase by reducing any dependence on CMOS, it would be beneficial to determine ways of providing gain and/or inversion within the molecular crossbar itself. 10.3.3 Signal Restoration at the Nanoscale: The Goto Pair Considering the desire for high device densities along with the lack of gain in crossbar circuits, it is useful to examine possible ways of providing signal restoration at the nanoscale. Such circuits should improve device density since nanoscale structures are expected to be much smaller than anything implemented with CMOS for similar purposes. One possibility that has been introduced by Hewlett-Packard is a circuit composed entirely of nanoscale switches that has been dubbed the crossbar latch [21]. Without going into the particulars on how this circuit functions, it is important to note that, for such circuits, signal restoration is made possible because what is stored can be considered a regenerated version of what is read. Thus, a latch is one viable option for providing signal restoration within digital nanoelectronic circuits. Considered here is another latch, the Goto pair, which can provide signal restoration at the nanoscale. This circuit is named for E. Goto, who first proposed the circuit in 1960 [22]. Although the original Goto pair was envisioned for solid-state electronics, recent developments suggest that molecular devices can be fabricated with the NDR characteristics necessary for circuit operation [23]. As can be seen in Fig. 10.8, a Goto pair consists of two NDR devices in a totem pole configuration, with a clock acting as the power supply connected to the load NDR device and an input connected through a resistor to the node between the NDR devices. When the clock voltage is held high there are three operating points, two that are stable and one unstable. The instability of the middle operating point results from biasing both devices in the NDR region [22, 24]. Of greater importance is the fact that the two stable points of this circuit are used to store data in the form of a voltage at the node between the

Fig. 10.8. Schematic of a Goto pair latch and load line diagram. There are two NDR devices in a totem-pole configuration, with the drive device connected to ground and the load device connected to the clock/power supply

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two devices. These low and high voltages, VLO and VHI , can represent logic 0 and 1, respectively [25]. Data is latched by supplying a current, Iin , into the input node which determines the resulting state of the circuit. If this current is above some positive threshold while the clock transitions from low to high, the circuit will settle on the logic 1 stable point and will remain in that state until the clock drops low again. Likewise, a current below some negative threshold will result in latching a logic 0. Since the latch operates based on the input current, a voltage controlled current source at the input is essential to the functionality of the circuit. In general, transistors could be used as fairly good current sources, as they are in [24]. In our case, however, an input resistor is used instead to act as the current source due to the limitation to two-terminal devices. Many molecular switching devices fabricated to date can be used for this purpose since they are essentially tunable resistors. Obvious uses of the Goto pair are to restore signals and/or act as memory elements for digital logic circuits. In addition to these, the Goto pair is also useful for implementing a circuit known as a majority logic gate. Majority logic, as the name suggests, is based on gates whose outputs take on the logic value of whatever the majority of the inputs may be. For example, the output of a three input majority gate would be high only when two or more of the inputs are high. An interesting property of a three input majority gate is that one of the inputs can be used as a control line to force the circuit to act as either a two input OR gate (control held high) or a two input AND gate (control held low) as can be seen in Table 10.1. Logic functions can thus be implemented using majority gates that are forced to behave as AND gates and OR gates. Of course, in some cases, functions can be implemented with less complexity by directly implementing majority logic functions [26, 27]. Regardless of the form of logic chosen for circuits composed of majority gates, it should be pointed out that combining Goto pairs with crossbar arrays of molecular devices that are essentially tunable resistors leads to a form of PLA based on majority logic. Such programmable majority logic arrays (PMLA) add a great deal of versatility to the type of circuits that can be implemented using digital nanoelectronics. Table 10.1. Truth table for majority gate, showing its behavior as an OR function (top half of the truth table) or as an AND function (bottom half of truth table) depending on the value of one of the inputs (control input) Control 0 0 0 0

A 0 0 1 1

B 0 1 0 1

OUT 0 0 0 1

1 1 1 1

0 0 1 1

0 1 0 1

0 1 1 1

Function OR

AND

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10.3.4 Hysteresis and NDR based Devices in Programmable Logic Combining the ideas explored thus far in this section, a logic structure is considered consisting of crossbar arrays driving rows of Goto pairs, as illustrated in Fig. 10.9. Since the crossbar arrays can be programmed such that the various Goto pairs are driven by different numbers of inputs, the overall circuit has the ability to implement logic as networks of latches and majority gates. Using crossbar arrays in this way is somewhat different from other approaches in that logic is not simply implemented in the array but is a result of both the array and Goto pair functionality. Essentially, voltage inputs are converted to current inputs due to the molecular switches behaving as variable resistors. In this way, the molecular devices serve as equal weights for the majority gate since the input currents directly depend on their resistance. Due to Ohm’s law, the currents are summed at the input node of the Goto pair and the output value latched will be the majority of its inputs. This circuit acts as a majority gate, as opposed to some other form of threshold gate, if (1) the on/off current ratio is large, and (2) the on state is the same, or nearly the same, for all molecular switches. The layout of the proposed PMLA would look like that shown in Fig. 10.10. This design consists of four crossbar arrays connected via rows of Goto pairs. There are two types of molecular devices in this structure: the devices in the crossbar itself act as molecular switches (programmable resistors), while the devices connected to each row act as NDR devices in a Goto pair. In such a structure, an output from an array plus its corresponding Goto pair can be programmed to function as either a latch or a majority gate. As can be seen in Fig. 10.9, this functionality can be determined by noting which molecular switches within the array are programmed on and which are off. As the outputs of one logic level feed into the inputs of another,

Fig. 10.9. Circuits for majority gate (first row) and latch (second row) that can be obtained by properly programming molecular switches in a crossbar with the rows connected to Goto pairs (left), resulting in a form of programmable majority logic array (PMLA)

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Fig. 10.10. PMLA possible layout: the ovals between the clock lines and nanowires represent the stacked NDR devices making up the Goto pairs and at each junction between nanowires is a programmable molecular switch. The circles on the periphery represent contacts from the nano circuitry to a CMOS layer

these cascaded arrays can be used to implement multiple levels of logic. In fact, since in this particular design the output from the third array is connected back to the input of the first, what we have is a version of a whirlpool PLA [28] where the various arrays (quadrants in Fig. 10.10) can be used again and again to implement multiple levels of logic. The difference between the approach presented here and the whirlpool PLA is that in the PMLA signals can actually ping-pong around for multiple levels of logic within the same quadrant of the overall array. This is made possible by the fact that the input and output of a Goto pair is essentially the same node. One issue that must be dealt with in the design of such circuits is the possibility of data indirection. Put another way, the input of the Goto pair is actually the same node as the output. What this means is that the current from the output could actually switch the state of the circuit. Likewise, the voltage on the output could lead to a current through the input that could switch a previous Goto pair when such circuits are cascaded. To prevent this problem of indirection, three clocks are used that are out of phase, but overlapping, so that the current during the write stage of operation primarily comes from the input and not the output [22, 25]. An example of this clocking scheme can be seen in Fig. 10.15.

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10.4 MolMOS Architecture 10.4.1 The CMOS Interface & I/O Considerations As can be seen in the proposed PMLA layout (Fig. 10.10), the inputs and outputs of the array are connected to a CMOS layer through vias (the circles on the periphery of the structure). The motivation for using CMOS in this way is based on the fact that the nanowires are likely too small to interface directly with off-chip circuitry. In addition to being an interface to the outside world, CMOS also provides the PMLA with complemented signals since no intrinsic inverters are available in the nano layer. In the proposed PMLA design, these complemented signals may be provided for some but not all of the inputs to the array (for example, in Fig. 10.10 only inputs IN0 and IN5 are available in both true and complemented form, while all other signals are only in non-complemented form). Since it is likely that many functions do not require all inputs to be complemented, such an approach can be utilized to ensure logical completeness while at the same time reducing the amount of circuitry required in the CMOS layer. Figure 10.10 also shows that in each half of the array both VHI and VLO signals are provided. The signals VHI and VLO are the high and low voltages from the Goto pair that represent logic 1 and 0, respectively. These signals are provided as inputs to the array at each logic level because the three input majority gates can be controlled to behave as two input AND or OR gates, as described in Sect. 10.3.3. While it is desirable to implement as much functionality as possible using majority logic, there may be instances when AND and OR gates are still useful. For this reason, always having VHI and VLO as possible inputs to all logic levels makes for a more versatile array. 10.4.2 Augmenting the PMLA with CMOS When considering the mapping of a Kogge–Stone adder (described in [29]) to such a nano-scale array, it is important to note that, for most of the inputs, inverters are only needed at the very beginning and end of the adder. Furthermore, for this particular example, exclusive OR (XOR) logic which may be complex as an implementation at the nano-scale, is only required at the beginning and end of the adder implementation. As such components may not be as well suited for implementation within nano-scale logic as they are in CMOS, the implementation of some logic functionality CMOS becoming advantageous. It is believed that such an approach should lead to a more optimized overall design in terms of area, power and performance. A methodology for designing such a hybrid CMOS/nano system is described in [8]. Somewhat different from what was originally proposed, the approach taken here is to attempt to provide some logic functionality within CMOS in such a way that the overall system remains flexible in terms of what can be implemented. More specifically, for the Kogge–Stone example, it is considered that the XOR for the initial propagate (P = A⊕B) signals may be implemented more easily in CMOS than in the PMLA. In fact, if the propagate signals are to be implemented this way,

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it may be just as easy to compute the generate (G = AB) signals in CMOS as well. Following this train of thought, the overall system could include some look-up tables (keeping the system programmable) and shift registers for implementing some logic at the CMOS level. In order to maintain the versatility of a programmable system, a single CMOS look-up table (LUT) is used to compute the same function for each bit position of two input vectors, A and B. After each bit position is computed, the result is shifted into the register and then the next position is computed. For N bit vectors, this would require at least N clock cycles and should probably be implemented in such a way that all N clock cycles in CMOS can be completed within one cycle of the clock used for the nano-scale PMLA. This is assuming that the nano-scale logic is slower than CMOS, which seems to be a reasonable assumption for now considering the large resistances at the nano-scale. 10.4.3 Array Access for Programmability As the reader may have noticed from Fig. 10.10, not all of the nano devices in the array can be directly accessed through the peripheral I/O pins. This is important to note since, for the purpose of programming the array, all nano devices must be addressed one-by-one. Taking this into consideration, the layouts shown thus far are not complete as more interface pins must be included for the purpose of programmability. In order to allow for full programmability in the PMLA design, two options are considered and detailed below: Option 1) CMOL Approach – Based on the CMOL architecture designed by Strukov and Likharev [13], additional pins may be placed throughout the interior of the array such that all nanowires are directly accessed and use the CMOS layer for decoding. In this approach, the nano-scale crossbar array may be placed at an angle α with respect to the CMOS layer below. The motivation for this would be ease of fabrication as the minimum wire pitch in the CMOS layers would be larger than that of the nano layer(s). Option 2) NanoWire (NWFET) Decoders – The use of doped Si for the fabrication of the nanowires such that interior nano devices can be accessed through some form of nanowire FETs. This approach is similar to that taken by DeHon in [11]. Such a scheme would consist of multiplexers where the nanowire FETs are gated by microwires. This setup would allow each nanowire, and thus each molecular device, to be accessed one-by-one from CMOS. Upon considering these two approaches to providing access to all molecular devices, it may be reasonable to utilize both. For the I/O connections, that are to be used during run-time as well as for programming the array, the first option is used since during run-time it is desirable to access many lines simultaneously. Therefore, the run-time I/O, represented by the circular connections in Fig. 10.10, should be implemented using a scheme similar to the CMOL approach [13]. The interior lines of the array, that are not to be accessed during run-time, are a different matter since those connections are needed only for programming the array.

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If configuration time is not a major concern, the second approach is suitable for programming the interior devices. Thus, for this part of the design, nanowire FET multiplexers are included such that the devices between the I/O logic levels can be directly accessed serially for programming only. 10.4.4 A More Complete Picture of the Overall Architecture Figures 10.11 and 10.12 show illustrations that represent the various components, both in CMOS and at the nano-scale, that make up the overall PMLA system. It can be seen in the left half of this figure how CMOS is used to provide some logic via look-up tables and shift registers. It is also shown how some inputs to the PMLA are delivered in both their buffered and inverted forms. Not shown on the CMOS end of this figure are decoders for programming the crossbar array and connections to the nano level for the global signals VHI , VLO , and all clocks. When considering the overhead associated with such a system, these implied circuit blocks must be included as well. Figure 10.12 is another representation of what the layout of the nano-scale PMLA might look like. For the most part, Fig. 10.12 is similar in content to Figs. 10.10 and 10.14 with the exception that it also includes the nanowire FET-based decoders to be used for programming the internal molecular switches not accessible by the run-time I/O. This rendering shows one possibility for implementing the nanowire FETs where specific areas of the wires are explicitly doped to function as channels for the devices. This is a similar approach to that used in a design by DeHon where

Fig. 10.11. Illustration of the CMOS components in the overall PMLA architecture. For the purposes of driving the nano-scale PMLA, the rails for the CMOS logic are VDD = 1.6 V and VSS = 0.6 V. Not shown are the decoders necessary for programming the array and the VHI and VLO connections

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Fig. 10.12. Illustration of the nano-scale components in the overall PMLA architecture

the nanowires might be grown such that some areas of the wires are doped differently than others [11, 14]. Another possibility would be to fabricate them using some form of lithography, such as the imprint methods used by Heath and at Hewlett-Packard [30, 31]. For nanowires fabricated this way, it may be easier to leave the entire wire uniformly doped and use the microwire gates to apply negative voltages when a FET is to be turned off. In this case, the nanowire FETs can be considered depletion mode transistors. Thus, the vision for implementing the programmable majority logic array on the nano-scale includes the design of a hybrid CMOS/nano system. This is done such that CMOS can be used for programming the nano-scale crossbar array, implementing more irregular logic, and interfacing the array with off-chip circuitry. The particular designs shown here for the CMOS end of the system include the use of look-up tables and shift registers for performing some logical operations on words of data before anything is done at the nano-scale. As mentioned in Sect. 10.4.2, this technique does not slow down the overall system, and in fact may even speed it up, so long as the CMOS clock driving the shift registers can run N times faster than the clocks used for the nano-scale PMLA, where N is the word size of incoming data. This may actually be a reasonable assumption for these systems since the resistances of the nano-scale devices is on the order of 10 G. It is important to

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note that improvements in clock speed may not be the motivation for using such nano-scale devices but their use should lead to lower-power operation and increased device densities that may allow for a great deal of on-chip parallelism for some applications.

10.5 Circuit Simulation of MolMOS System A critical part of the design of any circuit like those presented here is simulation for the purpose of verification. Of course, reliable simulation is only possible if models are provided which accurately reflect the characteristics of the included devices. In this section, a model known as the Universal Device Model (UDM) is briefly described followed by some simulation results providing functional verification of the nanoscale PMLA circuitry. 10.5.1 Device Modeling for Circuit Simulation In order to simulate nanoelectronic circuit designs, models for the nanoscale devices must be developed in such a way that they include non-classical properties like negative differential resistance, coulomb blockade, and hysteresis. As nanoelectronics research is currently providing a plethora of device types, it is useful to develop modeling methodologies that allow quick and easy exploration. The UDM approach taken here is to build models empirically from either experimental or theoretical data for the novel devices in question. The I –V characteristics of such devices are modeled from a set of four possible equations representative of behavior common to nanoscale devices: linear (resistor-like) behavior, thermionic emission (diode equation), negative differential resistance (Gaussian equation), and coulomb blockade (step function). Thus, a complete UDM model can include of a broad set of these non-classical characteristics [32]. 10.5.2 Functional Verification of a Stand-Alone Nanoscale PMLA In the functional verification of the nanoscale PMLA described in Sect. 10.3.2, the UDM is used to model the molecular NDR devices of the Goto pairs. For the purposes of simulating this circuit, a model based on the room temperature molecular NDR device from [23] is used. Using such a device for the implementation of the Goto pair circuit, it was found that the crossbar array can be programmed for latches and majority gates, where the molecular devices are modeled as variable resistors with an on resistance of 90 G and an off resistance of 9 T. Such on/off resistance values are in the range of those measured from actual molecular switches, such that these simulation results approach what one might expect from a true prototype of the PMLA. Figure 10.13 shows a schematic of the PMLA where the circuit is programmed to function as a full adder, adding bits A and B to produce the sum (S) and carry out (COUT ) outputs. An illustration of what the layout of this adder might actually look like is shown in Fig. 10.14.

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Fig. 10.13. Schematic of a PMLA programmed as a full adder

Fig. 10.14. Physical layout of the full adder PMLA shown schematically in Fig. 10.13. This layout is different from the schematic representation in that I/O is more evenly distributed around the array

Simulation results of the PMLA adder functionality are shown in Fig. 10.15. The top three waveforms in this figure show the offset and overlapping clocks used to prevent data indirection in a Goto-pair-based circuit. Since the first logic level is

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Fig. 10.15. Simulation results from Cadence Spectre of the PMLA programmed to function as a full adder

controlled by Clock1 , the input data is required to be valid while Clock3 is high. In this example, the inputs are actually held for an entire clock cycle on Clock3 . Just as is the case for inputs into the PMLA, the outputs of the circuit are valid while Clock3 is high. Thus, for an input vector sampled on the rising edge of Clock1 , the output is only valid following the next rising edge of Clock3 . With this in mind, the results shown in Fig. 10.15 verify the functionality of a PMLA programmed to function as a full adder.

10.6 Conclusions and Future Directions This chapter has touched on a few issues relating to the design, modeling, and scaling of hybrid CMOS/molecular circuits. Such circuits have the potential to help maintain the historic advances in the electronics industry by increasing the actual, functional, and virtual levels of integration and by overcoming some of the manufacturing difficulties encountered by conventional top-down fabrication. Programmability is an important feature for many other molecular electronic designs in that, if for no other reason, it allows for fault tolerance. Further, it is likely that the PMLA design discussed here could be utilized in such a way as to avoid some of the problems associated with crossbar array circuits. Even so, there are still many areas within this design that require more attention. Among such issues are thermal management at the CMOS layer (as molecular devices may be aromatic), low-power operation, and continued development and improvement of design methodologies.

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These various challenges, in addition to others, are being taken on in such a way that novel nanotechnologies like molecular electronics are showing themselves as plausible candidates for future circuit integration.

Acknowledgment This work was supported by a University of Virginia FEST grant, the National Science Foundation (NIRT 0210585), ARDA/DTO, DARPA/ONR MoleApps program (N000140410706), and MARCO IFC. The authors would also like to thank J. Ellenbogen and S. Das from the MITRE Corporation; K.K. Likharev and D. Strukov from SUNY Stony Brook; and L. Harriott, J.C. Bean, A. Cabe and J. Lach from the University of Virginia for interesting discussions on this topic.

References 1. International technology roadmap for semiconductors: 2005 edition, 2005 2. Technology roadmap for nanoelectronics: 2000 edition. http://www.cordis.lu/esprit/src/ melna-rm.htm 3. K.S. Kwok, J.C. Ellenbogen, Moletronics: Future electronics. Mater. Today 5, 28–37 (2002) 4. J.M. Tour, W.L. Van Zandt, C.P. Husband, S.M. Husband, L.S. Wilson, P.D. Franzon, D.P. Nackashi, Nanocell logic gates for molecular computing. IEEE Trans. Nanotechnol. 1(2), 100–109 (2002) 5. M.R. Stan, P.D. Franzon, S.C. Goldstein, J.C. Lach, M.M. Ziegler, Molecular electronics: From devices and interconnect to circuits and architecture. Proc. IEEE 91(11), 1940–1957 (2003) 6. S.C. Goldstein, M. Budiu, Nanofabrics: Spatial computing using molecular nanoelectronics, in Proceedings 28th Annual International Symposium on Computer Architecture, June 2001, pp. 178–189 7. A. DeHon, P. Lincoln, J.E. Savage, Stochastic assembly of sublithographic nanoscale interfaces. IEEE Trans. Nanotechnol. 2(3), 165–174 (2003) 8. M.M. Ziegler, M.R. Stan, CMOS/nano co-design for crossbar-based molecular electronic systems. IEEE Trans. Nanotechnol. 2(4), 217–230 (2003) 9. M.M. Ziegler, Regularly structured design for coping with nanoscale integration complexity. Ph.D. Dissertation, University of Virginia, Charlottesville, Virginia, August 2004 10. M.M. Ziegler, M.R. Stan, A case for CMOS/nano co-design, in Proceedings International Conference on Computer Aided Design, November 2002, pp. 348–352 11. A. DeHon, M.J. Wilson, Novel devices and approaches to programmable devices: Nanowire-based sublithographic programmable logic arrays, in Proceedings International Symposium on Field Programmable Gate Arrays (FPGA), February 2004, pp. 123–132 12. P.J. Kuekes, R.S. Williams, Demultimplexer for a molecular wire crossbar network (MWCN DEMUX), US Patent, number 6256767 (Hewlett-Packard), July 2001 13. D.B. Strukov, K.K. Likharev, CMOL FPGA: A reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices. Nanotechnology 16(6), 888–900 (2005) 14. Y. Cui, C.M. Lieber, Functional nanoscale electronic devices assembled using silicon nanowire building blocks. Nano Lett. 291, 851–853 (2001)

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15. K.K. Likharev, D.B. Strukov, CMOL: Devices, circuits, and architectures, in Introducing Molecular Electronics, ed. by G. Cuniberti, K. Richter, G. Fagas. Lecture Notes in Physics, vol. 680 (Springer, Berlin, 2005), pp. 447–478, Chap. 16 16. C.P. Collier, E.W. Wong, M. Belohradsky, F.M. Raymo, J.F. Stoddart, P.J. Kuekes, R.S. Williams, J.R. Heath, Electronically configurable molecular-based logic gates. Science 285, 391–394 (1999) 17. A.R. Pease, J.O. Jeppesen, J.F. Stoddart, Y. Luo, C.P. Collier, J.R. Heath, Switching devices based on interlocked molecules. Acc. Chem. Res. 34(6), 433–444 (2001) 18. M.A. Reed, J. Chen, A.M. Rawlett, D.W. Price, J.M. Tour, Molecular random access memory cell. Appl. Phys. Lett. 78(23), 3735–3737 (2001) 19. N. Gergel, N. Majumdar, K. Keyvanfar, N. Swami, L.R. Harriott, J.C. Bean, G. Pattanaik, G. Zangari, Y. Yao, J.M. Tour, Study of room temperature molecular memory observed from a nanowell device. J. Vac. Sci. Technol. A 23(4), 880–885 (2005) 20. M.M. Ziegler, M.R. Stan, Design and analysis of crossbar circuits for molecular nanoelectronics, in Proceedings IEEE Conference on Nanotechnology, August 2002, pp. 323–327 21. P.J. Kuekes, D.R. Stewart, R.S. Williams, The crossbar latch: Logic value storage, restoration, and inversion in crossbar circuits. J. Appl. Phys. 97(3), 034301 (2005) 22. E. Goto, K. Murata, K. Nakazawa, K. Nakagawa, T. Moto-Oka, Y. Ishibashi, T. Soma, E. Wada, Esaki diode high-speed logical circuits. IRE Trans. Electron. Comput. EC-9, 25–29 (1960) 23. J. Chen, W. Wang, M.A. Reed, A.M. Rawlett, D.W. Price, J.M. Tour, Room-temperature negative differential resistance in nanoscale molecular junctions. Appl. Phys. Lett. 77(8), 1224–1226 (2000) 24. R.H. Mathews, J.P. Sage, T.C.L.G. Sollner, S.D. Calawa, C.-L. Chen, L.J. Mahoney, P.A. Maki, K.M. Molvar, A new RTD-FET logic family. Proc. IEEE 87(4), 596–605 (1999) 25. G.S. Rose, M.R. Stan, Memory arrays based on molecular RTD devices, in Proceedings IEEE Conference on Nanotechnology, August 2003, pp. 453–456 26. W. Wang, K. Walus, G.A. Jullien, Quantum-dot cellular automata adders, in Proceedings IEEE Conference on Nanotechnology, August 2003, pp. 461–464 27. G.S. Rose, M.R. Stan, RTD circuit design for memory and logic, IEEE Trans. Nanotechnol. (submitted) 28. F. Mo, R.K. Brayton, Whirlpool PLAs: A regular logic structure and their synthesis, in Proceedings International Conference on Computer Aided Design, November 2002, pp. 543–550 29. J.M. Rabaey, A. Chandrakasan, B. Nikoli´c, Digital Integrated Circuits: A Design Perspective, 2nd edn. (Prentice-Hall, Englewood Cliffs, 2003) 30. Y. Luo, C.P. Collier, J.O. Jeppesen, K.A. Nielson, E. Delonno, G. Ho, J. Perkins, H. Tseng, T. Yamamoto, J.F. Stoddart, J.R. Heath, Two-dimensional molecular electronics circuits. Chem. Phys. Chem. 3(6), 519–525 (2002) 31. Y. Chen, G. Jung, D.A.A. Ohlberg, X. Li, D.R. Stewart, J.O. Jeppesen, K.A. Nielsen, J.F. Stoddart, R.S. Williams, Nanoscale molecular-switch crossbar circuits. Nanotechnology 14, 462–468 (2000) 32. G.S. Rose, M.M. Ziegler, M.R. Stan, Large-signal two-terminal device model for nanoelectronic circuit analysis. IEEE Trans. VLSI Syst. 12(11), 1201–1208 (2004)

11 Sublithographic Architecture: Shifting the Responsibility for Perfection A. DeHon

11.1 Revising the Model In our conventional, top-down, lithographic model we define a minimum lithographically imageable feature size (e.g., half pitch) and build devices that are multiples of this imageable feature size. Within the limits of this feature size, VLSI layout can perfectly specify the size of features and their locations relative to each other in three dimensions – both in the two-dimensional plane of each lithographic layer and with adequate registration between layers. This gives the designer complete flexibility in the layout of circuit structures as long as she adheres to the minimum imageable and repeatable feature size rules. As we approach the atomic-scale, it becomes harder and harder to maintain this model. Precise location of atoms becomes relevant. Discreteness of the underlying atoms begins to show up as a significant fraction of feature size. Variations occur due to statistical doping, dopant placement, and interferometric mask patterning. Topology in the regions surrounding a pattern impact the fidelity of reproduction of the circuit or interconnect, creating the demand for optical proximity correction. Perfect repeatability may be extremely difficult or infeasible for these feature sizes. Bottom-up approaches, in contrast, promise us finer feature sizes that are controlled by physical phenomena but do not promise perfect, deterministic alignment in three dimensions. We may be able to get good repeatability of certain kinds of small feature sizes (e.g., nanowire diameters, molecular or colloid dimensions, surface film thicknesses) and correlation of tiny features within a single nanowire using axial and radial composition, but we may have little correlation from nanowire to nanowire in the plane or between nanowire planes. This leads us to ask if we can, reasonably, give up our demand for perfect device fabrication, perfect correlation, and complete design freedom in three dimensions in order to exploit feature sizes measured in small numbers of atomic lattice spacings. Our research suggests this is a viable alternative, as reviewed in this chapter, but it will require a very different

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approach to architecture, design, and testing than we took when feature sizes were measured in thousands of atoms.

11.2 Bottom-Up Feature Definition Chemists and material scientists are demonstrating numerous techniques to define atomic-scale feature sizes in a bottom-up fashion. One area where many complementary techniques are coming together is in the fabrication of nanowires. Self-limiting chemical processes [1] can be used to produce nanoparticles of controlled diameter. Nanowires with diameters down to 3 nm can be grown from nanoparticle seed catalysts [2]. The diameter of the grown nanowires is closely correlated to the diameter of the seed catalysts [3]. Bottom-up synthesis techniques also allow us to define atomic-scale features within a single nanowire. Using timed growth, features such as composition of different materials or different doping levels can be grown along the axis of the nanowire [4–6]. This effectively allows us to place device features into nanowires, such as a field-effect gateable region in the middle of an otherwise ungateable wire. Further, radial shells of different materials can be grown around nanowires with controlled thickness using timed growth [7, 8] or atomic layer deposition [9, 10]. These shells can be used to force the spacing between device and wire features or to build devices integrating heterogeneous materials with atomic-scale dimensions. Once grown, nanowires can be assembled into tight-pitch arrays using Langmuir– Blodgett (LB) flow techniques [11]. Using an insulating core shell which can be etched differentially with respect to the core of the nanowire, the wires can be tightpacked so that the core shell thickness defines the spacing between nanowire conductors. Once such a tight array is defined, it can be transferred onto an electrical substrate. The shell can then be etched away if it is not needed after serving to define the spacing between wires [12]. Multiple layers can be stacked with different (e.g., orthogonal) orientation [11, 13]. In other approaches, timed vertical growth or atomic-layer deposition on planar semiconductors can be used to define nanometer features sizes of differentially etchable materials. Cut orthogonally, the vertical cross-section can be etched, producing a comb-like structure where the teeth, as well as the spacing between the teeth, are single-digit nanometers wide (e.g., 8 nm). The result can serve as a pattern for nanoscale imprint lithography [14, 15] to produce a set of tight pitch, parallel lines; that is, the long parallel lines resulting from the differential etch can be stamped into a resist mask [15] which is then etched to produce a pattern in polymer or coated with metal to directly transfer metallic lines to a substrate [14]. Chapter 9 provides additional examples and discussion of bottom-up synthesis techniques. These techniques give us the ability to create very small feature sizes using basic physical properties of materials to define dimensions. However, they do not allow us to build arbitrary topologies, and the correlation between features is limited. We can have correlated features within a nanowire, but only in a single nanowire; we cannot control which nanowire is placed next to which other nanowire or how they

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are aligned. Imprint techniques allow us to have small features but demand regular structures and offer limited alignment between separate mask layers.

11.3 Regular Architectures Consequently, these bottom up-techniques allow us to define regular and repeating structures (e.g., rows of parallel conductors, crossed arrays of parallel conductors) with very fine dimensions (e.g., 3–5 nm half pitch) but do not allow us to define arbitrary geometries at these dimensions. Even optical lithography can produce finer resolution regular structures than it can arbitrary topologies [16], and the variation in feature clarity and definition based on regional proximity (e.g., optical proximity correction effects) is already driving designs to increased regularity to reduce variation effects. At the same time, the need for high defect and variation tolerance drives us to regular structures which include many copies of interchangeable components. These interchangeable structures allow us to fabricate a modest number of spare resources (cf. spare tire) to substitute for broken resources or resources with undesirable parameters (e.g., resistances that are too large or small, devices that are too slow or leak too much, devices which cannot be turned “on” or “off”). Taken together these effects drive us away from the arbitrary topology model and toward more stylized structures matched to our fabrication capabilities.

11.4 Statistical Effects Above the Device Level In the past, statistical effects were the primary domain of the process engineer. The Law of Large Numbers [17] guaranteed that the large number of statistically placed dopants in a device had a tight distribution. Consequently, there was little intra-die device variation, and the process engineer could easily provide the circuit engineers and architects with a moderately uniform set of perfect devices. As our devices shrink to the point where they are made from modest numbers of atoms and dopants, we no longer have Law of Large Numbers statistical guarantees on dopant distributions in a device and it becomes impossible to guarantee consistent device behavior. Nonetheless, the shrinking feature sizes mean that we have very large numbers of things above the device level – large numbers of wires and large numbers of devices. Accepting that higher levels in our system stack will now be exposed to the atomicscale statistical effects, we can exploit the Law of Large Numbers at these higher levels to obtain reliable device characteristics and yield. 11.4.1 Defect and Variation Tolerance A circuit element (e.g., conductors, transistors, switches) gets its characteristics, including variation, from the low-level devices which compose it. As a result, high variance devices or device features will result in circuit elements that also exhibit

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high variance or high defect rates. Most elements will be in a usable range, but the higher variance means there may be a low percentage of elements that are unacceptable. If we were forced to use every fabricated circuit element, the component would never yield or would have bad characteristics that would render it unusable. However, only a low percentage of the devices are bad; consequently, if we can provide spares for every circuit element, we can avoid all the unacceptable components. The Law of Large Numbers on circuit elements suggests that the number of spares we need to guarantee high yield of the intended circuit is comparable to the expected number of bad elements (Sect. 11.6.1, [18]). This suggests that our architectures need to evolve so all elements are interchangeable and, preferably, organized into large sets of interchangeable resource pools so that the Law of Large Numbers works to our advantage. This is concretely illustrated in terms of nanowire sparing in our nano programmable logic array (PLA) architecture described below (Sect. 11.6.1). 11.4.2 Differentiation Law of Large Numbers statistical effects can also be used to mitigate the fact that we are forced to build regular structures. That is, they can provide reliable differentiation within the otherwise regular structures. One challenge posed by regular structures like tight-pitch nanowire crossbars is this differentiation. How can we selectively address a single nanowire if all the wires are the same and are fabricated at a pitch too small for us to build arbitrary topologies lithographically? If we could control the production of arbitrary patterns at the nanometer scale, we could build a decoder to provide the pitch matching between this scale and the scale at which we could define arbitrary topologies. The trick is to build the decoder statistically. That is, we differentiate the nanowires statistically and carefully engineer the statistics to guarantee high probability that there will be a unique address associated with each nanowire. Kuekes and Williams propose a scheme that uses random particle deposition to define the address for each nanowire [19]. DeHon, Lincoln, and Savage propose using a doping profile along each nanowire to define the nanowire address [20]. In both cases, if you pick the address space sparsely enough, Law of Large Numbers statistics can guarantee unique addressability of the nanowires. To illustrate this phenomenon intuitively, consider selecting ten nanowires out of a large pool with 106 different nanowire types. The probability that the second nanowire selected has the same address as the first is 10−6 ; assuming the first i nanowires have unique addresses, the probability that the (i + 1)-st nanowire has the same address as any of the first i is only 10i 6 . This means, the probability that the tenth nanowire is the same as any of the previous nanowires is 1096 . Together, the probability that all nanowires are unique is: 9 i=1

1−

i 106

<

999991 106

9 = 0.9999.

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Fig. 11.1. Restoration array

In general, we can guarantee over 99% probability of uniqueness of N nanowires using only 100N 2 addresses [20]. If we allow a few duplications, the address space can be much smaller [18]. In another scenario, DeHon used the statistical selection of coded nanowires to assemble nanoscale wires for restoration [21]. As shown in Fig. 11.1(a), if we could perfectly place coded nanowires in an array, we could use the array of nanowires, each with an embedded field-effect region, as an array of inverters to restore a set of input wires. However, the bottom-up techniques that can assemble these tight-pitch feature sizes cannot order or place individual nanowires and cannot provide correlation between nanowires. As shown in Fig. 11.1(b), we can use statistical alignment and placement of the restoration nanowires. Not every input will be restored, but the Law of Large Numbers guarantees that we can restore a reliably predictable fraction of the inputs. For further details see [18, 21].

11.5 NanoPLA Architecture These principles are concretely illustrated in the nanoPLA architecture developed at Caltech [21]. The logic structure is based on a crossed set of parallel semiconducting nanowires (Fig. 11.2) grown and assembled as described above. Programmable switches [22–26] sandwiched between the crossed nanowires allow the construction of programmable, wired OR planes. Crosspoints are programmed by placing a

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Fig. 11.2. Simple nanoPLA block

We apply an address on the lithographic scale address lines (A0. . . A3). The applied address (1100) allows conduction through only a single nanowire. By monitoring the voltage at the common lithographic node at the far end of the nanowire (Vcommon), we can determine if the address is present and the wire is functional (e.g., non-broken). By monitoring the timing of the signal on Vcommon, we may further be able to determine the resistance of the nanowire Fig. 11.3. Addressing a single nanowire

voltage differential across a pair of crossed nanowires. The stochastic decoder described above (Sect. 11.4.2) allows individual nanowires to be addressed from the lithographic scale for testing and programming; that is, we use the decoder to place a test voltage on a single nanowire (Fig. 11.3) and measure its conduction and to place a differential voltage across a particular pair of nanowires (Fig. 11.4) to program the crosspoint at their junction. The output of the programmable, wired OR plane is restored via a restoration plane using field-effect gating of the crossed nanowire set as described above (Sect. 11.4.2, Fig. 11.1). The restoration planes can provide inversion such that the pair of planes provides a programmable NOR. The two back-to-back NOR planes can be viewed as a traditional AND–OR PLA with suitable application of DeMorgan’s

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Fig. 11.4. Programming a nanowire–nanowire crosspoint. We apply addresses to the lithographic-scale addresses of both the top and bottom planes to select individual nanowires in each plane. We use the stochastic restoration columns to turn the corner between the top plane and the restoration inputs to the bottom plane. Note since column 3 is an inverting column, we arrange for the single, selected signal on the top plane to be a low value. Since the stochastic assembly resulted in two restoration wires for this input, we end up activating both nanowire inputs. As a result, we place our designated voltage across the two marked crosspoints in order to turn “on” the crosspoint junctions between the restored inputs and the selected nanowire in the bottom plane

theorem. A second set of restoration wires provides buffered, non-inverted inputs to the next wired OR plane; in this manner, each plane gets the true and complement version of each logical signal just as we normally provide in a VLSI PLA. Logic evaluation in the PLA can be gated from the microscale wires, allowing us to use a familiar two-phase clocking discipline. As such, the PLA cycle shown in Fig. 11.2 can directly implement a finite-state machine. The programmable crosspoints can be used to personalize the array, avoid defective wires and crosspoints (Sect. 11.6), and implement a deterministic function despite fabrication defects and stochastic assembly. To build larger components using these structures, we arrange to build an array of these nanoPLA blocks where each block drives outputs that cross the input (wired OR ) regions of many other blocks (Fig. 11.5) [21, 27]. This allows us to build modestsized PLAs (e.g., 100 P-terms), which are efficient for logic mapping, and to keep the nanowire runs short (e.g., 10 μm) in order to increase yield and avoid the high resistance of long nanowires. The nanoPLA blocks provide signal buffering for long wire runs and switching as well as logic. With an appropriate overlap topology, these nanoPLAs can support Manhattan (orthogonal X–Y) routing similar to conventional, island-style FPGA architectures [28]. This organization makes it relatively straightforward to adapt conventional PLA and FPGA mapping tools (e.g., UCLA’s PLA mapping tools, PLAMAP [29], and Toronto’s Placement and Routing tools for Island-Style FPGA Architectures, VPR [30, 31]) to map logic to these interconnected nanoPLAs [21]. Mapping the Toronto

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Fig. 11.5. NanoPLA block tiling with edge I/O to lithographic scale

20 benchmark suite [32] to 10 nm pitch nanowires, we typically see density two orders of magnitude greater than defect-free 22 nm lithographic FPGAs [21] even after considering lithographic interfacing overhead, defects, and statistical assembly effects. Reviewing the features of the nanoPLA architecture: 1. All nanoscale features are provided in the nanowires and defined without lithography using bottom-up synthesis techniques. 2. The architecture is regular, relying only on parallel arrays of crossed nanowires. 3. No correlation is required between the assembled nanowires (see [20] for details on alignment tolerance). 4. Differentiation is provided by statistical assembly. 5. Deterministic, defect-avoiding functionality is defined by post-fabrication configuration. 6. Coarser-grained lithographic wires and devices are used to provide reliable access to the nanoscale features for testing and programming.

11.6 Defect Tolerance Two key features of the nanoPLA design are: 1. All key resources exist in large pools of interchangeable elements (e.g., wired OR “product” terms in the PLA, individual wires in the route channels). 2. Element assignment to each logical or routing function is performed after fabrication; we identify the defects and configure the design to avoid them. 11.6.1 Wire Sparing Logically, all the P-Terms (wired OR’s or product terms when the two-planes are viewed as an AND – OR PLA) in a nanoPLA are equivalent. Consequently, we can

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Fig. 11.6. Probability of yielding less than 100 good 0.90

OR -terms

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as a function of N for Por =

assign any logical P-Term to any physical nanowire. Broken or non-addressable nanowires can be ignored. We design the array with extra, or spare, wires in each nanowire array. As long as each array yields a sufficient number of non-defective nanowires, we can still use the PLA array. We simply avoid enabling any of the programmable crosspoint connections to the defective nanowires. We can perform an N-choose-M calculation to determine the number of wires we must physically populate (N ) to achieve a given number of functional wires (M) in the array. The probability that we will yield exactly i restored P-Terms is: N i N −i . (11.1) (Por ) (1 − Por ) Pyield (N, i) = i That is, there are Ni ways to select i functional P-Terms from N total wires, and the yield probability of each case is: (Por )i (1 − Por )N −i . We yield an ensemble with M items whenever M or more items yield, so our system yield is actually the cumulative distribution function: N i N −i (Por ) (1 − Por ) . (11.2) PMofN (N, M) = i M≤i≤N

Given the desired probability for yielding at least M functional OR terms, PMofN , (11.2) gives us a way of finding the number of physical wires, N , we must populate to achieve this. Figure 11.6 plots (1 − PMofN ) versus N for the case where M = 100 at Por = 0.90 on a log scale. For example, with N = 124 total nanowires, PMofN (124, 100) > 99.9%. We would expect to yield, on average, 0.9 × 124 ≈ 112 nanowires (i.e., the expected value of a sum of identical, independently distributed random variables is the product of the number of variables and the expected value of each variable). By provisioning these additional nanowires (about 12% more than

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required on average), we guarantee high yield. This example and Fig. 11.6 illustrate how quickly a small percentage of spares beyond the expected number provides strong guarantees of high and consistent yield. 11.6.2 Crosspoint Defects Individual crosspoints may not be programmable. The nanowire crossings can contain only tens of molecules or atomic bonds. If the molecular monolayer film used to assemble the switches [23, 33] is not perfectly filled or the bonds to the nanowires are statistically formed, there will be a non-trivial probability that a particular crosspoint may have an insufficient number of bonds to provide good conductivity when programmed into the low-resistance “on” state. For example, Chen [34] reports that 85% of the molecular junctions in a molecular-switch crossbar are programmable. We expect these rates to improve with experience and tuning, but the small number statistical effects will mean we always have some probability that an individual junction cannot be programmed. If we demanded that every junction on a nanowire be programmable in order to consider the nanowire usable, almost all of our nanowires would be unusable. For illustration, consider a junction defect rate of 5% (Ppgm = 0.95) and nanowires with 100 junctions. The probability that a nanowire has 100 non-defective junctions is (0.95)100 ≈ 0.006; that is, we would be lucky to find one such perfect wire in each set of 100. However, when we program any particular P-Term into a nanowire, we will never want to turn on all the junctions, so it is never really necessary to have a nanowire that has no defective junctions. For example, if a logic array (AND or OR plane) of a nanoPLA has defective junctions as marked in Fig. 11.7, the OR term f = A + B + E can be assigned to nanowire W 3, despite the fact that it has a defective (non-programmable) junction at (W 3, D) – i.e., the OR term f is compatible with the defect pattern of nanowire W 3. The probability that a nanowire can support f is (0.95)3 > 0.85 which is much higher than the 0.6% probability that the nanowire is defect free. In fact, the OR-term f = A + B + E can be assigned to any of the wires shown in Fig. 11.7 except for wires W 2 (which has a defective junction on input E) and W 6 (which has a defective junction on input A). In general, within a set of M nanowires, the probability that an OR term with C inputs has at least one nanowire that can support it is: M (11.3) Pmatch (C, M, Ppgm ) = 1 − 1 − (Ppgm )C . For the particular case of f (C = 3) and a collection of six nanowires with Ppgm = 0.95, we have: 6 Pmatch (3, 6, 0.95) = 1 − 1 − (0.95)3 > 0.99999. In practice, we will want to map a collection of P-Terms to a nanoPLA, so we must negotiate among all the logical P-Terms as to which P-Term gets which

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Fig. 11.7. OR array with defective junctions

nanowire. For a particular PLA, each P-Term will generally be supported by one or more nanowires. Knowing the compatibility between P-Terms and nanowires, we can formulate the assignment task as a bipartite matching problem to attempt to satisfy the requirements of all P-Terms. In [35, 36], we show that a standard benchmark set [32] can be mapped to nanoPLAs with 5% defective crosspoints (Ppgm ) and no additional spare nanowires. That is, even though almost every nanowire contains defective junctions, all nanowires can still be used in the design. 11.6.3 Variations The most direct way to tolerate excessive variations in device parameters is to treat them as defects. Consequently, junctions with too high an “on” resistance or nanowires with contact or “on” resistance that is too high can be avoided as described above. In more sophisticated schemes, we might measure the resistance of junctions and nanowires and use that information during assignment; for example, we can make sure slow junctions are allocated to non-critical paths that can tolerate slower operation and we can compensate with fast and slow resources along a path to make sure no path is composed entirely of slow devices. For example, Katsuki et al. use measured gate speeds to optimize device placement on configurable devices to improve yielded circuit performance [37]. 11.6.4 Roundup These solutions push the responsibility for perfection from fabrication to the architecture level, exposing the statistical effects to higher levels of our design hierarchy where we have large numbers of elements. It is still necessary to control manufacturing to produce consistently low rates of defects (e.g., disconnected wires and

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non-programmable junctions), but we do not have to demand perfection from manufacturing. Further, we can make engineering trade-offs between the cost involved in achieving a given device defect rate and the overhead required to accommodate it.

11.7 Testing and Configuration Both statistical addressing (Sect. 11.4.2) and statistical defects (Sect. 11.6) demand that we test and determine the characteristics of each component. Sparse addressing guarantees that we must, at least, discover the addresses before configuration. The matching technique for crosspoint defect tolerance (Sect. 11.6.2) demands that we perform component-specific matching. These techniques would be prohibitively expensive if we were to use a conventional testing approach where all component characterization is performed on an expensive, high-speed tester. Rather, to support the necessary paradigm shift to component-specific testing and configurations, it will be necessary to change our test and configuration schemes as well. Instead of performing all testing from off-chip, we embed a small test and configuration manager on each component. This on-chip tester can be a small processor and need only occupy a small percentage of the die area, even if built out of reliable, coarse-grain lithography. The high-speed tester is now only responsible for validating the correct operation of this test and configuration manager. Since this unit is small and of limited functionality, it will require lower test time than conventional components. The embedded test manager is responsible for diagnosing the defectprone nanoscale logic. The chip only needs a supply of power in order to run tests on the remainder of the component; it does not need to be coupled to an expensive tester for the nanoscale logic testing. For component personalization, we can view the embedded tester and configuration manager as a more sophisticated bitstream loader. That is, on configurable devices like FPGAs, we personalize them by loading a configuration bitstream that indicates how each element should be programmed. In the simplest case, each bit in the bitstream might be the state of one configuration cell in the component. However, bitstreams can be encoded or compressed for compactness and security and can include checksums for safety. As a result, there is already a small amount of circuitry dedicated to interpreting the configuration bits arriving at the component and translating them appropriately to set actual configuration bits on the device. To support the matching algorithm described in Sect. 11.6.2, the bitstream simply describes the set of P-Terms required in each nanoPLA array but not which nanowire implements each P-Term. The test and configuration manager is then responsible for running the matching algorithm as the abstract configuration is uploaded for each nanoPLA array. In [35], we show that a linear-time greedy algorithm is sufficient to perform this P-term matching; the algorithm works independently on each nanoPLA array, does not need a complete defect map of the array it is mapping, and need store no state between the mapping of each individual nanoPLA array. As a result, this

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component-specific mapping can be encapsulated entirely within the component and only has the effect of moderately increasing bitstream load time. During the operational lifetime of the part, elements may break (e.g., fatigue, electromigration) or slow down (e.g., NBTI [38], hot carrier injection). With the embedded tester as an integral part of the component, it can diagnose, and potentially recover from these failures that increasingly occur during operation.

11.8 New Abstraction Hierarchy As developed above, circuit design near the atomic scale demands that we deal with the non-trivial probability that an individual device or wire will be unusable due to these small number effects. Consequently, we must change our abstraction hierarchy, making higher levels of architecture aware of the statistical effects at the atomic scale. This is not an entirely new phenomenon as we have long taken this approach for high-density data storage (e.g., flash memory, magnetic disks). However, we must now consider applying a similar revision of duties to our computational resources as well as our data storage resources. 11.8.1 Lessons from Data Storage We have long accepted that memories and storage devices need not be fabricated perfectly [39]. Rather, we design our storage architectures to tolerate both manufacturing defects and operational faults. This has allowed us to aggressively increase the density of memories and magnetic media. Techniques include: 1. 2. 3. 4.

Spare rows and columns to tolerate defects in memory banks [39] Spare memory banks to tolerate defective memories Bad sector maps on disk drives to tolerate errors in magnetic media, and Error-correcting codes (ECC) to tolerate transient errors in memory [40, 41]

Further, when we engineer a memory system, we optimize across these levels. That is, we must balance the yield of individual memory cells and the number of spare rows and columns required to accommodate them, jointly selecting the combination of cell yield and sparing that minimizes net memory bit area. Similarly, we balance the data retention and error rate of an individual memory bit against the cost of the associated ECC to the same end. 11.8.2 Abstraction Hierarchy for Computation In a similar way, we must revise our abstraction hierarchy for logic as we approach atomic-scale feature sizes. As summarized in Table 11.1, instead of assuming arbitrary topologies and perfect device fabrication, these atomic-scale effects are reflected higher in the stack. Design must accommodate the regularity required from bottom-up techniques in order to obtain nanoscale features. Further, as with memories, circuits and architectures must be designed to accommodate the inevitable

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Atomic scale

Design • • •

uniform feature sizes defined • by reliable half pitch deterministic arbitrary topology • •

hybrid fabrication with smallscale features defined by bottom-up synthesis statistical for small-scale features regular topology for small-scale features

Fabrication

Designer expects

• •

top-down • “perfect” fabrication of de- • sign

bottom-up and top-down statistical assembly

•

100% yield of acceptable de- • vices

statistical device yield

•

reliable, fixed function de- • fined by fabrication

configurable circuitry defined by fabrication

• •

high-speed, off-chip tester • discard components with any deviations from perfect model •

on-chip, embedded test and configuration manager post fabrication defect mapping

• •

ignores defects assumes perfect operation

•

allows post fabrication configuration of non-defective resources to provide perfect functionality employs continuous checking and repair

Circuit style

Testing

Architecture

•

defects, variation, and ultimately the faults that will occur when devices are built from small numbers of atoms and molecules and store charge in small numbers of electrons. Optimization is, again, a cross-level engineering effort, selecting the right balance of individual device yield and architectural sparing of resources to provide the greatest net density and performance.

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11.9 Conclusions In order to build devices with feature sizes measured in tens of atoms, we must shift some of the responsibility for delivering perfect components from the process engineer to the circuit designer and architect. At these scales, small number statistics work against us, making it infeasible to demand high uniformity between devices and unreasonable to demand the construction of arbitrary circuit topologies. Rather, we must expose the demands for design regularity and statistical variation tolerance to higher levels of the system stack where we have large numbers of elements and where we can use those large numbers of elements to achieve statistically consistent results. Consequently, architectures become more regular and are designed for the statistical yield and operation of these atomic-scale devices. Further, testing and diagnostic become part of the lifetime support structure for the component. The responsibility for delivering perfect components shifts from the primary domain of the process engineer to a shared responsibility among the process engineer, circuit designer, and architect.

References 1. Y. Tan, X. Dai, Y. Li, D. Zhu, J. Mater. Chem. 13, 1069 (2003) 2. Y. Wu, Y. Cui, L. Huynh, C.J. Barrelet, D.C. Bell, C.M. Lieber, Nanoletters 4(3), 433 (2004) 3. Y. Cui, L.J. Lauhon, M.S. Gudiksen, J. Wang, C.M. Lieber, Appl. Phys. Lett. 78(15), 2214 (2001) 4. M.S. Gudiksen, L.J. Lauhon, J. Wang, D.C. Smith, C.M. Lieber, Nature 415, 617 (2002) 5. Y. Wu, R. Fan, P. Yang, Nanoletters 2(2), 83 (2002) 6. M.T. Björk, B.J. Ohlsson, T. Sass, A.I. Persson, C. Thelander, M.H. Magnusson, K. Depper, L.R. Wallenberg, L. Samuelson, Nanoletters 2(2), 87 (2002) 7. L.J. Lauhon, M.S. Gudiksen, D. Wang, C.M. Lieber, Nature 420, 57 (2002) 8. M. Law, J. Goldberger, P. Yang, Annu. Rev. Mater. Sci. 34, 83 (2004) 9. M. Ritala, Appl. Surf. Sci. 112, 223 (1997) 10. M. Ritala, K. Kukli, A. Rahtu, P.I. Räisänen, M. Leskelä, T. Sajavaara, J. Keinonen, Science 288, 319 (2000) 11. D. Whang, S. Jin, Y. Wu, C.M. Lieber, Nanoletters 3(9), 1255 (2003) 12. D. Whang, S. Jin, C.M. Lieber, Nanoletters 3(7), 951 (2003) 13. Y. Huang, X. Duan, Q. Wei, C.M. Lieber, Science 291, 630 (2001) 14. N.A. Melosh, A. Boukai, F. Diana, B. Gerardot, A. Badolato, P.M. Petroff, J.R. Heath, Science 300, 112 (2003) 15. M.D. Austin, H. Ge, W. Wu, M. Li, Z. Yu, D. Wasserman, S.A. Lyon, S.Y. Chou, Appl. Phys. Lett. 84(26), 5299 (2004) 16. S.R.J. Brueck, International Trends in Applied Optics (SPIE, Bellingham, 2002), Chap. 5: There are No Fundamental Limits to Optical Lithography, pp. 85–109 17. J. Bernoulli, Ars Conjectandi (Impensis Thurnisiorum, fratrum, Basel, 1713) 18. A. DeHon, in Nano, Quantum and Molecular Computing: Implications to High Level Design and Validation, ed. by S.K. Shukla, R.I. Bahar (Kluwer Academic, Boston, 2004), pp. 213–241, Chap. 7

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19. S. Williams, P. Kuekes, Demultiplexer for a molecular wire crossbar network. United States Patent Number: 6,256,767, 2001 20. A. DeHon, P. Lincoln, J. Savage, IEEE Trans. Nanotechnol. 2(3), 165 (2003) 21. A. DeHon, ACM J. Emerg. Technol. Comput. Syst. 1(2), 109 (2005). http://doi.acm.org/ 10.1145/1084748.1084750 22. J. Chen, M. Reed, A. Rawlett, J. Tour, Science 286, 1550 (1999) 23. C. Collier, G. Mattersteig, E. Wong, Y. Luo, K. Beverly, J. Sampaio, F. Raymo, J. Stoddart, J. Heath, Science 289, 1172 (2000) 24. J.M. Tour, L. Cheng, D.P. Nackashi, Y. Yao, A.K. Flatt, S.K.S. Angelo, T.E. Mallouk, P.D. Franzon, J. Am. Chem. Soc. 125(43), 9 (1327) (2003) 25. D.R. Stewart, D.A.A. Ohlberg, P.A. Beck, Y. Chen, R.S. Williams, J.O. Jeppesen, K.A. Nielsen, J.F. Stoddart, Nanoletters 4(1), 133 (2004) 26. Z. Fan, X. Mo, C. Lou, Y. Yao, D. Wang, G. Chen, J.G. Lu, IEEE Trans. Nanotechnol. 4(2), 238 (2005) 27. A. DeHon, in Proceedings of the International Symposium on Field-Programmable Gate Arrays, 2005, pp. 127–137 28. V. Betz, J. Rose, A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs (Kluwer Academic, Norwell, 1999) 29. D. Chen, J. Cong, M. Ercegovac, Z. Huang, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(10), 1424 (2003) 30. V. Betz, VPR and T-VPack: Versatile Packing, Placement and Routing for FPGAs. http://www.eecg.toronto.edu/~vaughn/vpr/vpr.html, 1999. Version 4.30 31. V. Betz, J. Rose, in Proceedings of the International Conference on Field-Programmable Logic and Applications, ed. by W. Luk, P.Y.K. Cheung, M. Glesner. LNCS, vol. 1304 (Springer, New York, 1997), pp. 213–222 32. V. Betz, J. Rose, FPGA Place-and-Route Challenge. http://www.eecg.toronto.edu/ ~vaughn/challenge/challenge.html, 1999 33. C.L. Brown, U. Jonas, J.A. Preece, H. Ringsdorf, M. Seitz, J.F. Stoddart, Langmuir 16(4), 1924 (2000) 34. Y. Chen, G.Y. Jung, D.A.A. Ohlberg, X. Li, D.R. Stewart, J.O. Jeppesen, K.A. Nielsen, J.F. Stoddart, R.S. Williams, Nanotechnology 14, 462 (2003) 35. H. Naeimi, A. DeHon, in Proceedings of the International Conference on FieldProgrammable Technology (IEEE, New York, 2004), pp. 49–56 36. A. DeHon, H. Naeimi, IEEE Des. Test Comput. 22(4), 306 (2005) 37. K. Katsuki, M. Kotani, K. Kobayashi, H. Onodera, in Proceedings of the IEEE Custom Integrated Circuits Conference, 2005, pp. 601–604 38. D.K. Schroder, J.A. Babcock, J. Appl. Phys. 94(1), 1 (2003) 39. S.E. Schuster, IEEE J. Solid State Circuits 13(5), 698 (1978) 40. R.W. Hamming, Bell Syst. Tech. J. 29(2), 147 (1950) 41. G.C. Clark Jr., J.B. Cain, Error-Correction Coding for Digital Communications (Plenum, New York, 1981)

12 Quantum Computing D.P. DiVincenzo

12.1 What Is Quantum Computing? Given its placement at the end of this book, the reader will surmise that this chapter on quantum computing represents the farthest destination out from planar silicon CMOS along the road to the nano era. This would be a mistaken impression. Quantum computing is not a topic in nanotechnology, although it may eventually benefit from some avenues in nano research. It is not about a new use of quantum effects in transistors, and it is decidedly not of any use in supplementing or enhancing the performance of CMOS logic. At present, it is a technology that is essentially nonexistent. Rather, quantum computing is a new technique of mathematical logic consistent with the principles of quantum physics and analogous to (and an extension of) boolean logic. As a new mathematical system it indicates new routes to the efficient solution of computational problems. There is a technology implied, a quantum computer, but it is very different in basic function from a digital computer. The creation of this technology, as I will describe it in this chapter, is still in its infancy. When it is built, it may well resemble a magnetic resonance imager with fine-grained feedback loops much more than it will resemble anything we call a computer today; or it may resemble neither. This chapter will proceed as follows: I will trace the history of the idea of the quantum computer and how it emerged from other studies of the fundamental implications of physics for computation. I will define the basic mathematical concept of quantum computing and discuss the gates that define it as a system of mathematical logic (as the NAND gate defines boolean logic). I will outline the discoveries of Shor and others, which indicate that, for certain mathematical problems, this system of logic can greatly surpass boolean logic in computational power. Then I will discuss what it means to efficiently realize this mathematical logic system, quantum computation, in a physical device: the quantum computer. I will follow the line of the International Quantum Computer Roadmap, which enunciates

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a set of general principles of device physics that must be achieved if quantum computers are to become a reality. Finally, I will examine in more detail three of the most promising potential technologies for achieving quantum computation: Josephson junction circuits, singleelectron quantum dots, and ion traps. We will, in fact, come full circle back to nanotechnology, in that at least some of these possibilities will very likely use many of the advances of nanotechnology if they are to become reality.

12.2 History It has been a continuing source of puzzlement among current practitioners of the science of quantum computation that the subject wasn’t thought of a half-century earlier than it actually was. On the stage at the advent of large scale machine computing were such figures as Alan Turing and John von Neumann, two men who were very aware of the connections between physics and computation, and who were also very well aware of the role of quantum mechanics as the fundamental description of dynamical processes in the physical world. Turing [1], of course, invented the notion that computing could take place in any physical setting, and his gedanken machine provided a specification of what such a physical apparatus must, minimally, be able to do in order to compute. But Turing’s machine already represented a step in the wrong direction as far as quantum computing was concerned, as his construction abstracts what a machine operating according to the laws of classical physics does. His experience was with electromechanical relay circuits, and with the large-scale computers of the day (large departments of arithmetically talented young ladies). Turing was aware that he was not on rigorous ground in considering his machine universal, but it certainly embodied everything that computing was in his day, and did so for some time to come. von Neumann’s failure to envision quantum computing may have stemmed from a famous mistake that he promulgated concerning the physical nature of computing: he believed that, fundamentally, doing a computation generates heat. He even gave a number for the minimal heat generation of a computer: kB T ln 2 per logical gate execution. His basis for believing this number was another discussion in physics during his time, also erroneous, of the Maxwell-demon paradox. It is easy to see how von Neumann might have reasoned that, since computation is irreversible, it cannot be quantum. For the parts of quantum dynamics that least resemble the classical have to do with systems that are isolated from their environment; but if heat is being generated at some temperature T and expelled, the computer must be in contact with an environment. Quantum systems in close contact with their environment tend to evolve in ways that are closely approximated by the laws of classical mechanics. This irreversibility result, while false, bore fruit in later years upon reexamination, and led younger workers to the possibility of quantum computation. The first step in this process came when Landauer [2] attempted to provide thermodynamic arguments to back up the irreversibility assertion. He noted that the output state space of the NAND gate is smaller than the input state space. So it would seem that some

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degrees of freedom get lost and must end up as heat as the steps of boolean logic are carried out. But Landauer noted that it was not really the gate operation that caused the irreversibility, but rather the erasure of some registers that take place after the gate operation is complete. Then Bennett [3, 4], following on this clarification by Landauer, looked into how often erasure is really necessary. He showed that it is never necessary, and that a fully reversible implementation of boolean logic is possible. (He was able to write out his result in the language of Turing machines, in fact.) This landmark result cleared the way conceptually for the possibility of computation in a closed quantum system, but it took some time for such a proposal to be developed. In 1980 Benioff [5] took a first step, writing out a quantum Hamiltonian for a Schrödinger equation that would implement a Turing machine calculation as specified by Bennett. A little later Feynman [6] did the same thing for a logic-circuit model of computation. But these efforts only showed that ordinary, boolean logic could be consistently implemented in quantum systems. The possibility of a different mathematical logic system altogether in the quantum world is just dimly glimpsed in another, earlier paper of Feynman [7] in 1981, where he muses on the fact that many-body quantum systems are often very hard to simulate on a digital computer, so that perhaps they should themselves constitute the simulator. But the breakthrough conceptually in quantum computing, in my opinion, comes in 1985 with the paper of David Deutsch [8]. Here, and in a crucial follow up paper in 1989 [9], he recognizes that quantum physics permits a more general set of transformations between input and output than are encompassed by boolean logic. A new type of information processing, quantum computation, is permitted by the laws of quantum physics.

12.3 Fundamentals Rather than following further the historical developments of these ideas [10], I will now give the modern understanding of quantum computing that flowed directly from Deutsch’s seminal papers. We say now that the difference between boolean and quantum logic originates at a very basic level: the nature of information carried even by a single bit is different in the quantum world, as compared with the classical world of boolean logic. To indicate this fundamental difference, a different name is given to the two-state system in the quantum setting: it is a qubit, as distinct from a bit. A bit has just two possible states, 0 and 1. The qubit has a continuum of possible states, which is any superposition of 0 and 1, even though upon observation, the qubit state will be found to be one of the ordinary bit states 0 or 1. The state of the (unobserved) qubit is expressed by a qubit wave function: |ψ = a|0 + b|1.

(12.1)

The coefficients a and b are arbitrary complex numbers; their modulus squared corresponds to the probability that, if observed, the qubit will be found in the corre-

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sponding state. But the phase of these coefficients is also an indispensable feature of this quantum state, and has genuine consequences if this qubit is allowed to interact with other qubits. So, the information carried by a qubit is a two-dimensional vector in a space of complex numbers. In quantum mechanics, these state vectors evolve by rotation. That is, the allowed evolutions of a qubit are given by the application of a 2 × 2 rotation matrix to the vector described by the wave function. (This is just a statement of what the Schrödinger equation does to a state.) The logic gates of Deutsch’s quantum logic, then, are defined by rotation matrices. In Boolean logic, there are only two possible logic operations on a single bit: identity (i.e., do nothing), and NOT. In quantum logic these are represented by two simple matrices: 1 0 0 1 Identity: NOT: . (12.2) 0 1 1 0 But quantum logic permits a continuous set of other matrices. Deutsch noted the amusing fact that this logic contains elements that, after two applications, yield a NOT. Such a “square root of NOT” can be taken to be √ cos π/4 sin π/4 NOT: . (12.3) − sin π/4 cos π/4 √ Obviously there’s also a 4 NOT, or any other root of NOT; but the fourth-root plays a significant role in the theory, so we note it here: √ cos π/8 sin π/8 4 NOT: Q = . (12.4) − sin π/8 cos π/8 This Q is important (it is usually just called “the π/8 gate” in the literature) because it appears in the answer to the question, “what is a universal gate for quantum logic?” This question means the same thing as it does in boolean logic: Is there a single gate that, when used repeatedly in a logic circuit, can perform any transformation allowed in the logic? For boolean logic, the answer is the NAND gate. For quantum logic, there is a universal gate; in fact there is a continuum of universal gates. But it turns out that the most efficient gate set for quantum logic involves two or more gates acting in a circuit; that is, there are universal gate sets that appear to be of most interest in applications [10]. A universal gate set must obviously include more than just one-qubit gates. All two-qubit boolean logic gates that are reversible (and therefore compatible with quantum logic) and nontrivial are equivalent to the controlled NOT (or cNOT), in which one of the output bits is negated if the other is a 1, and is unchanged otherwise. The matrix representing this in the quantum theory is ⎛ ⎞ 1 0 0 0 ⎜0 1 0 0⎟ ⎟ (12.5) cNOT: ⎜ ⎝0 0 0 1⎠. 0 0 1 0

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This matrix is four-dimensional because it acts on a vector of the possible two-qubit states, which is a superposition of four basis vectors, viz., |ψ = a|00 + b|01 + c|10 + d|11. It can be shown that cNOT and Q are a universal gate set. This can be demonstrated in two ways: 1. (Abstractly) – Circuits of these two gates on n qubits can implement, to any desired degree of approximation, any rotation matrix on the space of n qubits (that is, a space of dimension 2n × 2n ). 2. (Concretely) – Quantum algorithms require two things: (1) implementation of reversible boolean logic; (2) creation of uniform superposition states (and the inverse). The universal gate of reversible boolean logic requires three bits; Toffoli showed [11] that it takes three bits to embed NAND into a reversible boolean gate (the Toffoli gate). There is a simple, finite circuit of Qs and cNOTs that exactly implements Toffoli. Application of Q2 on every qubit transforms the all-zero state into a uniform superposition of all bit strings.

12.4 Quantum Algorithms A quantum algorithm is not just a universal gate set, although this set is a crucial ingredient in a quantum algorithm’s execution. Here are the salient features of a quantum algorithm: 1. A regular (classical) computer program takes a problem statement (e.g., find the prime factors of integer N) and translates it into a list of quantum logic gates. 2. A set of qubits is initialized to the all-zero state. Note, then, that there is no notion that the problem data is loaded into the quantum register – all relevant data is stored on the “classical” side. 3. The list of quantum gates is applied to the qubits, rotating them away from the all-zero state. 4. Some (or all) of the qubits are measured. (Usually all are not necessary, as some are only in use as workspace.) Despite the continuum of states possible for a qubit (see (12.1)), the result of a measurement on a qubit has just two outcomes – 0 or 1. This constitutes the output of the algorithm, and it is, finally, just “classical” – an ordinary bit string. Within a few years of Deutsch’s papers, the possibilities for this quantum style of logic were well understood. But, could quantum logic actually do anything more efficiently than boolean logic that would be of any use to anyone? The answer, of course, turned out to be yes, although it took some years of effort to show that this was so. Shor’s landmark discovery of 1994 showed that there is, indeed, an efficient quantum algorithm for prime factorization. “Efficient” means that the number of quantum gates required to complete the calculation scales like (log N )3 (recall that N is the integer to be factored). This is by contrast to the best known classical algorithm, which needs a number of boolean logic gates scaling like exp((log N )1/3 ).

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Thus, there is an apparent exponential separation in computational efficiency gained by using quantum techniques. I will not give this algorithm here; it is clearly reviewed in many places [10]. In fact, the Shor algorithm (and most of the useful known quantum algorithms) has a very simple structure: it begins with a set of non-classical one-bit gates that produce a uniform quantum superposition of all possible bit strings, i.e, the wave function is written ⎛ log N bits ⎞ 1 ⎝ |000 . . . 000 + |000 . . . 001 + · · · + |111 . . . 111⎠ . (12.6) Ψ =√ N Then, most of the algorithm consists of ordinary arithmetic operations (realized by classical reversible boolean logic gates) applied to this superposition of bit states. The algorithm ends with another set of non-classical operations (called the “quantum Fourier transform”). Shor’s algorithm alone guaranteed that the attempt to build an operating quantum computer would become an activity of high interest; the rest of this chapter will be concerned with this effort. Before leaving the subject of quantum algorithms, I will briefly indicate some of the progress that has been made on quantum algorithms since Shor’s discovery. Discoveries of new quantum algorithms have taken place steadily in the 11 years since the discovery of the factoring algorithm. On the face of it, none of the new algorithms seem to be as compelling as Shor’s algorithm. Certainly, none of them deal with a problem mathematically as elementary as prime factorization. But within some (apparently esoteric) mathematical realms, there are problems for which quantum computing provides improvements fully as dramatic as in factoring. These involve the solution of classes of Diophantine equations (and thus within the larger class of number theory), problems in computational group theory and ring theory, and in the theory of quadratic residues. In all of these the fundamental complexity of computational problems is reduced: problems that are evidently not solvable in polynomial time become so in the quantum realm. (“Polynomial time” means a running time scaling like a power of the number of bits needed to specify the problem, e.g., (log N)α .) A few other broad areas in which important quantum algorithms exist also deserve mention. There is a broad class of optimization problems (e.g., finding the x for which some function f (x) has a maximum) for which quantum algorithms of the type introduced by Grover are effective. Grover algorithms do not result in an exponential decrease in computational complexity, but are capable of taking √ a computational procedure that requires S steps classically and reducing it to S steps of a quantum algorithm. Another area in which quantum computation provides large advantages is in the simulation of complex quantum physics problems. At some level this is an obvious application – one quantum system simulates another, as Feynman anticipated. However, identifying the simulation problems for which quantum computing methods offer the greatest advantages over classical techniques has been a delicate and

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non-trivial task that is still in the process of being sorted out after many years of work. It is also interesting to note that there are other categories of computations, for example, ones concerned with iterated function evaluation (f (f (f (. . . x) . . .))) for certain categories of function f ) for which quantum logic provides no advantage, that is, no speedup compared with the use of boolean logic. So, the efficacy of quantum techniques will probably remain an intricate story, in which there will be no succinct way of stating how computational complexity is reduced using quantum techniques. Finally, while not strictly in the realm of algorithms, there are known qualitative and quantitative improvements that are possible in cryptographic protocols via the use of quantum information processing. Cryptography may be most broadly defined as the subject of information transmission and processing where issues of privacy, security, trust, and reliability are of greater importance than those of computational efficiency. Quantum mechanics permits certain things, such as secret key exchange between two parties (Alice and Bob), to be absolutely secure in ways that are fundamentally impossible in a classical world. This is a kind of “quantum cryptography.” Actually, it is only one of several new applications of quantum techniques in cryptography, as defined more broadly, which have recently come to light (for example, secret sharing and secure remote function evaluation). There is no comprehensive review of quantum algorithms, as I’ve sketched it here, in the scholarly literature; however, a good account may be found in the annexes of the “Quantum Information Science and Technology Roadmap” and of the “Quantum Cryptography Roadmap,” about which I will explain more in a moment.

12.5 Realizing a Quantum Computer There was some small amount of discussion [12] of the question of how to make a physical apparatus that would realize the quantum Turing machine before Shor’s 1994 discovery. But these discussions became so much more concrete and extensive after his discovery, that it is fair to say that the quest to build a quantum computer began in that year. Within a very few years, there was a vast array of clever ideas and experiments initiated on many fronts. It is impressive, perhaps, just to list the different physical settings in which a plan was devised for creating a qubit in the laboratory: 1. 2. 3. 4. 5. 6. 7. 8. 9.

Nuclear spins in solute organic molecules Nuclear spins on semiconductor surfaces (C, Si) Nuclear spins of individual donors or acceptors in bulk semiconductors Atomic energy levels of individual ions in an ion trap Atomic energy levels of neutral atoms in optical traps or optical lattices Photons in optical cavities Photons in optical networks Electron spins of vacancy complexes in diamond Electron spins of electrons suspended above liquid helium

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10. 11. 12. 13. 14.

Electron spins of electrons trapped in semiconductor quantum dots Electron orbital states in semiconductor quantum dots Excitons in semiconductor quantum dots Rare-earth impurity levels in oxide crystals Collective excitations of superconducting condensates in Josephson junction circuits 15. Cooper-pair charge of superconducting islands 16. Quasiparticle states in the fractional quantum Hall effect It is amazing that, with only a few exceptions, all the items in this list had been thought through, and experiments were planned or initiated, by about 1997 – only three years after the Shor discovery. This creative explosion indicated that the concepts of quantum computing resonated with many of the active streams of work in modern experimental physics. On the other hand, from a technology standpoint, it is not a positive thing that such a long list of possibilities could come into serious play. In fact, it is a more or less rigorous law of technological development that if a large number of diverse approaches are conceivable for achieving a technology, then that technology is in a very immature state. We are very well aware in the computer industry that the emergence and dominance of planar CMOS technology along with its associated scaling methodology, alone among all the many techniques that have been employed though time to build devices for digital computers, was the sign of the maturing and perfecting of digital computer technology. The down-selection process that will bring us from 16 quantum computing technologies to one actual, optimal one has only barely begun. This is largely because some of the most basic quantum physics properties of these systems are still being sorted out. A selection before more of the basic physics is understood would surely be premature. However, the groundwork has already been laid for this future selection process. An analytical exercise called the Quantum Information Science and Technology Roadmap [13] was undertaken in 2002 by a group of leading scientists in the fields represented in the list above. It has been actively augmented and updated throughout its three years of existence. It is of course only superficially related to the International Technology Roadmap for Semiconductors (ITRS). The quantum roadmap has a much wider range of subjects to cover. On the other hand, it is much less able to say specific things about the future, since these depend on unknowable basic scientific advances. The approach that the analysts have taken is to develop a set of criteria and desiderata that any physical system must satisfy or achieve if it is to make progress towards the ultimate goal of creating a quantum computer. The starting criteria were those that I introduced in surveys that I had published in earlier years [14]. These are now referred to as the promise criteria, because if they can all be satisfied they only indicate that the system is worthy of further work – they are still far from the achievement of a quantum computer. But achieving these promise criteria indicates that there are no fundamental physics obstacles to achieving quantum computing in the system, and

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that engineering prototyping of computing machines using this physical system can usefully begin. Here is a short statement of what is needed in the physical setting under consideration: 1. Well-characterized qubits that can be incorporated into a scalable system 2. The ability to initialize the quantum state of the qubits to a simple starting fiducial state, such as the all-0 state 3. A low decoherence rate, much smaller (e.g., 10−4 ) than the operation time of quantum gates (one tick of the clock) 4. The ability to accurately execute any of a universal set of quantum gates 5. A capability to reliably measure the state (0 or 1) of chosen qubits in the system Most of these criteria should be clear from the earlier discussion and will become clearer in the examples discussed below. But criterion 3 deserves some immediate comment. More colloquially, it says that the noise seen by the qubits of the system must be sufficiently low. Noise can refer to fluctuations of physical parameters of the system (for example, voltage variations arising from Johnson noise of a resistor), or to unintended couplings of qubits to other quantum degrees of freedom in their environment. The word “decoherence” in quantum physics refers to the effect that this noise has on qubits, which in some respect has no analog for bits. Qubits can be driven by noise to flip their state (0→1) just as bits might, but they may also be driven to exhibit random variations in the phase of superposition states, an imperfection that has no analog in the boolean world. One might worry that, since a phase is an analog variable, error correction for a quantum computer would be as hard (indeed, as impossible) as it is in an analog computer. But a landmark theoretical discovery in quantum computing in 1996 showed that, because of the digital nature of quantum measurements, reliable quantum computation is possible with noisy qubits, so long as the level of noise stays below some threshold value. This is very good news, since it says that quantum operations and quantum memories do not have to be made ever more accurate and ever more noisefree as the size of the computations increases, as they would for an analog computer. This fault tolerance is achieved by means that are exactly analogous to those used in digital computing – redundancy and error-correcting codes. Unfortunately, because the nature of quantum noise is different from that of classical noise, the threshold noise levels are apparently much worse than they are in digital computation. The threshold number that has emerged from many detailed studies is the one stated in the list above, a probability of error of about one part in 104 per clock cycle. It is this small required error probability that drove much of the thinking about the 16 physical settings listed above; the quantum system must be very noise free, and must be capable of very precise, reproducible control. It gives us at least a dim glimmering of understanding of what the quantum computer will look like when it is built. It will have to consist of a classical analog controller which will itself be of considerable complexity – think of a million-channel precision voltage source or lock-in amplifier. It will be wrapped around a quantum-physics system that will be as precise as an atomic-physics experiment, or a bureau-of-standards clock, but also

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with millions of constituent, interconnected parts. It will only very slightly resemble a present day digital computer, or any other present-day piece of technology.

12.6 Physical Implementations I will now choose three settings among the 16 listed above, and indicate the progress that is being made towards the satisfaction of the five criteria. We have seen a lot of progress in the last few years in a couple of these areas, and we may even claim to be very near to satisfying all five promise criteria. I emphasize again, however, that satisfying these five criteria does not mean that we have a working technology. On the historical timeline of digital computing, it puts us at about 1947, when the transistor was first operated. When the five criteria are satisfied, we have our quantum version of the transistor – but we have no idea how this quantum transistor will be used in the engineering of a large quantum system. 12.6.1 Josephson Junction Circuits The reader will not be surprised that an author from the IBM Watson Research Center begins this survey of physical implementations of quantum computers with superconducting microcircuits, since a program to make a computer in Josephson technology was a large-scale development project at this laboratory up until the early 1980s [15]. IBM Research does indeed now have a project to make the quantum computer using Josephson circuits [16]. But, as the preceding sections of this chapter have made clear, the relation between these two programs is very slight. It is, perhaps, a testimony to the great flexibility of Josephson technology that it is capable, in quite different ways, of satisfying the requirements for a good digital switch, and for those of a good qubit device. At the time that the IBM Josephson computer program was underway more than 20 years ago, it was already understood in other labs [17] that the Josephson junction could exhibit some quantum properties analogous to an atom. In an early experiment, the analog of photon-assisted ionization of an atom in an electric field was demonstrated in a current-biased Josephson junction [18–20]. Experiments at that time showed the glimmerings of qubit properties: discrete energy levels were seen, and the quantum-tunneling needed in the ionization experiments showed that the system possessed some degree of quantum coherence. The coherence time was some fraction of a nanosecond, not very different from the inverse of the transition frequencies in this “atom”; so the degree of coherence was not very great. This state of affairs was not dramatically different after the lapse of some 15 years, when the Shor algorithm was discovered. Despite the tremendous advances in superconductivity in those years, and the discovery of many new superconducting materials, the best potential for quantum computing devices remained with the oldest of materials and processes – which were, in fact, aluminum shadow deposition with alumina tunneling barriers. Yet very little had changed in the observed coherence times of these devices. However, it was clear to several workers in the mid-1990s

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Fig. 12.1. Aluminum shadow-evaporation qubit circuit from the group of J.E. Mooij [21]

that the potential for considerable improvement was there, if careful engineering was employed to rigorously exclude external noise and to increase the sensitivity of existing detector designs to make them sensitive to individual charges or flux quanta. There has been an outpouring of results from many labs around the world [21]. Using a wide variety of Al–Al2 O3 circuits (see Fig. 12.1), dramatically longer coherence times have been achieved. As Fig. 12.1 shows, coherence times, as measured by pulse techniques borrowed directly from atomic spectroscopy, are well into the range of hundreds of nsecs. The present record, achieved in a related circuit, is 4 μsec [22]. Even longer coherence times will be required. But what is it that is coherent in these systems? What is the qubit, and how is it measured? To explain “what,” I must discuss something of the device physics of the Josephson junction. Josephson’s laws, for an electrical engineer, mean that the I –V characteristic of a Josephson junction is that of a lossless, wide-bandwidth, nonlinear voltage-controlled inductor [23]. A linear inductor has the characteristic t V (t ) dt . (12.7) I (t) = L−1 Josephson’s equations imply that, for the Josephson junction, t V (t ) dt . I (t) = Ic sin 2π/Φ0

(12.8)

Here Φ0 = h/2e is the flux quantum. The defining property of inductance is that it involves an instantaneous functional relationship between the flux (the time integral of the voltage) and the current. This property is possessed by these two equations. By putting a Josephson junction into a circuit with a capacitance, one can create a nonlinear LC oscillator. A harmonic oscillator (formed by a linear LC circuit) has equally spaced quantum energy levels; but a non-linear LC oscillator (ideally lossless) has unequally spaced quantum energy levels. In a circuit with a few Josephson junctions, the non-linearity of the oscillators can be used to craft a non-linear oscillator with

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two closely spaced quantum energy levels, well separated from the rest, that can act as the two states of the qubit. The many different Josephson qubit circuits found in the literature attest to the fact that the optimization problem is a complex one involving (1) sculpting the nonlinear oscillator spectrum appropriately; (2) having at the same time the capability to sense the state of the oscillator, which in many cases involves a purpose-built magnetometer circuit fused together with the qubit circuit; and (3) the need to prevent, as much as possible, room-temperature noise in the controlling circuitry from disturbing the qubit. In the figure, the bilateral symmetry of the circuit is one of several strategies that result in a high degree of environmental isolation. Several iterations of this complex optimization have taken place in several labs in the last few years, and the results have been impressive. Relative to pre-Shor numbers, they have resulted in an increase of coherence times of about four orders of magnitude. Armed with these improvements, workers are cautiously moving to the next step of implementing and testing two-qubit circuits, and figuring out how larger circuits could be planned in a sensible manner. 12.6.2 Semiconductor Quantum Dots One might naturally expect that quantum computing devices will emerge from the technology that proved most successful in implementing digital computing. Certainly, 50 years of semiconductor research has produced impeccable materials, innumerable processes for growing microscopic structures, and a huge body of detailed knowledge about the quantum properties of complex semiconductor devices. Quantum mechanics is essential for understanding how transistors work. But quantum mechanics is not essential to what they do; as Alan Turing certainly recognized, transistors do exactly what very classical, electromechanical relay networks could do. So, it should not be taken as a foregone conclusion that a semiconductor device will be the premier qubit. This being said, 50 years of research is certainly there to be used, and semiconducting devices definitely deserve consideration. The problem is, to some degree, that of too much information – there is a wealth of possible approaches to making a qubit in semiconductors, involving optical properties of individual impurities or quantum dots, the quantum Hall effect, nuclear spins of bulk donors or surface adatoms, and many others. A few have emerged as viable alternatives, and I will sketch progress along one line that we initiated with a paper about eight years ago [24]. As you will see, it is off the main line of IC and semiconductor device development: it is in a non-standard materials system (although not an unknown one), in a structure that would be considered better suited for opto-electronic applications than for transistor applications (making, in fact, a poor quality transistor by the usual criteria), and operating at extremely low temperatures (1 K or less). But, it does make a qubit! The scheme begins with a quantum dot as it might be realized by gating an inversion layer in a III–V heterostructure. If, by top-gating, the inversion layer is depleted everywhere except in a little circular region in the gap between the electrodes (see

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Fig. 12.2. Schematic of single-electron quantum dot array for spin qubits

Fig. 12.2), then the resulting little isolated puddle of electrons might function in some ways like an atom. This vague thought has been around for at least 20 years, but has gradually been put into practice in increasingly sophisticated ways. All the initial important experiments involved I –V measurements of such a dot when contacted antipodally. The most important feature that was investigated early on in this work was the so-called Coulomb blockade. This refers to the observation that there is usually a gap in the I –V characteristic at small voltage – the presence of electrons on the dot blocks passage of other electrons. But as the confining gate potentials are varied, there are single points on the gate-potential axis, which repeat periodically, at which the gap vanishes and the conductance of the dot becomes high. This phenomenon, which is the basis for using the dot as the base region of a (not-very-good) transistor – the single electron transistor, indicates that the electron number on the dot is quantized, that is, stable at one particular value over long periods of time. The periodic vanishing of the blockade occurs at voltages (i.e., electrochemical potentials) at which the stable configuration of the dot switches from having N electrons to N + 1 electrons (to N + 2 to N + 3 . . . ). In the big picture, this is about what was known eight years ago, when we considered whether this circuit element could host a qubit in a quantum computer. While the possibility of stably holding a set of electrons was well established, the absolute electron number N could not be determined, but could be inferred to be in the tens or hundreds in many quantum dots. Thus, our proposal involved a considerable extrapolation: We considered what could be done if the electron number of the dot could be stably held at one. This was considered an unappealing regime experimentally, as the dot was observed to become too small to contact. But this is not a concern for the qubit application, because our concept was entirely contactless, as I will discuss. The single electron can embody a qubit in a very natural way: the spin of the electron has exactly two possible quantum mechanical states, corresponding to angular momentum of either +h¯ /2 or −h¯ /2 in the direction of an external magnetic field. At the time of our proposal, the coherence time of such a qubit was unknown. Measurements of coherence of single-electron propagation had been made in such semiconductors at that time; the numbers were never better than about 1 nsec. But on theoretical grounds, we expected that the spin coherence time could be much longer than this, because electron spin is much more weakly coupled to the environment

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Fig. 12.3. Measurement scheme of Delft University group for detecting spin of single electron in quantum dot [26]

than electron motion. Our expectation has finally been beautifully confirmed in a recent experiment (see below). In this system we realized that the easiest way to manipulate a qubit would be to couple it to a neighboring one. If the potential barrier between two dots is lowered, one turns on a strong “exchange” interaction between two spins, making the anti-aligned state of the spins energetically favored over the aligned state, just as in chemical bonds. As a logic gate, exchange can implement a perfectly good boolean logic operation, a swap of two bits. Swap is not a useful gate by itself for boolean logic, but square root of swap, a perfectly legal quantum logic gate, is quite useful. We showed [25] that fractional powers of swap constitute an alternative universal set of quantum logic gates. In our 1997 proposal, we also had to invent a scheme for measuring these spin qubits. Individual spins had never been detected in a solid. We pointed out that by making tunneling in and out of the dot spin-dependent, one could map the two different spin states of the dot into two different charge states of the dot, which are much easier to sense (using a single-electron transistor, in fact). There have been several remarkable recent experiments that have brought this proposal very much closer to reality. The first constitutes a breakthrough in the ability to measure single spin states reliably. Using a capability – developed in several labs in recent years – of measuring the electron charge of a quantum dot, in a noninvasive way, using the resistance of a nearby point contact, a group at Delft University devised a single dot in which spin-to-charge conversion was possible [27] (Fig. 12.3) and was used to measure the spin state with much better than 50% reliability. This readout technique enabled another great advance in a recent experiment done by a group at Harvard [28]: With a double quantum dot device, each holding a single electron (Fig. 12.4), fractional swap has been demonstrated. This experiment was also able to measure the spin coherence time. It was found to be at least 1 μsec, with a suggestion that longer times will be readily possible in an improved version of the experiment. On the basis of this work, a speculative design for a large scale GaAs quantum dot quantum computer has now been published [29].

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Fig. 12.4. Metalization atop a two-dimensional electron gas in a III–VI heterostructure; it forms a double dot for qubit studies at Harvard University

12.6.3 Ion Traps I now briefly survey a third possible approach to quantum computing, which bears essentially no resemblance to any present-day computer technology, although it slightly resembles the vacuum tube technology that made the ENIAC and like machines possible in the 1940s. It is very much a 21st century vacuum tube, in which a single atomic ion, or a small array of ions, is held motionless by electric forces in the center of a vacuum region. Such a suspended ion can be manipulated, with exquisite precision, using pulsed laser beams and pulsed microwaves. Shortly after Shor’s discovery, there was [30] a rather realistic theoretical proposal for how to use arrays of ions as a quantum computer. Ten years of experimental work have shown that this possibility has real promise. Atomic physics offers a vast array of possibilities for quantum states that might be employed as a qubit. After long searching, workers in this community have focused on particular pairs of low-lying energy levels in a small number of ions (of Be, Ca, and Sr) as a qubit. From the perspective of solid-state implementations, the coherence times available in these systems (about 10 seconds) are awesome. Two-bit gate operations, effected by laser pulses, have already been achieved with precision approaching 99% [31]. It would appear that only an engineering effort is required for realizing an iontrap quantum computer, but the problems to be dealt with are nevertheless daunting. The system is not intrinsically miniaturizable, and the likely physical size of a largescale ion-trap quantum computer approaches that of an aircraft hangar. Most workers foresee the need for physical motion of ions as an essential step in data transmission, which would make the operation speed very slow (perhaps 1 kHz clock speed). The laser optical control system would be of unprecedented scale and complexity (probably also of aircraft-hangar size). So, despite the impressive showing of this system

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according to the promise criteria discussed above, the path to a real quantum computer in this area is perhaps unappealing. 12.6.4 Outlook I hope that this chapter has made several points clear: Quantum computing is not a new way to stay on the Moore’s law curve a little longer. It is a fundamentally different way of using physical systems to do computation. For certain problems it represents no advantage over present techniques of machine computing; for other problems it represents such a huge advantage that it can be said with confidence that if those problems are ever solved on a computing machine, that machine must use quantum logic. Quantum computing is not a branch of nanotechnology, although nanotechnology might be employed as a tool to make quantum computers. But a quantum computer may actually be built with fancy vacuum tubes and have no use whatsoever for nanotechnology. Many possibilities are in play for the physical implementation of quantum computers. An infrastructure already exists for keeping track of the progress of these different possibilities – the roadmap. But as a technology, quantum computing is completely immature, and likely to remain so for many years to come; consequently, no “winner” can or should be chosen presently. The ideas of quantum computing have invigorated several fields of basic research. As I have discussed, they have been the driving force behind remarkable new discoveries in Josephson junction device physics, in semiconductor quantum dot device physics, and in ion-trap spectroscopy and control. It may well have the same effect in a variety of other distinct fields, carbon tube transistors being among them. It may be hoped that in ten years the details of this chapter will be thoroughly obsolete, and completely new and unanticipated effects will have been seen and controlled in such a way that it makes the path to a quantum computer clear. We will see.

References 1. A. Hodges, Alan Turing: the Enigma (Walker and Company, New York, 2000) 2. R. Landauer, Irreversibility and heat generation in the computing process. IBM J. Res. Develop. 5, 183 (1961) 3. C.H. Bennett, Logical reversibility of computation. IBM J. Res. Develop. 17, 525 (1973) 4. C.H. Bennett, Notes on the history of reversible computation. IBM J. Res. Develop. 32, 16 (1988) 5. P. Benioff, The computer as a physical system: A microscopic quantum mechanical Hamiltonian model of computers as represented by Turing machines. J. Stat. Phys. 22, 563 (1980) 6. R.P. Feynman, Quantum mechanical computers. Found. Phys. 16, 507 (1986) 7. R.P. Feynman, Simulating physics with computers. Int. J. Theor. Phys. 21, 467 (1982)

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8. D. Deutsch, Quantum theory, the Church–Turing principle and the universal quantum computer. Proc. R. Soc. Lond. A 400, 97 (1985) 9. D. Deutsch, Quantum computational networks. Proc. R. Soc. Lond. A 425, 73 (1989) 10. M.A. Nielsen, I.L. Chuang, Quantum Computation and Quantum Information (Cambridge University Press, Cambridge, 2000) 11. E. Fredkin, T. Toffoli, Conservative logic. Int. J. Theor. Phys. 21, 219 (1982) 12. S. Lloyd, A potentially realizable quantum computer. Science 261, 1569 (1993) 13. Quantum Information Science and Technology Roadmap, http://qist.lanl.gov/ 14. D.P. DiVincenzo, The physical implementation of quantum computation. Fortschr. Physik 48, 771 (2000) 15. Special issue, Josephson Computer Technology, IBM J. Res. Devel. 24(2) (1980) 16. R.H. Koch, J.R. Rozen, G.A. Keefe, F.M. Milliken, C.C. Tsuei, J.R. Kirtley, D.P. DiVincenzo, Low-bandwidth control scheme for an oscillator stabilized Josephson qubit. Phys. Rev. B 72, 092512 (2005) 17. R.H. Koch, D.J. Van Harlingen, J. Clarke, Observation of zero-point fluctuations in a resistively shunted Josephson tunnel junction. Phys. Rev. Lett. 47, 1216 (1981) 18. J.M. Martinis, M.H. Devoret, J. Clarke, Phys. Rev. Lett. 55, 1543 (1985) 19. M.H. Devoret, J.M. Martinis, J. Clarke, Phys. Rev. Lett. 55, 1908 (1985) 20. J.M. Martinis, M.H. Devoret, J. Clarke, Phys. Rev. B 35, 4682 (1987) 21. J.E. Mooij, Superconducting quantum bits. Phys. World 17(12), 7 (2004), available as http://physicsweb.org/articles/world/17/12/7/1 22. P. Bertet, I. Chiorescu, G. Burkard, K. Semba, C.J.P.M. Harmans, D.P. DiVincenzo, J.E. Mooij, Relaxation and dephasing in a flux-qubit. Phys. Rev. Lett. 95, 257002 (2005) 23. M.H. Devoret, A. Wallraff, J.M. Martinis, Superconducting qubits: A short review. Preprint, see http://arxiv.org/abs/cond-mat/0411174 24. D. Loss, D.P. DiVincenzo, Quantum computation with quantum dots. Phys. Rev. A 57, 120 (1998) 25. D.P. DiVincenzo, D.A. Bacon, J. Kempe, G. Burkard, K.B. Whaley, Universal quantum computation with the exchange interaction. Nature 408, 339 (2000) 26. http://www.nature.com/nature/journal/v430/n6998/pdf/nature02693.pdf, Fig. 1 27. J.M. Elzerman et al., Single-shot read-out of an individual electron spin in a quantum dot. Nature 430, 431–435 (2004) 28. J.R. Petta et al., Coherent manipulation of coupled electron spins in semiconductor quantum dots. Science 309, 2180 (2005) 29. J. Taylor et al., Nat. Phys. 1, 177 (2005) 30. J.I. Cirac, P. Zoller, Phys. Rev. Lett. 74, 4091 (1995) 31. D. Leibfried, R. Blatt, C. Monroe, D. Wineland, Quantum dynamics of single trapped ions. Rev. Mod. Phys. 75, 281 (2003)

Part IV

Afterwords

13 Nano-Whatever: Do We Really Know Where We Are Heading? H. Kroemer

13.1 Introduction: “Nano-Talk = Giga-Hype?” The title of my talk seems to indicate a certain skepticism, and one might wonder whether in old age I have turned into a pessimist who no longer believes in a bright future. Nothing could be farther from the truth. I share the optimism of many of those who are actually actively involved in developing the field, be it in physics, technology, or applications (like many at this conference). My skepticism pertains to the unbelievable hype that has arisen, during the last decade, about the “nano-whatever” field, a hype that exceeds anything I have encountered during my 50 years in solidstate physics and technology. The prefix nano suddenly gets attached to everything (this conference is no exception), and we are deluged with predictions about fantastic future applications, often promised for the immediate future. That wouldn’t be so bad if these predictions came predominantly from individuals who are actually knowledgeable about the topic, individuals in the technical community who are actually actively involved in developing the field, be it in physics, technology, or applications (like many at this conference). Much of the hype is being generated by outsiders who are not actually involved in these three areas and are basically clueless about how the process from science and technology actually works, but simply wish to profit from the development. I fear a severe backlash when it becomes clear that many of those predictions are unrealistic.

13.2 From Physics and Technology to New Applications 13.2.1 Kroemer’s Lemma of New Technology Any detailed look at the history of how applications have arisen from new science and technology provides staggering evidence for what I have called, on other occaOriginally published at Phys. Stat. Sol. (a) 202(6), 957–964 (2005). Courtesy of Wiley-VCH, Weinheim.

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sions [1, 2] my Lemma of New Technology: The principal applications of any sufficiently new and innovative technology always have been – and will continue to be – applications created by that technology. In other words: The principal applications have not been of the kind where one improves on something that could already be done on an acceptable level; they have been applications that previously could not have been met or were no even recognize at all. As a rule, such applications have indeed arisen, although usually not immediately. The problem with truly new applications is that they are extraordinarily hard to predict, and were historically rarely predicted. Ultimately, progress in applications is not deterministic, but opportunistic, exploiting for new applications whatever new science and technology happen to be coming along. I will give below three examples from the pre-nano past for my thesis, but let me draw one conclusion right away: We must take a long-term look when judging the applications potential of any new technology. The latter must not be judged simply by how it might fit into already existing applications, where the new discovery may have little chance to be used in the face of competition with already entrenched technology. Dismissing it on the grounds that it has no known applications will retard progress towards the ultimately important applications rather than advancing it! 13.2.2 Three Examples The Transistor When the transistor was invented – or should I say discovered?1 – it was widely viewed as a replacement for electron tubes or for electromechanical switches. These developments did indeed happen. But the dominant significance of the transistor is that it created the modern computer. This development could hardly have been predicted, nor was it predicted at the time: The original transistor was the bipolar transistor, but the computer revolution is based on CMOS transistors whose low dissipation made large-scale ICs possible. Ironically, the discovery of bipolar transistor action (via minority-carrier injection) grew out of a failed attempt to build a field-effect transistor (FET) in germanium. The interface-state density at the interface between the Ge and the gate dielectric was far too high to permit a modulation of the carrier density in the FET channel. There was no reason to expect the situation at a Si/SiO2 interface to turn out any better, but this is what actually happened, leading to the development of MOS transistors and ultimately (after long doubts) to CMOS. Semiconductor Laser When, in 1963, I proposed the idea of the double-heterostructure laser (DHL), I was refused resources to develop the necessary technology, on the grounds that this device could not possibly compete with existing lasers and hence would never find any 1 The citation for the 1956 Physics Nobel Prize reads “for the discovery of the transistor

effect.”

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applications. This was of course a failure to recognize the central role of the creation of new applications, expressed in my Lemma. Instead, the DHL created its own applications, from the CD player to fiber communications, plus many others. And without fiber communications, there could never have been an Internet. Fiber communications actually required two new technologies, the DH laser and a technology for low-loss glass fibers. Such synergisms involving two or more new technologies are a frequent feature of new applications. But they increase the overall unpredictability of the path from new technology to new applications. Once the DHL technology was established, non-lasing light-emitting diodes started to invade the entire illumination field, and are in the process of taking over all applications that require colored light in any case (traffic lights are a good example), as well as the low-wattage white-light field. Such “backdoor invasions” into pre-existing applications are also a common feature of a new technology – after it has created its own new applications. Nuclear Magnetic Resonance (NMR) When Bloch and Purcell received the 1952 Nobel Prize in Physics for the development of NMR, this new phenomenon was a purely scientific discovery, not anticipated to have important applications. Yet in the end it created one of the central analytical tools for organic chemistry. But this was only the beginning. Out of this chemical tool grew medical magnetic resonance imaging, one of the most powerful diagnostic tools of modern medicine, which was honored by the 2003 Nobel Prize in Medicine. This development again required synergism with another technology: the development of superconductor wires capable of retaining their superconductivity in high magnetic fields, based on ideas of Abrikosov, who was honored by the 2003 Nobel Prize in Physics. 13.2.3 Lessons From the Lemma of New Technology flow a number of lessons [2]. Although we cannot realistically predict which new devices and applications may emerge, we can create an environment encouraging progress by not always asking immediately what any new science might be good for. In particular, we must educate our funding agencies about this historical fact. This may not be easy, but it is necessary. Cutting off the funds if no answer full of fanciful promises is forthcoming is not the road to progress, a fact not altered by disguising this shortsightedness with the fancy name of “strategic research.” We must make it acceptable to the quest for applications to defer that answer; and at the very least a search for applications should be considered a part of the research itself, rather than a result to be promised in advance. Nobody has expressed this last point better than David Mermin in his recent put-down [3], “I am awaiting the day when people remember the fact that discovery does not work by deciding what you want and then discovering it.” What is not acceptable – and what we must refrain from doing – is to justify the research by promising credibilitystretching mythical improvements in existing applications. Most such claims are not

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likely to be realistic and are easily refuted; they only trigger criticism of just how unrealistic the promises are, thereby discrediting the whole work.

13.3 Roots of Nano-Technology Given the hype surrounding nanotechnology (NT), few people realize that some of us have been practicing NT for over 30 years – we just didn’t call it NT. By 1974 we saw the first papers on actual experimental devices demonstrating quantum effects, grown by the new molecular-beam epitaxy (MBE) technology. Involving quantization effects, this work was NT per definitionem. In the 30 years since then, these techniques have progressed much further; perhaps the most spectacular results being in quantum cascade lasers (see the paper by Capasso at this conference). A second root of NT is colloid chemistry, which naturally deals with particles on a nanoscale, and which has been remarkably successful in synthesizing “loose” semiconductor nanoparticles with interesting optical properties. I will say more about them later. But physical technologies, like epitaxial growth techniques or colloid chemistry, were joined biological techniques. The synthesis of long DNA strands with a pre-set sequence of base pairs is pure NT in biology and medicine. The combination of physical and biomedical techniques will undoubtedly be one of the most important areas of NT overall, and it deserves the highest possible level of attention at a conference like ours, which grew out of the physical root of the technology. Not being personally knowledgeable about biology, I will, for the remainder of my presentation, stick to physical NT, but I would strongly recommend that the leaders of this conference routinely include in future meetings one or two prestigious invited speakers from the other side.

13.4 Back to the Future: Beyond a Single Degree of Quantization One of the characteristic features of more recent development in physical NT is an increasing emphasis on nanoscale effects in more than one spatial dimension, as opposed to the earlier structures where we studied quantization in just one dimension, with the remaining two spatial dimensions remaining macroscopic. Maybe this is the threshold beyond which it becomes legitimate to speak of NT. 13.4.1 Quantum Wires To me, the beginning of the search for reduced dimensionality was Sakaki’s 1980 “dream” of achieving huge electron mobilities in ideal quantum wires [4], drawing on the idea that in a one-dimensional transport structure an electron could scatter only forward or backward, with the forward process being inefficient in momentum dissipation, and the latter being improbable.

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In the end, this promise remained unfulfilled, due to interface roughness scattering, which had limited the achievable mobilities already in a two-dimensional electron gas, but which was much more severe in quantum wires whose surface-tovolume ratio is much larger. In effect, the second spatial dimension of quantization, within the plane of the wafer, was purely “man-made” by lithography, without any help from nature. It was to be the first encounter with what I consider to be the central problem of almost all nanostructures, the problem of statistical fluctuations – geometrical and others – on the atomic level just below the nominal nanometer dimensions of the structure. What we need badly is a way to have nature help us rather than fighting her. One potential set of candidates with nature-made wire dimensions are the various nanotubes currently being explored. It is too soon to offer a verdict on this possibility, but I was encouraged by a paper at the 2003 APS March meeting where single-wall carbon nanotubes were reported with mobilities higher than in most bulk semiconductors. 13.4.2 Quantum Dots Much of the current research in nanostructures has turned towards quantum dots (QDs), with three dimensions of spatial quantization, especially for optical applications. The initial research utilized the “self-assembled” QDs that form spontaneously during the initial MBE deposition of a material on a lattice-mismatched substrate. This had the advantage that no nanoscale lithography was needed. But the price for this is that the fluctuation problem becomes even more severe than in the case of quantum wires, with fluctuations both in position and size of the dots. While individual single QDs have very narrow optical lines, the exact energetic location of these lines is subject to fluctuations that are very large compared to these natural line widths. In multi-dot ensembles, these fluctuations cause huge inhomogeneous line width broadening within a dot assembly, making the often-cited delta-function-like density-of-states distribution of a set of identical dots an illusion. There are of course applications where such fluctuations are acceptable, and I am in fact an admirer of just how much has been achieved along this direction (see the paper by Henini at this conference). But I believe that the full potential of QDs for future applications goes far beyond what is achievable with this approach, and that we must ultimately overcome not only the size fluctuation, but also the position fluctuations. In fact, tight size control is probably unachievable without tight position control, and position control also becomes necessary for applications where the dots need to be contacted electrically. Hence QDs do not relieve us of the continuing need for lithography down to tens-of-nanometers size scales; lithography will remain an integral part of QD technology. Even with pre-patterning of the substrate, tight size (and shape) control is not assured. If for size control we simply rely on intercepting all the atoms impinging on a precisely pre-defined collection area, we still have to contend with purely statistical Poisson fluctuations: If N is the average number of atoms (or bonding pairs) per dot, √ the actual number will fluctuate with a standard deviation of N. For N = 1000

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(not an unrealistic extrapolation of what we may wish to achieve in the future), this would imply a 3% size variation, probably too large for at least the more demanding applications. Hence, overcoming the Poisson fluctuations must be one of our targets. One simple approach would be to forgo self-assembled dots altogether and to employ post-growth “cookie-cutter” lithography on extended epilayers of precise thickness to define both size and position of the dots. There are almost certainly other approaches.

13.5 More Challenges 13.5.1 Lithography Alternatives for the Nanoscale Given the continuing need for lithography on a nanoscale, we should pursue alternatives to the extreme-UV photolithography approach currently pursued (for good reasons) by the semiconductor industry. For pure research, serial techniques, like e-beam or ion-beam writing, or the use of a STM-like scanning probe, are acceptable. But for practical applications we need techniques that have the massive parallelity of photolithography. In fact, it is this parallelity that lies at the root of Moore’s law. I believe that nano-printing is a promising alternative; it is already being pursued by several research groups, and I believe we should pay more attention to it. 13.5.2 “Loose” Nanoparticles As I mentioned earlier, one of the roots of NT has been colloid chemistry, which by its very nature deals with “loose” nanoparticles rather than QDs on a substrate. Loose nanoparticles suffer from the same fluctuation problem as QDs on a crystal surface. But they have the advantage that they can, in principle, be sorted after their synthesis. I would consider the development of suitable sorting techniques a matter of high priority, ideally not just sorting by size (via centrifuging), but via selected optical excitation. Much of the current interest in loose nanoparticles is in their optical properties, at least where a precisely-defined spatial localization is not required. But I also consider them to be potential building blocks for assembly into three-dimensional nanostructures, similar to the way tennis balls placed into a proper-sized (and shaped) box tend to arrange themselves into a regular lattice. In fact, the achievement of nanoscale three-dimensional structures with controlled properties, rather than just two-dimensional structures, is one of the greatest (and so far unsolved) challenges to nanotechnology. Assembling nanoparticles would be one of the alternatives to in situ synthesis. Another application worth exploring would be the use of nanoparticles as chemical catalysts, including photocatalysts operating under illumination, for example, using sunlight to split water molecules into hydrogen and oxygen. The average photon energy in sunlight is significantly above the 1.23 eV net energy needed, but water does not absorb at that energy due to a high reaction barrier that must be overcome,

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which requires a suitable catalyst. If NT could provide such a catalyst (and perhaps also provide suitable membranes to separate the H2 from the O2 ), the impact on the world-wide energy problem could be huge.

13.6 “Other” Quantization Effects Throughout the above, the word quantization has, at least implicitly, referred to the quantization of energy levels in nanoscale structures. But there are other physical properties that are naturally quantized. 13.6.1 Charge Quantization and Coulomb Blockade The oldest of these is the quantization of electric charge. Classical electronics treats electric current flow as a continuous fluid, and to the limited extent that the discreteness of the electron charge enters classical circuit theory at all, it is as a nuisance effect in the form of shot noise. One of the great opportunities of emerging NT is the potential of single-electron electronics. Nanotechnology is rapidly making it possible to build capacitors sufficiently small that the voltage per electron needed to charge the capacitor becomes larger than the thermal voltage kT /q. For example, for a cube-shaped capacitor with linear dimensions of 10 nm, filled with a dielectric constant of ten, that voltage is 180 mV, already large compared to a room-temperature kT /q of about 26 mV. Following my Lemma, I am not going to speculate exactly what applications such effects might have, be they in metrology, instrumentation, digital logic, or what have you, but I am convinced that research in this field should and will be an active area of future NT. 13.6.2 Magnetic Flux Quantization A second example of “other” quantization effects is the quantization of the magnetic flux contained in a superconducting loop. It has been pointed out that computers based on Josephson junction circuits manipulating discrete flux quanta could in principle be much faster and have much lower dissipation than a conventional computer based on voltage-state logic in semiconductor circuits [5]. In the absence of roomtemperature superconductors, the required cryogenics would of course rule out such a scheme from “everyday” computers, but the cryogenics cost is likely to be acceptable in advanced larger computers where the highest possible performance outweighs all other considerations. At present, the principal limitation to the implementation of this scheme is the technological one of statistical fluctuations amongst Josephson junctions due to fluctuations in their conventional oxide tunnel barriers. If NT could provide atomic-level control over the barriers, this just might lead to the ultimate high-speed mainframe computer.

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13.6.3 Spintronics Electrons not only have charge, they also have spin, and spintronics is the field dedicated to attempts to exploit the spin. Its greatest applications triumph has been in the phenomenon of giant magnetoresistance, the basis of all modern magnetic-disk read heads. Spintronics is not necessarily a part of NT, but it overlaps with NT, and is often quoted in a NT context. Hence, it cannot be ignored in a discussion of NT and its potential applications. As a very active area of modern solid-state physics and technology, spintronics, too, has received a high level of hype, second only to “nano.” And as in the case of “nano,” I am skeptical about some claims about future device applications, specifically about applications where the spin is utilized in an “imitation mode,” namely, using the electron spin rather than the electron charge for various electronic functions that can be performed perfectly well – or better – by charge alone. A notorious example is a “spin transistor” imitating an ordinary bipolar transistor, but using spin orientation rather than electron charge as the signal carrier from an “emitter” to a “collector.” As a research tool for studying spin physics, it is beyond reproach, and I am in fact highly in favor of unrestricted pure research of any kind in spintronics. But viewed as a practical device, the spin transistor has no chance of competing with an ordinary bipolar transistor in any applications that can be met by the latter. Similar criticisms apply to several other applications that have been proposed for spintronics devices. My advice to individuals wishing to go beyond pure research in spintronics, and looking for real-world applications of spintronic devices, is to stick to applications that cannot be done without spin, i.e., where spin is necessary! Giant magnetoresistance is one of those. I am sure there are others; for example non-reciprocal wave propagation effects like Faraday rotation. And of course there is the application of spintronics to hypothetical future quantum computers.

13.7 Meta-Materials One area of NT that I believe to be worth pursuing is the field of meta-materials, defined as artificially structured quasi-bulk materials with new properties that are basically unattainable in an unstructured homogeneous bulk material. What we normally consider a homogeneous material is, on an atomic level, a highly inhomogeneous structured assembly of individual atoms. Nanostructured meta-materials simply work with a second structural level where the “atoms” on that level are themselves artificial “quasi-atoms” put together from true natural atoms. A promising example of the latter would be the extension of so-called photonic crystals to optical wavelengths. This name refers to structures in which – in their simplest form – the dielectric permittivity varies periodically with position, with a periodicity that is on the order of the wavelength of the radiation inside the medium. (For a review of photonic crystals see [6].)

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Wave propagation in periodic media invariably exhibits band structures, with allowed and forbidden bands of propagation, regardless of the nature of the waves. Most work on photonic crystals has concentrated on achieving frequency bands inside which the propagation is forbidden. But unusual effects also take place inside the allowed propagation bands. Just as the allowed bands in an electronic band structure contain regions where the effective mass of the electrons becomes negative (at least in certain directions), a photonic band structure contains regions where a (suitably defined) effective refractive index can become negative [7]. Optical gaps and negative refraction have been demonstrated at microwave frequencies, where the structure periods are macroscopic. Their extension to optical frequencies provides a strong impetus for developing nanotechnologies in this direction.

13.8 Research vs. Applications Re-visited Even if the process from science and technology to applications is opportunistic rather than deterministic, we can speed up this process by better cross-discipline communication between scientists, technologists, and application engineers. It is not uncommon that new possibilities arise within science or technology even as their originators have few (or unrealistic) ideas about applications for them. But an applications engineer might be aware of a potential new application that are just waiting for just such a scientific/technological breakthrough to make the application possible. What I am pleading for is a new form of “triangular workshop” in which these three principal groups talk to each other, rather than each group talking only amongst its own members. For example, a scientist might see some scientific possibilities and might ask the technologists how the necessary structures might be built. Conversely, a technologist might see some possibilities to build something and might ask the scientists whether such a structure might have interesting properties. Most importantly, the two groups might ask the applications engineers what they could do with such structures if they had them. The process would be turned around when an applications engineer perceives of a potential new revolutionary application and asks the scientists about the scientific possibilities and constraints and the technologists how the required structure could be built. For example, given my interest in photonic crystals, I would like to throw the technologists the challenge to develop photonic crystals with interesting refraction properties in the optical regime (infrared and visible), which would require largeamplitude periodic variations of the local refractive index with a nanoscale periodicity. And I would also throw the engineers the challenge of what applications they might have if we gave them a slab of material having a negative refractive index or other bizarre optical properties.

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13.9 Conclusion The title of my presentation asked the question: “Do we really know where we are heading?” To which my answer is: “Not exactly.” We can identify a significant number of different overall directions that appear promising, but I do not believe we can predict which of these directions will be the most promising ones and which – if any – may be blind alleys. And my (or anybody else’s) list of directions is almost certainly incomplete; be it because of limited insight or because new unforeseeable directions may emerge in the course of time. I do not believe we can foresee just how far this any given direction will progress. But does this uncertainty really matter? Hardly! There is enough “out there.”

References 1. H. Kroemer, Rev. Mod. Phys. 73, 783 (2001) 2. H. Kroemer, in Future Trends in Microelectronics: Reflections on the Road to Nanotechnology, Proc. NATO Adv. Res. Workshop, Ile de Bendor, France, 1995, ed. by S. Luryi, J. Xu, A. Zaslavsky. NATO ASI Series E, vol. 323 (Kluwer Academic, Dordrecht, 1996), p. 1 3. N.D. Mermin, Phys. Today 52, 11 (1999) 4. H. Sakaki, Jpn. J. Appl. Phys. 19, L735 (1980) 5. K.K. Likharev, V.K. Semenov, IEEE Trans. Appl. Supercond. 1, 3 (1991) 6. J.D. Joannopoulos, R.D. Meade, J.N. Winn, Photonic Crystals (Princeton University Press, Princeton, 1995) 7. C. Luo, S.G. Johnson, J.D. Joannopoulos, Appl. Phys. Lett. 81, 2352 (2002)

14 Silicon Forever! Really? H.L. Stormer

14.1 Motivation What makes silicon technology so interesting? Yes, it represents an industry far beyond $100 billion. Yes, every person living in a developed country interacts with it almost constantly. Yes, the world’s commerce and communication have become unthinkable without it. Yes, most of today’s products are designed or refined by “silicon.” Yes, it is a showcase for what humans can wring off from Mother Nature through clever engineering. However, what ultimately makes such data processors really interesting – at least in my view – is what they will be able to teach us about ourselves, about our brains, about thought, about consciousness. 14.2.1 The End of Scaling We have come a long way. From a single transistor the size of a fingernail in 1947 to today’s ∼100 M+ transistors on a chip the size of a postage stamp. It represents an incredible triumph of human ingenuity, maybe, in its accumulative string of inventions – the biggest triumph of engineering so far. So what’s the problem? What’s the reason for unrest in the silicon camp? The answer to this question is that the “sky had always been the limit,” but now the sky is within sight. Most experts of the silicon world foresee the limit of scaling to be reached within this decade, maybe a bit beyond. Scaling, the ability to continually reduce the size of the transistor and achieve this at a rate of about a factor of two every 18 months, has been the steroid to the silicon industry. This scaling is expected to be running into severe roadblocks in about five years’ time. There always had been skeptics of continued scaling and the proverbial ceiling was prophesized to be near many times along the way. Human ingenuity always performed an end run around the approaching obstacles. Yet, this time, the ceiling to Originally published at Solid-State Electr. 50(4), 516–519 (2006). Courtesy of IEEE.

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be hit is the sky itself and fundamental physical laws make it unlikely to see many more end runs. The result is an ultimate scale in silicon; a smallest silicon transistor; the standard brick for all future silicon buildings. The industry is concerned. Moore’s law, the dogmatized observation that device size was shrinking exponentially with time, will soon prove not to be a law after all, but just a rule, with temporary relevance to some industry. To the scaling addict it will represent the ultimate low: no progress towards smaller transistors. The “boring” standard transistor – the brick – will be upon us. 14.2.2 The “Beginning” of Architecture The end of scaling, the comeuppance of Moore’s law, is not the end of progress. Indeed, bricks may be boring. However, most brick buildings have not yet been erected, most bridges have not yet been built and most usages of bricks have not even been imagined. Ultimately, the edifices are what we value and revere. As long as new bricks gave us better means to construct, we exploited them towards our architectural ends. With the brick as commodity, it all resides with the architect. And architects have their work cut out for them. As impressive as our silicon data processors are, their accomplishments are puny when compared with those of biological data processors such as our brain. Why can a Pentium chip only run PowerPoint, Word, and Excel, whereas we can think about the origin of life or about dark energy in the universe? Why can’t I have an intelligent conversation with my laptop about the future of the silicon industry? In terms of raw operations per second, my laptop and I are not that far off. I should be running on about 1011 neurons, each having ∼103 synapses switching at a rate of ∼1 kHz, for a total of ∼1017 operations/sec. My laptop with ∼108 transistors at 109 Hz for a total of ∼1017 operations/sec should be roughly at par. One may argue about the fraction of devices engaged at any moment in either processor. One may also question the number of bits per synaptic operation. However, my laptop and I probably do not differ by much more than one order of magnitude in bits/sec; and I am not sure who (or what) has the lead. So why can I “think” while my laptop cannot? The difference must lie with the way the devices in both processors are interconnected and the programs that are being run. It is unlikely that the difference resides with the different brick that has been used – transistor in one case, neuron/synapse in the other. It is rather the different edifice that has been built from either of these components. Architects and computer scientists to the front! As long as Moore’s rule brought us exponential progress in hardware through apparently incessant scaling of the devices, progress in performance was always assured and progress in architecture and software could be viewed as an additional side benefit. At the end of scaling, architecture and software is all there is to progress. Considering the rather rigid architecture of the past decades, the sky again can be the limit, even if it now applies to the shape and intricacy of buildings rather than the size of the brick. There should be no gloom in the industry. Architects and computer scientists should see their grand opportunity to emerge from under the shadow of

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an ever-cited Moore’s rule that made their contributions appear secondary. Moore’s rule is dead. Long live Zip’s rule (my phantom measure for the exponentially shorter running time of a standard suite of programs run on chips of ever-improving design). 14.2.3 Silicon Stands Tall To a hardware person, the recognition of the end of scaling may be demoralizing. It appears that the job is done. And it may well turn out this way, at least for a long time to come. Other semiconductors are unlikely to replace the present silicon and give us more “bang for the buck” at the same ultimate scale. Silicon’s individual properties such as electrical, mechanical, chemical, and thermal seem adequate and, as a combined set, quite favorable. “Luck of the draw,” one might say, although I surmise that many other semiconductors could have been brought to a similar performance level with similar investment in its engineering – to a similar level, but not much better than silicon. When it comes to the ultimate scale, the ultimate speed, it is “geometry, geometry, geometry” that counts and the element Si retreats from the limelight. Silicon forever? It would not be the end of the world. More and more our technologies will reach fundamental limits set by the laws of nature, dethroning human “laws,” such as Moore’s law, and assigning them the level of mere temporary fit to the data – with much psychological and economical impact, though. In any case, what has been achieved in terms of scaling, and still will be achieved in the coming decade or so, is tremendous. The latest experimental transistors are on the atomic scale, in the sense that any of their portraits prominently show the graininess of the underlying atomic matter. Silicon technology stands tall. If we return to our (superficial) comparison with the human brain we have beaten Mother Nature’s data processor in many respects by leaps and bounds. Its fundamental switching device, the synapse, exceeds the size of today’s latest transistor by a factor of 10-to-100. Its switching speed is measured in fractions of a millisecond, whereas transistors switch at fractions of a nanosecond – more than five orders of magnitude ahead. Transmission speed along axons barely exceeds 100 m/sec, the speed of a small airplane, whereas transmission along the wires of silicon circuits progresses at the speed of light, ∼108 m/sec (another six orders of magnitude). In general, biological neural technology would not have made it very far on the design screens of Intel, IBM, or STM. Mother Nature is not a very accomplished engineer when it comes to electricity. Biology is about molecules. Signal transmission and data processing are obviously afterthoughts (no pun intended). A biological cell is a magnificent chemical factory whose detailed inner working still escapes us. Yet electricity is not part of it. In fact, biological data processors do not work “electrically” in the sense that our electronic circuits do. They function “ionically.” It’s the best Mother Nature could do with molecules to perform data processing. Signal transmission along an axon is a most cumbersome process in which ions are pumped periodically through the walls of a largely water-filled hose, in bucket-brigade fashion. Switching of a synapse involves the explosion of hundreds of nano-sized vesicles that deliver their neuro-transmitter load diffusively across the synaptic cleft to the next neuron. The oft-cited hugely

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advantageous parallelism of brain operation is a necessity due to the slowness of its chemically based components, rather than the reverse: the components are slowed down to be able to exploit parallelism. Yet, indeed, it is most impressive what Mother Nature was able to build given what she had at her disposal. But metal wires and transistors are simply better components to build data processors than cells are. In fact, the copper wire is highly underrated as an invention and should be viewed as the greatest contribution ever made to electronics. The superiority of our human-made electronic components should make us enthusiastic about a bright future for exploiting them for data processing in ways as yet undreamed of. Much of this will come about based on the ultimately scaled silicon technology into which it will grow over the coming 5–10 years. And yet, as one steps back, silicon technology has its shortcomings, too. 14.2.4 The Silicon Wart The manufacturing of a silicon chip is a tedious process. Cutting, spinning, baking, exposing, developing, implanting, annealing, depositioning, oxidizing – and a similar sequence 20-some times over, in exceedingly expensive, clean environments filled with costly, sophisticated equipment. Biological processors, on the other hand, just grow. Can we imagine human-made electronics that “just grow”? Why not? After all, Mother Nature has provided an existence proof on how to build very complex structures, even if those structures are not the most accomplished when it comes to electronics. Complexity is the communality between human-made and naturemade data processors and their level of complexity may be comparable, or become comparable soon. Yet in the “manufacturing process” nature excels by leaps and bounds. Take a seed corn, add water, and get a tree. Take an egg and get a fly, a frog, a chick. We have only the most rudimentary understanding about how it works. However, if we could exploit the process in some primitive fashion, we may gain tremendously in what we can manufacture and at what cost. Commonly, the process is referred to as “self-assembly,” which camouflages much of our ignorance. Matter routinely self-assembles on many levels and to varying degrees of complexity. The silicon industry can rightfully claim to exploit selfassembly to an extraordinary extent when it grows(!) crystals from silicon atoms, when it grows silicon dioxide on top of silicon, when it deposits copper into trenches, when it uses solder bumps, and so on and so forth, throughout all its process steps. We are not placing atoms one-by-one into given places. Mother Nature does it largely all for us. Yet this can be viewed as the most rudimentary level of self-assembly – atom-by-atom. Can we assemble molecule-by-molecule? The silicon industry can rightfully argue that it also exploits this process, when it deposits resist or in packaging. Again this is rudimentary, since it produces a random assembly of mostly polymeric chains. Yet the aim is to assemble something useful purposefully. What is commonly referred to as nanotechnology recognizes this challenge. In fact, in my view, the challenge of the self-assembly of matter into complex patterns is the very heart of nanoscience. Creating a full-fledged data processor by self-assembly

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cannot be the initial aim. Even a simple circuit may be too complex for years to come. However, a “transistor” can be self-assembled today. Chemistry is able to create molecules of almost arbitrary design and their electronics can certainly be tuned to behave like an electronic switch when linked to external contacts. In fact, the chemist has some dozens of different types of atoms at hand to create such a “transistor molecule.” This provides for more opportunities to tune its properties “just right” as opposed to the hand-full of different elements used in a silicon transistor. Moreover, “transistor molecules” are cheap, probably not more than ∼$100 for 1023 of them. In spite of the dwindling cost per silicon transistor on today’s chips of ∼10−4 cents, the cost advantage is enormous. Silicon eat your heart out! Nanosized wires, too, can be mass-produced; for example, they may be mass-produced in the form of nanotubes with transport properties superior to those of copper. All these components can be created in very high volume and probably very, very cheaply per unit. So why don’t we use them to make circuits and processors? The answer is clear: the crux of the matter does not reside with creating transistor molecules or creating nanotube wires by exploiting the self-assembling manner of chemistry, although this may have its own challenges. Instead, it lies in the wiring of the components into a complex circuit. Silicon technology creates devices, wires, and circuits almost concurrently by means of lithography. Lithography is the linchpin of the technology. I allege that one would be able to rival the performance of today’s silicon chips by using most any other semiconductor and dielectric for the switches and a different metal for signal transmission. However, the job could not be done without lithography. For this reason “silicon technology” should really be called “lithography technology,” although it would be an awkward tongue twister. Lithography is the key process that allows us to create the complex data processors of today, whereas all other processes and materials are probably replaceable. 14.2.5 Beyond Lithography I allege that there exist currently only two processes on earth that allow for the assembly of very complex entities: lithography and biology. The earlier is much more limiting than the latter. Biology is the master builder on earth, but its materials are simply not suitable for electronic purposes. Can biology, in a broader sense, be exploited to create more complex electronic data processors than we have available today? To follow this path there are two possible routes. The first is to modify biological processes to create electronically viable molecules that biology can assemble into useful electronic units. Think of a bacterium that incorporates a one-kilobit electronic storage cell. It attaches itself to an electrical grid, dies, but leaves the electronic unit intact, which functions as one of millions of memory cells to a system. Bacteria do assemble single domain hematite magnets for navigation. For them to assemble some semiconductor/conductor structure may not be so far-fetched. One could imagine a similar biological process for the creation of logic, although any such path will require our rethinking of processor architecture, fault tolerance, and integration. Quite

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generally, I strongly believe that the creation of any such future processor will require an integrated hardware/software methodology, beyond the application-specific chips of today. The optimized solution for any given task will require specific hardware that may be created specifically and uniquely. If the cost of the processor is sufficiently low, e.g., being “made” by specialized bacteria, such a grow, use, and recycle approach could still be economical. The previous path remains biology-centric. It modifies existing biological systems to manufacture parts and assemble them in some yet-to-be-invented process. Its merits are exploitation of existing highly developed biological machinery. Its drawback is the inherent electricity-ignorance of biology. Hence, the second route may start from “square one” as biology must have started eons ago: Create new molecules that have an electronics-related purpose, such as a switch, a wire, or a memory or that are precursors of such functionalities. Very importantly, these units are endowed with rudimentary intelligence, such as specific recognition sites, docking sites, or sites for splitting, extending, rotating, or twisting. Organic chemistry – not necessarily biological – has proven to be extraordinarily versatile for such tasks and may, in fact, be able to also support the required electrical properties of such molecules. Alternatively, organic end groups may function as the intelligence to otherwise inorganic backbones, conducive to their final electrical purpose. The purposeful creation of appropriate units and the detailed study of their assembly behavior could be viewed as the very, very simple beginnings of an electronics-aimed “biology.” This sounds very futuristic and probably is so, at least in its long-term goals to assemble a highly complex electronic data processor. On the other hand, smaller electronic units such as inverters, NAND gates, and memory cells (or whatever the globally optimized components of the eventual architecture were) don’t seem to be so far-fetched. As an intermediate step to the all-out selfassembled data processor of the future, one may well imagine hybrid systems that exploit lithography technology. Highly specialized silicon processors at the core of fingering trees of nanoscale wires could well provide part of the intelligence for the assembly of pre-assembled, electronic units at the end of its dendritic wire tree. We are far from constructing such a complex functioning electronic processor by molecular self-assembly. Yet we know that complex machinery can be constructed by such a process, as amply demonstrated by our biological environment. This existence proof totally changes the playing field. The question is not whether it can be done at all, but merely how to do it. We will need very clever research and engineering to make progress towards a goal that ultimately will enable us to construct very powerful data processors in an economical way – just the way nature builds its powerful machinery.

14.3 Conclusion Lithography has given us the means to create enormously complex data processors, whose raw number of operations per second is beginning to rival the operation rate of our human brains. While the operations per second on a chip will probably saturate

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within less than a decade, there remain sheer infinite possibilities to wire a chip’s components and to create ever more powerful problem solvers. To go beyond the lithographic age will require the adoption of biologically inspired self-assembling manufacturing processes. At this stage, we hardly know anything about them, but we do have an existence proof in biology itself. That’s why research towards such goals is very well aimed and should prove very fruitful and quite exciting, indeed.

14.4 Acknowledgements and Disclaimer The content of this text derives from numerous conversations spread out over years with many colleagues and friends from several disciplines. I am deeply indebted to these individuals who gladly shared their wisdom, views, sarcasm, and humor and who comprise too large a list to remember in detail. This text does not address various other, very imaginative approaches to lead us beyond the foreseeable limitations of silicon processors. In particular, quantum computing comes to mind. This neglect is simply a result of the author’s ignorance, which on these subjects even exceeds that displayed on the subject he has addressed above. Some of the talking, reading, and thinking was supported by the National Science Foundation through the NSEC (CHE-0117752) award; the New York State Office of Science, Technology, and Academic Research; and a grant from the W. M. Keck Foundation.

14.5 Citations The lack of citations for this paper should not be viewed as the author grabbing credit for all of the thoughts that may have transpired. Views of the kind presented in this text can be found in many journal articles and on the web. The author does not lay claim to the originality of any of the thoughts uttered. They are probably all lifted – often in a subconscious way, though – from a casual conversation with one of his colleagues or from his unsystematic reading of a random text.

Index

1/0 current ratio 265 1952 Nobel Prize in Physics 319 2003 Nobel Prize in Physics 319 4× increase 19 Γ phonon 69, 71 A-defects 80 ab initio pseudopotentials 47 ab-initio 65 Abrikosov 319 abstraction hierarchy 293, 294 AFM 175 AIMPRO 65 Al2 O3 148, 149, 159 Alan Turing 30 ALD 148, 149 AlN 159 aluminium nitride (AlN) 147 aluminium oxide (Al2 O3 ) 147 aluminum 15, 29 ammonium flouride (NH4 F) 127, 131 anharmonic 71 anisotropic strain 234 anisotropy etching 246 antiphase domain boundaries 243 architecture 328 Arrhenius plots 73 assembly line technology 34 atomic form factor 43 atomic layer deposition (ALD) 147, 251 atomic scale 281, 294, 295 atomic-scale features 282 auto industry 34, 35 automobile 33, 34 Avogadro’s constant 9 back-gated 205 backdoor invasions 319 band gap 67

band structure 169, 325 beyond lithography 331 biaxial compressive strain 181, 182, 185 biaxial strain 169, 170, 177, 184 biaxial tensile strain 169, 170, 172, 175 bicycle 33, 34 binding energy 68, 70 biology 331 bipolar transistor 318, 324 Bloch and Purcell 319 Bloch wave functions 50 body biasing 194, 195, 209, 217 Boltzmann 72 Boltzmann constant 71 bond polarization 124 Born–Oppenheimer 67 boron 72 bottom-up 281, 282, 288, 294 bottom-up self-assembly 258 brains 327 brick 328 bridging nanowires 246 Brillouin zone 66, 68, 70, 71 buffer layer 170, 171, 173–176, 178, 182 buffered hydroflouric acid (BHF) 121, 127, 128 business model 17 CAD 24 camel’s hair brush 18, 26, 27, 29 capacitance equivalent thickness 114 Capasso 320 capital depreciation 19 capping layer 147, 159 capture radius 72 Car and Parrinello 66 carbon nanotubes 250, 321 carrier mobility 154–156, 169, 177, 183, 186 Carver Mead 13

336

Index

catalyst materials 237 catalyst nanoparticles 235, 246 catalysts 322 CD player 319 CD reductions 26, 28, 29 change caupled device 20 charge quantization 323 charged defects 68 chemical mechanical polishing (CMP) 120 chemical potential 70 chemical vapor deposition (CVD) 147, 230, 238 chemical vapor transport 238 chemically grown silicon oxide (SiO2 ) 116, 132 chip complexity 12 chirality 250 cluster 64, 65 CMOL 273 CMOS 169, 183, 185, 186 CMOS transistors 318 CMOS/nano co-design 262 CMOS/nano interface 260 coded nanowires 285 colloid chemistry 320, 322 colored light 319 complementary metal–oxide semiconductor 22 complementary MOS (CMOS) 113 complex index of refraction 45 complexity 330 compound-semiconductor nanowires 242 compressive strain 182, 184, 186 Computer-Aided Design 24 conductance modulation 251 configuration entropy 72 configurational entropy 70, 74 configurations 72 conjugate gradient 68 conjugate gradients 67 connecting nanowires 244 contamination 116, 122, 142 cookie-cutter lithography 322 COP 80 copper 29, 81, 84 copper silicide 86 core radii 68 core-shell heterostructure 242 Coulomb blockade 323

Coulomb potential 47 Cramming More Components into Integrated Circuits 17 critical thickness 170 cross-level engineering 294 crossbar array 264 crosspoint 285, 290, 292 crosspoint defects 290 cryogenics 323 CVD 148 cyclic clusters 65 Czochralski 63 D-defects 80 dangling bond 64, 117 David Mermin 319 decoder 284, 286 decoding 260 deep energy levels 236 deep-level transient spectroscopy (DLTS) 62 defect 61, 173, 177, 178, 180, 182, 283, 284, 288, 292, 293 defect bands 68 defect engineering 107 defect reactions 81 defective crosspoints 291 defects in silicon 79 deflationary 31 Delta Airlines flight 191 22 Dennard’s scaling theory 113 density-functional (DF) 65, 73 density-of-states distribution 321 depletion region 243, 251 design 16, 18–21, 23, 25, 33, 35 DF 65, 67 DG 212 DH laser 319 diamond 65 diamond crystal structure 44 dielectric function 45 differentiation 284, 288 Diode–Transistor Logic (DTL) 18 dipole matrix element 45 directed assembly 229, 249 directed self-assembly 232 dislocation 82, 170–173, 175, 177, 178 disolved oxygen O2 131 dissolved oxygen 138 divacancy 63, 65

Index DNA 252, 320 domain boundaries 243 dome 231 donor energy 56 dopant 70 dopant segregation 244 doping 63 doping nanowires 243, 247 double-gate 197, 199, 200 double-gate (DG) 194 double-heterostructure laser (DHL) 318 DRAM 19–24, 29, 36 Dynamic Random Access Memory 12 dynamical matrix 69–71 economic statement of Moore’s law 23 economic value 31 economies of scale 33, 34 EDA 24, 25 effective mass 325 effective mass theory 57, 63 Ehrenreich–Cohen dielectric function 45 elastic strain relaxation 178, 185 electron affinity 54, 55, 243 electron and hole mobility 169 electron correlation 65 electron exchange 68 electron mobilities 320 electron mobility 170, 171, 173, 177, 183 electron paramagnetic resonance (EPR) 62 electronegativity 160 Electronic Design Aids 24 Electronics Magazine 16, 17 elephants 30 empirical pseudopotential method 44 empirical pseudopotentials 53 end of scaling 329 end of the semiconductor industry 35 energy band structure of crystalline silicon 45 energy bands 42 energy bands of silicon 44 energy gap 64, 68 energy saving 33 enhanced carrier mobility 169 epitaxial alignment 241, 245 epitaxial connection 245, 247 EPR 64, 68 equipment prices 35

equipment technology 28 eutectic temperature 239, 241 excited states 68, 73 excitonic effects 46 excitons 46 extended defects 84 extreme-UV photolithography 322 Fairchild 14–16, 18, 19, 36 Fairchild Semiconductor 14, 16 Faraday rotation 324 fast Fourier transforms 66 Fermi-level pinning 158 fiber communications 319 field emitters 239, 245 field-effect sensors 252 field-effect transistor (FET) 251, 318 FinFET 200–203 finite-state machine 287 first-principles 66, 73 first-principles theory 62 flatband voltage 156 fluidic assembly 249 flux quanta 323 Ford 34 formation 68 formation energy 70 fossil fuels 33 fractional horsepower electric motor 13 free energy 70, 72–74 FTIR 62, 68 gap levels 62, 63, 73 gate dielectric 113 gate insulator 113 gate oxide 113 gate stack 113 Gaussian 64, 65 Ge-on-insulator (GOI) 182 general gradient 67, 68 geometry optimizations 65 germanium nanowires 241, 251 gettering 61 GGA 68 giant magnetoresistance 324 Gibbs 70 glass fibers 319 gold 236 Gordon Moore 11, 12, 15, 18, 29, 31, 36

337

338

Index

Goto pair 268 grain boundary 105 graphite 250 Green’s function 64, 74 ground state 73 Grover search 302 GW 64

hydrogen-terminated Si 115, 124, 126–128, 138, 139, 144, 149, 151 hydroxide ion (OH− ) 117, 126, 133 hydroxide (OH− ) 138 hyperfine parameter 56 hyperfine splitting 56 hysteretic switch 258

H2 molecule 72 H-passivated Si 132 hafnium oxide (HfO2 ) 114, 147 hafnium silicate (HfSiO) 147 hafnium silicon oxynitride (HfSiON) 147 hafnium tetrachloride (HfCl4 ) 148 half pitch 281, 294 handcraft 25 handcrafting 25 harmonic 71 Hartree approximation 43 Hartree potential 47 Hartree–Fock 65 He implantation 173 Hellmann–Feynman 67 Helmholtz 70, 71 Henini 321 Henry Ford 34 heteroepitaxial growth 242 HF 124 HF last 115 HfO2 148, 149, 156, 158 HfSiO 156, 159 HfSiON 156 high-k 29, 148, 157, 209 high-k crystallization 156 high-k dielectrics 114 high-k gate dielectric 114 high-k gate insulator 114 high-permitivity gate dielectric 114 high-permittivity (high-k) gate stacks 147 HNO3 123 hole mobility 170, 171, 177, 181–186 humans 24, 25, 30 hybrid crystal orientation technology (HOT) 184 hydrocarbon contamination 123 hydroflouric acid (HF) 132 hydrogen 61, 62, 65, 66, 68, 69, 72 hydrogen passivation 115

imageable feature size 281 imitation mode 324 impurities 61 indium phosphide 240, 248 industrial age 13, 32, 33, 35 inflation 31, 34 information technology 33 infrared (IR) absorption 118 inhomogeneous line width broadening 321 integrating nanowires 244 interconnections 252 interface chemistry 113 interface roughness scattering 321 interfacial silicon oxide SiO2 150 interfacial SiO2 155 internal combustion engine 13 International Technology Roadmap for Semiconductors (ITRS) 185 Internet 33, 319 interstitial H2 70 ion-core pseudopotential 47, 48 ionization energy 54, 55 iron 91 iron oxide 97 iron–silicon alloy 4 Jack Kilby 15, 16 Jahn–Teller 63 Japan 21, 22, 33 Johann Gutenberg 30 John Bardeen 14 Josephson junction 323 Josephson junction qubit 306 Julius Edgar Lilienfeld 14 k-point 67, 68, 73 Karl Marx 13 kinetic energy 67 Kohn–Sham equation 47, 48 Kramers–Kronig transformation 45

Index large scale integration 24 lateral oxidation 158 lattice mismatch 229, 232, 242 Law of Large Numbers 283–285 layer deposition (ALD) 115 layer-by-layer oxidation 122 layout 25 LDA 68 leakage current 191–193, 196, 198, 202–204, 207, 209, 210, 216, 236 learn-on-the-fly 74 Lemma of New Technology 318 light-emitting diodes 319 linear combinations of atomic orbitals (LCAO) 64 lithography 321 lithography alternatives 322 local density 67, 68 local density approximation 47 local exchange 67, 68 local fields 46 local strain 184, 186 local uniaxial strain 169, 186 local vibrational mode (LVM) 62 localized 69 localized defects 61 LVM 65, 67, 68, 71, 73 Madelung energy 68, 73 magic denuded zones 81 magnetic flux quantization 323 Manhattan 287 manufacturing 12, 14–18, 21–23, 25, 27–30, 33–38 manufacturing infrastructure 19 marker 68 MD 66–70, 73, 74 mechanical resonance 245 medical magnetic resonance imaging 319 medium scale integration 24 MEMS 7 mesa transistor 15, 18, 26 meta-materials 324 metal contamination 122 metal gate electrodes 114, 147 metal nitrides 147 metal–oxide semiconductor 12 metal-catalyzed nanowires 235

339

metal-oxide-semiconductor field-effect transistor (MOSFET) 113 metallic gate 210 metastable 68, 70 metrology 323 micro-processing unit 12 MIPS 25 misfit dislocation density 170 misfit dislocations 170 mobility enhancement 213, 214 MODFET 170, 174 modulated reflectivity spectra of silicon 46 molecular devices 258 molecular dynamics (MD) 66 molecular dynamics simulations 49 molecular-beam epitaxy (MBE) 320 molecules 332 MolMOS 260 Monkhorst–Pack 66 Monte Carlo 70 Moore’s clock 12, 19, 28, 37 Moore’s law 11–13, 23, 30, 32, 34–36, 42, 113, 227, 322, 328 Moore’s wall 22, 30, 32, 35 MOSFET 170–172, 175, 177, 181–183 MOSFET scaling 191–193, 195, 215–217 MOSFETS 174 Mother Nature 329, 330 MPU 20 N-choose-M 289 nano-printing 322 nano-talk = giga-hype 317 nanochips 11 nanocrystals 53, 55 nanoimprint lithography 228 nanoparticles 235, 237 nanoPLA 285, 287, 288, 290, 292 nanoscale effects 320 nanoscale periodicity 325 nanoscience 330 nanotechnology (NT) 320, 330 nanotubes 321, 331 NanoWire 273 nanowire 281, 282, 284–286, 288, 290–292 nanowire applications 251 nanowire assembly 249 nanowire growth 238 nanowire heterostructures 242

340

Index

nanowire integration 244 nanowire interconnections 252 nanowire sensors 252 nanowire shape 239 nanowires 58, 235 negative differential resistance (NDR) 259 negative metal–oxide semiconductor 22 negative refraction 325 negative refractive index 325 neural 329 neurons 328 NH4 F 132 nickel 81 nitridation 154, 156 nitrogen 61 non-reciprocal wave propagation 324 normal mode 71 nuclear magnetic resonance (NMR) 319 nucleation 148, 150 nucleosynthesis 3 O2 138 on-chip 294 on-chip tester 292 optical gaps 325 optical lithography 18 optical properties 52 optoelectronic devices 242, 243 Order(N ) 66 organic chemistry 332 Oskar Heil 14 Ostwald ripening 231 oxidation 139 oxidation-induced stacking fault 80 oxide 62 oxidized metal 103 oxygen 61, 72 oxygen precipitation 80 oxygen vacancy 157, 158 p–n junction 245 p-MOSFET 185 P-Terms 288–290, 292 parallelity 322 parameters 66, 73 parasitic resistance 203, 215 particle removal 122 passivation 240 PC market 22, 23

performance 17, 22, 25 periodic 68 periodic supercells 65 periodicity 65 pervade 17 pH 116, 127, 131, 132, 134, 138 Phillips–Kleinman cancellation theorem 43 phonon 71 phonon density of states 70, 71 photoemission 42 photoluminescence 62 photonic crystals 324, 325 photovoltaics 79, 82 piranha clean 115 pitch reduction 260 PLA 267, 286 plane wave 66 pLVM 69 PMLA 269 Poisson 28 Poisson fluctuations 321 polycrystalline silicon (poly-Si) 114, 147 porous silicon 53 position fluctuations 321 post fabrication 294 post fabrication defect 294 post-fabrication configuration 288 potential energy 67, 68, 70 PRDDO 65 pre-patterning 321 precipitation 84 preferential etching 132 process information 30 product terms 288 productivity 13, 28, 31, 33, 35 programmable crosspoints 287 programmable logic array (PLA) 267, 284 programmable majority logic arrays 269 pseudo-atomic orbitals 66 pseudolocal vibrational modes 69 pseudopotential 43, 65, 67, 68 pulsed laser deposition 238 pyramid 230 quantization 240, 323 quantum algorithms 301 quantum cascade lasers 320 quantum computers 324 quantum dots 55, 321

Index quantum effects 320 Quantum Information Roadmap 304 Quantum Monte Carlo 74 Quantum Monte Carlo methods 54 quantum wires 320 quasi-atoms 324 quasi-bulk materials 324 quasi-particle gap 54 qubit 299 Raman 62, 68 Raman spectra 181 Raman spectroscopy 175, 180 rare-earth silicides 234 RCA clean 115 RCA standard clean (SC-1) 121 RCA standard clean (SC-2) 121 real space 50 recombination 61 rectification ratio 265 rectifying junction 245 reflectivity 42 refractive index 325 remote Coulomb scattering 155 remote optical phonon scattering 155 Resistor–Transistor Logic (RTL) 18 resonant modes 69 restoration 285 restoration plane 286 retrograde channel doping 193–195, 208 rotator 70 routing 287 saddle point 68 Sakaki 320 Sankey 66 SC-1 121 SC-2 121, 123 scale length 193, 197, 199, 206 scaling 113, 327 scaling limit 207 scattering-Xα 65 Schottky-barrier contacts 250 self-assembled nanowires 235 self-assembled QD 321 self-assembly 229, 330, 332 self-interstitial 61, 63 SEM 180 semiconductor 169, 183

Semiconductor Industry Association 23 semiconductor nanoparticles 320 semiconductor–metal transition 5 semiempirical parameters 65 SGOI 175–178, 180, 182, 183 Shockley Transistor 14 Shockley–Read–Hall recombination 236 Shor factoring 301 show stopper 35 Si back-bond 133 Si–Si back-bond 124, 139 SIA 23 SIESTA 66 SiGe 173–175, 180 SiGe buffer layer 172, 175–177 signal restoration 268 silicon 65, 66, 327 silicon cleaning 115 silicon nitride (Si3 N4 ) 154 silicon oxidation 136 silicon oxide (SiO2 ) 113 silicon oxynitride (SiON) 113 silicon polymorphs 49 silicon suboxide 116 silicon surface preparation 148 silicon-on-insulator (SOI) 175 silicon/silicon oxide interface 113 simulated quenching 67 SiO2 113 SiO2 dissolution 124 SiON gate dielectrics 155 size fluctuation 321 SOI 178, 180, 184–186 SOI substrate 183 solar cell 82, 83 solid solubility 235 spin 70 spin densities 68 spin qubit 308 spin transistor 324 spintronic 324 SPM 121 SSOI 175, 177, 178, 180, 181, 183 standard clean 1 (SC-1) 115, 116 standard clean 2 (SC-2) 115, 116 statistical fluctuations 321 steam engine 13 strain 169, 171–173, 175, 177–181

341

342

Index

strain relaxation 170, 173, 174, 178, 180, 181 strain-induced nanostructures 229 strain-relaxed 176 strain-relaxed buffer layers 178 strain-relaxed epitaxial layer 170 strain-relaxed graded Si1−x Gex buffer layers 181 strain-relaxed SiGe 172, 178, 182 strain-relaxed SiGe buffer layer 170, 171, 177 strain-relaxed SiGe islands 178 strain-relaxed SiGe layers 178 strain-relaxed SiGe-on-insulator (SGOI) 171 strained Ge 182, 183 strained layer 170 strained layer devices 183 strained Si 170, 171, 174–178, 180–186 strained Si CMOS 173 strained Si MOSFET 180 strained SiGe 178, 182 strained SiGe layers 186 strained-silicon-on-insulator (SSOI) 171 Stranski–Krastanow growth 229 strategic research 319 strategy 19 structure factor 43 sulfuric acid-hydrogen peroxide mixture (SPM) 116 Sumerian clay tokens 30 supercell 67, 69, 72 surface chemistry 113 surface roughening 122 surface roughness 120 swirl defects 80 synapse 329 synapses 328 synergism 319 tax law 19 TEM 174 TEMAH 154 temperature 67, 69–73 tensile strain 171, 175, 178–182, 184, 186 test and configuration manager 292, 294 testing 292, 295 (tetrakis(ethylmethylamido)hafnium (TEMAH, Hf(NC2 H5 CH3 )4 ) 153 thermal donor 74

thermally grown silicon oxide (SiO2 ) 132 thermodynamic integration 70 thermostat 69 thin body 194, 196–198, 205, 208–211, 215 threshold voltage (VT ) 147, 156, 157, 191, 198, 205, 208, 212 tight binding 53 time-dependent local density approximation 50 titanium 237 top-down fabrication 258 total energies 70 traffic lights 319 Traitorous Eight 14 transistor molecule 331 transition metals 61, 81 transmission electron micrograph (TEM) 173 tri-gate 205, 209 triangular workshop 325 trimethylaluminum (TMA, Al(CH3 )3 ) 149 Turing machine 298 UDM 276 ultimate standards 8 ultra-soft pseudopotentials 67 uncatalyzed deposition rate 240 uniaxial compressive strain 185, 186 uniaxial strain 184 uniaxial tensile strain 184, 186 Universal Device Model 276 unpredictability 319 VT 195 vacancy 61, 63–65 van Hove singularities 46 vapor pressure 242 vapor–liquid–solid 239 variance 284 variation 281, 283, 291, 294, 295 vertical nanowire transistors 251 very large scale integration program 21 vibrational entropy 71 vibrational lifetimes 69 VLS 239 voltage-state logic 323 wafer bonding 171, 175, 177, 178, 183–185 wafer size 28, 29, 38

Index Walter Brattain 14 water vapor 144 wetting layer 229 William Shockley 14–16 wired OR 285–288 wood-based paper 30 X-ray absorption microspectroscopy 84 X-ray beam induced current 84 X-ray diffraction 179

X-ray fluorescence 87 X-ray fluorescence microscopy 83 X-ray microprobe 83 yield 21–23, 28, 29, 35, 289, 293 zero-point energy 68 zirconium oxide (Z2 O2 ) 147 zone-refining 6 ZrO2 148, 149

343

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