Handbook of RF and Microwave Power Amplifiers (The Cambridge RF and Microwave Engineering Series)

Handbook of RF and Microwave Power Amplifiers Whether you are an RF transistor designer, an amplifier designer, or a system designer, this is your one-stop guide to RF and microwave transistor power amplifiers. A team of expert authors brings you up-to-speed on every topic, including: r r r r r r r

devices (Si LDMOS and VDMOS, GaAs FETs, GaN HEMTs); circuit and amplifier design (discrete, hybrid and monolithic); CAD; thermal design; reliability; system applications/requirements for RF and microwave transistor amplifiers; amplifier measurements.

Covering state-of-the-art developments, and emphasizing practical communications applications, this is your complete professional reference on the subject. John Walker is currently European Sales Manager at Integra Technologies, Inc. He received his Ph.D. from the University of Leeds in 1976 and has since held various industry positions, including Microwave Hybrids Manager at Thorn-EMI Electronics and RF Division Manager at Semelab. He is the Editor and Coauthor of the books High Power GaAs FET Amplifiers and Classic Works in RF Engineering. He is a Fellow of the IEE.

The Cambridge RF and Microwave Engineering Series Series Editor Steve C. Cripps, Distinguished Research Professor, Cardiff University Peter Aaen, Jaime Pl´a and John Wood, Modeling and Characterization of RF and Microwave Power FETs Dominique Schreurs, M´airt´ın O’Droma, Anthony A. Goacher, and Michael Gadringer, RF Amplifier Behavioral Modeling Fan Yang and Yahya Rahmat-Samii, Electromagnetic Band Gap Structures in Antenna Engineering Enrico Rubiola, Phase Noise and Frequency Stability in Oscillators Earl McCune, Practical Digital Wireless Signals Stepan Lucyszyn. Advanced RF MEMS Patrick Roblin, Nonlinear FR Circuits and the Large-Signal Network Analyzer Matthias Rudolph, Christian Fager, and David E. Root, Nonlinear Transistor Model Parameter Extraction Techniques Forthcoming Sorin Voinigescu, High-Frequency Integrated Circuits David E. Root, Jason Horn, and Jan Verspecht, X-Parameters Richard Carter, Theory and Design of Microwave Tubes Anh-Vu H. Pham, Morgan J. Chen, and Kunia Aihara, LCP for Microwave Packages and Modules Nuno Borges Carvalho and Dominique Scheurs, Microwave and Wireless Measurement Techniques

Handbook of RF and Microwave Power Amplifiers Edited by

JOHN WALKER Integra Technologies, Inc.

CAMBRIDGE UNIVERSITY PRESS

Cambridge, New York, Melbourne, Madrid, Cape Town, Singapore, S˜ao Paulo, Delhi, Tokyo, Mexico City Cambridge University Press The Edinburgh Building, Cambridge CB2 8RU, UK Published in the United States of America by Cambridge University Press, New York www.cambridge.org Information on this title: www.cambridge.org/9780521760102  C Cambridge University Press 2012

This publication is in copyright. Subject to statutory exception and to the provisions of relevant collective licensing agreements, no reproduction of any part may take place without the written permission of Cambridge University Press. First published 2012 Printed in the United Kingdom at the University Press, Cambridge A catalog record for this publication is available from the British Library ISBN 978-0-521-76010-2 Hardback The technical descriptions and procedures in this book have been developed with the greatest of care; however, they are provided as is, without warranty of any kind. The author and publisher of the book make no warranties, expressed or implied, that the equations, programs, and procedures in this book are free of error, or are consistent with any particular standard of merchantability, or will meet your requirements for any particular application. They should not be relied upon for solving a problem whose incorrect solution could result in injury to a person or loss of property. Cambridge University Press has no responsibility for the persistence or accuracy of URLs for external or third-party internet websites referred to in this publication, and does not guarantee that any content on such websites is, or will remain, accurate or appropriate.

Contents

List of contributors Preface 1

Silicon LDMOS and VDMOS transistors: physics, design, and technology

page xiv xv 1

Wayne Burger and Christopher P. Dragon

2

1.1

Technology overview 1.1.1 Introduction/history 1.2 LDMOS and VDMOS construction 1.2.1 LDMOS 1.2.2 VDMOS 1.3 Device physics 1.3.1 Current transport 1.3.2 Behavior of parasitic elements/models 1.3.3 BVDSS , RDSon , HCI boundaries 1.3.4 Snapback/ruggedness 1.3.5 Operating voltage considerations 1.4 Design/layout 1.4.1 Top-down finger layout 1.4.2 Bond pad manifolds 1.4.3 Metal design – electromigration 1.4.4 Thermal 1.4.5 Operating voltage considerations 1.4.6 Frequency considerations: gate length, gate width, resistors 1.4.7 HVICs References

1 1 2 2 8 10 10 12 17 22 26 27 27 29 30 32 34 36 37 39

GaAs FETs – physics, design, and models

42

Rob Davis

2.1

Introduction 2.1.1 Properties of GaAs and related compounds 2.1.2 The Schottky barrier gate and the MESFET 2.1.3 The Pf 2 limit 2.1.4 Types of GaAs FET

42 43 45 45 46

vi

Contents

2.2

2.3

2.4

2.5

2.6

3

Power device physics 2.2.1 The device I–V characteristic and loadline 2.2.2 The dynamic I–V characteristic 2.2.3 The consequences of trapping effects 2.2.4 Device breakdown 2.2.5 Breakdown mechanisms and optimisation 2.2.6 Comments on GaAs FET breakdown ratings 2.2.7 The FET equivalent circuit 2.2.8 Device gain and figures of merit Device design 2.3.1 Power device design 2.3.2 FET channel and recess design 2.3.3 Power cell design 2.3.4 Power cell combination 2.3.5 Thermal design Device fabrication 2.4.1 Overview 2.4.2 Key process steps 2.4.3 Low-cost GaAs device fabrication 2.4.4 Packaging Models 2.5.1 Device models 2.5.2 Small-signal models 2.5.3 Large signal models 2.5.4 Load-pull Concluding remarks References

Wide band gap transistors – SiC and GaN – physics, design and models

51 51 53 54 57 58 59 60 61 63 63 63 67 71 72 74 74 75 81 81 84 84 84 85 89 90 91

103

Robert J. Trew

3.1 3.2

3.3 3.4 3.5

3.6

Introduction Background 3.2.1 SiC transistors 3.2.2 AlGaN/GaN transistors Material parameters Transistor amplifier operating principles Device design and RF performance 3.5.1 4H-SiC MESFET amplifier 3.5.2 AlGaN/GaN HFET amplifier Transistor DC and large-signal RF models 3.6.1 Equivalent circuit transistor models 3.6.2 Physics-based large-signal transistor models

103 105 106 108 111 115 118 120 123 125 125 128

Contents

3.7

3.8

4

Large-signal effects 3.7.1 Space charge limited current transport 3.7.2 Nonlinear source and drain resistance 3.7.3 Gate leakage 3.7.4 Reliability and time-dependent performance degradation Summary References

Amplifier classes, A–S

vii

130 130 133 144 146 152 153 159

Steve C. Cripps

4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12

5

Introduction Active device models Class A Class AB and Class B Class C Class F Class J Inverted modes, inverted Class F Class E Class S Multimodes Conclusions References

159 161 162 164 171 173 176 179 181 183 184 186 186

Computer-aided design of power amplifiers

188

Stephen Maas

5.1 5.2

5.3

5.4

Introduction Methods of analysis 5.2.1 Linear analysis 5.2.2 Harmonic-balance analysis 5.2.3 Time-domain analysis 5.2.4 Applications of analytical methods Passive circuit structures and simulation accuracy 5.3.1 Scattering parameter models 5.3.2 Closed-form models 5.3.3 Models from EM simulation 5.3.4 Database models 5.3.5 Parasitic extraction Solid-state device models 5.4.1 Power device models 5.4.2 Modeling cell interconnections in large devices 5.4.3 Thermal effects in device models

188 188 188 193 202 205 205 206 208 210 212 212 213 213 213 214

viii

Contents

5.5

5.6

6

Special aspects of power-amplifier modeling 5.5.1 Loss in circuit metalizations 5.5.2 Loss in circuit components 5.5.3 Bond wires Practical aspects of nonlinear circuit simulation 5.6.1 Convergence difficulties 5.6.2 SPICE models in harmonic-balance analysis 5.6.3 Problem size minimization and solution optimization 5.6.4 Numerical considerations 5.6.5 Design flow References

Practical HF/VHF/UHF RF power amplifier realization

216 217 219 219 221 221 226 226 227 228 230 232

Daniel P. Myer

6.1 6.2 6.3

6.4

6.5

Introduction RF power amplifier markets The realization process 6.3.1 RFPA qualitative specification delineation 6.3.2 RFPA specifications, generic list and quantification guidelines 6.3.3 Specification/hardware realization RFPA system level design overview 6.4.1 RF power amplifier module design overview 6.4.2 RF power transistor device selection process guidelines 6.4.3 RF power transistor bias/thermal tracking networks 6.4.4 RF input/output coupling/decoupling networks 6.4.5 Power transistor impedance matching 6.4.6 Feedback networks 6.4.7 Thermal management Hypothetical amplifier design example 6.5.1 Hypothetical application example overview 6.5.2 Amplifier qualitative specification delineation 6.5.3 Amplifier specification quantification 6.5.4 Amplifier hardware design/realization 6.6.5 RF transistor selection 6.5.6 Gate bias/temperature tracking/compensation network 6.5.7 Input/output RF/DC coupling/decoupling networks 6.5.8 Input/output impedance matching networks 6.5.9 Feedback network 6.5.10 Test setup configuration/analysis 6.5.11 Physical RFPA module construction 6.5.12 RFPA module test results 6.5.13 Beyond the test data References

232 232 233 234 236 241 242 243 246 249 250 250 251 251 252 252 252 253 254 255 257 259 259 267 268 271 273 281 283

Contents

7

Microwave hybrid amplifier realization

ix

284

Dominic FitzPatrick

7.1 7.2 7.3

7.4

7.5

7.6 7.7

8

Introduction Printed circuit boards Housing 7.3.1 Materials 7.3.2 Sealing and hermeticity 7.3.3 Construction 7.3.4 Thermal issues and heat sinking 7.3.5 RF connections Components 7.4.1 Passive – lumped components 7.4.2 Passive – distributed components 7.4.3 Transistors Amplifier design 7.5.1 Topologies 7.5.2 Matching and stability 7.5.3 Internally matched device amplifiers 7.5.4 Combining 7.5.5 Module size/system integration Biasing and control 7.6.1 Control and interfacing Tuning techniques References

Monolithic power amplifiers

284 285 293 294 294 299 305 311 315 315 323 331 333 333 336 343 344 344 345 352 353 355 357

Inder J. Bahl

8.1

8.2

8.3

8.4

Overview of MMIC power amplifiers 8.1.1 Brief history of MMIC power amplifiers 8.1.2 Advantages of monolithic power amplifiers Monolithic IC technology 8.2.1 MMIC fabrication 8.2.2 MMIC substrates 8.2.3 MMIC active devices 8.2.4 MMIC matching elements MMIC design methodology 8.3.1 CAD tools 8.3.2 Design procedure 8.3.3 EM simulators MMIC PA summary and examples 8.4.1 Narrowband power amplifier 8.4.2 Broadband power amplifiers 8.4.3 Ultra broadband power amplifiers 8.4.4 High-power amplifiers

357 357 358 359 360 361 361 362 370 370 371 372 372 374 376 377 381

x

Contents

8.5

8.6

9

8.4.5 Millimeter-wave 2.4W PA 8.4.6 Wireless 3W power amplifier 8.4.7 High-voltage monolithic PAs Packaging of MMIC PAs 8.5.1 Ceramic packages 8.5.2 Plastic packages 8.5.3 Package assembly MMIC power amplifier characterization References

RF power amplifier thermal design

386 386 387 389 390 394 396 401 406 411

Mali Mahalingam

9.1 9.2

9.3 9.4 9.5 9.6

10

Why thermal design deserves careful attention? RFPA thermal design – basics 9.2.1 RFPA thermal design in a typical portable product 9.2.2 RFPA thermal design in a typical radio base station 9.2.3 Basic heat transfer processes and their role in an RFPA thermal performance Thermo-physical properties of materials in an RFPA Tools to characterize and predict the thermal performance of RFPAs RFPA thermal design and management – advanced RFPA thermal design – trends and prognostication References

Reliability

411 413 413 416 419 423 427 432 440 442 446

Bill Roesch

10.1 Introduction 10.2 Vocabulary and definitions (units, goals, and strategy) 10.2.1 Reliability goals 10.2.2 Semiconductor reliability strategy 10.3 Failure criteria 10.4 Failure modes 10.5 Failure mechanisms 10.5.1 Metalization 10.5.2 Dielectric 10.5.3 Bulk substrate material 10.5.4 Schottky gate FET failure causes 10.6 Failure distributions 10.7 Acceleration factors 10.7.1 Thermal acceleration 10.7.2 Current acceleration 10.7.3 Voltage acceleration factors 10.7.4 RF bias acceleration

446 447 448 448 449 450 451 451 453 454 454 455 458 458 462 465 472

Contents

10.8 10.9

10.10 10.11 10.12 10.13

11

Reliability predictions (MTBF, MTTF, FITs, etc.) Wear-out versus defects (acceleration versus real life) 10.9.1 Thermal excursion example no. 1. Interconnect vias 10.9.2 Thermal excursion example no. 2. Copper bump 10.9.3 Defect amplification and K factors 10.9.4 Environmental example – humidity activation energy Process effects and influence Design for reliability Historical trends and technology comparisons Summary References

Power amplifier applications

xi

473 475 475 478 482 488 492 495 501 502 505 508

Mustafa Akkul and Wolfgang B¨osch

11.1 Introduction 11.2 System design parameter tradeoffs 11.2.1 Output power–efficiency tradeoff 11.2.2 Linearity, modulation scheme, and crest factor 11.3 System level linearization techniques 11.3.1 Introduction to linearization techniques 11.3.2 Digital baseband predistortion 11.3.3 Memory effect compensation 11.3.4 Impact on power efficiency 11.4 Wireless communication power amplifiers 11.4.1 Mobile radio communication today 11.4.2 System level and power amplifier requirements 11.4.3 Power amplifier design outline 11.4.4 Doherty amplifier for efficient base stations 11.5 Military power amplifiers 11.5.1 Radar Tx/Rx modules 11.5.2 EW applications 11.5.3 Anti-IED applications 11.6 In-phase power combining techniques 11.6.1 Wilkinson power combiners 11.6.2 Gysel combiner 11.7 Quadrature-phase power combining – balanced amplifiers 11.7.1 Branch-line quadrature hybrid [19] 11.7.2 Lange coupler 11.8 Anti-phase power combining – push–pull amplifiers 11.8.1 Coupled coil transformers 11.8.2 Transmission line transformers 11.8.3 RF/microwave push–pull amplifier

508 509 509 512 514 514 514 517 517 519 519 522 523 527 530 530 534 538 538 538 542 544 547 549 552 553 554 557

xii

12

Contents

11.9 Doherty combining 11.10 Conclusions References

559 567 568

Amplifier measurements

570

Michael G. Hiebel

12.1 Introduction 12.2 Power measurements 12.2.1 Typical power sensor principles 12.2.2 Typical sources of measurement uncertainties 12.2.3 High-power RF measurements and directional power 12.2.4 Power measurements using a spectrum analyzer 12.3 S-parameter measurements 12.3.1 The concept of S-parameters 12.3.2 Scalar network analyzers and their limitations 12.3.3 Vector network analyzers 12.3.4 Introduction to system error correction 12.3.5 Calibration with different connector types 12.3.6 Calibration with PCBs, test fixtures, and wafer probers 12.3.7 Calibration consideration for high-power setups 12.3.8 Residual errors and measurement uncertainties 12.4 Further linear measurements 12.4.1 Amplifier gain definitions 12.4.2 Efficiency factor 12.4.3 Linear distortion, phase and group delay measurement 12.4.4 Linear stability considerations 12.4.5 Mixed-mode S-parameters 12.5 Nonlinear measurements 12.5.1 Inter modulation distortion (IMD) and harmonic distortion (HMD) 12.5.2 Compression point 12.5.3 Large-signal network analysis 12.5.4 Load- and source-pull measurements 12.5.5 Hot S-parameters 12.6 Modulated measurements 12.6.1 Crest factor and CCDF 12.6.2 Adjacent channel power ratio (ACPR) 12.6.3 Noise–power ratio (NPR) 12.6.4 Error vector magnitude (EVM) and constellation diagram 12.6.5 AM/AM and AM/PM measurements 12.6.6 Memory effects

570 570 570 574 576 579 580 580 582 586 588 589 593 596 598 599 599 602 603 605 608 611 611 615 616 619 622 623 624 625 630 630 632 632

Contents

xiii

12.6.7 Pulsed measurements 12.6.8 Bit error ratio (BER) and symbol error ratio (SER) 12.7 Noise measurements 12.7.1 Amplifier noise factor and noise figure 12.7.2 Noise figure measurement 12.7.3 Noise parameters 12.8 Conclusions References

633 635 636 637 637 640 641 642

About the authors Index

644 651

Contributors

Mustafa Akkul ASELSAN A.S.

Dominic FitzPatrick PoweRFul Microwave

Inder Bahl Cobham Sensor Systems

Michael Hiebel Rohde & Schwarz GmbH & Co. KG.

¨ Wolfgang Bosch Graz University of Technology

Stephen Maas AWR, Inc.

Wayne Burger Freescale Semiconductor

Mali Mahalingam Freescale Semiconductor

Steve Cripps Cardiff University

Daniel P. Myer Communication Power Corporation (CPC)

Rob Davis RFMD

Bill Roesch TriQuint Semiconductor

Chris Dragon Freescale Semiconductor

R.J. Trew North Carolina State University

Preface

In 1989, I was responsible for organizing a workshop at the European Microwave Conference on High-Power Solid State Amplifiers. This workshop proved popular and so Artech House asked me to persuade the speakers to turn their material into a form suitable for publication, the result was the book entitled “High-Power GaAs FET Amplifiers” of which I was editor and a coauthor. That book is of course not just out of print but also largely out of date. This book adopts the same philosophy as the previous one with chapters on device technology, amplifier design, CAD, thermal design, reliability, measurements, and applications – but with a completely different set of authors and with every chapter completely re-written to bring the content up to date. The political, economic and technical landscape has changed almost beyond recognition in the intervening two decades. In the 1980s most RF and microwave engineers were working in military electronics, defense spending was largely responsible for all the technical advances, and there were no mobile phones! Compare that with the situation now where there are probably just as many RF and microwave engineers working on commercial applications as there are in military electronics, commercial applications often drive technical advances, and most households will have not just one but several mobile phones – and it is the mobile phone industry that has largely been responsible for this shift toward commercial applications. However, there is one consequence of this sea-change in the industrial and technical environment which has had a profound knock-on effect when it comes to writing a book such as this. Now the commercial pressures of shortest possible time to market and minimum cost, etc. are so intense that any prospective author working in this field has to be prepared to commit endless hours of their own rather than their employer’s time to the task. I want to publicly acknowledge my deep debt of gratitude to all the authors in this book for making that commitment and hence making this book possible. John Walker

The “Handbook” is a comprehensive reference for RF and microwave power amplifiers. It includes both theory and practice as well as a variety of different applications. Often overlooked supporting topics such as CAD, thermal design, and reliability are treated in depth. John Walker has put together an outstanding team of authors, each of whom is well qualified to address his topic. Finally, I like the way it is organized with separate chapters for three types of RF-power transistors (silicon, GaAs, and GaN/SiC) and separate chapters for amplifiers of different frequency types (HF/VHF/UHF, microwave, and IC). Fritz Raab, Green Mountain Radio Research Company John has successfully brought together, in one book, the current knowledge from world experts actively involved with the characterisation and modelling of devices together with those developing and designing RF and microwave power amplifiers. The timely publication of this book will serve as a useful reference source for engineers working in both the commercial and military market sectors. Steve Nightingale, Cobham Technical Services

1

Silicon LDMOS and VDMOS transistors Physics, design, and technology Wayne Burger and Chris Dragon Freescale Semiconductor

1.1

Technology overview

1.1.1

Introduction/history Power amplifiers are at the core of nearly all high-power (i.e., >5 W) RF applications. The application space includes cellular phone basestation transceiver systems, pulsed radar, ISM (industrial, scientific, medical), avionics, digital television broadcast, etc. This diverse and evolving RF power amplifier landscape dictates the strategy for the design, fabrication, and optimization of multiple generations of RF power devices. The RF power transistor must satisfy a broad and often conflicting set of application requirements, including but not limited to power, linearity, efficiency, gain, reliability, thermal management, bandwidth, ruggedness, digital predistortion (DPD) linearizability, and cost effectiveness. The amplifier architecture has also evolved to adapt to the everchanging system requirements, most recently with the widespread adoption of Doherty amplifiers to boost back-off efficiency in linear applications. These architectural evolutions create opportunities for further refinements in the RF power transistor to extract peak performance from the architecture. The various major market segments of the RF power market tend to embrace a dominant device technology that meets a broad range of these requirements until a new technology emerges to offer a more compelling solution. Through the late 1970s, silicon bipolar transistors were the preferred RF power device technology [1–2]. The relatively low frequencies and amplifier requirements of the era were compatible with silicon bipolar transistor technology, which was capable of providing a robust, cost-effective solution. The bipolar transistors had adequate gain and efficiency, could be readily scaled to achieve the desired power levels, and offered linearity that was consistent with the modest requirements of that era. On the other hand, power gain was relatively poor, packages with isolated flanges were expensive, thermal runaway due to the negative temperature coefficient had to be carefully managed (usually at the expense of degraded performance because of the need to incorporate ballast resistors), and the evolving and increasingly more stringent linearity and efficiency requirements were becoming difficult to design into the transistors. The limitations of the silicon bipolar transistor eventually created an opening for a new generation of transistor technology that offered superior performance without

2

Silicon LDMOS and VDMOS transistors

these limitations. The early 1980s witnessed the emergence of double diffused MOS (DMOS) transistors that were superior to silicon bipolar transistors for many highpower RF amplifier applications [3–4]. A range of factors contributed to this improved performance, starting with the improved frequency response inherent to a majority carrier device compared to the minority carrier transport in the bipolar transistor. Second, the DMOS transistor structure lends itself to high breakdown voltage designs without seriously compromising frequency performance, opening up the possibility of increasing the power supply voltage, lowering the power supply cost, and simplifying the design of ever higher power devices. Another key advantage is that MOSFETs are not susceptible to thermal runaway, due to the positive coefficient of thermal resistance [5]. The ability to design DMOS transistors with high linear efficiency has also emerged as a key factor in their widespread deployment. These topics will be explored in greater detail later in this chapter. DMOS transistor structure and fabrication technology diverged into two main subgroups depending on the direction of current flow, lateral DMOS and vertical DMOS transistors (LDMOS and VDMOS, respectively) [6–11]. Each of these variants has their strengths and weaknesses, and each has largely succeeded in finding appropriate market segments within which to flourish. The doping profile in the channel region of both transistors is formed through the overlap of lateral diffusion profiles, but LDMOS maintains the drain region and current flow laterally near the surface where it can be easily modified and optimized, making it more attractive where linear efficiency and high-frequency operation are important. VDMOS, on the other hand, can achieve excellent power density (i.e., extremely low RDSon /area) since the large drain drift region needed to sustain high breakdown voltages extends vertically below the surface. This same structure tends to limit the scaling of the gate structure, detracting from the high-frequency performance. This makes it the logical choice for applications that require very high-power density at relatively low frequencies. Comparisons between these two technologies will be explored throughout this chapter.

1.2

LDMOS and VDMOS construction

1.2.1

LDMOS Figure 1.1 shows a picture of a packaged high-power LDMOS transistor, a view of the internal construction, and a higher magnification image of the LDMOS die. Figure 1.2 shows a cross-section of a standard LDMOS die. LDMOS die are n-channel enhancement mode MOSFETs. The LDMOS transistor has a long, lightly-doped n-type drift region (hereafter referred to as the n-drift region) between the drain contact and the gate/channel of the device. The LDMOS transistor has the n-drift region oriented laterally referenced to the silicon surface, the origin of the “L” in LDMOS. The drain supply voltage to first order determines the length and doping level in the n-drift region. LDMOS devices optimized for handsets may have an n-drift length of less than 0.5 μm, while an LDMOS device designed to operate at 50 V in an industrial application may require a drift region

3

1.2 LDMOS and VDMOS construction

(a)

Figure 1.1a 2.1 GHz, 170 W LDMOS single-ended part in an air cavity package.

Ceramic substrate

Embedded capacitor Drain lead Transistors

Array of bonding-wires

Gate lead MOS capacitors 50 0m

il

Flange (b)

Figure 1.1b High-power LDMOS device with lid removed illustrating the LDMOS building

blocks, MOSCAPs, and extensive wirebond arrays in the input and output matching networks.

4

Silicon LDMOS and VDMOS transistors

ESD Protection

(c)

Gate Lead

Drain Lead

Figure 1.1c Typical layout of a 50 W LDMOS building block designed for ∼2 GHz operation.

Drain

Gate oxide gate oxide metal strap n + source

n -drift region

n + drain

Channel

p + “sinker”

PHV region p-type epitaxy

p + substrate

Source

Figure 1.2 LDMOS cross-section illustrating key features, including topside gate and drain connections and a backside source.

5–6 μm long. The vast majority of cellular infrastructure base stations are designed with a supply voltage of 28–32 V. When the transistor is turned on, the drift region simply acts as a voltage variable resistor and creates a voltage drop such that the potential in the drain region below the gate is significantly less than the applied DC bias in order to preserve the integrity of the gate oxide and ensure that HCI (hot carrier injection) is limited. Most LDMOS designs also leverage a technique termed RESURF – REduced SURface Fields [12], which relies upon a rapid two-dimensional expansion in the depletion region width with increasing drain bias that keeps the peak electric field below the critical field for impact ionization, without compromising the low drain bias RDSon of the transistor; this technique enables very high breakdown voltages while maintaining the low RDSon necessary to achieve high-power density. Unless stated otherwise, references to power

1.2 LDMOS and VDMOS construction

5

gate n-region

n + drain

n+ source VD = 0 V

5V p-type substrate

10 V 20 V 50 V

Figure 1.3 Depletion region boundaries for VDS voltages of 0, 5, 10, 20, and 50 V in an LDMOS

device.

density refer to W/mm gate periphery; with this definition, high-power density correlates with improved performance for most figures of merit. The nature of the reactive circuit elements in an RF transistor enables the peak drain voltage to reach approximately twice the drain supply voltage Vdd during class AB operation, and even higher during other modes of operation [13]. The ability to withstand these peak voltages explains why data sheets for transistors designed for 32 V Class AB operation typically specify 65 V minimum for drain-to-source breakdown voltage, BVDSS . The lightly doped n-drift region in the LDMOS device, along with the lightly doped p-epi region, are designed to deplete as the drain voltage increases, in alignment with the RESURF principle. The epi depth/doping as well as the n-drift’s depth/doping/extension must be optimized such that the peak electric field across this depletion region does not exceed critical avalanche breakdown levels during the application’s RF voltage swings. Figure 1.3 illustrates through simulation how the depletion region edge progresses through the n-drift region as the drain bias voltage is increased from 1 V to 65 V, with the gate biased at a typical voltage for Class AB operation. Since this region is the largest parasitic resistance within the transistor, it also determines the saturation current and hence power density. Keeping this resistance as low as possible while maintaining an appropriate breakdown voltage and HCI reliability is a critical part of the design tradeoff made in the LDMOS transistor design process. Proprietary techniques are employed to increase the power density without compromising BVDSS or HCI. These three parameters (BVDSS , HCI, RDSon ) define the boundary within which the transistor drain structure is optimized. The lightly doped p-type epitaxial layer is also important to achieve low drain to source capacitance, Cds , which is important to achieve good high-frequency performance. The gate of the LDMOS transistor is most commonly composed of a stack of polysilicon and a silicide (e.g., WSi, CoSi) [14–15]. While a DC current will not flow in the gate of a MOSFET, displacement current from the AC waveform will flow through the gate capacitance, resulting in an undesirable voltage drop across the width of the gate

Silicon LDMOS and VDMOS transistors

1E20 n + source Net Dopant Conc (cm –3 )

6

n + drain

1E19

1E18

p-type lateral channel diffusion

1E17 n − drift region 1E16

1E15

Figure 1.4 Lateral doping profile along the surface of an LDMOS device.

finger. The silicide lowers the gate resistance by at least an order of magnitude over that of highly doped polysilicon. In the case of WSi this can range from 10 /sq to less than 1 /sq, depending on thickness. If the gate resistance is too high, the power gain of the device will suffer. The gate length and gate oxide thickness are key in determining the frequency response of the transistor (i.e., ft , the unity current gain frequency of the transistor). Thinner gate oxides and shorter gate lengths result in a higher ft . In addition, a thinner gate oxide results in a higher device transconductance (gm ), but not necessarily higher RF power gain. This is because the thinner gate oxide also increases the input capacitance of the device which can lower gain. This is another example where design tradeoffs must be considered. The asymmetrical p-channel region of the device is one of the distinguishing features that differentiates the DMOS transistor from the standard MOSFET. For the LDMOS transistor, this region is created by using the gate to self-align a moderate dose p-type implant (referred to as the PHV implant) to the source edge of the gate of the transistor. A subsequent furnace anneal is used to laterally diffuse (the “D” in DMOS) this implant into the channel. The source-side structure is completed by the self-aligned implant and subsequent diffusion of the heavily doped n-type source/drain implant. Figure 1.4 presents the simulated profile from the source to the drain contact along the surface of the transistor, illustrating the four distinct regions of the device (n + source, PHV, n-drift, and n + drain). The result is a MOSFET with a nonuniform channel doping profile, with the source side more heavily doped than the drain side. One advantage of this is that the dopant gradient generates its own electric field which provides a small boost to the overall current transport of the device [16]. More importantly, this design allows the large supply voltages described earlier to be applied without suffering punch-through. As the

1.2 LDMOS and VDMOS construction

7

drain voltage is increased, the depletion region will spread away from the n–p junction formed by the intersection of the n-drift and PHV/p-epi regions. If that depletion region were to reach the source side of the device, the n + source to PHV junction barrier would be lowered resulting in a dramatic increase in the supply of electrons injected into the channel and swept to the drain terminal by the applied electric field. This phenomenon is referred to as punch-through, and results in a loss of control of the drain current by the gate voltage. Since the depletion region width is inversely proportional to the doping density, the growth of the depletion region into the PHV slows considerably as it moves towards the more heavily doped source side of the channel in an LDMOS device (see Figure 1.3). This preserves the high-voltage capability of the transistor. The source of the transistor is unique in an RF LDMOS device because it gets shorted to the body of the transistor. The body cannot be biased separately from the source. This is done so that the back of the wafer can be used as the grounded source in the application. Making electrical ground connection to the back of the die obviates the need for source wires to be present to make a top-side connection. By eliminating the topside source bond wires, a large amount of source inductance is eliminated, increasing the gain of the transistor. To make this backside source possible, the n + source is shorted to a heavily doped p-type region called the p+ sinker by metal 1 (typically an aluminum alloy). This metal is not contacted by a bond wire for biasing and simply acts as a means to short the pn junction between the two regions. The p+ sinker is implanted very early in the process and is thermally diffused until it meets the p+ substrate doping which is gradually diffusing upward during this thermal cycle. The p-epi must not be entirely consumed by the substrate up-diffusion because of the breakdown voltage and capacitance constraints described earlier. A balance between keeping a low-resistance path through the p+ sinker into the p+ substrate and retaining ample lightly doped p-epi for breakdown and low Cds must be struck. The wafer is then thinned through a backgrind process (to thicknesses in the 2–6 mils range) and back-metal is deposited on the wafer backside so that a good, low-resistance contact can be made between the die and package. There are two components of the device design that are located above the silicon surface: the field plate and the drain metallization. The field plate provides an extra degree of freedom within the n-drift optimization tradeoff described earlier. By placing a grounded conductor (i.e., the field plate) close to the surface of the n-drift region, the field plate can perturb the depletion region and electric fields such that a higher doping and/or shorter extension can be used for the n-drift region for a given amount of breakdown voltage and HCI. In other words, the parasitic drain resistance of the device can be lowered, the RF power density of the device can be increased, and the HCI levels in the device can be reduced if the field plate is designed correctly. Figure 1.5 is a simulation of the subsurface electric field for a device both with and without a grounded field plate, from which the peak electric field can be seen to be dramatically reduced for the device with a field plate. In addition, since this field plate is grounded, it can act as a shield between the drain metals and the gate of the transistor, reducing the feedback capacitance Cgd . The drain metallization must be designed to meet the application’s electromigration requirements. RF power devices are typically

8

Silicon LDMOS and VDMOS transistors

with shield

Lateral E-Field Magnitude (V/cm)

4.0e+05

without shield

2.0e+05

0.0e+00 n + source

channel and n − drift

Figure 1.5 Comparison of the lateral electric field magnitude with and without a field plate shield.

designed to operate at a junction temperature up to 200 ◦ C at relatively high current densities. A typical device design target might be a 100-year electromigration median time to failure (MTTF) at rated power and 200 ◦ C. This requires a very robust metallization, and is typically satisfied with a thick aluminum or gold top metal with dimensions (thickness and linewidth) that are appropriate to keep the current density low enough to meet the MTTF goals.

1.2.2

VDMOS The VDMOS transistor (Figure 1.6) shares many of the device design and operational considerations described for the LDMOS transistor. The most significant difference is that the body/substrate of the VDMOS transistor is n-type rather than p-type, and it serves as the drain of the VDMOS transistor whereas the body/substrate is the source for the LDMOS device. The n-drift region is a lightly doped n-type epitaxial layer on top of a heavily doped n-type substrate; the VDMOS epi thickness is the equivalent of the n-drift “extension” in the LDMOS device. This region is also the primary source of parasitic resistance in the VDMOS device but it extends down towards the backside of the die rather than remaining at the surface. This design allows the epi thickness to be adjusted to achieve the target breakdown voltage. For very high breakdown voltages in the 200 + V regime, this vertical design is more appropriate than the lateral design of the LDMOS transistor. VDMOS transistors suitable for RF operation at drain bias levels in excess of 100 V are now on the market [17–18], whereas 50 V is the highest drain voltage operational rating on an LDMOS transistor available today [19–21]. Increasing the drain voltage is the logical pathway to develop high-power parts with user-friendly impedance levels. This has led to a divergence in the market where these technologies

1.2 LDMOS and VDMOS construction

9

Gate

Source metal overlay

Source oxide Gate n + source

n + source p+ diffusion

Channel n-type epitaxy

n + substrate

Drain

Figure 1.6 VDMOS cross-section illustrating key features. Unlike the LDMOS structure, the gate

and source are on the topside while the drain is on the backside of the structure. Adapted from reference [25].

compete against each other, with LDMOS tending to have the highest values of gain, efficiency, and operating frequency, while the VDMOS can achieve higher power levels at higher drain bias values, but at lower frequencies. While the vertical drift region design enables higher drain voltage ratings and power capability, which are significant advantages for certain applications, this drift region design is not amenable to the incorporation of field plates; the performance gains achieved by LDMOS for the past half dozen years were enabled by the incorporation of field plates to allow for aggressive reductions in RDSon and increases in power density without compromising reliability or breakdown voltage. The vertical drift region design also leads to the backside of the device being the drain rather than source/ground terminal (the LDMOS transistor brings the source to the device backside). Since the transistor mounting flange is mechanically and electrically connected to the PA heat sink and to ground, this introduces complexity into the packaging environment for the VDMOS device compared to the LDMOS transistor. Finally, the transition of current flow from lateral to vertical induces current crowding that tends to limit performance compared to the LDMOS purely lateral transport [22].

10

Silicon LDMOS and VDMOS transistors

0.45

7.0 V

0.40

6.0 V 5.4 V

0.35

5.0 V

IDS (A)

0.30 0.25

4.4 V 0.20 4.0 V

0.15

3.4 V

0.10

3.0 V

0.05

VGS = 2.0 V

0V

0.00 0

10

20

30

40

50

60

70

80

VDS (V)

Figure 1.7 IDS -VDS family of curves for various VGS values.

1.3

Device physics

1.3.1

Current transport DMOS devices behave largely the same as standard three-terminal n-channel MOS devices with regard to transistor operation. The current-voltage response can be characterized as having cutoff, linear, and saturation regimes of operation (see Figure 1.7). Current equations for the linear and saturation regions of operation can be approximated by equations (1.1) and (1.2), respectively [23], where ID is the drain current, μS is the electron surface mobility, Cox is the gate oxide capacitance per unit area, W is the total gate width, L is the effective gate length, and VG , VT , and VD are the gate, threshold, and drain voltage, respectively. Due to the graded doping profile within the channel of the device, there is an additional electric-field induced drift current component which is not present in standard MOSFETs, providing an additional boost to the apparent mobility and gm . Note that for small drain voltages, the VD2 term can be dropped from equation (1.1), which then reduces to the familiar linear relationship between ID and VD .   μs Cox W 1 2 (VG − VT )VD − VD ID = (1.1) L 2 ID =

μs Cox W (VG − VT )2 2L

(1.2)

It is worth noting that DMOS devices as commonly designed for RF operation cannot be used as four terminal devices (i.e., gate, drain, source, and body). In both LDMOS

11

1.3 Device physics

Gate

Drain

Source

Figure 1.8 Illustration of the current flow in the LDMOS structure. The current flow is lateral

across the drain and channel, and is then shunted to the source connection at the backside of the wafer.

and VDMOS devices, the body of the device is used as the source or drain, respectively. In both cases this eliminates the need for a top-side contact for all three terminals of the device (i.e., gate, source, drain). In the case of LDMOS, only the gate and drain have top-side contacts allowing for the source to remain a low-resistance, lowinductance connection (i.e., wirebonds are replaced by diffusions that electrically connect the source to the backside of the wafer, which is then connected to system ground – see Figure 1.2) which is important for RF applications. VDMOS has only gate and source top-side contacts, which has layout densification advantages, especially for very high voltage operation, as will be discussed in a later section. The drain of the VDMOS transistor is internally shorted to the substrate which, as previously described, requires an accommodation during packaging since the wafer backside cannot be mounted directly to the package flange and heat sink. The current paths for the LDMOS and VDMOS transistors are illustrated in Figures 1.8 and 1.9, respectively, but remember that current flow is the opposite of electron flow. The LDMOS device shows current beginning at the drain where a positive voltage has been applied and flowing through the lightly doped n-drift region before crossing the channel. The current then passes through the n+ source into the metal which shorts the n+ source to the p+ sinker, and then into the p+ sinker. The current then moves vertically through the silicon and out the backside of the substrate to ground. The VDMOS device has a current path which begins at the back of wafer and moves vertically to the surface, transitioning through the lightly doped drift region formed by the epitaxial layer. It then crosses the channel and exits out of the source contact terminal.

12

Silicon LDMOS and VDMOS transistors

Gate

Source metal overlay

Source oxide Gate

p + diffusion

Drain

Figure 1.9 Illustration of the current flow in the VDMOS structure. The current flow is vertical through the drain region, turning lateral across the channel and into the source.

1.3.2

Behavior of parasitic elements/models In RF power applications, the operational effectiveness (e.g., gain, power density, efficiency, etc.) of a transistor is mostly limited by its parasitic elements. It is in minimizing these elements that the true challenge of device design becomes apparent. Capacitances and resistances pose the biggest problems. Resistances are a problem because they not only dissipate energy but also limit the peak current and hence peak power capability, and contribute to an increase in the knee voltage and hence degrade the peak efficiency of the transistor. Parasitic resistances, although a necessary by-product of certain regions of the device (i.e., the n-drift region) to meet breakdown voltage and HCI reliability goals, tend to degrade the overall performance of the transistor. Many variations of the basic DMOS structure have been reported in an attempt to reduce RDSon without compromising BVDSS . Capacitances pose several problems. The most classical impact is simply to degrade the frequency response of the transistor. Equations (1.3) and (1.4) are simplified equations for fT (unity current gain frequency) and fmax (unity power gain frequency), respectively [24], where Cgs is the input capacitance, Rout is the real part of the output resistance, and Rin is the real part of the input resistance. fT =

gm 2πC gs

(1.3)

1.3 Device physics

13

1.20E-12

CDS/mm (F/mm)

1.00E-12 8.00E-13 6.00E-13 4.00E-13 2.00E-13 0.00E+00 0

10

(a)

20 VDS (V)

30

Figure 1.10a Typical drain-source capacitance (CDS ) versus voltage curve for an LDMOS device.

1.35E-12

CGS/mm (F/mm)

1.30E-12 1.25E-12 1.20E-12 1.15E-12 1.10E-12 1.05E-12 0 (b)

1

2

3

4

5

6

VGS (V)

Figure 1.10b Typical drain-source capacitance (CGS ) versus voltage curve for an LDMOS device.

 f max

fT = 2

Rout Rin

(1.4)

The other impact is that many transistor capacitances are nonlinear functions of the junction voltage and therefore can result in a distortion of the signal being passed through the PA. Figure 1.10 presents input capacitance Cgs , output capacitance Cds , and feedback capacitance Cgd versus voltage curves that are representative of an LDMOS transistor, illustrating the sensitivity of the capacitances to terminal voltage. The variation of these capacitances degrades the efficiency of the input and output matching networks since the fixed value passives in these networks must be designed to operate in an environment where the capacitances being matched depend on voltage. What

Silicon LDMOS and VDMOS transistors

5.00E-14

4.00E-14 CDG/mm (F/mm)

14

3.00E-14

2.00E-14

1.00E-14

0.00E+00 0

5

10

(c)

15

20

25

30

35

VDG (V)

Figure 1.10c Typical drain-source capacitance (CGD ) versus voltage curve for an LDMOS device.

Gate

Drain RG

n+

n−

n+

p

p+

CGS

CGD

RD

CDS

RS p-epi

p + substrate

Source

Figure 1.11 Key parasitic capacitances and resistances superimposed on the LDMOS structure. The gate resistance RG is actually perpendicular to the plane of the drawn structure (i.e., into the page).

follows is a more detailed discussion on each of the key parasitic elements of DMOS transistors. Figure 1.11 shows the various parasitic resistances and capacitances in an LDMOS transistor. The drain resistance (Rd ) is largely dominated by the n-drift region and must be designed to sustain appropriate levels of breakdown voltage while minimizing HCI.

1.3 Device physics

15

1E20

Dopant Conc (cm–3)

1E19

1E18

1E17 good sinker linkage poor sinker linkage 1E16

Figure 1.12 Comparison of the vertical doping profiles through the sinker region of an LDMOS device with and without good linkage to the substrate.

This is discussed in more detail in the next section. The gate resistance (Rg ) is kept low through the use of a silicide which sits atop the polysilicon gate. The silicide provides at least an order of magnitude reduction in gate resistance over just polysilicon. Given the high-power capability of these devices, total gate widths tend to be measured in millimeters rather than microns. How this is achieved from a layout perspective is shown in a later section. The important aspect to consider is that the RF signal is traveling down long stretches of gate and therefore it must also be considered to act as a transmission line. If Rg gets too high, a voltage drop occurs along the gate width and the gain of the device becomes poor. Finally, Rs is driven primarily by the sinker region, the link to the p+ substrate, the p+ substrate resistance, and various smaller resistances associated with the die attach and metal package flange. If one were to take a vertical look at the dopant profile seen through the sinker to the substrate it would look like the solid line in Figure 1.12. A failure to form a low-resistance link between the p+ sinker and the substrate is illustrated by the dashed line in Figure 1.12, which will degrade the RF performance of the transistor. The capacitances in the LDMOS device typically have both fixed and nonlinear components. Beginning with the drain-to-source capacitance Cds , a typical Cds C–V curve is plotted in Figure 1.10a. The nonlinear nature of the curve is due to the nonlinear spreading of the depletion region into both the body and n-drift region as the drain voltage is increased (see Figure 1.3). It is affected by the dopant levels in the device as well as the shield designs which can perturb the n-drift depletions if placed close to the surface. In addition, there are fixed, voltage-invariant intermetal fringing capacitances within the device that shift the entire C–V curve up. The nonlinear nature of Cds can be a problem since voltage swings will create a range of capacitances for each RF cycle. This leads to distortion and can also become problematic for specific types of PA design such as

16

Silicon LDMOS and VDMOS transistors

envelope tracking that vary the drain voltage dynamically to adjust output power levels. Another challenge from nonlinear capacitances is the impact of the nonlinearity on the matching network design; since the matching network components are voltage invariant (inductors and MOS capacitors, typically), the instantaneous impedance transformation will vary across the RF cycle as the device intrinsic capacitance varies, resulting in compromised performance over most of the RF cycle. And finally, Cds determines, to first order, the intrinsic output impedance of the transistor; for silicon transistors in particular, this junction capacitance can lead to very low impedances that are difficult to design broadband matching networks for. The gate-to-source capacitance Cgs in the device is highly dominated by the gate oxide of the transistor. Due to the nature of all MOSFETs the Cgs C–V is highly nonlinear and shown in Figure 1.10(b). Prior to the device reaching threshold there is no inversion layer to span the channel directly below the oxide. Therefore a depletion region is created to uncover charge to balance the applied gate voltage. Once the device goes into inversion, there is an ample supply of electrons directly beneath the oxide surface on which E-field lines can terminate. The capacitance becomes much larger since it now consists of only the gate oxide rather than the gate oxide in series with a depletion capacitance; the onstate Cgs for an LDMOS device is typically two to four times larger than Cds measured at 28 V whereas for a VDMOS device the ratio is closer to unity. This nonlinear behavior of the input capacitance with voltage also creates problems with linearity in the form of phase delays from the input to the output of the device. The gate-to-drain feedback capacitance (Cgd ) has the same C–V shape as Cds but the magnitude in a typical LDMOS device is much lower – Cdg at 28 V is typically less than 5% of Cds at 28 V. The nonlinear contribution stems solely from where the n-drift region is overlapped by the gate and is therefore manipulated by the n-drift doping, the extent of the lateral diffusion of the PHV in the channel, the gate oxide, and the variation in depletion region locations with bias. There are also significant contributions to Cdg from intermetal fringing. Various shield designs have been used to conceal the gate from the drain metal and hence reduce the feedback capacitance. The shield is grounded and therefore terminates E-field lines originating with the drain. Excessive Cgd can lower power gain in the device and increase the instability. The descriptions applied to the parasitic resistances and capacitances for LDMOS also apply to the VDMOS structure. In exchange for the n-drift region becoming vertical and thereby increasing the flexibility to design for breakdown voltages of 100 V or higher, the parasitic capacitances of the VDMOS structure tend to be higher than for the equivalent power RF-LDMOS device. In addition, compared to LDMOS the VDMOS structure lends itself towards lower operational frequencies (i.e., lower gain at a given frequency). The lack of a grounded shield structure in the VDMOS device (see Figure 1.6) tends to increase Cgd , in addition to not providing the additional device design flexibility that a grounded shield layer provides (i.e., the grounded shield has enabled higher n-drift doping concentrations to increase power density without sacrificing HCI performance). There are few benign parasitic elements when considering the performance of highpower RF transistors. A robust design process based upon models that include these parasitic elements is critical to enable optimization of the design across a broad range

1.3 Device physics

17

of performance metrics. An excellent reference for the characterization and modeling of RF power devices is [25].

1.3.3

BVDSS , RDSon , HCI boundaries Breakdown voltage (BVDSS ), linear regime on-resistance (RDSon ), and HCI are three critical parameters that are traded off against one another in the pursuit of higher RF performance. Many aspects of the transistor design are constrained by these parameters and for the most part are controlled by the drain region of the device. Manipulating the drain of the device in various ways (i.e., n-drift doping, n-drift length, shield placement, and design) is collectively referred to as drain engineering. This section is devoted to this topic. Breakdown voltage between the drain and source of a MOSFET while the transistor channel is OFF (i.e., gate voltage is zero for standard LDMOS and VDMOS devices) is referred to as BVDSS . For a typical wireless base station application with the PA operating in Class AB bias, the drain DC supply voltage will be in the 26–32 V range, but the peak RF voltage which occurs on top of the DC bias will essentially be double this value. This would imply a minimum BVDSS requirement of 64 V. For this reason the data sheets typically specify 65 V minimum BVDSS for cellular infrastructure applications. This is achieved with the lightly doped n-drift region that is designed to operate in the RESURF regime. Discussion of the breakdown mechanism is required to understand how this works. The drain-source breakdown in an LDMOS or VDMOS device occurs when the electric field across the n-drain/p-source junction (the junction which is vulnerable in these devices is actually between the drain and the body of the MOSFET, but recall that the source and body are shorted so the drain-source vernacular remains accurate) exceeds the critical level required for a phenomenon known as avalanche breakdown to initiate. With any p/n junction that is reverse biased (as is the case when a positive voltage is applied to the n-type drain while the p-type source is grounded), a depletion region extends into each side of the junction creating a balance of charge. There are no free-flowing electrons in the n-type depletion region or free-flowing holes in the ptype depletion region, hence they are depleted of mobile carriers. Without these mobile carriers, the dopant atoms within the silicon lattice present a fixed charge (i.e., positive charge in the n-type depletion region and negative charge in the p-type region). These fixed charges set up an electric field across the depletion regions. The integrated fixed charge in the depletion regions on either side of the junction is always equal. If the drainsource voltage is increased, the depletion regions grow uncovering additional fixed charge which in-turn results in a larger electric field. How large the depletion region is depends on the level of dopant in that region. If the region is highly doped, the depletion region is quite small since a very small depleted area uncovers a large amount of fixed charge (recall that the fixed charge comes from the dopant in the lattice). If the region is lightly doped the opposite is true: the depletion region must extend a large distance to expose the necessary fixed charge. This concept is important in that for a given applied voltage, the peak value of the electric field that extends over a long distance is lower

18

Silicon LDMOS and VDMOS transistors

than one which occurs over a very narrow region. It is the peak value of the electric field which incites avalanche [26]. Within the depletion region electron-hole pairs are constantly being generated that are swept from the depletion regions by the electric field created by the applied voltage, resulting in the leakage current in the device. As the voltage across the junction increases, the peak electric field will eventually reach a value where the spontaneously generated electron-hole pairs gain sufficient energy from the field to break electron bonds during collisions with the lattice atoms, leading to the generation of new electron-hole pairs. This newly formed electron–hole pair repeats the pattern; it is easy to see how the process can lead to an exponential increase in current for a sufficiently large applied voltage. This process is termed avalanche breakdown. The resultant electrical curve is shown in Figure 1.7. In this example it is clear that an exponential growth in current is occurring at ∼72 V. Designing for high BVDSS is most easily achieved by using a light dopant level on both sides of the drain–source (body) junction. In both LDMOS and VDMOS cases, the body is already lightly doped. The drain however has many design elements which can be adjusted to achieve the desired breakdown voltage. The most obvious given the discussion thus far is to simply use a lightly doped drain. However, if the n-drain region is short and shallow, then the depletion region will very quickly consume the entire n-area and hit the n+ drain contact area, pinning the lateral growth of the depletion region. This means that length and depth of the n-drift region become additional parameters which must be carefully designed. The result is a two-dimensional depletion region spread (RESURF) that does not occur in simple one-dimensional junction theory [12]. Referring to Figure 1.3, the progression of depletion laterally from the channel and vertically from the body causes a reduction in field strength as the overall electric field is now split into vectors which are orthogonal to one another. A full discussion of RESURF is beyond the scope of this chapter but the typical pattern in lateral electric field across the n-drift region is seen in Figure 1.6 with two electric field peaks: one near the channel and one near the n+ drain contact area. To maximize BVDSS the n-drift doping, depth, and length are designed so that these peaks are nearly equal. Another element of drain engineering design is the use of shields or field plates above the n-drift region (see Figure 1.2). The concept behind field plates is to provide an additional degree of freedom to modify the field distributions within this critical region of the device. If a grounded conductive layer is placed close enough to the surface of the device it creates a surface for electric field lines to terminate upon; this structure is commonly referred to as a field plate. The field plate serves several purposes. One is to reduce capacitive coupling between the drain and gate which improves highfrequency performance. It should be noted that early devices placed a grounded metal shield between the drain and gate to reduce capacitance, but far enough from the silicon surface to have minimal effect on the electric field distribution in the drain. Over the past ten years, LDMOS device design has evolved to place the field plate closer to the silicon surface to intentionally alter the field distribution in the drain region. In this regime, the coupling between the drain and the field plate enhances the RESURF behavior in the device, allowing a higher dopant level to be used to achieve a given BVDSS .

1.3 Device physics

19

The higher dopant level increases the power density, improving device performance. In addition, the device engineer can place the shield only above the portion of the n-drift region that is needed and can also control how close it is by choosing the thickness of the dielectric deposited below the shield, providing additional flexibility in the device design. It is important to note that the field plate integrates easily into the lateral structure of the LDMOS device; the VDMOS structure is inherently incompatible with field plate structures. Looking at a typical family of ID –VD curves for various VG values there are two general regions of MOSFET operation as discussed earlier: linear and saturation. In the linear region of operation the MOSFET current versus voltage curves exhibit a slope whose reciprocal is referred to as RDSon . The steeper this slope is then the larger the RF signal can swing before becoming limited by the capability of the transistor. A lower RDSon value typically translates into higher power density and higher efficiency and is considered a critical design component in any LDMOS or VDMOS device. The desire is to keep RDSon as low as possible. The largest contributor to RDSon is the n-drift region where the breakdown voltage discussion above illustrates the need for a lightly doped (more resistive) design. This is one of the fundamental tradeoffs to be made when designing an RF PA transistor, and it is of little surprise that the vast majority of the device design activity is devoted to drain engineering precisely this particular tradeoff. This drove the need for shields/field plates in LDMOS and experimentation with a variety of doping techniques in the n-drift area. Other contributors to RDSon include the source resistance components of the LDMOS and VDMOS devices already covered as well as the channel resistance contribution which is negligible if designed properly. LDMOS devices rely on the lateral diffusion of a p-type implant to create the channel doping profile. This results in the preferred higher doping at the source end of the channel and lower doping at the drain end of the channel (see Section 1.3). However, if the lateral diffusion is too great due to either a thermal cycle which is too aggressive or a gate length which is too short, the p-type dopant will reach the n-drift region and overcompensate. This results in the p-type dopant counter-doping the n-type dopant and that area of overcompensation becomes a p-type region. If there is no n-type region to link up to the drain edge of the gate (see Figure 1.2) then the small p-type region becomes a large parasitic resistance, RDSon increases dramatically, and power capability is lost in the device. This makes controlling gate length and lateral diffusion thermal cycles a critical manufacturing concern for LDMOS. The VDMOS transistor has similar considerations in terms of controlling the lateral diffusion of the PHV implant. HCI in MOSFET transistors must be considered with respect to the impact it will have in RF PA applications. HCI is the third major consideration (the other two being BVDSS and RDSon ). There are a variety of metrics available to characterize HCI, including threshold voltage shift, transconductance degradation, etc. The two critical parameters impacted by HCI for RF power devices are shifts in RDSon and bias current (commonly referred to as IDQ ). For a thorough understanding of these effects a discussion of the device physics involved is required. Two things must be present for HCI to occur: an electric field strong enough to impart significant energy to the carriers making them “hot” and the carriers themselves

Silicon LDMOS and VDMOS transistors

1.00E+00 1.00E-01 1.00E-02 1.00E-03 1.00E+04 IDS (A)

20

1.00E-05 1.00E-06

VDS = 0.1 V

1.00E-07

VDS = 28 V

1.00E-08 1.00E-09 1.00E-10 1.00E-11 0

0.5

1

1.5

2

2.5

3

VGS (V)

Figure 1.13 Sub-threshold ID –VD curves for an LDMOS device (VD = 0.1 V, VD = 28 V).

(i.e., electrons). In the BVDSS discussion the concept of RESURF was used to illustrate that there are two electric field peaks within the n-drift region of an LDMOS device. The electric field peak at the drain edge of the gate is the one which results in HCI if it gets too strong. Under normal transistor operation, electrons are flowing across the channel with the aid of a lateral electric field. As with avalanche breakdown, the field can become strong enough that the electrons are accelerated to a point where collisions with other electron-hole pairs or the silicon lattice occur. While the field is not strong enough to begin the avalanche process, the carriers traveling near the surface can get misdirected during a collision and end up being injected into the gate oxide. How deep into the oxide they are injected depends on the energy of the electron and the available energy states in the oxide. Once injected this electron acts as a fixed negative charge which induces a positive charge in the channel below it. Depending on exactly where the electron is injected there are two different device degradation mechanisms which can occur. If the electron is injected directly over the channel of the device (see Figure 1.2) the impact is on the bias current or IDQ under RF operation. Looking at subthreshold curves of a typical LDMOS device (Figure 1.13) taken with a drain voltage of 0.1 V and 28 V there is an observed shift in the curves. The threshold voltage (VT ) is lower when 28 V is applied to the drain. This is due to a short-channel effect within the field-effect transistor (FET). At the surface of the channel a larger depletion region extends into the channel when larger drain voltages are applied. This uncovers fixed negative charge in the channel. When a positive gate voltage is applied, it is looking to generate an equivalent

1.3 Device physics

21

negative charge in the channel. This leads to inversion as electrons are created at the channel surface and the threshold voltage has been exceeded. If the larger depletion region has already created some negative charge for the gate electric field to terminate upon, then less inversion electrons are required to create a completely turned-on channel. The result is a lower VT . PA applications will set the DC bias using the 28 V (in this example) drain supply by increasing the gate voltage above VT until the desired IDQ is reached. If HCI is occurring during normal device operation, electrons above the channel will induce a positive charge essentially reversing the increased depletion spread caused by the 28 V. This increases VT and starts to de-bias the part (i.e., IDQ decreases). Over time as more electrons are injected, the device slowly loses its bias and the part will no longer operate as needed in the PA. If the electron is injected above the n-drift region, the induced positive charge simply increases RDSon which, as stated earlier, will result in decreased power capability. Robustness to HCI must be designed into the transistor and characterization performed to define acceptable levels. Characterization of HCI affects is performed through stress testing at the DC bias which will be applied to the device in the application. A typical base station PA could require a drain voltage of 32 V and an IDQ of 4 mA/mm of total gate width. A drain voltage of 32 V is applied and then the gate voltage is increased until the 4 mA/mm is reached. A rapid assessment of the HCI would entail applying the steady state DC stress to the transistor for 16–48 hours so that an extrapolation can be made out to 20 years; the RDSon and IDQ drift are established by taking periodic measurements throughout the stress period. Care should be taken to control the temperature of the device under test (DUT) as well as the ambient temperature as VT is temperature sensitive and can also impact the IDQ readings. As described earlier, HCI into the gate oxide above the channel region reverses the depletion region spread caused by the DC bias drain voltage. Referring to our example once again, this means that the VT curve at 32 V begins to move toward the VT curve at a drain voltage of 0.1 V. This is a self-limiting phenomenon which means that the initial impact to IDQ is quite large and then additional injection has less and less effect as time goes on. HCI degradation can be estimated as a logarithmic response by plotting the IDQ response against the time of stress and (Figure 1.14). Most of the degradation occurs in the first few hours and then levels off dramatically. Using this log response, an estimation for the degradation out to 20 years can be made. A well-designed transistor will keep the 20-year degradation in IDQ below 10%. This is usually adequate for ensuring that the PA remains within performance specifications. RDSon increases are also tabulated after the stress testing described above. Again, the 20year response should be below 10% but also of importance is the initial 16 h shift which should be lower than 5% (preferably lower than 3%). It is important to note that HCI is a function of temperature, voltage, and current, and that the above DC testing is intended to provide a device with acceptable HCI sensitivity under most operating conditions. The final assessment of HCI requires testing in the actual application environment to properly account for the actual stress conditions. Many facets of the device structure impact HCI sensitivity, including surface oxide quality, n-drift junction profiles, shield design, etc. HCI mitigation strategies typically work against another device parameter (e.g., reduced n-drift doping to lower HCI will

22

Silicon LDMOS and VDMOS transistors

0.0024 0.00238 0.00236 0.00234

IDQ (A)

0.00232 0.0023 0.00228 0.00226 0.00224 20 years 0.00222 0.0022 1E+01

1E+02

1E+03

1E+04

1E+05

1E+06

1E+07

1E+08

1E+09

Time (s)

Figure 1.14 HCI induced degradation of the quiescent current (IDQ ) in an LDMOS device.

degrade Rdson and potentially impact BVDSS ). The tradeoffs between BVDSS , RDSon , and HCI are fundamental to the design of LDMOS and VDMOS transistors. Engineering various ways of improving these tradeoffs to allow for improvements in RF performance has driven device development in this application space for more than 10 years and continues today. Extensive device simulation is needed to fully understand the complex interactions which are involved with any particular device design. It is also important to periodically characterize HCI under typical application conditions to ensure that the DC characterization remains relevant in its ability to predict application HCI behavior.

1.3.4

Snapback/ruggedness Various RF applications require that the devices be able to withstand different levels of RF stress – they need to be considered “rugged” enough for the application. Usually what drives the ruggedness required is the level of RF voltage/current excursions expected to be experienced by the transistor. These excursions are frequently created by mismatch conditions that occur at the output of the device. Radar applications, for instance, use pulsed signals which may incur transients which stress the device, while applications such as a CO2 laser routinely have the PA operating into what is essentially an open circuit. Usually various voltage standing wave ratios (VSWRs) are used to stress the devices to determine the level of ruggedness. Devices are tested at 5:1 or 10:1 (or higher) VSWRs at different levels of input overdrive to assess robustness. It is also common to

23

1.3 Device physics

Gate

Drain

oxide gate oxide metal strap n + source

n − drift region

n + drain

p + “sinker” PHV region p − type epitaxy

p + substrate

Source

Figure 1.15 LDMOS cross-section illustrating the parasitic npn bipolar formed between the drain,

channel, and source regions.

characterize ruggedness at elevated drain voltages where the device is more sensitive to ruggedness failures. There are two device related design concerns which must be considered when ensuring adequate transistor ruggedness: breakdown voltage and snapback current. The avalanche breakdown concept has already been discussed in detail in the previous section. If RF voltage swings are allowed to exceed the breakdown voltage then the current within the device rises rapidly and there is a risk of a catastrophic thermal failure of the transistor. This means that the first measure of defense against ruggedness failures is designing the part such that the voltage swings spend very little time exceeding breakdown. Of course one could design the part with an extremely large BVDSS to ensure a high level of ruggedness but as is made clear in the previous section this would result in a loss in RF performance. Ideally, the transistor should have the lowest level of BVDSS needed to provide adequate ruggedness for the application. This means that at the extremes the BVDSS will be exceeded, therefore the second aspect of ruggedness design involves increasing the current level which can be withstood while in breakdown. This is most directly linked to a phenomenon known as snapback. Referring to Figure 1.15, there is a parasitic bipolar device within the LDMOS structure (a similar parasitic bipolar device exists within the VDMOS structure – indeed, it is a byproduct of typical MOSFET structures). The emitter is the n+ source, the base is the body of the device and the collector is the drain. When impact ionization is initiated and avalanche breakdown occurs, there is a sudden and dramatic increase in the level of electrons and holes in the drain region of the device. The built-in electric fields pull

Silicon LDMOS and VDMOS transistors

0.45

7.0 V

0.40

6.0 V 5.4 V

0.35

on-state breakdown

5.0 V

0.30 IDS (A)

24

0.25 4.4 V 0.20 4.0 V

0.15

off-state breakdown

3.4 V

0.10

3.0 V

0.05

VGS = 2.0 V

0V

0.00 0

10

20

30

40

50

60

70

80

VDS (V)

Figure 1.16 On-state versus off-state breakdown curves.

the electrons out of the drain of the transistor, while the holes are injected into the base region of the bipolar transistor. The hole current can forward bias the emitter–base junction, and so more electrons are injected across the channel and into the high field drain region which creates more holes and electrons due to avalanching and creating a feedback loop that can result in extremely large, localized current flows that result in catastrophic thermal failure of the transistor. This is referred to as snapback, and can be characterized by both a snapback voltage and current. The goal of enhancing ruggedness is to prevent snapback from occurring by both delaying the onset of impact ionization, and to design the transistor to minimize the injection of holes into the base of the parasitic bipolar once impact ionization has been initiated. Increasing the snapback voltage typically entails increasing BVDSS . However, BVDSS is the off-state breakdown voltage; it is equally important to increase the onstate breakdown (see Figure 1.16). The drain region design (doping levels, shields, etc.) dictates the on and offstate breakdown behavior; design for ruggedness becomes another of the tradeoffs of the drain engineering process. Strategies to increase the snapback current entail both moving the location of impact ionization away from the base of the parasitic bipolar transistor, and designing the device to shunt the hole current to ground, bypassing injection into the base of the bipolar. Figure 1.17 is an example illustrating the effect on hole current by modifying the drain of the device to accomplish both goals (moving the impact ionization away from the base of the bipolar, and shunting the hole current to ground).

1.3 Device physics

Gate

Drain

Hole current injected into base

Gate

25

Drain

Hole current shunted to substrate

Baseline

Optimized

Figure 1.17 TCAD simulation of hole current density for two structures taken into avalanche breakdown. The one of the left depicts a baseline device with the majority of the hole current being injected into the base of the parasitic npn, while the optimized structure on the right shunts the hole current to the grounded substrate, preventing latch-up.

1.4

1.2

TLP Current (A)

1

snapback

0.8

0.6

0.4

0.2

0 0

10

20

30

40

50

TLP Voltage

Figure 1.18 Typical snapback curve due to turn-on of the parasitic bipolar transistor in an LDMOS device.

Characterization of snapback voltage and current is typically carried out using a transmission line pulse generator (TLPG) system, in a similar manner to how ESD sensitivity is characterized. The system works by charging up a transmission line to successively higher voltages and then throwing a switch allowing the stored energy on the transmission line to enter the transistor. At each pulse the voltage and current are recorded allowing a plotting of the snapback curve (see Figure 1.18). Simple DC

26

Silicon LDMOS and VDMOS transistors

measurements will end in destruction once the snapback voltage is exceeded. The TLPG system allows various design parameters to be investigated for their efficacy in adding ruggedness to the device. Finally, the fully designed part is tested as described earlier with various levels of VSWRs and overdrives. This is also a test to destruction where the final level of survivability is recorded. It is important to note that ruggedness performance is a function not simply of the device but the complete operating environment (surrounding circuit, input waveforms, operating temperature, etc.); the final assessment of ruggedness performance must be conducted in the final application under realistic operational and stress conditions.

1.3.5

Operating voltage considerations Although considerable time has been spent in this section discussing ways of designing the breakdown voltage for a given device, the focus has largely been on base station type designs where a voltage supply of 26–32 V is used. LDMOS and VDMOS devices, however, can be easily adapted to the voltage supply requirements of a wide range of applications. The optimum voltage level tends to be proportional to the RF power requirements of the application. In general, changing the n-drift region length (laterally by layout for LDMOS and vertically by epi thickness for VDMOS) and doping level is the easiest way to tailor the breakdown voltage to a given supply voltage requirement. For lower voltage applications such as handset PAs, the voltage can drop as low as 3 V, while for broadcast applications 50 V is quickly becoming commonplace. Other applications in the industrial/scientific/medical (ISM) space are amenable to even higher operating voltages, with VDMOS devices on the market designed for 100 V or higher operation (i.e., BVDSS over 200 V). Typical n-drift region lengths range from 3 μm for cellular infrastructure’s 28–32 V requirements down to the range of 0.5 μm for the low voltage, low-power applications, but can be as high as 6–9 μm for the 50 V applications and very high RF powers. Each end of this range has its own set of design concerns to consider. At the low-voltage end of the spectrum, such a short n-drift region makes it difficult to make the part resistant to snapback. Just by the nature of such a small drift region, the avalanche process is going to occur in close proximity to the base of the parasitic bipolar transistor. This makes the use of a p+ region around the n+ source to lower the gain of the bipolar transistor that much more important in these designs. For 50 V LDMOS designs there is the challenge of achieving breakdowns in excess of 100 V. Long n-drift regions coupled with intelligent shield designs are needed to optimize the usual set of tradeoffs (RDSon, HCI, ruggedness, and BVDSS ). But at some point, the vertical breakdown begins to be the limiting factor as opposed to the lateral breakdown. To circumvent this limitation, a thicker epitaxial layer must be used to extend the amount that the depletion region can extend vertically before hitting the highly doped p+ substrate. The link-up between the p+ sinker and the substrate must be redesigned since there is now a thicker epi layer through which a low-resistance path must be created. The VDMOS device structure is more amenable to increasing the operating voltage. In VDMOS the epi layer thickness and doping level determine the breakdown characteristics. The LDMOS structure has

1.4 Design/layout

27

Figure 1.19 LDMOS discrete transistor layout for an ∼50 W device with 500 μm unit gate width

(UGW).

more flexibility to be designed for very high-power density (W/mm gate periphery) with low parasitic capacitance due to the lateral structure and access to shield layers, but this flexibility tends to be limited to breakdown voltages in the 100–130 V range. VDMOS devices, on the other hand, can be designed with breakdown voltages in excess of 200 V, but with relatively higher parasitic capacitance levels that tend to limit the frequency of operation.

1.4

Design/layout

1.4.1

Top-down finger layout LDMOS and VDMOS devices for RF PAs deliver very large amounts of power. It is not uncommon for a single transistor die to deliver 50 W, and often two to four of these blocks are arranged in parallel within a package to create a single device which delivers in excess of 200 W. Generating this amount of power requires a very large gate width. Single transistor gate widths are routinely over 50 mm and have been known to run to over 1 m. This is an extremely large amount of gate periphery which must be given a layout design which is efficient and optimized for RF operation. This section will discuss the various critical design concerns regarding top-down layout of LDMOS and VDMOS devices. The layout of power transistors with very large gate periphery is designed to satisfy a number of considerations, including thermal, aspect ratio for stress and package compatibility, and frequency of operation. The solution to this challenge is to arrange a large number of shorter gates in parallel such that they operate in unison as one transistor. This parallel arrangement is referred to as an array of gate fingers. All of these fingers sit within one large active area surrounded by some type of field oxide isolation. Figure 1.19 shows a top-down view of a typical LDMOS layout designed for ∼50 W RF power at 2 GHz. Each gate finger is 500 μm wide and is referred to as the unit gate width (UGW) of the transistor. Two fingers in parallel yields 1 mm of gate periphery. The fingers are arrayed such that there is symmetry around the center of each drain and each source. This leads to twice as many gate fingers as there are drain fingers as each drain (and source) feeds two gates. The RF signal and biases are going to be applied to the bond pads at the end of the fingers. This means that each finger will act as a transmission line as the signal progresses

28

Silicon LDMOS and VDMOS transistors

Figure 1.20 Layout showing gate buses feeding gate taps spaced at 100 μm intervals along the fingers in an LDMOS device.

down its length. To minimize the transmission line losses or phase delays which can result, the concept of gate taps is introduced. Notice in Figure 1.20 that there is a gate contact every 100 μm attached to a metal line connected to the gate bond pad. This gate metal line or gate bus is used to carry the input signal down the length of the finger with minimal transmission line effects due to the high conductivity of the aluminum alloy. This bus is then electrically connected to the gate itself such that each 500 μm gate is actually five 100 μm gates in parallel. Recall that the gate itself also typically has a silicide atop the polysilicon to keep the intrinsic gate resistance low. This silicide resistance, however, is two to three orders of magnitude higher in resistance than the metal gate bus, illustrating the necessity of the gate bus. Other unit gate widths and gate tap spacings are employed, typically dictated by the power level and frequency. Larger and larger UGWs eventually generate transmission line losses even within the gate bus while very small UGWs make for very poor aspect ratio devices. Higher frequencies will cause transmission line losses to appear sooner due to the shorter wavelengths and it is therefore more common to see large UGW devices operating in the 900 MHz space and below in the cellular infrastructure arena. Finally the device pitch must be considered. The drain-to-source pitch for LDMOS or source to gate pitch for VDMOS of a given layout is the distance between each axis of symmetry within a single finger (i.e., from the center of the source to the center of the drain for LDMOS, or center of gate to center of source for VDMOS). The LDMOS drain region is typically kept to a minimum because the n+ implant region needed to

1.4 Design/layout

29

make a good drain contact is a large contributor to the output capacitance within the device. Therefore, the minimum n+ drain is determined by the minimum drain contact dimension plus enclosure rules for the n+ implant. The rest of the drain contribution to pitch is set by the n-drift region requirements of the transistor. The source side of the device allows for more flexibility and can usually be expanded or contracted to fit a given package space or meet a thermal requirement. When shrinking the source area for LDMOS care must be taken that the p+ sinker implant does not get too close to the channel of the device. Recall that the p+ sinker undergoes an aggressive thermal drive to diffuse the dopant down through the epi to meet the p+ substrate. Lateral diffusion of the dopant is occurring at the same time and typically reaches several microns. Device pitch, unit gate width, and gate tap spacing are all flexible design parameters that are adjusted based on the performance requirements of the part.

1.4.2

Bond pad manifolds To provide an RF signal to the transistor, wires much be connected from the leads of the package to the silicon die. In the case of LDMOS there are only gate and drain wires since the source is connected through the package flange to ground. This seemingly simple electrical connection turns out to be quite complex in the field of RF device design, since these elements are not merely electrical conductors but instead these conductive elements have capacitance, inductance, and transmission line behaviors that are fundamental to the RF performance. Despite the design considerations mentioned in the previous section, the transistor die still has a large aspect ratio. It is not uncommon to have die which are 1–3 cm wide with an array of fingers spanning most of the length (see Figure 1.1). Placing one gate wire in the center of this array will cause a transmission line affect to be present from the center fingers to the outside fingers. Each finger will not receive the same RF stimulus and this can introduce nonuniformities in device operation due to phase differences between the individual fingers. To remedy this situation, a large number of wires in parallel are bonded from the package lead to a bond pad which spans the entire width of the device. The bond pads incur parasitic capacitance but this is minimized by placing them on top of the field oxide. The goal is to feed the array of fingers as uniformly as possible to maximize performance. This parallel arrangement of wires introduces inductance at the input and output of the device and this must be incorporated into any matching intended for the transistor. Moreover, this wire array is typically utilized and optimized by designers to present a desirable level of impedance at the package lead to ease the customer’s use of the part. At a finer level of detail, there is design of the metal which connects the bond pad to the finger itself. The primary consideration in this region of the device is resistive losses due to large amounts of RF current being funneled out of each finger into the large expanse of bond pad metal. However, designing to meet electromigration requirements typically minimizes this resistive loss (see Section 1.4.3), so this is not typically a problem. Nevertheless, flares such as shown in Figure 1.21 can be used to minimize the impact.

30

Silicon LDMOS and VDMOS transistors

Figure 1.21 Drain metal flare designs for transitioning from drain bus to drain bond pad.

1.4.3

Metal design – electromigration Electromigration is a phenomenon which occurs in metal lines when the DC current density within the lines becomes excessive in conjunction with elevated temperatures – conditions that are easily met in RF power devices. Momentum transfer due to collisions between electrons and the metal conductor atoms can displace the metal atoms which leads to resistance increase and eventually an open circuit under severe conditions. This is a wearout mechanism which occurs over the lifetime of the part and, as such, is a reliability consideration. Electromigration is discussed further in Chapter 10, but this section discusses how to design a device properly such that adequate electromigration lifetimes are achieved. To begin designing for electromigration robustness, the metal being used must be characterized with various current and temperature stress tests. Different metal alloys and metal types vary widely in their electromigration responses. Gold, for instance, has much higher electromigration resistance than aluminum. Aluminum alloys, typically formed by the addition of a small percentage of copper [27] have been developed and are in widespread use in the semiconductor industry; AlCu alloys have excellent electromigration properties compared to pure Al. Copper is another conductor with good electromigration properties. It is important that the electromigration characterization of the metal conductor uses the same processing and structures (linewidth, topography) as the actual device to accurately reflect the microstructure and stresses in the conductor. Once the necessary material constants for the chosen conductor and design have been generated, a simplified form of Black’s equation [28] can be used to begin the design calculations. A MTTF = 2 e J



EA KT

 (1.5)

where MTTF is the median time to failure (typically defined as a certain percentage increase in line resistance), A is a material constant (includes geometry effects), J is the current density, EA is the activation energy, k is Boltzmann’s constant, and T is the temperature.

1.4 Design/layout

31

Figure 1.22 Top-down illustration of the current flow in an LDMOS device.

One of the first things to notice about Black’s equation is that the lifetime it predicts is inversely proportional to the square of the current density. Assuming that the material properties of the conductor have already been optimized to maximize the MTTF performance, the current density is the next parameter that the device engineer will manipulate to improve the MTTF. The current density is typically controlled by using a thick top metal layer, consistent with fabrication design rules and the device structure, stacking metal layers to reduce the current density, and finally by drawing wider and wider lines to lower the current density until the target MTTF is reached. There are of course limits to how wide the metal layers can be due to parasitic capacitance considerations, so careful consideration of electromigration is required in the design of the device. In LDMOS devices, the drain lines carry the largest currents. A top-down view of the current flow (Figure 1.22) shows that there is a greater and greater amount of current being carried by the line as it nears its connection with the drain bond pad. Therefore the electromigration critical design point is the end of each drain finger as it enters the drain bond pad. One common practice is to flare the metal making it wider as it approaches the end of the finger. This keeps the current density relatively constant along the finger length. The downside is that extra parasitic capacitance is generated between the drain metal and the underlying structure (i.e., the gate and source). One technique that can be used to enhance electromigration performance is to design the high-current conductors so that they are in the so-called bamboo regime [29]. Each metal line is comprised of metal grains (see Figure 1.23). If the metal linewidth is kept below the median grain size the line begins to look like a piece of bamboo with the grain boundaries traversing the line laterally. Electromigration occurs preferentially along grain boundaries, so keeping the metal line within the bamboo regime results in

32

Silicon LDMOS and VDMOS transistors

Figure 1.23 The figure on the left is a cross-section TEM through the drain metal of an LDMOS device showing the intersection of three aluminum grains; the image on the right is a contrast-enhanced optical microscope view of the aluminum drain bondpad, showing the distribution of grains in the film.

greatly enhanced electromigration lifetimes. Typical grain sizes can range from less than 1 μm to greater than 5 μm depending on the metal deposition process. The other critical parameter to note in Black’s equation is temperature. The lifetime is exponential with temperature. Given that many PA power transistors run at high-power densities, temperatures can get as high as 200 ◦ C. Hence, the thermal performance of the device and package are important considerations that affect the peak temperature. It is common to find RF power transistors designed to occupy a larger area than is necessary to reduce the areal power density and thereby lower the junction temperature. Once the device design is completed a design curve or calculator is typically generated and made available to enable the customer to calculate the MTTF for their application condition (see Figure 1.24).

1.4.4

Thermal Given the large amount of power dissipated in LDMOS and VDMOS transistors for PA applications, thermal heating within the device must be accounted for. Excessive temperatures will degrade both the performance and reliability. This means that the thermal resistance of the part must be engineered to manage the heat generated during operation. The factors which contribute to the thermal resistance are the materials which the heat must pass through as well as the cross-sectional area through which the heat passes. LDMOS and VDMOS transistors are made from silicon which is given a metal backing (typically gold or a solderable metal film) which is attached either eutectically or soldered to the package flange, which in turn is mounted to the heat sink. Factors which must be considered in the thermal design include layout (increasing the source-drain pitch reduces the power density), substrate thickness (50–75 μm is a typical thickness for high-power parts), die attach technology (gold eutectic being the best, followed by

33

1.4 Design/layout

Pout (W)

25

Vdd (V)

28

Drain Eff (%)

42

10,000 Electromigration MTTF vs. Temperature

MTTF (Years)

1,000

100

10 110

120

130

140

150

160

170

180

190

200

210

Temperature (C)

Figure 1.24 A graph of the electromigration MTTF vs. temperature. The variables are output power, drain voltage, and drain efficiency. The equation for the curve is based upon Black’s equation.

solder), voids formed during die attach (paradoxically, accounting for voids can actually cause the optimum substrate thickness to increase since it acts as a heat spreader around the void), and flange thermal conductivity and thickness (thermal performance is an important driver of package technology). The heat in a DMOS transistor is generated within the primary parasitic resistance of the device: the n-drift region. Looking at the top-down view of an LDMOS transistor (see Figure 1.1) there is an array of drain regions which are all generating heat during operation. From each of these regions the heat will fan out laterally as it moves towards the backside of the wafer. It is therefore a very good approximation to use the total active tub area as the cross-sectional area driving thermal resistance. There are exceptions to this such as when a device is quite small and the edge effects begin to become a large

34

Silicon LDMOS and VDMOS transistors

contributor to the overall thermal resistance cross-section, but for large transistors the approximation is valid. This begins to play a role into how the UGW and pitch are chosen when designing the transistor. Choosing the largest pitch possible for a given package area will yield the best thermal resistance. For a given amount of gate periphery and a given package constraint, moving to the largest UGW that is consistent with electromigration and performance considerations allows the source-drain pitch to be increased, improving thermal performance. It is apparent that there are a wide range of considerations that must be managed during the device design process to achieve the best balance of performance and reliability. Over the years these techniques have held increasing importance as power density within the device has improved. Customers are always seeking more power out of a given package footprint, which places continued challenges on maintaining good thermal resistance. One aspect of device design which helps is the increase of efficiency. As devices have become more and more efficient, either through intrinsic performance or through high-efficiency architectures like Doherty, the heat dissipation has improved for a given amount of delivered power. Thus, a 50 W part with 45% efficiency generates significantly less heat than a 50 W part with 35% efficiency, making thermal resistance design a more important factor for the 35% efficiency part (these are typical efficiency levels in cellular base stations operated in Doherty or simple Class AB, respectively). It should also be mentioned that thermal properties affect the uniformity of the transistor. Figure 1.25 shows an infrared scan of a typical LDMOS transistor. The center of a transistor generally runs hotter than the edges. This creates nonuniformity within the device as the edge fingers will have a slightly different threshold voltage, etc., due to the heat profile. Good thermal design practices will minimize these temperature variations.

1.4.5

Operating voltage considerations This book is focused on RF technologies for power levels exceeding 1 W, or to generalize, noncellular handset RF power applications. For these powers levels and for frequencies up to ∼3 GHz, silicon technologies and in particular LDMOS and VDMOS dominate. The reasons are fairly simple – a low-cost structure, good performance (gain, efficiency, linearity), excellent reliability, and relatively straightforward scalability to powers up to ∼1 kW. The market has segmented by application voltage into three primary bands: 12 V, 28–32 V, and 50 V or higher. As would be expected, the range of device power levels also scale with operating voltage. The 12 V market ranges up to ∼70 W devices, the 28–32 V market ranges up to 300–400 W, and the 50 V + market includes devices rated at over 1 kW. The 12 V market application is primarily for land mobile applications (fire, police, taxi, etc.). The specified maximum application voltage is typically 16 V to allow for automotive battery chargers operating in worst case conditions. Excluding low cost, the most important requirement of this market given the harsh environmental and application conditions that can be encountered is ruggedness. Ruggedness considerations dictate BVDSS in the 50 V or higher range. The land mobile market is characterized by slices of spectrum that vary by country, but in general operate at frequencies under 1 GHz;

35

7S18125AH

Temperature (°C)

GATE

DRAIN

1.4 Design/layout

Figure 1.25 Thermal scan for a 125 W LDMOS device. The PA is typically designed to limit the maximum junction temperature below 150 ◦ C, although the devices are typically rated to operate up to 200 ◦ C to 225 ◦ C.

efficiency at these power levels and frequencies can reach in excess of 70% at P1 dB for class AB operation. Linearity requirements are fairly modest compared to cellular. The dominant technology for this market segment is LDMOS. The 28–32 V market application is dominated by cellular infrastructure, but also includes broadcast, avionics, and other noncellular applications. The cellular infrastructure market is also dominated by LDMOS. This market segment is very performance competitive, requiring state-of-the-art gain, efficiency, and linearity. The application ruggedness requirements are less demanding than for land mobile. Cost is an important consideration, so long as performance is competitive. The cellular infrastructure market has been under significant cost pressures for the past decade, which has driven packaging innovation such as high-power over-molded plastic transistors that have a lower cost structure than the historical ceramic air-cavity packages. The BVDSS minimum for these voltages is typically 65 V. LDMOS products are on the market for frequencies up to 3.8 GHz for WiMAX applications; VDMOS devices compete in the subGHz, noncellular arena where their more limited frequency capability is not a limitation. The 50 V and higher markets are concentrated in the relatively broad noncellular application space that includes ISM, avionics, and broadcast markets. These markets

36

Silicon LDMOS and VDMOS transistors

have a very diverse set of performance requirements, with certain applications requiring high-pulse CW with no linearity requirements, while others demand stringent back-off linearity with good efficiency. These devices require excellent ruggedness performance; certain applications like CO2 lasers routinely subject the transistors to open circuit conditions at high power levels, representing a testing ground for a transistor’s ruggedness capability. This application space typically requires higher power transistors than are practical with 28 V devices, with products on the market at power levels exceeding 1 kW. 50 V devices tend to have minimum BVDSS values in the 105 V–120 V range, but applications with extreme ruggedness requirements could have even higher breakdown values. It is only within the past several years that 50 V LDMOS devices have been on the market [19–21]. VDMOS competition is robust, particularly at lower frequencies and high power levels. The vertical structure of VDMOS also enables scaling of the breakdown voltage to allow operating voltages of 100 V [17–18]. The lateral LDMOS structure does not scale as readily to support BVDSS values of 200 V or higher that are necessary to operate at 100 V.

1.4.6

Frequency considerations: gate length, gate width, resistors Before delving into frequency considerations, it is worthwhile to consider the impact of transistor gain on efficiency and cost. It becomes challenging to design stable parts with good isolation if the gain exceeds about 25 dB in a single stage transistor (multistage lower power ICs have been designed with gain up to ∼35 dB [30–31]). The desire for high gain is primarily cost – a higher gain, high-power final stage in the PA lineup will require a lower power and hence lower cost driver, potentially fewer devices in the lineup, and require less space on the printed circuit board (which also translates into cost savings). There are also lineup efficiency benefits with a high-gain final stage. The power-added efficiency (PAE) is a metric that tracks the conversion efficiency of DC from the power supply into RF power, and is defined by the equation: PAE =

Pout − Pin PDC

(1.6)

where Pout is the RF output power, Pin is the RF input power, and PDC is the power from the DC power supply to the device. PAE, as the name indicates, is a measure of how efficiently the device converts DC power to RF power, and hence can be used to determine power dissipation in the device. A 50% PAE device must dissipate an amount of power equal to its output RF power while a 25% PAE device dissipates three times as much power as it transmits. The highest possible PAE that meets other system requirements is clearly the goal. By manipulation of the variables, PAE can also be written as:   1 PAE = η D 1 − (1.7) G where ηD is the drain efficiency (defined as the ratio of Pout to PDC ), and G is the RF power gain. For a gain of 20 dB (a factor of 100), the PAE is within 1% of the drain efficiency. As the gain falls below 15 dB, the PAE begins to fall rapidly, degrading

1.4 Design/layout

37

overall efficiency and increasing operating costs in addition to requiring more expensive techniques and mechanical items to manage the dissipated heat. By the same token, there is little efficiency motivation for the gain to exceed 20 dB from an efficiency perspective, although there are still cost and board space considerations. Simple filter theory predicts for a single pole transfer function that power gain will follow a 6 dB/octave rolloff with frequency, i.e., a 20 dB gain part at 2 GHz will have 26 dB gain at 1 GHz, 32 dB gain at 500 MHz, etc. A common approach during device design is to develop the transistor to have as high a gain as possible at its maximum operating frequency without compromising other parameters (i.e., reliability, ruggedness, etc.), and then to limit the gain increase at the lower frequencies to maintain a stable device and circuit. Maximizing performance at the highest frequencies of operation causes the device designer to migrate towards the classical solutions of shorter gate lengths, thinner gate oxides, and aggressively reducing all parasitic capacitances and resistances. The LDMOS structure is more amenable to optimizing for high frequency compared to VDMOS, with LDMOS dominating the cellular infrastructure frequencies. Excessive gain at lower frequencies can be countered by degrading the intrinsic gate of the transistor (longer gate length, thicker gate oxide). Another approach that offers ancillary benefits is to add series resistance to the gate feed network, which not only decreases the gain to manageable levels but also lowers the Q of the input network, facilitating the design of broadband matching networks. High-power device design also requires careful optimization to the layout of the individual fingers. Practical limits of gate width at frequencies of 1–3 GHz are of the order of 1000 μm, with the maximum gate width decreasing as the frequency is increased. Excessive gate widths exacerbate distributed effects (transmission line delays, phase shifts, etc.) and lower the gain and can impact efficiency and linearity. As frequencies decrease below 1 GHz, these distributed effects become less important and the device layout tends to be dictated by package constraints and reliability considerations, such as electromigration.

1.4.7

HVICs High voltage integrated circuits (HVICs) in the context of high-power RF devices typically refers to having at least two stages of amplification along with elements of the matching network (e.g., inductors, capacitors, resistors) all integrated onto the same semiconductor substrate. HVICs in cellular infrastructure were first introduced as driver devices that were designed to power the final stage of the PA lineup. The first highpower cellular infrastructure HVIC in production was the MRFIC5001, introduced by the semiconductor sector of Motorola (now Freescale) in 1999. The MRFIC5001 is a 10 W, 900 MHz GSM driver HVIC; this HVIC is a two-stage device having 26 dB gain at 26 V, and was based on the third-generation HV3 LDMOS platform from Motorola. The design of both driver stage and final stage high-power HVICs has flourished since this time, with almost all PA designs now including HVICs in the lineup [32–35]. The advantages of integration are well known, and include a dramatic reduction in component count and board space, lower cost, and reduced overall performance

38

Silicon LDMOS and VDMOS transistors

Output stage

Input stage

GND

VD1

NC

NC

NC RF in RF in

NC

VG1

VG2

NC

GND

Figure 1.26 Assembly drawing of a 2 GHz, 100 W LDMOS high-power IC. This is a 2-stage IC, with a fully integrated input and interstage match (input impedance is 50 ), and an integrated shunt-L output match.

variation. Modern HVICs are two stage designs due to the high gain of the individual LDMOS stages. A traditional discrete design matching network is constructed using high-Q inductors and capacitors. The inductor is formed from wirebonds and can have a Q in the 50–100 range. The matching network passive elements in HVICs include spiral metal inductors and integrated series and shunt capacitors. The most challenging passive to integrate into the LDMOS flow is the spiral inductor which, due to the heavily doped substrate, is limited to Q values in the 5–10 range; integrated capacitor performance does not tend to be the limiting factor in HVIC designs. The relatively low value of the integrated inductors is adequate for the design of input and interstage matches, but is too low for the output stage. Wirebonds continue to be employed at the output of the final stage of HVICs where the much higher currents require the highest possible inductor Q to achieve target performance levels. The performance of HVICs has advanced over the past decade. This has been enabled not only by the improved performance of the LDMOS transistor, but also by passive component optimization and refinements in the design methodology to extract as much performance as possible. An example of the state-of-the-art in IC design today is the MW7IC18100N [36], which is a two-stage IC rated at 100 W at 1.8 – 2.0 GHz with 30 dB gain, designed as a high-gain, high-power output device for GSM and GSM Edge applications (see Figure 1.26). Another example of the progress made in HVIC performance is found in the MW7IC3825N [37]. This IC is designed for 28 V operation

References

39

in the 3.4–3.6 GHz band, is rated at 25 W P1 dB , and has been characterized for WiMAX operation. These examples illustrate the significant progress made in both the process technology as well as the design methodology to enable the design of high-performance, high-power HVICs.

Summary The application space for high-power RF transistors is broad and growing, ranging from the ubiquitous cellular base station to avionics, broadcast, industrial, scientific, medical, etc. The requirements placed upon the RF power transistor varies depending upon the application requirements, including power gain, linearity, efficiency, reliability, thermal management, bandwidth, ruggedness, linearizability and, last but certainly not least, cost. LDMOS and VDMOS technologies dominate these applications due to an excellent combination of these factors. VDMOS is strongest at lower frequencies and higher power levels where the vertical structure can best be leveraged into a higher operating voltage capable of very high power levels. LDMOS is the dominant device technology for cellular infrastructure basestation PA applications, and has over the past few years been introduced into markets that were traditionally the domain of VDMOS and silicon bipolar transistors. VDMOS and LDMOS together dominate the market for high-power PAs from frequencies in the low MHz range up to 4 GHz, and for power levels that exceed 1 kW. Investments continue to be made in both VDMOS and LDMOS to further improve performance and meet the evolving requirements of the end applications.

Acknowledgments The authors would like to acknowledge the support and assistance provided by our colleagues at Freescale, without which much of this chapter would not have been possible.

References 1. J. T. C. Chen and C. P. Snapp, “Bipolar microwave linear power transistor design,” IEEE Trans. Microw. Theory . Techn., vol. MTT-27, no. 5, pp. 423–430, May 1979. 2. C. P. Snapp, “Microwave bipolar transistor technology – present and prospects,” Ninth European Microwave Conference, Sept. 1979, pp. 3–12. 3. E. Fong, D. C. Pitzer, and R. J. Zeman, “Power DMOS for high-frequency and switching applications,” IEEE Trans. Electron Devices, vol. ED-27, no. 2, pp. 322–330, Feb. 1980. 4. O. Ishikawa, H. Yamada, and H. Esaki, “A 2.45 GHz Power LD-MOSFET with reduced source inductance by V-groove connections,” International Electron Device Meeting, 1985, pp. 166–169.

40

Silicon LDMOS and VDMOS transistors

5. J.-J. Bouny, “Advantages of LDMOS in high power linear amplification,” Microwave Eng. Europe, pp. 37–40, 1997. 6. A. Wood, W. Brakensiek, C. Dragon, and W. Burger, “120 watt, 2 GHz, Si LDMOS RF power transistor for PCS base station applications,” IEEE MTT-S Microwave Symp. Dig., vol. 2, pp. 707–710, 1998. 7. C. Cassan, J. Jones, and O. Lembeye, “A 2-stage 150 W 2.2 GHz dual path LDMOS RF power amplifier for high efficiency applications,” IEEE MTT-S Microwave Symp. Dig., pp. 655–658, 2008. 8. F. van Rijs, “Status and trends of silicon LDMOS base station PA technologies to go beyond 2.5 GHz applications,” IEEE Radio and Wireless Symposium, 2008, pp. 69–72. 9. P. H. Wilson, “A novel high voltage RF vertical MOSFET for high power applications,” Tenth IEEE International Symposium on Electron Devices for Microwave and Optoelectronic Applications, 2002, pp. 95–100. 10. M. Trivedi and K. Shenai, “Comparison of RF performance of vertical and lateral DMOSFET,” Eleventh International Symposium on Power Semiconductor Devices and ICs, 1999, pp. 245– 248. 11. J. Zhang, D. Sdrulla, D. Tsang, D. Frey, and G. Krausse, “Design of rugged high voltage high power p-channel silicon MOSFET for plasma applications,” 38th European Solid State Device Research Conference, 2008, pp. 71–74. 12. J. A. Appels and H. M. J. Vaes, “High voltage thin layer devices (RESURF Devices),” International Electron Device Meeting, vol. 25, pp. 238–241, 1979. 13. F. H. Raab, F. H. Raab, P. Asbeck, S. Cripps, P. B. Kenington, Z. B. Popovic, N. Pothecary, J. F. Sevic, and N. O. Sokal, “Power amplifiers and transmitters for RF and microwave,” IEEE Trans. Microw. Theory Techn., vol. 50, no. 3, pp. 814–826, 2002. 14. W. R. Burger, “Recent advances in RF-LDMOS high-power IC development,” IEEE International Conference on IC Design and Technology, 2009, pp. 35–38. 15. S. J. C. H. Theeuwen and H. Mollee, “S-band radar LDMOS transistors,” European Microwave Integrated Circuits Conference, 2009, pp. 53–56. 16. W. Xie and B. Li, “An analytical current model for lateral gradual doping channel in LDMOS,” IEEE International Conference of Electron Devices and Solid-State Circuits, 2009, pp. 16–19. 17. STMicroelectronics, “RF power transistors HF/VHF/UHF N-channel MOSFETs,” STAC4932B datasheet, Feb. 2010 Revised Aug. 2010. 18. Microsemi, “RF power MOSFET n-channel enhancement mode,” ARF1500 datasheet, Rev. E, Oct. 2008. 19. P. Piel, W. Burger, D. Burdeaux, and W. Brakensiek, “50 V RF LDMOS: An ideal RF power technology for ISM, broadcast, and radar applications,” 2008. [Online] Available: http://www.mwjournal.com/2008/DownloadablePDFs/FREESCALE50VLDMOS.pdf [Accessed: 6 Aug. 2010]. 20. Freescale Semiconductor, “RF power field effect transistor,” MRF6VP11KHR6 datasheet, Jan. 2008 [Revised April 2010]. 21. NXP, “LDMOS avionics radar power transistor,” BLA6H0912–500 datasheet, Mar. 2009 [Revised May 2010]. 22. M. Trivedi, P. Khandelwal, and K. Shenai, “Performance modeling of RF power MOSFET’s,” IEEE Trans. Electron Devices, vol. 46, no. 8, pp. 1794–1802, Aug. 1999. 23. P. H. Aaen, J. A. Pl´a, and J. Wood, Modeling and Characterization of RF and Microwave Power FETs, Cambridge University Press, 2007, pp. 21–22.

References

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24. P. H. Aaen, J. A. Pl´a, and J. Wood, Modeling and Characterization of RF and Microwave Power FETs, Cambridge University Press, 2007, p. 32. 25. P. H. Aaen, J. A. Pl´a, and J. Wood, Modeling and Characterization of RF and Microwave Power FETs, Cambridge University Press, 2007. 26. S. M. Sze, Physics of Semiconductor Devices, New York, NY: John Wiley & Sons, 1981. 27. M. C. Shine and F. M. d’Heurle, “Activation energy for electromigration in aluminum films alloyed with copper,” IBM J. Research Develop., vol. 15, no. 5, pp. 378–383, 1971. 28. J. R. Black, “Electromigration failure modes in aluminum metallization for semiconductor devices,” Proc. IEEE, vol. 57, no. 9, pp. 1587–1594, 1969. 29. S. Vaidya, T. T. Sheng, and A. K. Sinha, “Linewidth dependence of electromigration in evaporated Al-0.5%Cu,” Appl. Physics Lett., vol. 36, no. 6, pp. 464–466, 1980. 30. G. Bouisse, “High power silicon MMIC design for wireless base stations,” 30th European Microwave Conference, 2000, pp. 1–3. 31. Freescale Semiconductor, “RF LDMOS wideband integrated power amplifiers,” MW7IC915NT1 datasheet, Sept. 2009 [Revised Dec. 2009]. 32. G. Wang, L. Zhao, and M. Szymanowski, “A Doherty amplifier for TD-SCDMA base station applications based on a single packaged dual-path integrated LDMOS power transistor,” IEEE MTT-S Microw. Symp. Dig., pp. 1512–1515, 2010. 33. L. Zhao, G. Bigny, and J. Jones, “A 120 watt, two-stage, LDMOS power amplifier IC at 1.8 GHz for GSM/EDGE applications,” IEEE MTT-S Microw. Symp. Dig., pp. 1509–1512, 2008. 34. C. Cassan and P. Gola, “A 3.5 GHz 25 W silicon LDMOS RFIC power amplifier for WiMAX applications,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2007, pp. 87– 90. 35. C. D. Shih, J. Sjostrom, R. Bagger, P. Andersson, Y. Yinglei, G. Ma, Q. Chen, T. Aberg, “RF LDMOS power amplifier integrated circuits for cellular wireless base station applications,” IEEE MTT-S Microw. Symp. Dig., pp. 889–892, 2006. 36. Freescale Semiconductor, “RF LDMOS wideband integrated power amplifiers,” MW7IC18100NR1 datasheet, May 2007 [Revised Mar. 2009]. 37. Freescale Semiconductor, “RF LDMOS wideband integrated power amplifiers,” MW7IC3825NR1 datasheet, Nov. 2008.

2

GaAs FETs – physics, design, and models Rob Davis RFMD

2.1

Introduction The manufacture of Gallium Arsenide FET devices and integrated circuits is now a mature industry. The GaAs FET was first developed in the 1960s and 1970s [1], with the impetus to establish a manufacturing capability coming in the 1980s driven by governmental support – most notably the comprehensive “MIMIC” programme in the United States. In the intervening time the GaAs FET became the default solid-state device for all manner of RF and microwave applications. However, the position of the GaAs FET in this arena has not gone unchallenged. It was soon joined by the GaAs HBT which has dominated the cellular handset power amplifier market. The upper frequency limit of silicon LDMOS technology has steadily increased over recent years as its highly mature technology was further refined with the result that this technology currently dominates high-power RF applications below 3 GHz. More recently, gallium nitride devices join the fray. The GaN FET is a device technology of great promise that is steadily being made available by more vendors as its reliability is established. Initially, gallium nitride is also targeting the lower frequency bands but is capable of being developed for applications across the whole microwave bandwidth. For the higher millimetre-wave frequencies indium phosphide technology has a place. However, GaAs FET technology is proven, competent, mature, and remains a good choice for many applications including high-frequency power and high linearity. GaAs technology also has significant cost advantages over its nonsilicon competitors. The economies of scale that the cellular communications market has brought to GaAs technology has revolutionized the manufacture of GaAs products and has given rise to dramatic reductions in cost. It is in the area of continued cost reduction that the most significant new developments in GaAs device and associated technologies are focused. This chapter aims to introduce contemporary GaAs-based power FET technology. It is written with the perspective of the user of the technology in mind. The material properties and the pertinent device physics are reviewed and relevant concepts are recapped briefly as necessary. The device design issues are described followed by a section on fabrication with particular focus on low-cost manufacture. The chapter concludes with a discussion of device models for circuit design.

43

2.1 Introduction

Table 2.1 GaAs FET materials properties [2, 3] Parameter

Si

GaAs

Al0.22 Ga0.78 As

In0.2 Ga0.8 As

Units

Band gap, Eg Conduction band step, Ec (wrt AlGaAs) Electron mobility, μ (undoped) Electron mobility, μ (Nd = 3E17 cm–3 ) Lattice constant Breakdown field, EBR Thermal conductivity, κ

1.12

1.424 0.17

1.698 0

1.14 0.31

eV eV

1400

8500 4000 5.653 4 × 105 0.44

3600

6900

5.655 (4–6) × 105 0.2

5.734 (2–4) × 105 0.05

Cm/V.s Cm/V.s ˚ A V/cm W/cm.C

2.1.1

3 × 105 1.3

Properties of GaAs and related compounds GaAs and its related compounds offer inherently good electronic properties for microwave semiconductor devices. Key material properties of GaAs and two common partner materials – AlGaAs and InGaAs – are given in Table 2.1 with the corresponding values for silicon provided for reference. The GaAs-based materials shown have direct band-gaps and high electron mobilities. High mobility results in lower access resistance and rapid acceleration of channel electrons to their saturated velocity over a short distance. These are important benefits for microwave devices. Further performance enhancement may be engineered by combining compatible materials with differing band-gaps to form heterojunction devices. Suitable combinations of materials allow very effective device structures to be manufactured that can provide a high degree of spatial control of the charge thereby allowing device performance to be optimized. AlGaAs has a wider bandgap than GaAs or InGaAs material. The resulting step in the conduction band when AlGaAs is used in conjunction with GaAs or InGaAs channel layers allows the current to be confined in the narrower band-gap material. The step in the conduction band edge between AlGaAs and InGaAs can be engineered to be considerably greater than that between AlGaAs and GaAs, and therefore the former combination provides a significantly higher degree of electron confinement. Heterojunction devices are only possible if the desired material combinations are sufficiently compatible to allow defect free growth across the crystal interfaces. The AlGaAs crystal has the same face-centered cubic structural form as GaAs with a lattice constant that remains very close to that of GaAs for all fractions of aluminum composition. Consequently Alx Ga1–x As is crystallographically compatible for all values of mole fraction x. Unfortunately, high values of aluminum composition x are unattractive for other reasons. The first limiting factor is the emergence of a high density of deep levels called “DX centers” [4] which are formed for x ≥ 25% and their density rises sharply for values of x above this value. For the case of InGaAs, high indium fractions are desirable as the conduction band offset and mobility improve with increasing indium content. InGaAs also has the same crystal form as GaAs, however the indium atom is relatively large compared to gallium with the result that the lattice constant of Iny Ga1–y As increases

44

GaAs FETs – physics, design, and models

with mole-fraction y. Consequently, when a thin channel layer of InGaAs is grown on a GaAs or AlGaAs crystal the InGaAs layer structure pseudomorphically adopts the template of the host crystal and this gives rise to a strained (compressed) layer. Naturally, there is a limit to this behavior and for a given thickness of the Iny Ga1–y As layer there is a maximum value of y which should not be exceeded in order to maintain an acceptable degree of strain [5]. For thicknesses or mole fractions beyond the critical limit then the crystal strain will be relaxed by the generation of misfit dislocations. For useful AlGaAs/Iny Ga1–y As devices with a channel thickness in the region of 10 nm, the maximum useable value of y is of the order of 20–22%. The above issues therefore constrain the molecular compositions that are possible for practical AlGaAs/GaAs/InGaAs devices and the compositions of AlGaAs and InGaAs given in Table 2.1 are chosen to satisfy the constraints described above and are typical of those used in practical device structures. Although the bulk material data given in the table does not strictly apply to thin or strained-layer structures with adjacent heterojunction interfaces affecting electron transport, the data shown is indicative and useful in conveying the basic principles. A further important attribute for a semiconductor for microwave applications is the ability to engineer substrates with very high electrical resistivity in order that RF signals carried by the tracks on the finished device should experience low attenuation. GaAs is naturally blessed in this regard due to the relative ease with which the material may be made into a good insulator. High-purity GaAs naturally has a high resistivity and is deemed to be semi-insulating (SI). The high resistivity arises because the Fermi-level is pinned very deep in the forbidden band by a naturally occurring crystal defect known as “EL2” (Electron Level 2). EL2 is a near mid band-gap electron trap which effectively clamps the Fermi-level so deep that very few free electrons or holes are available for a meaningful current flow. The natural resistivity of pure GaAs is typically 106 –107 -cm at room temperature. Substrate manufacturers further refine the degree of insulation by incorporating very small amounts of carbon during the crystal growth process. Carbon is a p-type dopant in GaAs and this is used to counter-dope the slightly n-type nature of pure GaAs. By compensating the high density of deep-donor EL2 defects with a low concentration of shallow acceptors from the carbon doping, the resulting resistivity can be fine-tuned. A typical commercial SI GaAs substrate exhibits a resistivity >108 -cm at room temperature. Of course no semiconductor material is ideal and GaAs and its related compounds come with some natural drawbacks that must be accommodated in the design of successful products. Notable disadvantages of GaAs are a relatively low thermal conductivity and the absence of a native oxide or similar passivant. The former issue limits the ability of GaAs devices to dissipate heat through the substrate thereby making thermal design an area of particular attention in the design of high-power products. The second issue of imperfect passivation gives rise to “slow-state” phenomena. A number of alternative terms are used here to describe the mechanisms and their effects. The terms: “traps,” “deep-levels,” “surface-states,” and “dispersion” are all commonly used. They refer to an undesirable feature of semiconductor devices where crystalline imperfections result in electron or hole states that are of intermediate depth in the band-gap such that they

2.1 Introduction

45

interact with the free carriers at noticeable levels but at rates which are slow compared to the intended transistor response. The result is that, in addition to the desired fast response, there follows a secondary slow tail that can compromise the device performance in a variety of ways. Effective control of dispersive phenomena in GaAs devices took many years to adequately resolve. Both of these topics are addressed in more detail in the sections to follow.

2.1.2

The Schottky barrier gate and the MESFET A class of transistor which is very suitable for GaAs is the Schottky-gate FET. This form of FET is a natural choice for GaAs because, unlike the MOSFET, the Schottky-gate FET can accommodate an imperfectly passivated surface. A host of device variations have followed since but the primary device of the family is the MEtal-Semiconductor FET or MESFET. This is essentially a Schottky barrier gate between two ohmic contacts on a layer of n-type semiconductor that forms a conducting channel. A Schottky barrier is formed when a metal is brought into contact with a semiconductor surface. Given a suitable difference in material work-functions, charge redistribution in the semiconductor occurs which depletes the adjacent semiconductor region of its mobile carriers (in the manner of a one-sided p +-n junction). The extent of the depletion depth is controllable by the amount of bias across the junction, and by this means a bias applied to the Schottky gate will modulate the available charge and hence the current in a FET channel. The rate that the junction can control the current limits the frequency response of the device. The limiting processes here are the RC time-constant of the gate junction and the time for the carriers to travel along the channel. The relevant key material properties are the mobility and the saturated velocity, and in high-mobility materials such as the GaAs family then the saturated carrier velocity is the dominating factor.

2.1.3

The Pf 2 limit The maximum power obtainable from a transistor manufactured from a given semiconductor material is dependent on the frequency at which the device is required to operate. The relationship of power with frequency is an inverse-square law, sometimes referred to as the “Pf 2 = constant” limit [6]. The factors that determine this relationship are the breakdown field, the saturated carrier velocity, and the physical size of the device footprint. The rms power density, P’ , obtainable from a sinusoidally driven transistor with the peak current density Jmax and voltage swing of Vmin to Vmax is given by: P =

Jmax (Vmax − Vmin ) 8

(2.1)

For a FET with its speed limited by the electron transit-time τ , traveling at the saturated velocity vsat , over characteristic length L, with a peak voltage limited by the breakdown

46

GaAs FETs – physics, design, and models

field Eb , and approximating Vmin to zero, then: Jmax E br L 8 Jmax E br vsat τ = 8 Jmax E br vsat = 16π f T 1 ∝ fT

P =

(2.2) (2.3) (2.4) (2.5)

where fT is the cut-off frequency. This same analysis is used to define the Johnson figure of merit for a semiconductor material JFOM [7]: E br vsat . (2.6) 2π Returning to equation (2.4), Jmax is crudely of the order of 500 mA/mm for most flavours of GaAs power FET irrespective of operating frequency. However, the ability of a FET to deliver Jmax across the entire gate periphery of a device diminishes as the frequency increases. This is primarily due to de-phasing of the input signal along gate fingers and across the multigate manifolds. Consequently, the remote regions of the device are driven progressively out of phase compared to the region in the immediate vicinity of the gate terminal thereby resulting in a net reduction in current delivered to the drain. In order for the phasing effects to remain invariant the physical device width must be scaled inversely with the frequency thereby giving a further 1/f contribution. In combination with equation (2.5) the overall effect on the total power, P, is then: JFOM =

P∝

1 . f T2

(2.7)

Clearly this is a simplification which omits a host of other factors such as RC losses, matching effects and thermal considerations, but it does capture the dominant limiting processes for a well-designed microwave power FET. Validation of equation 2.5 is given in Figure 2.1 which shows the rated breakdown voltages versus process fT for a variety of commercially available power FET processes of the varieties described in the next section.

2.1.4

Types of GaAs FET Four key GaAs FET variants are compared in Figure 2.2. The first type, shown in Figure 2.2a is the MESFET consisting of a Schottky gate controlling the current in a simple uniformly-doped channel. The first devices were ion-implanted structures and this approach became the standard manufacturing technique for GaAs transistors for a number of years. The MESFET was gradually refined with enhancements that included optimizing the doping profiles, the use of epitaxially grown layers, and the development of recessed gate structures for enhanced breakdown. The advent of “bandgap engineering” introduced AlGaAs as a partner material. A variety of heterostructure

47

2.1 Introduction

0.15 μm P

100 0.15 μm P

0.15 μm P

fT GHz

80

0.15 μm P

0.25 μm P

60

0.25 μm P 0.25 μm P 0.25 μm P 0.3 μm P

40

0.5 μm P

0.5 μm P 0.5 μm M

0.5 μm M 0.5 μm P 0.5 μm H

20

0

5

10

15

20

25

30

BVgd V

Figure 2.1 Breakdown voltage – frequency relationship for commercial power FET processes

(M: MESFET, H: HFET, P: pHEMT).

Figure 2.2 Key GaAs FET device types; (a) metal-semiconductor FET (MESFET) (b) doped-

channel heterojunction FET (HFET); (c) high-electron mobility transistor (HEMT); (d) pseudomorphic high-electron mobility transistor (pHEMT).

48

GaAs FETs – physics, design, and models

FET (HFET) developments then followed. The most straightforward HFET, depicted in Figure 2.2b, uses a wide bandgap AlGaAs spacer layer that spaces the GaAs channel from the gate [8–10]. This structure constitutes an effective power device with excellent power and linearity performance [11]. The transconductance achievable from this structure is relatively modest, however a valuable attribute is the near constant value with gate bias [8, 12, 13] that is achievable which is important for improving linearity. A number of developments of the HFET have been investigated, typically involving the use of InGaP as an alternative wide bandgap layer and with InGaAs as the doped channel layer. Reference [14] summarizes the benefits and drawbacks of an InGaP barrier layer including its absence of DX centers and that it is less likely to suffer surface oxidation. However, it is also has a less advantageous conduction band alignment than AlGaAs, and its use as an HFET barrier layer has not found widespread use. The further device developments described here focus on improvement of the channel properties so as to enhance the frequency performance. A key development was the AlGaAs/GaAs high-electron mobility transistor (HEMT) or modulation doped FET (MODFET) [15]. These are equivalent names for a device structure shown in Figure 2.2c which avoids doping the channel directly and instead dopes the adjacent AlGaAs layer. Mobile electrons then populate the GaAs channel but, at low fields at least, suffer much less scattering as the doping impurities have been separated from the conduction channel. HEMTs of this type have been superseded by the pseudomorphic device discussed below, but the concept was a key stepping-stone in the development of the microwave FET. The pseudomorphic-HEMT (pHEMT) shown in Figure 2.2d is a significant enhancement of the HEMT that introduces the benefit of an InGaAs channel [16–18]. InGaAs is a narrow band-gap material with excellent electron transport properties. The first incarnation of the pHEMT was a single heterojunction device with an AlGaAs barrier and charge supply-layer above the InGaAs channel. As material growth quality improved, a second AlGaAs layer beneath the channel was added which provides better charge confinement and hence higher current capability. The principle of modulation doping for the double pHEMT is illustrated in Figure 2.3 which shows the idealized band diagram for a pHEMT channel. However, as described above, InGaAs possesses a larger lattice spacing than GaAs and AlGaAs which limits the indium mole fraction to around 20%. This is a fairly modest indium fraction with the result that the exceptionally high mobilities that are the norm in the higher indium composition channels of the lattice-matched In0.52 Al0.48 As/In0.53 Ga0.47 As/InP HEMT devices are not achieved in GaAs-based structures. However, it should be realized that the key device benefit achieved in AlGaAs/InGaAs devices comes not from the fundamental mobility of the channel material, but rather from the separation of the carriers in the channel from their dopant atoms in the adjacent wide band-gap region. In this respect the increased conduction band step introduced by the use of InGaAs for the channel layer is very beneficial. Although the innate channel mobility is not improved above pure GaAs, it is substantially improved above doped GaAs and in AlGaAs/InGaAs pHEMT devices channel mobilities exceeding 6000 cm2 /Vs are obtained. For a MESFET with a directly doped channel then the achieved mobilities would typically be less than half that of

2.1 Introduction

Doping plane

49

Doping plane

+

+

_

_

EF

High mobility channel

AlGaAs

InGaAs

AlGaAs

Figure 2.3 Idealized pHEMT band diagram and modulation doping principle.

the pHEMT value. This improvement is comfortably sufficient to ensure that the device speed of the pHEMT is not significantly limited by the channel mobility. The semiconductor band-diagrams that correspond to the key device types of Figure 2.2 are given in Figure 2.4. The diagrams were calculated using a public-domain Poisson-Schr¨odinger equation solver [19] and the figure shows the equilibrium conduction and valence band solutions for the zero-bias condition together with the resulting electron concentration. The four band diagrams highlight the differences in the nature of the confinement of the channel electrons (electron density n) in the region between the Schottky barrier of the gate terminal on the left-hand side and the mid band pinning of the Fermi-level of the insulating substrate that occurs off-scale on the right-hand side of the plots. For the MESFET of Figure 2.4a the channel charge distribution is essentially that of the bulk semiconductor layer with an effective width modulated by the extent of the depletion of the Schottky gate. The application of negative gate bias further increases the energy difference between the Fermi-level and the conduction band and thereby extends the gate depletion reducing the available charge in the channel. For the situation where a positive bias is applied to the gate then by the reverse process the depletion depth reduces and the MESFET channel widens towards the gate. The use of negative, zero and positive gate biases for a MEFSET structure are shown in Figure 2.5a. The HFET structure with a band diagram shown in Figure 2.4b differs from the previous case due to the AlGaAs spacer layer beneath the gate, and the mobile charge from the doping in this layer is transferred to the (also doped) channel where it is energetically favourable to remain. A change to the gate bias voltage modulates the depletion edge in the same manner as the MESFET, but now the presence of the heterojunction provides a constraint on the minimum depth of the depletion layer edge. As shown in Figure 2.5b, under positive gate bias conditions the electron concentration remains largely confined by the heterojunction barrier and so, unlike the MESFET, the upper extent of depletion layer edge is constrained and does not move significantly towards the gate. The HEMT

50

GaAs FETs – physics, design, and models

Ec

Ef

0.6

−0.5 0.4

−1.0

Ev 0.2

−2.0

0

50

(a)

100 150 Depth (nm)

1.0

0.8

Ef

0.6 0.4

−1.0

Ev 0.2

−1.5 −2.0 (c)

0

50

100 150 Depth (nm)

0.2

n 0

50

100 150 Depth (nm)

200

200

1.0 x1018

0.5

n (cm–3)

−0.5

Ev

1.0

Energy (eV)

Ec

0.6 0.4

−1.0

(b)

0.0

n

Ef −0.5

−2.0

200

1.0 x1018

0.5

0.0

−1.5

n

0.8

n (cm–3)

0.0

−1.5

Energy (eV)

0.5

0.8

n (cm–3)

Energy (eV)

Ec

Energy (eV)

0.5

1.0 x1018

1.0

Ec

0.8

Ef

0.6

0.0

n

−0.5

0.4

−1.0

Ev 0.2

−1.5 −2.0 (d)

n (cm–3)

1.0 x1018

1.0

0

50

100 150 Depth (nm)

200

Figure 2.4 Zero-bias band diagrams and electron densities for key GaAs FET device types; (a) metal-semiconductor FET (MESFET); (b) doped-channel heterojunction FET (HFET); (c) high-electron mobility transistor (HEMT); (d) pseudomorphic high-electron mobility transistor (pHEMT).

structure of Figure 2.4c has a similar AlGaAs/GaAs heterojunction to the HFET just discussed but with the difference that the GaAs region is undoped. The band-bending of the junction creates a small well that is populated with carriers from the doped AlGaAs region. The mobility of the channel is intended to be that of the intrinsic material as the scattering from the dopant ions is eliminated now that they are spatially separated from the path of the mobile electrons. However, the confinement capability of this modest well is quite limited and this structure is therefore not effective as a power device. This issue is resolved in the pHEMT of Figure 2.4d with an InGaAs channel. Here the deeper conduction band offset between AlGaAs and InGaAs provides a high degree of confinement and the use of a double heterojunction with doping provided from both the upper and lower AlGaAs barrier layers achieves a high sheet-charge density. Also employed

51

2.2 Power device physics

Ec

0.0

Ef

0.6

−0.5 0.4

−1.0

Ev 0.2

−1.5

(a)

n 0

50

100 150 Depth (nm)

200

1.0 x1018

0.5

0.8 n (cm–3)

Energy (eV)

Ec

Energy (eV)

0.5

−2.0

1.0

1.0 x1018

0.8

0.0

Ef

0.6

−0.5 0.4

−1.0

Ev 0.2

−1.5 −2.0 (b)

n (cm–3)

1.0

n 0

50

100 150 Depth (nm)

200

Figure 2.5 Effect of variation of gate bias on device band diagrams and electron density for (a)

MESFET and (b) HFET. Solid line is the zero gate bias condition, long dash is for reverse bias and short dash is for forward bias.

here is the use of delta doping. In conventional doping the dopant atoms are included uniformly in the crystal at modest concentrations. However, in delta-doping the silicon dopant atoms are deposited in a continuous thin layer just a few atoms deep. This has benefits to device operation in that the dopant atoms are all very close to the channel ensuring maximum transfer of electrons into the channel – the so-called “modulation efficiency.” A further benefit is that it is easier to manage the MBE growth reactor to dope in this way.

2.2

Power device physics

2.2.1

The device I–V characteristic and loadline An idealized I–V characteristic is shown in Figure 2.6. The knee voltage, Vknee , is the voltage where the current saturates. Below this point the device is a voltage controlled resistor and above Vknee the DC current is saturated and ideally is independent of drain voltage. The maximum current Imax is typically defined just above the knee voltage and is the maximum current the device can supply before the gate junction becomes forwardbiased and starts to draw gate current. Another key parameter for a power device is the breakdown voltage as this limits the peak voltage that the device load-line can swing up to. The pinch-off voltage Vp is the gate voltage required to turn-off the drain current (typically to a threshold value of order 1 mA/mm). The detailed behavior of the FET I–V characteristic is determined by the combination of the Schottky gate depletion dependence on the gate-channel potential and the velocity-field characteristic of the source-drain channel. In reality this is a complex and interdependent 2D problem. However, for submicron gate GaAs-based devices where the electron velocity saturates under the gate over much of the I–V space then a useful

52

GaAs FETs – physics, design, and models

Imax Vgs > 0 Idss Ids

Vgs = 0 QA

Vgs < 0

QB V knee

Vds

Vgs = Vp Vmax

Figure 2.6 Ideal FET DC I–V characteristic with class A and B loadlines.

simplified description can be considered. In this model the current is determined by the saturated electron velocity and the number of available carriers. The fraction of the maximum channel current that is available is determined by the extent that the gate depletion region extends down into the channel. An important benefit of the saturated velocity mode of device operation is that over the main part of I–V space the drain current is generally a more linear function of gate voltage. Good linear behavior may be pictorially observed from the family of Id –Vd curves that make up a device I–V graph having approximate equal spacing as Vg is varied. Such behavior is unlike the long-gate or “gradual channel” case of the traditional JFET where saturation is a low-field and constant mobility process resulting in a square-law dependence of drain current on gate voltage [3, 20]. It is readily apparent that a good power device has high peak current Imax , a high breakdown capability, a low Vknee and equally spaced curves on the I–V characteristic. Figure 2.6 illustrates the maximum power class A and class B load-lines that may be supported on the idealized I–V characteristic. The class A loadline is the simplest to understand and the figure shows the I–V locus swinging from the peak current value Imax and minimum voltage value Vknee to a maximum voltage at zero current limited by the device breakdown. The resultant quiescent bias point is QA . The maximum output power for the idealized class A situation is given by equation (2.1). The class B loadline is achieved by reducing the operating current to bias point QB . The same load resistance is required and a similar maximum power is delivered but with higher efficiency achieved due to a reduced DC dissipation. For a real device the I–V characteristic departs from the ideal in a number of important ways. Figure 2.7 highlights some key features of a more realistic DC I–V characteristic which would be observed using a slow-sweep curve tracer. The figure illustrates “thermal droop” where self-heating of the device causes a reduction of electron velocity and mobility. The spacing of the lines of constant gate voltage is also no longer ideal and exhibits compression at the limits of the gate voltage range.

2.2 Power device physics

53

Imax

Vgs > 0

Idss Ids

Vgs = 0 Vgs < 0

Vknee

BVds

Vds

Figure 2.7 Practical FET DC I–V characteristic exhibiting breakdown, thermal droop, and

transconductance compression. 100

DC Q A (6V, 0V) Q AB (6V, -0.3V) Q B (6V, -0.6V)

80

60 Id mA

QA

40

Q AB

20

0

QB

0

1

2

3

4

5

6

7

Vd V

Figure 2.8 Measured pulsed I–V characteristic for 0.25 μm pHEMT process at class A, AB, and B bias points.

2.2.2

The dynamic I–V characteristic A further departure from the ideal characteristic occurs when the dynamic response is considered. Figure 2.8 shows typical pulsed I–V characteristics that have been measured with a commercial system [21, 22]. A set of dynamic I–V plots are overlaid onto a conventional DC I–V measurement. In the pulsed case the device is biased at quiescent bias points indicated on the figure and short, low-duty cycle pulses from this bias point are then used to explore the I–V plane and map out the characteristic. The bias point should be chosen to be typical of the intended operating point with the aim that the measured dynamic I–V will replicate the RF behavior of the device. As is apparent in Figure 2.8 the dynamic behavior differs significantly from the static case. The difference

54

GaAs FETs – physics, design, and models

is, for the most part, due to the presence of slow traps in the semiconductor. Traps are deep-level states that can capture and retain electrons or holes for extended periods. The possible causes and locations are numerous [23–26] and include traps at the un-gated semiconductor surface and the substrate interface, DX levels in AlGaAs, and free ions in passivating materials. A concise overview of the phenomena for both GaAs and GaN devices is given in reference [27]. The traps are energy states that have energies sufficiently deep into the semiconductor forbidden band that the likelihood of a carrier interacting with the state is relatively small and when a carrier does occupy such a state then a further low probability event is needed in order for it to be released again. The result is that the lifetime in a deep-level state can be quite long, and time constants of microseconds to milliseconds are commonplace. The impact of the trapped charge in the deep states is that the associated field affects the passage of the free carriers in the channel thereby modifying the device characteristic. Because the capture and release time constants of the traps are very long compared to the period of a microwave signal, the RF (carrier) signal and trap occupancy do not directly interact. However, the trap occupancy is affected by the mean bias condition giving rise to the situation that the dynamic I–V changes slightly as the mean bias position changes. A useful way to think of this is that there isn’t a unique and definitive I–V characteristic for a particular FET, but rather there is a slightly modified one for every mean bias condition. A helpful physical model is that of the field associated with the trapped charge acting as a slowly varying “virtual gate” that modifies the effect of the physical gate. A particular area of concern for trapping effects is the semiconductor surface. Without a suitable passivant material there are inevitably a large number of surface states present. Indeed, it is worth noting that the density of available surface states is typically comparable with the intended doping of the device channel. It therefore becomes an important device design task to minimize their impact on the device performance. This is achieved by such measures as keeping the etched surface area to a minimum, maximizing the distance of such areas to the channel and the use of charge-screening layers to isolate the channel from changes to the surface potential. In contemporary optimized FET structures the trapping effects have been addressed to a substantial degree. Improved materials growth quality, improved wafer processing techniques, and advances in device design techniques have reduced the density of available states and mitigated their impact on the device response. Nevertheless, discernable slow-state effects are the norm and these effects have an impact that can limit the device performance and introduce difficulties in device characterization and modeling.

2.2.3

The consequences of trapping effects The physical processes described above give rise to a multitude of observable device effects to be minimized by the device designer and accommodated by the circuit designer. The effects are summarized in the following paragraphs. Reduced output power: For devices operating as an amplifier and biased as such, the resulting equilibrium trapping state reduces the peak device current due to increased surface depletion and increases the effective knee voltage by increasing the dynamic

2.2 Power device physics

55

Id

Time (a) Gate lag

Time (b) Drain lag

Figure 2.9 Typical GaAs FET gate and drain lag responses; (a) gate lag; (b) drain lag.

channel access resistances. These modifications to the device I–V are illustrated in Figure 2.8 and reduce the maximum output power that a device can deliver. Gm and gds dispersion: Measurements of device transconductance (gm = dId /dVgs ) and output conductance (gds = dId /dVds ) with frequency are observed to undergo a transition from their DC values, and this variation with frequency is called dispersion [25, 26, 28]. The transition frequency range is typically in the 1 kHz to 1 MHz range with the transconductance decreasing from the DC value and the output conductance increasing from the DC value. Historically, dispersion measurements were a primary assessment tool for device trapping effects before pulsed I–V assessment came to the fore. For contemporary GaAs power devices transconductance dispersion is usually small and the dispersion of the output conductance is the dominant phenomena. This is clearly observed in FET DC I–V characteristics such as Figure 2.8. The spacing of the lines of constant gate voltage has remained largely invariant indicating minimal difference in transconductance. However the increase in the slopes for the pulsed characteristic demonstrates the increased output conductance experienced by a dynamic stimulus. It should be realized, however, that the difference between the DC and dynamic I–V slopes does not indicate that slow-states have compromised the output conductance for the RF signal. It is more accurate to view the dynamic I–V measurement as revealing the underlying “true” output conductance that is obtainable from the short gate structures that are typically employed in GaAs-based devices. For the DC case, the aforementioned underlying I–V is modified by changes in the equilibrium trap occupations which evolve with the (slowly varying) bias voltage in such a manner so as to supplement the action of the gate and so reduce the resulting output conductance. The mechanism can be visualized such that as the drain voltage is increased then the amount of trapped charge in the vicinity of the gate also increases and the field associated with the trapped charge acts in concert with that of the Schottky gate bias thereby helping to suppress the increase in drain current that would otherwise occur. Gate and drain lag: Gate and drain lag are terms that describe the delayed response of the drain current to changes in the gate and drain voltages, respectively [26, 29–32]. Typical gate lag and drain lag responses are illustrated in Figure 2.9 and show how the dominant fast response is followed by a slow tail. The tail can persist for timescales

56

GaAs FETs – physics, design, and models

ranging from a few microseconds to milliseconds depending on the detail of the device construction and the fabrication techniques employed. The plots relate to the same physical test as is performed in the pulsed I–V plot of Figure 2.8; however, the x-axis on the plot is now time rather than drain voltage and the traces show the time evolution of just one sample point on that I–V plot. With gate-lag the drain voltage is held constant and the gate voltage is stepped from the quiescent value to the required sample point, and with drain lag the gate voltage is held constant and the drain voltage is stepped. Memory effects: In addition to the modifications to the device characteristics described so far, the dispersion mechanism also results in hysteresis in the device response, or in other words the device can exhibit a memory of a recently applied stimulus. As discussed, the trapped carrier population is a function of the mean bias condition. For a highfrequency continuous-wave signal where the period of the RF is short with respect to the trap time-constant then an equilibrium trap occupation will be achieved and a stable dynamic device characteristic is observed. However, for low-frequency signals or, more likely, an RF carrier modulated with a modulation frequency that is comparable with the trap time-constant, then the trap occupation can be influenced by this low-frequency variation. The result is that the RF characteristic can be subtly modified by the lower frequency component of the signal thereby giving a dependence on the recent history. Of course this is a familiar problem for all semiconductor devices even if trapping mechanisms were to be completely controlled as thermal time constants have similar consequences. The impact of trapping effects on a modulated signal is simulated in reference [33]. Inaccuracy in large-signal models: Traditional device models are based on I–V characteristics measured at DC. However, as has been shown, the trapping effects give rise to dynamic I–Vs which are noticeably different from the static one. This means that models which simply use the static characteristic do not accurately predict the device performance. Invariably, the real device will provide less power and exhibit less gain than the DC-derived model. Techniques for the generation of improved large-signal models are addressed later in the chapter. Increased breakdown voltage: So far the list has given a series of detrimental effects that arise from the presence of surface states. However, they do have an important beneficial impact on breakdown voltage. As will be discussed in more detail in the next section, the associated surface charge located in parallel with the channel has the positive benefit of assisting to spread the electric field in the gate-drain region over a longer distance thereby reducing the peak field developed and hence increasing the device breakdown voltage. Kink effect: The list ends with a phenomenon that has long been observed where traces on the I–V characteristic can exhibit a kink to a higher drain current as if the gate bias was suddenly adjusted higher as the drain voltage is swept. Similar effects have been reported in various kinds of semiconductor transistor, such as silicon MOSFETs, GaAs-MESFETs, doped channel HFETs, AlGaAs/InGaAs-HEMTs, and InAlAs/InGaAs-HEMTs [34]. Various mechanisms have been explored and it is clear that there are a number of different kink-effect processes that may be present depending on the detailed device

2.2 Power device physics

57

D BVgd BVds

G BVgs

S Figure 2.10 Breakdown voltage definitions.

construction. It is possible to observe mechanisms that affect the DC characteristic but are not observed at RF [35], while for other structures they may be observed also or exclusively in the dynamic characteristic [34, 36]. The possible mechanisms that may be involved include field ionization of traps where an increase in the drain voltage induces release of trapped electrons thereby allowing the associated channel depletion to lessen [34, 37]. Other processes involve the presence of hole charge generated by impact ionization. Here a build up of hole charge at the source end of the gate can give rise to a parasitic bipolar effect that can cause current injection thereby reducing the effective source resistance [38]. It is also possible that associated change in the channel potential reduces the effective pinch-off voltage [39]. A further mechanism suggested by 2D simulation is for impact ionization generated holes to interact with and partially discharge surface electron traps thereby widening the channel [40]. Other simulations indicate a possible contribution from redistribution of the 2D electric field when the lateral extension of gate depletion reaches the edge of the recess [36].

2.2.4

Device breakdown The three breakdown conditions generally quoted for FETs are the Gate-Source, GateDrain and Drain-Source breakdown voltages BVgs , BVgd , and BVds , respectively, as illustrated in Figure 2.10. The typical definition employed is the voltage for which a current of 1 mA/mm of gate width is observed. BVgs and BVgd are so-called two-terminal tests (i.e., with the third terminal floating) and, with the notation used here, are negative. In power devices the gate is usually positioned asymmetrically to optimize the gate-drain breakdown value. BVds is a three-terminal test with the gate bias set to a sufficiently negative value so as to ensure that the device is pinched off. BVds is positive. It is common for only two-terminal tests to be quoted on data-sheets or in wafer acceptance criteria. However, the three-terminal drain-source breakdown is also an important parameter, particularly so for power devices, as this configuration corresponds to how the device is actually used. Different physical mechanisms are generally observed for the breakdown processes experienced under two and three-terminal conditions with the result that BVds can be significantly less than might be expected from a simple consideration of the

58

GaAs FETs – physics, design, and models

combination of the gate-drain breakdown and the applied gate voltage (i.e., Vgs -BVgd ) [41].

2.2.5

Breakdown mechanisms and optimization Significant attention has been paid to the optimization of breakdown performance in order to optimize output power, and breakdown performance for power devices has been developed to the point that power GaAs FET devices are usually thermally limited rather than being limited by device breakdown. A number of physical processes are involved in the evolution of the breakdown process and depend on the precise device construction and on the operation of the device. The key processes described here are [42–47]: r thermionic field emission (TFE) over the reverse-biased gate barrier; r tunneling through the gate barrier which narrows as the device is heavily reversebiased; r impact ionization in the channel; r parasitic bipolar effect; r electric field spreading due to the surface potential. These processes can all operate in concert to give a variety of interesting behaviors. A typical evolution of a breakdown event begins in a high-field low-current condition with increased gate-drain leakage caused by field-emission of current over the reverse-biased gate-drain barrier. It is normal for the field to be so high that the barrier becomes thinned which causes the field-emission to be enhanced by quantum-mechanical tunneling. Energetic electrons can then find themselves injected into the high-field channel with excess energy. The electrons will relax their energy by various means and one possibility is impact ionization where electron-hole pairs are created caused by collisions with the lattice. Impact ionization is self-reinforcing in a high-field channel as the electron-hole pairs produced can go on to seed other ionization events in an avalanche multiplication process. Breakdown tends to be a fairly gradual process at first as the applied voltage is increased and steadily over several volts the total breakdown current becomes progressively dominated by the impact avalanche component. Detailed studies analyzing this behavior in GaAs FETs have used the differing temperature dependence of the TFE and impact ionization processes to identify the relative contributions.1 The picture so far then is that of energetic electrons defeating the gate barrier, seeding impact ionization and the breakdown current running away with a positive feedback mechanism. However, this is not necessarily quite the end of the story. On some devices it is possible to observe a “snap-back” effect where, as a certain current threshold is crossed, the device can no-longer support the breakdown voltage resulting in the breakdown characteristic of Figure 2.11. In this event then the voltage collapses to a low value and the device current rises markedly [48]. This process may or may not be fatal depending on the device 1

TFE has a positive temperature coefficient which is to say the current over the barrier increases with temperature [42, 46]. Conversely, in GaAs devices, the temperature dependence of the ionisation coefficients acts in the opposite sense.

59

Id

2.2 Power device physics

Snap-back

Impact ionization TFE/Tunnelling

Vd Figure 2.11 Breakdown snap-back caused by a parasitic bipolar effect.

and the circuit. The mechanism giving rise to the snapback is a by-product of impact ionization where the resulting equilibrium hole concentration can induce a “parasitic bipolar effect” (PBE). Once created, the ionized holes can follow a number of paths: They can be collected by the gate terminal and add to the gate current, they can escape into the substrate, or they can flow to the source. A common understanding of the parasitic bipolar effect is that the holes collecting in the substrate act as a parasitic back gate and have the effect of opening the channel “from the back” [49, 50]. However, in a heterojunction FET holes tend to be confined in the channel by the valence band well and in this case may not readily flow into the source contact or substrate. Instead they will drift to the source region and an equilibrium hole charge is developed there. This localized positive charge favours injection of electrons from the source contact into the channel thereby inducing an increased drain current by another means [49]. Parasitic bipolar effects are well known in silicon devices [51, 52] but appear less so in the GaAs community.

2.2.6

Comments on GaAs FET breakdown ratings GaAs FET circuits are often designed to operate quite close to the transistor rated breakdown limits with safety margins less than are typically employed with other technologies. A number of factors make this a safe thing to do. The nature of GaAs FET breakdown is such that it is typically quite gentle in its onset and results in significant circuit performance reduction before device degradation is observed [43]. Also, the typical dominant aging mechanism of devices operating under high-field conditions is a hot-electron induced surface degradation. The surface damage leads to a subsequent increase in trapped surface charge causing increased spreading of the electric field and hence an increase in the breakdown voltage [53]. This so-called “breakdown walkout” provides a fail-safe mechanism where the failure process effectively hardens the device against further degradation.

60

GaAs FETs – physics, design, and models

Lg

Cgd

Rg Cgs

Rd

+

Ld

Rds

--

Cds

Ri

gm

Rs

gm = gm0.e

−jωτ

Ls

Figure 2.12 Common GaAs FET equivalent circuit network.

A further relevant phenomenon is the observation that the RF breakdown of GaAs FETs can be frequently higher than their DC breakdown data would suggest [54]. The literature is not comprehensive but the perception of devices safely operating at values not commensurate with their DC breakdown values is a common one. A popular explanation is that of avalanche delay [55], which can inhibit the onset of breakdown because the period of a microwave signal is typically comparable with the characteristic delays of the avalanche process. An attempt to quantify the effect was given by Shrikov [56] who measured a modest one volt enhancement to the drain-source breakdown. Snap-back effects (if present) may also be too slow to respond to the RF signal which in that case could be expected to give an apparent RF breakdown enhancement.

2.2.7

The FET equivalent circuit The usual small-signal equivalent circuit network used to represent a GaAs FET is shown in Figure 2.12. The prime elements are the voltage-dependent drain current generator of transconductance gm0 and the gate capacitance Cgs across which the controlling voltage is developed. The remaining elements are unavoidable parasitic components whose presence degrades the device performance and so whose values are minimized as much as possible in the device design and the fabrication approaches employed. Figure 2.13 illustrates the mapping of the equivalent circuit onto the physical structure. The parasitics which are commonly particularly significant are the shunt feedback capacitance Cgd and the access resistances Rg , Rs , and Rd . The gate and source resistances Rg and Rs compromise gain by reducing the fraction of the input signal that reaches the intrinsic gate. The source and drain Rs and Rd compromise output power and efficiency. The source inductance, Ls , is often a critically important parasitic which, together with Rs , gives rise to series feedback compromising device gain. However, the value of Ls is dominated by the interconnection network including the via to ground and therefore not shown on the cross-section view of Figure 2.13. The remaining parasitics usually have a lesser impact though can still be significant.

2.2 Power device physics

S

G

n+

D n+

Rg

Ledge

Ledge Rs

Cgs Cgd Ri

Channel

61

Rd

gm Rds

Substrate

Cds

Figure 2.13 Correspondence of GaAs FET physical structure and equivalent circuit network.

An area of particular note in the mapping of the equivalent circuit is the network of elements used to model the depletion region. The depletion region is a single entity that delineates a single region of space-charge. However, it is accessed by all three device terminals and so in the equivalent circuit the depletion region must therefore have a connection to the three terminals. This is achieved in the lumped model by the use of two capacitance elements Cgs and Cgd . The gate-source capacitance, Cgs , connects across the depletion region from the gate metal to channel forming the main contributor to the input capacitance. The gate-drain capacitance, Cgd , connects from the gate metal across to the drain-side of the depletion region and forms a shunt feedback capacitance. Modulation of gate depletion region edge requires charge to be added to or removed from the depletion region. In the low-field region this process is dielectric relaxation [57] modeled by the Cgs -Ri arrangement where the gate-charging resistance, Ri , represents the nondepleted low-field channel resistance of the channel under the gate. In the highfield region the modulation of the depletion region edge is limited by the finite saturated velocity of the channel carriers limiting the rate that carriers can be supplied or be swept away. There is therefore a time delay given by the product of the length of the saturated region and the carrier velocity that limits the speed of this process and this gives rise to a delay term,τ , for the current generator equivalent circuit element.

2.2.8

Device gain and figures of merit The key gain quantities for a microwave FET are illustrated in Figure 2.14 which shows a set of typical commonly used gain curves for a pHEMT device. The most straightforward microwave gain quantity is the power gain in a 50  system. In Figure 2.14 this is shown as S21 . This curve shows a one-pole response dominated by the 50  source impedance and the device input capacitance. Once above the 3 dB corner frequency S21 falls at 6 dB/octave. In order to achieve a useful gain performance the device must be presented with more appropriate terminating impedances. The remaining curves on the plot are the

GaAs FETs – physics, design, and models

U

Gain (dB)

62

MSG

S21

h21

MAG

log(Frequency Hz)

fT

fmax

Figure 2.14 Microwave gain curves and figures of merit.

quantities generally employed to indicate what performance is achievable from a device for specific terminating conditions. h21 : The hybrid parameter h21 is the current gain into a short-circuit load. The intersection of this curve with the unity gain axis is a key device figure of merit called the transition frequency, fT which is discussed in more detail below. Gmax: The Gmax curve is the composite plot of the maximum available gain and maximum stable gain curves (MAG and MSG, respectively). MAG is the gain obtained when the input and output are both simultaneously matched for optimum gain. This quantity may only be determined when the device is unconditionally stable. Where it is possible that a combination of source and load impedances will cause the device to oscillate then MAG is undefined and so instead the MSG is plotted. MSG provides the theoretical gain obtained immediately before oscillation occurs and has a slope of 3 dB/octave. The slope of MAG is of the order of 6 dB/octave but varies due to the variation of the optimal termination conditions which are frequency dependent. Figure 2.14 shows just one transition frequency between MSG and MAG. In highperformance FETs it is quite common for there to be a further transition at higher frequencies back to MSG as the device becomes conditionally stable again. In practice, Gmax can be thought of as the best gain obtainable but its interpretation is complicated by the conditional stability issue. U: A somewhat theoretical gain quantity often favoured by device specialists is the Unilateralized gain “U” [58], also known as Mason’s invariant gain [59]. For this quantity the feedback has been perfectly neutralized to give a gain measure that is free from complications of the effects of conditional stability. fT and fmax : Two popular figures of merit for RF devices are fT and fmax . They assist in the ready assimilation of a device’s performance and to allow convenient comparisons of different devices. The transition frequency fT is the unity gain frequency of h21 – the

2.3 Device design

63

frequency for which the current gain of the device has fallen to 0 dB. fT is a useful and reasonably unambiguous figure of merit that is convenient to measure and relates directly to the primary equivalent circuit elements that determine the device RF gain. The elements concerned are the intrinsic transconductance of the gate gm0 and the associated capacitance Cgs that limits the rate at which the input voltage may be varied. The usual approximate expression for fT is given in equation (2.8). fT ∼

gm0 2π (C gs + C gd )

(2.8)

A significant weakness of fT as an indicator of device performance is that it neglects other important parasitics, and in particular takes no account of device input resistance. This is because h21 is the current gain for the case of an input current generator with infinite output conductance. It is therefore quite possible for a device with a high fT rating to actually have a relatively poor power gain. Clearly however, a device chosen for a power amplifier should have a low input resistance and high power gain. A figure of merit that addresses this requirement is fmax , the so-called “maximum frequency of oscillation.” This parameter is the frequency for which the power gains U and Gmax have fallen to 0 dB, as a power gain of unity is the minimum gain required for a device to be able to oscillate (see Appendix 2.1 and reference [60]). The expression for fmax can be determined for the network of Figure 2.12 [61] and is given in equation (2.9) which illustrates the relative significance of the various parasitic components. f max =



fT

2 (Rg + Rs + Ri )/Rds + 2π f T Rg C gd

0.5

(2.9)

A difficulty with fmax is that there is no universally adopted approach to its determination and it is commonly overestimated. This is discussed in Appendix 2.1 where recommended methods for the practical determination of fT and fmax are described.

2.3

Device design

2.3.1

Power device design The process of optimizing a power device comprises three main steps: (a) designing the basic FET device structure, (b) designing the power cell where a set of gates are assembled to form a stackable unit, and (c) forming a composite device from a set of cells to provide a device with the required power for a given requirement.

2.3.2

FET channel and recess design Here the task is essentially to select the FET type and gate length appropriate for the operating frequency and to optimize the current density capability and breakdown voltage without unduly compromising the other competing specifications such as gain and linearity. Key areas of attention are the epi-design and the gate recess.

64

GaAs FETs – physics, design, and models

Epi-layer design: GaAs FET epitaxial layer structures vary in complexity from the simplest uniformly-doped MESFETs [62], through reasonably straightforward multilayer designs for HFETs [8], to complex many-layer quantum-well structures for pHEMTs [63]. In uniformly-doped MESFETs the epi-layer design choices are fairly limited. High power requires high current which is achieved by a high doping density and/or a thick channel. Both of these factors have limits. For the case of doping density, then as this parameter is increased the breakdown voltage falls due to the increased electric field that is developed. In addition, the semiconductor mobility is degraded due to increased scattering associated with the dopant atoms. Alternatively, as the channel thickness is increased then, for a given gate length, the output resistance falls and this can compromise the device’s ability to deliver current into the desired load resistance. To prevent this problem the gate aspect ratio (the ratio of gate length to channel depth) should be maintained to be of the order of five or more in order to ensure a satisfactory output resistance. The aspect ratio constraint presents no issues for longer gate devices but for higher frequency applications requiring submicron gate lengths, then the restriction on channel depth forces high levels of channel doping to achieve the desired current density thereby resulting in a compromised breakdown voltage and undesirable channel mobility. MESFETs with tailored doping designs are employed with the aim of achieving improved device characteristics such as linearity and noise. More ideal device performance is achieved by concentrating the doping deeper into the device with the objective of achieving, for example, a step-doped or similar profile. A desirable outcome from this measure is to introduce less variation in depletion depth as the channel is modulated thereby resulting in a more constant device transconductance and gate capacitance. However, this benefit comes inevitably at a cost of reduced current density for a given peak doping and gate length. Such devices therefore tend to have lower current capabilities than uniformly doped FETs. The limiting case for a step-doped profile is the HEMT which seeks to restrict the current flow to a narrow plane at a fixed depth into the semiconductor. The HEMT achieves this while being substantially free from the mobility degradation associated with increased doping densities as described above for the MESFET. This is because in the case of the HEMT the current-carrying channel is physically separated from the donor ions and so much higher doping levels can be used without adversely impacting the mobility. GaAs-based HEMT structures typically achieve sheet-charge densities above ˚ would correspond to an 1.5 × 1012 cm−2 which, for channel depths of order 100 A, 20 −3 equivalent bulk-doping density in excess of 1 × 10 cm . Even if such a bulk-doping density was a practical proposition (which it isn’t as this density is considerably greater than the solubility limit of the n-type silicon dopant in GaAs), the mobility would be enormously degraded and not be more than a few hundred V/cm2 s at best. In the HEMT the doping limit now becomes that for which the associated electrons can be effectively contained in the heterojunction channel. For the AlGaAs/GaAs HEMT the difference in band-gaps between the two materials is relatively modest with a commensurately limited degree of charge confinement. Consequently this device has a modest peak current capability. However, as shown in Table 2.1 the AlGaAs/InGaAs pHEMT has

2.3 Device design

Gate metal Inner recess

65

Outer recess

n+

n+ Ledge Cap layer Channel

Figure 2.15 GaAs Power FET recess structure.

a much more substantial band-gap difference with the result that the pHEMT device variant allows a high current density of order 500 mA/mm to be maintained for all practical gate-lengths. The gate-recess design: A most significant advance that allowed the GaAs FET to be developed into a useful power device was the development and optimization of the double gate-recess. The earlier devices had a simple single recess that was typically created by simply etching into the channel until the desired current was achieved. At this point the gate metallization would be deposited within the recessed region. The breakdown voltage is enhanced by increasing the width of the recess, thereby giving an increased separation between the gate metal and the drain n + contact region and reducing the peak field. However, in practice the increased expanse of free surface typically results in poor device performance with significantly reduced current and slow-state effects. The solution for this problem is the double recess [64–67] depicted in Figure 2.15. Here the gate is deposited in a small inner recess that lies within a larger outer one. In this construction the outer recess is larger on the drain side to provide the gate depletion with room to extend towards the drain as the gate-drain voltage is increased thereby reducing the peak electric field developed. In contrast to the single recess structure, the variations in surface depletion on the extended etched surface caused by changes in trap occupations now usefully attenuated by virtue of increased physical separation from the channel. This attenuation is generally further enhanced by the inclusion of moderate levels of n-type doping which act as a charge screen. Considerable attention has been paid to optimizing GaAs FET breakdown in the recent past. A significant driver has been cellular base-station PAs requiring a few hundred watts of peak power at 0.8–2.1 GHz. For a technology that hitherto operated power amplifiers with a typical drain bias of the order of 6–8 V, this application provided a significant challenge. Initial attention focused on optimization of the design of the epi-layers and of gate-recess structure. Figure 2.16 shows the impact of one design

GaAs FETs – physics, design, and models

50

BVdg BVds

40 Breakdown Voltage (V)

66

30

20

10

0 0.0

0.5

1.0

1.5

2.0

2.5

3.0

Lgd (micron)

Figure 2.16 Breakdown voltage dependence of gate-drain voltage separation.

variable, namely the length from the gate to the edge of the outer recess on the drain side (Lgd ), on breakdown voltage for a 0.5 μm gate power device. The two-terminal breakdown BVgd is seen to be readily controlled by the size of the recess but the three-terminal breakdown BVds exhibits a more limited dependence. The figure provides a reminder that even though BVgd is the normally quoted breakdown voltage measurement, in reality the device operates in a three-terminal condition and for a power amplifier the drain-source breakdown voltage, BVds cannot be neglected. Fortunately, in practice, commercially available device power processes are appropriately designed and the quoted BVgd data is generally a good indicator of the breakdown capability in a power amplifier configuration. Optimization of the recess gave a significant step forward in increasing the breakdown voltage but its ability to spread the field is limited. To improve further a greater degree of field spreading is required. Some attempts were made to employ reduced surface field p-layers as used to great effect in silicon LDMOS [69, 70], but most focus has been on the use of field-plate electrodes located in the gate-drain recess area [68]. Field-plates: As discussed above, the charge trapped in deep-levels on the surface of the gate recess provides a naturally occurring assistance in the field spreading. The use of field-plates makes it possible to engineer a more substantial effect and this has been an area of significant attention for higher voltage GaAs devices. In this context a field-plate is an extra electrode positioned on an insulating layer in the high-field gate-drain recess region. Its function is to provide a controlled potential that acts to suppress the peak field at the gate edge. The simplest construction is the gate-connected

2.3 Device design

67

field-plate investigated by a number of groups [71–75]. As the normal shape for a power FET gate is a T-shape (as discussed in Section 2.3.3), the simplest form of field-plate construction is merely an extension of the top of normal T-shaped gate in the direction of the drain to form a so-called -gate (“gamma-gate”). The field-plate approach can be very effective in increasing the breakdown field, and research work achieved device operation at and beyond a drain bias voltage of 28 V. Unfortunately however, the impact on the device gain is significant [76]. Both the gate-source and gatedrain capacitances are compromised making the technique unattractive for frequencies above L band. A more recent development has been the source-connected field-plate [77]. This configuration requires a more complex manufacturing process but has the great benefit of shielding the gate-drain coupling thereby reducing Cgd and actually improving Gmax. The input capacitance is still significantly affected and the device fT is consequently compromised, however for applications such as cellular communications for which the technology was targeted then this additional input capacitance can be accounted for in the input matching circuit. Significant effort was deployed on fieldplate technology for GaAs devices and with notable success. However, the efforts were largely overtaken by wideband gap technology such as GaN which has now become the preferred technology for high-voltage RF FET devices.

2.3.3

Power cell design Gate width: Power FET cells invariably require as much gate periphery as possible and a key factor which inhibits increasing the width2 of the gate finger is the impact of the cumulative loss and delay of the gate signal as it travels along the gate electrode [78–80]. The gate electrode is depicted in Figure 2.17a which shows a discretized model of a loaded transmission line. The gate metal is modeled by the incremental series resistance and inductance elements dRg and dLg with the associated gate capacitance elements dCg . The gate voltage waveform applied to the gate finger propagates along the structure and is progressively attenuated as it travels thereby reducing the overall device gain. In addition the finite time to traverse the structure further degrades the signal by introducing a progressive phase delay that adds to the overall signal degradation. In order to improve matters attention must be paid to the gate cross-section as the short gate length required for fast transit along the channel length would otherwise result in a reduced cross-sectional area thereby providing high series resistance and inductance along the finger width. The solution widely employed as shown in Figure 2.15 is to form a T-shaped gate to improve the propagation along the gate metal while still maintaining a short gate contact length for good gain performance. Power cell manifold issues: Having optimized the unit finger the next task is to design an assembly of unit fingers suitably combined so as to achieve an optimal power performance that has scaled well with respect to the innate performance of the unit finger [79–81]. Figure 2.17(b) illustrates the principle for an example network of four 2

By convention, the width of a gate is the long dimension perpendicular to the channel direction and the length of a gate is the dimension in the direction of channel current flow.

68

GaAs FETs – physics, design, and models

dRg Gate Terminal

dLg

dRg dLg

dCg

dRg dLg

dCg

dCg

(a)

Drain Gate

(b)

Figure 2.17 Power FET cell; (a) gate finger equivalent circuit; (b) gate manifold with four fingers.

fingers combined to make a modest multifinger cell and shows the fingers connected by an assembly of short transmission lines. As fingers are added then the overall device gain is further impaired due to the successive phase delay contributions experienced by the additional fingers. At first thought it might be imagined that this phase difference could be corrected by the use of an alternative layout which collected the drain currents with compensating delays in the output circuit. However, this neglects the impact of the high capacitive loading on the input network by the gate capacitance resulting in this network being relatively slow compared to the output network. The high impedance of the drain side of the device means that the output current contributions are collected with relatively small phase differences compared to the cumulative phase differences in the input that build up from the interfinger and along-finger delays. Another approach to maintain the gain would be to minimize the finger–finger phase delay by designing the device with fingers as close together as possible. Unfortunately the heat generated in power FETs is usually substantial and so the design freedom here is usually quite limited in order to maintain an acceptable channel temperature required for reliable device operation. Common-lead inductance: As the gate periphery is increased to achieve higher current capability then the importance of the inductance of the source connection becomes

2.3 Device design

D G

(a)

D

D G

69

G

(b)

(c)

Figure 2.18 GaAs FET power-cell layout variants; (a) gate-side source vias for high packing density; (b) source-bridge for reduced inductance of smaller cells; (c) individually via’d source stripes for highest frequency performance.

increasingly significant. The negative feedback generated by the common-lead inductance can be a significant factor reducing the gain of the power cell and close attention to minimizing its value is often required. A very common topology for power FETs is shown in Figure 2.18a which provides two vias per cell. The vias are located to the side of the device and connection to the source fingers is made by an air-bridge over the gate manifold. This layout is very effective for power cells as it allows multiple cells to be efficiently stacked in a row for a high density of fingers. The disadvantage of this configuration is that it results in a relatively long path from the via to each source finger. Higher gain can be achieved with the “source-stitched” layout of Figure 2.18b. Here the vias are located adjacent to the first and last unit fingers and connected to the source stripes by a low inductance bridged feed. The improvement is particularly significant for a modest numbers of gate stripes, however the via location does not make efficient use of die area for arrays of many fingers. Figure 2.18c makes use of recent improvements in via technology and the ability to fabricate narrow width slotted vias. Narrow via width allows source fingers to have directly attached ground vias and the slot shape allows the amount of via wall presented to the device source connection to be maximized keeping the source inductance per finger to a minimum. In general, the style for Figure 2.18a is most efficient on semiconductor area but styles (b) and (c) have gain benefits that can be attractive for higher frequencies. Many of the factors in the design of the power-cell are amenable to mathematical analysis and modeling [82]. However, the pragmatic and most accurate approach to the determination of the scaling behavior is merely to design a mask set of device variants that covers the required set of layout styles, gate widths, number of fingers per cell and gate spacings, and then fabricate the devices and characterize them. The results of such an exercise for a 0.5 μm gate power FET process are illustrated in Figures 2.19a and b. Figure 2.19a shows the fT of the power cell as the unit gate width is varied for a range of gates per cell. Figure 2.19b shows the corresponding curves for fmax . In general, the performance reduction with unit gate width is driven by the combination of increased gate finger resistance and increased via inductance/mm of gate periphery. The reduction with number of gates is dominated by the via inductance/mm of gate periphery.

GaAs FETs – physics, design, and models

25

8 gates 10 gates 12 gates 14 gates

20

fT (GHz)

15

10

5

0 100

200

300

400

500

Unit gate width (micron)

(a)

50

8 gates 10 gates 12 gates 14 gates

40

fmax (GHz)

70

30

20

10

0 100

(b)

200

300

400

500

Unit gate width (micron)

Figure 2.19 GaAs FET power-cell performance; (a) fT as a function of unit gate width and number

of gates; (b) fmax as a function of unit gate width and number of gates.

2.3 Device design

2.3.4

71

Power cell combination Power-cells are required to be combined to form a composite high-power device. Of course, combining has to be done in a manner that takes into consideration the same gain degradation issues that arose in the design of the power cell. Furthermore, the approach has to contend with the issue that the input impedance of the cell is likely to be challengingly small. The simplest approach, commonly done for modest frequencies and impedance levels, is to combine the required number of cells, provide each one with appropriate sets of gate and drain bond pads, and leave the end-user free to combine in the circuit as required. The individual cells can have common gate and drain bus bars, or be wholly separate cells depending on the size of the cell and the approach used to achieve satisfactory stability. Some examples of the variety of power device layouts used in GaAs device technology are given in Figure 2.20. The devices shown range from 200 mm discrete devices able to provide output powers of 100 W at 2 GHz to mm-wave power cells with a power capability of 0.5 W. The die can be supplied either packaged or as bare die. The latter approach provides the highest performance as it avoids the introduction of significant package parasitics in a sensitive part of the circuit. However, the assembly costs are higher and the circuit module has to provide a higher degree of environmental protection. The circuit designer will face the task of stabilizing, matching and combining the cells to achieve the required power amplifier performance. At this level the device combination cannot be treated as a “lumped” problem and is typically done with a corporate combing approach using a distributed network [83, 84]. One to three levels of corporate combining can be considered which combine 2, 4, or 8 die, respectively. Unfortunately the losses associated with each level of the combination build up and so the benefit diminishes. Generally up to two levels of combination are effective but going beyond three levels is unlikely to be worthwhile. In order to achieve optimal performance from a packaged power device then it is common to perform at least some of the impedance matching and combining functions “inboard” of the package parasitics. By including matching circuitry at the device terminals the impact of the package is incurred at a less sensitive part of the circuit. This approach is very common for high-power devices [85–88], so much so that the name internally matched FET (or IMFET) has emerged as almost a device type in its own right. It is normal in IMFET products to combine the functions of prematching with power combining techniques in order to combine the power of multiple devices. An illustration of the typical circuit topology used to achieve this is shown in Figure 2.21. Another aspect that can make large power die difficult to deal with is their propensity to oscillate. Their large periphery gives huge low-frequency gain which must be accomodated. Even more problematic is the risk of odd-mode oscillation which can arise due to loops in the combiner networks. Internally matching provides the opportunity to substantially alleviate this problem for the customer by including suitable internal stabilization techniques within the package [89]. A further option is to provide internal control of the harmonic terminating impedances as required for high-efficiency amplifier modes [90, 91].

72

GaAs FETs – physics, design, and models

(f)

(g)

(e)

(a)

(b)

(c)

(d)

Figure 2.20 Power FET photos: (a) 200 mm multicell L-band power FET; (b) 60 mm power L-band FET; (c) C-band power FET; (d) power combination in X-band power MMIC; (e) conventional power cell evaluation structure (BCB coated for mechanical handling protection); (f) source bridge power cell evaluation structure; (g) electron microscope image of power cell (evaporated second metal).

2.3.5

Thermal design Thermal design is a critical part of a power FET design process. The junction temperature must be maintained within operational limits in order to ensure reliable operation. Ohmic contacts to GaAs are observed to degrade at elevated temperatures, but normally the dominant degradation mechanism is gate-sinking. Here the gate metal diffuses into the semiconductor thereby moving the effective location of the Schottky junction and so reducing the device current [92]. A typical requirement is to maintain the junction temperature below 150 ◦ C in order to achieve a predicted operating life of 1 million hours. Gate sinking is discussed in greater detail in Section 10.7.1. A difficulty encountered in this endeavor is the level of uncertainty in the determination of the channel temperature. The available methods all have significant potential sources of error. Commonly available measurement methods are infra-red imaging, use of the

2.3 Device design

73

D G

Figure 2.21 Corporate combining and prematching circuit topology used in IMFETs.

liquid crystal transition temperature, or use of the gate junction as a thermometer [93– 99]. Infra-red imaging is relatively convenient for surface temperature measurement, but FETs present difficulties as the gate-drain area that needs to be resolved is small with respect to the infrared wavelength. The liquid crystal approach is limited in that it can only indicate when the transition temperature threshold is crossed rather returning a value for the peak temperature for a given operating condition. The electrical approach inevitably returns a measure of the average temperature across the device rather than the peak temperature and, for the traditional switched approach of reference [98], error is introduced by the delay involved in switching from the active operating mode to passive sensing mode. Newer measurement techniques being developed are Raman spectroscopy [100] and scanning thermal microscopy [101]. A recent advance to the electrical approach has also been published that uses the gate junction state directly in an admirably simple manner obviating the need to switch the gate into a sensing mode [99]. In this latter approach a change to the base-plate temperature is compensated by an adjustment to the drain voltage in order to return the gate junction thermometer to its original condition before the base temperature was adjusted. From this measurement a value for the mean thermal resistance can be obtained. An alternative approach is to use thermal simulation. The detailed device structure and the thermal properties of the materials used are well characterized and 3D thermal simulation tools are comfortably able to model structures to the required degree of problem complexity [102–104]. There are also numerous approximate methods in common usage. Typical techniques are 2D analytic solutions or basic numerical methods limited to linear thermal conductivities. Such approaches should be treated with some caution [102] as the approximations involved frequently do not apply to GaAs FET devices, and in the case of power FETs the thermal operating window available can provide significant design constraints with minimal margin for error. Table 2.2 shows the results of a series of calculations of thermal resistance for a microwave power FET that illustrates the variation in predicted values for different calculation methods and for different levels of physical detail that are included. It is also important to realize that the there is the potential for inaccuracy with even the most comprehensive simulation tool. For example, there remain some unknowns such as the contributions of thermal interfaces [100, 104], and usually some uncertainty over the precise construction of the thermal problem. It is clear then that whatever the approach

74

GaAs FETs – physics, design, and models

Table 2.2 Comparison of peak thermal resistance calculations for a 4 × 120 μm GaAs FET cell with a junction temperature Tj of 150 ◦ C on 100 μm substrates mounted with 15 μm epoxy (the linear analytic cases use an empirical approximation to include the contribution of the epoxy) Rth C/W (Tj ∼ 150 ◦ C)

Calculation method 2D linear analytic [107] 2D linear analytic with end-effect included 3D linear semianalytic (TXYZ) [107] 3D linear finite difference 3D nonlinear finite difference 3D nonlinear finite difference with surface metallization 3D nonlinear semianalytic [105] 3D nonlinear finite difference with surface metallization and plated vias

240 206 184 208 237 221 226 213

Table 2.3 Simulated thermal resistances (◦ C/W) for central finger (RC ) and outer finger (RO ) compared against measured values (100 ◦ C liquid crystal transition temperature) for packaged RFMD discrete FET devices [105] Device type

RC

RO

(RC + RO )/2

Measured

FPD1500SOT89 FPD1500DFN FPD2250SOT89 FPD2250DFN FPD3000SOT89

75 70 53 50 41

54 51 37 34 28

64.5 60.5 45 42 34.5

60 60 48 40 35

used there is scope for significant error. A good approach then is to support thermal simulations with experimental evidence of cases that can be accurately measured. An example of this is given in Table 2.3 where the temperature predicted by simulation is compared to 100 ◦ C liquid crystal transition temperature for a series of packaged discrete FET devices [105]. A further, particularly detailed comparison is given in reference [108] where a special device was constructed with one finger of a power cell array connected as a passive thermometer. A sensible and pragmatic way to mitigate any residual systematic error is to employ the same technique in the thermal design of product as was used by the fabrication facility in the generation of the device life data.

2.4

Device fabrication

2.4.1

Overview In this section GaAs device fabrication techniques are described from the starting point of the manufacture of blank wafers with suitable active layers on the surface of an insulating GaAs substrate. For a MESFET a simple doping scheme comprising a channel layer

2.4 Device fabrication

75

accessed by a highly doped upper contact layer is all that is required. MESFET layers can be created either by using ion-implantation of dopant ions into the substrate, or by epitaxial growth of layers onto the substrate. For more complex devices such as HFETs and HEMTs then epitaxial growth is required. These layers are a suitable combination of GaAs and AlGaAs/InGaAs partner layers doped as necessary to construct the required devices. The grown wafers are then transferred into a wafer processing facility where the semiconductor layers are patterned, implanted, etched, metallized and coated as required to fashion the desired devices and circuits. In the following discussion the focus will be on epitaxially grown layers, now the more common approach for GaAs-based FET device manufacture. In commercial devices, epitaxial layers are grown by molecular beam epitaxy (MBE) or metal organic chemical vapour deposition (MOCVD). In MBE, a substrate is heated under high vacuum and beams of the appropriate proportions of the constituent atoms are directed at the substrates, condensing on the surface to form very high-quality layers of the required compounds. The layers can be deposited with very high precision with layer thickness control down to a few atomic layers. After growth the layers are inspected for accuracy, typically assessing the sheet charge and layer thicknesses, the molecular compositions of the AlGaAs/InGaAs ternary layers and the quality of the surface. In MOCVD the constituent atoms are delivered to the surface of a heated substrate by means of suitable precursor organic gas molecules that chemically decompose at the heated surface and deposit the desired atoms at the surface layer by layer. Typical source gases are trimethylgallium, trimethylaluminum, trimethylindium and arsine with a hydrogen carrier gas. The crystal composition is controlled by adjusting the relative proportions of the gas flow over the surface.

2.4.2

Key process steps Upon receipt of the epi-wafers device processing can commence. To form the devices a set of process modules are developed that perform functions such as creation of ohmic contacts, recess etching, Schottky gate deposition, metal interconnect deposition, insulating film deposition and etching, substrate thinning, and via etching. These modules employ a set of process steps that are optimized to work in concert and are characterized and maintained to meet the necessary manufacturing tolerances. The menu of process steps that are typically employed are described in the following paragraphs [109, 110]. Lithography: All of the wafer processing operations need to be selectively applied in controlled areas. This is achieved by lithography – most commonly photolithography. Here a suitable photosensitive “resist” film is patterned with an image that has previously been created on a photographic glass plate called a mask. The resist film is spun onto the wafer, exposed with the required image and then chemically developed. For so-called “positive” resist the unexposed area remains intact thereby shielding the covered region from a subsequent etching or metal deposition process step. By this means the various device features may be patterned as required. Alternatively, “negative resist” can be used. This behaves in the opposite sense so that the exposed area remains after being developed.

76

GaAs FETs – physics, design, and models

Three types of lithography are in common usage for GaAs wafer processing. The simplest is contact printing. Here, after the photoresist has been applied, the technique is to align the mask to existing features previously fabricated, clamp the mask to the wafer and then expose the assembly to light. This is a low-cost approach capable of feature sizes down to 0.5 μm and is quite suitable for small-volume manufacture. It does however suffer from mask wear and registration accuracy issues across the wafer. The resolution is fundamentally limited by diffraction of the incident light source and for higher resolution other approaches are necessary. For GaAs FETs the highest resolution requirement is for the gate metal which is usually of the order of 0.5 μm or less. Traditionally, electron-beam lithography has been the solution adopted for fine geometry gate definition below 0.3 μm. Here the gate pattern is created by steering an energetic electron beam to the desired areas and thereby exposing a suitable resist material in those regions. This eliminates the optical diffraction problem (the electron de Broglie wavelength for kV electrons is below 0.1 nm), and gives a resolution limited by the scattering in the resist and backscattering from the wafer. For research devices E-beam gate lengths have been driven down to 0.05 μm or less. In commercial devices E-beam gates are typically available down to 0.15 μm. The chief disadvantages of E-beam lithography are complexity and throughput. The serial nature of the writing process means the exposure times are lengthy. The third lithographic technique in common usage is the optical stepper. Here the pattern is imaged on a portion of the wafer with refractive optics. The mask is usually enlarged, typically 5 times greater than the final image and the pattern, or shot, is stepped and repeated to cover the wafer. Shot sizes are typically up to the order of 20 × 20 mm2 . The use of optical steppers is the dominant approach for high-volume, high-yield processing. The precision of the stepper optics is extremely stringent and requires associated control of vibration and temperature, compensation for air pressure variation coupled with precise alignment tools, stage-stepping control, and complex focusing systems capable of adapting to lens aberration. Liftoff: In the patterning of metals on GaAs devices much use is made of a procedure called “liftoff.” This is a different approach to that used in silicon processes where the aluminum tracks are formed by depositing the metal film, applying and patterning the photoresist and then etching back where the metal is not required. The situation is different for GaAs devices which make use of gold tracks and composite metal stacks which are not readily etched. The approach for these metals is to apply and pattern the resist before the metal is deposited and therefore to use the resist to control where the metal is deposited. When the resist is dissolved, the unwanted metal that was deposited on the resist film is lifted off and removed. To facilitate this process the edge profile of the resist apertures is fashioned by various means so as to have an overhang or “lip” and the metal is evaporated with a near normal incidence to the wafer so that a clean break in the metal film is created by the shadowing effect of the overhang. Device isolation: Wafers with epitaxially grown active device layers require that the individual devices on the wafer be isolated from each other. This is either done using mesa etching or ion implantation. With mesa etching, islands of active material are retained and the regions of interconnecting epi-layers are removed by an etching process. Mesa etching is an effective approach that avoids the need for expensive implantation

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77

equipment. However, it introduces undesirable surface relief and introduces increased gate leakage at the point where the gate metal stripe rises up the side of the mesa and crosses the active layer. Any surface relief is unwanted from a processing perspective as it inhibits uniform photo-resist coverage for subsequent process stages, and steps tend to compromise the integrity of any metal tracks that have to go over them. With ion implantation the active device regions are protected with thick photo-resist and the areas to be isolated are deliberately damaged by an energetic beam of ions thereby rendering the exposed regions to have high resistivity. For ion-implanted MESFETs then device isolation may not be necessary as the doping for the device active areas can be done selectively in the regions where it is required. In this case implantation is serving the opposite purpose to the isolation case above. Silicon donor ions are implanted with energies to achieve the required depth profile. The wafer is then heated so that the damage done to the crystal structure during implantation is annealed out and the dopant ions incorporated into the crystal lattice in order to activate them as donors. Alternatively, a blanket doping implant over the whole wafer can be used and the active areas are then isolated either with an isolation implant or mesa etching as for epi-wafers. Ohmic contacts: The function of an ohmic contact is to make a low-resistance electrical connection from the metal tracks to the semiconductor active layers. Ohmic contacts to GaAs are made by the use of a nickel, gold and germanium metal stack deposited on to a heavily doped GaAs contact layer and annealed at approximately 400 ◦ C. The essential purpose is to reduce the thickness and effective height of the Schottky barrier that forms at metal-semiconductor junctions to such an extent that the behavior is ohmic. The exact mechanism remains somewhat elusive but involves the generation of a highly doped surface layer of germanium substituting for gallium in the crystal lattice. The nickel component first acts as a wetting agent for the GeAu but it is also believed to enhance the diffusion of germanium into GaAs [109]. Gate Etch: Prior to the gate formation a recess is etched into the semiconductor material to remove the highly-doped contact material above the channel. Historically, this was an “etch-to-current” activity where the etch rate would be carefully calibrated and a timed etch would be used to target the desired recess depth. Subsequent verification by testing the drain current of the etched structure would result in the wafer being returned for a top-up etch if the measured current was too high. Such crudity was eliminated with the advent of “etch-stops” where the etch chemistries are chosen so as to be selective to the various heterojunction layers. The heterojunctions may therefore be used to stop the etch process at precise depths with high accuracy and, crucially, the accuracy is maintained over the whole wafer. This advance was key to the development of high-yield manufacture and the use of large area wafers. For example, reference [111] demonstrates that the use of an AlGaAs etch-stop layer for a GaAs MESFET reduced the process standard deviation for Idss from 25% to 5%. Layers that are already present in the epi-stack for their electrical function may be employed if appropriate [111] or specific etch-stop layers may be added to the epitaxy design that are there purely for control of the etch process. Alternative dedicated etch-stop layers are AlAs [112] and InGaP [113].

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There are two main approaches to GaAs etching: “wet” or “dry.” Wet etchant solutions consist of an oxidizing agent to oxidize the surface and a second component to dissolve the oxide. Commonly used etches able to provide etch selectivity with AlGaAs are dilute hydrogen peroxide/ammonia, hydrogen peroxide/citric acid and hydrogen peroxide/succinic acid [111, 114, 115]. Dry etching uses plasma chemistries involving a combination of chlorine and fluorine radicals in concert with energetic ion bombardment [115, 116, 117]. The chlorine produces the etching reaction and the fluorine produces an etch-stop reaction with aluminum due to the formation of a nonvolatile aluminum fluoride protective layer on the surface. Both approaches have relative advantages and disadvantages. A wet chemical etch provides a low-damage surface and for this reason is often preferred. However, wet etching is isotropic and so has less dimensional control. Dry etching has the advantage of good directionality giving a high degree of dimensional control, but this can come at a cost of some surface damage from the ion bombardment. However, it is found to be possible to tailor the dry etch recipe so as to minimize the ion energy towards the end of the etch process and suitably control the degree of etch damage [116]. Therefore both wet and dry etches can be used for GaAs FET gate etching and both are in use in commercial processes. Schottky gate electrode: The gate structure must make a good Schottky barrier contact to the semiconductor, one that is stable over the life of the device and that provides a low resistance along the gate finger. The Schottky barrier height is largely pinned by surfacestates to about 0.7 eV rather than controlled by the relationship of the semiconductor and gate metal work-functions as normally described in introductory text books. Therefore in principle many metals will provide adequate Schottky barriers. In reality, considerations such as metal adhesion and thermal stability provide the practical selection criteria. The result is that there is a choice of two approaches to the formation of the gate electrode: an evaporated gold-based gate or a sputtered refractory metal approach [118, 119]. The most common technique is to use an evaporated gate typically using a titanium-platinumgold (Ti-Pt-Au) metal stack. Here the titanium layer ensures good adhesion, the gold provides low feed resistance and the intervening platinum layer acts as a diffusion barrier keeping the gold safely from diffusing into the gate junction. The second approach is the use of a wholly refractory metal approach, generally using tungsten-silicide or titanium tungsten. The Ti-Pt-Au approach is a simpler technology however refractory gates are more thermally stable. This is advantageous not just for device operation but also for device fabrication. The thermal resilience of a refractory gate allows the gate metal to be deposited before the ohmic contact metal thereby making the critical gate lithography much easier and allowing the ohmic metal to be self-aligned to the gate [120]. With the conventional Ti-Pt-Au stack the ohmic contact anneal step must be completed prior to the gate metal deposition. For power FETs it is generally the case that in order to obtain high power it is essential to be able to operate with as wide a device finger as possible. A limiting factor here is the gate metal resistance and so power FETs usually use some form of ‘T’-shaped gate where the top of the gate metal is widened to reduce the resistance along the stripe. In the case of E-beam gates the “T” is achieved by a multilevel resist approach, typically employing PMMA (polymethyl methacrylate) thermoplastic resist materials in

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a typically bi- or tri-layer scheme to produce a mushroom-shaped profile in the resist comprising a narrow stem and a wider T or mushroom top. This is typically achieved by using layers of resist that differ in their sensitivity to the developer solution and to use the more sensitive material for the definition of the T-top. A final thin layer may be employed to create a lip for improved liftoff. Following the creation of the mushroom cross-section in the resist the gate metal stack is deposited over the wafer and the resist developed away lifting off the unwanted metal and leaving the gate structures behind. An example of a developed PMMA resist cross-section that provides a good illustration of the approach is given in reference [121]. The result of the multilayer approach is to create the desired “T” shape with minimized gate resistance and capacitance. The use of stepper-based lithography introduces a different method of forming the gate. Here the approach is to form the T-gate with the T-top supported on a dielectric layer [122–124]. The gate-support layer is deposited, a T-stem is defined and etched in this dielectric layer and the T-top is defined in photo-resist on the top. Gate metal is then evaporated to form a gate of the required shape thereby giving the resistance benefit required. The drawback relative to the E-beam gate process described previously is that the gate capacitance is increased slightly due to a higher degree of dielectric loading associated with the dielectric layer supporting the “T” and typically, a larger T-top overlap area. Dielectric layers: A number of dielectric layers are required for a variety of purposes including protective coatings, supporting metal track cross-overs, and for the formation of integrated capacitors. A commonly used material for GaAs processes is silicon nitride deposited using plasma-enhanced chemical vapour deposition (PE-CVD). This technique is compatible with the modest thermal constraints of GaAs device manufacture. In this approach silicon nitride films are deposited during a plasma-enhanced reaction of silane, ammonia and nitrogen gases. Careful process optimization is required for the successful deposition of device films, with particular attention to film stress and plasma-induced damage. Film stress is a significant factor for GaAs devices as the material is piezo-electric [125]. The plasma is typically generated with a 13.56 MHz RF power source and the resulting film from this arrangement is stressed and typically tensile in nature. Control of the stress from tensile to compressive can be achieved by a number of methods including adjustment of gas composition or the addition of a component of lower frequency power, typically 1–2 MHz [125, 126]. The latter approach introduces a high energy ion-bombardment of the growing silicon nitride film and this results in a controllable change to the resultant stress state. Although effective in controlling the film stress, ion bombardment employed in the vicinity of a GaAs surface introduces unacceptable degradation of the surface thereby introducing a tradeoff of film-stress against surface degradation. However, devices are usually fabricated with a number of film layers and a good degree of stress control can be achieved by designing the stack of composite layers appropriately so that the overall film stress is acceptable and the surface damage arising from the near-surface layers is minimal. In order to pattern a silicon nitride film after deposition it must be etched and either dry or wet etching approaches may be used. Dry etching is preferred due to its superior dimensional control. It is typically performed using a sulphur hexafluoride (SF6 ) plasma diluted in helium in order to achieve a

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controllable etch rate. Wet etching of silicon nitride is uncommon but can be performed using a buffered Hydrofluoric acid etch. Interconnect metals: Usually, two levels of interconnect metal are required in order to make connections between devices and other components and external bond-pads. The first level metal is generally evaporated gold and is generally deposited to a thickness of 1–2 μm. A second level metal is needed so that one track may cross-over another, for capacitor formation, and to provide thicker tracks in order to carry high currents. Second metal tracks are usually electro-plated gold onto a sputtered seed layer. More recently some manufacturers are now employing evaporated second metal rather than using electroplating [127]. This can have cost advantages particularly for high volumes as the highly uniform finish of evaporated metal is more easily compatible with automatic visual inspection tools. Backside processing: GaAs RF technology is usually of the microstrip variety requiring a ground-plane on the backside of the wafer. Connection to the ground plane is made by through-wafer vias. Processing of the underside of the wafer therefore consists of thinning, via etching and metal deposition. The completed front surface is protected and then temporarily adhered to a supporting carrier with a wax or photoresist. The wafer is then ground down to the desired thickness. For power devices the final thickness requirement is normally governed by the thermal design and is typically in the range 50–120 μm. Through-wafer via etching is performed using directional dry etching. The backside is then metallized using electroplated gold onto a sputtered seed layer. Process Monitoring: In order to evaluate the performance of each wafer and to provide data for statistical control of the process, a number of standardized test cells are included on each wafer. The cells are called process control monitor (PCM) cells or “the coupon.” The number used per wafer varies and depends on the wafer size, the maturity of the process and local policies and can vary from ten to a hundred. The PCM contains both structures to assess individual process steps and standard devices which are evaluated at various points in the process flow. Structures are included to assess the contacts, the efficacy of the isolation, the quality of each of the various metal and dielectric layers, and any GaAs or thin-film resistors that might also be in the process. These and the standard device cells are typically assessed after the gate has been deposited, after the front-face has been completed, and finally at the end of the process. The device tests performed while the device is in the production line concentrate on cardinal parameters including the pinch-off voltage, drain current for Vg = 0 V (Idss ), maximum drain current, breakdown voltage, diode built-in voltage and ideality, gate leakage and the DC transconductance. These are monitored with a view to obtaining constant feedback on the process so as to keep it in control and for identifying occasional errant wafers so that they can be scrapped as soon as possible to eliminate the cost of further processing. Upon completion of the wafers, a standard PCM FET structure designed to be suitable for on-wafer RF testing is usually assessed with some level of RF test. This typically consists of a measurement of S-parameters at a specific standard bias point from which an indication of RF performance is obtained by extraction of fT , fmax , or Gmax. Some manufacturers also perform equivalent circuit extraction in order to be able to monitor key equivalent circuit parameters.

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At the end of the production line a set of the most critical parameters that have been tested are collated and used in the wafer acceptance test (“WAT”). For this test a defined fraction of the PCM structures have to be within the specification limits for the wafer to be acceptable to go on for visual inspection and release to the customer.

2.4.3

Low-cost GaAs device fabrication The recent increase in GaAs production volumes and the cost pressures of the cellular handset market that have driven that volume have revolutionized GaAs device manufacture and the capabilities that can be brought to bear. Key developments here are an increase of GaAs wafer diameter from 4 to 6 and the use of stepper-based lithography with its inherent benefits of high throughput, uniformity and yield. As discussed in the Schottky gate electrode part of Section 2.4.2, dielectrically defined gate techniques used in stepper-based processes inevitably have higher parasitic gate capacitance than unsupported approaches used by e-beam processes. However, the reduction of performance is acceptable for many applications and the benefits of lower cost and greater uniformity are substantial. Furthermore, the higher degree of die encapsulation required in order to provide the level of environmental protection that is increasingly demanded anyway involves an increased amount of encapsulating dielectric material. In this case, the fact that dielectric-defined gate processes start with a higher degree of dielectric loading becomes less of an issue. The substantial advantages of 6 stepper-based wafer fabrication has therefore led to the major manufacturers adopting this approach and offering optically defined gate technologies [128–130]. The initial use of optical steppers was for 0.5 μm applications and made use of relatively affordable “i-line” steppers (365 nm wavelength). This technology is suitable for devices with fT ’s of the order of 25 GHz and for applications to X band. More recently processes have been developed to be able to fabricate smaller gates for higher performance devices. The options here are to use a deep-UV stepper or one of a number of “gate-shrink” approaches. With a deep-UV stepper a shorter wavelength of 248 nm is employed to directly image gates down to the order of 0.25 μm [131]. Alternatively, or in combination, one of the gate-shrink approaches can be employed to pattern the gate dimension below the resolution of the stepper. Techniques that have been successfully employed include the use of dielectric sidewall spacers [120], chemical shrink [132], reflowed resist [133, 134] and the use of phase-shift mask technology[135]. With these techniques stepper-based approaches can be employed in production at and below 0.15 μm.

2.4.4

Packaging Packages are used for ease of handing the fragile die and for environmental protection. The range of available package types is extensive reflecting diverse requirements that stretch from DC to millimetre wave. The packaging solutions range from plastic molded structures for high-volume applications to hermetically sealed ceramic housings with high-quality integral heat sinks for the highest performance products. Figure 2.22 shows a selection of packages used for GaAs power devices.

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AF

SOT89

(a)

(b)

QFN

AS

(c)

(d)

Figure 2.22 Typical power FET packages; (a) SOT89; (b) ceramic flange mount; (c) leaded ceramic surface mount; (d) leadless plastic surface mount (QFN).

Traditionally, the packaging route for microwave power transistors was essentially limited to the metal-ceramic air-cavity package consisting of an alumina housing brazed onto a metal flange such as the AF package in Figure 2.22. This approach provides good heat dissipation properties, a good RF ground, a well-controlled parasitic environment, and hermetic sealing options. This approach remains the highest performance packaging option but this is achieved at a significant cost. Not only is the package cost the most expensive component in a packaged power transistor part, they are also expensive to assemble and the resulting components are not amenable to high-volume circuit board manufacturing processes. The high cost of conventional ceramic packaging encourages the development of alternative technologies and a sustained focus has been on the development of plastic packages [136]. The use of plastic packages introduces a number of difficulties compared to ceramic technology including increased ground inductance, substantial dielectric loading, and thermal dissipation and expansion issues. Established over-molded plastic packages such as the SOT89 style equipped with a reasonably heavy lead-frame are employed for modest power and frequency applications. More demanding situations have driven appropriate technology developments. Silicon LDMOS devices targeting

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(a)

(b)

Figure 2.23 QFN package cross-section; (a) over-molded package; (b) air-cavity package.

frequencies up to the order of 2 GHz have pursued over-molded plastic encapsulation of devices mounted on an integral copper heat spreader. Such solutions are suitable for in excess of 100 W [137]. However, GaAs devices generally address higher frequency and lower power applications. Surface mount packages, such as the AS and QFN styles in Figure 2.22 are desirable for high-volume assembly requirements. Leaded and leadless surface mount ceramic packages are well established and plastic surface mount techniques are currently receiving much attention. Of particular note is the example of the QFN package (Quad Flat No leads, JEDEC standard MO220 [138]) of which a 3 × 3 mm 12-pad style is shown in Figure 2.22. This package standard was originally developed for low-speed general electronics, however its construction is amenable for development for microwave frequencies and QFN packages have found application for a range of microwave devices and MMIC circuits. Standard plastic QFN packages such as is depicted in Figure 2.23a are used in applications up to 18 GHz and approximately 1 W dissipation. Developments have included power variants with a heavier duty lead frame and employing solder die attach [139, 140]. For higher frequencies the use of alternative materials and constructions are attractive in order to achieve lower dielectric loading. Significant attention has been paid to organic polymers which have superior microwave properties to plastic [141, 142]. Millimetre-wave capable approaches have been developed using multilayer approaches with air cavities as illustrated in Figure 2.23(b) [143]. Ceramic implementations are also pursued for higher frequency applications due to the superior mechanical precision of those materials and 40 GHz operation has been demonstrated [144]. An activity of significant interest for low-cost manufacturing is the optimal route to achieving acceptable environmental protection. Traditional ceramic packages were able to provide high levels of hermeticity. Alternatively, the environmental protection could be provided at the module level. However, the continual drive for lower manufacturing cost now increasingly excludes such options and recent work has focused on the development of hermetic low-cost packages [143] or adequate encapsulation at the die level. The latter objective is achieved by ensuring that the finished semiconductor die survive standard

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tests for hermeticity and are sufficiently robust that the encapsulation survives the mechanical handling encountered in the plastic packaging process. Two standard tests here are the “85/85 THB” and “HAST” tests which are discussed in more detail in Section 10.9.3. In the former the packaged parts must survive 1000 h at 85 ◦ C temperature, 85% humidity and the operating bias. The latter highly accelerated stress test aims to replicate the same stress in a much shorter time frame. The standard HAST conditions of 130 ◦ C with 85% relative humidity is achieved at approximately 18 psi overpressure. The standard assumption is that the 1000 h THB test is equivalent to 96 h of HAST based on earlier work on silicon device technology. This equivalence has been questioned for the case of compound semiconductor devices by a number of workers [145, 146] and the GaAs device industry has found the routine satisfactory attainment of the 96 h HAST requirement a difficult hurdle [147].

2.5

Models

2.5.1

Device models Device models are employed to simulate device behavior in circuit design. The accurate simulation of GaAs FET power amplifiers can present a number of difficulties for the presently available modeling techniques and the degree of success achieved varies considerably depending on the precise application. Available models for moderatelysized devices (up to a few mm of gate periphery) can generally predict first-order parameters satisfactorily such as terminal impedances, gain, power and power saturation, and give a reasonable indication of efficiency. However, the situation for more demanding requirements such as accurate modeling of very large devices, for the precise prediction of large-signal nonlinearity and for the impact of some transient phenomena such as selfheating and slow-state effects on digitally modulated waveforms is often less satisfactory.

2.5.2

Small-signal models Extraction of the parameters of the equivalent circuit model of Figure 2.12 is well established. For devices of gate peripheries up to the order of a millimeter or so, this model is readily extractable from a suitable set of bias dependent S-parameters using the direct extraction technique introduced by Dambrine et al. [148] and subsequently further refined by numerous authors. The essential technique relies on a set of off-state or “cold-FET” biases to extract the embedding parasitic elements from a simplified equivalent model applicable to this bias condition. The embedding parasitics obtained for this simpler network are assumed to be also appropriate for the on-state or “hot-FET” bias condition. These parasitic values may therefore be used to de-mbed the hot-FET data, thereby obtaining the y-parameters of the intrinsic FET equivalent circuit and, at this point, solving for intrinsic elements is straightforward. The model obtained from this process is usually acceptable for frequencies below around 10 GHz. At higher frequencies it is normal to find that the accuracy of the reverse isolation parameter S12

2.5 Models

Lg

Cgd

Rg Cgs

Rd

+ --

Ri

85

Ld

Rds Cdc

gm Cds Rs

Ls

gm = gm0.e−jωτ

Figure 2.24 High-frequency GaAs FET equivalent circuit network.

becomes unacceptable. The reason for the discrepancy is due to the inadequacy of the equivalent circuit topology. Better fits than that obtained from direct extraction methods may be readily obtained but it is generally found that this involves non-physical values for some of the elements. Alternatively, modified equivalent circuit topologies may be employed which attempt to address the additional complexity in the frequency response at the higher frequencies. Such factors as dipole capacitance and distributed effects [148–152] give rise to modified equivalent circuit models such as that of Figure 2.24. These more complex equivalent circuit topologies don’t lend themselves to a wholly direct extraction algorithm, however the Dambrine model can be taken as the starting point and strategies developed to deal with the additional elements in a structured manner [153]. As mentioned above, direct extraction performs well for devices of modest size. As the device size is increased above a few mm of gate periphery the device becomes increasingly distributed in nature, and also the device measurements become less reliable due to the low impedance level that results. Very low impedances are difficult to measure accurately in a 50  system and the obvious solution of scaling up smaller device measurements to replicate a very big device is not straightforward. A particular issue is that the thermal environments can be very different [154]. However, for the most part, at least for devices that are directly measurable, the development of small-signal models is a reliable activity.

2.5.3

Large-signal models The situation for large-signal models is less straightforward. Here the desire is to model the device response to an arbitrary signal. The difficulty of this challenge is perhaps not always fully appreciated. The normal approach is to use large-signal equivalent circuit models which have been created by transforming a set of bias-dependent linear models into a single nonlinear one. At the heart of this approach, at least for commonplace models, lies the “quasi-static assumption” where it is assumed that the instantaneous

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values of the equivalent circuit elements are uniquely dependent on their controlling voltages [155]. In other words the device is assumed to be memory-less. As has already been discussed this actually isn’t the case and both thermal effects and dispersion effects cause this assumption to be violated. Consequently, large-signal models employ various measures in attempt to account for these effects and a range of large-signal model formulations have been developed over the years. They typically have focused on particular aspects of device behavior and a Darwinian process of natural selection, skewed by the choices of models that the simulator vendors have chosen to support has resulted in a range of models coming to the fore. A FET model for PA applications should possess the following attributes: 1. 2. 3. 4.

Replicate the DC I–V well in order to accurately reproduce the correct bias point. Account for the effects of dispersion so that the RF swing is accurately modeled. Properly represent the bias-dependence of the capacitances. Accurately reproduce differentials of the bias dependent parameters as well as their absolute values. 5. Include the impact of temperature on device characteristics. 6. Include time delays for high-frequency models.

The commonly available models tend to have strengths that have addressed a subset of the above requirements and there is no obvious “best” model. For example, the Triquint “TOM” series of models introduced an effective approach to model the bias dependence of the drain conductance [156] whereas the Angelov/Chalmers model [157] is notable in including the characteristic peak in the transconductance dependence on gate bias typical of HEMT devices. The I–V characteristic is the focus of the Parker–Skellern model [158] which has a flexible functional form and well-behaved continuous derivatives. Many models include dispersion effects with various degrees of sophistication with the extended Angelov [159, 160] and Parker–Skellern models being comprehensive examples. It is not unusual for models to concentrate heavily on the device I–V, however for accurate simulation of linearity as frequencies increase then the accuracy of the reactive elements is also important [161]. The Angelov [160] and TOM3 models [162] have comprehensive bias dependent capacitance models. Another development is the (unpublished) Auriga model which is a further development of the Angelov model and which claims improved capacitance models and a modified drain current equation [163]. The popular EEFET3 and EEHEMT models [164] bring together a number of these features in two widely used forms. An appreciation has grown with time of the importance of charge conservation for the gate capacitance. As discussed in Section 2.2.7, the gate depletion region is a single entity but is accessed by all three terminals. It is seemingly straightforward to extend the small-signal model to employ two bias-dependent capacitors Cgs (Vgs , Vds ) and Cgd (Vgs , Vds ) to represent the depletion reactances with independent charge or capacitance functions of the remote controlling voltages. However, this approach will generally result in a non-conservative system so that the total gate charge is (Vgs , Vds ) path dependent. The consequences of this are the possibility of an unintended net gate current [165] and, as circuit simulators are required to maintain charge-conservation

2.5 Models

87

at each node, then simulator non-convergence and spurious results can occur. Other work has demonstrated that charge conservation is important for accurate prediction of nonlinear effects [166, 167]. Two approaches to resolve the problem are possible. The direct and conceptually straightforward approach is to construct the model in terms of a single gate charge entity that is a function of the local variables Vgs and Vgd . This is the approach used in the widely available TOM3 model [162]. The charge function cannot be directly measured and must be inferred from the small-signal Cgs and Cgd capacitances. The resulting model is fundamentally and unequivocally charge-conservative [167]. Alternatively, the charge may be separated into independent functions Qgs (Vgs , Vds ) and Qgd (Vgs , Vds ). To achieve charge conservation these elements must be augmented by additional charge control elements called trans-capacitances which are required in order to properly account for the contributions to the partitioned reactive currents that arise from both controlling voltages [168, 165, 169]. An example of a gate-charge model employing separate gate-source and gate-drain functions and employing transcapacitance to restore charge conservation is the formulation used in the EEFET3 and EEHEMT models. The functions employed are charge-conservative in the saturation region of the device I–V and so are valid for power amplifier circuits. However, the use of smoothing functions in order to force symmetrical behavior of the charge functions around Vds = 0 results in non-physical (negative) drain-source capacitance in the linear (i.e., subknee) region [170]. Large-signal models are developed by fitting the model equations to measured data by numerical optimization. The number of fitting parameters can be extensive and so to obtain good models robust methodologies are required to segment the problem into parameter subsets and to select good initial values. The most straightforward procedure is to use measured DC data for the I–V equation and to use bias-dependent S-parameter data to extract the charge functions and to model the correction terms necessary to modify the dynamic response of the I–V. The impact of dispersion can be a significant source of error for PA design and a more accurate approach can be to directly measure the dynamic I–V with a pulsed I–V measurement system [21, 22, 171, 172] and to use that to represent the model I–V [173]. This approach provides a direct model of the dynamic I–V at the quiescent bias point of interest and avoids the need to develop a complex empirical correction factor. The main drawback of this approach is that the resulting I–V model is no longer applicable for the whole bias plane but is specific to operation points in the vicinity of the quiescent point in the pulsed I–V set. The traditional compact device models generally do a reasonable job of describing first-order amplifier performance and adequately represent the terminal impedances and power saturation behavior. However, they are usually less successful at next-level parameters such as linearity measures, and usually do not include such refinements as self-heating or accurate bias-dependence of trapping phenomena. These shortcomings have inspired a lot of efforts spanning many years to enhance commonly available models. A substantial degree of improvement was obtained by augmenting the quasi-static models with corrective terms for trapping effects. Measures to accomplish this include empirical methods to modify the large-signal I–V response by means of corrections to the

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dynamic output conductance [174]. Later developments have been to make use of pulsed I–V data to frame the construction of more physics-based trapping models [175–177]. Thermal effects are also be included in this work by the use of self-heating terms and a thermal impedance model [178]. The next stage of this approach is to include the impact of the self-heating on to the trapping state by including a temperature dependence to the trap correction terms [179, 180]. The refinements to the trapping models have successively improved the state-of-art in this aspect of modeling. However, an area somewhat less developed is the provision of a satisfactory approach for the modeling of large periphery devices. A common experience is that conventional circuit model approaches do not satisfactorily scale above a few mm of gate width. However, such devices are required for numerous applications in the L to C band range. GaAs devices with 100–200 mm of periphery are capable delivering 50–100 W from a single die at 2 GHz but the circuit design approaches are largely “cut and try.” Conventional modeling approaches are ill-equipped to cope with this distributed problem and a number of new dimensions need to be added if models are to be adequate. Such devices have many fingers – frequently over a hundred – which see differing and coupled thermal and electromagnetic (EM) environments. A particular problem is also to model accurately the stability of such devices. The complete model for this highly complex situation is a coupled electro-thermal and EM model. There is an emerging body of academic literature on this topic with recent developments towards simplification and manageable computation speed. Reference [181] describes circuit simulation software coupled with a highly efficient thermal solver. Individual fingers of a power cell are modeled with a compact equivalent circuit model and the fingers are thermally coupled by a thermal circuit. Reference [182] specifically addresses the topic of large power devices with a similar approach that also includes coupled EM simulation. The latter approach is notable for being deployable on standard commercial simulators. Another direction in modeling aims to avoid the whole messy business of trying to persuade an equivalent circuit model with elements that follow prescribed bias-dependent functions into representing the measured data. An alternative approach instead employs table-based techniques where the nonlinear data is accessed and interpolated from lookup tables. The most well-known implementation of this approach is the Root model [183] available as a turn-key commercial modeling solution. Subsequent developments of this approach make use of more sophisticated interpolation schemes which provide better simulation of nonlinearity [184, 185]. A further theme receiving much recent attention has been the use of direct large-signal measurement [186]. Techniques explored here include fitting conventional equivalent circuit model parameters directly to observed large-signal behavior [187] and the direct extraction of extrinsic current and charge functions to describe the nonlinear behavior directly at the device terminals [188]. However, the ultimate logical end-point of this direction is to eliminate any level of equivalent circuit description altogether and instead to implement a wholly mathematical “black-box” or “behavioral” description of the data. The approach that has been adopted to achieve this is based on poly-harmonic distortion (PHD) modeling [189] which describes large-signal behavior by means of an

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89

extension to linear S-parameters. In this scheme additional terms are added to the linear parameters to account for harmonics and intermodulation frequency components. By this means complex waveforms may be described. The term X-parameters has been coined to describe the new nonlinear parameters and a commercial nonlinear vector network analyzer capable of their measurement are available. In order to be useful for characterizing transistors the X-parameters must be measured over the appropriate region of the Smith chart requiring the X-parameter characterization to be combined with a load-pull system [189, 190]. The resulting dataset is large requiring the dimensions of frequency, bias, signal amplitude and impedance state all to be characterized and recorded. However, the approach is mathematically rigorous and has been verified to high levels of compression [191]. In many ways conventional empirical models and new behavioral data models are complementary. The former possess such benefits of an innate generality, compactness and scalability by virtue of the underlying physics embodied in their construction. These are attractive qualities for device manufacturers who need to characterize a process in a general fashion. They also make use of relatively straightforward and widely available test equipment. Black-box behavioral models offer the prospect of automatic generation of high-accuracy models for specific devices and operating conditions. This latter picture is attractive for specific design requirements focused on particular devices where the generation of large datasets and a lack of model scalability are manageable issues.

2.5.4

Load-pull A long established, pragmatic, and reliable alternative to the nonlinear device model is the long-standing load-pull measurement. Here the device performance is explored with carefully characterized tuners and the circuit is designed to replicate the desired matching impedances. This approach has evolved to employ computer controlled tuners that are now able to include effective control of the source and load harmonic impedances [192]. The key limitation of the passive tuners provided by commercial vendors is that the losses arising between the tuner instrument and the device under test restricts the maximum reflection coefficient that can be attained and this rather limits the size of the device that can be characterized. Pre-matching circuitry can help here but the ultimate solution is achieved by the use of an active load-pull system such as that described in reference [193] where the reflected signal is synthesized as required to account for the loss so as to achieve the effective impedance as if an ideal lossless tuner were used. Active load-pull systems have been successfully demonstrated by a number of workers over many years but they have yet to achieve widespread use outside of the R&D lab due to reasons of cost and complexity. In this light it is interesting to note that a remarkably effective but simple and extremely low-cost alternative to load-pull test equipment is available using nothing but a simple linear model for the device output impedance [194]. Experience has shown that the estimate for the output power match condition obtained from this approach is consistently in excellent agreement with load-pull measurement and the technique remains a popular approach for first-cut circuit design.

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2.6

Concluding remarks This chapter has reviewed GaAs power FET technology. It has covered materials properties, device types and their operation, key device physics, and critical aspects of power device design. A summary of GaAs device fabrication has been provided contrasting established processes with new low-cost approaches and the chapter concludes with a brief review of device models. The wide range of subjects covered spans several decades of development by numerous research groups and industrial companies. It is therefore impossible to fully reference such a body of work and a balance had to be struck that weighed recognition of historical significance with clarity and brevity for the contemporary reader. A further limitation is this author’s limited capacity to read, digest and retain the breadth of literature. It is consequently inevitable that omissions will have occurred and for which it is hoped the relevant parties will understand.

Acknowledgment The author would like to thank the engineering team at the RFMD facility in Newton Aycliffe (members past and present) who have all contributed to the understanding that is contained in these pages. Particular appreciation is expressed to Mike Brookbanks, Richard Davies and Rob Dry who gave helpful support in the writing of the chapter.

Appendix 2.1 Comments on the determination of fT and fmax The h21 function is generally very well behaved and is easy to calculate in an unambiguous manner. This should be performed from a linear part of the h21 versus log. frequency curve where the first pole of the frequency response dominates. For a microwave device a frequency of around 5–10 GHz is typically a good frequency to use. An extrapolation to 0 dB at 6 dB/octave will give a reliable value and this may be simply calculated thus: f T = f h 21 ( f )

(A1)

= f 10

(A2)

h 21 d B( f )/20

where f is the frequency of evaluation, h 21 is the magnitude of the forward hybrid parameter and h 21 d B is its value in dB. The measurements should be properly deembedded to the device reference plane for the appropriate terminating impedances to apply. A useful “rule of thumb” for a well-designed device is that it will likely be an appropriate choice for an application for frequencies up to ∼fT /2. The situation for fmax is not as straightforward. In theory there is no issue as both Gmax and U both cross the 0 dB line at the same frequency and this point uniquely defines fmax [60, 195]. However, in practice for microwave FETs, fmax is usually somewhat

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higher than the upper limit of the available test equipment and examination of the gain curves for frequencies well below fmax invariably suggests Gmax and U will have distinct intercepts. The situation typically observed is that of Figure 2.14 with U following a well-behaved 6 dB/octave roll off and giving no hint that it will converge with Gmax. Vendelin [60] explains how additional terms in the frequency response will ultimately restrain the U curve; however, a judgment has to be made on the data that is available. In practice one of the U or Gmax curves is chosen and extrapolated to determine the 0 dB intercept. It is also very common not to specify which curve was used for this procedure. Many workers choose a 6 dB/octave extrapolation of U. For some this is due to a belief that it is the correct one or because of its apparent well-behaved slope. Others choose Gmax and return a commendably more conservative value; however the complicated Gmax curve provides ambiguity as to how it should be extrapolated. Given these issues there is a good argument not to quote fmax at all but to provide explicit Gmax curves or quote Gmax at particular frequencies. In any event, a degree of caution is required when comparing devices based on fmax values that one has not measured for oneself. Should a value for fmax be required and it is beyond the frequency range of available test equipment then, in this author’s opinion, a reasonable approach to its determination is to extrapolate Gmax at 6 dB/octave from a frequency where the device is unconditionally stable and with stability factor, k, comfortably above unity so as to be reliably free of the gain-peaking near the MAG/MSG stability break-point.

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3

Wide band gap transistors – SiC and GaN – physics, design and models R. J. Trew ECE Department, North Carolina State University

3.1

Introduction Although solid-state transistors have replaced vacuum electronics in the vast majority of microwave electronic systems over the past 40 years the revolution is not complete. In particular, the areas of high RF power for microwave and millimeter-wave radar and communications transmitter applications, the ability to produce adequate RF power levels at frequencies greater than 100 GHz, and the ability of devices to operate at high temperatures greater than about 250 ◦ C remain dominated by microwave tubes. Further solid-state material and transistor developments in these areas are among the last frontiers for semiconductor electronics. In these areas solid state transistors have not been able to compete with vacuum tube devices, and most systems that must deliver kW to MW power levels are designed using various types of microwave tube. The current state-of-the-art for microwave solid-state devices and for microwave tubes is shown in Figure 3.1. As indicated, solid-state devices produce RF power levels less than about 100 W and operate with reasonable RF output power to frequencies of about 100 GHz. The RF performance status shown in Figure 3.1 is for single device operation, and does not necessarily represent a true comparison of the RF output power capability of a system. Power combining and phased array technology permit the outputs of many solid state transistors to be combined, thereby producing significantly improved RF output power and solid state systems can, in practice, compete in terms of RF output power with tube-based systems in some cases. Combining technology can raise microwave RF output power into the kW range, at least through S band and into Ku band [1–4], and theoretically to much higher power levels. However, such multidevice concepts are increasingly difficult to apply as operating frequency increases and cannot extend the upper frequency limit beyond the present state-of-the-art. Operation at frequencies above X band and up to 100 GHz with RF output power in the hundreds of watts or kW range will require new semiconductor materials and/or transistor concepts. The upper frequency capability of a solid-state transistor is fundamentally dependent upon the charge carrier velocity in the semiconductor material from which it is fabricated, and the physical dimensions of the device. Modern semiconductor material growth technology and fine line lithography permit transistors with critical dimensions less than a micron (<10−6 m) to be readily fabricated, which permits transistors with high cutoff frequencies to be realized. At high electric fields most common semiconductor materials demonstrate a saturated charge carrier velocity on the order of v s ∼ 107 cm/s,

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Figure 3.1 Average RF output power versus frequency for various semiconductor and vacuum electronic devices [5].

or less. Although GaInAs-based HEMTs demonstrate good RF performance up to approximately 300 GHz, this performance results primarily from high sheet-charge density and resulting high device current. These two factors permit transistors with good RF performance at high frequency to be achieved. However, the RF output power from these devices is very low, and not suitable for most practical applications. Standard semiconductor devices such as field-effect transistors and bipolar transistors designed for high frequency are fundamentally limited in their RF power generation capability by low breakdown voltage, which prohibits their operation at the voltages necessary to generate high RF power. Also, relatively poor thermal conductivity makes it difficult to engineer the device for adequate thermal resistance, and devices designed for high RF output power tend to operate at elevated temperature, which limits device performance. Also, power devices must be designed for high current and this necessitates devices with large cross-sectional area. This, in turn, produces low impedance inputs that are difficult to impedance match, especially in power-combined schemes. All traditional semiconductor devices (i.e., those fabricated from Si, GaAs, InP, etc.) are limited in operating temperature by relatively low barrier energy, and the electronic barriers become increasingly leaky as temperature increases. Advances in semiconductor materials engineering, device design, and fabrication are providing solutions to many of these limitations and devices for high-power, highfrequency, and high-temperature applications are being developed. These devices are expected to find wide application due to the high reliability, small size, and potential low cost offered by solid-state electronics. One very promising approach is the development of microwave transistors fabricated from wide bandgap semiconductors, particulary SiC, GaN, and heterostructures of the III-Nitride system. Although research in these

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105

semiconductor materials has been pursued for many years, the technology for producing high-quality bulk SiC material for substrates has been demonstrated only in the last few years, and epitaxial SiC material of sufficient quality for device fabrication is now available. Bulk GaN substrates are not yet available, although device quality GaN and AlGaN epitaxial layers can be grown on sapphire and SiC substrates. A variety of electronic devices fabricated from these materials have been demonstrated and the results are promising for the development of transistors that can be used in high-power and hightemperature microwave transmitters. Due to high electron velocity (v s ∼2 × 107 cm/s) and high sheet-charge density (ns ∼1013 cm−2 ) III-Nitride heterostructure devices show promise for producing heterojunction FETs (HFETs) with improved mm-wave RF performance, potentially up to 300 GHz and above. At lower frequencies, on the order of X band and possibly as high as K band, SiC and GaN-based devices should be competitive with GaAs-based and InP-based transistors for many applications [5], particularly for improved RF output power capability. However, the higher current capability of the GaN-based heterostructures over SiC-based devices provides a fundamental advantage for higher frequency operation and improved RF output power above X or Ku band. In this chapter, the physical operation, design, and modeling techniques for wide bandgap transistors are presented. The microwave performance and status of transistor development from the wide bandgap semiconductor materials are presented. Problem areas that are presently limiting device performance are indicated. It is demonstrated that microwave power amplifiers fabricated from 4H-SiC MESFETs and AlGaN/GaN HFETs offer excellent RF power performance, particularly at elevated temperature. Theoretical transistor models predict room temperature RF output power on the order of 5–30 W/mm with PAE approaching the theoretical limits for class A and B operation for amplifiers fabricated using 4H-SiC MESFETs and AlGaN/GaN HFETs. Experimental results verify the theoretical predictions. Also, theoretical transistor models indicate that practical operation at elevated temperature, at least up to 500 ◦ C, is possible. The RF output power capability of devices fabricated from wide bandgap semiconductors is almost an order of magnitude higher compared with transistors fabricated from Si or GaAsbased materials. The wide bandgap semiconductor devices are finding application in RF sources and power amplifiers for base station transmitters for cellular telephone systems, satellite transmitters, HDTV transmitters, power modules for phased-array radars, surveillance and air-traffic control radars, wide-band amplifiers, and other applications. The transistors are particularly attractive since they are readily combined for high RF power applications. They are also attractive for applications that require operation at elevated temperature since they require minimal heat sinking.

3.2

Background A variety of electronic devices for high-power and high-frequency applications can be fabricated from SiC and GaN, and various heterostructures can be based upon these materials, particularly GaN-based heterostructures. Devices for power applications [6] include PIN diodes, Schottky–Barrier Diodes, MOSFETs, BJTs, JFETs, thyristors, and

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various ICs fabricated by combining the basic devices into complex structures. Highfrequency devices include MESFETs, HFETs, SITs, BJTs and HBTs, and IMPATTs. A variety of electronic devices, including both high-power RF and microwave devices, can be fabricated from nitride-based semiconductors. Microwave devices include MESFETs, static-induction transistors (SITs), Heterojunction bipolar transistors (HBTs), and HFETs. Devices for high-power applications include diodes, MOSFETs, MOSHFETs, and bipolar transistors. Excellent performance has been demonstrated from research and prototype devices, although many of these devices have not found widespread use or insertion into commercial systems. Microwave AlGaN/GaN HFETs are finding application for communications band base station amplifiers and microwave radar transmitters. The performance of SiC and GaN-based transistors are reviewed in this section.

3.2.1

SiC transistors Bipolar transistors (BJTs) have been fabricated in SiC. However, due to high resistance associated with the low mobility of p-type material, the base resistance for npn transistors is high, which limits the frequency response for the transistor [7]. It is shown that 6HSiC BJTs are limited in frequency response to about S band (i.e., 2–4 GHz), but good gain and RF output power are possible, with RF output power on the order of 50 W predicted. Power-added efficiency falls rapidly above about 1 GHz. The BJT device operation is dominated by minority carrier (electron) transit-time across the p-type base region. The use of 4H-SiC results in improved performance, and it is shown that electron mobility in the p-type base region can be on the order of 215 cm2 /V-s for a base region doped with Al to a concentration of NB = 4 × 1018 cm−3 [8]. For this device, the basecollector depletion region charging time, τ c , and the parasitic charging time, τ p , from the capacitance between metal pads and the underlying collector region dominate the overall electron transit time and, therefore, the fT of the device. The transistor demonstrated a peak fT = 4 GHz at a collector voltage of VCE = 20 V, and an emitter current density of JE = 10 kA/cm2 . The parasitic charging time can be minimized by improved device design and removal of the parasitic charging time produces a peak fT = 15 GHz. An improved device design by the same authors [9] yielded an fT = 7 GHz and an fmax = 5.2 GHz. Fabrication of the transistor on a semi-insulating substrate with resistivity greater than 105 -cm permitted the parasitic charging time to be minimized. The transistor was biased at VCE = 20 V, and operated at an emitter current density of JE = 10.6 kA/cm2 . The calculated maximum available gain (Gmax ) was 18.6 dB at 500 MHz and 12.4 dB at 1 GHz. A 4H-SiC BJT with good gain has been reported by Huang and Cooper [10]. This transistor utilized a thermal oxidation procedure, similar to that employed in 4H-SiC MOSFETs, to passivate the transistor surface. Previous SiC BJTs suffered from high surface leakage currents due to surface recombination velocity in the range 104 –105 cm/s [11, 12]. The passivated BJT had a current gain β = 55 and breakdown voltages of BVCEO = 500 V and BVCBO = 700 V. The current gain β remained above 50 with the current density above 700 A/cm2 . A record low on-state resistance for 4H-SiC BJTs was reported by Zhang et al. [13]. The 4H-SiC BJT used a 12 μm thick drift layer and

3.2 Background

107

produced an on-state resistance of 2.9 m-cm2 , with an open-base collector-to-emitter blocking voltage of VCEO = 757 V, and a current gain of β = 18.8. The transistor conducted a current of 5.4A (Jc = 859 A/cm2 ) at a forward voltage of VCE = 2.5 V. The same authors previously reported a 4H-SiC BJT that supported a voltage of 9.2 KV [14]. high-power SiC BJTs have been fabricated at UHF, and 215 W of pulsed class A power at 450 MHz has been reported [15]. The transistor was biased at VCE = 180 V and pulsed with a 0.1% duty cycle to avoid self-heating. The gain was 7.5 dB, and the RF power density was 4.3 W/mm when normalized to emitter finger length. SITs look very promising for RF power applications [16]. A SIT is basically a vertical FET. The device operates under space-charge-limited (SCL) electron transport conditions, and is very similar to a vacuum triode in operation. The device demonstrates low current gain (fT ), but excellent voltage gain and high power gain is possible. The low gain prevents the SIT from producing good performance much above C band, but excellent UHF and S-Band devices and amplifiers have been fabricated. Both 6H and 4H-SiC have been used. The first SITs were fabricated from 6H-SiC and a device with 11 cm periphery produced about 38 W at 175 MHz with 60% PAE [16]. The 6H-SiC SITs produced very low current, and the low current was found to be associated with anisotropic electron transport behavior. Currents traveling in a direction parallel to the c-axis of a 6H wafer were about five times lower than currents normal to the c-axis for the same voltage. This resulted in work shifting to the use of 4H-SiC, and a 4H-SiC SIT with 38 W RF output power, 9.5 dB of gain, and 45% drain efficiency at 3 GHz was developed [17, 18]. The device was operated under pulse bias and is useful for radar applications. Further progress includes a 800 W UHF SIT and a 900 W L-band SIT [19]. A two-stage amplifier with 1 kW RF output power using these devices was reported for the HDTV market [20] and other applications. The most recent result makes use of ion-implantation to produce a unit cell device that generates 107 W output power with 8.7 dB gain and 59% PAE under CW operation at 750 MHz [21]. The device was biased at Vds = 81.8 V and Ids = 1.87 A. This unit cell device is being used in a ten cell structure to produce a 10 kW RF solid state driver amplifier for commercial applications. The MESFET is a majority carrier device that can be fabricated using n-type SiC material so that only electrons are involved in current transport [22]. The MESFET is very attractive for fabrication of high-performance devices for use at microwave frequencies. The first SiC MESFETs were fabricated from 6H-SiC and MESFETs with current gain-bandwidth products of fT = 25 GHz were reported [23]. These devices produced 3.5 W (1.75 W/mm) RF power with 45.5% PAE at 6 GHz. Although the RF output power from the 6H-SiC devices is about three times that generally obtained from GaAs MESFETs, 4H-SiC has a low field mobility about twice that of the 6H-SiC and most device development has focused upon this material. Early 4H-SiC MESFETs with RF output power on the order of 2.8 W/mm at 1.8 GHz [24], and 2.27 W/mm with 65.7% for a class B amplifier were reported at 850 MHz [25]. In later work, a 4H-SiC MESFET with an fmax of 42 GHz was reported [26], indicating that these devices should be capable of producing excellent RF performance through X-band, and potentially to K-band. This device had a gate length of Lg = 0.5 μm and produced 5.1 dB gain at

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Wide band gap transistors – SiC and GaN – physics, design and models

20 GHz. high-power amplifiers have been produced and a SiC UHF television module has demonstrated good signal fidelity at the 2000 W PEP level. S-band 4H-SiC transistors with over 200 W peak power have been produced for radar applications and X-band power of over 6 W has been obtained [27]. A 4H-SiC MESFET with 42 mm of gate periphery on a single die produced 53 W of RF power with 37% PAE at 3 GHz [28]. X-band SiC MESFETs have produced 2.5 W/mm of RF power and 41% PAE at 8 GHz, and 30 W RF power from a 12 mm gate device at 9.7 GHz [29], and excellent RF power density of 5.2 W/mm at 3.5 GHz and 4.5 W/mm at 10 GHz were obtained. As the material quality improved RF output power has improved and a 4H-SiC MESFET has produced 56 W with 53% PAE at L-band [30]. The device had a fT = 12 GHz and an fmax = 17 GHz, and demonstrated minimal current drift up to 1100 h. A 4H-SiC MESFET has produced 20 W output power with 60% PAE in S-band [31]. A major limitation to RF output power is breakdown of the gate electrode on the drain side. The electric field at the gate edge can achieve a very high magnitude, particularly when the device is biased to high drain voltage and operated with large RF terminal voltages consistent with high RF power drive. It has been shown that the gate can leak current, and may demonstrate breakdown. The use of field-plates [32] has been demonstrated to result in significantly reduced electric field magnitude at the gate edge, thereby reducing gate leakage. The field-plate can be connected electrically to the gate, the source, or left floating. The use of the field-plate permits higher voltages to be applied, with improved RF output power. A field-plate 4H-SiC MESFET with a buriedgate design produced very high RF output power with a power density of 7.8 W/mm and 70% PAE at 3 GHz [33]. The device was operated in class A/B. The field-plate permitted a drain bias of Vds = 65 V to be applied. A two-stage broadband integrated amplifier circuit that produced 5 W over 10 MHz to 2.4 GHz was reported [34]. The integrated amplifier produced 22 dB gain, 37 dBm output power and 28% PAE. The third-order intercept was 47 dBm. A novel FET which used a β-SiC nanowire as the conducting channel has been reported [35]. The device consisted of a SiO2 layer grown on top of a Si substrate. The β-SiC nanowire was located on the surface of the SiO2 between two metal contacts. The Si substrate was used as the gate electrode, and application of a varying voltage permitted control of the current flowing in the SiC nanowire. Nanowire diameters varying from 10–25 nm with a length of 10 mm were used. The device demonstrated good hightemperature performance and it was concluded that the transistor could find application as a high-temperature gas sensor.

3.2.2

AlGaN/GaN transistors The AlGaN/GaN HFET demonstrates excellent RF performance. High sheet-charge density resulting from high Al incorporation in the AlGaN layer permits high channel current to be obtained [36]. Initial HFETs were fabricated on sapphire substrates, but recent work has focused upon the use of semi-insulating or p-type SiC substrates [37–39]. Excellent RF performance has been achieved at S-band through Ka-band frequencies, with the greatest RF power density obtained at S-band and up to X-band.

3.2 Background

109

Most AlGaN/GaN HFETs are fabricated with unintentionally doped AlGaN and GaN epitaxial layers. However, it is also possible to fabricate AlGaN/GaN HFETs with good RF performance using doped channel designs [40], and 1.73 W/mm RF output power with good gain was obtained at 8.4 GHz. The small signal performance of these devices demonstrated gain bandwidth products of fT = 39 GHz and fmax = 45 GHz. Small-signal performance with intrinsic current gain-bandwidth products up to fT = 106 GHz for a device with a gate length of Lg = 0.15 μm has been obtained [41]. These devices produced about 4 W/mm RF power and 41% PAE at 4 GHz. Very high RF power density has also been obtained and 9.8 W/mm RF power density with 47% PAE at 8 GHz has been reported [42]. The devices had gate widths of W = 2 mm and the devices were flip-chip mounted to AlN substrates for improved thermal conductance. Other devices fabricated using SiC substrates produced RF power as high as 10.7 W/mm at 10 GHz with 40% PAE [43], with further improvements yielding slightly over 11 W/mm. Devices fabricated using AlN interfacial layers between the AlGaN and GaN produced RF output power of 8.4 W/mm with a PAE of 28% at 8 GHz [44]. The introduction of field-plate technology suppresses the electric field at the gate edge and permits larger drain bias to be applied resulting in higher RF output power. A high RF output power density of >30 W/mm was reported for a field-plate device biased at a drain voltage of 120 V [45]. High PAE has also been reported, and an AlGaN/GaN HFET grown by MBE on a 4H-SiC substrate produced 8.4 W/mm with 67% PAE with a drain bias of 30 V [46]. Silicon has emerged as a viable substrate material for AlGaN/GaN HFETs and excellent RF performance has been obtained. Johnson et al. [47] reported RF output power of 12 W/mm with 52.7% PAE and 15.3 dB gain for a 0.7 μm gate length device. The HFET was biased at 50 V and operated at 2.14 GHz. The transistor is intended for communications band applications. Dumka et al. report 7 W/mm with 38% PAE and 9.1 dB gain at 10 GHz from a AlGaN/GaN HFET fabricated on a Si(111) substrate [48]. The device was biased at a drain voltage of 40 V. Reduction of the drain bias to 20 V resulted in a decrease in RF power to 3.9 W/mm, but an improvement of the PAE to 52%. high-frequency Ka-band performance has also been reported. At 18 GHz Ducatteau et al. report an RF power density of 5.1 W/mm with 20% PAE and 9.1 dB gain from a nitride HFET fabricated on a Si substrate [49]. The device had a 0.25 μm gate length and a current gain bandwidth of fT = 50 GHz. An AlGaN/GaN HFET fabricated on a SiC produced 5 W/mm with 30.1% PAE and 5.24 dB gain at 26 GHz [50]. Lee et al. [51] report 4.13 W/mm with 23% PAE and 7.54 dB gain at 35 GHz. The HFET was biased with a drain voltage of 30 V. The HFET was fabricated on a SiC substrate. At 40 GHz an RF power density of 2.8 W/mm, 10% PAE, and 5.1 dB gain was obtained from a device with a 0.18 μm gate length device [52]. The performance of the device was sensitive to frequency, and RF output power density increased to 3.4 W/mm by reduction of the operating frequency to 38 GHz. Using a recess gate design an RF output power density of 5.7 W/mm with 45% PAE was obtained with a drain bias of 20 V [53]. Increasing the drain bias to 28 V resulted in an increase in RF output power density to 6.9 W/mm. Palacios et al. [54] report excellent RF performance at 40 GHz from an AlGaN/GaN HFET fabricated on a 4H-SiC(0001) substrate. Devices with similar structures were fabricated using both OMCVD and MBE. The device

110

Wide band gap transistors – SiC and GaN – physics, design and models

produced 8.6 W/mm with 29% PAE and gain of about 5 dB. The OMCVD grown device had improved performance, with 10.5 W/mm, 33% PAE, and about 6 dB gain. Attempts to improve device performance include novel surface passivation and charge confinement. Lau and her colleagues [55] introduced a surface passivation technique involving a fluoride-based plasma treatment. The fluoride-based plasma treatment, along with a post-gate rapid thermal annealing step, was found to effectively incorporate negatively charged fluorine ions into the AlGaN barrier and positively shift the threshold voltage. The technique was used to fabricate an enhancement-mode (E-mode), HFET. Shen et al. [56] used the fluorine plasma process, along with a deeply recessed gate HFET design, to fabricate a device that produced 17.8 W/mm with 50% PAE and 15 dB gain at 4 GHz. The passivation process limited gate leakage and thereby permitted a drain voltage of Vds = 80 V to be applied, without the use of a field-plate. The strong polarization effects of the AlGaN/GaN structure may be a source of some of the reliability problems experienced with these devices. Attempts to investigate this include utilization of alternate barrier materials that are less polar. One such structure can be fabricated using InAlN, rather than the commonly employed AlGaN. An InAlN/GaN HFET with a gate length of 0.7 μm produced a gain-bandwidth product of fT = 13 GHz and and fmax = 11 GHz. The 2DEG was very high, with nss = 4 × 1013 cm−2 and an electron mobility of μn = 750 cm2 /V-s [57, 58]. An InGaN layer was used as a back-barrier to improve confinement of the 2DEG electrons [59]. The confinement improved the output resistance, and a device with a gate length of 100 nm produced a gain-bandwidth product of fT = 153 GHz and an fmax = 198 GHz. By adjusting the bias the same device produced an fmax = 230 GHz. A double heterojunction device design using an InGaN notch fabricated on a sapphire substrate produced RF output power of 3.4 W/mm and 41% PAE at 2 GHz [60]. Good RF performance has also been obtained from a GaN FET, fabricated using a novel surface passivation consisting of a thin AlN layer located between the GaN channel and a SiN surface passivation [61]. The resulting structure is basically a metal-insulator-semiconductor (MIS) FET. A device with a gate length of 60 nm produced fT = 107 GHz and fmax = 171 GHz. Most of the early results were for devices with very narrow gate widths to minimize device heating and thermal effects. More recent work has focused upon producing highpower devices and amplifiers suitable for use in applications such as communications base station transmitters. Ando et al. [62] reported RF output power of 10.3 W with 47% PAE and 18 dB linear gain at 2 GHz. This result was for a device with a gate width of 1 mm. Linear gate-width scaling with drain current and RF output power has also been demonstrated. A high-power integrated circuit using 8 mm of gate periphery yielded 51 W RF output power at 6 GHz under pulse bias conditions [63]. A communications band amplifier, using AlGaN/GaN HFETs fabricated on SiC substrates, and biased at 48 V produced CW RF output power of 100 W at 2.14 GHz [64]. A C-band amplifier using a 0.4 μm gate length and 50.4 mm gate width AlGaN/GaN HFET fabricated on a SiC substrate produced RF output power of 140 W with 25% PAE. The amplifier was operated with a pulse bias of 40 V [65]. A push–pull transmitter amplifier for 3G wireless base station applications was constructed using AlGaN/GaN HFETs fabricated on SiC substrates [66, 67]. At a drain bias of 50 V the amplifier produced 250 W RF output

3.3 Material parameters

111

power and, using digital predistortion linearization, an adjacent channel leakage power ratio (ACLR) of less than −50 dBc for four-carrier W-CDMA signals was obtained. Very high RF output power was obtained from wide gate width AlGaN/GaN HFETs fabricated on Si(111) substrates [67]. The individual HFETs had a gate width of 36 mm and when operated under CDMA modulation produced 20 W RF power with a drain efficiency of 27% when biased at a Vds = 28 V. The amplifier was fabricated using two of the devices and produced a maximum RF output power of 156 W with 65% drain efficiency at 2.14 GHz and no modulation. The same authors report further improvements by employing a source-grounded field plate on the HFET, and when biased at Vds = 60 V and under pulsed RF conditions, a saturated RF output power of 368 W with 70% PAE was obtained. Wide gate width devices require effective means for grounding, and a laser-assisted processing procedure for fabricating via holes was reported [68]. The process permits wide gate width devices to be effectively grounded, and a 20 mm gate width device biased at Vds = 26 V produced 41.6 W with 55% PAE at 2 GHz. Amplifiers fabricated using AlGaN/GaN HFETs have produced over 400 W of pulsed power with 600 MHz of bandwidth (2.9 to 3.5 GHz) and 50% PAE [69], a two-stage amplifier has produced 58 W with 38% PAE and 15 dB gain at X-band [70], and a MMIC amplifier has produced 500 mW RF power with 17% PAE and 12 dB gain in E-Band (71–95 GHz) [71]. The nitride devices are being aggressively developed for application in amplifiers for S-band communications band base station transmitters, and as amplifiers for X, Ka, and W-band radar transmitters.

3.3

Material parameters The DC and RF performance capability of electronic devices is fundamentally dependent upon the electronic, thermal, and mechanical properties of the materials from which the devices are fabricated. Of particular importance are the charge transport characteristics as a function of electric field for the material. Each semiconductor has a different velocityfield characteristic, and semiconductors of most interest for device fabrication will have high carrier velocity capability. The quality of semiconductor epitaxial material has continually improved, and the DC and RF performance of semiconductor transistors have experienced significant performance improvements as a result. A variety of technologies for growth of semiconductor epitaxial layers, such as molecular beam epitaxy (MBE) and organo-mellatic chemical vapor deposition (OM-CVD), have been developed and these technologies permit the growth of epitaxial layers of precise thickness and impurity doping concentration. It is now possible to fabricate solid state devices with layer thickness of only a few angstroms with precise defined impurity concentrations, and this level of control permits devices with frequency performance well over 100–300 GHz to be fabricated. The advantages of device fabrication from wide bandgap semiconductors can be seen from a comparison of fundamental electronic transport and material parameters. A summary of the semiconductor material properties most important to electronic device performance is listed in Table 3.1 for several semiconductors.

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Wide band gap transistors – SiC and GaN – physics, design and models

Table 3.1 Material properties for several semiconductors Material

Eg (eV)

εr

σ (W/◦ K-cm)

Ec (V/cm)

Si GaAs InP 3C-SiC 4H-SiC 6H-SiC GaN Diamond

1.12 1.43 1.34 2.3 3.2 2.86 3.4 5.6

11.9 12.5 12.4 9.7 10.0 10.0 9.5 5.5

1.5 0.54 0.67 4 4 4 1.3 20–30

3 × 105 4 × 105 4.4 × 105 1.8 × 106 3.5 × 106 3.8 × 106 2 × 106 5 × 106

For transistors the most important material properties for fabrication of highperformance microwave structures include a large energy gap, Eg (eV), a low value of dielectric constant, εr , high thermal conductivity, σ (W/◦ K cm), and high critical electric field for breakdown Ec (V/cm). Wide energy bandgap generally translates into an ability to support high internal electric fields before electronic breakdown occurs, and also provides for improved radiation resistance. Most transistor fabrication has been in Si, GaAs, and InP and related compounds and the vast majority of all devices commercially available are fabricated from these materials. The SiC and GaN-based materials have energy bandgaps about two to three times larger than those in the conventional semiconductors, such as Si, GaAs, and InP. The dielectric constant is an indication of the capacitive loading of a device and affects the terminal impedance. Generally, for solid state devices a low value for the semiconductor dielectric constant is desired, and this permits a solid state device to be larger in area for a specified impedance value. Increased area permits larger RF currents and higher RF power to be generated. The wide bandgap semiconductors have dielectric constants about 20% lower than the conventional materials. This, in turn, permits a wide bandgap semiconductor device to be about 20% larger in area compared to a comparable device fabricated from Si or GaAs for a specific impedance magnitude, and increased area permits larger RF currents and higher RF power to be generated. The thermal conductance of the material is extremely important since this parameter indicates the ease with which dissipated power can be extracted from the device. Poor thermal conductivity results in device operation at elevated temperature with degraded performance. Conventional semiconductors are, in general, poor thermal conductors, particularly the GaAs and InP materials. Conversely, SiC is an excellent thermal conductor and GaN is about the same as Si, the best of the conventional semiconductors. Diamond has the highest thermal conductivity of any known material and is often used to fabricate heat sinks for semiconductor devices that must operate in high-power applications. Finally, the critical electric field for electronic breakdown should be high. This parameter is an indication of the strength of the electric fields that can be supported internally to the device before breakdown. High electric fields permit large terminal RF voltages to be supported, and this is necessary for the generation of high RF power. The critical fields for the wide bandgap materials are excellent and very high, typically an

3.3 Material parameters

113

Velocity (x107 cm/s)

10

4H-SiC GaAs

AIGaN/GaN 6H-SiC

1 Si GaN

0.1 1

10

100

1000

Electric Field (kV/cm)

Figure 3.2 Electron velocity versus electric field transport characteristics for various n-type

semiconductors (Nd = 1017 cm−3 ).

order of magnitude greater than for the conventional semiconductors. In general the wide bandgap semiconductors have more optimum values for all these parameters compared to conventional semiconductors. Basically, a current is defined as the movement of charge and expressed as the product between the charge density and transport velocity. Therefore, the DC and RF currents that flow through a device are directly dependent upon the charge carrier velocity versus electric field transport characteristics of the semiconductor material. Generally, for high currents and high frequency, high charge carrier mobility and high saturation velocity are desirable. A comparison of the electron velocity-electric field (v-E) characteristics for several semiconductors is shown in Figure 3.2. The v-E characteristic is described in terms of charge carrier mobility μn , (units of cm2 /V s) defined from the slope of the v-E characteristic at low electric field, and the saturated velocity vs (units of cm/s), defined when the carrier velocity becomes a constant, field-independent magnitude, generally at high electric field. The high value for electron mobility of GaAs (typically, μn ∼5000 cm2 /V s) is the main reason that FETs fabricated from this material have such excellent high frequency performance. A primary disadvantage of fabricating transistors from SiC and GaN is the relatively low values for the charge carrier mobilities (typically, μn ∼200–500 cm2 /V s). In general, the wide bandgap semiconductors have relatively low mobility, but very high saturation velocity (typically, v s ∼1–2 × 107 cm/s). However, the mobility of SiC and GaN is adequate for transistors designed for high power operation [72] due to the large RF terminal voltages these transistors can sustain. The low mobility produces a relatively high knee voltage (i.e., the transition voltage between the linear and saturation regions on the transistor I–V curve), but the ability of the device to produce good RF output power and PAE in amplifier circuits is not seriously compromised by the relatively high knee voltage due to the large RF terminal voltages, which are on the order of 10–20 times the magnitude of the knee voltage. In practice, near ideal PAE is obtained for amplifiers fabricated from wide bandgap semiconductor transistors, and

Wide band gap transistors – SiC and GaN – physics, design and models

mobility Sheet Charge Density

1015

1014

1013

1000 10

100

Sheet Charge Density (cm–2)

1016

10 000 2DEG Mobility (cm –2/V-s)

114

1012 1000

Temperature (K)

Figure 3.3 Electron mobility and sheet charge density versus temperature for a 2D electron gas from Shubnikov–DeHaas measurements [5].

the AlGaN/GaN HFET amplifiers obtain near-ideal PAE up to X-band, and potentially higher. For a typical device doping density of Nd ∼2 × 1017 cm−3 , the electron mobility for 6H- and 4H-SiC are about 250 cm2 /V s and 500 cm2 /V s, respectively. The factor of two increase in mobility for 4H-SiC compared to 6H-SiC is one of the major reasons that the 4H polytype is preferred for device applications. The electron saturation velocity in both 6H- and 4H-SiC is v s ∼2 × 107 cm/s, which is a factor of two higher than for Si (v s ∼1 × 107 cm/s) and a factor of four higher than for GaAs (v s ∼(0.5–0.6) × 107 cm/s). The mobility and saturation velocity for the 2DEG for the AlGaN/GaN heterointerface is very suitable for device applications. The room temperature mobility of the 2DEG is in the range of 1000–1500 cm2 /V s, which is significantly better than for SiC or bulk GaN. The sheet-charge density for this structure can be very high and greater than nss ∼1013 cm−2 due to piezoelectric and spontaneous polarization induced effects. The measured sheet-charge density is about a factor of five better than is obtained for the more commonly employed AlGaAs/GaAs heterostructure. The characteristics for the 2DEG are shown in the Shubnikov-DeHaas and Hall mobility measurements in Figure 3.3 [5] for an AlGaN/GaN heterostructure grown on a sapphire substrate. The measurement over temperature indicates that the 2DEG mobility is very sensitive to temperature, demonstrating about ∼T −2.3 dependence. This indicates that devices fabricated from this type of structure will be temperature sensitive and performance will degrade rapidly with elevated temperature. The magnitude of electric field that produces saturated charge carrier velocity is also important since the device must be able to develop the saturation field to obtain maximum RF performance and high-frequency operation. The saturation fields for 4H-and 6H-SiC are about Es ∼60 kV/cm and Es ∼200 kV/cm, respectively, which are high relative to the comparable values of Es ∼3 kV/cm and Es ∼35 kV/cm for GaAs and Si. The saturation field for the AlGaN/GaN heterostructure 2DEG is less than for either 6H- or 4H-SiC.

3.4 Transistor amplifier operating principles

Zs = Rs + jXS

Pin

Pout

Z in

Z out

115

IL VL

Network

ZL = RL + jXL

Vs

Figure 3.4 General two-port network used for amplifier analysis.

Hole mobilities in SiC and GaN-based materials are very low, and on the order of 10–50 cm2 /V-s, and it is very difficult to observe saturation effects for hole transport. Extremely low mobility requires very high saturation fields, which approach the critical field for avalanche breakdown. Low mobility also results in high values for resistance, which limits device performance. The low hole mobility presents serious problems for use of p-type wide bandgap material in devices. For this reason, most devices under development are majority carrier devices, such as FETs and static-induction transistors that can be fabricated using only n-type semiconductor material.

3.4

Transistor amplifier operating principles The basic configuration for an amplifier is shown in Figure 3.4 [73]. The amplifier is a two-port network that consists of a source that feeds the input with a load connected to the output. The network has gain and thereby amplifies a signal passing through it from the source to the load. RF power can only be generated from a real source (i.e., resistance) and delivered through a network to a real load (i.e., resistance). Since electronic devices and networks, as well as most microwave sources and loads, also include reactance it is necessary to employ reactive tuning to obtain optimum power transfer. Conjugately tuned output and load impedances deliver maximum RF output power from the source to the load. The power delivered to the load, PL , from the network can be written as PL =

 1 1  Re VL I L∗ = |I L |2 R L 2 2

(3.1)

where VL and IL are the voltage and current at the load impedance, and RL is the real part of the load resistance. The power delivered to the load can be written as a function of the reflection coefficient at the load,   PL = Pout 1 − | L |2

(3.2)

where Pout is the RF power available from the network and L is the reflection coefficient at the load. Maximum RF power transfer occurs for no reflection from the load, L = 0

(3.3)

Wide band gap transistors – SiC and GaN – physics, design and models

0.7 0.6 Drain Current (A)

116

−1 dB Compression

0.5

−3 dB Compression

0.4 0.3 0.2 0.1 0

Linear

−0.1 0

5

10 15 20 Drain Voltage (V)

25

Figure 3.5 Dynamic current-voltage load lines superimposed upon the DC I–V characteristics for a GaAs MESFET amplifier (the three dynamic load lines indicate operation for linear, −1 dB, and −3 dB compression conditions) [5].

This condition occurs when the load impedance is set to the complex conjugate of the network output impedance ∗ Z L = Z out

(3.4)

The amplifier PAE is P AE =

(G − 1) PL − Pin x100% = Pin x100% Pdc Pdc

(3.5)

where Pin is the RF power into the network, PDC is the DC power dissipated in the network, and G is the network gain, expressed as G=

PL Pin

(3.6)

The dynamic characteristics of an amplifier using a GaAs MESFET as the active device are illustrated in Figure 3.5, which shows dynamic load lines (i.e., I–V characteristics) for three conditions: linear operation; −1 dB in compression; and −3 dB in compression. The dynamic load lines are superimposed upon the DC I–V characteristics for the active device. For the situation shown in Figure 3.5 the GaAs transistor is biased with a drain-source voltage of Vds = 8 V, and the network is tuned for maximum PAE for each dynamic load line. Since RF power can only be generated by a real source and delivered to a real load, the dynamic load line would be a straight line oscillating up and down the DC load line for the network. However, since the device has capacitance, the dynamic load line demonstrates elliptical behavior. While the device is operating below saturation the load line is confined within the DC I–V characteristics. As the device is driven into saturation the dynamic load line shifts and extends outside the DC I–V characteristics on both the high-current and low-current portions of the RF cycle. The average value of the RF current also increases, indicating that the device DC current increases as the device is driven into saturation. The extension of the dynamic load line outside the DC I–V characteristics is possible due to the complex nature of the network. The total RF current consists of conduction and displacement components and

3.4 Transistor amplifier operating principles

117

although the conduction current is limited by the I–V characteristics, the displacement current maintains current continuity at the terminals. That is, as the device is driven into saturation the conduction current is clipped by the I–V characteristics for the device, but the total RF current continuity is maintained by displacement current. Device capacitance increases as it is driven into saturation and inductive tuning is necessary to obtain optimum RF performance. Optimizing the inductive external impedance to match the capacitive impedance of the transistor results in the reversal of dynamic load line direction, as shown in Figure 3.5. Under optimum tuning conditions the network is essentially a resonant circuit with the reactive energy shifting between the capacitive and inductive fields. As the network is driven further into saturation the current clipping behavior increases, with a net increase in both DC current and device capacitance. The dynamic behavior of the amplifier network defines the factors that determine the RF performance limits of the device and the materials from which it is fabricated. The power delivered to the load is a product of the RF voltage and RF current that can be established at the load, and this is determined by the active device. Semiconductors are limited in the bias voltage that can be applied by the critical electric field for breakdown of the semiconductor material. Therefore, semiconductors that have high critical electric fields for breakdown are desirable for power device applications. The critical field for breakdown is a function of bandgap energy and wide bandgap semiconductors are desirable for power applications. The I–V characteristics shown in Figure 3.5 can be used to explain the basic classes of amplifier operation. For example, if the transistor is biased at a DC voltage and DC current located near the middle of the I–V characteristic plane, and the input and output impedances are tuned so that the dynamic RF I–V characteristic is confined completely within the I–V characteristic plane, the amplifier will operate under class A conditions. The transistor is always in an ‘on’ state and the maximum PAE is 50%. By changing the gate (or base) bias to reduce the DC drain (or collector) current the dynamic I–V characteristic will begin to clip on the high-voltage portion of the RF cycle. The waveform clipping will result in no channel conduction current, but the RF waveform will be maintained by capacitive current. The reduction in the drain current will produce a reduction in the DC power dissipation within the transistor, and the waveform clipping will produce a reduction in the RF power delivered to the load. However, the reduction in the DC power dissipation occurs more rapidly than the reduction in the RF output power, with a result that the PAE increases. For a bias condition where one half of the RF waveform is clipped, the RF output power will decrease by a factor of two (−3 dB). The ideal PAE for this mode has a theoretical value of 78.5%. Although the PAE is increased, the half-sinusoid current waveform produces harmonics at the output, although it is linear in the sense that an x dB increase in the input power results in an x dB increase in output power until the device is driven sufficiently hard to cause clipping of the top of the current waveform. Linearity is very important for amplifiers designed for communications systems. Using two transistors in a push–pull configuration, where each transistor is in the ‘on’ state for one-half of the RF cycle, doubles the output power and hence extends the linear range while maintaining the high PAE. The penalty is

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Wide band gap transistors – SiC and GaN – physics, design and models

the requirement for the additional transistor, along with the necessary RF circuitry to accomplish the final circuit. For operation between the class A mode and the ideal class B mode, the RF waveform is partially clipped and the PAE will be somewhere between 50% and 78.5%. This mode is generally termed class A-B, and many practical transistor amplifiers are designed to operate in this mode. This is necessary because real transistors have a soft-turn-on characteristic and so if operated in a pure class B mode then they are nonlinear at small signals and show a gain expansion region before saturating and then eventually entering the traditional nonlinear gain compression region. A very high-PAE mode can be obtained by biasing the transistor well below the voltage that permits channel conduction current to flow. In this mode, termed class C, the transistor only conducts during the peak of the voltage during the RF cycle. The current waveform becomes essentially a pulse. The ideal theoretical efficiency for class C is 100%, although this is only obtained with no power delivered to the load. Practical class C amplifiers, however, can be designed to operate with PAE in the 80–90% range. Electronic devices designed for microwave and RF applications operate in a transittime mode and are scaled in size by frequency considerations. Under normal operation the electric fields within the devices vary from low magnitude near the electron injection location to a magnitude sufficient to produce electron velocity saturation in the charge control/modulation region. Therefore, large current capability requires semiconductor materials that have high electron velocity. In general, both high-mobility and highsaturation velocity are desirable for high RF current. Traditional semiconductors such as Si and GaAs have electron saturation velocities that are limited to about vs = 1 × 107 cm/s, and this limits both the power that can be generated and the frequency response of the device. Wide bandgap semiconductors have electron saturation velocities that can be a factor of two higher. The combination of high-current and high-voltage capability make wide bandgap semiconductors very attractive candidate materials for fabrication of high-power and high-performance electronic devices.

3.5

Device design and RF performance The most promising devices for high-power, high-frequency RF applications are the 4H-SiC MESFET and the AlGaN/GaN HFET. Since the 4H-SiC MESFET can be fabricated entirely from n-type material the losses associated with use of p-type SiC can be avoided. The device is also relatively easy to fabricate due to a simple structure. The basic MESFET structure consists of a highly doped n-type epitaxial layer grown upon a highly resistive substrate, as shown in Figure 3.6. The drain-to-source current is thereby confined to the highly doped n-type layer. A control electrode (the gate) is located between the source and drain electrodes, which are designed to have ohmic current-voltage characteristics. The gate electrode is a nonlinear Schottky contact, which in normal operation is reverse biased, which creates a depletion region in the conducting channel, thereby permitting control of the drain-to-source current. Modulation of the voltage applied to the gate electrode permits the channel current to be modulated, and since a large channel current can be modulated with a small gate voltage, a large

3.5 Device design and RF performance

119

Figure 3.6 SiC MESFET structure.

n+ cap

n+ cap

Figure 3.7 AlGaN/GaN HFET structure.

transconductance (i.e., gain) is achieved. The magnitude of the transconductance and the upper frequency of operation of the device scale with reductions in gate length, and for this reason short gate lengths are desirable. In practice, gate lengths on the order of Lg ∼0.1–1 μm are routinely realized, and this permits operation with good gain to be realized above X and Ku-bands for SiC-based MESFETs. The AlGaN/GaN HFET is also readily fabricated and demonstrates excellent RF performance. These devices are similar to the MESFET, but differ in the semiconductor layer structure. A HFET structure is shown in Figure 3.7. Typically, an undoped layer of GaN is grown upon a highly resistive substrate, often SiC. A GaN buffer layer is often used to account for the lattice mismatch between the SiC and GaN layers. A thin updoped AlGaN layer is then grown upon the undoped GaN layer. The energy band discontinuity between the AlGaN and GaN layers creates an energy ‘notch’ at the heterointerface, and this results in the creation of a 2D electron gas (2DEG), which establishes a conducting path between the drain and source electrodes, which are fabricated in an analogous manner to the MESFET. A Schottky gate contact is located between the drain and source electrodes, as in the MESFET, and the same scaling rules apply. However, since the

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Wide band gap transistors – SiC and GaN – physics, design and models

0.7 +Vgs = –1 V 0.6

Ids (A)

0.5

Vgs = –2 V

0.4 0.3

Vgs = –5 V

0.2 Vgs = –8 V

0.1 0 0

10

20

30

40

50

Vds (V)

Figure 3.8 DC I–V characteristics for a SiC MESFET (Nd = 1017 cm−3 , Lg = 0.5 mm,

W = 1 mm) [5].

electron transport characteristics are much superior in the nitride heterointerface 2DEG compared to the bulk SiC, the AlGaN/GaN HFET is capable of much improved RF frequency performance. In fact, the nitride devices are capable of RF operation with good gain well above 100 GHz. In the next section the DC and microwave performance of these devices is described, and performance projections are presented. The investigation makes use of theoretical simulations and the results are compared to experimental measurements. Excellent agreement between the simulated and measured data is obtained. Once the device simulator is calibrated and verified against experimental data, the simulator is used to determine the performance for optimized device structures. The optimized device structures are tuned in Class A and Class A/B amplifier networks to investigate predicted performance.

3.5.1

4H-SiC MESFET amplifier The MESFET, since it is a majority carrier device, is an ideal transistor for fabrication using wide bandgap semiconductors [7]. The DC I–V characteristics for a MESFET fabricated from 4H-SiC and with gate length Lg = 0.5 μm and gate width W = 1 mm are shown in Figure 3.8. The device has been optimized for microwave performance in X-band and has a uniform channel impurity doping density of Nd = 5 × 1017 cm−3 and a channel thickness of a = 0.15 μm. The conducting channel is grown on a high-resistivity, semi-insulating substrate. The transistor produces a maximum channel current of Idss = 550 mA and a maximum transconductance of gm = 65 mS/mm, which is low by GaAs MESFET standards where the transconductances are generally in the range of several hundred mS/mm for an X-band transistor. The I–V characteristics indicate a knee voltage where the channel current saturates, with a drain voltage of about 9 V, which is high by GaAs MESFET standards where the devices typically saturate at less than a volt.

3.5 Device design and RF performance

121

40

H21 (dB), Gmax (dB)

35 30 25 20 Gmax 15 10 H21 5 0 1

100

10 Frequency (GHz)

Figure 3.9 Current gain (H21 ) and power gain (Gmax ) small-signal RF performance versus frequency for a SiC MESFET amplifier [5].

Po (dB m), PAE (%), G (dB)

60 PAE

50 40

Po

30 20

G

10 0 0

5

10

15

20

25

30

35

40

Pin (dB m)

Figure 3.10 Large-signal RF performance versus RF input power for a SiC MESFET amplifier (Freq = 10 GHz, Vds = 40 V, Class A operation).

The small-signal current (h21 ) and power gains (Gmax) for the device are shown in Figure 3.9. Although the transconductance for the 4H-SiC MESFET is low by GaAs MESFET standards, the device produces a gain-bandwidth product of fT = 24 GHz and a maximum frequency of oscillation of fmax = 56 GHz. The fmax is high due to a high-magnitude output impedance, which permits high-voltage gain to be developed. The small-signal RF parameters shown in Figure 3.9 indicate that the device is capable of producing good RF output power through X-band, and potentially higher. This is demonstrated in Figure 3.10, which shows the operation of the transistor when operated in a Class A amplifier circuit. The amplifier is biased at Vds = 40 V and is tuned for maximum PAE at 10 GHz. The amplifier produces a maximum RF output power of

Wide band gap transistors – SiC and GaN – physics, design and models

60 PAE (%), Po (dB m), G (dB)

122

50 PAE 40 Po

30 20

G

10 0 0

5

10

15

20

25

30

35

Frequency (GHz)

Figure 3.11 RF performance versus frequency for a SiC MESFET amplifier (Vds = 40 V, Class A operation).

5 W/mm with a maximum PAE of 50%, the ideal value for Class A operation. The linear gain of the amplifier is 14.8 dB. These results are excellent and superior to those obtained from a comparable gate width GaAs MESFET, which can only produce RF output power on the order of ∼1–1.5 W/mm. The relatively low electron mobility of SiC and high-saturation knee voltage of the transistor do not limit the RF performance of the device because the 40 V drain bias that can be applied is sufficient for the region under the gate to operate in velocity saturation conditions and efficient gate modulation of the channel current is maintained [72]. The gate breakdown voltage for this transistor is Vg dB = 100 V, thereby permitting the 40 V drain bias to be applied without encountering RF breakdown phenomena. The small-signal RF parameters indicate that the amplifier should operate above the X band. To explore the performance of the amplifier as a function of frequency it is operated over a frequency range extending from 3 GHz to 30 GHz and tuned for maximum PAE. The results are shown in Figure 3.11. As indicated the amplifier produces near ideal class A performance through X-band (12 GHz). At 12 GHz the amplifier produces 4 W RF power with 48% PAE and 10 dB linear gain. Above X-band the gain and PAE decrease due to increased losses that result from the low electron mobility. The PAE decreases from 48% at 12 GHz to 26% at 30 GHz. The high-frequency gain is significantly reduced and at 30 GHz is only about 3 dB, which is too low for practical use. These results stem from extensive investigations and have been calibrated and verified with experimental results. The study indicates that 4H-SiC MESFET amplifiers will be useful through X-band, but will have limited application at higher frequencies. The low mobility of SiC produces relatively high access region and contact resistances that severely limit RF performance at frequencies above X-band.

3.5 Device design and RF performance

123

60 Po (dB m), PAE (%), G (dB)

PAE 50 Po

40 30 20

G 10 0 0

5

10

15

20

25

30

35

Frequency (GHz)

Figure 3.12 Large-signal RF performance versus frequency for an AlGaN/GaN HFET amplifier (Vds = 25 V, Class A operation).

3.5.2

AlGaN/GaN HFET amplifier FETs fabricated using the AlGaN/GaN heterostructure offer the potential to produce a class of devices with excellent DC and RF performance. The charge density and electron transport characteristics of the 2DEG at the heterointerface between the AlGaN and GaN layers are excellent, with very high sheet-charge density on the order of 1013 cm−2 routinely realized. This magnitude is typically a factor of five higher than for the AlGaAs/GaAs 2DEG used in GaAs-based HEMTs. The sheet-charge density is higher than would be expected from standard 2DEG theory and this has been shown to be due to piezoelectric and spontaneous polarization effects. The 2DEG at the AlGaN/GaN heterojunction has excellent charge transport characteristics and the saturation velocity has a magnitude of about 1–2 × 107 v/cm and mobility in the range of 1000–1500 cm2 /Vs at room temperature. The combination of high sheet-charge density and high carrier velocity result in high current capability for the transistor. In practice, high channel current is obtained from these structures, and AlGaN/GaN HFETs with maximum channel currents over 1 A/mm and approaching 2 A/mm are routinely obtained experimentally. The simulated microwave performance as a function of frequency for an optimized AlGaN/GaN HFET Class A amplifier tuned for maximum PAE is shown in Figure 3.12 [7]. The transistor has a gate length of Lg = 0.5 μm, and a width of W = 1 mm and is biased at Vds = 25 V and Vgs = −4 V. This gate bias would be expected from the DC I–V characteristics to place the amplifier in class A operation. However, due to rectification effects under overdriven large-signal operation the transistor bias point shifts as a function of frequency and the amplifier shifts between class A and class AB operation from 3 GHz to 18 GHz. This is evidenced by the PAE, which was over 50% from 3 GHz to 25 GHz. The PAE peaked at about 58% from 12 GHz to 18 GHz. At frequencies above 18 GHz the PAE decreases to about 44% at 30 GHz due to increased

Wide band gap transistors – SiC and GaN – physics, design and models

60 Po (dB m), PAE (%), G (dB)

124

50 PAE 40 Po 30 20 G 10 0 0

5

10

15 20 Frequency (GHz)

25

30

35

Figure 3.13 Large-signal RF performance versus frequency for an AlGaN/GaN HFET amplifier optimized for high RF output power (Vds = 25 V, Class A operation) [5].

losses. The amplifier produces RF output power of about 3–5 W over the frequency range of 3 GHz to 30 GHz, which is excellent for a HFET with a 1 mm gate width. The linear gain is above 10 dB from 3 GHz to 18 GHz, and is still at 9 dB at 30 GHz. FETs can be designed to maximize RF output power, gain, or PAE, but it is, in general, not possible to obtain optimum performance for all three parameters simultaneously [74]. For the transistor described here, the modification of the structure for increased channel current and with retuning of the input and output impedances for an optimized combination of performance measures, it is possible to get an RF output power on the order of 10–12 W/mm while maintaining high PAE at high operating frequencies, as shown in Figure 3.13. In fact, even higher RF output power could be obtained, but at the expense of PAE and gain, which rapidly degrade as operating frequency is increased. In fact, a spot RF output power density greater than 30 W/mm at 4 GHz has been reported [45] for a transistor having Lg = 0.5 μm with a drain bias of Vds = 120 V. The breakdown voltage for the transistor was reported to be VdB = 170 V, which indicates that significant channel breakdown occurred on the high voltage portion of the RF cycle. Nevertheless, the peak PAE was 54.8% with an associated gain of 14 dB. For the results shown in Figure 3.13, the device is biased at Vds = 40 V and the gate bias is adjusted for Class A operation, which results in good PAE. The PAE is about 50% from 3 GHz to 10 GHz, and declines monotonically above X-band. However, at 30 GHz the PAE is still 30%. The gain remains above 10 dB up to about 25 GHz, and is still 8 dB at 30 GHz. By retuning for reduced PAE and gain it is possible to further increase the RF output power to slightly greater than 12 W/mm. These results indicate that AlGaN/GaN HFETs are capable of excellent DC and RF power performance well into the mm-wave frequency spectrum, and potentially well above 100 GHz. Excellent W and E-band RF performance has been reported [71, 75], and an E-band amplifier produced 500mW output power with 12 dB associated gain with about 10% PAE. With transistor power combining technology amplifiers with hundreds

3.6 Transistor DC and large-signal RF models

Iin

Vin

125

Iout Two-Port Network

Vout

Figure 3.14 Small-signal two-port network.

to thousands of watts of RF output power should be achievable. These amplifiers may be capable of competing with vacuum tube amplifiers in many applications.

3.6

Transistor DC and large-signal RF models Mathematical models for transistors find wide application for both device structure optimization and circuit design applications. Basically, there are two major types of model in practice: (1) equivalent circuit oriented models that are used in DC and RF circuit and system design applications; and (2) models that are based upon semiconductor device physics. The equivalent circuit based models require that the transistor be fabricated and characterized before the model can be defined. However, once defined, the model can be used in RF circuit and system design applications and it provides a means to investigate RF circuit performance and optimization without the need to actually fabricate the circuit until an optimized design is determined. The equivalent circuit models have been extensively developed and a variety of models are now readily available in virtually all commercially available simulators. The equivalent circuit based models are only accurate over the range of parameters for which they were defined, and often fail when extended outside these parameters. For this reason, new models are continually being derived and reported in the literature. The physics-based models offer an alternate approach. These models are based upon the fundamental semiconductor device equations and can be used to investigate the physical operation of the transistor before fabrication occurs. In this manner, the physics-based models can be used to investigate anomalous physical phenomena that are observed to occur in the transistor under various operating conditions, as well as for device design optimization applications. The physics-based models are, in general, more difficult to develop and require more intense computer resources for solution. The models are significantly more difficult to integrate into circuit and systems level simulators, and most of these models have been developed as stand-alone device level simulators. A variety of these simulators is commercially available and are very useful, particularly for device design optimization applications.

3.6.1

Equivalent circuit transistor models Equivalent circuit models for transistors follow from linear two-port circuit analysis. For example, a linear two-port can be represented by the block diagram shown in Figure 3.14. The input to the circuit block has input current and voltage, iin and vin ,

126

Wide band gap transistors – SiC and GaN – physics, design and models

Cgd

Rg

Rd

g Cgs

gm τ

Ri

rds

d

Cds

Rs s

Figure 3.15 Small-signal tee-equivalent circuit for FETs.

and the circuit block output has output current and voltage, iout and vout . Any two of the four variables may be selected as the independent variables, and the other two as the dependent variables and network equations established. For transistor applications it is common to select a combination of the input voltage, vin , and the output current, iout , as the dependent variables, and the input current, iin , and the output voltage, v out , as the independent variables. The network can then be described by the matrix equation      vin h 11 h 12 i in = (3.7) i out h 21 h 22 vout This formulation can be used to define the equivalent circuit model for the transistor. The various h-parameter terms take on a physical meaning. For example, the h11 term has units of resistance and represents the input impedance to the network when a shortcircuitis placed at the output terminals. Likewise, the h22 term has units of Siemens (inverse ) and is the output admittance when an open circuit is placed at the input terminals. The h21 parameter has no units, and represents the output current normalized to the input current, which is the forward current gain for the network. Likewise, the h12 parameter is the input voltage normalized to the output voltage, which is the reverse voltage gain for the network. Other formulations are possible depending upon the parameters selected as the dependent and independent variables. Since the entire network is linear, one set of parameters is easily converted to another through simple linear transformations. The formulation permits an equivalent circuit for the transistor to be established. All that needs to be done is to determine a configuration of circuit elements that replace the general network block and that generate the exact same dynamic response at the network terminals as the original circuit. Various circuit configurations can be developed, such as the hybrid-pi, or the T (tee) circuit. For microwave transistors the tee circuit is most commonly used. The basic circuit is shown in Figure 3.15, and various circuit elements are also included to indicate various parasitic elements associated with transistor operation. The equivalent circuit is ‘exact’ in that it accurately reproduces the linear electrical response of transistor performance and the main elements of the equivalent circuit can be directly derived mathematically from the original two-port network. The

3.6 Transistor DC and large-signal RF models

127

equivalent circuit is very useful for small-signal characterization of the transistor since the equivalent circuit element values can be directly determined from measured data by a parameter extraction process. Suitable routines are available and numerous practical techniques have been extensively reported in the literature. Parameter extraction software is commercially available from a variety of vendors. Nonlinear models for large-signal RF performance have been determined, based upon the linear equivalent circuit model for the transistor. However, this process is not exact, and it is, in general, not possible to theoretically derive an accurate nonlinear largesignal model directly from the linear equivalent circuit. Although many large-signal equivalent circuit models have been reported in the literature and are readily available in commercial RF circuit simulators, all of the models have been derived by developing nonlinear expressions for the various equivalent circuit elements and then using the resulting expressions to ‘define’ the large-signal equivalent circuit model. The procedure can become complex, and generally the linear equivalent circuit model is reduced to the most important, basic equivalent circuit elements, which are then characterized by nonlinear functions of various combinations of input and output current and voltage. The reduced equivalent circuit showing only the basic circuit elements is shown in Figure 3.16. The most important elements are the current generator and the input capacitance, and nonlinear expressions based upon power law, tanh(Vds ), Volterra Series, etc. formulations have been developed. As the model development progresses, additional elements in the equivalent circuit can be formulated as nonlinear functions and included in the model. The resulting equivalent circuit model can accurately predict the largesignal RF performance of the transistor, but requires that the parameters in the nonlinear expressions be determined. The only way this can be accomplished is by an experimental parameter extraction process whereby the nonlinear terms can be determined from measured data. The complete model can be complex, with the requirement to define many parameter values from the extracted measurement data. Many techniques for accomplishing this have been reported in the literature and most commercially available circuit and systems simulators include suitable large-signal parameter extraction routines. A major issue with the large-signal equivalent circuit models is that, since they are based upon experimental extraction of the nonlinear elements, they are generally accurate only for the range of parameters over which they have been calibrated. When the model is driven to regions outside the original characterization space, there is no reason to expect the circuit response to be accurate. In fact, the models often fail. For this reason new models are continually being developed and reported. Each iteration and new equivalent circuit model development effort is directed towards solution of a previously observed or reported failure. The new model, of course, also requires determination of the element parameter values by experimental extraction and calibration with measured data. The process requires that transistors be fabricated and characterized before a suitable model can be developed, and many transistor manufacturers routinely produce equivalent circuit models for their transistors. However, these manufacturer’s models generally only consider typical operating range data, and specific applications may require that a new model be defined. However, once the equivalent circuit models are determined they have proved very useful in circuit design applications.

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Wide band gap transistors – SiC and GaN – physics, design and models

Idg (Vout, Vin)

Cdg

Rg

Gate

Rd Drain

Cgs (Vin, Vout) Vin(t)

Igs (Vin)

Ids (Vin, Vout) Rds

Rin

Cds

Vout(t)

Rs Source Nonlinear Circuit Elements Idg (Vout – Vin)

Drain-gate voltage-controlled current source due to drain-gate avalanche breakdown

Igs (Vin)

Gate voltage-controlled current source due to forward biasing of the gate

Ids (Vin,Vout)

Drain-source voltage-controlled current source

Cdg (Vout – Vin)

Drain-gate capacitance

Cgs (Vin,Vout)

Gate-source capacitance

Cds (Vout)

Drain-source capacitance

Rin (Vin,Vout)

Gate-source charging resistance

Rds (Vin,Vout)

Drain-source resistance

Figure 3.16 Large-signal tee-equivalent circuit for FETs.

3.6.2

Physics-based large-signal transistor models An alternate approach to the development of transistor models is based upon solution of the basic semiconductor device equations. The semiconductor equations consist of: (a) the current density equations for electrons and holes, J n = qμn n E + q Dn ∇n

(3.8)

J p = qμ p p E − q D p ∇ p

(3.9)

and

where J is the current density, μ is the charge carrier mobility, n, p are the free electron and hole densities, and D is the diffusion coefficient.

3.6 Transistor DC and large-signal RF models

129

(b) The continuity equations for electrons and holes, 1 ∂n n − n0 + ∇ · J n = ∂t τn q

(3.10)

p − p0 ∂p 1 = − ∇ · J p ∂t τp q

(3.11)

and

where no and po are the thermal equilibrium density of electrons and holes, and τ n and τ p are the electron and hole recombination lifetimes. (c) Faraday’s Law, ∂ B ∇ × E = − ∂t

(3.12)

which completes the basic set of equations, where E and B are the electric and magnetic fields. These equations can be solved simultaneously to develop a model for a semiconductor device. Generally, solutions to these equations applied to a transistor structure are complex and difficult to solve analytically. However, the equations are readily solved using numerical techniques and a variety of simulators based upon either finite-difference or finite-element methods have been reported and are commercially available. These device level simulators permit detailed investigation of the physical operation of the device and can be used to both investigate phenomena observed in experimental measurements or they can be used for device design and optimization studies. In general, these simulators require significant solution time and are difficult to employ in circuit-level simulators. The physical models, however, can be extremely accurate as all phenomena known to affect device performance can be included. The physical models take as input data the device structure, semiconductor material and transport parameters, and bias conditions. The model can be set to take the voltage applied to the device terminals as input data and return the resulting currents that flow, or set up to take the current applied to the terminals as input data and return terminal voltages. The device input and output impedances can then be calculated from the terminal voltages and currents. The physical models are extremely flexible and can be modified to include phenomena that are found to affect device performance, such as charge trapping, breakdown mechanisms, surface and interface charging and discharging, and leakage currents, etc. Additionally, the device models can be modified to include transient and nonequilibrium phenomena, ballistic transport effects, and quantum physics behavior. These effects will increase the complexity of the model and generally increase the simulation time, but the resulting model can be made extremely accurate. Device simulators of this type find wide application in device investigations of operational physics, however, the models are generally not suitable for inclusion in circuit-level simulators. It is possible to generate a modified physics-based model that is suitable for integration into circuit and systems-level simulators [76]. In order to accomplish this, it is necessary to compromise the formulation between inclusion of pertinent physical phenomena and

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Wide band gap transistors – SiC and GaN – physics, design and models

solution efficiency. The goal is to produce a model that maintains the important physical phenomena that dominate device performance, while producing a model that can be very quickly and efficiently solved. In this manner the utility of the physics-based approach can be coupled with the simulation efficiency of the equivalent circuit-based approach. The model development proceeds by coupling a two-dimensional Poisson equation solution technique with a one-dimensional current density equation. By focusing the Poisson equation solution on the area under the gate electrode in a FET an analytic solution can be obtained [76]. The Poisson solution permits the electric field within the transistor to be calculated as a function of structure, impurity doping, and bias conditions. The electric field is then used to calculate the channel current density with use of the current density equation. This approach works well for structures where the channel is narrow so that the current flow is essentially one-dimensional. In fact, this model approach results in a physics-based transistor model that retains the accuracy of the physics-based approach, but can be solved in an efficient manner. The model can be integrated into circuit and systems-level simulators with great success. The simulation work reported in this chapter makes use of the model described above, which has been modified for use with wide bandgap semiconductor devices. Excellent results are obtained and the model very accurately predicts the DC and RF performance obtained experimentally.

3.7

Large-signal effects The wide bandgap semiconductor FETs are candidates for high-RF power applications since they can operate under high-voltage and high-current conditions. However, under these operating conditions the devices experience a variety of physical phenomena that affect their performance, and in some cases, produce deviations from the expected response. In most cases the phenomena are natural physical responses to the very high voltages and currents that occur under RF large-signal operation. The most significant of these phenomena are described in this section.

3.7.1

Space charge limited current transport Under high-current conditions the injected charge in a semiconductor can become comparable in magnitude to the background impurity density and space-charge limited transport can occur [77, 78, 79]. This condition can be achieved in practical devices under large-signal RF operation when high-magnitude input RF power is applied. The voltage that can be supported by a semiconductor device is limited by the internal resistance, and when high input power is applied, the injected current will increase to satisfy the boundary conditions imposed by the applied source. Generally, under these conditions the input impedance to the device is driven to a reduced magnitude, and although some of the input power is reflected by the reduced impedance of the device,

3.7 Large-signal effects

131

current injection increases. The injected charge and the internal electric field are related, as expressed by Poisson’s equation, dE q (3.13) = (Nd − n) dx ε where E is the one-dimensional electric field in the direction of current flow, Nd is the effective donor density that represents the positive polarization/piezoelectric charge in HFETs, n = n o + δn is the free electron density where n o is the thermal equilibrium density of charge, and δn is the density of injected charge. The thermal equilibrium density of electrons is essentially equal to the donor density (i.e., n o ∼ = Nd ) and when the injected charge becomes comparable in magnitude to the thermal equilibrium density of electrons Poisson’s equation is written as q q dE = (Nd − n o − δn) ∼ (3.14) = − δn dx ε ε Under high-injection conditions the electric field is reduced in magnitude as a function of increasing charge injection, and the resistivity and resistance of the semiconductor material become a function of current injection. This effect can become significant for semiconductor devices operated under high-current injection conditions. For low-level injection conditions where δn  no , the E field is essentially independent of injection level. In order to determine the conditions under which space-charge effects become significant, it is illustrative to solve equation (3.13) analytically. The current density is J = qnv

(3.15)

where J (A/cm2 ) is the magnitude of the current density and v (cm/s) is the nonlinear velocity–field curve, which is modeled as v=

μE 1 + |E| /E sat

(3.16)

where μ (cm2 /V s) is the low field mobility and E sat (V/cm) is the magnitude of electrical field that produces velocity saturation, expressed as Esat = vsat /μ = 8.0 kV/cm.

(3.17)

Equation (3.13) can be written in the form: λ dE J E + E sat = −1 + E sat d x Jsat E

(3.18)

where the λ parameter is λ=

εE sat q Nd

(3.19)

and has the dimensions of length. The λ parameter is typically very small for an AlGaN/GaN heterojunction 2DEG, since the effective doping is very high.

Wide band gap transistors – SiC and GaN – physics, design and models

D = 3.5 μm

0.8

D = 2.5 μm Resistivity (Ω-cm)

132

0.6 D = 1.5 μm 0.4

D = 0.5 μm

0.2

0 39

39.5

40

40.5

41

Current Density (MA/cm2)

Figure 3.17 Semiconductor resistivity versus current density at the onset of space–charge limited transport (the various curves indicate resistivity determined at locations from the current injection point) [77].

The solution of equation (3.18) depends on its magnitude at x = 0 which should reflect a combination of low E and high n. For the limiting case E(0) = 0, equation (3.18) has a solution:    (Jsat −J )2 x E sat J (3.20) E(x) = 1 + W −e−1− Jsat J λ Jsat − J that can be simply written in terms of the principle real branch of the Lambert W function for J < Jsat and the other real branch of W for J > Jsat . In equation (3.20), the length scale L J = λ Jsat J (Jsat − J )2

(3.21)

is larger than the length scale λ of equation (3.19) but is still less than an Angstrom for ∼ J = 12 Jsat . L J diverges near J = Jsat . The resistivity, ρ = E J , as a function of distance from the source for semiconductor fabricated using an AlGaN/GaN heterojunction 2DEG is shown in Figure 3.17. The resistivity is essentially independent of J until a critical threshold current, JSC , is achieved. In this example JSC ≈ 39.6 MA/cm2 . For a current density in excess of JSC the resistivity increases rapidly both with current, and with distance from the source injection point. Therefore, once space-charge limited transport conditions are established, the resistivity of a semiconductor will rapidly increase, and the effect is more significant with the length of the semiconductor region. The analytic solution of equation (3.18) is continuous at J = Jsat but its character changes. For J < Jsat , E(x) ∼ = E sat J (Jsat − J ) is almost independent of x except in the

3.7 Large-signal effects

region 0 < x < L J where E(x) ∝ linearly with x. Furthermore,

√

133

(J −J ) x. For J > Jsat , E(x) ∼ = x εvsatsat increases almost

E(x) = E sat J (Jsat − J )

(3.22)

is a second exact solution of equation (3.18) for J < Jsat , in addition to being an approximation of equation (3.20) in the region x > L J near the gate edge. In contrast to equation (3.20), however, equation (3.22) is not continuous at Jsat and is not physical at J = Jsat . This peculiar situation raises the possibility of mode-switching between the continuous solution and the constant solution. The mode-switching transition may occur for L J > L sg , when the length scale L J of equation (3.21) exceeds the length of the access region. This transition would be abrupt in practical devices where L sg is ˚ on the order of a micron and is much larger than λ = .32

A, the length parameter of equation (3.19), because L J > L sg only for J Jsat > 1 − λ L sg as J approaches Jsat . The magnitude of the JSC threshold current is approximately given by the expression JSC ∼ = q Nd vsat

(3.23)

and for a heterojunction 2DEG, it is assumed that Nd ∼ = n ss / h, where h is the width of the 2DEG quantum well. For a typical AlGaN/GaN 2DEG space-charge effects are expected to set in for a threshold current in the range of JSC ≈ 40 MA/cm2 . This is lower than the current density measured in experimental devices. Practical devices generally have a maximum drain current of Ids ≈ (1 − 1.2) A/mm, and for a quantum well width ˚ the current density is in the range of J ≈ 50 MA/cm2 . This indicates of about h = 25 A, that these devices most likely operate under space-charge limited conditions, particularly during the high-current portion of the RF cycle. In addition, the magnitude of JSC is expected to vary with n ss and vsat , and these parameters vary in magnitude with DC and large-signal RF operating conditions. The magnitude of JSC , therefore, can vary with HFET bias and RF drive, and this increases the nonlinearity of the gate-source resistance for an HFET under large-signal drive.

3.7.2

Nonlinear source and drain resistance The onset of space-charge limited current transport in a microwave HFET under largesignal operation will cause the source and drain resistances to significantly increase during the high-current portion of the RF cycle. Although both the source and drain resistances are affected, the increase in source resistance has the most significant effect upon transistor performance. The drain resistance is essentially in series with the relatively high-magnitude output load resistance and, therefore, the increase in the device drain resistance has minimal effect upon device performance. The source resistance, however, is common to the transistor input and output, as indicated in the tee-equivalent circuit, as shown in Figure 3.16, and any increase in source resistance will degrade the transconductance of the transistor by reducing the voltage that drives the current generator. For this reason it is imperative to reduce the source resistance in a FET to the greatest

134

Wide band gap transistors – SiC and GaN – physics, design and models

Cgsi

gmi

Rgs

Figure 3.18 Simplified equivalent circuit for a FET with a nonlinear source resistance.

Cgsext

gmext

Figure 3.19 Simplified equivalent circuit for a FET with the nonlinear source resistance transformed to the gate capacitance and transconductance.

possible extent. The increase in source resistance due to the onset of space-charge limited transport conditions will degrade transistor performance, both by decreasing the gain capability of the transistor, and by introducing undesirable nonlinearity. The effect of the nonlinear source resistance can be seen by reducing the equivalent circuit in Figure 3.16 to its basic circuit elements, as shown in Figure 3.18. This equivalent circuit can be transformed to the equivalent circuit shown in Figure 3.19 by rewriting the element values as gm i (3.24) gm ext = 1 + Rgs gm i + jω R gs C gsi and C gsext =

C gsi . 1 + R gs gm i + jω Rgs C gsi

(3.25)

In these expressions gm ext and C gsext are the transconductance and gate-source capacitance that are observed at the input to the equivalent circuit in Figure 3.18 and gm i and C gsi are the transconductance and gate-source capacitance intrinsic to the transistor, and represented by the equivalent circuit shown in Figure 3.19. For low frequencies, these equations simplify to gm i gm ext ∼ (3.26) = 1 + Rgs gm i and C gsext ∼ =

C gsi . 1 + Rgs gm i

(3.27)

According to equations (3.26) and (3.27), both the transconductance and gate-source capacitance observed at the terminals of the transistor will decrease as the gate-source resistance increases. The decrease in C gsext is particularly interesting, since this indicates that the magnitude of the input impedance to the HFET will increase as the device is driven into saturation. This is opposite to the normal operation of a FET, where the input impedance is driven to a lower magnitude as the device is driven into saturation.

3.7 Large-signal effects

135

2

Cgs (pF)

1.5

1 Eqn( ) Cgs_4_0_20 0.5

Eqn( ) Cgs_4_0_30

0 –4

1

6

11

16

21

Pin (dB m) (GHz)

Figure 3.20 Measured gate–source capacitance as a function of RF input power for an AlGaN/GaN HFET for Vds = 20 V, and Vds = 30 V.

The behavior indicated in equation (3.27) is supported by measured data, as shown in Figure 3.20. In this figure the measured input capacitance as a function of input RF power drive is shown for an AlGaN/GaN HFET. The increased RF power drive causes increased channel current, which has a magnitude sufficient to exceed the threshold for spacecharge limited current transport. The SCL current conditions produce an increase in the gate-source resistance, which produces the reduction in C gsex as expressed in equation (3.27). The C gsex magnitude is reduced by almost a factor of two over the measured range of input power, and this produces an increase in the device input impedance by a corresponding factor. The SCL current transport phenomenon has the desirable result of increasing the terminal impedances, which make it easier to design the transistor input amplifier, and other circuits. The onset of space-charge limited current can theoretically affect both depletion mode HFETs, as well as enhancement mode MOS type FETs (e.g., Si LDMOS FETs). The depletion mode HFETs have an inherent advantage of lower input capacitance compared to the enhancement mode FETs for a constant RF output power and supply voltage due to geometrical factors (e.g., thicker dielectric layers that result in the conducting channel being located farther from the gate electrode). It should be noted that the onset of space-charge limited current and the increase in the gate-source resistance under large-signal operation conditions has not been observed in the normal operation of Si LDMOS FETs or compound semiconductor MESFETs and HEMTs. The affect is commonly observed and appears to dominate in the nitride-based HFETs, most likely due to the higher current densities and internal electric fields under which the wide bandgap semiconductor nitride-based HFETs operate. The measured and simulated performance of the source and drain resistances as a function of current for an AlGaN/GaN HFET are shown in Figure 3.21. As shown, once

Wide band gap transistors – SiC and GaN – physics, design and models

12

10 Simulated 8 Rs, Rd (Ohm)

136

Measured

6 Rs 4 Rd 2

0 –0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

Drain Current (A)

Figure 3.21 Measured and simulated source and drain resistances as a function of drain current for an AlGaN/GaN HFET.

space-charge limited current transport conditions are achieved the source and drain resistances demonstrate current-dependent characteristics and increase with current drive. In fact, simulations indicate that under high-current drive conditions the source and drain resistance for the HFET can increase by up to an order of magnitude. The effect of a nonlinear source resistance upon on an HFET amplifier circuit can be significant. This can be shown by a circuit simulation in which a nonlinear, currentdependent source resistance is included [77, 80]. For this study, a harmonic-balance simulator that includes a physics-based FET model [76] is used. The HFET device model has been modified by inclusion of a source resistance in the form Rs = rss + rss =

rss 1−

I

,

(3.28)

I SC

where Rs is the source resistance, rss is the low-current magnitude of the resistance in the gate-source region, r ss is the increase in resistance after the onset of spacecharge effects, and I SC is the space–charge threshold current previously discussed. The nonlinear source resistance is a function of the time-dependent RF current and is included on the time domain, nonlinear side of the harmonic-balance interface. In this manner the source resistance is a function of the conduction current in the transistor. The modified simulator was used to investigate the DC and RF operation of a communications band AlGaN/GaN HFET amplifier. The HFET device had a gate length and width of L g = 0.8 μm and W = 0.4 mm, respectively. The device was biased with a drain voltage of Vds = 28v and was operated class A-B at a frequency of F = 2.14 GHz. The device demonstrated premature gain compression and was, therefore, selected as a

3.7 Large-signal effects

137

0.4 Vgs = +1 V

Vgs = 0 V

Drain Current (A)

0.3

Vgs = –1 V 0.2 Vgs = –2 V

0.1 Vgs = –3 V Vgs = –4 V 0 0

5

10

15

20

25

Drain Voltage (V)

Figure 3.22 Measured and simulated DC I–V characteristics for an AlGaN/GaN HFET

(Lg = 0.8 mm, W = 0.4 mm) [77].

candidate to determine if a nonlinear source resistance could explain the gain compression behavior. The measured and simulated DC I–V characteristics for the HFET are shown in Figure 3.22. As indicated in Figure 3.22, excellent agreement between the measured and simulated data is obtained. In the simulation a low-field mobility of μ = 1500 cm2 /V − sec and an electron saturation velocity of vsat = 1.25 × 107 cm/sec were used. The mobility was measured and the saturation velocity was adjusted to get agreement with the measured I–V characteristics. The saturation velocity used is below the theoretical value for electrons in an AlGaN/GaN 2DEG, but is consistent with measured data. Without inclusion of the current-dependent nonlinear source resistance, the simulated current increasingly deviated from the measured data as the gate bias voltage was increased from pinch-off and adjusted for increasing channel current. The measured and simulated RF performance and the DC drain and gate current as a function of input power to the amplifier are shown in Figures 3.23, 3.24, and 3.25, respectively. In the simulation seven harmonics were used in the harmonic-balance routine. The amplifier was tuned for maximum PAE. Excellent agreement between the measured and simulated device performance and the DC drain and gate current are obtained. The amplifier produced a peak PAE of 53%, with RF output power of 34 dBm and a gain of 19 dB. The linear gain for the amplifier was 25 dB. The experimental amplifier demonstrated premature gain compression and a degradation of gain beginning at an input power of slightly below about 0 dBm. Significantly, the simulated results accurately predict the change in slope of the gain response, as shown in Figure 3.23. The

Wide band gap transistors – SiC and GaN – physics, design and models

55 Sim. Po Meas. Po Sim. G Meas. G Sim. PAE Meas. PAE

50

Po (dB m) Gain (dB) PAE (%)

45 40 35

Nonlinear Source Resistance Onset

30 25 20 15 10 5 0 –10

–5

5

0

10

15

20

Input Power (dB m)

Figure 3.23 Measured and simulated RF output power, gain, and PAE versus RF input power for an AlGaN/GaN HFET amplifier (freq = 2.14 GHz, Vds = 28 V, Class AB) [77].

0.18 0.16

Simulated Measured

0.14 Drain Current (A)

138

0.12 0.1 0.08 0.06 0.04 0.02 –10 –8 –6

–4 –2

0

2 4 6 8 10 Input Power (dB m)

12 14

16

18 20

Figure 3.24 Measured and simulated DC drain current versus RF input power for an AlGaN/GaN HFET amplifier (freq = 2.14 GHz, Vds = 28 V, Class AB) [77].

3.7 Large-signal effects

139

0.001 0.0008

Gate Current (A)

0.0006 0.0004 0.0002 0 –0.0002 –0.0004 –10 –8 –6 –4 –2

0

2

4

6

8

10 12 14 16 18 20

Input Power (dB m)

Figure 3.25 Measured and simulated DC gate current versus RF input power for an AlGaN/GaN HFET amplifier (freq = 2.14 GHz, Vds = 28 V, Class AB).

2

Pin = 14.8 dB m Pin = 0.0 dB m

Gate Voltage (V)

0 –2 –4 –6 –8 –10 0 (a)

50

100

150

200

250

300

350

400

450

500

Time (ps)

Figure 3.26a RF gate voltage versus time response for an AlGaN/GaN HFET amplifier (the two waveforms indicate operation at the onset of space–charge-limited transport, and under maximum PAE).

simulator predicts both the change in gain slope at Pin = 0 dBm, and the gain saturation that occurs after maximum PAE is achieved. The change in gain slope is caused by the onset of space-charge limited current transport conditions. The time domain voltage and current waveforms at the gate and drain terminals are shown in Figures 3.26 and 3.27. Figures 3.26a and 3.26b show the voltage

Wide band gap transistors – SiC and GaN – physics, design and models

0.2 Pin = 14.8 dB m Pin = 0.0 dB m

0.15

Gate Current (A)

0.1 0.05 0 –0.05 –0.1 –0.15 –0.2 0

50

100

150

200

(b)

250

300

350

400

450

500

Time (ps)

Figure 3.26b RF gate current versus time response for an AlGaN/GaN HFET amplifier (the two waveforms indicate operation at the onset of space-charge-limited transport conditions, and under maximum PAE.

60 50 Drain Voltage (V)

140

Pin = 14.8 dB m Pin = 0.0 dB m

40

30

20

10

0 0 (a)

50

100

150

200

250 300 Time (ps)

350

400

450

500

Figure 3.27a RF drain voltage versus time response for an AlGaN/GaN HFET amplifier (the two

waveforms indicate operation at the onset of space–charge-limited transport conditions, and under maximum PAE).

and current waveforms at the gate terminal under low drive (Pin = 0 dBm) and large-signal operating conditions where the input power is sufficient to produce maximum PAE. The same waveforms at the drain terminal are shown in Figures 3.27a and 3.27b.

3.7 Large-signal effects

141

0.4 0.35

P in = 14.8 dB m P in = 0.0 dB m

Drain Current (A)

0.3 0.25 0.2 0.15 0.1 0.05 0 –0.05 0 (b)

50

100

150

200

250

300

350

400

450

500

Time (ps)

Figure 3.27b RF drain current versus time response for an AlGaN/GaN HFET amplifier (the two waveforms indicate operation at the onset of space–charge-limited transport conditions, and under maximum PAE).

For the low RF drive Pin = 0 dBm condition, the gate voltage and current are essentially low-amplitude sinusoids, as expected. Since the Pin = 0 dB drive condition is sufficient to produce some saturation, a slight deviation from pure sinusoidal behavior is noted, particularly in the RF voltage. The shift in phase in the gate RF voltage waveform at the higher drive condition shown in Figure 3.26a is due to the shift in gate-source capacitance at the higher drive levels, as previously discussed. As the device is driven into saturation the gate voltage grows in amplitude and shows the effects of harmonic generation. The gate RF current waveform shown in Figure 3.26b becomes highly nonlinear as the device is driven into saturation, and the seven harmonics are clearly evident. The mechanism that causes the nonlinearity is not evident in the gate terminal waveforms. The gate voltage does not obtain a magnitude sufficient to cause either forward or significant reverse conduction of the gate electrode. Some reverse conduction does occur and this generates a small, but finite, DC reverse conduction in the gate electrode. The small negative reverse gate conduction was observed in both the experimental data and the simulation. However, the small amount of reverse conduction is not sufficient to clip the gate RF current waveform and generate the nonlinear behavior observed in the waveform in Figure 3.26b. The RF voltage and current waveforms at the drain terminal are shown in Figures 3.27a and 3.27b, respectively. Again, the waveforms for the low-drive and maximum PAE conditions are shown. The low-drive RF drain voltage waveform shown in Figure 3.27a indicates the onset of saturation, and slight deviation from sinusoidal behavior is observed. The large-signal RF waveform demonstrates significant clipping, both at low and high RF voltages, and the waveform becomes more “squared” in shape. The clipping at the low-drain voltages is caused by the total RF terminal voltage dropping

Wide band gap transistors – SiC and GaN – physics, design and models

5 Nonlinear Source Resistance (Ohm)

142

4.5 4

P in = 14.8 dB m P in = 0.0 dB m

3.5 3 2.5 2 1.5 1 0

50

100

150

200

250

300

350

400

450

500

Time (ps)

Figure 3.28 Source resistance versus time response for an AlGaN/GaN HFET amplifier (the two waveforms indicate operation at the onset of space–charge-limited transport conditions, and under maximum PAE).

below the RF knee of the I–V characteristic, and the clipping at high drain voltages is caused by the onset of RF breakdown in the conducting channel. The RF drain current waveforms are shown in Figure 3.27b. The large-signal RF current demonstrates the “squaring” behavior caused by the drain voltage waveform clipping mechanisms that occur at low and high voltage magnitudes. The RF voltage and current are essentially out-of-phase, with the current magnitude being high when the voltage magnitude is low, and vice versa. The waveform clipping generates harmonics, which are clearly observed in the large-signal RF current. The RF drain current shown in Figure 3.27b consists essentially of conduction current, which flows through the conducting channel from the source to the drain. When the threshold for space-charge limited flow is reached the resistance of the material will become a function of the magnitude of the current and the gate-source resistance will become nonlinear. The magnitudes of the source resistance under the low drive and large-signal conditions are shown in Figure 3.28. The onset of space-charge dependent resistance is observed for the Pin = 0 dBm input drive condition during the high-current portion of the RF cycle. The source resistance increases from a DC magnitude of Rs = 1.85  to a peak magnitude of about Rs = 2.4 . However, under large-signal conditions the source resistance becomes highly nonlinear and increases significantly during the high-current portion of the cycle. Since the RF drain current shown in Figure 3.27b is composed essentially of conduction current, the magnitude of the source resistance is directly dependent upon this current. The magnitude of the source resistance increases from the DC magnitude of Rs = 1.85  to almost Rs ∼ = 5  during the peak of the RF drain current. Increasing the drain voltage results in an increased magnitude of the nonlinear source resistance during the high-current portion of the RF cycle, as shown

3.7 Large-signal effects

143

Nonlinear Source Resistance (Ohm)

10 9 8 7

vds = 28 V vds = 38 V vds = 48 V

6 5 4 3 2 1 0

50

100

150

200

250

300

350

400

450

500

Time (ps)

Figure 3.29 Source resistance versus time response for an algan/gan HFET amplifier at maximum PAE conditions for Vds = 28 V, 38 V, and 48 V.

in Figure 3.29. In this figure the results obtained by increasing the drain voltage from Vds = 28 V, to Vds = 48 V are shown. For Vds = 48 V the source resistance increases by almost an order of magnitude during the high-current portion of the RF cycle compared to the small-signal value. The nonlinear behavior of the source resistance helps explain the behavior of the RF gate current shown in Figure 3.26b. Although the RF gate current is composed essentially of displacement current, the gate circuit requires conduction through the gate-source region, which is normally a low-value resistance, and the magnitude of the RF gate current is dependent upon the magnitude of the source resistance. The harmonic generation due to the clipping of the RF drain current is transferred to the gate circuit and the magnitude of the gate current is, therefore, affected by the magnitude of the source resistance. The input impedance to the transistor is essentially a series combination of the gate-source capacitance and the nonlinear source resistance. The nonlinear source resistance has a significant effect upon the operation of the device. The source resistance essentially couples the input gate circuit to the output drain circuit for the device, as shown in the equivalent circuit shown in Figure 3.18. The drain current generator is driven by the voltage generated across the gate-source capacitance, according to the expression, i out = gmi vgs e− jωτ

(3.29)

where i out is the HFET RF output current, gmi is the intrinsic transconductance (mS), τ (s) is a delay time, and vgs is the RF voltage across the gate–source capacitance. The transconductance that is developed at the device output is reduced by the source resistance, according to equation (3.26), as previously discussed.

144

Wide band gap transistors – SiC and GaN – physics, design and models

@ Surface of AlGaN Layer

E (V/cm)

E (V/cm)

@ Mid-Point of Conducting Channel

Microns

Microns

E = 2 × 106 V/cm

Figure 3.30 Electric field magnitude versus distance at the mid point of the conducting channel and at the surface of the AlGaN Layer for an AlGaN/GaN HFET (the top curve is the total E field and the bottom curve is the x-directed E field. The dotted lines indicate the critical E field for breakdown in GaN.) [79].

3.7.3

Gate leakage When a high drain bias voltage is applied and the HFET is driven with a large RF signal the peak voltage at the drain can obtain a magnitude essentially twice the magnitude of the bias voltage. Detailed simulations indicate that the magnitude of the electric field at the edge of the gate electrode on the drain side can easily exceed Ec∼6–8 MV/cm, as shown in Figure 3.30, which is sufficient to produce quantum mechanical electron tunneling. The curves in Figure 3.30 indicate the electric field at the mid-point of the conducting channel and at the surface of the AlGaN layer. Both the magnitudes of the total electric field and the x-directed (i.e., in the direction of current flow) electric field are shown. The dotted line indicates the assumed breakdown voltage, which is in the range of Ec∼2 MV/cm. As indicated, both the total and x-directed electric field for the stated operating conditions significantly exceed the breakdown voltage. The electric field at the gate edge near the surface has a magnitude on the order of E∼8 MV/cm, which is sufficient to produce significant electron tunneling. Experimental data indicates that electron tunneling, in fact, occurs. The electrons that tunnel from the gate electrode can (a) accumulate on the surface of the semiconductor next to the gate, (b) conduct along the surface by a trap-to-trap hopping mechanism, creating a gate-to-drain leakage current, or (c) possibly travel through the AlGaN layer to the 2DEG conducting channel, as shown in Figure 3.31. Measured data indicate that the surface leakage path is dominant under practical operating conditions,

3.7 Large-signal effects

145

Electrostatic feedback Surface Leakage (Primary mechanism) Gate

AIGaN

Electron Tunneling

Gate/Channel Leakage (Secondary mechanism)

Electrostatic depletion

2DEG GaN

Figure 3.31 Gate electron leakage paths in an AlGaN/GaN HFET [79].

and the path through the AlGaN layer only occurs for extreme conditions following defect creation that can occur under high electric fields, etc. In addition, if the energy of the electrons is sufficiently high, they can cause avalanche ionization on the surface next to the gate. When this occurs electrons tunnel from the gate metal to the semiconductor surface area adjacent to the gate with sufficient energy to cause avalanche ionization, which is accompanied by light emission from the gate edge. Light emission from the gate edge is often observed in the large-signal operation of GaAs MESFETs and InP-based HEMTs, and has been observed in AlGaN/GaN HFETs under certain operating conditions. This indicates that surface breakdown occurs in the nitride devices and can be a factor affecting reliability. Avalanche ionization also occurs in the conducting channel of these devices and is a factor in the RF operation of the device when operated under large-signal drive. RF channel breakdown is, in fact, a factor that affects gain saturation in the HFET devices. When the electrons accumulate on the surface of the semiconductor at the gate, a “virtual gate” effect is created, where the gate effectively increases in length as the electron tunneling proceeds and the density of electrons on the semiconductor surface increases. The electrons that accumulate on the surface of the semiconductor create an electrostatic charge that produces a partial depletion of the conducting channel electrons, thereby causing a reduction in the channel current, and a corresponding decrease in RF output power. The electron tunneling and charge accumulation continue as a function of time. This mechanism is the primary physical basis for the nondestructive reliability problem associated with these devices. Typical performance degradation is shown in Figure 3.32, which shows the measured DC channel current and RF output power as a function of time. The increasing electrostatic charge acts to suppress further tunneling of the electrons from the gate metal, thereby limiting the effect. In this manner, the mechanism is self-limiting. The measured DC conduction current degradation shown in Figure 3.32 correlates with a degradation in RF output power. The current conduction characteristics vary with time and with device design, surface processing, and passivation, and varying power degradation results are obtained. It is possible to modify and reduce the tunnel leakage by the use of optimized field-plate device designs, and by the use of passivation, which minimizes the RF power degradation. With proper and optimized passivation, DC current

146

Wide band gap transistors – SiC and GaN – physics, design and models

Change in Idss (%)

10

0

–10

–20 0

100

200

300

(a)

400 500 600 Stress Time (hr)

700

800

900

700

800

900

Change in Pout (dB)

1

0

–1

–2 0 (b)

100

200

300

400

500

600

Stress Time (hr)

Figure 3.32 (a) Measured change in channel current (Idss ) and (b) RF output power versus time for

an AlGaN/GaN HFET (various lines indicate different devices included in the measurement) [79].

and RF output power degradation can be minimal, at least for limited ranges of DC bias voltage.

3.7.4

Reliability and time-dependent performance degradation One of the dominant reliability problems experienced by nitride-based HFET devices has been linked to gate leakage [79, 80]. Although gate leakage is not the only problem affecting device reliability, it is a first-order problem that needs to be solved before these devices find widespread application. The problem is manifested as a time-dependent decrease in drain current and RF output power, as shown in Figure 3.32, and has been primarily addressed through surface passivation techniques. The degradation is observed to vary significantly with surface passivation processes and from manufacturer to manufacturer. Also, gate leakage is not the only mechanism that results in drain current and RF output power degradation but it was among the first to be addressed. The phenomenon is reversible and does not produce permanent damage

3.7 Large-signal effects

147

Gate tunnel leakage

Itun Irev

Id

Ig Gate

t – τt

Drain [C] Icon

Ichbd Rd

Ifor

Rs

RF channel breakdown

Source

Figure 3.33 Large-signal HFET model used in the performance simulations [79].

or degradation to the device, and a period of inactivity generally results in the device returning to its initial performance. However, this recovery has also been observed to be a false recovery as when stress is reapplied to the device, it quickly degrades to its last degraded state. Additionally, under certain operating conditions, a “sudden reliability” problem has been observed [81], where permanent degradation in device performance occurs. Devices that experience this problem are characterized by high-magnitude gate leakage. A model for gate tunnel leakage in GaAs MESFETs has been reported [82]. This model has been modified for use with AlGaN/GaN HFETs, and the modified model can be used in a harmonic-balance simulator to investigate the gate tunnel mechanism as a function of DC and RF operating conditions. The model is shown in Figure 3.33. The gate tunnel leakage is represented as a current generator between the gate and drain electrodes. The model also includes RF breakdown within the conducting channel, which is represented by a current generator between the drain and source. This model accurately simulates the DC and RF performance of AlGaN/GaN HFETs, and the simulated and measured RF performance for a class A-B 2.14 GHz communications band AlGaN/GaN HFET amplifier are shown in Figure 3.23, and the measured and simulated Ids and Igs as a function of input power were shown in Figures 3.24 and 3.25, respectively. As shown in Figure 3.25, the gate conducts a small, but finite and negative leakage current for the entire range of input power, until the gate junction is driven into forward conduction at an input RF power of about Pin = 17 dBm. The model is in excellent quantitative agreement with the measured data for the reverse leakage conduction characteristics of the gate, and in qualitative agreement for the forward conduction, but slightly underestimates the input power required to drive the gate into forward conduction. As electrons tunnel from the gate to the AlGaN surface they can accumulate next to the gate electrode. The space charge from the electrons provides an electrostatic feedback to the gate that works to suppress the tunnel leakage, as shown in Figure 3.31.

Wide band gap transistors – SiC and GaN – physics, design and models

Electrostatic feedback

ntun (t )

Surface charge Nd Surface conduction

NTA

AIGaN

Figure 3.34 Gate electron tunnel leakage and surface conduction model [79, 83].

6.40E-02

6.30E-02 NTA = 2 × 1011 cm–2 6.20E-02 Ids (A)

148

6.10E-02

6.00E-02

NTA = 5 × 1011 cm–2

5.90E-02 0

200

(a)

400

600

800

1000

Time (s)

Figure 3.35a Simulated DC channel current versus time for two values of the acceptor-like surface

trap (NTA) density [79, 83].

This introduces time dependence to the gate leakage, with a corresponding time dependence associated with the RF power degradation. This effect can be modeled by introduction of a surface conduction layer that permits a variable surface charge, as shown in Figure 3.34. The NTA term represents the acceptor-like surface trap density, and can be expressed as NTA = Nd − n tun (t),

(3.30)

where Nd is the surface conduction layer charge density, and ntun (t) is the time-dependent tunnel charge density. In this model, the electrons that tunnel and accumulate next to the gate effectively reduce the density of the surface conduction electrons in this region and permit a varying surface trap density next to the gate to be determined. The model shown in Figure 3.34 reproduces the drain and gate currents observed in measured data. Measured and simulated time-dependent DC drain and gate currents are shown in Figure 3.35a and 3.35b, respectively, for two values of the acceptor-like surface trap density. Note that as the electrons accumulate on the surface near the gate, the magnitude of the tunnel leakage current is affected and the gate and drain currents become time-dependent. As the NTA density varies, the degree of electrostatic feedback is affected, with corresponding effects upon the gate leakage current, and the drain current degradation.

3.7 Large-signal effects

–2.28E-05

149

NTA = 5 × 1011 cm–2

–2.32E-05 –2.36E-05 Ig (A)

–2.40E-05 –2.44E-05

NTA = 2 × 1011 cm–2

–2.48E-05 –2.52E-05 –2.56E-05 –2.60E-05 0 (b)

200

400

600

800

1000

Time (s)

Figure 3.35b Simulated DC gate current versus time for two values of the acceptor-like surface trap (NTA) density[79, 83].

The magnitude of the electric field at the gate edge is a function of the device design and the magnitude of the terminal voltages experienced by the device while in operation. A reduction in the electric field will reduce the gate leakage current. AlGaN/GaN HFETs produce a very high-magnitude electric field at the gate edge due to the high sheet carrier concentration in the 2DEG. Very low channel resistance results, and minimal potential drop occurs along the channel region from the drain to the gate until the gate depletion region is encountered. Essentially the entire drain potential is supported over the narrow depletion region and a very high-peak E field results. Techniques to reduce the magnitude of the electric field at the gate edge include the use of field-plates, n-doped GaN cap layers, controlled polarization-induced surface charges [81], and modifications of the 2DEG sheet-charge density. Two main current paths for gate leakage currents can be identified. The main path is established by electron tunnel leakage from the gate, with electrons flowing along or near the AlGaN surface to the drain contact. The electron conduction occurs by a trap-to-trap hopping mechanism, where both thermionic emission and tunneling are likely involved, as illustrated in Figure 3.36. Simulations indicate that it is likely that the exact conduction mechanism changes as the electric field increases due to high DC and RF terminal voltages. This performance degradation process is essentially reversible and nondestructive, and removal of the bias and drive signals, with a period of device inactivity, causes the device to return to its initial state. However, as previously indicated, reapplication of DC and RF voltages often result in the device returning to a degraded state, which indicates that some permanent damage has occurred. The second current path consists of electron tunneling from the gate, with electron flow through the AlGaN layer to the 2DEG conducting channel. This current path requires a higher electric field, and often produces permanent damage to the AlGaN semiconductor lattice, with increased gate leakage. The lattice damage is observed in TEM images.

Wide band gap transistors – SiC and GaN – physics, design and models

Electrons can accumulate creating ‘virtual gate’ Strained Energy Band Electron tunneling E parameters Nss, M *tun

Thermionic Emission Tunnel Emission

Vdg = 0 EF

ΔG

s Surface hopping parameters ΔG, s Vdg = V Gate Metal

AIGaN Surface

Figure 3.36 Detailed model for gate-tunnel leakage and surface trap-to-trap hopping conduction [79].

0.2 Vg s = 0 V

0.18 0.16 0.14 Ids (A/mm)

150

0.12 Solid Lines: Measured Data Points: Simulation Data

0.1 0.08 0.06

Vg s = –2.5 V

0.04 0.02

Vg s = –5 V

0 0 (a)

1

2

3

4

5 Vds (V)

6

7

8

9

10

Figure 3.37a Measured and simulated DC I–V characteristics for an AlGaN/GaN HFET using the gate-tunnel leakage and surface conduction model [79, 83].

Using the gate tunnel leakage and surface conduction model it is possible to simulate the drain and gate current characteristics with excellent accuracy in comparison to measured data [83, 84]. For example, the model shown in Figure 3.34 produces the drain and gate I–V characteristics shown in Figure 3.37. Figure 3.37a and Figure 3.37b show the measured and simulated drain current and gate current for a AlGaN/GaN HFET. The gate tunnel leakage and surface conduction model accurately predicts the gate leakage and surface conduction current and accurately simulates both the drain and gate current

3.7 Large-signal effects

151

0.00E+00 Vgs = –1 V –2.00E-05 Vgs = –3 V

Ig (A)

–4.00E-05 –6.00E-05

Vgs = –5 V –8.00E-05 –1.00E-04

Vg s= 7 V (measured) Vg s= 5 V (measured) Vg s= 3 V (measured) Vg s= 1 V (measured) Vg s= 7 V (simulated) Vg s= 5 V (simulated) Vg s= 3 V (simulated) Vg s= 1 V (simulated)

Vgs = –7 V

–1.20E-04 0.00E+00 2.00E+00 4.00E+00 6.00E+00 8.00E+00 1.00E+00 Vds (V)

(b)

Figure 3.37b Measured and simulated DC gate current characteristics for an AlGaN/GaN HFET using the gate-tunnel leakage and surface conduction model [79, 83].

48.5 48

Id (m/A)

47.5 47 46.5 46 45.5 45 44.5 0 (a)

100

200

300

400

500

Time (s)

Figure 3.38a Measured and simulated DC drain current versus time for an AlGaN/GaN HFET including the effects of gate tunnel leakage and surface conduction (points are measured data and the line is simulated data) [79, 83].

characteristics. The model can be extended to time-dependent conditions, as shown in Figure 3.38 [83, 84]. Figures 3.38a and Figure 3.38b show the measured and simulated time-dependent DC gate and drain currents, respectively. The simulations are performed with a model that includes the effects of electrostatic feedback from the electrons that tunnel to the surface of the AlGaN layer adjacent to the gate electrode. The simulation results are compared to experimental data and excellent agreement between the measured and simulated data is obtained. The electrostatic feedback reduces the electric field at the edge of the gate electrode, thereby reducing the electron tunnel leakage. As electrons accumulate at the gate edge as a function of stress time, the feedback produces reduced gate leakage current. Also, the increased electron

152

Wide band gap transistors – SiC and GaN – physics, design and models

0 –0.001

Ig (m/A)

–0.002 –0.003 –0.004 –0.005 –0.006 –0.007 0 (b)

100

200

300

400

500

Time (s)

Figure 3.38b Measured and simulated DC gate current versus time for an AlGaN/GaN HFET including the effects of gate tunnel leakage and surface conduction (points are measured data and the line is simulated data) [79, 83].

density on the AlGaN surface partially depletes the 2DEG electrons, and a reduction in gate current occurs.

3.8

Summary Wide bandgap semiconductors, that is SiC and nitride-based heterostructures, can be used to fabricate high-frequency transistors with RF power performance superior to those fabricated from GaAs or Si. The most promising RF devices are FETs fabricated from 4H-SiC and HFETs fabricated from the AlGaN/GaN heterostructure. Optimized 4H-SiC FETs can produce RF output power on the order of 4–5 W/mm, which is a factor of four greater than obtainable from GaAs devices. Amplifiers fabricated from 4H-SiC MESFETs will be useful, particularly for RF applications in S and C-band communications, and potentially for X-Band radars. The AlGaN/GaN HFET can produce RF power density on the order of 10–12 W/mm, with very good PAE. Prototype nitride-based HFETs have produced a spot RF output power density as high as 30 W/mm, although this required drain bias of Vds = 120 V. The high mobility and sheet-charge density of the AlGaN/GaN heterostructure permit the fabrication of HFETs with excellent high-frequency performance, and devices that can operate up to and potentially exceed 100 GHz have been demonstrated. For both 4H-SiC and AlGaN/GaN HFETs poweradded efficiencies approach the ideal for operation up to X-band in both Class A and B operation. For X-band and below the SiC and AlGaN/GaN transistors are competitive with each other, and both produce RF output power superior to GaAs-based and InP-based transistors, while providing equivalent gain and PAE. Above X-band the AlGaN/GaN HFETs will dominate. However, improved thermal design is required to obtain the theoretically predicted performance, particularly for AlGaN/GaN HFETs, which are generally fabricated from material grown on SiC substrates. Both 4H-SiC and AlGaN/GaN devices are likely to find application in power amplifiers for base

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station transmitters for wireless communications, HDTV transmitters, power modules for phased-array radars, and other applications. The devices are particularly attractive for applications that require high RF output power and operation at elevated temperature. These solid state devices should provide an alternative to the use of microwave vacuum tubes in many transmitter applications. The wide bandgap semiconductor transistors, due to their inherently high input and output impedances, are attractive for use in power-combining, broad bandwidth, and phased-array radar applications.

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62. Y. Ando, Y. Okamoto, H. Miyamoto, T. Nakamura, T. Inoue, and M. Kuzuhara, “10-W/mm AlGaN-GaN HFET with a field modulating plate,” IEEE Electron Dev. Lett., vol. 24, pp. 289–291, May 2003. 63. R. Vetury, Y. Wei, D. S. Green, S. R. Gibb, T. W. Mercier, K. Leverich, P. M. Garber, M. J. Poulton, J. B. Shealy, “High power, high efficiency, AlGaN/GaN HEMT technology for wireless base station applications,” IMS Dig., pp. 487–490, 2005. 64. Y. Kamo et al., “A C-band AlGaN/GaN HEMT with Cat-CVD SiN passivation developed for an over 100 W operation,” IEEE IMS Tech. Dig., pp. 495–498, 2005. 65. T. Kikkawa, et al., “An over 200 W output power GaN HEMT push-pull amplifier with high reliability,” IEEE IMS Tech. Dig., pp. 1347–1350, 2004. 66. W. Nagy, S. Singhal, R. Borges, J. W. Johnson, J. D. Brown, R. Therrien, A. Chaudhari, A. W. Hanson, J. Riddle, S. Booth, P. Rajagopal, E. L. Piner, and K. J. Linthicum, “150 W GaN-on-Si RF power transistor,” IEEE IMS Tech. Dig., pp. 483–486, 2005. 67. R. Therrien, S. Singhal, J. W Johnson, W. Nagy, R. Borges, A. Chaudhari, A. W. Hanson, A. Edwards, J. Marquart, P. Rajagopal, C. Park, I. C. Kizilyalli, K. J. Linthicum, “A 36 mm GaN-on-Si HFET producing 368 W at 60 V with 70% drain efficiency,” IEEE IEDM Tech. Dig., 2005. 68. O. Kruger, G. Schone, T. Wernicke, R. Lossy, A. Liero, F. Schnieder, J. Wurfl, and G. Trankle, Laser-assisted processing of VIAs for AlGaN/GaN HEMTs on SiC substrates,” IEEE Electron Dev. Lett., vol. 27, pp. 425–427, June 2006. 69. K. Krishnamurthy, J. Martin, B. Landbert, R. Vetury, and M. J. Poulton, “Wideband 400 W pulsed power GaN HEMT amplifiers,” IEEE CSIC Symp. Dig., pp. 303–306, Monterey, CA, Oct. 12–15, 2008. 70. S. Piotrowicz, E. Morvan, R. Aubry, S. Bansropun, T. Bouvet, E. Chartier, T. Dean, O. Drisse, C. Dua, D Floriot, M.A. diForte Poisson, Y. Gourdel, A. J. Hydes, J .C. Jacquet, O. Jardel, D. Lancereau, J. O. McLean, G. Lecoustre, A. Martin, Z. Quarch, T. Reveyrand, M. Richard, N. Sarazin, D. Thenot, and S. L. Delage, “State of the art 58W, 38% PAE X-Band AlGaN/GaN HEMTs microstrip MMIC amplifiers,” IEEE CSIC Symp. Dig., pp. 1–4, Monterey, CA, Oct. 12–15, 2008. 71. M. Micovic, A. Kurdoghian, H. P. Moyer, P. Hasimoto, M. Hu, M. Antcliffe, P. J. Willadsen, W. S. Wong, R. Bowen, I. Milosavljevic, Y. Yoon, A. Schmitz, M. Wetzel, C. McGruire, B. Hughes, and D. H. Chow, “GaN MMIC PAs for E-Band (71 GHz-95 GHz) radio,” IEEE CSIC Symp. Dig., pp. 1–4, Monterey, CA, Oct. 12–15, 2008. 72. R. J. Trew, “Wide bandgap semiconductor transistors for microwave power amplifiers,” IEEE Microw. Mag. vol. 1, pp. 46–54, March 2000. 73. R. J. Trew, “High frequency solid state electronic devices,” IEEE Trans. Electron Dev., Special Issue on Vacuum Electronic Devices, pp. 638–649, May, 2005. 74. T. A. Winslow, R. J. Trew, P. Gilmore, and C. T. Kelley, “Simulated performance optimization of GaAs MESFET amplifiers,” Proceeding of the Thirteenth Biennial Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, Ithaca, NY, Aug. 1991, pp. 393–402. 75. M. Micovic, A. Kurdoghlian, H. P. Moyer, P. Hashimoto, M. Hu, M. Antcliffe, P. J. Willadsen, W. S. Wong, R. Bowen, I. Milosavljevic, Y. Yoon, A. Schmitz, M. Wetzel, C. McGuire, B. Hughes, and D. H. Chow, “GaN MMIC PAs for E-band (71 GHz–95 GHz) radio,” IEEE Compound Semiconductor Integrated Circuits Symposium (CSICS), pp. 1–4, Oct. 2008.

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76. M. A. Khatibzadeh and R. J. Trew, “A large-signal, analytic model for the GaAs MESFET,” IEEE Trans. Microw. Theory Tech., vol. 36, pp. 231–238, Feb. 1988. 77. R. J. Trew, Y. Liu, G. L. Bilbro, W. W. Kuang, R. Vetury, and J. B. Shealy, “Nonlinear source resistance in high voltage microwave AlGaN/GaN HFET’s,” IEEE Trans. Microw. Theory Tech., vol. 54, pp. 2061–2067, May 2006. 78. G. L. Bilbro and R. J. Trew, “RF knee walkout and source access region of unpassivated HFET’s,” Electronics Lett., vol. 42, pp. 1425–1426, Nov. 2006. 79. R. J. Trew, D. S. Green and J. B Shealy, “AlGaN/GaN HFET reliability,” IEEE Microw. Mag., vol. 10, pp. 116–127, June 2009. 80. R. J. Trew, Y. Liu, W. W. Kuang, and G. L. Bilbro (invited), “The physics of reliability for AlGaN/GaN HFETs,” Compound Semiconductor Integrated Circuits Symp. (CSICS) Dig., San Antonio, TX, Nov. 13–15, 2006. 81. Y. Inoue, et al., “Degradation-mode analysis for highly reliable GaN-HEMTs,” 2007 IEEE IMS Dig., pp. 639–642. W. Kuang, R. J. Trew, and G. L. Bilbro, “Modeling of surface defect related gate leakage in AlGaN/GaN HFET,” Materials Research Society (MR) Spring Meeting, San Francisco, CA, April 9–13, 2007. 82. T. A. Winslow and R. J. Trew, “Principles of large-signal MESFET Operation,” IEEE Trans. Microwave Theory Tech., vol. 42, pp. 935–942, June 1994. 83. W. Kuang, R. J. Trew, and G L. Bilbro, “An analytical model for surface leakage currents of AlGaN/GaN HFETs and effects upon device reliability,” WOCSDICE, IMEC, Leuven, Belgium, May 18–21, 2008. 84. R. J. Trew, Y. Liu, W. Kuang, and G. L. Bilbro (invited), “Reliability modeling of high-voltage AlGaN/GaN and GaAs field-effect transistors,” Proc. of SPIE, vol. 6894, 1H1–7, 2008.

4

Amplifier classes, A to S1 Steve Cripps Cardiff University

4.1

Introduction The alphabetical classification of electronic amplifiers appears to date back to the earliest era of electronics, and as such could well be approaching the centenary mark. Its survival to the present day represents a remarkable continuity, given the vast changes in technology that have taken place in the intervening decades. It can also represent a distraction for the modern RFPA designer working with solid state active devices and GHz frequencies, both of which were well below the horizon when the original classification came into general use. The plan in this chapter is to introduce and define the various Classes,1 and then consider how the original intent is often modified in typical modern applications, sometimes to the point where the original concept migrates into something palpably different. Although the definitions of Class A, AB, B, and C are well established and have a long historical precedent, the subsequent Classes (D, E, F, etc.) are of much more recent origin and in some cases have suffered from different interpretations by different authors. A curious but endemic feature of this subject is the assertive use of classifications by authors and designers when the final amplifier current and voltage waveforms have not been (and in many cases cannot easily be) measured directly. This has been known to lead to considerable controversy, given that some amplifier “Classes” have even been patented. Another issue which comes up when addressing this subject with a modern perspective is the intrusion of digital approaches to power amplification, primarily in the form of so-called “switch modes.” As active device technology improves, the frequency range at which it can be made to behave as a near-ideal switch increases. Until recently, this range could be reasonably restricted to the “HF” (MHz to tens of MHz) region, but newer technologies such as gallium arsenide and gallium nitride have extended this region into the “VHF” (hundreds of MHz), and more arguably into the “microwave” (GHz) region. There is thus something of a “gray” area, where a particular amplifier can be considered as a “smoothed-out” switch mode, or alternatively as a more conventional analogue PA class with some extra harmonic components. Both of these approaches will be described in the later sections on Class S, E, and J amplifier.

1

The word “Class” has such specific and specialised importance in this chapter that I will capitalize it throughout.

160

Amplifier classes, A to S

Efficiency is the central issue in the evolution of amplifier classes. The Class A amplifier can be considered to be a logical starting point, and will be described first. It has several positive attributes, notably simplicity of implementation, linearity, and high potential operating bandwidth. It does however have only moderate efficiency, even at maximum signal drive conditions, and this is what led early amplifier developers to explore Class AB modes, where the device is deliberately shut off for a portion of each RF signal cycle. This can have a dramatic effect in terms of increased efficiency, but almost always comes at a price of reduced overall linearity. As we progress through the alphabet in the PA idiom, this tradeoff between efficiency and linearity in general continues. A highly efficient Class C amplifier, for example, cannot be considered at all in applications having any form of amplitude modulation on the signal carrier. Since the start of the digital communications era, there has been a marked emphasis on linear RF power amplification, that is to say the system RFPA is required to amplify the signal in its final, fully modulated form. This represented something of a seachange for the RFPA industry, since in older systems it was more common to use the RFPA itself as a high-level modulator. Vacuum tubes appear to have been very amenable to the use of supply voltage variation as a means of imposing amplitude modulation (AM) on to the carrier. As silicon RF power transistors began to appear in the early 1960s, it seems that a major re-think took place, since these devices displayed highly nonlinear behavior under conditions of supply modulation. Conveniently (and, presumably, not serendipitously) there was a shift to “angle modulation” (frequency and phase modulation), especially in mobile transmitters, whereby the transmitter RFPA could be run at constant amplitude level. This allowed the ongoing use of efficient Class C-type amplifier designs and was something of a disincentive for device technology development towards more linear performance. But the more recent development of systems using complex, digitally based, modulation schemes has forced RFPA design, and the underlying device technology, to comply with stringent linearity specifications. There is nevertheless a counter-culture evident in the modern RFPA community, which seeks to reinstate the old regime. In principle, a digitally modulated signal can still be sent using only nonlinear RF amplification. The basic concept is to generate a constant envelope signal which carries the appropriate phase modulation, and then use supply modulation (and/or alternatives) to generate the required AM. The nonlinear relationship between the supply voltage and the output RF envelope amplitude can be managed in a modern system through the use of digital correction techniques, either on the tracking voltage itself, the signal envelope, or both. Such “LINC” (linear amplification using non-linear components) RFPA systems can in principle be much more efficient than the linear approach, although the efficiency at which the tracking voltage supply can be generated is a negative factor which must always be taken into account. LINC system design has thus renewed interest in the design of highly efficient amplifiers without the constraint of linearity. The classical solution of Class C mode is less attractive in solid state design, and this is the area in which switching, or quasiswitching RFPAs such as Classes D and E may well have a major role to play in future systems.

4.2 Active device models

161

Despite these possible future directions, the vast majority of RFPAs in current use have been designed for Class A (Section 4.3) or Class AB (Section 4.4) operation. Class A tends to predominate at higher GHz frequencies where applications usually demand highly linear performance, and RF bandwidths can be 10% or greater. Wireless communications systems, which typically use much narrower bandwidths, usually favour Class AB operation in order to maximize efficiency. Linearity requirements are, however, rapidly approaching those encountered in satellite communications and microwave link applications, and digital signal processing usually has to be employed in order to meet linearity specifications in Class AB operation. We note Class B (Section 4.4) somewhat in passing, as a singular point that divides Class AB from Class C (Section 4.5). Class F (Section 4.6) is something of the joker in the pack, in at least one sense, but has been the subject of much research over the last decade or so. It can be considered as a derivative of Class AB operation, and has been used in both linear and LINC applications. In a linear application, it can in principle increase the efficiency at peak power levels, without compromising linearity, but in practice poses some difficult circuit design issues, especially for higher power devices at GHz frequencies. In LINC applications it can challenge the efficiency of the more fashionable switch modes, and in specific cases may supply a higher output power due to better control of peak voltage. Other PA classes come and go according to the whims of researchers and patent attorneys, so as we proceed beyond Class F then definitions become a little harder to find, let alone to summarize. There are also some discrepancies between audio and RF electronics in the definition of some amplifier classes. The most notable of these is the Class D audio amplifier which is basically a pulse width modulator and is usually denoted as Class “S” at RF and Microwave frequencies (hence there is no section in this chapter on Class D). Also, in the audio world Class G and Class H are well defined but these terms have not come into general use at RF. Ironically, the audio definitions essentially utilize a technique known as “envelope tracking,” or ET, which is used at RF but has never been classified alphabetically. Section 4.11 attempts to summarize some of the “miscellaneous” categories.

4.2

Active device models In defining and analyzing RFPA Classes it is logical to adopt a common device model. At the outset, however, it has to be noted that RFPA devices fall into two distinct physical kingdoms, the bipolar transistor and the FET. Within these two kingdoms lie numerous genera; for example the most widely used bipolar device at GHz frequencies is the Heterojunction Bipolar Transistor, or HBT, but at higher power levels and lower (UHF) frequencies, the more traditional Si bipolar junction transistor (BJT) still survives. FET devices come in a somewhat greater diversity, both in terms of materials and structures. Gallium arsenide metal semiconductor FETs (GaAs FETs) dominated the GHz sector for several decades, somewhere between the late 1960s and the 1990s. More advanced material growing machinery such as molecular beam epitaxy (MBE) became commercially available in the early 1990s and led to the development of more

162

Amplifier classes, A to S

D

Imax

Ids

Vgs (linear steps)

G Ids Vgs

S

0 Vknee (<
Vmax

Figure 4.1 Ideal device model used for PA analysis.

optimum FET structures such as the high-electron mobility transistor (HEMT) and the pseudomorphic HEMT (pHEMT), but these were primarily still based on GaAs substrates. During the 2000s, gallium nitride has emerged as an “enfant terrible,” sporting high-voltage operation and potentially broader band operation than GaAs devices, albeit with no specific inherent frequency advantage. These various devices and technologies are described in earlier chapters of this book, but for the present purposes just about any of the FET devices will display a set of I–V characteristics as shown in Figure 4.1. These characteristics have been idealized for the purposes of maintaining a focus on the mode of operation. The ideality assumptions can be summarized as follows: r r r r

constant current-sink behavior outside the turn-on, or “knee” region; abrupt cut-off of current when the gate voltage drops below a “threshold” value; “saturation” of the current above a defined value, usually denoted by Imax ; linear relationship between output current and input voltage between the threshold and saturation points (in this chapter this will be called the “quasi-linear” region); r quasi-static behavior (same IV characteristics regardless of sweep speed).

In dealing with PA modes, an additional idealization is often deployed, which is to assume that the knee region has a negligible impact, and that the turn-on characteristic of the device can be ignored. This assumption is almost endemic among PA theorists, and can often represent the main underlying cause for discrepancies between measured results and theoretical performance predictions. For the purposes of this chapter we will, however, comply with the mainstream view which is to set Vk = 0.

4.3

Class A In Class A operation the device is kept entirely within the “quasi-linear” region. For maximum power performance, the device is supplied with a standing bias current of Imax /2 and the input signal voltage is constrained to swing between the limits of the quasi-linear range. Figure 4.2 shows the current and voltage waveforms for an ideal device with an input sinusoidal signal excitation.

4.3 Class A

163

2Vdc Vds Vdc

Imax Ids Idc

π

2π

3π 4π θ (= ω t, rad.)

Figure 4.2 Class A device waveforms.

The sinusoidal waveforms make the calculation of output power and efficiency very straightforward. The RF output power, Prf , is given by Imax Vdc Idc Vdc Prf = √ √ = 2 2 2 2

(4.1)

Pdc = Idc Vdc .

(4.2)

and the DC power supplied is

The “output efficiency” is defined as ηo =

Prf Pdc

(4.3)

so that in this case we obtain the classical result that the output efficiency of a Class A amplifier is 12 , or 50%. We note, however, that this much-quoted result will not apply in practice for any real device, due primarily to the “zero-knee” assumption. The effect of the knee voltage can be most simply expressed and quantified by assuming that the voltage swing will be maintained such that the minima do not encroach into the knee region, that is where Vds < Vk . So the RF output power under maximum drive conditions can be rewritten as Prf =

(Vdc − Vk ) Vdc − Vk Idc √ .Idc .√ = 2 2 2

and the corresponding efficiency becomes Vdc − Vk 1 ηo = = 2Vdc 2



Vk 1− Vdc

(4.4)

 .

(4.5)

The ratio Vk /Vdc is both technology and application dependent. If we survey the range of semiconductor technologies in current use at GHz frequencies, the ratio is approximately 0.1 in most cases, but this assumes that the device is being operated at its maximum rated

164

Amplifier classes, A to S

DC supply voltage. So in most practical cases the Class A efficiency can be expected to be no higher than about 45%. The above analysis applies only to a CW input signal which has the necessary magnitude to drive the device into a maximum current swing, that is over the full “quasi-linear” range from zero to Imax . In order to assess the efficiency for an amplitude modulated signal, it is necessary to obtain an expression for the efficiency under conditions of “power back-off” (PBO). This is an easy calculation to perform in the Class A case, since the DC bias remains constant, that is independent of the input drive conditions. So for a “backed-off” condition, where the RF output is Pbo , the efficiency will be ηbo =

Pbo Pdc

(4.6)

which can be expressed in terms of the RF output under full drive conditions, Pmax , as η pbo =

1 Prf . 2 Pmax

(4.7)

So the efficiency of a Class A amplifier backs off in direct proportion to the output power. For example, at the 6 dB back-off point, the efficiency is one quarter of the peak power efficiency. For a modulated signal that has a peak to average power ratio of 6 dB, an average efficiency in the 20–25% range is the best that can be expected from a Class A amplifier. This is an unacceptably low efficiency for many applications, and is the main reason Class A is not much used in wireless communications systems. The Class A mode does however have some advantages. Its linearity is usually good, due to the fact that the device is kept entirely within the quasi-linear range, where the nonlinearities are of the “weak” variety. The power gain is typically several dBs higher for a given device operating in Class A than in the more popular Class AB modes considered in the next section. For this reason, Class A operation becomes more widespread at higher frequencies, where the available devices deliver less than about 10 dB of gain in Class A. Class A amplifiers are also fairly easy to design, in that they do not require specific harmonic, as well as fundamental, matching. For this reason Class A is preferred for broadband (greater than octave) power amplifiers at GHz frequencies, although at subGHz frequencies the push–pull class B configuration [1] is widely used for multioctave bandwidths.

4.4

Class AB and Class B The use of a “reduced conduction angle” in the design of RF power amplifiers is well known, and also dates to the earliest era of electronics. As such we will not engage in lengthy preliminaries but consider the device waveforms shown in Figure 4.3. The key difference in moving from Class A to Class AB operation is that the quiescent bias current is changed to a lower relative value, often as low as about 10% of the Imax for the device. For a FET type device this can be easily implemented by moving the gate bias voltage closer to the threshold level. An RF signal input can thus still swing the device current up to the Imax value, as in Class A operation, but due to the symmetry of

4.4 Class AB and Class B

165

Imax Ids

Idc 2

3

4

3

4

3

4

(a) 2Vdc Vds Vdc

2

(b) 2Vdc Vds Vdc

2

(c) Figure 4.3 Reduced conduction angle (Class AB) waveforms; (a) current, (b) output voltage with

broadband resistive output termination, (c) voltage with short-circuited harmonic termination.

a sinusoidal excitation the negative-going part of the voltage cycle will swing the device gate voltage below its threshold value, thus “cutting off” the conduction for a portion of the RF cycle. The resulting current waveform is shown in Figure 4.3a, and is usually described as a “truncated” sinewave. It is the mathematical properties of such truncated sinewaves that determine the main performance benefits of Class AB operation, but before considering this in more detail we need to consider what now happens to the device output voltage. Due to the fact that an RF transistor can be conveniently approximated as an ideal current sink, the output voltage can be easily calculated; it is a simple matter of multiplying each individual current harmonic with the corresponding output load impedance, or in more symbolic language,  In .Z n (4.8) Vds = n

where In represents the harmonic components of current and Zn the load impedance value at the corresponding harmonic frequencies. Figure 4.3b shows the voltage waveform that would result from a broadband resistive termination, and it takes the form of an inverted replica of the current waveform. Such a result is unlikely in practice at GHz frequencies, where the characteristics of the output

166

Amplifier classes, A to S

Fundamental

0.5 DC

Amplitude (I max =1)

2nd 3rd

π

2π (CLASS)

4th 5th

0

A

AB

B

Conduction angle C

0

Figure 4.4 Harmonic components of reduced conduction angle waveforms.

matching network as a function of frequency will show large variations in both resistive and reactive components. It is thus an important stipulation in the design of Class AB amplifiers that the harmonic impedances are made as close to zero as possible. This “harmonic short” is never ideally achieved and is often the underlying cause of RFPAs performing less well than anticipated. However, for the present purposes we will assume that the output load does present a perfect short circuit to the device, so the harmonic components of the current do not generate any corresponding harmonic content in the output voltage, in which case the output voltage will then be sinusoidal, as shown in Figure 4.3c. So the output voltage of an ideal Class AB amplifier looks the same as for the Class A case, and it is to the current that we look for the differences. Figure 4.4 plots the DC and fundamental components of a truncated cosine wave. As the conduction angle is reduced, the DC component drops but the fundamental RF component remains very nearly constant, for conduction angles greater than 180◦ . This results directly in an efficiency increase, which is plotted in Figure 4.5. But it must be emphasized that the efficiency plot makes several assumptions, viz. r zero knee voltage; r short circuited harmonics, resulting in a sinusoidal device output voltage; r maximum voltage (VDC amplitude) and current (Imax /2 Amp) swings. A case of particular significance, if maybe not actually widely used, is the zero-bias or “Class B” condition. In this case the device is biased precisely to its threshold point and hence draws no current until some input signal is applied. When the drive is sufficient to cause the device current to swing to its maximum extent, the current waveform will

4.4 Class AB and Class B

+5 dB

167

100%

Efficiency (dB)

0

(dB)

–5 dB 2

0%

Conduction 0 angle IQ =10%

Figure 4.5 Power and efficiency of fully driven reduced conduction angle PA.

I max Ids

Idc π

2π

3π

4π

(a) 2Vdc Vds Vdc

π

2π

3π 4π θ (= ωt, rad.)

(b) Figure 4.6 Class B device waveforms.

become a half-wave rectified sinewave, as shown in Figure 4.6. The DC and fundamental components in the Class B condition have a simple closed form, Idc = I1 =

Imax , π Imax , 2

(4.9)

168

Amplifier classes, A to S

so that the RF and DC power is the same as for the Class A condition, Vdc Imax 4 Vdc Imax . = π

Prf = Pdc

(4.10)

The output efficiency is now given by ηo =

π 4

(4.11)

or about 78.5%. As with the Class A analysis, the allowance for a nonzero knee voltage will reduce this classical number by anywhere between 5 and 10%, depending on the device being used. The zero bias condition is a useful datum point, but is not often used. This is due to the fact that a “zero-biased” device will have very quirky performance at low signal levels, where a real device will not display an ideal cutoff behavior. In practice, the efficiency of a “deep” Class AB amplifier, biased around the 10% level, will show an efficiency quite close to the classical Class B value, as shown in Figure 4.5. Nevertheless, taking account of knee effects as well, it is unrealistic to expect an efficiency higher than 65% in a practical case, while maintaining the device entirely within the quasi-linear region. This is not to say that higher efficiencies cannot be measured, and are frequently reported in the literature, but such results are often taken with the device displaying significant gain compression. As before, it is important to consider the variation of efficiency as a function of input drive backoff, and the Class B case will again be considered due to its mathematical simplicity. For a device operating in Class B, and at a backed-off RF output level of Prf , we assume that the RF loading is unchanged from the maximum power condition, Pmax . So the backed-off current and voltage amplitudes can be expressed as  Prf Imax I1 = (4.12) . 2 Pmax  Prf V1 = Vdc (4.13) Pmax  Prf Imax . (4.14) Idc = π Pmax So for a constant supply voltage, the backed-off efficiency is   Pmax Prf Prf Vdc Imax Prf π π = . = . η pbo = . Pdc 4 Pmax Vdc Imax Prf 4 Pmax

(4.15)

This is a result of considerable significance for amplitude-modulated signals, since it shows that the PBO efficiency is a “slower” function than in the Class A case, being inversely proportional to the square root of the PBO ratio. In the case of a 6 dB PAR,

4.4 Class AB and Class B

169

100%

Efficiency

IQ=0 0.1

50%

0.2 0.5

0

Output power (2 dB/div) Figure 4.7 Efficiency characteristics for ideal Class AB PAs for backed-off drive conditions.

the efficiency at the mean power level has only dropped by a factor of two, as opposed to a factor of four in the Class A case. The same analysis can be performed for intermediate Class AB cases, but defies symbolic treatment; Figure 4.7 shows the resulting PBO efficiency characteristics which have been computed for a range of quiescent bias settings. It is clear that the same conclusion concerning the superior PBO efficiency can be made for quiescent settings up to at least the 10% level. It has already been emphasized that the desirable efficiency improvements that Class AB operation offers do come at a price. Lower power gain and increased circuit complexity generally will limit the range of applications to lower frequencies (where available devices have more gain to spare), and narrow bandwidths (due to the requirement for short-circuiting the harmonics). There is, however, another issue which concerns the linearity of a Class AB amplifier. This is something of a controversial topic, because device manufacturers often tailor the fabrication process to offer devices that have good linearity in Class AB, but often only when operated at a tightly specified quiescent bias setting. Figure 4.8 does show, nevertheless, that an “ideal” device will display significant nonlinearity when operated in Class AB. This results from the mathematical properties of truncated sinewaves; basically, at a given quiescent bias setting the conduction angle is itself a function of drive level and a nonlinear relationship between the drive voltage and the fundamental current component results, despite the device itself having an ideal transconductive characteristic. As the quiescent setting approaches the Class B point, the linearity tends asymptotically towards a linear characteristic, and at around the 10% level it becomes possible to “cancel” the gain expansion by tailoring the device transconductance characteristic. Whether this process has ever been implemented in such an a-priori manner is something of a moot point, but suffice it to say that such devices usually need the quiescent bias point to be set with considerable precision in order to obtain the specified linear performance. As such, the designer frequently does not have

170

Amplifier classes, A to S

P lin

Vq =0.5 (Class A)

0.25 0.15

Output Power (2 dB/div)

0.05

Vq =0 Vq =– 0.1 Vq =– 0.25 Vq = – 0.5

Input Power (2 dB/div) Figure 4.8 Linearity of Class AB PA modes.

Vdc bias network

fundamental match

input match harmonic termination

50 Ω

Figure 4.9 Topology of basic Class AB amplifier.

a free choice on the conduction angle, and some manufacturers will even recommend that higher quiescent settings should not be used at all. Figure 4.9 shows schematically the main elements in a typical Class AB amplifier circuit at GHz frequencies. The output matching network has to perform two main functions, a fundamental match which transforms the device load-line resistance to the system impedance level, and a harmonic “trap” which presents a short circuit at the harmonic frequencies. The fundamental matching network can be very similar to that used for a Class A amplifier, since the optimum fundamental load will be very close to the device load-line resistance. The harmonic trap can take various forms. A popular “textbook” solution is to use a short-circuited quarter-wave stub, which thus presents a short circuit only at the even harmonics and also acts as a convenient bias insertion point. But this is not often used in practice, due to the limited bandwidth over which an acceptably low impedance can be maintained. A second option is to use a shunt series resonator at the second harmonic. Fourier analysis of the half-wave rectified current

4.5 Class C

171

waveform reveals that the second harmonic is by far the largest component, and in many practical cases harmonics higher than the third can be regarded as “trapped” within the device itself, either through the action of the output capacitance, or the low-pass characteristic of the device itself. By far the most common solution for terminating the output harmonics, albeit not always intentionally, is to utilize the device output capacitance. It can be shown [2] that if the reactance of the parasitic output capacitance is equal to, or less than the fundamental load-line resistance, the output capacitor is by itself able to satisfy the requirements of a harmonic short circuit. This approximation tends to hold as the fundamental frequency increases, along with the device periphery. As a result, what could be described as a form of complacency seems to have developed amongst PA designers above 1 GHz. It is found, for example, that there is a wide range of applications where the device appears to give satisfactory performance by suitably careful optimization of the fundamental matching alone. This however does not in any way challenge the basic theory. It is merely a consequence of the fact that available transistor technologies have quite large output capacitance values (in the range of about 1 pF/W), which although being a major problem in designing the fundamental match over any useful bandwidth, just happens to solve the harmonic circuit problem very conveniently. This convenience does, however, break down when using a given device at a much lower frequency, and/or when a new technology comes along (such as gallium nitride) that has a much lower pF/W characteristic. The wireless communications industry has stimulated a vast amount of research and development into the design of Class AB amplifiers that give good linearity and high efficiency. These applications have however been focused in the lower frequency “strata” of the microwave spectrum, and utilization of these benefits becomes rapidly more difficult above about 8 GHz, due mainly to the lower gain of available devices.

4.5

Class C The Class C mode is a logical extension of the reduced conduction angle concept, where the conduction angle is reduced to less than half of the RF cycle. This results in a current waveform that looks more like a string of sharp pulses, as indicated in Figure 4.10. Referring back to Figure 4.6, the fundamental component starts to drop as the conduction angle crosses into Class C territory, but the DC component also continues to drop and the mathematics tells us that the efficiency climbs ever upwards towards 100% for an impulsive current, as shown in Figure 4.5. There are, however, a number of problems that need to be considered, which together have relegated the Class C mode into very limited practical use for certain specialized applications. This was not the case in the vacuum tube era, when the terminology was introduced. The reduction in RF power in Class C is a serious problem for a semiconductor device, since it means that to obtain a given RF power the size, or periphery, of the device has to be increased. This was less of an issue in the tube era, since the higher efficiency

172

Amplifier classes, A to S

I max Ids

Idc π

2π

3π

4π

(a) 2Vdc Vds Vdc

π

2π

3π 4π θ (= ω t, rad.)

(b) Figure 4.10 Class C device waveforms.

Input Voltage VMAX VT

Figure 4.11 Excess input voltage in very short conduction angle Class C.

enabled the device to be run at a higher plate voltage, thus effectively restoring the power shortfall. Such freedom in supply voltage selection is not available in the semiconductor world, where devices are usually operated at their maximum specified safe operating voltage. A larger problem with Class C is illustrated in Figure 4.11. Biasing the gate beyond its threshold point means that a very large drive signal will be required in order to swing the current up to Vmax , the gate voltage required for the device to draw its maximum current Imax . For a sinusoidal signal, this means that the negative-going peaks will drop down to a level that may cause some breakdown effects. In particular, given that the input voltage has a minimum that corresponds to the maximum peak swing of the output voltage, it becomes all too likely that some drain-gate reverse breakdown will occur.

4.6 Class F

173

Vmax Vds Vd

π

2π

3π

4π

Figure 4.12 Effect of adding an in-phase third harmonic component to the voltage waveform of a Class B amplifier.

A Class C amplifier also poses a greater challenge in terms of the necessary harmonic termination. The relative harmonic levels escalate quite rapidly as the conduction angle is reduced below the Class B value, and the “second harmonic approximation” may no longer be usefully valid. Despite these various disadvantages, it is worth mentioning that the Class C mode has found an important niche in recent years, as being a useful means of implementing the “peaking” stage of a Doherty PA.

4.6

Class F The Class F mode has been the focus of much research [3, 4]. In principle it offers a simple means of boosting the peak efficiency of a regular Class B or deep Class AB amplifier by more than 10%. This is achieved by allowing a third harmonic component in the voltage waveform, so that the output voltage looks more like a “squared-up” sinewave. As a preliminary, it is therefore important to understand the underlying mathematics of sinewaves having an added third harmonic component. The process is illustrated qualitatively in Figure 4.12. The addition of a small antiphase third harmonic component to any sinewave clearly reduces the peak-to-peak swing, since the relevant third harmonic peaks and dips are coincident in time with peaks and dips of the fundamental. As a result, the entire waveform can be scaled up, giving a higher fundamental component. This process clearly has a limit, that is to say there is an optimum level of third harmonic that results in a maximum increase in the fundamental amplitude; beyond this point the “twin peaks” start to increase and the benefits rapidly fade away. Finding this specific condition is something of a mathematical puzzle that has intrigued several authors over the years. Rhodes [5] tackled it by recognizing that the optimum condition was a singular point. More recently [6], the present author showed that the problem could be solved by factorizing the voltage expression, a formulation that turns out to have some wider implications. These will be discussed in a little more detail in Section 4.11, but the specific solution for the Class F case is now considered. If the current is assumed to be an ideal truncated cosinusoidal function, the corresponding Class F voltage “wave” can be expressed in the form v (θ) = Vdc − V1 cos θ + V3 cos 3θ

(4.16)

174

Amplifier classes, A to S

where VDC is the DC supply, and V1 , V3 are the fundamental and harmonic amplitudes. If for convenience we normalize the voltages to the DC level, this expression simplifies to v (θ) = 1 − v1 cos θ + v3 cos 3θ

(4.17)

and we seek the maximum value of v 1 for which v(θ ) remains greater than or equal to zero for all values of θ. Noting that the optimum condition will include a “zero-grazing” double root of v(θ ) = 0, equation (4.17) can be written in the form v(θ ) = (1 − α cos θ)2 (1 − β cos θ )

(4.18)

so that relationships between the α, β parameters can be established with v1 and v 3 by expanding (4.18) and comparing coefficients of similar terms in (4.17), noting in particular that the second harmonic term must vanish. Furthermore, (4.18) will force the v(θ ) = 0 condition so long as 0 < β < 1. This process results in the following relationships, β=

α 2

(4.19)

v3 =

α3 2

(4.20)

 v1 = α

3α 2 3 − 8 2

 .

(4.21)

The α parameter in effect controls the level of third harmonic for a set of zero-grazing waveforms defined by (4.18). We thus seek the value of α that gives the maximum value of v 1 , through the relationship in (4.21). Simple differentiation gives this value as 2 α=√ 3

(4.22)

corresponding to a maximum fundamental component of 2 v1 max = √ 3

(4.23)

and a corresponding third harmonic voltage v3 max =

1 . 6

(4.24)

So for the optimum Class F case, the voltage expression (4.17) can be written in the factorized form

2

√ √ 2 2 cos θ cos θ , (4.25) 1+ v (θ) = 1 − 3 6 a remarkable result of fairly recent origin [6].

4.6 Class F

175

Imax Ids Idc

π

2π (a)

π

2π

3π

4π

3π

4π

2Vdc Vds Vdc

θ (= ω

(b) Figure 4.13 Ideal optimum Class F device waveforms.

Since the DC components are unaltered from the Class B case, the optimum Class F efficiency will be π4 . √23 , or about 90.7%. The resulting ideal Class F waveforms are shown in Figure 4.13; note that the optimum solution has a third harmonic component that is slightly higher than that which gives a maximally flat response. As always, this result is conspicuously ideal and in practice the knee voltage will cause significant degradation. Indeed, ironically, due to the fact that the ideal Class F voltage spends a much higher proportion of the RF cycle within the knee region, the relative degradation from the ideal power and efficiency will be significantly higher than for a sinusoidal voltage. But caveats notwithstanding, the Class F mathematics certainly dangles a very juicy carrot which more than one generation of RFPA designers has found to be an irresistible challenge. And coming up with suitable Class F circuit topologies is indeed quite a challenge. The output matching network now has to perform three functions, r transform the fundamental (load-line) resistance to the termination impedance; r present the “appropriate” resistive termination at the third harmonic frequency; r short circuit the remaining harmonics, especially the second. It is the second of these requirements that is new, and formulating a strategy to deal with it has been the subject of much discussion. The above analysis gives a clear quantitative design goal for the required third harmonic voltage component, but transforming this into a corresponding design impedance presents some difficulties. The problem can be highlighted by considering the Class B case, where the ideal current waveform has a zero third harmonic component: what impedance is necessary to develop a voltage of Vdc /6 for a zero current flow? Some further discussion on this apparent paradox can be found in reference [2], but for the present purposes it will suffice to say that the design goal

176

Amplifier classes, A to S

o/c, 3fo

/4, fo

50

Figure 4.14 Possible Class F matching topology.

should be to present as high of a resistance as possible to the device at the third harmonic, and in particular to ensure that all of the reactive parasitics are parallel-resonated at the device output. This can be a daunting task when dealing with larger devices, whose output capacitance can be tens or hundreds of pF, and as a minimum will be bandwidth limited. Numerous circuit topologies have been devised for implementing Class F at GHz frequencies. A somewhat intuitive approach is shown in Figure 4.14, where a quarterwave stub is used to short the second (and in principle all of the higher even harmonics), and at the third harmonic the device output capacitance is resonated out with an open circuit stub, whose length at the fundamental is low enough such that it only adds a small extra capacitance that can be absorbed into the fundamental matching structure. But there are further constraints on maintaining the high-impedance environment at the third harmonic, in particular the fundamental matching network must have a suitably low-pass characteristic in order not to “load” the third harmonic impedance. This may require a more aggressive network at the fundamental, including a high-Q resonator, not only to realize the high third harmonic impedance, but also to block the extra third harmonic components from reaching the output. So the main difficulty in implementing Class F is bandwidth, and too often results are published that represent spot-frequency designs.

4.7

Class J The Class J mode has a fairly recent origin, being essentially promoted, as opposed to invented, by the present author [2]. The basic concept is to engineer a somewhat similar trick to that used in the Class F mode, but using second, rather than the third harmonic. Once again, it pays to examine the mathematics of the process first. Figure 4.15 shows what happens when an antiphased second harmonic component is added to a cosine wave. The resulting waveform becomes asymmetrical about the DC level, with a higher peak and a flatter minimum, which is now raised above the zero level. As a result, it is possible to scale up the waveform such that it again becomes zero-grazing and thus the fundamental component is significantly increased. Just as in the Class F case, it is necessary to determine the optimum level

4.7 Class J

Ids

177

Imax

Idc π

2π (a)

π

2π

3π

4π

2Vdc Vds Vdc

3π 4π θ (=ωt, rad.)

(b) Figure 4.15 Effect of second harmonic on voltage waveform.

of second (in the Class J case) harmonic in order to maximize the fundamental, while maintaining the nonzero crossing condition. Some trigonometric manipulations can be employed to show that for a normalized cosinusoidal voltage wave, v (θ) = 1 − cos θ

(4.26)

the maximum second harmonic component that can be added has a normalized amplitude of 1/2, so that the waveform becomes v (θ) = 1 −

√

2 cos θ +

1 cos 2θ 2

(4.27)

as shown in Figure 4.15. √ At first sight, the factor of 2on the fundamental would imply an efficiency of √ π (4.28) η = 2 = 1.11, 4 or 111%, assuming the current waveform was that of a Class B half-wave rectified sinewave. Clearly, this is inadmissible, and the reason for this is that the second harmonic components of voltage and current are in-phase, implying either power absorption or a negative resistive load. The Class J mode resolves this problem by shifting the entire voltage waveform, relative to the current, by 45◦ at the fundamental. The Class J voltage waveform thus becomes v (θ) = 1 − cos θ + sin θ +

1 sin 2θ, 2

(4.29)

which implies a fundamental load consisting of the regular load-line resistive component, but with an equal reactive component. The second harmonic load is a reactance,

178

Amplifier classes, A to S

Ids

Imax

Idc π

2π (a)

π

2π

3π

4π

2Vdc Vds Vdc

3π 4π θ (=ωt, rad.)

(b) Figure 4.16 Class J device waveforms.

f0, RL + jRL 2f0, −jX 50 Ω

Figure 4.17 Class J output matching circuit topology.

of comparable value to the load-line resistance. The efficiency is exactly the same as a Class B amplifier, as indicated by the unity normalized amplitude of the fundamental cosine voltage component. The resulting Class J waveforms are shown in Figure 4.16. The Class J mode has an important benefit over its regular Class B or Class AB counterparts, in that the second harmonic does not require a short-circuit termination. Indeed, the capacitive reactance that is required to terminate the second harmonic can in some cases be provided by the output capacitance of the device. This has probably caused widespread use of Class J in a fortuitous manner. This is illustrated in a typical Class J circuit configuration, shown in Figure 4.17. The output matching topology consists essentially of a capacitor, which provides the second harmonic termination, and a low-pass network for matching the fundamental. Depending on the frequency and the device technology in use, the parasitic output capacitance may in itself be within the range defined by the Class J design equations. In such cases, the “uninformed designer” can treat the whole design problem as an exercise in fundamental matching, and some judicious a posteriori tuning can introduce the necessary reactive component into the

4.8 Inverted modes, inverted Class F

179

Imax Ids Idc

π

2π (a)

π

2π

3π

4π

πVdc Vds

Vdc 3π 4π θ (= ωt, rad.)

(b) Figure 4.18 Inverted Class F mode waveforms (ideal); (a) current, (b) voltage.

fundamental impedance. Higher voltage harmonics can usually be regarded as negligible, due to the declining amplitude of the current components and the effect of the output capacitor. In practice there will be some interaction between the value of the capacitor at the second harmonic and the impedance of the fundamental network at the second harmonic.

4.8

Inverted modes, inverted Class F The modes which have so far been described can all be “inverted,” which means in effect that the current and voltage waveforms are reversed. So, for example, an inverted Class B mode consists of a device having a sinusoidal current waveform and a half-wave rectified voltage waveform. In the ideal case, the power and efficiency would be the same at the peak power level, but the power back-off efficiency characteristic would replicate the Class A curve in Figure 4.7, and as such this mode is not much used. A more interesting case is the inverted Class F mode, which has received considerable attention in the literature over the last few years. The waveforms, shown in Figure 4.18, show one useful potential advantage of Class F−1 . Due to the fact that the DC component of the half-wave rectified voltage sinewave has a value of Vpk /π , the fundamental component can be increased by a factor of π /2, assuming that the peak voltage of πVDC can be safely accommodated. This corresponds to a potential power increase of nearly 2 dB in comparison to a Class F configuration, and about a 2.5 dB increase in comparison to a Class B PA using the same device at the same supply voltage. In practice this extra peak voltage may exceed the breakdown specification of the device, although there are cases where this may not be a limitation.

180

Amplifier classes, A to S

Ids

Imax

Idc

Vds

π

2π (a)

π

2π

3π

4π

Vpk

Vdc 3π 4π θ (=ωt, rad.)

(b) Figure 4.19 Physically realizable inverted Class F waveforms; (a) current, (b) voltage.

The waveforms shown in Figure 4.18 are still highly idealized and unlikely to be realized in practice. Inverted Class F is conventionally “engineered” by starting off with the device biased as for Class A operation. The current clipping can then be realized by over-driving the device so that it saturates on the peaks and cuts off in the dips. This, however, will result in a more of a maximally flat current waveform, as shown in Figure 4.19. This only reduces the efficiency very marginally, but in practice a bigger hit will be taken when trying to engineer the stipulated voltage. The ideal half-wave rectified sinusoid contains multiple harmonics, and will usually be approximated by adding just second harmonic. As shown in Figure 4.19 (and as analyzed√in Section 4.7), this allows the fundamental component to be increased by a factor of 2, somewhat less than the π /2 factor that would apply for the ideal half-wave rectified sinewave. The peak power and efficiency advantages of Class F−1 are somewhat tempered by a “Class A-type” PBO efficiency characteristic, due to the high quiescent bias setting required to engineer the squared-up current waveform. There is, however, an interesting variant, shown in Figure 4.20. Here the current wave is a half-wave rectified (co)sinewave which has clipped peaks. With judicious adjustment, the voltage can be allowed to dip into the knee region, thus clipping the current such that it becomes an approximation to a square wave. This clipping can be adjusted to null out the second harmonic current component, so that the open-circuit impedance termination will allow a viable mode of operation that has an improved PBO efficiency characteristic. The clipping process does, however, significantly reduce the fundamental current component, causing a reduction in RF output power. The clipped condition will also likely result in a well-compressed condition, so that this variant may not be suitable for linear applications that use amplitude modulated signals. It appears that this variant has in the past been observed and given the name of “Class G” [7], but this term has not come into general use.

4.9 Class E

Ids

181

Imax

Idc

π

2π (a)

π

2π

3π

4π

Vds Vpk

Vdc 3π 4π θ (=ωt, rad.)

(b) Figure 4.20 “Clipped” variation on inverted Class F.

Vdc

Idc

CP

vc(t )

I(θ)

Figure 4.21 Basic Class E circuit.

4.9

Class E The Class E mode is defined, fundamentally, as a “switching” mode, where the active device characteristics that have been used thus far are replaced by a simple, perfect, switch. This immediately raises several questions about the validity, and indeed the relevance, of switching modes at GHz frequencies. But before considering these issues any further, we will examine the simplest and most basic form of ideal Class E operation. Figure 4.21 shows the simplest possible circuit for Class E operation. The active device takes the form of an ideal switch, which for the purposes of this analysis will be assumed to have negligible transition times and can be turned “on” or “off” at discretionary times within each RF cycle. The switch is shunted by a capacitor, and this in turn is shunted by a series resonant circuit. If we assume that the switch is being toggled periodically at a frequency that is close to the resonant frequency of the circuit,

182

Amplifier classes, A to S

Imax Irf

I (θ)

Idc

0

(a)

Imax Device Current

(b)

0

Imax Output Cap Current

0

(c)

0 Device voltage

Vpk (d)

Vdc 0

0

2π

4π

Figure 4.22 Ideal Class E waveforms.

there will be a sinusoidal current flowing around the resonant circuit loop. Figure 4.22 shows the resulting waveforms, including the currents in the resonant loop, the switch, and the shunt capacitor. The action of the switch is to force the resonant current either into the switch, when the switch is closed, or the shunt capacitor, when the switch is open. Given the “inertia” of the series resonator, the circulating current cannot change as the switch is “toggled.” The capacitor thus ends up with a current waveform as shown in Figure 4.22c, which can be integrated to show the voltage across it, as shown in Figure 4.22d. Looking at the waveforms at the switch terminals, it is clear that there is no time within the RF cycle that current and voltage are non-zero simultaneously. The system thus represents 100% efficient conversion from DC to RF energy, and due to the resonant nature of the circuit which contains the RF load, the energy will be mainly confined to the fundamental frequency. However, the high efficiency is as much a property of the assumed ideal nature of the switch, as the mode of operation. There is also an important caveat in that the peak voltage across the switch can be several times the DC supply voltage, causing breakdown issues when the switch is replaced by a transistor.

4.10 Class S

183

Figure 4.23 Class S amplifier concept.

In practice, the process of making a transistor behave like a switch requires some trickery, which involves the use of the knee region as well as the threshold of the device characteristics. This process usually involves sacrificing a significant portion of the device peak current capability so that, as with Class C operation, higher efficiency is obtained at the expense of obtaining lower power; this can be as much as 2–3 dB lower than normal Class AB operation for the same device with the same supply voltage. The Class E PA has been a favourite subject in the literature for nearly four decades, attracting particular attention from the academic community. Above 1 GHz, many of these papers and articles can be questioned in that they frequently do not show any RF waveforms at the device plane, and quote efficiencies that are much lower than would be expected from a pure switching mode. Efficiencies around 90% have been reported for Class E designs in the low GHz region, but the device is usually operating in a highly nonlinear condition. Such results have limited, albeit still potentially useful, applications in microwave communications.

4.10

Class S The Class S mode is the RF version of a pulse width modulation technique, widely used at lower frequencies under the name of Class D. The basic process is well known, and is indicated in Figure 4.23. The signal is sampled, and a train of pulses is generated, whose length is proportional to the instantaneous sampled amplitude. If this pulse train is passed through a low-pass filter, it is an elementary result of sampling theory that the original signal will be “reconstructed,” hence the term “reconstruction filter.” RF designers have always “dreamed” of the day when RF signals can be generated in this manner, and at any given time there is usually a vociferous faction which proclaims that the day has come. There are, however, some hazards upon which the unwary frequently stumble. Historically, the obvious outstanding problem is that of the necessary sampling rate. At audio frequencies, this can be made easily two or three orders of magnitude higher than the sampled signal bandwidth without posing any particular challenges on the speed of readily available electronic components. But for a signal at 1 GHz this clearly poses problems.

184

Amplifier classes, A to S

Vdc

Figure 4.24 Viable Class S amplifier configuration.

Vdc

Figure 4.25 “Bogus” Class S amplifier configuration.

There is in fact another problem which is frequently overlooked. In order to maintain high efficiency, the reconstruction process must not generate any significant power at any of the spectral frequency components that are caused by the sampling process. Figure 4.24 shows one way of achieving this. The active device switches the output filter and load between two voltage sources, which can be conveniently taken as zero (ground) and a positive DC supply. Switching between such “stiff” voltage sources ensures that the only current which is allowed to flow through the filter into the load is at the required signal frequency band. All other frequency components are presented with the high reactive load of the filter and as such do not create any power. Unfortunately, a single RF power transistor cannot be used to implement such a scheme, as shown in Figure 4.25. The transistor can be switched “on” or “off,” but this in effect means that the filter-load combination is being excited by a switched current source. It might be thought sufficient to accommodate this change by placing a suitable filter in shunt across the device, in order to provide a low-impedance path for the unwanted spectral components, but then the voltage of the desired signal will appear across the device terminals. As such, the device will start to dissipate heat as the level of the output signal is reduced, in much the same way as a regular Class A or Class AB amplifier. Implementation of a suitable switching configuration thus requires, as a minimum, a complementary pair of transistors which can switch the load between the two supply rails. Such a configuration poses difficulties at GHz frequencies, but as lower parasitic semiconductor technologies appear the possibility of realizing a Class S amplifier at low GHz frequencies does increase.

4.11

Multimodes The ongoing and widespread use of the “Class” categorization of RFPAs is somewhat puzzling. These classifications cite specific properties of the device current and voltage

4.11 Multimodes

185

Imax Ids

Idc π

2π (a)

π

2π

3π

4π

2Vdc Vds Vdc

3π 4π θ (=ωt, rad.)

(b) Figure 4.26 “Multimode” voltage waveform containing second and third harmonics.

waveforms, and at GHz frequencies these waveforms are very difficult to measure directly. They can, of course, be simulated, but it then becomes a judgment call as to whether the waveforms comply with the intended “Class.” In fact, a real device in a real circuit can frequently display waveforms that do not fall easily into a particular category. Take for example the current and voltage waveforms shown in Figure 4.26. The current is a regular half-wave rectified sinewave, but the voltage contains both second and third harmonic components, and as such does not fall under Class F, D, or J as described in this chapter. The voltage wave has the form V = Vdc cos θ + V1Q sin θ + V2Q sin 2θ + V3Q sin 3θ,

(4.30)

which has the same in-phase fundamental component as a regular Class A or Class B sinusoidal voltage, but with some added harmonic components. Since the harmonic components are in quadrature with the cosinusoidal current, they do not contribute power. The result is that such an amplifier will show the same efficiency as a Class B amplifier, but the harmonic voltage components imply that the device is not terminated with a short circuit at each harmonic, and in this case the harmonic terminations will be entirely reactive. Such a situation is probably very common in practice. The textbook stipulation of a global harmonic short is often unlikely to be fully implemented in a practical circuit, and this example is just one specific case of a large and continuous multidimensional “termination space,” which implies a continuum of harmonic matching conditions that yield the same fundamental power and efficiency as a classical Class B amplifier. The Class J voltage condition, defined earlier in the form V = 1 − cos θ − sin θ + (1/2) sin 2θ

(4.31)

186

Amplifier classes, A to S

is another specific example of this “space.” It was observed by the current author [6] that this can be written in a factorized form, V = (1 − cos θ )(1 − sin θ) v(θ ) = 1 − cos θ + v1q sin θ +

k=n 

vkq sin kθ ;

(4.32) (4.33)

k=2

it is easier to construct solutions by multiplying non-zero-crossing factors such as (1 − α cos kθ),

(1 − β sin kθ ),

and powers thereof. Such expressions will have the same RF power and efficiency as the classical Class B so long as the in-phase fundamental coefficient remains at unity and the in-phase harmonics are zero. It is also possible to generalize the expression further and include cosine harmonic components. Although this raises the possibility of generating unwanted power at the harmonic frequencies, the fundamental term can be enhanced. For example, the classical Class F mode can be shown to fall into the new theoretical framework,  2   2 1 V = 1 − √ cos θ (4.34) 1 + √ cos θ (1 − α sin θ) 3 3 with α = 1, but the more generalized formulation reveals a continuous set of modes based on Class F, but which contain additional quadrature even harmonics.

4.12

Conclusions The RFPA classes described in this chapter form a framework around which most practical designs will fit. Each mode however represents at least some degree of idealization, both in the characteristics of the active device, and also the fundamental and harmonic termination environment. Almost any practical RFPA which operates in the low GHz frequency region will likely display some variance from the traditional waveform Class definitions. But for the most part, designers who are unable to measure the device plane RF waveforms still indulge in a mindset of blind faith that the complex interaction between device and circuit can be fully characterized by a few letters of the alphabet.

References 1. J. L. B. Walker, Ed., High Power GaAs FET Amplifiers, Norwood: Artech House, 1993, pp. 18–21. 2. S. C. Cripps, RF Power Amplifiers for Wireless Communications, 2nd Edn., Norwood: Artech House, 2006. 3. V. J. Tyler, “A new high efficiency high power amplifier,” Marconi Rev., vol. 21, 1958, pp. 96–109.

References

187

4. F. H. Raab, “Class F power amplification with maximally flat waveforms, IEEE. Trans. Microw. Theory Tech., vol. 45, no. 11, pp. 2007–2011, Nov. 1997. 5. J. D. Rhodes, “Universality in maximum efficiency linear power amplifiers,” Int. J. Circ. Theor. Appl., vol. 31, pp. 385–405, 2003. 6. S. C. Cripps, P. J. Tasker, A. L. Clarke, J. Lees, and J. Benedikt, “On the continuity of high efficiency modes in linear RF power amplifiers,” IEEE Microw. Components Lett., vol. 19, no. 10, pp. 665–667. 7. P. Colantonio, F. Giannini, G. Leuzzi, and E. Limiti, “High efficiency low-voltage power amplifier design by second harmonic manipulation,” Int. J. RF Microw. Computer-Aided Eng., vol. 10, no. 1, pp. 19–32, Jan. 2000.

5

Computer-aided design of power amplifiers Stephen Maas AWR, Corporation

5.1

Introduction In any book about power amplifiers, it seems essential to discuss the most important tool in their design, circuit-analysis software. The development of such software has progressed from improvements in the understanding of linear and, especially, nonlinear circuit theory, as well as rapid improvements in computer and software technology over the past 20 or 30 years. While we all know about these successes, there exists a third dimension to the maturity of circuit-design software: our ability to create and especially to maintain large software systems to support a versatile design flow for a wide variety of RF/microwave components. In spite of these successes, however, circuitanalysis technology has not reached the point where it is perfectly transparent; some “street wisdom” on the part of the user is still required. By describing the underlying technology of these software systems, this chapter should impart some of that wisdom.

5.2

Methods of analysis

5.2.1

Linear analysis Linear analysis is an important part of any nonlinear circuit simulator; it is also intrinsically useful, as many types of circuit are quite satisfactorily treated as linear. Early linear circuit-analysis software treated all elements as two-ports and connected them in series, parallel, or cascade according to the structure of the circuit. Since most microwave matching circuits can be described easily this way, it was a useful way to create a set of circuit equations. Unfortunately, many kinds of circuit simply cannot be described as interconnections of two-ports. In this case, a more general method is needed, usually resulting in the creation of an admittance or other matrix describing the circuit. One such method, which was used in early general-purpose circuit-analysis programs, was based on so-called nodal incidence matrices [1]. This method was complicated to implement, so it was soon supplanted by nodal analysis.

Nodal analysis Nodal analysis has a number of attractive features. The nodal matrix, an admittance matrix of the circuit at each frequency of interest, can be created in a fully mindless

5.2 Methods of analysis

ΔI1

189

V1 n1

Y n2 ΔI2

V2

Figure 5.1 When the admittance Y is connected between nodes n1 and n2 , it changes the current in each node as shown.

manner, thus making it perfect for implementation by a mindless machine, a computer. Nodal analysis creates large sparse matrices (i.e., matrices that consist mostly of zero entries) and therefore can take advantage of modern numerical methods for handling such matrices. Although nodal analysis is generally less efficient than analysis based on cascaded two-ports, its versatility in handling a wide variety of circuit structures, combined with the speed of modern computers and sophistication of numerical methods for dealing with matrices, make it thoroughly practical even when applied to very large circuits. Nodal methods do have some disadvantages. First, and perhaps most obviously, many kinds of circuit element and structure do not have admittance representations. This is particularly troublesome when circuits are partitioned, a necessary step, as we shall see, for many kinds of nonlinear circuit analysis. Then, the circuit may become disconnected, causing the nodal admittance matrix to be singular. Similarly, DC analysis of circuits having inductors or transmission lines often fails, as nodes become interconnected by large, perhaps infinite, conductances. Methods have been developed for circumventing such problems; these will be described in due course. Consider the admittance element Y in Figure 5.1 connected between nodes 1 and 2. When we connect it into the circuit, it changes the total nodal current in each node as follows: Y (V1 − V2 ) = I1 Y (V2 − V1 ) = I2

(5.1)

where V1 , V2 are the voltages at the respective nodes, measured between the node and some arbitrary ground point. This can be written      I1 Y −Y V1 = (5.2) I2 V2 −Y Y implying that the matrix in (5.2) is simply added to the admittance matrix of the circuit, in the implied positions; that is, Y is added to the (1, 1) and (2, 2) positions and –Y to the (2, 1) and (1, 2) positions. equation (5.2) is sometimes called a stamp, implying that adding elements to the circuit matrix involves nothing more than “stamping” the matrix

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n2

n1 + V1 −

n3

+ V3 −

+ V2 −

Figure 5.2 In an indefinite admittance matrix, all node voltages are referenced to a common ground node.

with a predetermined pattern. Stamps for more complicated elements, such as controlled sources and other admittance matrices, can be generated similarly. The resulting matrix is called an indefinite admittance matrix. It is an admittance matrix in which the voltages represent node voltages relative to some arbitrary ground point; the situation is illustrated in Figure 5.2. It is clear that the node voltages cannot be determined uniquely in such a circuit. For example, we could find a set of voltages that satisfy, say, (5.2), add some particular DC quantity to each of them (5 V might be nice), and the currents remain unchanged. It is inevitable in such a case that the admittance matrix is singular. To remove the singularity, at least one node in the matrix must have some defined voltage; in practice, it is grounded. If the indefinite matrix is as shown below, ⎤ ⎡ I1 Y11 ⎢ I2 ⎥ ⎢ Y21 ⎢ ⎥=⎢ ⎣...⎦ ⎣ ... IN YN 1 ⎡

Y12 Y22 ... YN 2

... ... ... ...

⎤⎡ ⎤ V1 Y1N ⎥ ⎢ Y2N ⎥ ⎥ ⎢ V2 ⎥ ⎦ ⎣ ... ...⎦ YN N VN

(5.3)

grounding node n simply involves setting Vn to zero. Then the nth column can be removed, as its elements are all multiplied by zero. Similarly, the current In is then of no interest, so its row can be deleted as well. The resulting matrix is still square but (unless it has some other problem) no longer singular. Usually, not all of the node voltages are of interest. Only the voltages at accessible external nodes are of concern, and, in particular, we often want to characterize the N-node network by a P-port or P-node admittance matrix. This can be accomplished as shown in Figure 5.3. We first select the nodes that will become ports or accessible nodes and sequentially excite each port/node with a current source. We then obtain the voltages at each port or node. The voltages, divided by the excitation current, are the values in one column of the impedance matrix. When all the columns have been obtained, the impedance matrix can be converted to an admittance matrix, scattering matrix, or whatever type is desired.

5.2 Methods of analysis

n2

n1 I1

+ V1 −

191

+ n3

+ V3 −

V2 Z21 = V2/I1 − Z31 = V3/I1

Z11 = V1/I1

Figure 5.3 To find a P-node nodal admittance matrix from the N-node indefinite matrix, the P externally accessible nodes are excited in turn by current sources. The node voltages resulting from each excitation provide a single column of the Z matrix. The Z matrix port matrices can be found in a similar way; the voltages of interest are then those between the nodes defining the ports. The Z matrix can finally be converted to any desired form.

The most common method for factoring a nodal matrix is LU decomposition [2] and back substitution. Only a single factorization of the large nodal matrix is necessary, and the port or node voltages resulting from multiple current vectors can be found by back-substitution, a much less costly operation. This process is used most frequently for characterizing the linear subcircuit in a harmonic-balance analysis (Section 5.2.2). As we shall see, disconnecting the nonlinear circuit elements from the linear ones often leaves disconnected nodes, making the nodal matrix singular. This problem can be circumvented fairly easily in the following manner: 1. Before the indefinite matrix is created, moderate-value resistors are connected across each port of a P-port matrix or from the node to ground in a nodal matrix. The value of the resistance should be on the same order as resistances in the circuit; in most RF and microwave applications, 100  works well. 2. The matrix is reduced to a P-node or P-port admittance matrix as described above. 3. The added resistance now appears along the main diagonal of the P-dimension admittance matrix. The resistance is removed simply by subtracting its inverse from the main-diagonal terms. This process always works for a nodal matrix. In a port matrix, it is technically possible for it to fail, but it almost always works in ordinary circuits.

Modified analysis Many types of element, such as voltage-controlled voltage sources (VCVS), do not have an admittance representation. Others, such as ideal transformers, do not have a Y- or Z-matrix representation at all. It is possible to circumvent some of these limitations with other elements; for example, a VCVS can be realized from a cascade of a

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voltage-controlled current source and a gyrator; a transformer can also be realized by a cascade of gyrators. Modified nodal analysis is a somewhat more elegant alternative. Suppose we have a VCVS whose control terminals are (j, k) and voltage source terminals are (m, n). This element adds a constraint on the voltage of the (m, n) branch, and this must be included in the nodal matrix. We note that Av V j − Av VK + Vm − Vn = 0 I j = Ik = 0 Im = −In = 0

(5.4)

where Av is the voltage gain and I is the branch current. Then, we can augment the nodal matrix with an extra row and column representing (5.4): ⎡ ⎢ ⎢ ⎢ ⎢ ⎣ − −Av

− Av

− 1

⎤⎡ ⎤ ⎡ ⎤ | Vj ⎥ ⎢ ⎥ ⎢ | 1⎥ ⎥ ⎢ Vk ⎥ ⎢ ⎥ ⎥ ⎢ ⎢ ⎥ | −1 ⎥ ⎢ Vm ⎥ ⎥ = ⎢ Im ⎥ ⎦ ⎦ ⎣ ⎣ In ⎦ Vn −| − −1 I

(5.5)

This creates a new stamp for the element. All elements that cannot be described simply by an admittance matrix require this new stamp. A full treatment of modified nodal analysis is beyond the scope of this chapter. The interested reader should consult [3] for more extensive information.

Sparse-matrix method Imagine a large circuit having many thousands of nodes and consisting of simple, twoterminal elements. Each of these elements is connected to only two nodes, creating four entries in the matrix. From (5.2) we see that a matrix position ( j, k) has an entry only if a circuit element is connected between those nodes. Clearly, most nodes do not have elements connected between them, so most entries in the matrix are zero. Storing a large matrix consisting mostly of zero elements wastes memory, and computations with such a matrix largely involve multiplying zero by zero and adding the result to zero. This is especially troublesome, in view of the fact that LU decomposition of a matrix is an N3 process; that is, the amount of computation increases approximately as the cube of the matrix dimension, N. This situation clearly is wasteful, so methods have been developed to improve it. An early method, developed specifically for circuit analysis and still in use (e.g., in the circuitanalysis program SPICE), involves storing the nonzero matrix values in doubly linked lists, a list for each row and each column. In this way, large numbers of zero elements need not be stored. To find matrix elements, it is necessary to traverse the lists, clearly a slow process. Some kinds of access, however, such as finding locations for element stamps, can be facilitated by saving pointers to those locations. LU decomposition of a sparse matrix tends to create “fill-ins”; that is, zero locations are often replaced by nonzero values, and new locations in the lists must be created for them. Various heuristics are used to minimize fill-ins.

5.2 Methods of analysis

193

As the cost of computer memory has decreased, recent sparse-matrix methods have favored increased computational speed over minimized storage. Furthermore, the matrices in most kinds of nonlinear circuit analysis are not nearly as sparse as a linear, nodal matrix, and in such cases larger numbers of fill-ins tend to be generated, so the value of minimizing storage is, in any case, minimal. In such an environment, iterative methods that operate on the complete matrix are often used. The goal of such methods is to reduce the residual of the matrix. Specifically, suppose that one wishes to find the vector V given an admittance matrix Y and excitation sources I: YV = I

(5.6)

We estimate V in some way and define the residual, r(V ): r (V) = |Y V − I|

(5.7)

Clearly we need to minimize r(V ), or, equivalently, r2 (V ). One could view this case, for example, as an optimization problem. One might take the gradient of r2 (V ), ∇r2 (V ), and minimize r2 (V ) in the indicated direction. Although intuitively this process may seem slow, it scales with matrix size far better than simple LU decomposition. Other methods are more sophisticated, taking advantage of sparsity, matrix structure, and the availability of a good approximate inverse. In harmonic-balance analysis, which we describe in Section 5.2.2, a method called GMRES (generalized minimum residual), one of a class of methods called Krylov subspace methods, has been favored for many years. Such methods are used primarily for handling large sparse systems of linear equations, where the scaling of computation with matrix size may be on the order of N1.5 or better, instead of LUs N3 . Their advantage may be minor or nonexistent for small systems of equations, and their ability to handle ill-conditioned cases (those in which the matrix is nearly singular) are worse than classical LU decomposition. For this reason, the user of nonlinear circuit-analysis software must be especially careful to avoid situations where ill conditioning can occur. Use of certain kinds of time-domain model in frequencydomain simulators; use of models that are poorly defined, disconnected, or shorted in certain frequency ranges; poor choice of thermal parameters in self-heating models; and model parameters that create discontinuities are common problems that are often under the control of the user. We examine these matters later in this chapter.

5.2.2

Harmonic-balance analysis Harmonic-balance analysis seems to have been developed simultaneously by a number of individuals [4–6]. While single-purpose harmonic-balance software has existed since the mid 1970s, large-scale, general-purpose harmonic-balance simulators have been available only since the mid 1980s [7]. Since then, however, harmonic-balance analysis has become the dominant tool for power-amplifier designers at microwave frequencies, and it probably should be used more than it is for lower frequency (RFIC) applications.

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I Vs

+ −

R

+ V −

Figure 5.4 A simple DC circuit including a diode cannot be analyzed algebraically. The voltage and current at the diode can be found only by iterative means.

An heuristic introduction to harmonic-balance analysis Let’s consider the problem of finding the DC voltage of a diode in the simple circuit of Figure 5.4. The circuit is described by the equation, I =

Vs − V = Isat [exp(δV ) − 1] R

(5.8)

where δ = q/(ηK T ).

(5.9)

The quantities in (5.8) and (5.9) are what one might expect: q is electron charge, K is Boltzmann’s constant, T is absolute temperature, η is the diode ideality factor, Isat is the current parameter, V is the junction voltage, and I is the junction current. The rest of the terms are defined by the figure. It should be clear from inspection that (5.8) cannot be solved algebraically. We could, however, find V by means of the following algorithm: 1. Define the error equation, f (V ) =

Vs V + Isat [exp(δV ) − 1] − R R

(5.10)

This is simply Kirchhoff’s current law; f (V ) = 0 when it is satisfied. 2. Select some value of V as a first estimate of the solution. If we have some idea of what V should be, obviously that estimate should be used. In most cases, however, we have no idea,1 so perhaps simply choosing V = 0 might be a reasonable place to start. 3. Calculate f (V ). 4. By means of some appropriate numerical method, modify V so that | f (V )| decreases. 5. Repeat the process until | f (V )| is small enough. This idea raises two immediate questions; first, where do we obtain the “appropriate numerical method,” and, second, what, precisely is “small enough”? The first question is answered easily: the mathematicians have been here ahead of us. Any good text on numerical methods will describe many numerical techniques that might be appropriate. One good, general method for finding the zero of a function is Newton’s method. This technique, illustrated in Figure 5.5a, consists of repeatedly estimating the zero by a linear extrapolation from a known point on the curve. Given some function f (x), and 1

Or, more precisely, that big stupid machine on which we depend, called a computer, has no idea of the solution.

195

5.2 Methods of analysis

f(x)

f(x)

df dx df dx

f(x0)

f(x0)

x0 − Δx

x0

x

x0 − Δx

(a)

x0

x

(b)

Figure 5.5 Estimating the zero of a nonlinear function f (x) involves using the derivative to extrapolate to the x axis (a). This process is repeated until the zero is found to adequate accuracy. The method can fail, however, if the initial point x0 is poorly chosen; (b), for example, shows a case where the process has been trapped by a relative minimum.

an initial estimate x0 , we calculate f (x0 ) and df (x)/dx at x0 . The equation for the linear extrapolation is  d f  (5.11) f (x0 ) − x = 0 d x  x=x0 from which we obtain  x. We then estimate the zero as x = x0 − x

(5.12)

thus obtaining a better estimate of the zero. We now simply repeat the process with the new estimate of the zero as the starting point. If the curve is smooth and the original estimate x0 was reasonably close to the zero, eventually the process will converge to a solution. The performance of this method depends on the strength of the nonlinearity and the quality of the initial estimate, x0 . If it is applied to a linear equation, it will converge exactly in a single iteration, but if it is applied to a strongly nonlinear function, it may require many iterations. In some cases, it may fail completely. Figure 5.5b shows an example of a convergence failure, in which the process has been trapped by a relative minimum. Other quirks, such as an inflection point near the zero, can also cause convergence failure. Modifications of the method can sometimes circumvent some such problems; for example, reducing the step size from the full x to something smaller easily solves the inflection-point problem. The second problem, determining whether the solution has converged adequately, is more subtle. In the one-dimensional case we have examined here, the answer simply depends on the necessary precision. In most practical cases, however, we have a vector of harmonic voltages, V = [V0 , V(ωp ), V(2ωp ) . . . ]T where ωp is the fundamental excitation

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frequency. Then, instead of a scalar f (V ), we have F(V ), a vector of current errors. In this case, the criterion for a solution is much less clear. Should we specify a limit for the vector magnitude |F(V )|, the magnitude of each component of F(V ), or the fractional error in each component of F(V )? The answer largely depends on the type of problem we are addressing. In the first case, |F(V )| < ε, where ε is the limit, small components of F(V ) could be highly inaccurate even though ε is small. This could be troublesome for intermodulation analysis, where one expects large differences in the magnitudes of various frequency components. The second criterion, f k (V ) < ε, for all K components of the vector, is fine for small components but may be far too stringent for large components. The third, fractional error, is difficult to estimate when the error is large and the correct value of each component is unknown. It also tends to be too stringent for small error components. Usually, some combination of these criteria works best. It is important to recognize the idea underlying this little exercise: we have shown that it is not necessary to be able to analyze a nonlinear circuit directly. In fact, except for trivial cases, it is impossible to do so. It is only necessary to find some method that can reliably improve a hypothetical solution. Then, by applying that method repeatedly, we can reduce the error to the point at which it is negligible.

A more general case Now, let’s make the problem a little more difficult. Consider the situation in Figure 5.6, where the diode is excited by a sinusoidal source at the frequency ωp . In general, the source impedance is complex and, of course, differs at each harmonic of the excitation frequency. We now have made the problem multidimensional, since we need to satisfy our equations at a number of voltage harmonics, or, equivalently, at a number of voltage samples in the time domain. We can no longer write a simple equation having the form of (5.8), because the diode junction must be described in the time domain while we have described the linear part of the circuit in the frequency domain. How do we accomplish this? For the moment, let’s assume that we know the diode voltage. This is expressed in the frequency domain by V, a vector of harmonic components, or equivalently in the time domain by the sampled waveform v(t). Figure 5.6(b) shows that we can find ILIN (kωp ), the frequency-domain current in the linear part of the circuit at each harmonic frequency kωp , including DC, as ILIN (kω p ) =

V (kω p ) − Vs (kω p ) Z (kω p )

(5.13)

Note that Vs has a component only at ωp , the excitation frequency, and is zero when k = 1. The time-domain current in the diode, iNL (t) in Figure 5.6c, is i NL (t) = Isat [exp(δv(t)) − 1]

(5.14)

The time-domain junction voltage v(t) is periodic so it can be found by inverse Fouriertransforming V. Similarly, we Fourier transform the time-domain current to obtain its

5.2 Methods of analysis

ILIN

197

INL

Z(ω) + Vs

V − (a) ILIN Z(ω) +

Vs

V − (b) i NL(t) +

INL(t ) = Isat [exp(δv(t) ) − 1]

v(t ) −

(c) Figure 5.6 The more complicated case, in which the diode is excited by a sinusoidal source and a

complex source impedance; (a) shows this case; (b) and (c) show the decomposition into linear and nonlinear subcircuits, respectively.

harmonic components, INL (kωp ). To satisfy Kirchhoff’s current law at each harmonic, we require ILIN (kω p ) + INL (kω p ) = 0

(5.15)

Now we must face the fact that we don’t really know the voltage components V(kωp ). To find a valid solution, we must find the set of voltage components V(kωp ), k = 0 . . . K, where K is the greatest significant harmonic, that satisfies (5.15) at each k. In effect, we have K + 1 equations of the form (5.15) and K + 1 variables, the voltages V(kωp ). The problem is not much different from the previous one; we must find the zero of a nonlinear function. In this case, however, the problem is multidimensional. Fortunately, Newton’s method is easily modified to accommodate multidimensional problems. We formulate our voltages and currents in vector form and employ an iterative process entirely analogous to (5.11) and (5.12). We define our error function as F(V) = I LIN (V) + I NL (V)

(5.16)

F(V) = 0

(5.17)

and a solution is found when

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The zero is estimated as

 F(V) −

 ∂ F(V) V = 0 ∂V

(5.18)

which is solved for V. The new estimate of V is Vˆ = V − V.

(5.19)

The derivative of a vector with respect to a vector, which we see in (5.18), is a Jacobian matrix. This matrix contains all the derivatives of each component of F with respect to each voltage component V(kωp ). As such, it contains information about the effect of every voltage component on every error component. This is all the information about the local error that one could possibly have, and it implies that the method should be very powerful for finding the zero. For this reason, as well as considerable successful empirical experience, multidimensional Newton’s method has become the favored technique for both time- and frequency-domain nonlinear-circuit simulation. Compare Newton’s method to, for example, an optimization approach, in which the gradient, ∇|F(V )|, is used to determine the direction in which changes in V should go. That formulation would include information about the effect of each V(kωp ) component on |F(V )|, but not on the individual components of F(V ). It should be expected that such a method would be distinctly inferior to multidimensional Newton, as implementations of both methods quickly demonstrate [7]. Fortunately, the Jacobian matrix is surprisingly easy to create. The terms of the matrix are simply the Fourier components of the diode’s conductance waveform (i.e., its I–V derivative evaluated at v(t)) added to the admittances Y(kωp ) = 1/Z(kωp ) in appropriate locations. In large circuits, however, the Jacobian is invariably large, so solving (5.18) to obtain V can be computationally costly. Iterative methods such as GMRES are extremely helpful in minimizing that cost. Our final matter is to show how harmonic-balance analysis is applied to large circuits. It should be clear that (5.16) represents Kirchhoff’s current law, so it is valid when V, ILIN , and INL represent voltages and currents at both circuit nodes and frequencies. Specifically, V could just as well be V = [V1 (0), V1 (ω p ), V1 (2ω p ), . . . , V1 (kω p ), V2 (0), V2 (ω p ) . . .]T

(5.20)

where Vn (kωp ) is the voltage at node n and frequency kωp , and (5.18–5.19) remain unchanged. It is necessary only to generalize (5.13) in the obvious manner, I LIN = Y(V − V s )

(5.21)

where Y is the admittance matrix of the linear parts of the circuit, at all harmonic frequencies, arranged in the form of (5.20). Although previously we assumed Vs to be a single, sinusoidal excitation, (5.21) shows that this restriction need not be imposed. Vs could be, for example, a nonsinusoidal source or a set of nonsinusoidal sources connected to one or more nodes of the circuit and described by their Fourier series.

5.2 Methods of analysis

199

Harmonic balance variants As one might expect, the story is not as simple as presented above. A number of methods have been developed to improve the speed and robustness of harmonic-balance analysis and to accommodate more types of analysis. These include the following:

Norm reduction It is frequently observed that taking the full Newton step defined by (5.18) usually does not result in robust convergence. Dynamically adjusting the size of the step to provide an optimum reduction in the error function is invariably a better approach. Thus, (5.19) becomes Vˆ = V − βV

(5.22)

where β is a constant that can be varied as needed. Usually, β is initially small and is increased by the simulator until the error is minimized. Since the Jacobian need not be factored during this process, it is computationally relatively inexpensive and increases the simulator’s robustness significantly.

Semanskii iteration Semanskii iteration is simply a fancy name for reusing the Jacobian instead of reformulating it. Especially if the circuit is not too strongly nonlinear, or the process is close to a solution, using a single Jacobian formulation for several iterations can speed the solution process. Semanskii iteration can be used only when LU decomposition is used to solve (5.18); it is not applicable to Krylov methods. Since literally all modern harmonic-balance simulators use Krylov methods, Semanskii iteration is no longer of great interest.

Krylov subspace methods At each iteration of the harmonic-balance process, we must solve the matrix equation, JV = F(V)

(5.23)

where J is the Jacobian. When J is large and at least somewhat sparse, as it usually is, Krylov subspace methods, particularly GMRES, can be extremely helpful in solving (5.23) rapidly. This process requires that J and the right side of (5.23) be multiplied by a preconditioner. The preconditioner is an estimate of the inverse of J; the exact inverse is, of course, unknown; if it were known, the problem would be solved by the preconditioner multiplication. The success of the process depends strongly on the quality of the preconditioner. The closer it is to the inverse, the more efficient the solution of (5.23). By now it should be obvious that it is not necessary to solve (5.23) completely. It is necessary only to reach the point where V, applied to (5.22), decreases the circuit error. Thus, the solution of (5.23) need not be exact, and it can be terminated whenever an improvement in the error is reached. This is especially useful in the early steps of a harmonic-balance analysis, when even an exact solution of (5.23) would not result

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Computer-aided design of power amplifiers

in a good estimate of the zero, and thus would represent wasted effort. Because of the dependence on such partial solutions, these methods are sometimes called inexact Newton methods.

Weighting of the error equations We hinted at the problem of determining the aqdequacy of the solution earlier in this section. We noted that the norm |F(V )|2 , while the default method for determining convergence, is by itself a poor criterion, as it discriminates against small components of F(V ). In fact, the problem is worse that this. It can be shown that, in general, the gradient of F(V ) does not point in the same direction as V, and, in some types of circuit, it is actually perpendicular [8]. The problem is especially acute in circuits having controlled sources, which include virtually all of solid-state electronics. This means that a good Newton step, in the sense of improving most of the components of F(V ), does not necessarily improve the norm. This problem can be solved by weighting F(V ) before determining the norm. Multiplying F(V ) by the Jacobian is an appropriate weighting function. Using this simple method, before evaluating the circuit error, is a simple and highly effective technique for improving the robustness of harmonic-balance analysis.

Multitone excitations So far, we have assumed the excitation to be periodic, so it could be expressed as a Fourier series. This is, however, an unnecessary restriction. Nothing in the previous formulation requires that the frequency components be harmonics or the excitation sources have the same fundamental frequencies; they can be whatever excitation frequencies and mixing products are used and produced by the circuit. In general, the frequencies in the circuit are ω = mω p1 + nω p2 + · · ·

(5.24)

where m, n, . . . , are integers and ωp1 , ωp2 , . . . , are the excitation frequencies, assumed to be noncommensurate; that is, not harmonically related. Equation (5.20) then becomes V = [V1 (0), V1 (ω1 ), V1 (ω2 ), . . . , V1 (ω K ), V2 (0), V2 (ω1 ), V2 (ω2 ), . . . , V2 (ω K ), . . .]T (5.25) where ωk , k = 1, . . . , K are the set of nonharmonic mixing frequencies defined by (5.24). The only problem is the Fourier transformation; since the voltages and currents in general are not periodic, we cannot use a simple fast Fourier transform (FFT) to step between the time and frequency domains. A number of methods can be used to perform the necessary time-to-frequency transformation. Indeed, a cottage industry in developing such methods existed for a time during the 1980s and 90s [9–16]. One obvious choice is the use of a discrete Fourier transform (DFT). This works well as long as the frequency components are not closely spaced, a situation that is too restrictive for many kinds of analysis. The ill-conditioning of the DFT in such cases can be avoided by using nonuniformly selected time points in the transform; some of the transform methods focus specifically on that time-point

5.2 Methods of analysis

201

selection process [9]. The use of an n-dimensional Fourier transform is equivalent to selecting the time points optimally [10], but it is useful only when n noncommensurate excitation frequencies are used. This limits n to approximately n ≤ 3. Higher values of n are theoretically possible but become computationally expensive in practice.

Envelope analysis It is valuable to be able to use circuit-simulation techniques for excitations that are modulated waveforms. Such an analysis is straightforward in a time-domain simulator, but time-domain analysis may not be appropriate for certain kinds of circuit. For this reason, harmonic-balance methods that can handle such waveforms have been developed [17–19]. A naive approach to this problem might be to generate the modulated excitation waveform, sample it periodically at a rate based on the modulation time scale, and perform a harmonic-balance analysis for each sample. This approach has two problems: first, it yields no more information than an AM–AM/AM–PM behavioral model, in which the circuit’s amplitude and phase response to a range of sinusoidal signal amplitudes is determined and stored in a look-up table. Second, it does not account for long-term memory (memory on the order of the inverse bandwidth) in either the linear or nonlinear parts of the circuit. In envelope analysis, we perform a harmonic-balance analysis by sampling the modulated carrier at a rate related to the modulation bandwidth. The tricky part is including, in an approximate manner, the effects of circuit memory on the order of the sample period. Dealing with memory in the nonlinear subcircuit is simple; for example, consider a capacitor. The capacitor’s charge is Q(t) =

K 1  Q k (t) exp( jkω p t) 2 k=−K

(5.26)

where Qk (t) is the modulation waveform for the spectrum at the kth carrier harmonic, kωp . The capacitive charge is Q(V ) and the current is dQ(V )/dt. Differentiating gives   K  d Q(V )  1  d Q k (t) jkω p Q k (t) + i(t) = = exp( jkω p t) (5.27) dt V =v(t) 2 k=−K dt Since virtually all the circuit elements in the nonlinear subcircuit are small, this modification has only minor effects. The effect of the linear subcircuit is much more important. Dealing with the linear subcircuit is more of a problem. We need some method to find the circuit currents in response to the external node voltages, which are modulated sinusoids. This problem is not much different from that of using frequency-domain data in a time-domain simulator, and can be handled in much the same way. Existing approaches are to use a finite impulse response (FIR) model, an infinite impulse response (IIR) model, or to expand the frequency response in a Taylor series [17]. Depending upon the method employed, the harmonic-balance procedure can then be performed in the customary frequency domain or, alternatively, in the time domain (sometimes called a waveform balance approach). The iterative process, in any case, is somewhat more complex than for the simple sinusoidal analysis.

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Envelope methods are claimed to reduce computational cost relative to time-domain methods or multitone harmonic-balance methods. It is now understood, however, that the latter methods do not require uniform sampling intervals of a fraction of the carrier period, and when more intelligent approaches are used, the computational efforts of all are comparable. At the same time, the growing sophistication of behavioral modeling methods has moved much of this kind of analysis from the circuit to the system simulator; indeed, most of the information provided by envelope analysis is used at the systemanalysis level, where the system’s effect on the modulated waveform can be included. In the system simulator, the computational cost is far lower, as the nonlinear circuit needs to be analyzed only as necessary to generate a model. System calculations can then be performed indefinitely with no further attention to the nonlinear component. Furthermore, a fundamental dependence on behavioral models for modulated-waveform analysis allows modeling from measurements of real components as well as circuit analysis. For these reasons, dependence on envelope analysis, which never has been great, is currently decreasing in favor of behavioral modeling approaches.

5.2.3

Time-domain analysis It is well known that a linear circuit containing N independent reactive elements (i.e., not including such trivialities as two capacitors connected in parallel) can be described in the time domain by an Nth-order linear differential equation. Furthermore, any Nth-order linear differential equation can be expressed as a set of N linear, first-order differential equations. The same is generally true of nonlinear circuits. A number of methods exist for formulating the time-domain circuit equations directly in matrix form. While it is possible to use ordinary nodal analysis, in which only node voltages are the variables, it is usually more convenient to use a modified nodal form, allowing currents to be variables as well. The circuit is described by the equation, dX + G(X) + S = 0 dt

(5.28)

where X is a vector of time-domain node voltages and branch currents, G(X) is a vector of nonlinear functions of those quantities, and S is a vector of source voltages and currents. The key to time-domain analysis is the integration of (5.28). As with harmonic-balance analysis, many methods of solution are conceivably possible, all of which have differing numerical characteristics. In all cases, it is necessary to represent the derivative by a discrete approximation, which converts (5.28) into a set of nonlinear equations that can be solved sequentially. One simple approach is to estimate the derivative as  X(tn+1 ) − X(tn ) d X  =  dt tn t

(5.29)

5.2 Methods of analysis

203

where t is the time interval between points at which X is evaluated. This expression converts (5.28) into X(tn+1 ) − X(tn ) (5.30) + G(X(tn )) + S(tn ) = 0 t which can be solved algebraically for X(tn + 1 ). The process is then repeated at subsequent time points. This method, while simple and fast to evaluate, has unacceptably poor numerical characteristics. In particular, its error-propagation characteristics are poor, as well as its ability to handle stiff systems.2 A better method is to use  d X  X(tn+1 ) − X(tn ) (5.31) = dt t t n+1

that is, to treat this as the derivative at the next time step, rather than the current step. Then (5.28) becomes X(tn+1 ) − X(tn ) (5.32) + G(X(tn+1 )) + S(tn+1 ) = 0 t We now have a system of nonlinear equations that must be solved iteratively for X(tn + 1 ); an algebraic solution is no longer possible. If the vector X has dimension K, we now must find the zeros of K nonlinear equations, each of which is K-dimensional. We have seen this problem before, of course, in harmonic-balance analysis, where Newton’s method was used for the solution. The same method is applicable here. Although this approach requires an iterative solution at each time interval, it is much more robust than the earlier one. Of course, the computational cost appears much greater, but is actually not as severe as one might expect. In time-domain analysis, the changes in X(t) from step to step are generally fairly small, so convergence is rapid. This contrasts markedly with harmonic-balance analysis, where Newton steps are often extremely large. The greatest convergence difficulty in time-domain analysis usually occurs at the beginning of an analysis, where the simulator must determine the DC bias point and initial conditions for the analysis, and a solution must be found in a much larger space. The rules for convergence of time-domain methods are largely the same as in harmonic-balance analysis. The requirements which will be presented in Section 5.6.1, for example, apply equally to time-domain and harmonic-balance analysis.

Time-domain variants Shooting methods Just as harmonic-balance analysis inherently finds a steady-state response to a periodic excitation, time-domain analysis finds a network’s transient response, with or without an excitation that need not be periodic. To find steady-state conditions with time-domain analysis, it may appear necessary to integrate until the transient has died out. This may be impossible, in practice, as the circuit may have time constants that are orders of magnitude longer than the period of the excitation, so integration through a large number of cycles may be necessary. After 2

Stiff systems are those having multiple, widely varying time constants.

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this long integration, numerical errors could become so great that the results could be meaningless. This situation – a combination of long and short time constants – exists more often than not in RF and microwave circuits. Shooting methods avoid this long integration by searching directly for the steady-state conditions. The steady state is reached when X(t + T ) = X(t)

(5.33)

where T is the period of the excitation. The problem, in essence, is to find some initial condition X(t) that remains unchanged after integration through a period T. Again, this is a process of finding K zeros of K nonlinear equations, and can be approached in the same manner as similarly defined problems.

Frequency-domain models Many passive-element models, such as strip transmission lines and discontinuities, are best described in the frequency-domain and can be analyzed in a straightforward manner by frequency-domain electromagnetic (EM) simulators. The inability of time-domain simulators to accommodate frequency-domain data has been a significant impediment to their acceptance by designers of high-frequency electronics. Over the years, methods have been developed to allow time-domain simulators to use frequency-domain data. One obvious approach is to derive an impulse-response function by Fourier transformation. For example, given an impedance function Z(ω), a FFT can be used to create an impulse-response function z(t), which emerges from the FFT in discrete form and can be used in (5.32) in a straightforward convolution. This process has a number of problems. Since Z(ω) is truncated in frequency, z(t) extends over all time and is thus noncausal. Furthermore, it happens that Z(ω) must be very tightly sampled or artifacts and nonconvergence in the time-domain simulation can result. Straightforward practical problems can arise as well; for example, Z(ω) and z(t) must have compatible intervals, or some kind of interpolation is necessary. This is not only a complication, it can also cause nonconvergence. Although methods for ameliorating these deficiencies exist, the process is at best inefficient. Better methods attempt to determine a Laplace-domain expression of the form,  K   A∗k,i j Ak,i j + (5.34) Yi j = Y0,i j + sY1,i j + s − pk s − pk∗ k=1 where Yij is a Y-parameter of a multiport structure. As modern time-domain simulators invariably include a facility for handling elements characterized by their Laplace transforms, this method is very straightforward to implement. Its numerical characteristics are good and the characterization is causal.

Multitone analysis We noted in Section 5.2.2 that efficient analysis of circuits under multitone excitation required nonuniform sampling intervals. The same is true of time-domain analysis. While they are not as intuitive as in harmonic-balance analysis, techniques for handling

5.3 Passive circuit structures and simulation accuracy

205

multitone excitations have extended time-domain methods to such problems as intermodulation analysis of power amplifiers. A description of these techniques is well beyond the scope of this chapter; we note that they exist and are available in such software.

5.2.4

Applications of analytical methods As general-purpose circuit-analysis tools, time-domain methods are considerably older than harmonic-balance ones, dating from the late 1960s. One of the earliest nonlinear circuit analysis programs, SPICE, developed at the University of California at Berkeley, became available in the early 1970s. It was released as a public-domain software, guaranteeing its wide availability. SPICE still is used extensively for digital and analog integrated-circuit design. Since silicon RFIC design grew largely from the silicon analog world, SPICE and later time-domain programs have been the dominant software for those technologies as well. Harmonic-balance analysis was adopted by the microwave circuit design community largely because SPICE was not well suited to circuits having distributed structures. Distributed circuit elements, such as nonideal transmission lines and microstrip discontinuities, are more readily described in the frequency domain. Furthermore, transient response, which is what time-domain software inherently calculates, is rarely of interest to microwave designers, while steady-state response, which is provided by harmonicbalance analysis, is precisely what they need. RFICs, operating at frequencies below a few GHz, rarely use transmission-line structures. Interconnects in such ICs are often electrically short and can be modeled in other ways; for example, as RC transmission lines. Even so, many characteristics of these methods are merging. Modern time-domain software often includes methods for using frequency-domain models, and harmonicbalance analysis includes methods for handling nonperiodic waveforms and simulating transient characteristics. Similarly, system simulators are taking on some of the capabilities of circuit simulators, including the ability to account for component mismatches. In this way, different types of simulation can be integrated into a single process for solving problems that do not fit conveniently into a single method.

5.3

Passive circuit structures and simulation accuracy The problem of modeling passive elements in RF and microwave circuits has been a daunting one as long as high-frequency design has existed. Even today, the accuracy of circuit simulation is more strongly dependent on model accuracy than on the simulator itself. Many years ago, most discontinuities (e.g., irises in waveguides) had to be measured and the results tabulated. Occasionally the results could be normalized in frequency and dimension, so they could be scaled and applied to a wide range of structures. Eventually, closed-form expressions for the element models were derived from the measured and tabulated data. Today, efficient EM simulators can do much of the “heavy lifting”

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involved in modeling circuit structures. They are especially valuable for the modeling of power-amplifier components, as closed-form models sometimes are not accurate for the conditions of high current and low impedance often encountered. Such tools can be computationally costly, however, so the designer should be careful in using them. A little resourcefulness in design, especially favoring elements that are easy to model accurately, can do much to ensure the accuracy of the design process.

5.3.1

Scattering parameter models The simplest way to model any linear component is by its scattering (S) parameters. Modern calibration techniques now allow accurate S-parameter measurements to be made well into the millimeter-wave region. The universality of S-parameters is largely an historic phenomenon, dating from times before the widespread use of circuit-analysis software. Indeed, any other set of hybrid parameters can describe linear circuit elements; admittance (Y) parameters, which carry exactly the same information as S-parameters, have long been the customary way to describe RF transistors. Moreover, one could claim that characterizing devices by Y-parameters makes more sense than by S-parameters, as all such data are represented within the simulator in admittance form. S-parameter models are actually more general than one might at first assume. The output from EM simulators is invariably in the form of S-parameters (even though, like circuit simulators, they calculate Y-parameters directly), as is the data from database models, described later, in Section 5.3.4. Closed-form models, discussed in Section 5.3.2, start out life as S-parameter measurements as well. Thus, the points made in this section, which examines several considerations in the use of S-parameters to model circuit elements, apply to a wide variety of modeling methods. S-parameter models are somewhat inflexible. It is only rarely possible to scale S- or Y-parameters to describe a range of element types or sizes, and the parameters must be interpolated to obtain values at frequencies between those at which they were measured. The method of interpolation can affect the results of the simulation; simple linear interpolation between complex values is often unacceptable, as it results in gain and VSWR curves having a clearly nonphysical, scalloped appearance. Interpolation in a polar sense is much better, as are spline and rational-function methods [2]. An important consideration in all models (most easily illustrated, however, with S-parameter models) is that the manner in which the circuit element is measured must be consistent with the way in which it is used. More precisely, the modes at the interface of the model, in use, must match those of the measurement. This point is best illustrated by an example. Consider the measurement of a chip capacitor’s S-parameters. The capacitor is mounted on a carrier, with short, precise, 50  transmission lines, and the carrier is placed in a calibrated test fixture. The situation is illustrated in Figure 5.7. Since the test fixture’s reference planes are located at the edge of the carrier, the S-parameters are those of the capacitor plus its transmission-line connections. Normally, the transmission lines should not be part of the characterization, so the reference planes are moved closer to the capacitor; one convention is to place the planes

5.3 Passive circuit structures and simulation accuracy

207

(a)

(b) Figure 5.7 A chip component is usually modeled from measurements taken in a particular

configuration (a). If it is used in another configuration (b), the model may not be valid because the modes at the interconnection are not the same. In the above example, use of a tee junction does not completely solve the problem.

at the edge of the capacitor’s electrode.3 At this point we encounter a subtle problem. The fields at the capacitor’s edge do not consist solely of the quasi-TEM microstrip mode; they include a number of higher-order, evanescent modes that are concentrated near the microstrip-to-chip discontinuity. By moving the reference plane to the capacitor’s edge, we have eliminated the dominant mode but not the evanescent ones. When the capacitor is placed in a circuit, those modes must the same as in the measurement, or the model may lose its validity. The modes are the same only if the capacitor is connected via a 50  microstrip that is long enough to allow those evanescent modes to dissipate. If the capacitor is connected via a shorter strip, or one of a different impedance, the modes are different and thus the model is, to some degree, invalid. A second consideration arises when S-parameter models are used in a harmonicbalance analysis. Suppose, for example, that we are simulating a 10 GHz power amplifier and use 12 harmonics of the fundamental frequency, plus DC, in the analysis. This appears to suggest that we need S-parameters from zero to 120 GHz. Not only would this entail a difficult measurement, but it simply might not be possible to model many elements at such a high frequency. Most microstrip discontinuities, for example, cannot be modeled accurately at frequencies where high-order modes can propagate or where radiation and surface waves may occur. The latter depend on the dimensions of the 3

Another convention is to place the reference planes at the center of the chip. In this case, the circuit designer must add fictitious transmission line sections, each equal to half the capacitor’s length, to move the reference planes to the more desirable location at the edge of the chip.

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circuit’s housing and the location of adjacent structures, which might not be known at the time of the simulation. In practice, this problem is not as severe as one might fear. Solid-state devices have parasitic capacitances that shunt the nonlinear elements of the device or the device terminals, so high-frequency currents in the external circuit are usually negligible: a 1 pF gate-to-source capacitance of a large, 10 GHz power FET does a pretty good job of short-circuiting the gate at 120 GHz! Thus, it is rarely necessary that models be accurate at such high harmonic frequencies. It is necessary, though, that they be well behaved; that is, the S-parameters vary smoothly with frequency and do not take on impossible values. S-parameter models often take on bizarre values (e.g., a passive element becoming active) when a simulator extrapolates low-frequency measurements to obtain missing high-frequency data. To avoid this problem, one can simply add “dummy” S-parameters (e.g., representing a short-circuit) at a frequency well above the highest harmonic. Then, the simulator interpolates the data, instead of extrapolating it, and the results are more firmly bounded. A second problem occurs at DC. Such elements as strip-transmission-line discontinuity models must have low impedances at dc, and extrapolation to DC from RF values rarely ensures this. Again, DC S-parameters must be provided; this is invariably a simple thing to do. At DC, most models consist of short circuits (or at least very low resistances), open circuits, or simple resistances. Short circuits can create a problem in formulating the admittance matrix of the linear subcircuit, as connecting two nodes by a very low impedance creates large matrix entries. Conversely, an open circuit can leave a node floating, making the admittance matrix singular. Most modern harmonic-balance simulators have ways to handle such problems; simple ones are to formulate the admittance matrix differently at DC than at RF or to connect nodes by a finite, but negligibly small resistance, instead of zero. Other methods, more mathematically elegant, operate at the matrix level. In any case, the user should be aware of these potential difficulties and avoid them whenever possible. This discussion illustrates one important advantage of lumped-element models over S-parameter models: the former need not be interpolated, and they are well defined and guaranteed passive at all frequencies. The continuous nature of such models is an advantage in some types of circuit, especially oscillators, where the inevitable “graininess” of S-parameters can cause poor convergence. For this reason, many kinds of model, while generated from measurement data or EM simulation, are often realized in the simulator in lumped-element form.

5.3.2

Closed-form models Closed-form models consist of lumped and distributed circuit elements whose values are determined by algebraic expressions, or, at worst, a relatively simple numerical process. Those expressions can be derived in a number of ways. Frequently, they are based on an approximate analysis of the device, but sometimes they are completely empirical, with parameter values determined by measurements. Most models used in circuit simulation

5.3 Passive circuit structures and simulation accuracy

209

Air Bridge or Undercrossing

(a)

Cp L

R

C1

C2 (b)

Figure 5.8 Single-layer spiral inductor (a) and equivalent circuit (b) in a I–V technology. Multilayer inductors may require a more complex equivalent circuit and silicon implementations may have to account for additional loss mechanisms.

Cp L C1

R C3

C2

Figure 5.9 Equivalent circuit of a chip capacitor (Figure 5.7a. Cs is the rated capacitance and Cp is

the parallel capacitive parasitic. The inductance L arises from the currents in the capacitor’s plates and causes both parallel and series resonances.

are closed-form, but increased capabilities of both analytical software and EM simulators has created new kinds of model with significant advantages. Closed-form models consisting of lumped elements often can successfully model distributed structures. An example is the use of such models to describe microstrip or other strip-transmission-line discontinuities. Just as one can model a transmission line by a cascade of series inductors and shunt capacitors, a discontinuity usually can be modeled successfully by lumped elements. As an example, consider the planar spiral inductor shown, along with its model, in Figure 5.8. As well as inductance, the spiral has loss, capacitance between its the turns of windings, and capacitance from the windings to ground. If the spiral is not too large relative to a wavelength (and if it is, the inductor will likely be too large for use anyway), these parasitics can be modeled as lumped elements. The interwinding capacitance is modeled, to a good approximation, by a single capacitor across the terminals of the spiral, and the capacitance to ground by capacitors at each end. The loss is modeled by a series resistor, and, of course, the inductance by a simple inductor. A second example, a model of the chip capacitor of Figure 5.7a, is shown in Figure 5.9. The capacitor has series inductance, simply by virtue of its length and the fact

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that it carries a time-varying electric field. It also has dielectric and metallization losses, and shunt capacitance between its electrodes and bond pads. The inductance creates a series resonance and the interelectrode capacitances, combined with the inductance, create a parallel resonance. The latter resonant frequency is much higher than the former. Determining the values of the model elements is usually straightforward. The method depends strongly on the type of device. For example, many of the capacitor parasitics can be found from the series and parallel resonant frequencies, and the loss resistance from transmission loss at resonance. If nothing else works, the model can be determined from fitting its parameter values to measured S-parameters. Closed-form models are frequently used for strip transmission lines. Over the years, equations for such lines have been developed and polished, in many cases, to impressive accuracy. The critical characteristics of the lines – characteristic impedance, phase velocity, loss, and non-TEM dispersion – are expressed in such models by algebraic equations. Although the expressions are sometimes fairly long, they can be evaluated rapidly and rarely have a significant effect on computation time. As one might expect, models for the most frequently used types of line are most accurate. Microstrip models are more mature than models for other types of line; models of coplanar waveguide and suspended-substrate lines are probably next best. Models of less used structures, such as slotlines, are not as good. Most closed-form transmission-line models work well in circuit simulators, as they involve simply calculating a set of admittance parameters algebraically from the line dimensions. While most models are relatively simple, and are not costly to evaluate, some can be relatively complex; certain coupled-line models and microstrip-discontinuity models are an example of the latter. Even so, in comparison to EM simulation, such models invariably make quite modest demands on computational resources.

5.3.3

Models from EM simulation As computer capabilities have advanced, so has the practicality of using EM simulation for characterizing the passive parts of high-frequency circuits. As of this writing, it is practical to analyze the entire pattern of metal interconnections in a small IC as a single structure. With time, and predictable improvements in both software and computer hardware, it should be possible to do even more, and it is not unreasonable to expect that, eventually, virtually all but the simplest passive structures will be characterized by EM simulation. Several kinds of EM simulator, using various means for analysis, are available today. A detailed discussion of these simulators is outside the scope of this chapter; Swanson [20] has given a good discussion of their use and technology. Below, we outline only their characteristics as relevant to power-amplifier design.

Two-dimensional simulators 2D simulators analyze the cross-section of a transmission line or similar structure, determining its inductance, capacitance, series-resistance and shunt-conductance matrices. It is assumed that the structure is infinite in length. From these matrices, all

5.3 Passive circuit structures and simulation accuracy

211

characteristics of the line can be determined for its quasi-TEM mode only, although non-TEM dispersion effects sometimes can be included from empirical relations. Such simulators are very versatile in the kinds of structure they can accommodate and are quite valuable in cases where closed-form models are poor. Closed-form models often are inaccurate in dealing with thick metal, especially in coupled strip transmission lines, cannot analyze multiple, asymmetrical strips at all, and often cannot describe lines on multiple dielectric layers. 2D EM simulators can deal easily with these cases. They are especially useful for creating coupled-microstrip models in ICs, where metal thickness is often not small compared to the gap widths. The lack of any need to specify a strip transmission line’s length during the EM analysis is a significant advantage. Because of this, the strip’s length can be varied in the circuit simulator (e.g., during numerical optimization) without need to repeat the 2D simulation. For most structures, 2D simulation is very fast, often only slightly slower than the evaluation of a closed-form model.

Planar simulators These simulators, sometimes called “21/2 -D” simulators, should more correctly be called 3D predominantly planar simulators. They are based fundamentally on spectral-domain moment methods, which originally were limited to zero-thickness metal strips on layered dielectrics and imposed restrictions on the geometry and current distribution on metal, such as via holes, that were perpendicular to the substrate. Virtually all of these original limitations have been circumvented over the years, however, and such simulators now can accommodate a wide variety of structures, including thick metal, dielectric “bricks,” (rectangular areas of dielectric that differ from the surrounding dielectric), internal ports, vertical structures, and so on. Planar simulators can use either an open or closed formulation. In the open formulation, the metal is placed on dielectric layers of infinite extent; on closed structures, the dielectric is placed inside a metal box. The open formulation is perhaps more versatile, allowing the analysis of patch antennas, for example; the closed formulation is somewhat more accurate. Similarly, some formulations require that metal edges align with a predetermined grid; some do not. Again, the former, while more restrictive, are generally more accurate. The latter can be made equally accurate, although sometimes at the cost of increased computation time. Planar simulators are much faster than full 3D simulators. While slower than 2D, they include all non-TEM effects. Unlike 2D, they can analyze structures that have a complex 2D shape and need not be infinite in any dimension or have any particular symmetry. This makes them ideal for strip transmission lines and their discontinuities. The speed of many simulators is impressive; because of this, they can be used for determining the S-parameters of complete circuit nets, the entire pattern of metal used for interconnections on ICs.

Three-dimensional simulators 3D simulators are the most general but also the slowest of the simulators considered here, and they make the greatest demands on computer resources. “Full 3D” simulators

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can treat a wide variety of problems, including structures having great complexity in all dimensions. They are not restricted to layered dielectrics. Typical applications of 3D simulators are the analysis of waveguide discontinuities, waveguide-to-coax or waveguide-to-microstrip transitions, and coaxial rotary joints. 3D simulators have relatively little applicability in planar circuits; planar simulators can deal with virtually all problems that arise in such circuits. It is frequently assumed, quite incorrectly, that the presence of any vertical structure in an otherwise planar circuit requires the use of full 3D simulation. While this may have been true in the past, it is no longer true today.

5.3.4

Database models While EM simulation of such structures as microstrip discontinuities can be quite fast, its speed still can be prohibitive when large numbers of such elements are involved or many frequencies must be used. One solution to this problem is to precompute the S- or Y-parameters of a wide variety of structures, save them in a database, and recall them in a circuit simulation. Since the structures in the database may not correspond precisely to the dimensions or other characteristics of the circuit element, some appropriate type of interpolation is necessary. Technologies exist today for automatically converting the database parameters to an accurate lumped-element equivalent circuit [21]. Doing so provides smooth interpolation between frequencies and insures passivity of the resulting network. It also eliminates small discontinuities in the frequency response, which could cause convergence problems in some calculations.

5.3.5

Parasitic extraction Early analog and digital ICs were traditionally designed as lumped-element circuits. As circuit speed and complexity increased, the interconnections between transistors had a significant effect on the circuit’s performance. Thus, it became necessary to model the interconnecting conductors. The design flow, however, often evolved into one where the circuit’s initial design was based on ideal interconnections. Then, the interconnections were analyzed and their effect included as a final stage of the design. This often resulted in a circuit that did not work, and it became necessary to redesign the chip with, perhaps, shorter connections. Since silicon RFIC design evolved from analog design, this rather disjointed approach has been adopted for RFICs as well. Many kinds of software have been developed for parasitic extraction, and they use various methods for modeling the connections. All are, in some sense, types of EM simulator. Modern RF and digital ICs use short, narrow conductors, which usually can be modeled acceptably as RC circuits. Some extractors boast an “inductance aware” extraction, which includes the conductors’ inductance. A preferable design flow uses concurrent layout and circuit design, in which the layout is created simultaneously with the circuit design. Some kinds of modern design software

5.4 Solid-state device models

213

support this methodology. In those, the design, layout, and parasitic extraction are integrated, so the designer is spared an unpleasant surprise after the layout is complete. The need for characterizing circuit metal as part of the design process has always been obvious in the development of microwave circuits. Even in microwave ICs, however, when layout is delayed to the end of the design process, it often happens that some structures simply do not fit, and redesign becomes necessary. Concurrent design prevents this from occurring.

5.4

Solid-state device models While power-device modeling is covered in Chapter 2, and thermal effects in devices are covered in Chapter 9, certain aspects of the device model affect the way simulations proceed, and, indeed, determine whether the amplifier can be simulated successfully at all. We consider some of those matters in this section.

5.4.1

Power device models Power devices are large, as they must handle large currents and high voltages. To accommodate a high current, the total gate width of a power FET often is large relative to a wavelength. To prevent degradation of device performance by distributed effects, the device must be divided into a number of cells, each a smaller FET with its own gate; source and drain regions are generally shared with adjacent cells. Similarly, BJTs and HBTs are realized as a number of individual cells connected in parallel, often with shared electrodes as well. In ICs, the designer may have some degree of freedom in deciding how many cells can be used in a particular device and how they are arranged. The design must then include analysis of the interconnection parasitics and must describe the multicell device by a single transistor model or, if necessary, at most a few transistors.

5.4.2

Modeling cell interconnections in large devices The cells of a power device invariably include a large number of interconnections. The way those connections are arranged and the amount of metal in those interconnections can affect the performance of the device. In a cellular handset amplifier, for example, the load impedance at the device may be on the order of 1 or 2 ; in this case, even 0.1 nH of inductance represents approximately 1  of reactance at 1.8 GHz, clearly a nonnegligible quantity. At the opposite end of the device, the way that the gates or bases are connected is also important. Simplest is a parallel connection, although in very large devices this connection may not provide uniform drive to all the cells. A tree-structured connection usually provides more uniform drive but is larger and more complicated to model. Although it is a frequent practice, modeling interconnect metal by conventional transmission-line and discontinuity models is rarely successful. Such models are often

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not very accurate in a low-impedance environment and are correct only when well separated from each other. In a power device, both discontinuities and straight transmission lines are close enough together that their fields couple, violating a fundamental assumption in the model’s formulation. EM simulation is a preferable tool for modeling the interconnection parasitics. Since the interconnects feed individual cells, it may be tempting to treat each cell in the simulation as a separate transistor. The computational cost of this approach is rarely justified by the gain in accuracy. Since a properly designed interconnect structure provides uniform drive to the cells, and proper thermal design should result in uniform cell temperatures, there is little to gain by treating the cells as separate devices. It is almost always acceptable to reduce the large device to a scaled, single device or at worst a very few devices.

5.4.3

Thermal effects in device models In power devices, high power dissipation is to be expected, so it is almost always necessary to include self heating in device models. Often self-heating models are not available, or the simulator does not support them (SPICE does not). Most device models, however, include at least thermal scaling; that is, at the outset of the simulation, the user can specify a temperature for each device. Once the simulation is complete and the power dissipation has been determined, the user can correct the temperatures as necessary and rerun the simulation. This is a clumsy process, especially when a large number of devices are involved. Self-heating models determine the device temperature by calculating the power dissipation from the terminal voltage and current waveforms and the user-specified thermal resistance. The power dissipated in the device at any instant t is Pd (t) =

K 

vk (t)i k (t)

(5.35)

k=1

summed over the device’s K terminals. If the thermal mass of the device is large enough, and the time scale of the variations is small, device temperature is  θ jc Pd (t)dt Td = TBP + (5.36) τ where Td is the device temperature, TBP is the mounting-surface (or “baseplate”) temperature, θ jc is the thermal resistance between the device’s active area and the baseplate, and τ is some long period of time. If the thermal time constant is not long compared to the time scale of the excitation, the device temperature varies with time and must be included in the analysis. This can be accomplished by the electrothermal equivalent circuit in Figure 5.10. The temperature T(t) then becomes a variable quantity within the model, much like any other control voltage or current in satisfying (5.17). In the figure, the thermal resistance is treated as a linear quantity, but in reality the thermal resistance of all semiconductor materials is nonlinear, increasing with temperature. This is an important effect in determining

5.4 Solid-state device models

θjc

Cth

215

+ T(t )

Pd (t ) TBP

+ −

−

Figure 5.10 Electrothermal equivalent circuit for determining the device-temperature waveform. The current is set numerically equal to the power dissipation waveform Pd (t) from (5.35), θ is the thermal resistance, and Cth is the thermal capacitance. The device temperature is numerically equal to the voltage across Cth .

Ic Rbb

+ Vbb −

+ + Vbe −

Vce −

+ Vcc −

Figure 5.11 Biased bipolar transistor subject to self heating. The resistance Rbb provides stability.

device temperature, but few device models include it. When included, it can significantly degrade the numerical conditioning of the problem. While self-heating models are considerably more satisfactory than thermal scaling, they do tend to be ill-conditioned, sometimes causing convergence failure in both harmonic-balance and time-domain analysis. Ill conditioning and the resulting convergence failure can be a sign of thermal instability in the circuit, as well. Such instability can be difficult to predict, and when it occurs, it can be difficult to recognize as the cause of convergence failure. The problem can also be exacerbated by poor behavior of the model outside its normal operating limits. The problem can be illustrated by the simple, dc-biased bipolar transistor shown in Figure 5.11. The power dissipation in the device, Pd , is Pd = Vce Ic

(5.37)

where Vce and Ic are the collector voltage and current, respectively; we have assumed the base power to be negligible. The temperature increase caused by this dissipation, T, is T = θ jc Pd

(5.38)

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where θ jc is in ◦ C/W. Finally, we can say Ic = β(T )Ib

(5.39)

Vbb − Vbe Rbb

(5.40)

and Ib =

where β is the current gain, Vbe is the base-to-emitter voltage, which we approximate as a function of temperature only, and the other terms are as shown in the figure. Rbb , a ballast resistor, is included specifically to improve thermal stability. Substituting (5.38) to (5.40) into (5.37) gives T =

θ jc Vce β(T )(Vbb − Vbe (T )) = C tb f b (T ) Rbb

(5.41)

where Ctb is a constant and fb is the part of (5.41) dependent on T. The result is a transcendental equation, which must be solved graphically or numerically. This is done by expressing (5.41) as T  = Ctb f b (T )

(5.42)

T  = T

(5.43)

and solving simultaneously. This is shown in Figure 5.12. In silicon BJTs, β increases with temperature and Vbe decreases. As a result, (5.42) increases monotonically with T. If Ctb is small enough, the solution is well defined. As Ctb increases, however, the solution becomes multiple, poorly defined, and finally no solution exists. The latter case corresponds to thermal runaway, a well known property of silicon bipolar devices. In HBTs, by contrast, β decreases with temperature, so the situation is much better. However, even then, ill-conditioning can occur if Ctb is too large. In a similar manner, it is possible to show that the addition of emitter resistance removes the effect of β, so the thermal stability of the silicon device is much improved; however, in HBTs, the negative thermal feedback provided by β is lost. For this reason, silicon power devices are usually emitter-ballasted. Although base ballast provides better stability in HBTs, it decreases gain significantly, so most HBT amplifiers use a combination of emitter and base ballast. Clearly, if the device itself is not thermally stable, any analysis of the circuit that includes self heating is likely to fail. However, even in cases where the device is thermally stable, a self-heating model that is badly behaved outside of the normal range of operation may exhibit ill conditioned behavior. We consider the importance of model behavior outside the normal range of operation in Section 5.6.

5.5

Special aspects of power-amplifier modeling Some characteristics of circuit-element models have an especially strong effect on power amplifiers and their simulation. Circuit losses, for example, are important in all types

5.5 Special aspects of power-amplifier modeling

Very large Ctb

217

ΔT ′ = ΔT

ΔT ′

Large Ctb Small Ctb ΔT ′ = Ctbfb(ΔT )

Stable Temperatures (a)

ΔT ′

ΔT

ΔT ′ = ΔT ΔT ′ = Ctbfb(ΔT ) Large Ctb Small Ctb Stable Temperatures (b)

ΔT

Figure 5.12 Stable thermal operating points are found by solving (5.42) and (5.43) simultaneously. When β increases with temperature, as in silicon BJTs, it may happen that no operating point is possible. This situation corresponds to thermal runaway. Conversely, in HBTs, β decreases with current and thus provides inherent stability. Thermal instability is still possible, however, in HBTs.

of circuit, but in power amplifiers they become critical. Similarly, while all chips use bond wires, large networks of bond wires are common in power devices and thus must be treated in special ways.

5.5.1

Loss in circuit metalizations Power amplifiers have high current not only in their devices but also in their circuit metal. As a result, I2 R losses in the metal can be surprisingly high; this is especially the case in ICs, where metal layers are thin. The DC resistance of a rectangular metal sheet is given by R = Rsq

L W

(5.44)

where L is the length of the metal sheet, W is its width, and Rsq is the sheet resistance in /square. The sheet resistance is the resistance of a square section of the metal, a quantity that is independent of the size of the square. Rsq is simply ρ/t, where ρ is the metal’s resistivity and t is the thickness in compatible units.

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Estimating metal losses is usually straightforward, but a few matters can complicate it. These are listed below. 1. Skin effect: As frequency increases, the current becomes concentrated at the surfaces of the conductor. The skin depth, δ, the depth at which the current density decreases to exp(–1) of its surface value, is given by δ=√

1 π f μσ

(5.45)

where μ is the permeability of the material, σ is the conductivity, and f is the frequency. In RFICs, which operate at low frequencies, skin effect is rarely much of a concern, but in microwave ICs it may be significant. If the metal thickness is more than two or three skin depths, increasing its thickness does not measurably decrease its losses. Most strip-transmission-line loss models account for skin depth. 2. Current distribution: Current in flat conductors tends to concentrate at the edges. This is true of DC as well as RF currents. Unfortunately, the conductor edges usually are fairly rough, especially if they are defined by chemical etching. This roughness increases the length of the path that the current must follow, thus increasing resistive losses. As one might expect, the current distribution is less uniform in wide conductors than in narrow ones. Microstrip loss models account for this nonuniform current distribution, as do loss estimates from EM simulations. They generally do not account for edge roughness, although they sometimes include corrections for surface roughness. 3. Multilayer metallizations: Many types of circuit board and IC use more than one layer of metal for their metallizations. If the frequency is low enough that skin effect can be ignored, the layers can be treated to a good approximation as resistances in parallel; thus, Rsq =

Rsq1 Rsq2 Rsq1 + Rsq2

(5.46)

where Rsq1 and Rsq2 are the sheet resistances of the two metal layers. 4. Metal imperfections: Especially in ICs, the resistivities of metal layers are invariably greater than their handbook values. The latter are determined from large, pure samples of the metal, but deposition technologies rarely provide such perfection. Changes in grain structure and inclusion of impurities can increase the metal resistivity substantially. Alloys, for example, invariably have much higher resistivity than pure metals. 5. Metal oxidation and surface roughness: Especially at high frequencies, where the current is concentrated at the metal surface, such imperfections as roughness and an oxide layer increase losses. In microstrip circuits, most of the surface current is on the underside of the conductor, so the substrate’s smoothness largely determines the metal’s smoothness. Many of these phenomena are difficult to quantify. They can result in an effective metal resistivity that appears to vary with frequency and metal dimensions. Even in simple

5.5 Special aspects of power-amplifier modeling

219

cases (e.g., low frequencies and simple metal structures) many strip-transmission-line models are not terribly accurate in predicting losses. Perhaps the best simple way to treat them is to use the standard models in combination with a conservative estimate of the metal resistivity. The author’s general practice is to use at least double the handbook resistivity values in all transmission-line models. Calculation of losses by means of an EM simulator sometimes is not as rigorous as one might assume. The usual process is to calculate the surface current distribution on the conductors, then to determine the sheet resistance, accounting for skin effect if necessary, and to determine the losses by integrating. This method is accurate for low-loss conductors that are otherwise ideal, but does not directly account for metal imperfections described above, and its use for multilayer metallizations is problematical. Metal losses have little effect on the circuit-simulation process. If anything, they tend to improve the conditioning of the admittance matrices, and thus may have at least a theoretical effect in preventing convergence difficulties. This is likely to be important only in inherently ill-conditioned cases, such as transmission lines that are precisely one-half wavelength long.

5.5.2

Loss in circuit components Because of the high currents in power-amplifier components, losses in nominally lossless components – capacitors and inductors – can be high as well. It is not unknown for chip capacitors, which ideally dissipate no power, to become hot enough to melt the solder connecting them to the circuit board! For this reason, it is important in simulations to monitor the currents in such elements and, along with information about their Qs, calculate their power dissipation. This is especially important for components in output circuits, where resonator currents can be quite high, and even small losses may have a large effect on efficiency. A simulation of a WCDMA handset amplifier illustrates the effect of circuit loss. The matching circuit consists of a simple structure with two shunt capacitors and a series transmission line, a structure that is typical for such amplifiers. Figure 5.13 shows the results of the amplifier simulation. The simulation is just of the power stage; such amplifiers usually include a driver stage as well. The figure shows the total RF output power of the complete amplifier (i.e., including all harmonics) and the total RF power at the input of the output matching circuit. The difference between these curves, 0.5 dB at maximum efficiency, represents the power dissipation in the matching circuit. This analysis shows that 11% of the output power is dissipated in the matching circuit. At first glance, this loss is distressing, but in cellular handset PAs, where small, inexpensive capacitors and inductors must be used in the output matching circuit, it is largely inevitable.

5.5.3

Bond wires While bond wires exist in all kinds of circuit, they are usually used simply as interconnections. In power amplifiers, however, bond wires, which have inductances of a fraction

Computer-aided design of power amplifiers

WCDMA Amplifier Power Sweep 40

80 Total Output Power (L, dB m) Power Sweep

Gain (L) Power Sweep

Efficiency (R) Power Sweep

Total Pwr at MC Inp (La,dB m) Power Sweep

20.04 dB m 31.59 dB m

30

70 60

20.04 dB m 31.08 dB m

25

50

20

40

15

30

10

20

5

10

0 −10 −8 −6 −4 −2

Eff. (%)

35 Output Power (dB m)

220

0 0

2

4

6

8 10 12 14 16 18 20 2223

Power (dB m) Figure 5.13 Simulation of a cellular handset power amplifier, showing input and output power at the output matching circuit. The output loss caused by matching-circuit elements in this case is 0.5 dB.

of one nanohenry, are often used as matching elements. This is an especially common practice in output circuits, where very low inductances are often needed. The use of bond wires for inductances creates three difficulties: (a) determining the wire’s inductance and resistance, (b) making sure that the wires can carry the required current, and (c) making certain that the desired wire length and shape is consistently produced in a production environment. Even where the bond wire is not used as a matching element, the low impedance level of the circuit may cause the wire inductance to have a significant effect on matching or port VSWR. The DC fusing current of a 25 μm diameter gold bond wire is approximately 0.6 A and its DC resistance is approximately 0.05 /mm of length. The fusing current depends somewhat on the bond wire’s length, and the resistance may be affected by skin effect and the kinds of imperfection described earlier. The inductance of the wire is more difficult to determine. A single straight wire over a ground plane can be modeled as a transmission line, but all practical bond wires are asymmetrically arched, a more complicated situation. Finally, power devices rarely use single bond wires; they usually use multiple, closely spaced wires. The wires are invariably magnetically coupled, so the impedance of N wires is not simply 1/N times the impedance of a single one. Such large bond-wire networks must be analyzed as a whole, not scaled from single-wire analyses. The determination of bond-wire impedance is a straightforward problem for a 3D EM simulator (Section 5.3.3). With care, a bond wire sometimes can also be modeled acceptably by a planar EM simulator, with straight vertical and horizontal sections, as long as the total length of the modeled wire is the same as the real one. These simulations are generally costly, so they should be minimized, perhaps by limiting the number of bond-wire configurations in the design.

5.6 Practical aspects of nonlinear circuit simulation

221

The problem of uniformity may be less than it at first appears. Automatic bonding equipment produces highly uniform bond-wire shapes; as long as the process’s standard shape is acceptable, wire uniformity should not be difficult to achieve.

5.6

Practical aspects of nonlinear circuit simulation

5.6.1

Convergence difficulties We noted earlier that Newton’s method is not guaranteed to converge; harmonic-balance simulators regularly remind us of this fact. Newton-based harmonic-balance analysis is nevertheless quite robust, even when applied to stunningly complex problems. Most convergence problems are not inherent in the simulator; they arise from poor characteristics of models, which are often under the control of the user, and from the user’s misunderstanding of the best way to set up an analysis.

Model characteristics Many standard models are not well conceived for use in harmonic-balance simulators. Others have undocumented constraints on parameter values, which, if not observed, cause convergence failure. Finally, models designed for use in time-domain simulators are often transferred unmodified to harmonic-balance simulators, where they do not work as well. A fundamental rule of Newton-based circuit analysis is the following: all expressions describing nonlinear circuit elements must be continuous through their second derivatives. This is equivalent to saying that a plot of the first derivative must not have any kinks in it. Clearly, since Newton’s method depends on derivatives to estimate the zero of a function, any sudden change in the derivative makes convergence more difficult. The existence of such problems can be inherent in the model or can be caused by the way parameters are determined. Consider, for example, a nonlinear passive conductance element described by the I/V equations, I (V ) = a0 + a1 V + a2 V 2 + a3 V 3 I (V ) = 0

V > Vth V ≤ Vth

(5.47)

In this case, the parameters an must be selected not only to match the I/V characteristic of the real device, but also such that I(Vth ) = 0 and dI/dV = 0 at V = β. It can be shown that these constraints define two of the an values. This leaves only two coefficients to adjust the shape and overall magnitude of the characteristic. A naive user of this model, however, might not recognize this, and select all the polynomial coefficients to obtain the best overall fit to the measured I/V curve. The virtually certain result would be a discontinuity at V = Vth . Another potential problem is a consequence of the way harmonic-balance analysis operates. In the early iterations of an analysis, it is possible, indeed likely, that the independent variables in the analysis (usually node voltages) become quite large, well beyond the normal operating range of the device. In this case, it is essential that the

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Computer-aided design of power amplifiers

model be well behaved not only in its normal range of operation but at voltages well outside that range. The SPICE diode model serves as a good illustration. Suppose we were to use an ordinary textbook characteristic for the junction current, I (V ) = Isat exp(δV )

(5.48)

where Isat is the diode’s current parameter and δ ∼ 40. In the initial iterations of a harmonic-balance analysis of a diode circuit, the voltage can reach several hundred or even several thousand volts, clearly causing a numerical overflow or underflow. To solve this problem, the function uses a quadratic extension above some large threshold value of V; the extension is designed so the derivatives are continuous at the threshold value. Note that a linear extension of the function would introduce a discontinuous second derivative at the threshold voltage, which would not be acceptable. Values of independent variables need not be huge to cause trouble. Consider a device model that includes self-heating. It is likely that the model is not well defined at temperatures below absolute zero, but it is possible that the simulator, which doesn’t know the difference between a volt and a degree, might, at some point, create a thermal value that is less than zero. Often, naive model developers simply create a hard limit of T0 . This is an excellent way to obtain poor convergence characteristics. This kind of problem is greater in harmonic-balance analysis than in time-domain analysis, as Newton iterations in time-domain analysis begin with a value of voltage or current, at each time interval, that is close to the correct value. The iterative process usually changes the value of the independent variable only slightly. Occasionally, however, large values of the independent variables can occur in time-domain analysis, usually at start-up or when a step function of the excitation occurs. It should go without saying that derivatives of nonlinear model characteristics must be programmed correctly. This is not as easy to ensure as it may seem, however, as many nonlinear device models use expressions that are exceedingly complicated, and their derivative expressions are even more so. It is quite common for printed model documentation to contain errors, and for those errors to propagate through simulator implementations for years. One solution, often observed today, is for the model developer to create a standard implementation, usually in SPICE but sometimes in pseudo-code or a high-level language such as Verilog A. This standardizes the implementation and reduces the danger of multiple implementations having their own errors. Instead, they all contain the same errors. Another solution is the use of automatic differentiation, a technology for creating exact, analytical derivatives from a functional expression in source code. In this case, the derivatives of the nonlinearity need not be programmed, but derivatives for each elemental function (such as an exponential, sine function, and so on) must be programmed, as well as the chain-rule process. The advantage of this technology is the guarantee of correct derivatives, as long as the derivative-generating process is correct. The disadvantage, of course, is that an error in the process affects all models, not just one. A final possibility is the use of numerical derivatives; that is, simply estimating  f (v) d f (v) ≈ dv v

(5.49)

5.6 Practical aspects of nonlinear circuit simulation

223

using some small increment v. This is almost never done in either harmonic-balance or time-domain analysis. It introduces many numerical problems; for example, determining the size of v so that it is small enough to produce a reasonably accurate derivative but not so small that it is affected by loss of numerical precision. Empirical experience with numerical derivatives shows that they often are not sufficiently accurate to allow good convergence, especially near the solution. It is common in some simulators to add low-value conductances across all nonlinear elements, or from all nodes to ground, to improve convergence characteristics. The need for this can be understood intuitively by recognizing that the Jacobian is similar to an admittance matrix. If a nonlinear element is turned off, say, by biasing a FET well below its threshold voltage, some of its nodes may be open-circuited. This results in a row of the Jacobian having zero or very small entries, rendering it singular or nearly so. In SPICE, the default value for the conductance is 10−12  − 1 . This value of conductance rarely has a significant effect on the accuracy of the solution, but it still can be helpful in providing good convergence. The value can be increased by statements in SPICE’s options block. Harmonic-balance simulators usually have similar capabilities.

Analysis characteristics Continuation methods We noted earlier that Newton’s method converges reliably in a single iteration in any linear circuit. Thus, one possibility for improving the convergence is simply to linearize the circuit in some way. The strength of any nonlinearity is directly related to the level of its excitation; any nonlinear element approaches linearity as its RF voltage or current approaches zero. This simple fact can be used to obtain convergence in difficult conditions: analyze the circuit at some low excitation level, then increase the level using the previous results (perhaps scaled according to the excitation level) as the initial estimate. The analysis proceeds in this manner until the desired excitation level is reached. This process takes advantage of the near-linearity of the circuit at low levels, and uses solutions at higher levels as initial estimates. These expedients usually are enough to prevent convergence failure. This method is sometimes called source stepping. It is one of a more general class of methods called continuation methods, in which some parameter of the circuit is varied stepwise and a solution is obtained at each step. Besides source stepping, continuation methods may include parameters that vary the linearity of nonlinear elements from nearly linear to their specified nonlinearity. Both have been used in circuit simulators; however, because of its ease and generality of implementation, source stepping is most common. It is important to recognize that source-stepping, or other continuation methods, are effective only when strong nonlinearity or large excitation causes convergence difficulty. Continuation cannot provide a solution if the problem is ill-conditioned, say, by the use of a poorly conceived self-heating model.

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Frequency set The selection of a frequency set can affect convergence. By frequency set, we mean simply the set of frequency components used in the harmonic-balance analysis. In a simple single-tone analysis, the frequency set is simply the set of harmonics from 0 to Kωp , where ωp is the excitation frequency and K is a harmonic great enough so that the result has adequate accuracy. In a multitone analysis, the situation is more complicated. The set of frequencies in the analysis is ω = kω p1 + lω p2 + mω p3 + · · ·

(5.50)

where ωpn are the excitation tones, and the range of the integers k, l, m, . . . must be limited in some way. A number of limiting schemes are possible; for example, k = −K . . . K l = 0... L ....

(5.51)

and so on. Note that it is not necessary to include l < 0, as this simply creates harmonic components that already exist in (5.51). This set is sometimes called a rectangular or box truncation [14], as plotting the (k, l) pairs on a rectangular grid creates a box pattern. Another possibility, called a triangular truncation, involves the use of (5.51) with the additional constraint that K + L < Q, where Q is some maximum order of the mixing products of interest. A third possibility is the mixer set, in which ω = kω p ± ω0

(5.52)

and k is limited as in the single-tone case. This set is used for mixer analysis, in which ωp is the local oscillator and ω0 is the IF. Although the frequency set is rightly selected according to the problem at hand, it nonetheless has a strong effect on convergence, analysis time, and memory use. It should be obvious that a greater number of frequency components causes greater memory use and slower analysis. The effect on convergence may be less clear, however. Intuitively, one might expect the use of a greater number of frequency components to provide a better estimate of the solution, and thus convergence might be more robust. In fact, the frequency set has a relatively weak effect on convergence, and minimizing the number of harmonics while significantly oversampling in the time domain usually provides better convergence. The reason for this mildly nonintuitive situation can be illuminated by an examination of the way harmonic-balance analysis operates. For simplicity, we consider a single-tone problem limited to K harmonics and a single nonlinear function. If the independent variables are voltages (which is always the case in nodal analysis), limiting the harmonics to K makes Vk = 0, k > K. This is equivalent to setting all the embedding impedances in the circuit to zero at those frequencies. Since the frequency spectrum is strictly bandlimited, the v(t) waveform used to calculate the current in the nonlinear subcircuit is very “clean”; that is, unaffected by aliasing or other Fourier-transform errors. The current, i(t), is then obtained from the nonlinear function, i(t) = fNL (v(t)). The fourier transform

5.6 Practical aspects of nonlinear circuit simulation

225

of this quantity is not strictly bandlimited to Kωp . If the waveform is oversampled (i.e., the sampling interval is much less than the Nyquist limit), the harmonics of interest are not affected significantly by those higher harmonics, so the harmonics k > K are discarded without incurring error. If the sampling interval is minimal, however, the lower harmonics can incur aliasing errors, a form of numerical noise that changes from iteration to iteration, making convergence difficult or impossible.

Termination criteria Earlier we made the point that harmonic-balance analysis is a process of iteratively improving an estimate of the solution. At some point, that solution is “good enough” and the process must terminate. How do we decide what is “good enough”? A number of possibilities are immediately evident. The first is simply to require that the magnitude of the current-error vector be less than some threshold: |ILIN (V) + INL (V)| < ε

(5.53)

Another is that the individual current errors at each harmonic be below some threshold; that is, |ILIN (kω0 ) + INL (kω0 )| < ε

(5.54)

for all harmonics at all nonlinear elements. Finally, we could require that the fractional error in each harmonic be below some threshold: |ILIN (kω0 ) + INL (kω0 )| <ε (|ILIN (kω0 )| + |INL (kω0 )|)/2

(5.55)

where the denominator of (5.55) is an estimate of the element current at that particular harmonic. All of these methods have pitfalls, introduced by the presence of harmonics having very large and very small magnitudes. In (5.53), it is possible for the error to be relatively small, while errors in individual weak harmonics, which are often of most interest, are quite large. Suppose, for example, we are analyzing a power amplifier under multitone excitation, and we are especially interested in its intermodulation distortion. An error limit of, say, ε = 10−6 would be far too small for the fundamental tones, and might well prevent successful convergence. That error might still be too great to resolve intermodulation tones, however, which could be well below this level. A similar problem exists with (5.54); an absolute error limit may be too small for larger frequency components yet too large for smaller ones. The limit shown in (5.55) has the opposite problem. A fractional error of, say, 1% (ε = 0.01) might be fine for larger components, such as the fundamental-frequency output, but it is pointless to determine intermodulation tones to such a small error. One solution to this dilemma is the use of a hybrid criterion. For example, we could examine each current-error component and determine whether either (5.54) or (5.55) is satisfied. If all components satisfy one or the other, the problem terminates. When

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Computer-aided design of power amplifiers

this criterion is used, the absolute error of (5.54) can be specified for weak components, and the fractional error of (5.55) for larger components. This approach naturally accommodates both large and small components with appropriate error criteria.

5.6.2

SPICE models in harmonic-balance analysis When general-purpose harmonic-balance simulators were originally developed, few nonlinear device models were available. The obvious source for such models was SPICE, so SPICE models were simply transferred to the harmonic-balance simulator. Since then, many more device models have been developed, and the original implementation of these models often was in SPICE as well. As a result, many such models are optimized for SPICE, and similar time-domain programs, but are not well suited to harmonic balance. The reason for this situation arises in the differences between silicon monolithic ICs, for which SPICE was created, and microwave hybrid and monolithic ICs, for which harmonic balance simulators are generally used. Silicon ICs consist primarily of nonlinear circuit elements, with relatively few linear ones; microwave ICs consist mostly of linear circuit elements, which are incorporated into a single admittance matrix. Many SPICE device models, however, consist of many nonlinear elements and few linear ones. Separating these models into linear and nonlinear subcircuits often leaves isolated nodes, resulting in an ill-conditioned harmonic-balance Jacobian matrix. Often, parts of such models that do not affect microwave circuits are included in SPICE models, introducing unnecessary computational overhead. A good example is the inclusion of a substrate parasitic transistor in the VBIC BJT model. Microwave devices, both HBT and BJT, do not have this parasitic. Its effects can be removed by using device parameters that turn off the elements, but this practice still may create isolated nodes, and, in any case, adds useless overhead in analyzing “dead” nonlinear elements.

5.6.3

Problem size minimization and solution optimization Minimizing the size of the problem can do much to reduce the computational cost of a nonlinear analysis. At this point, it should be clear that the size of the problem is essentially the size of the Jacobian matrix, which is proportional to the number of harmonics and to the number of nodes or ports at which nonlinear elements are connected. Minimizing either of these quantities helps to speed the analysis. We have already touched on the matter of selecting a sensible frequency set and minimizing model complexity. Other technologies can do much to minimize the size of the problem that must be solved. In the past, nonlinear circuits rarely included much DC circuitry. In today’s RF and microwave ICs, however, it is common to have fairly complex circuitry, such as bias circuitry, which can be treated as linear. Treating such circuits as part of the RF circuit is wasteful and unnecessary. Simulator technologies exist that can identify the parts of the circuit that have no significant RF voltage and treat them as linear. Those parts can then be incorporated into the linear subcircuit, reducing the problem size. In simulators having this capability,

5.6 Practical aspects of nonlinear circuit simulation

227

dramatic improvements in simulation speed are observed; reducing the size of the nonlinear problem also can improve simulator robustness. Harmonic balance can be formulated such that the independent quantities, the nonlinear element voltages, are at either ports or nodes. Use of a port formulation minimizes problem size, while the nodal formulation is more versatile. Because of the importance of minimizing problem size (and thus, presumably, simulation time), virtually all early microwave simulators used a port formulation. In time, however, numerical methods for handling large, sparse matrices improved, allowing the nodal formulation to have simulation efficiency virtually as good as a port formulation. This evolution parallels the evolution of linear circuit simulators, which, in their earliest incarnations, used port concepts. Today, such methods are obsolete, and nodal (or modified nodal) methods are virtually universal. Each time a new simulation begins, the simulator must, in essence, find its way through a variety of possibilities to obtain a solution. It does this by using the Jacobian matrix to “point” to the direction, at each iteration, of the fastest decrease in the error function. Unfortunately, some of the steps in that process are good ones and some are not. It is possible for the simulator to remember which steps were successful in decreasing the error function and which were poor. Then, the information can be used to speed subsequent analyses. The idea is useful as long as the circuit does not change much between analyses, which is often the case; after all, in the process of “tweaking” a circuit to optimize it, most circuit modifications are minor. Such methods can be very useful in power-amplifier analysis, where, for example, large pumped capacitances seem to be quite effective in sending the simulator off toward places where it should never go.

5.6.4

Numerical considerations Much of harmonic-balance and time-domain analysis involves solving linear equations. This is obvious in the case of (5.18), but even the process of performing a Fourier transform is inherently a matrix operation. It is well known that ill conditioning (i.e., near singularity) of the matrix can result in large errors. Given the N-dimensional system of linear equations Ax = b

(5.56)

the error in the solution vector, x, can be bounded as δb δx ≤ κ ( A) x b

(5.57)

where κ(A) is the condition number of the matrix, and is the maximum norm of the vector v, v = max |vi |

1≤i ≤N

(5.58)

The condition number can be found in any of several ways; see [2]. Equation (5.57) says, in essence, that any fractional variation in b is amplified by the condition number in determining the fractional error in x. In (5.18), the right-side vector is F(V ), which is subject to considerable numerical noise and error, as it involves

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Computer-aided design of power amplifiers

multiple Fourier transforms and loss of precision from extensive computation. Thus, poor conditioning of the Jacobian can easily create errors large enough to make convergence impossible. We have discussed the source of ill conditioning periodically throughout this chapter. The most common sources of ill-conditioning probably are (a) poorly conceived models, and (b) characteristics of the circuit itself. Among the former are poorly conceived selfheating models and the latter include parts of the circuit that would be disconnected save for some large impedance. Models frequently are ill-conditioned, in the sense that they lead to an ill-conditioned admittance matrix of the linear subcircuit or to an ill-conditioned Jacobian. Many phenomena that affect conditioning have been described earlier (e.g., Sections 5.6.1 and 5.6.2), so it suffices simply to make the point once more. In general, nonlinear capacitors are characterized by their charge-voltage functions, Q(V ), and the current is found by differentiation in the frequency domain, which involves simply multiplication by jω. Another approach, which is useful in some models, is to use the capacitance, defined as dQ(V )/dV. In that case the independent quantity is the voltage derivative, not the voltage itself. The Jacobian’s entries normally have the magnitudes of circuit admittances, but this formulation creates entries whose magnitudes are those of the capacitances. These small entries create near-zero values in the matrix, which cause ill conditioning. The solution in this case is very simple: scale the capacitances larger (by a factor of, say, 109 ) and make the independent voltages affecting them smaller by the same factor. It is amusing to note that this problem has occasionally been presented as a fundamental difficulty in using a capacitive formulation. However, this simple expedient solves the problem completely. In a port formulation, loops of independent voltages (e.g., three nonlinear capacitors in a pi configuration) can cause ill conditioning. The problem arises from the fact that the loop voltages are linearly dependent; one voltage is extraneous, as it can be determined from the others. This is the reason for the requirement in SPICE that loops of capacitors and voltage sources cannot be used.4 This problem is very difficult to avoid, as the nonlinear elements in a circuit are often hidden inside models, and such loops can be created without any obvious indication. Then convergence is poor. Use of a nodal or modified nodal formulation usually prevents this problem.

5.6.5

Design flow A fast, robust simulator cannot do much to speed the task of designing an amplifier if the designer’s development process is fraught with bottlenecks. The difference between the fastest and slowest circuit-simulator engines might make, at most, a few weeks difference 4

SPICE also proscribes cutsets of inductors and current sources, for the same reason. This restriction is found in simulators that use mixed voltages and currents as independent quantities.

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229

in a project of several months, but the use of a cumbersome design flow might easily double or even triple development time. One great impediment to a smooth design flow is the common division of the design task into separate, disjointed efforts, such as initial design, parasitic extraction, EM analysis of critical circuit elements, and layout. Each of these stages can uncover a flaw requiring substantial redesign at a time when much effort has already been expended. Integrating these tasks into a single, concurrent flow can do much to expedite the design process. Software can be an important part of improving the design process, but it must be designed not only for its analytical capabilities, but to support an efficient design flow as well. As the RF/microwave industry evolves from almost completely military and aerospace functions to more commercial ones, with more stringent cost requirements and tight schedules driven by the need for a short time to market, the software industry is becoming aware of the need for human as well as analytical functionality. This is a worthwhile development. The integration of EM analysis software with circuit-analysis software serves as an example to illustrate this phenomenon. Even well into the late 1990s, it was customary for EM software to run in batch mode on one or more powerful computers. The designer often did not know what parts of a circuit had to be EM simulated until a circuit layout was completed. Then, the circuit elements to be simulated had to be redrawn for the EM simulator, as the layout and EM software’s graphics module were generally incompatible, with concomitant risks of error, and the circuit elements finally simulated. These results were fed back into the circuit-analysis software and the circuit resimulated. The results of the resimulation often were not acceptable, so redesign was necessary, along with another loop through the simulation-layout-EM process. An improvement came with cosimulation, the ability of disparate tools to run simultaneously and to share data. This could be done in a number of ways, supported to a greater or lesser degree by the computer’s operating system. Examples of the latter were Unix pipes and Microsoft Windows’ dynamic data exchange (DDE) capability. These allowed a certain degree of interprocess communication, especially the direct transmission of data between simulators without the user’s intervention. While these technologies allowed input and output data sharing, they did not constitute full integration, as the types of interaction were limited. Today, full integration of circuit simulation with EM, layout, and even system simulation is possible. This capability is supported in part by operating system technology, in particular Microsoft Windows’ component object model (COM) technology, a standard that allows separate software modules to be integrated at the object-code level. As a result, simulators can be fully aware of the operation of other simulators and obtain all the information they need about the effect of one simulator on data they deal with. For example, if the user changes the dimensions of a microstrip tee junction, that change can be reflected instantly in the layout, and the EM simulator becomes aware of the change and can resimulate the junction. In this way, multiple iterations through the simulationlayout-EM loop are avoided, and many sources of error involved in copying data are fully eliminated.

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However valuable these technologies are, they do not let the user “off the hook.” Engineering judgment in their use is still essential. For example, it is not yet possible (although it may be, eventually) for software to determine the optimum setup, in terms of frequency sets and termination criteria, for a harmonic-balance analysis. The user must understand the matter and make appropriate decisions. Similarly, some circuit elements can be modeled more easily and more accurately than others; for example, straight microstrip transmission-line models are invariably much better than closedform microstrip junction models. Such elements should be used preferentially, wherever possible, in microwave designs. Finally, the user must be aware of the effect of certain kinds of model on analyses. The interpolation of S-parameters, for example, can be critical for various types of analysis: linear interpolation can result in passband plots having a scalloped appearance and the lack of smoothness can cause convergence failure. Earlier, we described the problem of S-parameters that do not span the frequency space used in a nonlinear analysis. This also can – and usually does – cause convergence difficulty.

References 1. N. Balabian and T. A. Bickart, Electrical Network Theory, Wiley, New York, 1969. 2. G. Dahlquist and A. Bj¨ork, Numerical Methods, Englewood Cliffs, NJ: Prentice-Hall, 1974. 3. J. Vlach and K. Singhal, Computer Methods for Circuit Analysis and Design, Second Edn., Norwood, MA: Artech House, 1994. 4. M. S. Nakhla and J. Vlach, “A piecewise harmonic balance technique for determination of periodic response of nonlinear systems,” IEEE Trans. Circ. Syst., vol. CAS-23, p. 85, 1976. 5. S. W. Director and K. W. Current, “Optimization of forced nonlinear periodic currents,” IEEE Trans. Circ. Syst., vol. CAS-23, p. 329, 1976. 6. F. R. Colon and T. N. Trick, “Fast periodic steady-state analysis for large-signal electronic circuits,” IEEE J. Solid-State Circ., vol. SC-8, p. 260, 1973. 7. K. S. Kundert and A. SangiovannI–Vincentelli, “Simulation of nonlinear circuits in the frequency domain,” IEEE Trans. Computer-Aided Des., vol. CAD-5, , p. 521, 1986. 8. H. Yeager and R. W. Dutton, “Improvement in norm-reducing methods for circuit simulation,” IEEE Trans. Computer-Aided Des., vol. 8, p. 538, 1989. 9. G. B. Sorkin, K. S. Kundert, and A. Sangiovanni-Vincentelli, “An almost-periodic Fourier transform for use with harmonic balance,” IEEE MTT-S Int. Microw. Symp. Dig., p. 717, 1987. 10. V. Rizzoli, C. Cecchetti, and A. Lipparini, “A general-purpose program for the analysis of nonlinear microwave circuits under multitone excitation by multidimensional Fourier transform,” Proceedings of the 17th European Microwave Conference, 1987. 11. E. Ngoya, J. Rousset, M. Gayral, R. Quere, and J. Obregon, “Efficient Algorithms for spectra calculations in nonlinear microwave circuits simulators,” IEEE Trans. Circuits Syst., vol. 37, p. 1339, 1990. 12. P. Rodrigues, “A general mapping technique for fourier transform computation in nonlinear circuit analysis,” IEEE Microw. Guided Wave Lett., vol. 7, p. 374, 1997. 13. P. Rodrigues, “An orthogonal almost-periodic fourier transform for use in nonlinear circuit simulation,” IEEE Microw. Guided Wave Lett., vol. 4, p. 74, 1994.

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14. K. S. Kundert, J. K. White, and A. Sangiovanni-Vincentelli, Steady-State Methods for Simulating Analog and Microwave Circuits, Boston: Kluwer, 1990. 15. J. C. Pedro and N. Borges de Carvalho, “Artificial frequency mapping techniques for multitone harmonic balance,” IEEE MTT-S Int. Microw. Symp. Dig. Workshops, 2000. 16. V. Boric, J. East, and G. Haddad, “An efficient Fourier transform algorithm for multitone harmonic balance,” IEEE Trans. Microw. Theory Tech., vol. MTT-47, p. 182, 1999. 17. V. Rizzoli, A. Neri, and F. Mastri, “A modulation-oriented piecewise harmonic-balance technique suitable for transient analysis and digitally modulated signals,” Proceedings of the 26th European Microwave Conference, 1996, p. 546. 18. E. Ngoya, J. Sombrin, and J. Rousset, “Simulation de circuits et systemes: methodes, actuelles et tendances,” Seminaire Antennes Actives-MMIC, Arles, Arles, France, 1994. 19. E. Ngoya and R. Larcheveque, “Envelop [sic] transient analysis: a new method for the transient and steady-state analysis of microwave communication circuits and systems,” IEEE MTT-S Int. Microw. Symp. Dig., p. 1365, 1996. 20. D. G. Swanson and W. J. R. Hoefer, Microwave Circuit Modeling Using Electromagnetic Field Simulation, Artech House, Norwood, MA, 2003. 21. J. Rautio, “Synthesis of compact lumped models from electromagnetic analysis results,” IEEE Trans. Microw. Theory Tech., vol. MTT-55, p. 2548, 2007.

6

Practical HF/VHF/UHF RF power amplifier realization Daniel P. Myer Communication Power Corporation (CPC)

6.1

Introduction This discussion focuses on the practical realization of radio frequency power amplifiers (RFPAs), the process that exists between nothing and something, the path an RFPA design engineer can take from the RFPA application conceptual phase to the construction of actual hardware. Since the end use application/market defines and drives the need for an RFPA, an overview of major application areas is covered initially. The applications will demand that certain RFPA specifications are satisfied, so an overview of generic amplifier specifications relative to several applications is logically provided next. The specifications are viewed from several vantage points, i.e., they are covered qualitatively, in other words, for a particular application, which RFPA specifications are most relevant. Then they are defined quantitatively, not so much for a unique application, but with a bias towards the RFPA itself, with an effort to provide a guideline as to what constitutes a realistic specification value, and what does not. The chapter will end off with a design example that originates with a hypothetical application and uses the concepts presented to generate a specification and RFPA module design to satisfy the requirement. Again, this is a chapter on practical realization, while it will cover some theoretical aspects of RFPA design, it will also cover how to construct the amplifier and emphasize test configuration/data analysis. The goal is to help facilitate a design that can not only be manufactured once, but in volume with design margin, and profitability.

6.2

RF power amplifier markets There are several major markets or end use application areas of RFPAs, the more common ones are: r r r r r

military; medical; scientific; industrial; commercial.

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Within these broad areas there exist a host of unique applications where the RFPA finds a home: r Military: communications, communication jamming, improvised explosive device (IED) Jamming, countermeasures, radar, and psychological warfare; r Medical: magnetic resonance imaging/spectroscopy (MRI/MRS), thermotherapy, cardiac tissue ablation, benign prostatic hyperplasia (BPH) treatment, RF cauterizing; r Scientific: nuclear magnetic resonance (NMR) spectroscopy, nuclear quadrupole resonance (NQR), electron paramagnetic resonance (EPR) r Industrial: electromagnetic compatibility testing (EMC), RF heating/drying, adhesive compound curing; r Commercial: semiconductor wafer plasma processing, cellular base stations, AM/FM radio, HDTV broadcast. All these applications have one thing in common; an RFPA is essential and vital to the process. But just having any RFPA, will not suffice either, i.e., an RFPA designed for MRI could not be used effectively for HDTV broadcast and vice versa. Each application carries with it a unique set of requirements or specifications that the RFPA, if it were to be used successfully, must meet. All RFPAs have certain operating characteristics, and for each unique application, some are more important than others. In a satellitebased RFPA, for example, efficiency is very critical due to limited power availability, on the other hand an MRI RFPA specification is more focused on linearity and less on efficiency. For the applications listed above, a brief overview of some of the required RFPA specifications for each discipline is provided in the following paragraphs.

6.3

The realization process RFPA realization is, in a broad sense, a three-step process: 1. RFPA qualitative specification delineation: A task concerned with assessing a particular proposed application that requires an RFPA and distilling out of the multitude of existing amplifier performance specifications, only the ones necessary and sufficient (in other words, required specifications) that once quantified, will define a list of amplifier characteristics to satisfy the end use application. For example, consider the application of RF heating. RFPAs are used in this requirement to heat materials (plastics, human tissue, etc.) with its output power. Clearly, there is no need, for instance, for good phase linearity, the material to be heated will not respond any differently to an RFPA that has excellent phase linearity than with one that does not. This step of qualitative specification delineation is by no means a trivial process and is executed best by maintaining a close working relationship between the RFPA engineer and the system engineer intimate with the given application. Simply because an RFPA Engineer knows, for example, how to design an amplifier with excellent linearity does not necessarily mean he is aware of what distortion types to assess in order to

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enable good picture quality from a TV transmitter. The TV system engineer will know these parameters based on his field experience. Since there are many applications for RFPAs, this step is only covered here in a cursory sense, such that the RFPA Engineer is aware and informed of its importance. 2. RFPA specification quantification: With a list of required RFPA specifications relative to a given application assembled, the next step is to assign numeric values to each particular one along with a clarification of what the numbers represent; i.e., minimum, maximum or typical. An arrival at a particular number for a certain specification usually is the result of field trials where system performance is monitored while only the amplifier parameter of interest is successively degraded to the point where it becomes evident in the overall system performance. An RFPA Engineer must be very familiar with amplifier specifications not only for what they imply but also for what value represents a realistic application demand and one that is not physically or economically realizable. Therefore, an overview and definition of RFPA specifications is provided along with highlighting both ideal and typical values to provide the RFPA Engineer with a frame of reference or boundaries from which to work in during the realization process. The typical values are what one might expect to get from a generic RFPA without any form of error correction applied. 3. RFPA hardware realization: Following the specification delineation and quantification, a design example is provided to illustrate methods to physically realize RFPA hardware. This step will define the basic architectural components of an RFPA module: the RF transistor, matching networks, feedback networks, DC bias and supply networks. An RFPA module design that can be applied to several applications will be shown as a design example.

6.3.1

RFPA qualitative specification delineation Military amplifiers: For just about any application in the military or defense market, one amplifier characteristic is paramount: reliability. RFPAs for military applications must endure extreme, harsh environmental conditions (temperature, altitude, salt fog, exposure to aviation fuels and sand, etc.) and perform flawlessly. In the event that they do encounter some partial malfunction, then they need to be “battle sure.” This implies the RFPA must provide some level of performance and be expected to override fault protection shutdown circuitry in spite of the fact that it may be damaged. Military communications require an RFPA to be extremely broadband, adverse load VSWR tolerant, and if the modulation format demands it, have excellent linearity. For applications where an RFPA is battery powered, high levels of amplifier efficiency are needed. Jamming/countermeasures applications require extreme broadband capability and antenna load VSWR tolerance. Linearity is not overly important as the goal may sometimes be to overpower enemy communications and distortion components may actually augment the process.

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Radar RFPAs will need to work well in the time domain and maintain good pulse fidelity; fast rise and fall transition durations (formerly known as rise/fall times), lowpulse tilt (amplitude droop), and have and low levels of pulse overshoot and ringing. Amplifiers used for psychological warfare operations (Psy-Ops) are generally used for emulation of enemy civilian and military communication systems which can be either AM/FM radio or television broadcast. In this event, RFPAs will need extreme bandwidth to cover multiple channels along with high linearity and very low intermodulation distortion (IMD). Medical Amplifiers: Amplifiers for the medical market need to be reliable as well; however, the environment they are exposed to is very benign. Usually RFPAs in medical applications are located in hospitals or research institutions where the ambient temperature remains at approximately +25 ◦ C. MRI and MRS, which provide detailed anatomical and metabolically profiled human images, demand the RFPA deliver certain levels of performance in three domains: time, power and frequency. In the time domain, the RFPA must deliver high levels of pulse fidelity (fast rising and falling transition durations, low-pulse tilt, low overshoot and ringing). In the power domain, the RFPA must exhibit low levels of AM/AM and AM/PM (gain and phase linearity, respectively) distortion. In the frequency domain, the MRI/MRS RFPA must deliver uniform performance at several key frequencies, while having low noise output at frequencies other than the carrier, specifically while the RFPA is transmitting the carrier. For medical heating (thermotherapy, cardiac tissue ablation and benign prostatic hyperplasia treatments), the focus is on precise power control. To heat human tissue safely, a feedback control (ALC) loop is the best method for keeping the RF power output variations extremely low. Linearity is not necessarily critical but does enable the RFPA to be more easily controlled by feedback loops. Medical heating is usually narrowband (i.e., 915 MHz + / − 5 MHz), and while the load VSWR may be harsh, the RFPA’s output can be protected with Circulators. Scientific Amplifiers: NMR spectroscopy employs all the same principles as MRI except, instead of analyzing patients, an NMR Spectrometer will evaluate chemical compounds or pharmaceuticals. NMR essentially makes the same demands on an RFPA that MRI would, however an amplifier for NMR/NQR and EPR will require more precise pulse fidelity (faster rising/falling transition durations, lower droop and virtually nonexistent pulse ringing/overshoot). Industrial Amplifiers: EMC RFPAs must provide RF power over ultra broad bandwidths spanning several octaves from the audio frequency range up into the microwave frequency range (10 kHz to over 1 GHz). EMC RFPAs are used to test the radiated “susceptibility” of electronic products. This is the product’s ability to maintain normal operating functions while being subjected to external RF radiation. The EMC RFPA output will be fed into wideband antennas which will radiate RF energy into products under evaluation. Material heating and Compound curing demand that the RF power be precisely controllable and stable over temperature and time.

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Commercial amplifiers: Amplifiers for semiconductor wafer processing must be able to withstand severe load VSWR. While these RFPAs usually have a matching network which works to actively match the impedance of the plasma, there still exist severe transient load VSWR excursions. These amplifiers must also have extremely reliable performance as an amplifier failure can lead to shutting down wafer fabrication production lines. Cellular base station RFPAs must handle multiple carriers simultaneously. Due to this requirement, these RFPAs must be extremely linear such that IMD distortion is minimized. Typically, the IMD requirement is much lower than can be achieved with a stand alone, un- corrected RFPA. Therefore, error correction schemes such as pre-distortion and feed-forward are employed to reduce IMD components below required limits. AM radio transmitters require good linearity while FM transmitters have a stronger emphasis on efficiency and low cost. Conventional television transmitters place high demands on signal linearity. Reviewing the applications, it is apparent that certain RFPA operating parameters are instrumental in defining an RFPA for one application, but are absent in another while some are common to all.

6.3.2

RFPA specifications, generic list and quantification guidelines The RFPA specifications simply define, quantitatively, the manner in which a particular RFPA must behave under a given set of conditions. The conditions are input stimulus signal characteristics, expected output signal response performance (transfer function), output load VSWR, supply voltages, environmental (operating/storage) conditions (temperature, shock, vibration and altitude). A list of generic RFPA specifications is provided below with definitions accompanied by quantifications of what an ideal amplifier would deliver, followed by what a typical one might provide. The typical values represent what is readily accomplished with a generic broadband amplifier, the more a requirement demands a particular specification quantification to propagate towards an ideal value, the more difficult(and costly) it will be to design and manufacture the amplifier. The quantifications are not indicative of any particular end use application, the goal is to provide the RFPA engineer with a common sense, a feel for what is readily attainable, and what is not. r Power output (units: W): the amount of power an RFPA can deliver into a particular load VSWR, over a given frequency and dynamic range. What is ideal: the RFPA would deliver the precise amount of power demanded by a particular application, This power level would be exact, proportionally controllable, with zero power level fluctuations due to temperature, component variation and free of noise and distortion components. What is typical: a power level that varies in a quasi linear fashion and drifts a few watts for every few degrees shift in ambient temperature along with a power spectrum of noise and distortion components. r Frequency response/range (units: Hz): the range of frequencies that an RFPA is expected to uniformly meet all specifications. What is ideal: a range of frequencies

6.3 The realization process

r

r

r

r

r

r

237

were the RFPA exhibits flawless uniform(identical time and power domain responses) performance (stable power, no distortion or noise), outside of this range the amplifier has no response to any other frequencies. What is typical: a range of frequencies where performance is not uniform; i.e.: gain will vary by several dB, distortion and noise will be present, rise and falling transition durations vary along with efficiency. Gain (units: dB): the measure of how much greater in power an RFPA will increase the level of an input signal. What is ideal: the output power is an exact, constant, linear multiple of the input power that is independent of frequency, temperature and drive level. What is typical: gain variation of 1–5 dB across a given bandwidth, a shift in value of a few tenths of a dB for every few degrees change in ambient temperature. Gain flatness (units: + / −dB): the amount of gain variation over the specified frequency range. What is ideal: absolutely no ( + / −0 dB) of gain variation over the required frequency range. What is typical: depending on the required bandwidth, the gain flatness can vary about a nominal value from + / −0.5 dB to + / −4 dB or more. Gain flatness is very difficult to maintain over wide frequency ranges (>1 octave). Gain linearity/AM-AM distortion (units: + / −dB versus a specified power domain dynamic range): the ability of an amplifier to hold its gain constant throughout the application of an RF input signal with varying power levels. What is ideal: the RFPAs nominal gain value (gain = G dB + / −0 dB) remains perfectly constant from an output power of 0 W to the maximum power demanded by the application. What is typical: gain variations of + / −1 dB are readily achieved by Class A and AB amplifiers, over a dynamic range of 40–60 dB. Gain linearity is class dependent with Class A being the most linear and least efficient, while Class D/E are the most nonlinear but most efficient. Gain temperature stability (units: + / −dB): the ability of an RFPA to hold its gain constant over varying levels of ambient temperature. What is ideal: absolutely no ( + / −0 dB) of gain variation regardless of ambient temperature variations. What is typical: gain variations of 6 dB over temperature swings of −10 to +80 ◦ C are common. The variations are easily corrected for with ALC control loops or open loop gain stabilization networks. Gain stability of + / −0.25 dB over 40–50 ◦ C is achievable with open loop temperature compensation networks. ALC loops can improve these values further. Phase linearity/AM–PM distortion (units: + / − ◦ versus a specified power domain dynamic range): insertion phase linearity or AM to PM distortion, is the ability for an RFPA to hold its insertion phase constant over varying output power levels. What is ideal: an insertion phase variation of Θ + / −0 ◦ from zero power output to full rated power. What is typical: an insertion phase variation of + / −10 to + / −15 ◦ around a nominal insertion phase value (Θ) over a 40–60 dB dynamic range is easily achieved via Class A amplifiers. Predistorted and feed-forward amplifiers can have much less phase variation. Dynamic range (units: dB): the range of output power levels that an RFPA must work over. Usually the maximum power output is the upper limit. What is ideal: the RFPA’s output would be linearly controllable with no non linear deviations from exactly 0 W

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r

r

r

r

r

r

to the required maximum rated power. What is typical: the linear classes of RFPAs; A, AB, and B offer the best dynamic range (approx 40–60 dB), Class C, D, and E have limited dynamic ranges (<10–15 dB uncorrected; i.e., without pre-distortion). The low end of the dynamic range is limited by it noise floor, the high end would be bounded by unacceptable levels of nonlinear gain compression or expansion. Efficiency (units: %): the amount of DC input power an RFPA will require to produce a given amount of RF output power. What is ideal: theoretical maximum efficiency for the specific amplification class. What is typical: Class C, D, and E offer the best methods for high efficiency, >50–70% and relatively constant over a limited dynamic range; however, linearity (both gain and phase) will suffer. Broadband Class AB efficiency runs in the 40% range, but drops substantially at reduced power output levels. Rise time (rising transition duration) (units: s): the amount of time it takes an RFPA to progress from 10 to 90% (in voltage) of any given rectangular RF pulse output. What is ideal: the amplifier’s output power rising transition duration is exactly equal in time to the RF input signal’s rising transition duration, regardless of how fast or slow. What is typical: rise times of 250–750 ns are readily accomplished. Fall time (falling transition duration) (units: s): the amount of time it takes an RFPA to progress from 90% to 10% of any given RF pulse output. What is ideal: the amplifier’s output power falling transition duration is exactly equal in time to the RF input signal’s falling transition duration, regardless of how fast or slow. What is typical: fall times of 50–500 nS are readily accomplished. Pulse overshoot (units: %): the amount an RFPA’s output deviates from an expected 100% output power value during the period directly following the rise time transition duration. What is ideal: 0% overshoot, the amplifier’s output exactly follows the input. What is typical: 10–15% overshoot is common though controlling overshoot becomes more problematic with faster rising transition duration times along with lower operating frequency range into the 1–30 MHz range. Pulse droop (pulse tilt) (units: %): the amount an RFPAs output either decreases (negative tilt) or increases (positive tilt) across the duration of a rectangular RF output pulse. What is ideal: 0%, an RFPA with a perfectly flat rectangular RF input pulse delivers an amplified exact replica on the output. Note: pulse tilt can be an extremely elusive pulse parameter to define let alone design for or even measure. The most problematic issue with pulse tilt is the pinpoint assignment of the 100% power amplitude discrete location on the rectangular RF pulse envelope which will serve as the reference point. Pulse waveforms can manifest themselves in an infinite amount of subtly different shapes, even if they are all classified as “rectangular” pulses. What is typical: a pulse tilt value of 10% is common. Less than 5% becomes very difficult to manage over broad frequency and dynamic ranges. Ringing/settling time: (units: seconds): The duration of time that an RFPAs output overshoots and exponentially decays sinusoidaly down to a 100% pulse power output. What is ideal: absolutely no ringing or overshoot which might initiate ringing. What is typical: depending on the frequency range and rising transition duration time, ringing can occur and last for 20–500 nanoseconds or perhaps longer.

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r Distortion, harmonic (units : -dBc): the level of unwanted signal components which are integer multiples of the RF input signal frequency that are measured relative to the magnitude of the RF output signal. What is ideal: absolutely no harmonics, the only output of the amplifier is a replica of the input RF spectrum, with all frequency components amplified exactly the same. What is typical: even-order harmonics are less than −20 dBc at the second-order harmonic and decreasing further at higher even-order frequencies, Odd-order harmonics are less than −12 dBc at the third-order harmonic and decreasing further at higher odd-order frequencies. r Distortion, inter-modulation (units: dBc): the level of unwanted signal components that arise from the application of two or more RF input signals propagating through a nonlinear medium. The distortion signals are close in frequency to the original input signals. What is ideal: there are no IMD components, the output frequency spectrum is an exact, amplified replica of the input spectrum. What is typical: IMD distortion components will typically fall −20 to −30 dBc down from the two-tone output signals. r Noise floor (units: dB relative to thermal noise floor): the amount of noise an amplifier puts out when its input is terminated with a 50  resistor. RF power amplifiers typically are not concerned with noise as their primary task is to provide large amounts of electrical energy. In other words, the amplifier, per se, can be a substantial noise source. There are, however, situations where an RFPA may be required to emit as little transmitted noise as possible at frequencies other than the carrier. What is ideal: the amplifiers noise output is zero dB over the noise power of a 50 Ω resistor. What is typical: a noise output level of 10–15 dB above the thermal noise of a 50 Ω resistor. r VSWR, input (units: dimensionless): a measure of the RFPAs ability to keep its input impedance close to a specific value (i.e., 50 ) over a given frequency range so as to achieve a maximum transfer of power from a signal source to the amplifier input. What is ideal: a 1:1 VSWR is a perfect match, all the signal sources power will enter into the input port of the RFPA for all frequencies. What is typical: a 2:1 VSWR (or less) over a broad frequency range is commonly acceptable. Usually the input of an RFPA requires a small amount of signal power (on the order of 0 dBm), so a 2:1 VSWR corresponds to approximately 90% of the signal source power entering into the RFPA’s input port. r VSWR, load (units: dimensionless): a measure of the RFPA’s output impedance relative to a given load. An RFPA’s output impedance is a dynamic parameter depending on a variety of variables; power output, supply voltage and frequency. It is a desirable to match the RF transistor to its load impedance for maximum power transfer. Unfortunately, for many applications, the load will vary widely and present a serious challenge to the RFPA Engineer to design an RFPA that can withstand adverse load VSWRs and maintain specified performance. What is ideal: a perfect match, 1:1 VSWR for all frequencies and power levels. What is typical: this depends heavily on the end use application, but can vary anywhere from a close match 1.2:1 to an open or shorted load (∞:1). r Stability, spurious output, load pull dependent (units: -dBc): this defines an amplifiers ability to maintain stable operation (i.e., not generate any unwanted spurious signals and maintain an output power that remains controlled by the input power

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and a stable transfer function) while the input/output load VSWR is varied. This is sometimes defined as load pull stability. A word of caution here to those who specify or have been requested to design an amplifier as “unconditionally stable,” implying the amplifier will not oscillate terminated by any input/output load VSWR. While there does exist ways to theoretically show an amplifier is unconditionally stable into adverse loads, it is strongly argued here that no such thing as a truly “unconditionally stable amplifier” has or ever will exist in the real world. The basis for this argument is that any physical amplifier whether broadband or narrowband, can be subjected to virtually infinite number of operating points, assembly process control variations, device lot/date code variations and changing environments, be it frequency, output power levels, operating temperatures, modulation formats, input/output port isolation values and combinations of complex input/output load terminations. To be certain, there will be one combination of the listed operating points that will cause an oscillation or some level of spurious output. Since an infinite amount of operating points exist, it would require an infinite amount of time to test and verify a given amplifier is “unconditionally stable,” unfortunately (or perhaps fortunately, at least for the poor soul tasked with testing an RFPA for unconditional stability) no one can live long enough to test and confirm this. What is ideal: unconditional stability, no oscillations for any condition of operation. What is typical: conditional stability, the amplifier will be stable under a defined, discrete set of conditions such as Load VSWR up to a given point (i.e., 3:1, fully rotational about the Smith Chart), dynamic range, fixed frequency ranges, or at an output for spurious frequencies that are an acceptable amount below the carrier. Typical values of load pull spurious are −40 to −60 dBc. r Operating temperature range (units: degrees): the temperature range over which the amplifier will be expected to meet all specifications. Every component in an RFPA will have electrical characteristics that are temperature dependent. This dependency can cause an RFPA to be specification compliant at one temperature and out of specification at another. The key is to design the RFPA so that the effects of varying temperature are minimized. What is ideal: the RFPA will operate uniformly at all temperatures with no variation in gain, output power, distortion, etc. What is typical: the RFPA will operate over a limited temperature range (−50 to +125 ◦ C, for example) where the high end of the temperature range is determined by the RF power transistor’s junction temperature and required failure rate. r Altitude (units: feet, meters above mean sea level (AMSL)): the altitudes within which the amplifier is expected to meet full specification. Altitude can impact an RFPA’s performance primarily with ones that use forced air cooling as air becomes thinner are higher altitudes, rendering the efficacy of this cooling method problematical. What is ideal: an RFPA is operational from Submarine to Outer Space with no variation in performance. What is typical: the RFPA is limited to certain altitudes by the method by which heat is removed, for low altitudes forced air cooling is adequate, for high altitudes and space, liquid cooling becomes more effective. r Shock/vibration (units: G, rms): the level of six axes (x, y, z and rotational: yaw, pitch, and roll) mechanical energy an RFPA can withstand and still be specification compliant. What is ideal: the RFPA can withstand exposure to shock and vibration

6.3 The realization process

241

resulting from transportation (shipping) and application (military applications: airborne, ground transport, colocated ordinance etc.) and remain functional regardless of what level of mechanical shock is imparted. What is typical: an RFPA will have set limits of how much shock the unit can endure, amplifiers have been designed to withstand as much as 5000 G of transient shock and as much as 60 G of continuous, random, six axis vibration. r Conducted/radiated emissions: the level of unwanted RF noise whether signal, spurious, distortion or other that gets out of the RFPA either on physical wires (conducted emissions) or through an improperly shielded enclosure (radiated emissions). What is ideal: the RFPA will contain all radio frequency energy within the confines of the physical housing of the amplifier system. The RF energy will only exit the chassis through coaxial cables and connectors. What is typical: all RF power amplifiers will emit and conduct some level of RF energy unintentionally to other collocated circuits, subsystems, and equipment, shielding measures must be deployed such that the emissions are within acceptable limits based on the particular application EMC guidelines. r Conducted/radiated susceptibility: the ability of an RFPA to maintain its specified performance with unwanted signal/spurious/noise energy from other collocated circuits, subsystems and equipment getting into its on physical wires (conducted susceptibility) or through improperly shielded RFPA enclosures (radiated susceptibility). What is ideal: an RFPA can operate normally regardless of being subjected to any level of electromagnetic (EM) interference or impulse. What is typical: All RF power amplifiers will be affected at some level of RF energy unintentionally coupled into it from collocated circuits, subsystems and equipment. Shielding measures must be deployed such that the susceptibility thresholds are within acceptable limits based on the particular application EMC guidelines. r Mean time to failure (units: hours): the average amount of time an amplifier will function before experiencing a malfunction or failure. What is ideal: a particular amplifier will be operated within its specified ranges and perform flawlessly indefinitely. What is typical: it depends heavily on the temperature of the RFPA’s semiconductor or “die” temperatures, MTTFs of 20,000 to 100,000 h are common.

6.3.3

Specification/hardware realization Regardless of the application, a specification defining an RFPA will draw from some or all the above listed Operating Specifications. How these parameters are specified closely influence how a particular RFPA design is realized. There are multitudes of applications for RFPAs, it is nearly impossible to illustrate one particular method to realize an RFPA design for each. However, it is possible to cover techniques that can address Specifications that are common to several applications. The steps exhibited and taken will progress from specification delineation and quantification to block/wire design, then to RFPA module design.

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Figure 6.1 Simplified system level block and wiring diagram for a typical RFPA system.

RFPA system design can be best accomplished by working “backwards” if you will. That is, an RFPA system design begins by starting with the maximum RF power requirement of a particular application, and designing the RFPA output section first, as opposed to last. We begin with output section first for the following reasons: 1. The application (or end use) demand for RF power is the first and foremost requirement for an RFPA to meet and the output section addresses this directly. 2. How the output module design of the RFPA evolves, and what its transfer/distortion characteristics are, will dictate the design of the stages that will precede it (low-level driver and intermediate power amplifier stages). 3. Depending on what RF power transistors are chosen for the RFPA section and how they perform from a DC standpoint (i.e., DC operating voltages and DC current demands) will also determine what type of DC power supplies are required.

6.4

RFPA system level design overview The step following specification delineation and quantification for a RFPA system design is the System Block and Wire diagram. A simplified System Block and Wire diagram is shown in Figure 6.1 for a 1 kW amplifier example. The architecture in this diagram can be used to realize any RFPA system application requirement. It shows the basic elements or subsystems: r low-level driver stage; r intermediate power amplifier stage; r RF power divider;

6.4 RFPA system level design overview

r r r r r

243

RF power amplifier section (usually consisting of multiple, identical RFPAs); RF power combiner; directional coupler; DC supply section; digital control section.

The top of the system level block and wire diagram shows the output power requirement of each stage and above each subsystem block diagram are typical gain/loss values relative to each stage. Working the power requirement from right to left, it is apparent how the application power requirement demands a focus on the output RFPA section first. Based on the application power requirement, we need to select aN RF power transistor that can provide adequate RF power, and most importantly, provide the necessary power while concurrently satisfying the application requirements for linearity, efficiency, distortion, transition duration response times and anticipated load VSWR excursions. Another reason for working on the RFPA output first is the initial verification of meeting specifications on a modular, scaled down level. If, for example, distortion levels cannot be met on a modular level, either the designer has to improve the RFPA module design or plan for ways to provide system level error correction. There are a variety of processes occurring in any RFPA system; however, if you were to break them down and classify them, there are primarily two: r power amplification; r power transfer. Power amplification, obviously, is accomplished with the RF power transistors; power transfer is accomplished with matching networks, dividers and combiners. Therefore, it is readily apparent that RF device selection and impedance matching will be critical steps.

6.4.1

RF power amplifier module design overview After the block/wiring top level system design, the output RFPA section itself can be broken down further into a generic lower level block diagram as show in Figure 6.2. RF power modules have the some or all of the following basic sections: r r r r r r

RF power transistor; device bias/temperature compensation network; input/output RF and DC coupling/decoupling networks; input/output matching networks; feedback networks; heat removal.

This leads to the first major task in RF power amplifier stage realization: selection of an RF power transistor. This is perhaps the single most important decision the RF power amplifier design engineer makes, there are other decisions, for sure, but this is the most critical. This is also not a decision that is made by merely comparing RF transistor data

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Practical HF/VHF/UHF RF power amplifier realization

Figure 6.2 Block diagram of the component level view of an RFPA module.

sheets of different RF transistor manufacturers; it is a decision that is made after data sheet review, CAD simulation, prototyping, rigorous testing of individual PA stages and then comparison of actual, application specific results. Careful review of RF transistor data sheets is a very important, albeit initial step. Figure 6.3 is part of a typical RF power transistor data sheet. Although the data sheet contains a large amount of data, determining whether or not a particular device is suitable for a given application may not be readily apparent when reviewing it. The reason is that RF power transistor manufacturers simply cannot fully anticipate all the applications for which a particular device may be deployed, they will make generic recommendations for applications, but it is up to the RF power amplifier design engineer to make the final judgment call, and only after several devices have been tested and evaluated. In spite of its vague nature, the RF transistor data sheet is at least a starting point. The following is a brief overview of its major sections: 1. Applications: manufacturers recommendation of potential applications for the device; i.e.; medical, broadband, VHF communications, etc. 2. Absolute maximum ratings: maximum values for power dissipation, junction temperature, supply/breakdown voltages and device currents. 3. Electrical characteristics: quantification of key parameters: r power output: how much power the device can reliably deliver when matched into a 50  load. r frequency range: what frequencies the device can be used over. r gain: typical power gain level, usually at the maximum operating frequency. r efficiency: how efficiently the device can convert DC power into RF power. r thermal resistance: a measure of the devices ability to remove the heat of its semiconductor dies to an outside surface.

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6.4 RFPA system level design overview

TetraFET

D1020UK METAL GATE RF SILICON FET MECHANICAL DATA

B

C (2 pls)

2

G (typ)

3

1 H

P (2 pls) A

D

4

5

E (4 pls)

GOLD METALLIZED MULTI-PURPOSE SILICON DMOS RF FET 150 W – 28 V – 400 MHz PUSH–PULL

F I

FEATURES • EXTRA LOW Crss

N

O

M

J

K

• SIMPLIFIED AMPLIFIER DESIGN

DR PIN 1 PIN 3 PIN 5

SOURCE (COMMON) DRAIN 2 GATE 1 DIM A B C D E F G H I J K M N O P

Millimeters 19.05 10.77 45° 9.78 5.71 27.94 1.52R 10.16 22.22 0.13 2.72 1.70 5.08 34.03 1.61R

PIN 2 PIN 4

DRAIN 1 GATE 2

• SUITABLE FOR BROADBAND APPLICATIONS • SIMPLE BIAS CIRCUITS

Tol. 0.50 0.13 5° 0.13 0.13 0.13 0.13 0.13 MAX 0.02 0.13 0.13 0.50 0.13 0.08

Inches 0.75 0.424 45° 0.385 0.225 1.100 0.060R 0.400 0.875 0.005 0.107 0.067 0.200 1.340 0.064R

Tol. 0.020 0.005 5° 0.005 0.005 0.005 0.005 0.005 MAX 0.001 0.005 0.005 0.020 0.005 0.003

• LOW NOISE • HIGH GAIN – 10 dB MINIMUM

APPLICATIONS • HF/VHF/UHF COMMUNICATIONS from 1 MHz to 500 MHz

ABSOLUTE MAXIMUM RATINGS (Tcase = 25 °C unless otherwise stated) PD

Power Dissipation Drain – Source Breakdown Voltage * Gate – Source Breakdown Voltage * Drain Current * Storage Temperature Maximum Operating Junction Temperature

BVDSS BVGSS ID(sat) Tstg Tj

389 W 70 V ±20 V 25 A –65 to 150 °C 200 °C

* Per Side Semelab Plc reserves the right to change test conditions, parameter limits and package dimensions without notice. Information furnished by Semelab is believed to be both accurate and reliable at the time of going to press. However Semelab assumes no responsibility for any errors or omissions discovered in its use. Semelab encourages customers to verify that datasheets are current before placing orders.

Semelab plc.

Telephone +44(0)1455 556565. Fax +44(0)1455 552612. E-mail: [email protected] Website: http://www.semelab.co.uk

Document Number 2599 Issue 5

Figure 6.3 Typical datasheet of an RF power transistor (courtesy Semelab Ltd., UK).

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Practical HF/VHF/UHF RF power amplifier realization

r breakdown voltages: voltage levels (at the device terminals) where the device will break down and fail. r threshold voltages: range of DC voltage levels (for FETs) where the device begins to conduct current. r load mismatch tolerance: a measure of what level of load VSWR the device can safely tolerate. r large signal impedances: usually plots of large signal input/output impedances plotted on a Smith chart that the device needs to see in order to deliver its rated power output, gain and efficiency at a specific power input, frequency, supply voltage and bias current. r typical transfer function plots: power output, efficiency, gain and distortion versus power input and output. r typical scattering (S) parameters versus frequency for broadband computer aided simulation. r input, reverse transfer and output capacitances versus supply voltage plots which visually show how the devices parasitic capacitance varies as a function of supply voltage.

6.4.2

RF power transistor device selection process guidelines The following is a discussion in more detail of each major section of a typical RF transistor data sheet. Proper RF transistor selection starts by taking into consideration the intended application, in other words, primarily what RF signal/modulation format the RFPA will ultimately be expected to amplify, to what power level with an acceptable level of distortion. A particular application may not demand a power level that will exceed that of an individual transistor, however if it does, combiners and dividers must be employed to reach a desired power output level. In either case, whether an RFPA design requires one or more RFPA stages, the system level specification must be met with substantial design margin at the individual final output stage level (if one transistor stage has adequate power) or scaled up (if one transistor stage does not have enough power).This margin will be eroded as more amplification stages are cascaded. Inside the device selection process exists the decision not only for what particular part within a class of transistors but also a selection of the specific class of transistor itself. By “class” of transistor, it is meant bipolar junction transistor (BJT), vertically diffused MOSFET(VDMOS), laterally diffused MOSFET (LDMOS), gallium arsenide FET (GaAsFET), gallium nitride (GaN) and silicon carbide (SiC) transistors. No one class of transistor is universally better than the others, each class of device has salient features that make it more amenable to a particular application than another. While BJT transistors have less gain and are more difficult to match across broad bandwidths than their MOSFET counterparts, in some pulse applications they can exhibit faster rising and falling transition durations. A disadvantage of BJTs currently is that there are fewer companies manufacturing these devices. MOSFETs (both vertically

6.4 RFPA system level design overview

247

and laterally diffused) offer higher Gain, easier bias configurations, higher large signal impedances and are less prone to thermal runaway. A limitation of MOS FETs is the availability of devices operating broadband over 1 GHz. GaAsFET and especially GaN devices offer excellent choices for ultra-broadband operation from 20 MHz to over 6 GHz. However, GaAS and GaN devices are more expensive and require more sophisticated bias schemes (sequencing) to safely turn the devices on. Silicon Carbide transistors offer a significantly higher maximum junction temperature ( + 255 ◦ C as opposed to + 200 ◦ C for LDMOS). Therefore, in the device selection process, the initial step is selection of which class of RF power transistor, then selection of a particular device within that class amongst device power levels and different manufacturers. Although it may be desirable to use as few RF power transistors as possible, there are applications and situations where it can be prudent to use multiple devices as opposed to fewer. For example, in mission critical Military applications, where reliability and “battle sure” characteristics are key, it is preferable to use more RF power transistors since the heat will be spread out over more devices (which can yield lower die temperatures) and in the event there is a single device failure, the impact on overall system performance is minimized. With this in mind, RF power transistor data sheets within a preselected class are first compared in terms of end use application compatibility. Although RF device manufacturers would prefer to make one transistor suitable for all uses, they do at some point optimize transistors to lend themselves better to certain applications. For example, Avionics RFPAs operate primarily in pulse mode and there exist RF transistors that are designed to put out substantial power, but expressly in pulse format. Try to get the same power out of this device in CW mode (or even extended pulse widths for that matter) and the device will be destroyed. A close review of absolute maximum ratings will cover just how far the device will hold up under extreme conditions such as maximum dissipation and junction temperature. The power output of a transistor states how much RF power a device can deliver. Take care in reviewing this parameter and note the conditions in which the device manufacturer has specified the output power. Remember, the RFPA has to deliver power, but is more accurate to state the RFPA has to deliver concurrent power, that is, deliver power while concurrently maintaining a variety of other specifications such as distortion levels, pulse fidelity, efficiency, etc. A particular transistor may deliver 300 W of RF power, but if the application demands 300 W of power with less than 1 dB of Gain Compression and your device is compressing 5 dB, the device, while capable of delivering the power is not capable of concurrently delivering the power at the required Gain and Gain Linearity level. The frequency range of a particular RF device should not be thought of in an absolute sense, that is, if a power transistor has a maximum specified frequency of 500 MHz, this does not mean the device will cease to function at 501 MHz. It will function at 501 MHz, it may even function at 600 MHz, and you may be able to use it there, but bear in mind if you do other parameters may not remain in specification such as minimum

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Practical HF/VHF/UHF RF power amplifier realization

Gain. The designer who does operate transistors far above their maximum frequency should do so only with a good amount of design margin. The gain specification of RF power transistors depends on many factors, frequency of usage, how the device is matched (narrowband versus broadband), output power level, temperature and load VSWR. Usually, a manufacturer will rate a device at a minimum gain at a particular frequency. This is a minimum value; however the devices they supply will usually have gain in excess of this amount. For the application where large quantities of amplifiers are expected to be produced, be cautious to design an RFPA stage that anticipates the “minimum,” and NOT “typical” gain of the device. The reason is that over time, the wafer fabrication process may yield transistors with lower gain than the typical value, and if you have designed a stage to require a device with typical gain, if a lot code of transistors is delivered with minimum gain, your amplifier will be out of specification and there will be no recourse with the manufacturer. A way of insuring your transistors are more uniform in performance is to put their performance under the restrictions of a source control drawing, or SCD. The SCD is a document of mutually agreed upon RF Transistor performance specifications, where the two parties in the agreement are the transistor manufacturer and RFPA manufacturer. This document calls out tighter performance specifications than exist on the standard device data sheet. It will force the device manufacturer to “cherry pick” devices from a lot that meet the values in the SCD. This will invariably lead to higher transistor costs, especially if the volume is low, but this issue can be eradicated by high-volume production quantities. How efficient a transistor operates is tied in closely with what class of amplification the transistor is biased to, if it is operated broadband or narrowband, what load VSWR it sees and what type of power combiner (zero degree versus quadrature) is used to sum the power of multiple stages. Usually, the efficiency listed on a data sheet was measured under narrowband, conjugate matched conditions so broadband efficiency will be lower and frequency/output power level dependent. The thermal resistance value is a measure of how easily the device can remove the heat its die generates to an external heat sink. Selecting a device with the lowest possible thermal resistance will yield lower die temperatures and failure rates. A low thermal resistance also provides for better pulse tilt performance. The breakdown voltages quantify what level of voltage the device will fail at, the larger this value the more a particular device will tolerate load mismatches. Device manufacturers specify transistors to handle severe load VSWRs, and they may in fact be able to withstand load VSWRs of 10:1; however, sometimes a severe load VSWR may precipitate oscillations which in turn can damage the part. The threshold voltages show a range of where the particular device begins to draw current based on a gate bias voltage. This voltage and its variation as a function of temperature will play a key role in the design of the bias thermal tracking network. The input and output impedance of the RF transistor is characterized by large signal impedance parameters. This is usually presented on the data sheet as complex series equivalent impedance that is plotted on a Smith Chart. The lower the input and output impedances are the more difficult it becomes to match it to 50 . The lower the Q of the impedances the better, as devices with a low Q lend themselves more readily

6.4 RFPA system level design overview

249

Figure 6.4 Generic circuit architecture for a thermally compensated bias network.

to broadband operation. These impedance levels provide a good starting point when determining input and output transformation ratios. Transfer function plots provide a good visual indication of how a device performs over a specific dynamic range of output power levels in terms of gain, efficiency and distortion. Scattering or “S”-parameters and “X” Parameters when provided, will enable computer aided simulations. CAD simulations are an invaluable tool to optimize input/output matching, broadband gain and efficiency. Input, reverse transfer and output capacitances are parasitic capacitances that exist within the semiconductor device. These capacitance values are dynamic (i.e., they vary with DC supply voltage and output power level). The lower the capacitance values the better as they will influence a host of parameters including gain, maximum operating frequency, stability and phase linearity.

6.4.3

RF power transistor bias/thermal tracking networks As discussed, there are three broad classes of RF power transistor: r BJTs; r metal oxide semiconductor FETs (vertically and laterally diffused, VDMOS, LDMOS); r gallium devices: arsenide (GaAsFET) and nitride (GaN). All three transistor types require unique bias networks and some form of thermal tracking to help maintain relatively constant quiescent currents while being subjected to varying thermal environments. Without the thermal tracking networks, RF bias currents may tend to drift and move into bias points that yield excessive or unstable gain or undesirable transfer functions. Figure 6.4 shows a simplified block diagram for a thermal tracking network architecture that might bias Bipolar, LDMOS/VDMOS and GaAs/GaN FET transistors. Bipolar

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Practical HF/VHF/UHF RF power amplifier realization

biasing requires a higher current capability than MOSFET devices. Bias networks for FETs, in the simplest form, can be a simple potentiometer. In any case, the bias networks must contain some source of temperature dependent voltage. Thermal tracking (or compensation) is a way to reduce bias current (or voltage) such that the quiescent currents and bias point of the RF transistor remains reasonably constant over temperature. The bias networks for GaAsFET or GaN devices are more elaborate sequenced networks, i.e.; the gate and drain voltages are “sequenced” or turned on/off in a defined order so as not to damage the device. GaAs transistors will draw heavy and perhaps destructive levels of drain current if a drain voltage is applied with zero gate voltage. To safely turn these devices on, the gate voltage needs to be brought negative first, the drain voltage is then applied, and the gate voltage is incrementally raised. The process is reversed to turn the device off. The main roll of the sequencer is to control this process.

6.4.4

RF input/output coupling/decoupling networks The input and output coupling capacitors are chosen to block DC and provide minimum capacitive reactance at the low end of the amplifier’s frequency range. These capacitors must maintain resonance free operation across the amplifier’s operating band. Capacitor manufacturers’ data sheets usually show a typical capacitor series resonance performance curves over a particular frequency range. These curves convey that even chip capacitors will series self-resonate at some frequency. For narrowband applications, the series resonant frequency of a particular chip capacitor will be the best frequency to use the device as a coupling/decoupling capacitor as it exhibits the lowest possible impedance. RF chokes are employed to decouple the RF signal and to feed in the DC operating bias and supply voltages/currents. As in the case of coupling/decoupling capacitors, the RF chokes should also exhibit resonance-free operation where a particular choke exhibits only inductive reactance across the entire band of intended amplifier operation.

6.4.5

Power transistor impedance matching There are a variety of methods to match the impedances of an RF power transistor to 50 . What method to use is determined by the frequency range and required bandwidth. High frequency and very high frequency (HF, 1–30 MHz, VHF 30–300 MHz) RFPAs are best matched with discrete LC networks for narrowband and transmission line transformers for broadband (>1 octave) applications. Ultra-high-frequency (UHF, 300 MHz-1 GHz) RF power transistors are matched with printed micro-strip, transmission line transformers or combinations of the two. For the HF to UHF frequency range, transmission line transformers are by far the most versatile matching technique as they are architecturally identical regardless of where in the frequency spectrum they are applied. The frequency range may be different, however the transformer coaxial impedances and interconnections are the same. How long the coaxial line elements are, and whether or not they are ferrite loaded are the primary differences between a transformer operating at HF or UHF frequency ranges. In addition to extreme bandwidth capability, the transmission line transformer has the

6.4 RFPA system level design overview

251

Figure 6.5 Schematic of an RLC feedback network applied to an enhancement-mode, N-channel

MOSFET.

ability to convert an unbalanced signal to a balanced drive required for commonly available Gemini RF Power transistor packages that are prevalent in this frequency range.

6.4.6

Feedback networks Feedback can be employed to reduce low-frequency gain and help improve the individual amplifier module gain flatness. Figure 6.5 shows the generic circuit architecture for an resistive-inductive-capacitive (RLC) feedback network. The inductor (L) and capacitor (C) are chosen to resonate at the lowest operating frequency of the RFPA. The intent is to have maximum negative feedback where the gain of the transistor is greatest. The capacitor will also block the DC supply voltage from reaching the gates (or bases) of the RF transistors. The value of (R) adjusts the amount of feedback. This represents only one method of RF Feedback, there are other more complex methods (transformer based) that achieve DC isolation by magnetically coupling the feedback signal.

6.4.7

Thermal management While generally not considered part of the RFPAs circuitry, the method by which heat is removed from an RFPA is equally vital. Improper heat removal can lead to degradation of an array of RF performance parameters including linearity, efficiency, gain and stability,

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Practical HF/VHF/UHF RF power amplifier realization

etc. In addition, higher operating die temperature equates to reduced operating lifetime and increased Failure Rates. For most applications, forced air cooling is adequate, in high-altitude airborne applications, liquid cooling is a preferred option as the reduction in air density inhibits the efficacy of forced air. In either case, however, the thermal interface between the RF power transistor and the module base, heat sink or chill plate is critical, so the details of creating a proper transistor flange thermal interface are covered.

6.5

Hypothetical amplifier design example: (20–400 MHz RFPA subsystem module for 1 kW amplifier application in electronic warfarecommunication jamming) To help illustrate and better convey a typical RFPA module realization, a hypothetical amplifier design example is presented. The process will involve: r r r r r r r

6.5.1

hypothetical application example overview; RFPA qualitative specification delineation; RFPA specification quantification; RFPA module hardware design; RFPA module physical construction; test setup; test results.

Hypothetical application example overview RF Power amplifiers that are used for electronic warfare (EW) communication jamming applications must have very broad bandwidth capability such that they have the ability to jam various communication bands. Frequencies in the range of 20–200 MHz are popular for land/mobile communications and military aviation bands heavily populate 225– 400 MHz. It is beneficial to have one amplifier cover both bands so the design goal is to span 20–400 MHz. The amplifier will be used to selectively inhibit communications; its output will be connected to a broadband antenna, so the load VSWR will deviate far from a perfect match.

6.5.2

Amplifier qualitative specification delineation The following is a list of specifications that are critical to broadband jamming applications. This is a cursory initial attempt, only field trials and beta testing will reveal if certain parameters are more essential than others. 1. High power: the RFPA must have enough output capability to overpower receivers and block enemy signal transmissions. 2. Broad bandwidth: the RFPA must have adequate operating frequency range to cover a variety of communication bands.

6.5 Hypothetical amplifier design example

253

3. High gain: the amplifier must have enough gain such that it can be driven to full power output by a small signal level input. 4. Flat frequency response: the amplifier should perform uniformly at all frequencies within the desired range. 5. Load VSWR tolerant: since the RFPA will be used to jam point to point communications at various frequencies; it will more than likely have to drive antennas that present less than ideal load VSWRs which may go as high as 5:1. The amplifier must be able to drive into these loads without damage. 6. Stability, spectral load pull: as the RFPA must not be damaged by driving adverse load VSWRs, it also should not oscillate at unacceptably high power levels under these conditions as well. 7. Linear: although high gain linearity is not usually critical, certain jamming situations will require the RFPA’s output levels to be precisely controlled. 8. Temperature range/stability: the amplifier will be most likely used in adverse field environments where high temperatures are common. The amplifier will be expected to provide acceptable performance in these temperature extremes. 9. Altitude: the amplifier may be in an avionics platform if it is expected to jam airborne communications, in this case, forced air cooling will not be an option, liquid cooling and chill plates are preferable. 10. Shock/vibration: most military amplifiers are deployed in mobile transport environments. Ability to withstand severe shock and continuous vibration is essential. 11. Radiated emissions and susceptibility: while the RFPA is intended to render specific enemy communication equipment ineffective, it must not interfere with or have its own operation impaired by other colocated equipment. The RFPA must then be adequately shielded for EMI. 12. Mean time to failure: the amplifier, above all, must be reliable, lives will depend on it. To ensure this, the transistor silicon (or die) temperature must be kept as low as possible.

6.5.3

Amplifier specification quantification With a generic list of required specifications, the next step is to assign quantities to each line item. Since the focus here is on HF/VHF/UHF RFPAs, the specifications that directly address the power amplifier module will be covered quantitatively. (Note: for ease of illustration, quantities will be loosely assigned and may not represent actual system requirements, which in many cases, is classified information). r r r r r r

system power output: 1 kW, continuous wave, minimum; bandwidth: 20–400 MHz, minimum; gain: +60 dB, nominal; gain flatness: + / −3 dB, maximum; antenna load VSWR: <5.0:1, maximum; stability, spectral load pull< −45 dBc up to 5.0:1 load VSWR, maximum;

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Practical HF/VHF/UHF RF power amplifier realization

Figure 6.6 System block and wiring diagram for 20–400 MHz, 1 KW RFPA system.

r gain linearity (AM to AM distortion): + / −1.5 dB over 20 dB dynamic range, maximum; r phase linearity (AM to PM distortion): + / −10 ◦ C over 20 dB dynamic range, maximum; r temperature range: −10 to +50 ◦ C; r altitude: 40,000 feet AMSL, maximum; r shock/vibration: 10 G rms, six axis, maximum; r radiated emissions and susceptibility: Mil-Std-461E; r mean time to failure: >100,000 h, minimum, calculated.

6.5.4

Amplifier hardware design/realization The requirement has now been defined quantitatively. The process to start the physical realization begins with the System Block and Wire diagram as shown in Figure 6.6. The simplified diagram shows all the stages in the RFPA system. While there do exist RF transistors that can deliver 1 kW of CW output power, the challenge becomes heat removal and AC coupling of the RF signal. If an RF device puts out 1 kW of RF power at, for example, 50% efficiency, then 1 kW of heat will need to be dissipated. Add in bad load VSWR and the dissipation will worsen. In addition to heat dissipation, the RF current that will be present at the low-impedance output of a 1 kW transistor will tax even the highest quality chip capacitor. It will be a more reliable approach to use multiple RF power transistors. One of the benefits of a system level block and wiring diagram is it shows the insertion gain, loss and RF power levels as power propagates through the amplifier

6.5 Hypothetical amplifier design example

255

stages. It displays just how much power is lost through directional couplers, RF dividers and combiners. The loss values shown in the block and wire diagram are from actual couplers and hybrid combiners. Note that for an amplifier to produce 1 kW of linear load power into a 5:1 VSWR it actually needs to be capable of driving 2788 W of power into a 50  load. After adding losses for the coupler and combiners, the total required RF transistor die power is about 4172 W. Choosing a binary multiple port combiner with 32 ports, then 4172 W divided by 32 yields about 130 W. We now have an approximate maximum RF transistor output power. The next phase is RF device selection where the selection guidelines are for an RF power transistor capable of 20–400 MHz operational bandwidth at a power level of at least 130 W of linear power. The system block and wire diagram is broken down further in Figure 6.7 to a block diagram of the basic RFPA module.

6.6.5

RF transistor selection Current popular output power ranges for RF transistors are 100, 150, and 300 W of output power. Since we need approximately 130 W of CW output power, the focus is on the 150 W range of CW RF power transistors that are designed for operation up to 400 MHz. An overview of classes of transistors was first considered. Since the frequency of operation was only to 400 MHz, GaAs and GaN devices were ruled out. They will work far in excess of 400 MHz; the added cost for this unneeded capability is not economically justifiable. BJTs were not selected due lower gain and most importantly, a limited amount of device manufacturers. Few manufacturers mean a low probability of obtaining a “second source” (i.e., an alternate manufacturer with an equivalent part that will replace the primary device in terms of form, fit and function) of BJT transistors. It sounds innocuous, but not having a second source of a replacement RF transistor is a very difficult situation to be in. You simply do not want to one day find yourself in this particular fix and here’s how this might happen: 1. RF transistor semiconductor wafer fabrication processes are fickle, although they are tightly controlled, in the end they are run by humans. At any point in time a particular device process control can vary yielding devices that may work on a substandard level and can render an RFPA with slim design margins in violation of specification. 2. RF transistor device manufacturers have, can and someday may either discontinue, de-rate or sell a particular line of transistors to another manufacturer. If either of these situations occur, a once profitable RFPA design can overnight devolve into a “lab queen” (an amplifier that can only meet specification by copious amounts of tuning, requiring days or weeks in the test lab) or, even worse, cause a “stop production” mode where shipments have ceased leaving the RFPA engineer (yes, this would be you) frantically searching for an alternative part.

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Practical HF/VHF/UHF RF power amplifier realization

Figure 6.7 Multilevel breakdown of an RFPA module to component level.

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D1020UK Vgs vs Temp 5.6 5.4

Vgs for Ids = 2 amps

5.2 5 4.8 4 8 4.6 4.4 4.2 4

Flange Temperature°C

Figure 6.8 2 A Idq bias point of the D1020UK versus temperature.

This leaves the MOSFET class of devices. For this particular application, either vertical or lateral MOSFETs will work equally well. The selection process now descends to segregating parts that work across the 20–400 MHZ band at a minimum of 150 W of linear CW power with a manufacturer recommended application for communications in the HF/VHF and UHF band and a load tolerance at least up to 5:1 VSWR. Several devices were considered, their data sheets compared and RFPA stages were constructed and actual test data compared. The Semelab D1020UK was selected based on its ability to satisfy the design criteria. The data sheet for this device is in Figure 6.3.

6.5.6

Gate bias/temperature tracking/compensation network The gate voltage versus temperature plot of the D1020UK is shown in Figure 6.8. This was obtained by biasing the device to 2A quiescent and varying the gate voltage for a constant Idq as the ambient temperature was varied from −50 to +150 ◦ C. Note the gate voltage level to sustain 2A quiescent drops approximately 4.4 mVDC/◦ C. In other words, if the gate bias voltage is held constant over increasing temperature, by virtue of the fact that the 2A bias voltage point is continuously lowering with increasing temperature, then the fixed gate bias voltage migrates by default into higher and higher drain currents. This makes the gain and operating class point of the FET dependent on temperature. To mitigate this issue, an open loop thermally tracked bias voltage can be deployed. This is accomplished by mounting a temperature sensing IC mechanically adjacent to the device that is to be compensated. Ideally, it is desired to have the bias voltage dropped by the equivalent amount that the 2 A gate bias voltage point drops. What is nice about the bias voltage variation of the D1020UK is that it is approximately linear. This makes it easy to correct as temperature sensors that have linear outputs (in mV/◦ C) are readily available.

Practical HF/VHF/UHF RF power amplifier realization

Vtemp 0.1

Figure 6.9 Operational amplifier based thermal tracking circuit for the D1020UK.

D1020UK Quiescent Bias Current vs Temperature 3 2.5 D1020UK IDQ (Amps) mps)

258

2 1.5 Uncompensated

1

Compensated

0.5 0 -10

0

10 20 30 Ambient Temperature (Degrees Celsius)

40

50

Figure 6.10 Comparison of the quiescent currents of D1020UK without (dashed trace) and with (solid trace) a thermally tracked bias voltage.

All that needs to be done is to adjust the transfer function slope of the temperature sensor such that it has the inverse slope of the gate voltage. The gate bias/temperature compensation network for the amplifier is shown in Figure 6.9. It consists of a simple precision variable voltage divider ( −5 VDC) network that is summed together with a temperature dependent voltage (Vtemp) that is mechanically linked to the RF transistor to lower its bias voltage as the device heats up. The part chosen for the temperature sensor is the Analog Device TMP35 which has a scale factor of about 10 mVDC/◦ C. The 5 K  resistor and 10 K potentiometer adjust this scale down to 4.4 mVDC/◦ C and then it is summed into the precision variable −5 VDC reference. This is an open loop compensation network and helps the D1020UK maintain a more temperature stable bias current. Figure 6.10 shows the drain current versus temperature with and without thermal tracking. Without thermal tracking the Drain current varies

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1.1 A over the −10 to +50 ◦ C temperature range. Adding the thermal tracking network reduces this by over 80% to 0.2 A of drain current variation. While this is considered good performance, it is important to note that this is open loop correction and the temperature compensation accuracy can vary from lot code to lot code and also on the same device due to memory effects. Thermal compensation networks can be designed with greater accuracy if they take into account the behavioral modeling of a particular class of device.

6.5.7

Input/output RF/DC coupling/decoupling networks A coupling/decoupling network is merely another name for capacitors and coils in an RFPA. Coupling networks are usually capacitors that pass the RF power signal from one device to another while blocking DC voltages and currents. Decoupling capacitors are used to bypass RF signals to ground. Inductors in coupling networks perform the duality function, that is they will pass DC voltages and currents while suppressing RF signals. In a broadband RFPA, the values selected for these components are solved for at the extremes of the operating band edges. These networks will be based relative to the large signal input and output impedances of the D1020UK. The coupling/decoupling components generally have to meet three criteria: r satisfy a minimum reactance(impedance) requirement at the lower frequency limit; r handle high DC and RF currents, voltages, and power; r sustain resonance-free operation beyond the RFPA upper frequency limit. By viewing the three requirements, one need only solve for a component value at the lower band edge. The remaining criteria are assessed by manufacturer’s data sheets and component verification testing on a vector network analyzer (VNA). The values for the coupling and decoupling inductors and capacitors are solved for in the next section as it will be required to see what impedance matching network is required first.

6.5.8

Input/output impedance matching networks There is a multitude of ways to match the input and output impedances of an RF power transistor. If one looks at the characteristics of the input and output impedance of the D1020UK, it becomes apparent (at least for a broadband amplifier application), that it will be difficult, if not impossible, to provide an exact, complex conjugate match for the device at all frequencies and input drive/output power levels to be expected to be used. A balance has to be struck between where to choose to match a particular device. On the input, the device should be matched at the point in the frequency range where its gain is lowest (the highest frequency it will operate at). The output is matched at the highest level of expected RF output power. To match impedances over multiple octaves in the HF/VHF/UHF band, the transmission line transformer is the most effective method. In addition, it converts an

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Practical HF/VHF/UHF RF power amplifier realization

unbalanced signal to a balanced drive required for Gemini packaged transistors such as the D1020UK. The transformer, while able to transform impedances over wide frequency ranges, only does a fixed transformation ratio. RF power transistor terminal impedances will vary, so a transformer will transform impedances of a transistor effectively over a limited frequency range and output power level. Outside of these areas, input VSWR, gain, and efficiency will suffer. Starting with the input matching network, the input terminal impedance of the D1020UK is extracted from its Smith chart on the device data sheet. The gate to gate series equivalent input impedance at 400 MHz is 0.4-j2.3 . Converting this to a parallel equivalent impedance yields a real portion of 13.62  from gate to gate. Dividing 50  by 13.62 equates to 3.67:1. The nearest realizable balanced drive transformation ratio is 4:1. A rough estimate of output impedance from drain to ground is given by the equation: Ro =

2 Vdd 2Po

(6.1)

The transistor will be operated at 28 VDC and at approximately 75 W of power per side. This estimates approximately 5.23  from drain to ground. The push–pull configuration of the Gemini package doubles this to 10.45 . We can also extract a close value also from the Smith chart drain to drain series equivalent impedance as was done for the input. The series equivalent value is 0.9-j3  at 400 MHz. Converting to the parallel equivalent yields a real portion of 10.84 . Dividing 50  by 10.45 equates to 4.78:1. Again, the nearest realizable ratio with a balanced drive capability is 4:1. The term “realizable ratio” means a value of transformation ratio that can be physically constructed with a finite number of transmission lines. For a particular transformation ratio to be physically realized, the square root of the transformation ratio must be a rational number. If it is not, an infinite number of transmission lines would be required to realize the ratio, an obvious impracticality. For both the input and output transformations, an approximate 4:1 ratio is required. Invoking a topological network synthesis procedure [1] for transmission line transformers, the first step is to satisfy the necessary and sufficient conditions for finite coaxial element equal delay transmission line transformers: √ N = Rational Number (6.2) where N = required transformation ratio. The square root of 4 is 2, a rational quantity. The necessary and sufficient realizability condition is satisfied. The synthesis procedure can now begin with the reasonable expectation of a physically realizable network. The first step is to determine the number of coaxial lines in the first subgraph: √ (6.3) n 1 = 4 = 2, where n1 is the truncation of the square root of the transformation ratio N, and in this case is the number 2.

261

6.5 Hypothetical amplifier design example

Zo

Z in

Z out Zo

Figure 6.11 Subgraph result of a topological synthesis of a 4:1 transmission line transformer.

Z in

Zo Zo

Z out

Zo

Figure 6.12 Completed unbalanced to balanced drive 4:1 transformer network.

The synthesis procedure will terminate if: √ N1 = √ N − n 1 = 0 N1 = 4 − 2 = 0

(6.4)

The process terminates and two coaxial lines are inserted into subgraph 1 as shown in Figure 6.11. The characteristic impedance, Z0 , of the coaxial lines is solved for by:  (6.5) Z 0 = Rs Rl where Rs and Rl are the source and load resistances terminating the transformer, respectively. These values are 50 and 12.5  and solve for a characteristic impedance of 25 . The synthesis procedure provides a transformer architecture that is applicable to unbalanced to unbalanced loads. The D1020K in a push–pull configuration demands a balanced drive network. Therefore the transformer of Figure 6.11 needs to be converted to a true balanced network (one that would present an electromagnetically balanced distributed network) by interchanging the shield and center conductors of the lower transmission line element. The transformer configuration now provides a balanced to balanced drive. A 1:1 balun transformer is added at the high impedance port to provide the unbalanced to balanced drive conversion such that the input to the transformer can be reached by ground referenced coaxial or micro strip feeds. The final 4:1 unbalanced to balanced transmission line transformer architecture is realized and shown in Figure 6.12. The synthesized 4:1 architecture is a “boiler plate” circuit structure, that is, in this format it is an engineering construct that can conceivably work in broad frequency spans

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Practical HF/VHF/UHF RF power amplifier realization

Figure 6.13 Simplified parasitic model of 4:1 transformer network.

anywhere from 10 kHz to well over 1 GHz. That’s comforting, but the RFPA specification only requires 20–400 MHz. The transformer architecture needs some massaging to get it to have a “sweet spot” of 20–400 MHz. By “sweet spot” it is desired to have the transformer’s absolute values of insertion loss minimized and return loss maximized from 20–400 MHz. In the world of engineering constructs, the physical transmission line transformer is an ideal transformer nested in a plethora of parasitic reactances. These reactances will limit the usable frequency range. The reactances that limit the lower and upper frequency range of the transmission line are primarily inductive in nature. The low-frequency range is limited by shunt inductance, the high end is limited by parasitic series inductance, and these are shown schematically in Figure 6.13. Parasitic distributed gradient capacitive reactances will resonate with line inductances and may cause in-band insertion loss “suck-outs,” a narrow band of frequencies within the pass band where the insertion loss spikes to very high values and then returns to low values. Additional losses in the transformer are from ferrite cores, coaxial line dielectric, copper conductors as well as radiation losses. After realizing the 4:1 architecture, the next step is ferrite loading the coaxial line elements in order to suppress even mode (nontransmission line) currents and create a net mutually coupled inductance that is in far excess of the impedance to be transformed so that its parallel loading effect is immaterial. As shown, a physical transmission line transformer is a complex model, an ideal transformer, mutually coupled inductors, parasitic reactances, and transmission lines. An equivalent circuit of the mutually coupled inductors is shown in Figure 6.14. There are essentially four inductors in the 4:1 transformer section, two in each coaxial transmission line. For all intents and purposes, inside the coaxial lines, the coefficient of coupling is

6.5 Hypothetical amplifier design example

i

263

i L1

L1

L3 M12/21

L2

M34/43

L3

L2 L4

L4

Figure 6.14 Mutually coupled inductances of a 4:1 transmission line transformer.

considered bi-directionally unity, that is, all the flux generated by the center conductor of the coaxial line is linked to the outer shield and vice versa. The 4:1 is open circuited to help visualize the mutually coupled inductors with a common-mode current, i, flowing through all four inductors. The net value of this inductive reactance should be at least 5–10 times the value of impedance of 50  so it does not adversely load down the very impedances the transformer is trying to step up. The path for finding the total inductance starts with: vi = L 1

di di di di di di di di + M12 + L 3 + M34 + L 2 + M21 + L 4 + M43 dt dt dt dt dt dt dt dt

(6.6)

where Mx y = k



Lx L y

(6.7)

and k=1 Lx = L y

(6.8)

L 1 = L 2 = L 3 = L 4 = M12 = M21 = M34 = M43 L t = 8L SW

(6.9)

So

What the above equations state is that due to the 4:1 transformer configuration of four mutual, bi directionally unity coupling coefficient inductors, to solve for the net shunt inductance, simply multiply the inductance of what will result from winding an inductor of a single wire on a given ferrite (Lsw ) by eight. We would like to have the shunt inductance to be >5–10 times greater than 50  so as not to load it down. We also must keep the length of the 25  coaxial lines as short as possible so as not to incur in-band resonances in the response of the 4:1 transformer. We therefore start out with keeping the number of turns through a ferrite core to a minimum of two turns.

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Practical HF/VHF/UHF RF power amplifier realization

Figure 6.15 Measured results of mutually coupled inductances of a 4:1 transformer.

Solving for the required inductance factor at 20 MHz: Xl ∼ = ωl ∼ = + j500 ∼ = ω8n 2 Al

(6.10)

where n = number of turns through the ferrite core = 2. Note that the above equation is laced with “approximately equal to” (∼ =) signs instead of “equal to” (=). The reason is that the inductance factor tolerance of ferrite toroids is about + / −25% at best, so there is little point in trying to solve this equation precisely as any inductor or transformer you might construct using ferrites will vary wildly in value. It has been factored in ahead of time to have the shunt inductance of the transformer to be 5–10 times 50 , so if you land in this region, the transformers low-end response will be acceptable. The equation was nevertheless solved and an approximate inductance factor of 124 nh/n2 was calculated. A ferrite core from ceramic magnetics (Part 6.T503125T-C2050) was chosen as its measured inductance factor is 100 nh/n2 . The transformer is constructed with 25  coaxial lines with two turns through each ferrite toroid core. The transformer was evaluated on a VNA with the low-impedance side of the transformer loaded by an open circuit. This will measure the parallel inductance. The plot in Figure 6.15 shows the results with the value of inductive reactance at an adequate level of 4.3 μH which yields a parallel inductive reactance of + j540 , more than enough so as not to impair the low-frequency return loss response. The transformer can

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Figure 6.16 Input return loss of the 4:1 input transformer with 6.25  chip resistor terminations on the low-impedance port.

then be terminated with 6.25  chip resistors to evaluate how the device transforms the resistances to 50 . The graph of the transformer’s input return loss is shown in Figure 6.16. It yields an average of −21.6 dB of return loss. The plot of the transformer’s input Insertion Loss is shown in Figure 6.17, (note the values on the data need to be divided by two as the plot is of the transformer’s return loss with an open circuit load, hence the insertion loss is half). There is a small resonance at 383.62 MHz, these can occur in ultra-broadband transformers, the best way to mitigate them is to shorten the length of the coaxial lines. Typically, the transformer will also have series inductive reactance that will impair the high-frequency range. This can be tuned in with compensation capacitors. Although these can be calculated, it is fairly quick to optimize a transformer by substituting different values of shunt capacitance during test procedures and selecting the value that yields the best broadband return loss. Since both the input and output ports of the amplifier demand a 4:1 transformer, the same device architecture will be used both ports. The output transformer uses larger cross-sectional area ferrites and larger diameter coaxial cable to accommodate the higher power levels. With the impedance matching transformers solved for, it is now a fairly simple task to go back to solve for the coupling capacitors. We know the capacitance value must present a low reactance at 20 MHz. The coupling capacitors are to be inserted at the

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Practical HF/VHF/UHF RF power amplifier realization

Figure 6.17 Low-impedance open port return loss of 4:1 transformer (to obtain insertion loss, divide plotted values by 2).

50  point between the 4:1 and 1:1 transmission line transformers. It is desired to have the reactance at least 1/100th of 50  or less than –j0.5  at 20 MHz. Solving for C: 1 = 0.0159 μF (6.11) ω.0.5 The maximum amount of average current that the series coupling capacitor will see occurs at 150 W CW, therefore √ √ Pmax .z 150.50 vrms Imax = = = = 1.73 A (rms) (6.12) z z 50 Based on the three criteria set earlier we have two of them solved for, the minimum value of capacitance and the maximum average current with a 50  load. To be conservative, the maximum current will be doubled to account for driving adverse load VSWRs. The D1020UK is a + 28 VDC device, so the DC operating voltage must be in excess of this value. The chip capacitor selected is a 0.1 μF, 50 WVDC 200B series capacitor manufactured by ATC. The capacitor can handle over 9 A of average RF current so it will be suitable not only for the output coupling capacitors but the input as well. The remaining issue is to verify the capacitor, on its own, will maintain a lowimpedance, resonance-free, operation throughout the entire amplifier bandwidth. This C≥

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Figure 6.18 Impedance of 0.1 μF chip capacitor from 20–400 MHz.

is verified by doing a one-port impedance analysis using a VNA. Figure 6.18 shows the response of the coupling capacitor across the 20–400 MHz bandwidth.

6.5.9

Feedback network Manual calculation of the feedback resistance value can be very roughly determined by the following equation [2]: (V2 + V3 ) R f =  V1 −V2   V2  − R4 − R2 R1 where: Rf = feedback resistance in ; V1 = voltage gate to gate at 400 MHz = 9.7 V rms; V2 = voltage gate to gate at 20 MHz = 2.17 V rms; V3 = voltage drain to drain on D1020UK at 150 W output = 43.3 V rms; R1 = R2 = impedance on output of input matching transformer = 12.5 ; R4 = output load, drain to drain = 12.5 .

(6.13)

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Practical HF/VHF/UHF RF power amplifier realization

This equation only provides a rough estimation of feedback resistance value. In a broadband amplifier, intentional negative feedback can swing positive if not carefully modeled. In this particular case, the equation yielded a value of 52.5 . At some levels of drive the amplifier went into oscillation, so the value was increased to 100  and the amplifier became stable. With this level of feedback the gain at 20 MHz was reduced by approximately 8.3 dB. The small signal gain plots are given in Section 6.5.12.

6.5.10

Test setup configuration/analysis Prior to the discussion of the example RFPA’s construction and electrical test results, some effort will be devoted to what is required to verify the amplifier is specification compliant on a modular level. It is prudent to verify compliance at a modular level for the obvious reason that if you can’t meet specification there, in certain parameters, it is unlikely performance will improve at a system level. Knowing how to test an RFPA is every bit as essential as knowing how to design one. How accurately the test results are acquired will ultimately advise the RFPA engineer of how much design margin does/doesn’t exist. The tests must be performed only on test equipment that is within its calibration cycle and has National Institute of Standards and Technology (NIST) traceability. This is to insure that whatever test results you obtain will ultimately agree with your customer’s data. Even though the module is fairly small and may cost only a few thousand dollars to fabricate, to fully analyze and test for this particular requirement will require several million dollars in test equipment. Decisions will need to be made along the way whether or not to purchase, rent, lease or use a test facility’s equipment. The key piece of test equipment is the VNA. This unit has the ability to measure input return loss, transformer insertion loss, small/large signal gain, gain flatness, and insertion gain/phase linearity. The spectrum analyzer in conjunction with the paralleled loads and binary stepped transmission line will monitor the modules spurious response while being subjected to various load VSWRs. The binary stepped transmission line [3] is simply lengths of coaxial cable cut to specific lengths and switched in line with 2, 3, 4, and 5:1 load VSWRs such that impedances along constant load VSWR circles can be applied to the output of the RFPA module. This leads back to an earlier discussion in this chapter on the topic of unconditional stability. This is the very test that is performed to assess load pull stability. It becomes apparent that it is impossible to present a circuit at the output of an RFPA that can emulate all impedance points bounded by constant load VSWR circles on the Smith Chart. Figure 6.19 is a block diagram that illustrates the interconnection of a typical test setup that will verify a substantial portion of the module’s performance. The output of the VNA is fed to a low-level test driver to increase the power to the point where it is sufficient to drive the RFPA to full power. The precise output power level of the RFPA is sampled with a calibrated directional coupler and fed to an RF Power meter. For gain, gain flatness, and insertion gain/phase linearity, the VNA has the ability to calibrate out the response variations of the low-level driver. The VNA can characterize a majority of the amplifier’s frequency and power domain responses. In addition, when the RFPA is

6.5 Hypothetical amplifier design example

269

Figure 6.19 Typical RFPA module/system test configuration.

subjected to temperature, altitude and vibration analysis, the very same test setup can be deployed with the initial response transfer functions stored in memory and compared as temperature and vibration levels are increased. While the setup in Figure 6.19 can cover a majority of the required tests, to execute radiated and conducted emissions tests will require the sophisticated setup in Figure 6.20. These are highly elaborate systems, the center of which are 3 and 10 m anechoic chambers which effectively provide a controlled EMC environment in which to test the amplifiers susceptibility to, and emission of, EM radiation. The RFPA is placed in a 3 m chamber and subjected to high-power RF energy emitted from closely placed bi-conical log and double ridge horn antennas. The amplifier is then monitored for its ability to maintain specified operation without degradation of performance while the frequency and field strength of the radiated RF energy is varied over very broad ranges. For radiated emissions, the amplifier is placed on a turntable within the semi anechoic 10 m chamber; it is then rotated while transmitting full RF power output. Highly sensitive, Bi-conical, Log periodic and Active Loop antennas are located about 20 feet away and will be elevated and lowered based on the EMI/EMC specifications. The signal received by the antennas is plotted on a graph with limit lines that show if the amplifier is emitting RF energy beyond acceptable amounts. Radiated emissions is one of the few requirements of the RFPA specification that if the amplifier is not compliant at a module level, it remains possible to be compliant at a system level since the amplifier will be mounted within a metal chassis that will allow for further shielding and reduction of emissions.

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Practical HF/VHF/UHF RF power amplifier realization

Figure 6.20 Simplified block diagram of 3 and 10 m EMC test chambers.

A highly accelerated life test (HALT) chamber is shown in Figure 6.21. This has the unique ability to apply random vibration to the RFPA module in six axes (X, Y, Z, yaw, pitch, and roll). This is more effective than a single or dual axis vibration table as it can effectively impart vibration energy to the module that is close in line with what it will encounter in the field. In addition, the HALT chamber has the ability to change temperature from −100 to +200 ◦ C.

6.5 Hypothetical amplifier design example

271

Figure 6.21 HALT chamber.

6.5.11

Physical RFPA module construction A photo of the individual breadboard RFPA stage is shown in Figure 6.22. The printed circuit board with micro strip interconnecting transmission lines is mounted into an aluminum module. There are two PC boards, one for the input divider/matching network and one for the output. The transistor is mounted in a milled-out channel 0.070" deep such that the gate and drain leads sit flush with the PC board. This channel is perhaps the most important machined surface within the entire module, care was taken to specify that it has a surface flatness of better than 5 μm/cm along with an RA (average surface roughness) of better than 1 μm. The device manufacturer has provided this mounting information [4]. With the mating surface ready, a very thin layer of thermal compound was applied to the bottom of the RF transistor’s flange. The compound is applied such that the color of the gold plating on the flange is visible through it. The idea here is that the best thermal interface is metal to metal contact, but since the surfaces of both the transistor and finely machined surface are not perfect, very small air pockets will exist. The role of the thermal compound is therefore not to get in between the module to transistor (metal– metal) contact, but rather to fill the minute air pockets. The final step in mounting the transistor is to use the appropriate screws with the recommended mounting torque. In this particular case, two 4–40 screws were deployed with a torque of 5.0 in.lbs.

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Practical HF/VHF/UHF RF power amplifier realization

Figure 6.22 Breadboard of 20–400 MHz, 150 W CW RFPA module; thermal tracking sensor is located in the front center on the module wall.

The input 1:1transformer consists of two turns of 0.062 inch, sleeved, 50  semi rigid coaxial cable on a 0.5 inch Ceramic Magnetics ferrite toroid part 6.T503125T-C2050. The input 4:1 transformer consists of two turns of 0.062 inch, sleeved, 25  semirigid coaxial cable on two of the same cores. The input coupling capacitors isolate the DC bias voltage on the gates and couple the RF input signal from the 1:1 to the 4:1 transformer. The temperature compensated bias voltage sensor is mounted to the side wall and its output is fed to the gates of the transistor through a 5 K resistor. The resistor values can be this high as the gates of a MOSFET present an extremely high DC impedance. The output 1:4 transformer is constructed with a heavier gauge (0.085 ) sleeved 25 and 50  semirigid coaxial cable. Three turns of 25  coaxial cable are wound through Ceramic Magnetics toroid part 6.T874525T-C2050 for the 4:1 transformer and similarly for the 50  coaxial cable on the output 1:1 transformer. The selection of toroidal transformers helps also to meet EMC requirements as transformers wound on toroids will radiate less RF energy. Although not shown, the RFPA module will be populated with three more identical amplifier stages, the outputs of which will be connected to a four port combiner. With 150 W of output capability per stage, one module will yield about 500 W of output power after combiner losses.

6.5 Hypothetical amplifier design example

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Figure 6.23 Rubberized EMI gasket seated in milled out channel in RFPA module wall top surface.

The module is a machined out enclosure, the side walls have a channel milled out to seat a metallized rubber EMC gasket (Figure 6.23) that will seal the interface to the top cover. This mechanical configuration will provide an effective method of limiting unwanted radiated emissions at a modular level. While there exist many numerical methods to design an RFPA to meet certain electrical specifications such as power output and gain, designing an RFPA to comply with radiated/conducted emissions and susceptibility represents a formidable challenge. This is due to the fact that many of the things that influence the module’s shielding properties are difficult to model. This will tax even the most sophisticated EM simulation programs. There are preventative measures one can take in the design phase of an RFPA: 1. Form all inductive (transformers and chokes) components on toroidal cores if possible. 2. Individually shield each stage with milled out enclosures and covers that seal the gain stage with EMI rubberized gasketing. 3. Use inline filtercons on all DC/signal feeds into and out of the RFPA module where possible. 4. Test each unique RFPA for EMC compliance at a modular level.

6.5.12

RFPA module test results The final RFPA module schematic is shown in Figure 6.24, the transistor is connected to the input–output transformers, bias adjust and thermal tracking networks. The values

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Practical HF/VHF/UHF RF power amplifier realization

Figure 6.24 Complete 20–400 MHz, 150 W CW RFPA module schematic.

of compensation capacitance will change and depart from those that provided the best return loss with chip resistor test terminations and will now be chosen to satisfy the best input match/gain at 400 MHz and best efficiency at 150  uniformly across the band. The two port small signal response of the network is shown in Figure 6.25a, b. Figure 6.25a shows the input match characteristics. The RFPA module stage has high gain at the 20 MHz low-frequency band edge with poor return loss and the inverse at the high end of the band. The RLC feedback networks as shown in Figure 6.5 were used to lower the gain 8.3 dB at the low end of the band and improve the overall gain flatness. Figure 6.25b shows the gain flatness plot with this feedback. The gain flatness is 6.8 dB peak to peak, this can be compensated for on a system level by using a small signal gain equalization network or an ALC loop. The feedback capacitor is chosen primarily as a DC blocking component and the inductance value is chosen so as to resonate at 20 MHz such that the feedback and gain reduction is maximized where the device’s gain is greatest. The gain and phase linearity (AM–AM and AM–PM distortion) response of the amplifier is shown in Figure 6.26a–e. With a bias current of 2A at a Drain voltage of +28 VDC , the linearity response of this device is very good for a broadband class AB biased device. On average the gain linearity is + / −0.74 dB, with a peak deviation of + / −1.05 dB. From the average value vantage point, there is + / − 0.76 dB of gain linearity margin, however the peak gain linearity deviation at 400 MHz is + / −1.05 dB. This leaves + / −0.45 dB of gain linearity margin. In other words, the low-level driver gain and intermediate power amplifier stage gain linearity transfer functions will have to have substantially less gain linearity error if the aggregate response of the entire system (Figure 6.6) is to maintain the specification compliance value of + / −1.5 dB.

6.5 Hypothetical amplifier design example

a)

b)

Figure 6.25 (a, b) Input return loss, and small signal gain of the RFPA module.

275

276

Practical HF/VHF/UHF RF power amplifier realization

a)

b)

Figure 6.26 (a–e) Phase and gain linearity test results over 20 dB dynamic range to 150 W.

6.5 Hypothetical amplifier design example

c)

d)

Figure 6.26 (cont.)

277

278

Practical HF/VHF/UHF RF power amplifier realization

e)

Figure 6.26 (cont.)

The same is true with phase linearity; overall the average phase linearity error is + / −4.4◦ with a peak deviation of + / −7.9◦ at 400 MHz. This leaves + / −2.1◦ of allowable phase linearity error in the front two stages of the RFPA system. This is not leaving much room for these stages to have any non linearity present in their own transfer functions. A possible remedy is optimize the transfer function of the D1020UK at 400 MHz, or move to a higher frequency part that will have improved gain and phase linearity at 400 MHz. Figure 6.27 shows the efficiency of the amplifier from 20–400 MHz. The average efficiency is 56.8% with a worst case value of 42.9%. The device’s data sheet specifies a minimum efficiency of 50%, so between the gain/phase linearity and efficiency, we have a reasonably good indication that the output impedance of the device is well matched. Using the test setup of Figure 6.19, the output of the RFPA module is connected to a binary stepped transmission line, then into 50  high-power loads that are paralleled. First two loads are paralleled for a 2:1 VSWR. The binary stepped transmission line will switch in 50  coaxial cable lengths that will ultimately rotate the impedance in discrete steps about a constant 2:1 VSWR circle. While this is occurring, the RFPA’s frequency and output is incremented from 20–400 MHz and 0–150 W, respectively. The spectrum analyzer is monitoring the frequency spectrum to confirm that there are no

6.5 Hypothetical amplifier design example

279

D1020UK Drain Efficiency vs. Frequency @ Pout =150W CW 80 70

Drain Efficiency(%) ency(%)

60 50 40 30 20 10 0 20

115

210 Frequency (MHz)

305

400

Figure 6.27 Broadband drain efficiency of the 20–400 MHz RFPA module at 150 W CW.

spurious signals that rise above −45 dBc. This process is then repeated for a 3:1 load VSWR, then 4:1, and finally 5:1. The RFPA module did exhibit some spurious oscillations that were −60 dBc down below the carrier level. One might be lulled into a false sense of security that the Spectral load pull stability requirement is met as the spurious outputs that did appear are lower than −45 dBc. This may be the case, but to confirm this continuously over all frequencies, power levels, load impedances, potential modulation formats and temperatures represent countless hours of bench testing, even with automated load pull test setups. Any load pull stability test, no matter how comprehensive, will only be a cursory attempt at best. It may be fair to say the amplifier module has conditional stability within the limits and scope of the available test methods and conditions. Figure 6.28 shows the RFPA module undergoing six axis random vibration and temperature stress. As with other requirements, it is beneficial to evaluate random vibration on a modular level. Random vibration performance is similar to radiated emissions in that an RFPA that meets specification at a modular level will more than likely pass at a system level as the chassis that the module is integrated into will absorb a good portion of the random vibration energy imparted to it. The module was subjected to 15G rms of random, six-axis vibration. This was 50% over the required specification on a system level. RFPA circuitry, by virtue of its nature in terms of construction (i.e., chip capacitors, resistors) readily lend itself to be inherently immune to high levels of mechanical shock. The weak point in the RFPA circuitry is any component that protrudes well off of the PC board with some degree of mass to it. In this particular case, the ferrites loaded onto the transmission line transformers can sometimes impart enough force on the coaxial lines on which they are wound to generate enough torque that may either crack the solder joint

280

Practical HF/VHF/UHF RF power amplifier realization

Figure 6.28 RFPA module undergoing vibration and temperature qualification testing.

or delaminate the metallization of the PC board. Care must be taken to secure these and other devices with similar mechanical properties. While the thermal circuit is usually considered separate from the electrical network, it is every bit as important and has perhaps more direct impact on reliability than anything else. The section on RFPA module construction covered the details in preparing a proper thermal interface between the RF transistor and the module base. The next task is removal of the heat from the module of the entire system. While this is outside the scope of this material, the objective of whatever method of cooling is deployed is simple; the transistors die temperature must be kept as low as possible. Lower die temperature will not only increase MTBF, but lessen the amplifier’s vulnerability to failure from excessive overdrive and load VSWRs. Bear in mind, a 10 ◦ C reduction in die temperature may seem trivial, however, it can approximately halve the failure rate of the transistor. The plot in Figure 6.29 shows typical MTBF of RF power transistors versus die temperature and drain current. Both of these two quantities can be minimized with optimized thermal design, system architecture and output matching networks. Thermal design will cover mechanical interfaces, appropriate selection of chill plates, heat sinks and exchangers. If the heat generated by any given architecture yields excessive die temperatures, then adding modules may be an option to spread the heat out amongst more devices. In either of these cases, the output matching networks of the RF transistors must be optimized such that the efficiency is the best it can be.

6.5 Hypothetical amplifier design example

281

Mean Time To Failure

MTF, Mean Time To Failure (Hrs)

10000000

ID = 1 A

1000000

3A 100000

5A

10000

1000 120

140

160

180

200

220

TJ , Junction Temperature (°C)

Figure 6.29 Graph of a typical RF power transistor MTTF versus junction temperature and drain

current.

6.5.13

Beyond the test data The test data on the amplifier looks good and with some CAD based circuit optimization will probably yield better design margin. It is important to note at this time that the test data itself should be used for more than determining whether or not a particular module is meeting specification. Data in discrete form is no doubt useful, it defines the performance of a particular module, however, RFPA data in comparative trend format is far more powerful. It not only defines the performance of a particular module, but also highlights potential hidden process variations that may be in decline, not only in the manufacture of the RFPA, but also in the component suppliers. The HF/VHF/UHF RF power amplifier market has never seen demands for true commodity commercial volumes of millions of amplifiers. As such, attempts to try to apply statistical control processes such as Six Sigma can end in frustration. There are, however, facets of Six Sigma that lend themselves to lower volume production runs. Short term sigma level (or Zst ) scorecards look at amplifier test data in small lot quantities (say, for example, 25 systems). In this environment, amplifier performance of 25 systems can be statistically compared and areas where the amplifier is running close to specification or experiencing a transient period of either marginal or exceptionally good performance can be easily highlighted and brought to attention. This attention to test data trends along with root cause analysis will uncover both supplier and manufacturer process deviations and flaws.

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Practical HF/VHF/UHF RF power amplifier realization

Another useful process to consider primarily in the testing of RFPAs is gauge repeatability and reproducibility (gauge R&R). The underlying concept behind this is determining or quantifying the variability in a measurement system by measuring the performance of a particular RFPA several times to determine repeatability. Reproducibility is found by having several different RF technicians measuring the RFPA performance in order to quantify the variation in a measurement system resulting from operators. The net result of a gauge R&R study is that it will ultimately provide error tolerances that may require certain amplifier parameters to be more tightly specified in order to circumvent the possibility that even in the event of the presence of manufacturer measurement errors, the system still arrives at the customer within specification. While the above two topics relate to test data and test equipment, the following topics address what the module design should go through next. A manufacturing engineer should assess the module construction with a design for manufacturability (DFM) study to ensure that its construction is amenable to low-cost assembly processes such as semiautomated or fully automated assembly and acceptance test procedures (ATPs). Further along in the design process, quality engineers need to be involved to perform failure mode and effects analysis (to identify RFPA design and process problems before they occur). Wiebull analysis along with calculated and demonstrated MTBFs will provide insight into the expected lifetime of the newly minted RFPA design.

Summary/conclusions: current technology/future trends in amplifier design It has been said here that two things primarily occur in any RF power amplifier: r efficient amplification; r efficient or maximum power transfer. One must amplify a signal, transfer it to the next stage, then do it all over again. The devices responsible for amplification are obviously transistors. So if we wanted to know what may happen in the future, we can extrapolate what has occurred in the past. Twenty-five years ago, the class of RF transistors most common were BJTs. MOSFETS were starting to become commercially available. Since then, MOSFETs (whether vertical or lateral) have been the workhorses of HF/VHF/UHF RF power amplifiers. BJTs for now, appear to be in decline. In the 1985–90 timeframe, MOSFETS that could operate up to 175 MHz at power levels of 300–600 W became available. In the last year, 50 V LDMOS FETs have arrived that can deliver 1 KW up to 500 MHz. What was true then is still true now, namely operating such high-power devices presents the same challenges of heat removal and the AC coupling of high-power, high-current RF signals. GaN and GaAsFET devices continue to find themselves in amplifiers that are breaking barriers in ultra broad bandwidths. It is apparent that a continuing trend in RF power transistor technology can be expected with higher and higher power outputs and broader bandwidths found in smaller or equivalent sized packages. No one, however, has found a way to produce a device

References

283

that is distortion free or has significantly improved efficiency performance; all devices discussed have varying degrees of non linear transfer functions and inefficiencies. This is not to say a device of this nature will never arrive, only that in over a half century of transistor development, it simply has not. On the topic of matching and maximum power transfer, suffice it to say, if the computer industry progressed with the same speed, we would all still be using abacuses. A quick review on one of the earliest papers on transmission line transformers by Guanella [5] and Ruthroff [6] show that they remain virtually unchanged in construction and application since the 1940s. It is a testimony to what elegant and efficient devices they are, and also to how difficult they are to improve upon. So if we match transistors the same way and if they really are not more linear or much less efficient, then where are the improvements to come from? Based on advances in the cellular and plasma processing amplifier markets, improvement on raw amplifier performance has, can and will come in the form of advanced amplifier error correction techniques such as predistortion, feed-forward and high-speed, digitally based ALC loops. These advances evolve primarily from advances in higher speed analog to digital conversion, digital signal processing and error correction.

Dedication I would like to dedicate this chapter to my wife, Catherine Leigh, son Justin Daniel, and daughter Mikaela Sienna Myer.

Acknowledgments The author would like to acknowledge the contributions of Robert Schoepfer, Gregory Muller, and Thuy Lu.

References 1. D. Myer, “Synthesis of equal delay transmission line transformer networks,” Microw. J., vol. 35, no. 3, pp. 106–114, March 1992. 2. N. Dye and H. Granberg, Radio Frequency Transistors-Principles and Practical Applications, Butterworth-Heinemann, 1993, pp. 193–197. 3. R. K. Blocksome, “A binary stepped transmission line,” R.F. Des., July/August 1982, pp. 22–29. 4. N. Padfield, “Mounting guidelines for SEMELAB RF MOSFETs” Semelab PLC Application Note, pp. 1–9. 5. G. Guanella “New method of impedance matching in radio-frequency circuits,” Brown Boveri Rev., Sept. 1944, pp. 327–329. 6. C. L. Ruthroff, “Some broad-band transformers,” Proc. IRE, vol. 47, pp. 1337–1342, Aug. 1959.

7

Microwave hybrid amplifier realization Dominic FitzPatrick PoweRFul Microwave

7.1

Introduction The variety of approaches taken in the design of power amplifiers is vast and the subdividing of the approaches into various categories, such as “hybrid” is (like the term microwave itself) a generalization in which the edges are somewhat blurred. The Cambridge Advanced Dictionary defines hybrid as something “that has been produced from two different types . . . especially to get better characteristics, or anything that is a mixture of two very different things.” In this case the mixture is considered to be of lumped and distributed components. Until recently a hybrid amplifier was considered as one which used packaged devices, however in striving to achieve better performance at higher frequencies discrete devices and MMICs have been integrated into circuits containing both distributed circuits and discrete components, see Figure 7.1. Hybrid amplifiers have thus been created as an effort to “cherry pick” the best technical solutions within an economic framework. The place of hybrid amplifiers in the market ranges from the prototype and feasibility proving stages of product development, to volume manufacturing, to low-quantity highest performance products. Microwave hybrid power amplifiers (MHPAs) are used in low-volume applications such high-energy physics particle accelerators to volume applications in mobile phone base stations. Solid state powers amplifiers (SSPAs) have become the technology of choice for the mobile communications market and a significant proportion of the satellite communications market. The advent of wide bandgap materials has seen huge improvements in bandwidth performance below 6 GHz, and the next generation of commercial products will see these advances cover X band and beyond. Many electrical engineering students undertake an amplifier design project as part of their studies, while large engineering companies have found amplifier design groups expensive and difficult to manage (often leading to very successful “spin-out” companies!). Some managers have struggled to understand why the design and development of MHPAs is not as predictable a process as the design of other electronic system components. This chapter seeks to highlight some of the pitfalls that have so troubled some design programmes; it will also hopefully help designers in selecting the optimum approach to meeting customer requirements. Too often the term “black art” has been applied to what is in effect a process which is poorly controlled, and this starts right at the very basic level of the design . . . .

7.2 Printed circuit boards

285

Figure 7.1 Mixed technology microwave hybrid power amplifier. Photo courtesy of Cree Inc.

1–2.3 GHz SiC 50 W Amplifier, www.cree.com.

7.2

Printed circuit boards It might seem strange to start a chapter on MHPAs with a discussion on printed circuit boards (PCBs). However, as with house building, this is the foundation of our structure and a poor choice here will lead to the final design solution being compromised. Microwave PCBs are divided into two categories, hard and soft substrates. Hard substrates are primarily alumina, a ceramic with a tightly controlled dielectric constant (εr ≈ 9.8) although other materials such as glass and sapphire are used. Alumina substrates benefit from high thermal conductivity and high operating temperatures which has made them popular in military and space applications. The patterning of the conductive circuits is achieved either by deposition (thick film) or etching (thin film). Resistors can be integrated into the circuits by adjusting the metalization (such as using a nickelchromium layer). Grounding is an issue as the material is brittle and holes either need to be punched when the material is in its “green,” unbaked form or laser drilled. Similarly, the mounting or attachment of the substrate can cause problems due to poor thermal coefficient of expansion mismatch with some of the common metal housing materials, see Figure 7.2. New electrically conductive adhesives have been developed which allow a sufficient amount of “give” between the layers, however this is neither a cheap material nor is the dispensing and curing easy. Metal alloys with a closer thermal expansion have been developed as will be discussed later. Soft substrate is the term applied to a now vast range of products that are composite materials, either fibre or particle based. The all-pervading FR4 fibre glass material of the conventional electronics industry is inappropriate for MHPAs as the dielectric constant is poorly controlled and the dielectric losses high. At the other end of the spectrum is pure polytetrafluoroethylene (PTFE), a synthetic fluoropolymer which has a low dielectric constant, which can be tightly controlled, with low loss. However, it has poor thermal performance. By mixing PTFE with fibre based boards then low loss, controlled dielectric constant, and a reasonable thermal performance can be achieved. Additionally, profiling and drilling the boards is cheap and relatively simple. By adding ceramic particles the

Microwave hybrid amplifier realization

500 450 Silver Copper

400 Thermal Conductivity (W/m°C)

286

350 Gold

300 250

Aluminium

200 Tungsten

150

Molybdenum

100 50

Alumina

Solder (PbSn) Teflon

Kovar

0 0

GaAs

10

20

30 40 50 60 70 Thermal Coefficient of Expansion × 106/°C

80

90

100

Figure 7.2 Thermal properties of common microwave materials.

dielectric constant can be adjusted, even to the extent that they can be close to that of alumina, thus offering circuits of similar dimensions. A further advantage of these substrates is that they are easily laminated, so a wide range of thicknesses are available, and they can be provided with a range of metal backings. Processing is similar to that of conventional circuit boards except that with PTFE based materials an additional stage to “roughen up” the surfaces is necessary in order to successfully plate to the surface. As the demand for circuits for the mobile phone industry rose then so the number of PCB processors who could handle PTFE substrates increased and prices fell. The key parameters of substrates commonly used in hybrid amplifiers are shown in Table 7.1. Not included in the table is cost, this is because when considering the cost of a circuit substrate one should not only consider the purchase price of the raw material but also the processing costs. For example, a circuit on a low dielectric maybe three times larger than on a high dielectric. Furthermore, the finished PCB cost needs to be put into the context of the whole amplifier itself. What is the cost/W of output power? Knowing this figure of merit will aid the decision in choosing an output PCB; is it more cost effective to opt for an expensive low-loss board or a cheaper higher loss material? Non-PTFE materials have been developed so that standard PCB fabrication techniques can be employed. A side benefit of this development has been that the step change in dielectric constant, εr , at around room temperature has been removed. The typical change in εr due to the crystalline structure altering in a PTFE material can be seen in Figure 7.3. This change causes equally sharp changes in the equivalent electrical length of transmission lines. Some materials (such as ceramic loaded PTFE), while not displaying as significant an inflection point, have a much greater overall change in εr

287

7.2 Printed circuit boards

Table 7.1 Properties of common substrates used in MHPAs

Property Dielectric constant Thermal coefficient of dielectric constant Dielectric loss (tan ) Dielectric strength Volume resistivity Thermal conductivity Coefficient of thermal expansion Water absorption (ASTM-373) Type

Soft

Units

Hard Alumina1 99.6%

RT/duroid 5880

RT/duroid TMM10i

RT/duroid R4003C

ppm/◦ C

9.9 −

2.2 −125

9.8 −43

3.55 +40

0.0001 8.7 1014 26.6 8.2

%

0

0.0009 285 2 × 1013 0.20 X = 31 Y = 48 Z = 237 0.015

0.002

AC-kV/mm -cm W/m/K ppm/◦ C

2 × 108 0.76 X = 16 Y = 16 Z = 20 0.16

0.0027 31.2 1.7 × 1016 0.64 X = 11 Y = 14 Z = 46 0.06

Ceramic loaded thermoset plastic

Woven glass, ceramic filled thermoset

Substrates

Ceramic

PTFE/ microfibre

Er(T)Er(25)

Chart 1: RO4000 Series Materials Dielectric Constant vs. Temperature 1.008 1.006 1.004 1.002 1.000 0.998 0.996 0.994 0.992 0.990 0.988 –50

–30

–10

10

30

50

70

90

110

130

150

Temp°C RO4003

RO4350

PTFE/Woven Glass

Figure 7.3 Relative change in dielectric constant with temperature. Courtesy of Rogers Corp.

www.rogerscorp.com.

with temperature. Another advantage of thermoset materials is that they do not soften when heated and thus are more suitable for wire bonding applications. In the ideal world we would want the substrate to be a totally homogeneous material where the dielectric constant is isotropic, i.e., has a consistent value throughout. Due to the manufacturing processes and material compositions this does not happen and the 1

CoorsTek, ADS-996.

288

Microwave hybrid amplifier realization

dielectric constant may even vary with orientation of board, thus if the circuit layout and the substrate orientation is not consistent between manufacturing runs there may be variations in performance. It is obviously essential that board manufacturers are aware of these differences and take account accordingly. The effects of these dielectric constant changes are most dramatic in high “Q” elements such as resonators. Thus, isotropy of the substrate material is an important consideration in the design of narrow-band amplifiers. It can also affect wide-band designs where coupling structures are produced on the PCB, such as Lange couplers [1]. Generally speaking, the finer and more randomly placed the loading materials in substrate the lower will be the variation in dielectric constant, thus woven glass based materials tend to exhibit the highest anisotropy. Very consistent dielectric materials such as pure PTFE can be used; however these have their own problems. The thermal conductivity of the PCB is important in medium power amplifiers where surface mount devices are used, although even in these cases the majority of the heat generated is conducted to the heatsink through the grounding vias. In high-power amplifiers the power devices are bolted through the PCB to the housing floor or directly to a heatsink. The amount of power dissipated in the circuit structures themselves should not be underestimated. If a power device delivers 100 W and the output circuit following it has 0.5 dB of loss this means that 11 W is dissipated in the PCB (assuming the majority of the loss is not radiated). There are two main methods of loss in the PCB, resistive loss in the metal conductors and dielectric loss in the substrate. The conductor loss is determined by the properties and dimensions of the metal used while the substrate loss is dependant not only on the loss of the material itself (quantified by tan δ) but by the percentage of the electric fields flowing through the substrate. These two have a tendency to work against each other; to get the lowest substrate loss one would look to use as thin a substrate as possible and narrower lines, while for minimizing conductor loss one needs wider lines. The thickness of a transmission line, particularly in MHPAs, is affected by two considerations, the DC current and the frequency of operation. For DC currents the cross-sectional area of the transmission line is inversely proportional to the resistance, i.e., double the cross-sectional area, halve the resistance. At microwave frequencies however, the currents are flowing only in a limited proportion of the thickness, the extent of which is referred to as the “skin depth.” This term leads to a common misconception, the current flows in the electrical surface closest to the ground plane (the electrical fields are between the surface of the ground plane and the underside of the transmission line), thus plating up or changing the metalization of the top surface conductor may make no difference. The formula for skin depth, δ, (in metres) is:  δ=

2ρ 2π f μo μr

(7.1)

where ρ is the bulk resistivity of the conductor (-cm); f is the frequency (Hz); μo is the permeability constant (H/m) = 4π × 10−7 , and μr is the relative permeability.

7.2 Printed circuit boards

289

Table 7.2 Bulk resistivity of commonly used metals Material

Aluminum Copper Chromium Gold Nickel Palladium Silver

Bulk Resistivity 2.65 (μ-cm)

1.67

18.0

2.30 8.71

10.8

1.59

Table 7.2 lists the bulk resistivities of some common materials. For example, at 5 GHz the skin depth in a copper conductor will be 0.92 μm, while a 1/2 oz. copper plated PCB has a copper thickness of 18 μm. A common rule of thumb is that the copper PCB trace should be at least 5δ to minimize loss. Also note that the purpose of gold plating or flashing on microwave PCBs is to passivate the surface or improve the contact of bonding areas, not to reduce the RF resistivity. As the RF current flow is primarily on the underside of the track the surface roughness of the substrate will impact the loss. The most common conductor material is copper. There are two standard approaches to attaching the copper to the substrate material. The lowest cost and hence most common method is electrodeposited or ED copper. The alternative is rolled copper, where thin sheets of copper are bonded to the substrate material. Rolled copper has lower insertion loss due to the uniformity of the material and the reduced surface roughness; this is particularly noticeable as frequency increases. However, ED has a better adhesion to the substrate, i.e., higher peel strength. Traditionally, both types are specified in ounces, this comes from the number of ounces of copper per square foot of board area, (1 oz. ≈ 0.0355 mm). Copper cannot be left bare and so it is common practice to either plate or coat the copper. Such treatments range from “flashing” with a nonreactive metal such as gold (typically 5 μm), to hot air solder leveling (HASL), and conductive polymers. When selecting the substrate material the most significant consideration is the impedance range that can be realized. The general rule of microwave design, “Watch out when dimensions approach a significant fraction of a wavelength” applies here. If the substrate thickness is too large then instead of the electromagnetic (EM) fields forming in the quasi-TEM mode, other modes propagate. A good rule of thumb is that the thickness of the substrate should not exceed 20◦ phase length at the highest operating frequency. Table 7.3 summarizes the impedances, circuit dimensions, and current limitations for a range of substrate materials. Other considerations in the selection of the dielectric and its thickness are the current capacity required (usually limited by DC bias currents), and the size of discrete components, such as device tabs. In linear design software models there are limitations on the ratio of track width to substrate thickness, which usually restrict the minimum impedance to ∼25 . Therefore it may be necessary to use an EM analysis for parts of the circuit where wide lines are unavoidable. When deciding whether a hard substrate is the optimum solution it is important to consider the surface area of the circuit. Generally, hard substrates are limited to a maximum size of 50 × 50 mm. Hence, a circuit may need to be made from a number of ceramic “tiles.” Conversely, antennas have been made on soft substrates over 1 meter long. Typically, however, blank soft substrates sizes range from 250 × 250 mm to 800 × 600 mm.

290

Microwave hybrid amplifier realization

Table 7.3 Typical substrate trace dimensions with approximate current rating

Substrate

εr

Thickness (mm)

50  width (mm)

Alumina (Thin-film) (Thick-film) CuClad 217LX RO4350B TMMi 10

9.8

0.635

0.61

λ/4 (90◦ ) @ 10 GHz (mm) 2.87

2.17

0.787

2.40

5.46

3.66 9.8

0.508 0.508

1.09 0.48

4.41 2.90

Current for a 30 ◦ C temp. rise2 (A) 12 12 5 3.8 2.3

Figure 7.4 Impact of processing on track dimensions and edge coupling (slopes exaggerated).

In the design of microwave circuits it is easy to assume that the circuit dimensions produced by the CAD software are those that will be fabricated; however it is essential to understand the processing that will be involved in manufacturing the PCBs and to take into account the impacts. For example, where the production process involves etching away the unwanted copper the actual shape of the cross-section of the track is trapezoidal, and the size of the etch angle is proportional to the thickness of the track, see Figure 7.4. There are two main PCB conductor creation approaches, (a) subtractive, and (b) additive. In the subtractive process the etch angle results in the track width being wider at the bottom (remember that this is what determines the RF impedance), while in the additive process the track is plated up from a thin layer and thus is wider at the top. Also worthy of note is that the edge coupling between the adjacent tracks (and ground planes) is 2

Approximate as this depends on a number of factors including peripheral circuit features, trace termination, backing material and fixing method (see later).

7.2 Printed circuit boards

291

assumed in most simulator models to be between vertical walls (or whatever the etching process was of the sample from which the models were derived). A further complication is that some PCB manufacturers take into account the etch factor of their process, while others don’t, hence the designer must know whether or not to take this into account when creating the mask. Grounding is an important part of microwave circuit designs. Typically, the ground plane is a continuous conductor on the reverse side of the substrate, so it is necessary to connect to it. The standard approach is to drill the substrate material and then plate the hole with a conductor (plated through hole – PTH) to create a via. With many RF substrate materials this has its own problems. PTFE materials are difficult to bond to and hence the surface of the hole must be roughened to promote adhesion of the copper during the plating process, and this is particularly difficult to achieve in through-holes. Also, due to the differing thermal coefficients of expansion between the conductor and the substrate, cracking around the top of the via can result, particularly where the PCB undergoes significant temperature cycling. These factors therefore push the designer to use larger holes and thicker plating. Rather than using via holes, slots may be cut in the board and their edges plated, but this may be a nonstandard approach for some PCB manufacturers, who would normally do slot cutting after plating and should therefore be highlighted in the requirement drawings. Inserting pins through boards is acceptable for simple prototype circuits, but the result is generally not flush with the substrate surfaces and thus may necessitate profiling of the box floor or restrict the placement of components. Substrates can be supplied metalized on the back side which makes it possible to directly solder the substrate to the metal; however this will require using background heating. When using aluminum backing it is necessary to plate the aluminum first (not a trivial process), hence copper or brass backing are preferred. Electrically conductive adhesives are also available and can be used to bond the metal and substrate together. For large bonding areas the adhesive can be supplied in films which may be more convenient. The use of metal backed substrates is popular for a number of reasons: r r r r r

it provides good heat sinking; edge mounted connectors can be directly attached; good mechanical base for mounting large components; shrinkage and warping of the PCB is reduced; easier attachment to housings.

However, weight, substrate, and processing costs are increased. Metal backed materials are particularly popular for test jigs and prototypes where the expense of a custom housing can be avoided and weight is not a significant issue. Mounting PCBs within housings or directly to heat sinks can be done simply using screws to clamp the board in place. However, care should be taken to ensure that the contact between the board and the backing material is consistent by the use of appropriate screw head size and quantity dependent upon the “stiffness” of the substrate. Areas where particular care should be taken are around the input and output connections and where pockets are machined out for the devices. Gaps between the ground plane on the back of the substrate and the box floor may produce resonant cavities which will alter the response

292

Microwave hybrid amplifier realization

of the amplifier. They can also provide feedback paths leading to oscillations. Screws should have metal lands under them, especially with PTFE boards as under compression the PTFE has a tendency to “creep” away from under the screw. It is advisable to use cap heads to avoid damage from screwdrivers slipping, especially where there are fine tracks, or delicate air-wound inductors. Crinkle or spring washers are usually adequate to lock the screws. The standard size is sometimes larger than the screw head, so where space is at a premium the next size down or an imperial size will fit the body of the screw and not protrude far beyond the screw head. Direct screw clamping is not recommended for hard substrate materials such as alumina due to the brittleness of the material. Most commonly the substrate is soldered or epoxied directly onto a metal carrier which in turn is screwed into the housing. Alternatively, spring clips can be used to hold the tiles in place. Modern epoxies have proved increasingly popular in mounting both substrates and active devices. The type of epoxy used must be considered carefully, some can crack under thermal stress. For such applications thermo-plastic adhesives which have some “give” are a better solution. Conventional PCBs may also be soldered directly into housings. This gives excellent thermal and electrical conductivity with the added advantage that no board “real estate” is taken up by the mounting screws. In order to get an even solder join, solder paste is screen printed onto the underside of the PCB or a preform used. Pressure needs to be applied across the PCB during reflow to prevent areas from lifting and, if not constrained by walls, to keep the PCB correctly aligned. Attention must be paid to the temperature distribution across the unit as all parts of the solder joint must reach the reflow point, but without going so high as to damage the substrate, housing plating or degrade the solder. A low-flux solder should be used, particularly when large boards are involved, otherwise pockets of flux may form under the board. Some solder pastes may require a drying period after application to the PCB to allow solvents to dissipate. An alternative configuration to microstrip is to use coplanar waveguide (CPW). In this construction method the ground plane is brought to the top surface, this produces a circuit with very tightly contained fields which is therefore less susceptible to proximity effects such as lids and to radiative coupling. Although popular for low-power devices it has draw backs for MHPAs, due to the need to heatsink devices. With flange mounted devices there is a discontinuity in the odd and even modes at the device package junction, and for surface mount there needs to be a ground plane connected to with vias. Typically the substrate requires a large number of vias to ensure ground continuity, hence losing one of the advantages of CPW. Another major drawback is that tuning of line impedances in CPW is very difficult compared with microstrip. It is often necessary to have slots in the PCB material for flange mounted components. Rather than being directly attached to the PCB these are bolted to the housing floor with leads soldered to the substrate tracks. For microwave devices the alignment of the PCB and housing is critical so that gaps are minimal as they can cause unwanted impedance changes and resonances, as shown in Figure 7.5. As the same requirements are imposed on the input and output connector launches the dimensional tolerances on the housing and PCB can be extremely tight. One solution, particularly suitable to PCBs soldered into housings or test fixtures, is to machine the slots into the PCB and housing simultaneously. This ensures precise alignment between the two. Unfortunately, this

293

7.3 Housing

RF Link

W, width of microstrip

L

W

Substrate H

Metal Backing

X

Housing Z

Z

H

S s Z = 377 × — w X = Z tan

2πH λ

L = Inductance of RF Link (e.g. bondwire or device tab) Note: H is in metres

Figure 7.5 Ground path effects.

option is not possible with hard substrates, and with soft substrates held in place a much higher degree of clamping is required, and care must be taken to ensure “swarf ” is not forced into the gaps between board and ground plane. A final consideration with soft substrates is their moisture absorption. During processing and cleaning, PCBs are subjected to a large number of chemicals. These can cause a variety of problems, from producing corrosive liquids to changing the electrical properties of the substrate. For instance, the dielectric constant can alter and if the circuit is tuned to compensate for this, then over time as the substrate “dries out” the εr will change and hence, the circuit performance changes. Thorough cleaning followed by a baking out stage is necessary.

7.3

Housing Other than for prototypes and test jigs MHPAs require housing. Although this may at first seem trivial, before considering the construction of a suitable housing the requirements should be considered. r interference: to stop the signals in the amplifier interfering with and being interfered by external signals, circuits and materials; r protection: to prevent the circuits being harmed by mechanical or chemical action; r heat sinking: the heat generated by the power components needs to be removed in a controlled manner. The housing can either incorporate or provide the connection to the method of heat removal; r mounting and connecting: the amplifier does not exist in isolation; it requires signal connections, supply connections and a method of fixing to its surroundings. The role of the housing is to ensure that these are reliable and convenient.

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Microwave hybrid amplifier realization

The relative importance of each of these must be balanced against the other considerations of cost and weight. The same approach would not be taken in a safety-critical application in a harsh environmental to a laboratory test amplifier. As in all elements of design, the end solution is a compromise between conflicting needs.

7.3.1

Materials The most common material for MHPA housings is aluminum. It is relatively cheap, easily machined, strong and light weight. It has good electrical and thermal conductivity and so is excellent for screening and heat sinking. The main drawback is that it cannot be directly soldered to. This can be overcome through plating, but this is a multistage process with typically first a nickel seed layer followed by the gold or tin plating. It is rare that the aluminum is left untreated as although the oxide layer that forms on the surface is fairly un-reactive, there is a danger that small residues of acidic solutions will be left behind from the flux used in many solders. These can react with the aluminum oxide to form salts which can cause dendrites to grow leading to short circuits. A lowcost aluminum surface treatment is chromate conversion, commonly known by the brand names Iridite or Alodine. Some forms of this process are banned under the Restriction of Hazardous Substances (RoHS) legislations as they contain toxic hexavalent chromium. Care should also be taken as the electrical conductivity can be inconsistent and dependent upon thickness. The coating cannot be soldered to. For high-performance hermetically sealed systems Kovar is used as an alternative to aluminum as will be discussed later. Kovar’s thermal coefficient of expansion (TCE) is closer to that of GaAs, see Figure 7.2; however, it is three times denser and its thermal conductivity is considerably lower than aluminum which is an obvious drawback for MHPAs. Aluminum alloy 6061 is preferred due to its good mechanical properties and machinability. Where the lid is to be welded to the unit (rather than clamped) then aluminum alloy 4047 is preferred. This contains silicon which improves the ductility of the weld and reduces cracking.

7.3.2

Sealing and hermeticity Very few things are as likely to illicit impassioned debate amongst MHPA design engineers as the issue of the appropriate level of sealing. When one looks into the area in depth, one can easily be lead to despair that there is nothing that can be done to prevent moisture ingress. However, we should take heart from the fact that systems continue to operate for many years, and in fact the ruggedness and survivability of some relatively cheap products such as mobile phones, satellite low-noise down-converters (LNBs), and GPS receivers is impressive. The aim should be to provide reliability commensurate with the cost of the unit (including cost of replacement). In fact many military systems providers are now looking at availability of parts rather than requirements to survive storage of 20 years in harsh conditions. Protection of amplifier circuits is required not only from mechanical damage but also from corrosion and vapour ingress. In the fabrication of amplifiers there are a large number of chemicals used, from the lubricant used during machining of the housing, to

7.3 Housing

295

those used in the PCB processing and housing plating, to the fluxes in solders. These, especially in the presence of water, can form particularly corrosive solutions. Condensation can cause short circuits or changes to performance in RF applications by changing the electric fields around transmission lines. Avionic systems have proved particularly vulnerable to condensation, where equipment can be sitting in warm moist air, and within only a few minutes be at high altitude and low temperatures. The temperature at which condensation forms is called the Dew Point and varies with the humidity of the air; as the air temperature increases so does its ability to “hold” water. The extent of the protection required is dependent upon the expected lifetime of the product, temperature range (higher temperatures increase chemical activity – hence storage temperature is a key factor), and sensitivity of the circuits to corrosion, which in turn depends upon the materials used and how the active circuits are packaged. Standards were established for military systems covering many areas of the design and testing of electrical systems. MIL-M-38510, the general specification for microcircuits, required that all hybrid microcircuits that contain active semiconductors should be hermetically sealed. The MIL standards are no longer supported, mainly because they could not keep pace with the speed of component and process developments, but many of their requirements have been assumed into requirement specifications. Recent work [2] has shown that hermetic sealing to MIL-STD 883 may not be adequate and that modern plastic packaging can provide better reliability. A big fear in the early days, particularly of GaAs circuits, was “hydrogen poisoning” and so hydrogen “getters” were incorporated into circuit packages. Improved passivation of the active devices has resulted in the virtual elimination of this issue. A complete seal against moisture ingress is difficult if not impossible to achieve. Welding, brazing, or soldering all of the joints can produce an adequate seal; however there is the need to provide RF and DC interfaces and access to the unit for repair and maintenance. Moisture can ingress into a housing in three ways: r diffusion; r capillary action; r breathing. Diffusion: water vapour will diffuse in if the partial pressure differential is inwards even if there is an absolute pressure differential in the opposite direction. Hence, a condition can exist where a filler gas in the housing (such as nitrogen) can be diffusing outwards while the water vapour is diffusing inwards. It is often not realized that water vapour molecules are smaller than the other main gases in the atmosphere – oxygen and nitrogen. Water vapour (H2 O) has a molecular weight of 18 as compared to nitrogen (N2 ), 28 and oxygen (O2 ), 32. Thus, the water vapour seal is the hardest to achieve. The measure of diffusion is moisture vapour transmission rate (MVTR) and is dependent upon the relative concentrations on either side of the barrier. Table 7.4 shows the MVTR values for different composition rubber o-ring seals tested under identical conditions. No material provides a 100% seal, the relative gas permittivity of various materials is given in Table 7.5 [3], however the real question should be, when does a leak become critical, which comes back to the intended life and operating and storage conditions.

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Microwave hybrid amplifier realization

Table 7.4 Relative rubber o-ring sealing performance

O-ring material

MVTR (g m−1 day−1 )

Fluorocarbon Nitrile Silicone Polyurethane

9.5 × 10−4 40 × 10−4 90 × 10−4 130 × 10−4

Table 7.5 Relative gas permittivity for various materials

Nylon

Silicones

Epoxies

LCPs

Glasses/ ceramics

Metals

1

10−2

10−4

10−6

10−8

10−10

Capillary action: water may form on the outside of the unit from direct exposure or condensation, depending upon the environment. The rate at which the water permeates the unit will depend upon the nature of the material in which any hole or crack exists. Obvious risk areas are along the lid edge and any screw holes that break through into the chamber. Breathing: for unsealed units the majority of the water ingress will be through breathing. As the pressure changes between the inside and outside of the unit there will be a movement of air. Thus, moisture will be contained within the unit. A degree of protection to components and tracks can be offered by conformal coatings, however these can affect the RF impedance of circuits, there is also the problem of when to apply them. Application before tuning may mean that the coating integrity will be breached if it is necessary to change components during tuning and test, however adding the coating afterwards runs the risk of altering the circuit performance in an uncontrolled manner. Also, although a conformal coating protects from short circuits, condensation above the protective layer can still detune the matching circuits. The ultimate solution is to hermetically seal the amplifier. The argument against hermetically sealing is that if harmful chemicals build up over time then by allowing the unit to “breathe” the concentration is reduced, whereas in a sealed chamber it may reach harmful levels and cause corrosion. The main problem is due to water moisture, thus not only is it necessary to seal the amplifier but also to reduce the moisture content within the unit (obviously cleaning so as to remove as much of the contaminants as possible is essential), therefore air is driven out before sealing and replaced with an inert gas such as nitrogen. The decision to hermetically seal should not be taken lightly as this requires special components such as the RF and DC connectors as well as the lid seal itself, and with each one there is not only a high-integrity seal to produce but another potential failure point. Of course if it is decided that the unit requires to be sealed then an additional test stage needs to be incorporated to prove the integrity of the seal.

7.3 Housing

297

Studies have shown [2] that the required level of hermetic sealing for high reliability is 5 × 10−11 mbar l/s. However, standard leak testers struggle to meet these levels so often specifications have actually been set lower at about 10−8 mbar l/s. Hermetic joints must be metal; epoxies and gaskets do not offer sufficient sealing, hence solder or welded joints are used. The standard approach to hermetic sealing is for the lid of the housing to be laser welded or soldered to the walls. Specialist advice should be sought for laser sealing as to the dimensions of the lid and housing as these are critical to producing a good seal and related to the laser power. Of course this process must be carried out after tuning and testing, and if there is a subsequent failure then the lid must be machined off to allow for repair/retuning. For RF and DC connections, hermetic feed-throughs are usually made from a Kovar (an iron nickel cobalt alloy) outer ring and center pin with a glass body. The TCE of Kovar is close to that of glass and the Kovar can be plated so that it can then be soldered in place. For RF connections the ratio of the diameter of the center pin to the outer barrel must be such as to present a 50  impedance. It is obvious from the reliability of modern electrical components such as mobile phones and LNBs that it is not necessary to provide a hermetic seal to achieve reasonable reliability. Improvements have been made in the passivation layers on the surface of active semiconductors and in the construction of the device packages themselves. However, system specifications tend to be conservative and a degree of environmental screening is often required. An alternative approach, where full hermetic sealing is not required, but where protection from harsh environments is necessary, is to use a compression gasket around the lid. Sometimes environmental and electrical screening cannot be achieved to the degree required in a single gasket so two separate ones used. There is a large variety of gaskets including solid and hollow tubes to flat custom forms. They can be complete rings, spooled line or moulded in place. The benefits of this approach are that the unit can be opened at any time making tuning and repair simpler (especially important in power amplifiers!), also no specialist equipment such as a welding system is required. Some of the key considerations are shown in Figure 7.6. To ensure that the correct amount of compression occurs the dimensions of the trough are critical. Typically, the gasket is compressed 25–30% hence the dimension d in Figure 7.6b should be such that this is achieved, similarly w should be determined such at that at the correct compression the gasket is not restricted horizontally. Where the gasket is not recessed (e.g., flat gaskets) it is advisable to include protrusions in the machined face which ensure the correct amount of compression is achieved, but not overdone. A disadvantage of the gasket sealing approach is that the wall width required to fit the gasket and fixing screw is greater than without, which can lead to space issues. With appropriate cutting tools the material under the gasket can be removed as shown in Figure 7.6d, however this results in more difficult assembly, hence it may not be an option for volume applications. The lowest cost form of the gasket material is provided on a spool and can be laid in the recess, which can include intricate routing. Fixing screws need to always be outside of the sealing ring, or where this is not possible (for example, in center posts) include their own gaskets. When joining up the ends of the gasket it is better that the two ends overlap rather than form a butt joint as shown in Figure 7.6e

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Microwave hybrid amplifier realization

Lid d w Housing Wall

Conductive Gasket

(a) Before compression.

(b) After compression.

Fixing hole separation

(c) Housing gasket detail and mounting screws.

(d) Under cutting the gasket recess.

(e) Joining Gasket ends, butt join (left) and angled join (right) -preferred.

Figure 7.6 Housing sealing using compression gaskets.

and manufacturers can supply suitable adhesives to join the ends. An example of this type of seal can be seen in Figure 7.7. Although not a MHPA, this is an example of a hybrid microwave assembly that is mounted externally and subject to a north European climate and must be highly reliable. The housing is made from cast aluminum with a chromate passivation. The RF circuits are electrically sealed by an internal lid which includes compartments. The environmental seal is provided by a compression gasket and a layer of silicon rubber. RF screening is provided by an interference fit between the internal lid and PCB. The unit is designed to be mounted at an angle so that if there is any condensation within the unit it will drain to the lower right hand corner away from the active circuits.

7.3 Housing

299

Figure 7.7 Gasket sealed satellite down converter (LNB), manufactured by Grundig Ltd.

[1] Pinned through board connection, [2] waveguide to microstrip interface, [3] Die cast main housing with gasket recess, [4] Foam RAM for mode suppression, [5] internal lid with cavity walls and connecting “mouse-holes.”

One consideration specific to MHPAs is that the unwanted by-product which we seek to minimize – heat – actually works to our advantage. Although the danger of short circuits exists at switch on, especially after storage in cold conditions, the operating temperature of most MHPAs will keep the air in the unit above the dew point and so condensation is less likely.

7.3.3

Construction The construction of MHPAs can vary from the simple to the very intricate. The basic model is a cavity into which the RF and DC circuits are all fitted, as shown in Figure 7.8. For larger amplifiers it is often preferred to separate the DC circuits into another chamber. This may be so that bias adjustment can be carried out with the lid in place for the RF unit, for electrical isolation, for testing and monitoring, or because the sealing method of the DC components is different to that of the RF. It can also reduce the lengths of feed connections which are areas of danger for interference and oscillation. The variety

300

Microwave hybrid amplifier realization

Figure 7.8 Simple construction, wideband hybrid amplifier module, before and after lid sealing and painting. Courtesy of Labtech Microwave Ltd. www.labtech.ltd.uk.

of configurations for amplifier modules is enormous; Figure 7.9 describes some of the more common approaches. a. “H” section: this is simple to construct and has the benefit that the RF and DC cavities can be sealed independently. The feed locations of DC and monitoring points to the RF PCB can be positioned where needed, with complicated routing being kept in the DC compartment. The drawback with regard to MHPAs is that the heat sinking for power devices is poor. Floor thickness can be increased under the power devices; however this still gives a higher thermal resistance due to the thermal path length than other options. b. Orthogonal Cavities: Similar benefits to the “H” section, but with longer wire links to the RF PCB. The depth of the cavity of the RF section is related to the minimum height of the DC PCB, which could cause issues with box modes. It does offer the ability to have the power devices mounted on a face which can be attached onto a heat sink or cold wall. c. “Wrap around”: a good solution where there are power components in the DC section that also require heat sinking. The long RF section would typically be split into a number of chambers using internal dividing walls as shown in Figure 7.10.

7.3 Housing

301

RF PCB DC PCB Feed through

(a)

Coaxial Connector

(b)

Link cable

(c)

(d)

Lid

Heatsink/Base (e) Figure 7.9 Typical amplifier housing formats: (a) cross-section of “H” section module;

(b) cross-section of orthogonal cavity module; (c) “wrap-around” module; (d) split section module; (e) planar module.

d. Split section: this format, although requiring additional RF connectors and a cable, has the benefit of giving interstage access which can be useful in tuning and fault finding. e. Planar: one of the problems with the previous module formats is that the circuits are within cavities and this can cause production issues with assembly and test due to

302

Microwave hybrid amplifier realization

Figure 7.10 (a) X band and (b) S Band MHPA modules: (a) wrap-around construction showing bias control with RF chambers around the perimeter. Note the weight reduction removal of excess material where possible; (b) side-by-side construction. Photos courtesy of Surrey Satellite Technology Ltd. www.sstl.co.uk.

access. A solution to this problem has been to incorporate the sidewalls into the lid. The RF and DC circuits may then be incorporated into a single PCB. The circuit design must have a low susceptibility to ground proximity effects; otherwise the fitting of the lid will detune the performance. The construction allows power devices to be mounted directly to the heatsink thus maximizing thermal transfer. Another

7.3 Housing

303

Figure 7.11 Handling internal corners.

issue with this design is that the RF connections need to come vertically through the board which can give rise to difficulty linking to them and launching unwanted modes (see later). It is possible to mount connections in line with the PCB; however the junction with the lid requires close attention. The housings themselves may be formed by three main methods: direct machining, casting, and piece parts. Improvements to the performance and speed of computer numerically controlled (CNC) machining centers has dramatically reduced the cost and increased the possible intricacy of housings. Designs should be discussed with the machinist before finalizing, as there are a number of simple aspects that will reduce cost and improve manufacturability. These include: 1. Use as large a cutter as possible for the internal cavities, where possible avoid tight corners. If necessary a corner can be opened up using a drill hole, see Figure 7.11. 2. Holes that require tapping are best drilled through to stop taps from jamming. Use as large a hole and thread size as possible. The minimum tap depth is 1.5 × diameter of the fixing. Blind holes can be a store for the chemicals and substances used in processing; it is much easier to completely clean through holes3 . 3. Reduce as far as possible the number of cutting axes required, this will speed up machining and reduce cost. 4. Countersinking holes is an additional operation, only countersink where necessary. 5. Minimize the number of different cutters and drills required. Making amplifier housings from cast parts is limited to volume requirements, and for MHPAs the parts will still require some machining to produce the necessary surface finishes for mounting power devices. Complex shapes can be created and this has lead to this being a popular option for base station amplifiers. 3

This caused a problem with flange mounted transistors failing over time. Removing the blown devices revealed a very thin layer of sticky ‘goo’ under the devices. Assembly technicians were reminded of the need for scrupulous cleaning under the devices and an inspection stage was introduced prior to device fitting. Still the transistors failed. Eventually, running a cotton bud down the transistor mounting holes revealed the source of the ‘goo.” As the devices were being clamped down, dissolved flux was forced up the holes and spread under the device flange, increasing the thermal resistance. In this case the RF PCBs were soldered into the box and then cleaned in an ultrasonic surfactant cleaner, leaving residue in the blind holes.

304

Microwave hybrid amplifier realization

The third option of using piece parts covers a number of different applications ranging from low-cost custom assemblies to high-cost light weight units for the avionics industry. In the first case simple box extrusions are used for the side walls which can be bolted to heatsinks or lids. The second case utilizes a process called aluminum dip brazing. This can produce assemblies with very thin walls (<1 mm) thus lightweight, but also with integrated features such as air and water cooling sections that are sandwiches of corrugated and sheet aluminum through which water or air can be forced, see Figure 7.13e, and bosses for screw fixings. The parts are cut out and assembled using tabs and slots with aluminum silicate pastes administered along the joints. The whole assembly is immersed in a bath of molten salt which solders the joints. In this way a pressure-tight seal can be formed. Such a process is expensive and the number of manufacturers limited, but where weight is at an absolute premium this can be the best solution. Where screws are used to compress the lid, the number and spacing will depend upon whether the required screening is primarily electrical or environmental. For environmental screening the number of screws is dependent upon the stiffness of the lid (∝ to thickness) and the gasket material. When there is a pressure seal it is necessary for the lid and walls to be thick enough (or stiffened using webbing) so that they don’t buckle under pressure. The extent of electrical continuity is dependent upon the operating frequency of the amplifier. If the length of any electrical “gap” exceeds λ/8 (in air) at any operating frequency the slot so formed can create a radiating element from which signals can escape or leak into the amplifier. It should also be remembered that it is not necessarily the maximum operating frequency of the amplifier itself that should be considered but that of the devices inside. An important side note is screw locking. In many mechanical applications epoxies are applied to the screw holes to prevent screws coming loose. This can be an absolute disaster for microwave applications as the screw lock is nonconductive and can effectively insulate the screw from the housing. Appropriate locking methods including epoxy painting (this can be a useful additional protection especially against chemicals which could attack rubber seals) and, where height allows, using pan head screws with spring washers. An important consideration in the design of microwave amplifier housings is the resonant frequency(s) of the cavities. A fully enclosed metal box will have a resonant frequency dependent on its dimensions [4]. The presence of a dielectric material (the PCB) on one face will affect this frequency and the tracks on the PCB will couple with the cavity. This can not only cause oscillations but also unpredicted disturbances to the amplifier gain. As a rough guide, when the width of the cavity approaches λ/2 the cavity will become resonant. Thus, cavities should be made small enough that they will not support any modes within the operating band, however this is not always practical. The fields can be broken up by the judicious use of pillars within the cavity to short out the resonances, however it is important that these are grounded at the top and bottom; any gap where contact is not made with the lid can turn the pillar into a resonator itself. This is also true of internal walls. Alternatively, microwave absorber or radio absorbent material (RAM) can be used to load the cavity. These come in two basic types, magnetically loaded and dielectrically loaded. Different sizes are targeted at different

7.3 Housing

305

frequency ranges so it is important to choose the correct one for your application. Lowcost foam versions (see Figure 7.7) are often also electrically conductive so care must be taken not to short out circuits. Although an excellent solution to moding problems, one should not “dive in” and distribute RAM about the cavity before investigating the cause of the oscillation or perturbation in the response. It could also be caused by poor grounding of the circuit board, thus you would be treating the symptom and not the cause.

7.3.4

Thermal issues and heat sinking Above room temperature the reliability of most components is inversely proportional to temperature, and components will have a maximum operating temperature above which permanent damage will be done. For microwave transistors a common figure quoted is that for every 10 ◦ C increase then the mean time to failure (MTTF) will reduce by a decade. Power amplifiers require good thermal management, not only for maximizing lifetime but also to obtain the best performance. The maximum temperature for the device is specified as the junction or channel (the current carrying region within the transistor) temperature. The manufacturer will also specify the thermal resistance (TR) from the junction to the device flange. The design task is to ensure that the junction temperature is kept as low as possible, within the constraints of size, weight, and cost. Under steady-state conditions the resistance to heat flow is a product of two factors, the intrinsic TR of the material and the interface with the next layer. Initially, there is also thermal inertia (TI) (or thermal capacitance) which may be important in pulsed amplifiers, as gain and output power are proportional to the channel temperature. The thermal components can be represented by electrical analogues, resistors for TR and capacitors for TI. For example, consider a transistor screwed into a box which in turn is bolted to a heatsink. In this case there is the TR of the device channel to flange, θ jc , that of the layer between the flange and the box floor, θ fb , the box material itself, θ bx , the box heatsink junction, θ bh , and finally that of the heatsink (assumed to be either in still air or a fixed air flow), θ h . All of these TRs add to give a net θ T , see Figure 7.12a. A note of caution, the thermal resistance is not constant, it is proportional to the temperature difference, the greater the difference the greater the heat flow. The TI of the interface layers is typically very small and is ignored. The temperature differential between the device channel and the heatsink is the dissipated power PD , times θ T . The TI can be calculated by observation of the actual temperature rise profile [5], which is described by the formula:   (7.2) Trise = θ jc Pd 1 − e−t/θ jc C j where t is the time. A typical response is shown in Figure 7.12b. The TR of a particular junction is a result of the intrinsic material thermal conductivity (W/m ◦ C), where the m refers to the thickness of the material in metres. While this would appear to suggest that all materials should be as thin as possible this is not quite the case; in order for the heatsink to operate most effectively the temperature must be given the opportunity to “spread,” otherwise only a limited portion of the heatsink will be effective in removing

Microwave hybrid amplifier realization

Channel Junction to Flange, θjc

Box Floor, θbx

Flange to Box Layer, θfb

Box to Heatsink Layer, θbh

Flange Thermal Inertia, Cj

Heat Source PD

Heatsink to Ambient Air, θh

Box Floor Thermal Inertia, Cb

Heatsink Thermal Inertia, Ch

θT = θjc + θfb + θbx + θbh + θh (a)

Temperature Rise 160.00 140.00 120.00 Temperature (°C)

306

100.00

For:

80.00

Θjc = 2.8 °C/W

60.00 Cj = 0.1 × 10–6 °C/s

40.00

Pd = 50 W

20.00 0.00 0.00

0.20

0.40

0.60

1.00

0.80

1.20

1.40

1.60

Time (μs) (b) Device

Mounting Holes

Device Flange 70°, ‘spread’ angle

H

x = H tan 70° (c)

Figure 7.12 Thermal performance: (a) electrical analogue of thermal resistance and inertia; (b) example thermal profile showing effect of thermal inertia; (c) thermal spreading below device.

7.3 Housing

307

the heat. In terms of heat transfer it is recommended that the heat sources be separated such that the heat “illuminates” an area defined by a 70◦ angle as shown in Figure 7.12 (c). In practice, other considerations come into play, such as: r thickness required for mounting screw tapping (1.5 × diameter minimum); r separation of devices, determined by flange width or the RF matching circuits. Ideally H and the device separation should be set such that the “illuminated” areas just touch for each device; r box width. One of the advantages of using multiple devices over a single high-power device is the ability to spread the thermal load over a larger area. The response in Figure 7.12b is typical for a power device flange, this has limited thermal capacity because of its physical size. When considering large boxes the effect can be a much greater time delay. For surface mount devices (resistors and loads as well as transistors) the heat is mainly transferred to the ground plane through via holes. The ability of a single via to conduct heat is given by the thermal resistivity, θ v : θv =

4h κπ (do2 − di2 )

(7.3)

where h is the substrate thickness and do and di are the outer and inner diameters of the via. The constant, k, is dependent upon the conductor (plating) material and for copper is 384 W/m ◦ C. This assumes that the via is unfilled, filling the via will improve the thermal conductivity, however the conductivity of solder (Figure 7.2) is significantly less than that of copper and hence, it is best to err on the side of caution and ignore the filling effect. A number of vias will be required to achieve the required TR, it should be remembered that as the via gets further away from the heat source then so its TR increases. It can be seen from Figure 7.12a that the easiest way to reduce the operating temperature is to remove an interface, e.g., directly mounting devices to the heatsink. For MHPAs a problem comes from maintaining a good RF ground; the ground plane of the matching circuits must be continuous with that under the devices as shown in Figure 7.5. Extruded heatsinks have a reasonably wide dimensional tolerance, which must be catered for in approaches such as Figure 7.9e. A solution is to manufacture the housing and heatsink as one unit. In order to reduce the TR of the interface layers a thermal compound is used to fill the microscopic air gaps between the mating surfaces, but applying it liberally can actually increase the thermal resistance; thermal compounds are not as good thermal conductors as the metals used in the flange or the housing. Although widely used below microwave frequencies this approach is seldom used above 1 GHz, as the best thermal compounds are electrically nonconductive, and attempts to improve the electrical conductivity have degraded the thermal resistance. An alternative is to use soft thin metal shims such as Indium under the flange. These deform and compensate for any surface roughness; however, they also introduce another interface layer. The best solution is for the finish of the metal surfaces to be as flat as possible. Selectively machining the recess where the

308

Microwave hybrid amplifier realization

devices sit to a “mirror” finish is an acceptable solution in lower volume applications; this is smoother than that on the underside of most transistors. Where a heatsink is bolted to the housing floor the electrical conductivity is less of an issue and in this case a thermal layer is appropriate and a graphite sheet may be considered. This has high thermal conductivity (20 W/m ◦ C) and is manufactured in sheets as thin as 0.13 mm. It is much easier to handle and less messy than thermal grease. In addition to the flatness of the mating surfaces it is important that the correct torque is applied to the screws fixing the transistor. This information is available from the device manufacturers and depends on the material and thickness of the flange. Over-tightening can cause the flange to bow, which will not only increase the thermal resistance but could damage the brittle materials inside the package (ceramic and active device). The screws should be as large as will fit in the flange holes, with both a flat and spring washer. “Cap-head” socket types have less risk of the driver slipping and damaging surrounding circuitry. When tapping into soft metals such as copper or aluminum, it is important to use a slight countersink. If over tightened the edges of the hole can become raised and thus distort the mating surface (some flanges have the countersink included which is equally acceptable). The finish and flatness of the underside of the device flange should be inspected as part of the assembly operation, if not on an individual basis then certainly on a sample of each delivery. Any sign of twisting or scratching of the flange should be a reason to reject the device back to the supplier. Some device suppliers suggest that the flange flatness can be improved using wet/dry abrasive paper – don’t accept it! The manufacturer is responsible for providing the devices in a useable condition, but such polishing may be necessary on the housing mating surface. For class A biased devices a simple check is to measure the flange temperature under known conditions. Where the budget allows or volume is sufficient, a thermal imagining system can quickly spot a device that has not been mounted correctly. Note: “issues” have been seen with some of the handheld infra-red thermometers when amplifiers are operating with RF signals, the exact interference mechanism is not currently known. Detailed thermal calculations are very complex. Finite element software is available that can model thermal behavior, however these tend to be expensive and the simulations difficult to construct. In a known environment, that is, where the power to be dissipated and the size of the amplifier housing are known, it is often simplest to construct a test using an equivalent load resistor (dissipating the same heat as the power transistor(s) in the worst case scenario) bolted to the floor of a representative housing. This not only assists in the selection of the best heatsink and the required air velocity, but also where size and weight are critical parameters, what customization of the heatsink can be made without affecting the heat transfer to the air. It is important to include in the experiment heat sources for the main power dissipating circuit elements, including those of the DC bias circuit. Many different types of heatsink are available, from the conventional parallel finned to the “post” style used with computer processors. This latter type often comes with fittings for fans to be directly attached and uses a turbulent air flow, as well as relatively large surface area to maximize heat transfer to the air. Standard heatsinks use a parallel array of tapered fins, while others use a “root” style as shown in Figure 7.13a. These are made using aluminum extrusions, cut to the appropriate length. Where the

309

7.3 Housing

125 60 16

Typical Performance

°C/W Black

Length

50 100 150 200 300

°C/W

0.64 0.46 0.35 0.28 0.24

1.00

135

°C/W

0.80 Natural Finish

0.60 0.40

Black Anodised

0.20 0

0

50 100 150 200 250 300 Length in (mm)

(a) 1.0 0.9

0.7 0.6 0.5 0.4

0.3 0.2 0.1

1

2

3

4

5

ABL REF

θ

No.of fins

195AB

300

22

196AB

400

30

197AB

500

38

198AB

600

46

199AB

750

58

0.30 0.25 °C/W

MULTIPLICATION FACTOR × CW

0.8

195AB

0.20

196AB 197AB 198AB 199AB

0.15 0.10 0.05

50

100 150 Length in (mm)

200

6

AIR VELOCITY Meters Second (m/s)

(b)

(c)

(d) Figure 7.13 Heatsink types: (a) “root” style, note improvement in q from black anodizing;

(b) impact of air flow; (c) high power ridged fan heatsink; (d) extruded heatsink with cross-cut; (e) bonded fin assembly; (f) complex dip-brazed assembly. Photos (a)–(c) courtesy of ABL Ltd., www.ablcomponents.co.uk, photos (d)–(f) courtesy of H.S. Marston Ltd., www.hsmarston.co.uk.

heat is distributed evenly across a housing floor, sheets of aluminum can be brazed or epoxied into an aluminum housing or base plate, Figure 7.13e. Although the junction between the fin and the plate is not as thermally efficient as an extrusion, the surface area of the heatsink is greater for an equivalent footprint (more fins). Heatsinks can be constructed out of the housing itself. An integrated heatsink will have superior performance as the thermal junction between the housing and the heatsink

310

Microwave hybrid amplifier realization

(e)

(f) Figure 7.13 (cont.)

has been eliminated. In volume applications the housing may be cast; the internal floor will require machining to give a good surface flatness where the power devices are to be mounted, but with a rougher finish the heatsink fins will cause more air turbulence and a larger surface which will improve heat transfer, Figure 7.13c. The capability and speed of modern machining stations has meant that it is often cost-effective to produce housings by direct machining; however, producing the relatively narrow, deep gaps required may be difficult using conventional cutters. An alternative that has been used successfully is to make an array of diamond wheel cutters on a spindle, with the appropriate gaps set using spacers. This can then cut the slots required in the housing block. The alignment of the heatsink fins relative to the heat producing components is important when forced air cooling is employed. Where possible the arrangement should be such that the components are perpendicular to the airflow, otherwise the air will be

7.3 Housing

311

preheated by the first components. Without forced air the heatsink should be mounted with the fins vertical. The primary method of heat loss is convection but radiation can play a secondary roll. The ability of a surface to emit infra-red radiation is referred to as emissivity (ratio compared to an ideal black body), thus black anodized aluminum finish is common for heatsinks (emissivity of ∼0.8 compared to ∼0.05 for polished), see Figure 7.13a. The treatment to increase emissivity must not insulate the heatsink from the air. As most of the cooling is a result of convection, it follows that cooling effectiveness is dependent on air density and hence altitude. An altitude of 3000 m will degrade a heat sink’s efficiency by ∼20%. When pushed to reduce the junction temperature then increasingly complicated methods can be used. The effectiveness of a heatsink can be increased by forced air cooling. If this is available within the system it is a simple solution, however if including a fan with the amplifier, consideration must be given to failure and maintenance. The fan is probably the most unreliable component (moving parts) and will have a limited life. It is also more susceptible to shock and vibration. Airflow improves the effectiveness as shown in Figure 7.13b. Aluminum is commonly used in microwave housings for reasons of cost, weight and machinability, however its thermal conductivity is almost half that of copper (250 compared with 400 W/m ◦ C). Some amplifiers have been constructed with a copper “puck” fixed into the floor of an aluminum housing, with the devices bolted onto the copper. Water cooling can be very effective, but many steer away from it for the simple reason that water and electricity is not a good mixture! One solution is to use water to cool a plate onto which the amplifier modules are bolted. This can be constructed using dip brazing techniques or having copper pipes epoxied or soldered into the cooling plate. Another extension of this approach is to use heatpipes. These components have thermal conductivities up to a thousand times greater than copper. Typically, they are made in rod form and work by the heat at one end causing a liquid in the tube to change to a vapour which, due to the low pressure inside, quickly moves to the other end where it cools back into a liquid, so transferring energy. The liquid is absorbed into a porous lining and is drawn by capillary action back to the hot end. Heatpipes can be embedded in amplifier modules or cold plates with the cold end clamped to a water-cooled heat exchanger. Sometimes the customer provides a cooled-surface onto which the amplifier module is clamped. This is also known as a “cold-wall.” The responsibility for removing the heat is theirs, however the designer must ensure that there is sufficient thermal transfer between the two surfaces. It is also important that the customer is fully aware of how much heat will be generated. There are broadband class A power amplifiers that have efficiencies of between 10 and 20% which may surprise some.

7.3.5

RF connections Microwave signal connections are most often coaxial, although direct waveguide interfaces are also used (Figure 7.7). The type of coaxial connector is dependent upon the operating frequency and power level. To make connectors function at high frequencies

312

Microwave hybrid amplifier realization

Table 7.6 Coaxial connector power handling calculations Maximum average power (W) Connector type

N

SMA

3.5 mm

2.4 mm

Max. oper. freq.

18 GHz

26 GHz

40 GHz

65 GHz

Frequency (GHz) Max. power (W)

1 1900

10 570

1 590

10 180

1 280

10 85

1 130

10 36

Note: this assumes a perfect match, 23 ◦ C, in dry air at sea level. Temperature (◦ C)

De-rating

Altitude (m)

0

40

80

0

1500

15,000

1.2

1.0

0.8

1.0

0.95

0.5

the size is decreased; this reduces both the current handling and the voltage breakdown, thus reducing the power handling capabilities. Besides match, the operating environment must also be considered as both temperature and altitude reduce the power handling ability of coaxial connectors; the quoted figures from Astrolab Ltd.4 are included in Table 7.6. The performance of the connector depends upon the materials used (their purity), method of constraining the center conductor, and the precision of the manufacturing. The use of epoxy center contact captivation (identified by a hole in the metal walls filled with the epoxy – typically blue or black) should be avoided in high-power applications; the epoxy has higher loss than the surrounding PTFE and consequently experiences localized heating which can result in the epoxy “blowing out” of the connector. Example de-rating calculation: SMA connector at 10 GHz operation at 80 ◦ C and 1500 m, then 180 × 0.8 × 0.95 = 136.8 W. The most common method of connecting to the RF PCB is to bolt the connector through the sidewall of the chassis, Figure 7.14a. The connector center pin can be supported by an extended dielectric (usually PTFE). In hermetically sealed and fieldreplaceable units the center pin will be a separate part mounted in a glass bead and soldered or fired directly into the housing. Where the pin is unsupported the diameter of the hole through which it passes must maintain 50 . In the PTFE sleeved case, the manufacturer sets the PTFE diameter to produce a 50  transmission line. In the case of an air-filled hole the relationship between the pin diameter and that of the hole can be approximated by a simple formula: Z 0 = 138 × log

D d

(7.4)

which, for 50  impedance, simplifies to D = 2.303 × d where D is the outer diameter and d is the pin diameter. 4

www.minibend.com.

(7.5)

7.3 Housing

313

Figure 7.14 Coaxial launches: (a) panel mount; (b) impedance discontinuity at transition; (c) through-board mode suppression; (d) stress relief tape bond; (e) stress relief sliding contact. Photo (e) courtesy of Anritsu Ltd.

314

Microwave hybrid amplifier realization

Table 7.7 Coaxial transition parameters for 50  and cut-off frequency Centre pin (mm)

Feed hole (mm)

Cut-off frequency (GHz)

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

1.15 2.30 3.45 4.61 5.76 6.91 8.06 9.21 10.36 11.52

115.6 57.8 38.5 28.9 23.1 19.3 16.5 14.4 12.8 11.6

For power applications it is important to maximize the current carrying capacity of the connector, as the diameter increases so the coaxial transmission line can support other modes which can be excited at a discontinuity, e.g., the transition from coax to microstrip and vice versa. Thus, it is necessary to keep the dimensions below the frequency at which these other modes can start to be supported. Table 7.7 shows the relationship between pin and hole diameter and higher order mode cut-off frequency. It has been noted that where a discontinuity exists this can launch other modes. Figure 7.14b highlights the risk area around the connector launch. This figure shows the region where the coaxial fields of the connector are changing to the transverse fields of the substrate. It can also be seen that the length of the signal path and that of the ground path are different, which causes the even and odd mode phase velocities to become out of step. Note that this is also an issue where different parts of a circuit are mounted on carrier tiles. At connector launches this ground path problem can be resolved by extending the housing wall to overhang the PCB and by placing ground pads with vias included on the top surface of the PCB. An approach using this method has been described [6] which shows excellent performance to >40 GHz. A modification of this is to create a taper transition from coplanar to microstrip. A drawback of this approach is that the PCB needs to be mounted under the connector. It is sometimes required to mount the connector through the substrate material as shown in Figure 7.14c. PCB mount connectors are becoming increasingly popular; however care must again be taken to avoid moding. Many conventional PCB connectors have integral posts at the four corners of the flange which are intended to be soldered through the PCB. As well as providing a mechanical connection these can also help to reduce moding at the right-angle connection. As the operating frequency increases four posts are not sufficient and additional vias are required. These grounds can be posts, plated vias, or mounting screws. Direct solder attachment of the center pin to the PCB track is the standard approach with soft substrates as the “give” in the substrate material provides thermal and mechanical stress relief. Mechanical pressure is put on the pin during the mating cycle. For hard

7.4 Components

315

substrates there is little compliance so a direct solder attachment is not recommended. There are a number of variations on the wire bond link shown in Figure 7.14d, including having the center pin flattened at the end and the wire bond at right angles to the pin (which is slightly offset from the track). A very successful solution is shown in Figure 7.14e where a sliding contact fits over the center pin. This contact can itself be soldered directly to the PCB track.

7.4

Components The components used in hybrid microwave amplifiers can be divided into active and passive. MHPAs take advantage of the compact space that a lumped element component can provide or the tailored frequency performance of a distributed component. Advances in processing have produced low-temperature co-fired ceramic (LTCC) discrete packaged devices, which may contain a mixture of discrete and distributed components in what appears to be a single element, thus there is even a blurring of the categorization between lumped and distributed. A conflict exists between accepted practice in the general electronics engineering industry and what “tricks” you can play to improve RF performance. For example, mounting a surface mount chip resistor on its side can shift a package resonance up in frequency – out of the wanted band – but will give production engineers with automated assembly lines high blood pressure! Chip components have recommended pad sizes for solder connections. These pads will have an associated capacitance which the designer may want to minimize. Hence, a compromise needs to be reached between the RF performance and the production requirements. In the end, the component must meet its RF performance requirements while still being manufacturable.

7.4.1

Passive – lumped components Amplifiers require capacitors, resistors and inductors for their operation. In microwave design such elements do not behave as a pure element. By knowing the properties of the element, these can be incorporated into the circuit design and used for our advantage. For example, a feedback network may comprise of a resistor, a capacitor and an inductor. The capacitor (C), and resistor (R), will have parasitic inductance. By choosing the appropriate physical size and shape for the capacitor and resistor they can either reduce the inductance needed or encompass it entirely within the two elements. Modeling the Rs, Ls, and Cs can be done either using a physically based model or by using experimentally measured S-parameters. Many component suppliers now produce libraries of data on their components which can be readily used in simulators. Users should approach these with caution, particularly as frequency increases. Ideally, the surroundings should have been entirely de-embedded so that the model exists independent of its environment. It is important to verify the models used in the environment in which the components are intended. It is also useful to understand the construction of the components so that there may be some expectation of the behavior with frequency.

316

Microwave hybrid amplifier realization

Resistors These have a wide variety of uses in amplifier circuits, e.g., low-frequency biasing, loads, attenuators and feedback elements, and signal balancing in combiners. In microwave applications resistors are mainly made from metal films, the metal being chosen for its resistance properties rather than its conductivity as in PCB tracks. The majority of resistors used are based upon a surface mount chip, however there are times (particularly below 3 GHz) when the inductance associated with a leaded resistor can be of benefit. Leaded resistors for such applications should be metal film as carbon composition or wire wound resistors generally contain many parasitic elements and thus have widely varying impedance characteristics. The inductance of the lead lengths associated with the resistor is calculated from:   4l Inductance in nH = 0.2 × l 2.3 × log − 0.75 , (7.6) d where l is the lead length and d is the diameter (in mm). Chip resistors basically consist of a ceramic tile onto which has been deposited a metal film (thin film) or paste (thick film). The paste is fired at high temperatures and then the resistance can be trimmed to the necessary value. The continued miniaturization of electronics has been beneficial to the microwave industry as the smaller the component then the lower the parasitics and hence the closer the performance is to that of the “pure” element. With size reduction comes lower power handling. The exact power handling ability is dependent on a large number of factors and has been excellently documented in other work [7]. As discussed in Section 7.2, at high frequencies the current is not evenly distributed through the conducting material, thus the quality of the conducting surface is of paramount importance, and this tends not to be well controlled in thick film products due to the nature of the paste. The key aspect of thick film is that it is low cost. Thin-film resistors are more expensive to manufacture. A thin resistive layer, typically of nickel/chromium (nichrome) or tantalum nitride is deposited on the ceramic and then conductive terminations are deposited at either end. Sheet resistances vary between 5 and 250 /sq which are very suitable for the typical resistances required in amplifier circuits. It is important to check how the resistance values are trimmed, see Figure 7.15a, as sometimes a path is cut in the conductor which can have intrinsic capacitive and inductive effects. The end terminations on standard resistors tend to be “wrap-around” as the topside is also often printed with the resistive material. Better RF behavior may be achieved by mounting the resistors upside down as this reduces the effective electrical length, but it will also increase the capacitance to ground. High-performance thin-film resistors are often offered with the option to have the end terminations on the top side only, and are mounted “flip chip.” For high-power application a third metallization can be added to the underside of the resistor so that it may be soldered directly to the ground plane for optimum thermal transfer. Specific values for resistors, such as 50 , have been produced with one of the end terminations wrapped around to cover the complete underside of the resistor. This is for use in terminations or loads. The majority of surface mount resistors are made using alumina substrates. For high-power applications beryllium oxide (BeO), thermal conductivity 290W/m ◦ C, or

317

7.4 Components

CAP ID=Cf C=0.021 pF

Helical Trim

PORT P=1 Z=50 Ohm

RES ID=R1 R=100 Ohm

IND ID=L1 L=LPS nH

PORT P=2 Z=50 Ohm

Pulsed Trim CAP ID=Ci C=0.02 pF

CAP ID=Ci C=0.02 pF

Meander Trim

(b) (a)

Thru Loss

Insertion Loss (dB)

–6

–8

DB(|S(2,1)|) 100R_Modelled_RTD DB(|S(2,1)|) 100R_Modelled_AI

–10

DB(|S(2,1)|) 100R_Sparams DB(|S(2,1)|) Lumped Model AI

–12

DB(|S(2,1)|) Lumped Model RTD

–14

0

5

10 Frequency (GHz)

15

20

(c)

Figure 7.15 Surface-mount resistors: (a) resistor trimming approaches; (b) simple equivalent circuit for 0603 resistor on 0.8 mm thick εr = 2.2 with recommended mounting pads; (c) performance of 0603 100  resistor, manufacturer’s raw data (100R_Sparams), resistor model and EM on 0.635 mm alumina and RT duroid 5880 substrates and lumped equivalent circuit.

aluminum nitride (AlN), thermal conductivity 170W/m ◦ C, are used. Despite having lower thermal conductivity, AlN is increasingly popular as beryllia is highly toxic in its powder form. It is banned in a number of applications and countries, products containing it must be appropriately labelled, and it is difficult to dispose of. Increasing volumes and the number of suppliers have seen the price of AlN products fall to acceptable

318

Microwave hybrid amplifier realization

Table 7.8 Conventional thick-film resistors mounted on 0.8 mm FR4 substrate

Reference

Size (mils)

Size (mm)

Power rating (mW)

0201 0402 0603 0805 1206 2010 2512

20 × 10 40 × 20 60 × 30 80 × 50 120 × 60 200 × 100 250 × 120

0.51 × 0.25 1.02 × 0.51 1.52 × 0.76 2.03 × 1.27 3.05 × 1.52 5.08 × 2.54 6.35 × 3.05

50 63 100 125 250 500 1000

levels. Where single terminations cannot handle the power level required, resistors can be used in parallel. This has the added advantage of reducing the series inductance, but capacitance can increase. Resistors in microwave circuits are often approximated by a simple equivalent circuit, as shown in Figure 7.15b. However, it should be noted that the value of Ci is dependent upon the pad size and the substrate used, hence a generic model for the resistor should not be used. The value of Cf depends upon the resistor size, pad dimensions, and end terminations. An example of how different models and substrates will affect the model performance is shown in Figure 7.15c. A 100  resistor has measured S-parameters from 45 MHz to 2 GHz; these are extrapolated to 20 GHz as a reference. The resistor is modeled using both a lumped element equivalent circuit as in Figure 7.15b and a using a modified equivalent circuit replacing Ci with an EM simulation for the mounting pads. The parasitic inductance and the resistance are constant for all simulations. This shows that the performance of the resistor itself cannot be taken in isolation. If S-parameters are used they need to cover the full frequency range and be properly de-embedded from the measurement test fixture. The mounting pads need to be included in the simulation, either directly or as tracks feeding the component. Table 7.8 lists the power rating and size of common surface-mount resistors.

Capacitors These are essential in the operation of microwave amplifiers, they have functions at both DC and RF and the requirements are often at odds. They are used for interstage bias de-coupling, matching, by-passing and localized charge storage. As with resistors, not only must their primary characteristic – capacitance – be considered but also the parasitic elements. In its most basic form a capacitor consists of two parallel plates separated by an insulating material. Such capacitors, called single-layer capacitors (SLCs), are commonly used in microwave applications. The capacitances that can be achieved are determined by the relative dielectric constant of the insulating material, εr . The capacitance, C in pF is given by C=

0.00885εr A , d

(7.7)

7.4 Components

319

Horizontal Orientation C17AH101K-7UN-X0T 100.0 pF Temp = 25 0 –1

S21 (dB)

–2 –3 –4 –5 –6 0

1

2

3

4

5

6

7

8

9

10

Frequency (GHz) Vertical Orientation C17AH101K-7UN-X0T 100.0 pF Temp = 25 °C 0 –1

S21 (dB)

–2 End termination

–3

Capacitive Plates, end termination removed.

–4 –5 –6 0

1

2

3

4 5 6 Frequency (GHz)

7

8

9

10

Figure 7.16 Effect of plate orientation. Courtesy of Dielectric Laboratories, Inc., www.dilabs.com.

where A is the area of the plates in mm2 and d is the separation in mm. Working against the application of the capacitor in MHPAs is that the closer the plates are then the lower the breakdown voltage, and the higher the εr the worse the temperature stability and often the loss. In order to achieve high capacitance values layers of capacitors can be made with alternate plates joined together as shown in Figure 7.16, hence their name “multilayer capacitors” (MLCs). In this way higher capacitance values can be achieved for the same foot print. The parasitic elements of a capacitor are largely due to the dielectric materials and the physical size. The inductance is proportional to the length of the plates. The loss in the dielectric, (the energy that is dissipated as heat) is expressed as a resistance in parallel, RS . Modeling capacitors in the microwave region can become very tricky, not least because the performance changes dramatically with orientation, as shown in Figure 7.16. With the plates parallel to the ground plane (horizontal) a series of resonances exist, rotating the capacitor 90◦ so that the plates are now perpendicular to the ground plane (vertical) removes half of the resonances. There are a number of

320

Microwave hybrid amplifier realization

Table 7.9 Characteristics of various dielectric materials and approximate changes with frequency Material

εr

Tan δ (DF)

Q100 MHz

∼Q1 GHz

∼Q10 GHz

Barium Titanate Ceramic Alumina Porcelain

1200–8000 30 10 15

0.03–0.1 0.002 0.0005 0.00007

33–10 500 2000 ∼14000

3–10 50 200 1400

<1 5 20 140

theories regarding this behavior, one is that it is due to the physically longer path-length between the signals of the top and bottom plates in horizontal mounting, another is that the capacitor acts like a folded transmission line connected to the feed track at one end and open circuit at the other, thus becoming a resonator [8]. It is arguably simpler and more practical to measure the S-parameters of a capacitor than develop a model, particularly if one would need to make a measurement to verify the model! As in the discussion on resistors, the effect of the substrate cannot be ignored. For MHPAs the most important characteristic is the insertion loss. Assuming that a suitable value of capacitance is chosen to keep the impedance low (1/ωC) then the loss is a result of the dielectric loss. This has several measures, quality factor (Q), dissipation factor (DF) or tan δ. Q=

1 XC 1 · = = DF tan δ RS

(7.8)

An ideal capacitor would have the RF current lead the voltage by 90◦ . In the real world this is not the case and the phase difference is δ. This is more commonly quoted as tan δ (where the measure of substrate loss comes from). Tan δ is dependent upon frequency and temperature, but unfortunately few manufacturers provide information on this relationship. For example, having measured the output power of a device and the insertion loss of the output matching circuit including a decoupling capacitor, it is found that the output power is lower than expected. The measurement of the matching circuit was under small signal conditions, under power conditions the loss causes heating, which increases the tan δ, increasing the loss. It must be remembered that an insertion loss of 0.1 dB equates to 2% of the power being lost in the device. In 100 W that is 2 W in a very small space. Table 7.9 gives a summary of the characteristics of some of the most common materials used in capacitor dielectrics. The manufacturer’s measurements are generally made at low frequencies and the values for Q in the table are approximate based upon observed performance. Although exact data is rarely provided in data sheets at the frequencies, temperatures and power levels that a designer might want, what is clear is that the materials used should have the lowest possible loss. The insulation resistance, RP , (the DC current path through the dielectric material), is typically of the order of 100,000 M and so is usually ignored for RF purposes. For frequencies up to 8 GHz where MLCs are used, the capacitance values decrease with frequency to avoid self-resonance with the internal inductance. SLCs are preferred

7.4 Components

321

above 8 GHz although their planar construction may necessitate wire bonding or careful hand soldering. Dielectric Laboratories offer a “Gap Cap,” where the bottom plate of the SLC is split in half effectively making two series capacitors. This may be more suitable for some production environments than a SLC, but note that it does have a slightly lower self-resonant frequency (SRF). For narrow band applications it is possible to use MLCs above the SRF for DC blocking, however it should be noted that above SRF the impedance of the capacitor increases like an inductor. Indeed, in some applications chip capacitors have been used above their SRF as inductive elements as they are more repeatable, lower cost, and easier to handle than very high-frequency inductors. It is risky to operate near the SRF as the impedance varies rapidly in this vicinity and is sensitive to temperature. It should also be noted that although capacitors from a single supplier are highly repeatable, performance will vary for similar types of capacitor between suppliers, particularly the SRF. The electronic industries association (EIA) divides capacitors into three classifications, which are basically determined by the stability of the capacitance. For matching and coupling EIA class 1 are used, for charge storage and low-frequency bias decoupling class 3 is used. Aging is generally not a significant issue in class 1 capacitors; however in class 3 the variation can be significant. This is caused by temperature and high-voltage field strengths affecting the crystalline structure of the dielectric. As mentioned, for the parts of the circuit where the RF signal flows it is required that the insertion loss be as low as possible, but there are parts of the circuit where this characteristic is not the case. Where broadband decoupling is required, for example at the ends of bias lines, the intention is to ensure that unwanted signals are terminated. Damping resistors in the bias lines cause problems with changing voltage drops with frequency, but a lossy decoupling capacitor will not affect the DC performance. Here a mixture of capacitor types are used, a high-quality MLC and one or more increasing capacitance ceramics.

Inductors The properties of inductors include the fact that their impedance increases with frequency. To increase the inductance the wire can be wound in a coil. This increases the magnetic flux linkage, which opposes the flow of current through the wire, hence increasing the inductance. The coil also has capacitance between the turns, which causes the inductor to have a self-resonant frequency. Conversely to the case with the capacitor, above SRF the inductor behaves as a capacitor, i.e., its impedance decreases with frequency. For the lower microwave regions wound inductors can still play a part, however they are usually air cored and their impedance can vary dramatically. Their main application is in bias circuits where a few turns of spaced coils can produce a useable inductance; at higher frequencies a single loop of wire can be used. A danger with these types of component is that the fields are not well contained and thus they can be sources of transmission and reception of radiation. Where they are used they are often positioned such that they are at right angles, and physically separated as far as possible. Some companies have succeeded in producing low-inductance surface mount chip

322

Microwave hybrid amplifier realization

inductors, however their current handling and range is relatively limited. The inductance, L, of an air cored coil is given by [9]: L=

0.394 × r 2 N 2 , 9r + 10l

(7.9)

where r is the coil radius in cm, N is the number of turns, and l is the length of the coil. Also, for optimum Q, l = 2r. Very wideband inductances have been achieved by winding fine gauge wire either on a removable conical former (hence, air cored) or on a conical iron former to increase the inductance. An advantage of using air cored inductors or even single loops of wire is that the effective impedance can be tuned, either by altering the height of the wire above a ground plane, or by altering the spacing (and the parasitic capacitance) of the turns on the coil. For many microwave applications it is preferred to use distributed components as discussed later.

Integrated components The developments in LTCC technology have given designers the option of incorporating a number of elements in a single packaged device. These are still volume applications unless the size/weight benefits can justify the setup costs. The approach consists of incorporating conductive, resistive and dielectric pastes onto “green” ceramic tapes. Different layers are laminated together and the whole assembly is then fired. Internal vias can be created, and each layer is inspected prior to laminating. In this way a variety of components from simple structures such as lumped element filters or bias “tees” to complete functional blocks can be created.

Isolators and circulators Another benefit of the mobile communications revolution was the packaging development of these magnetic/ferrite components. In the 1980s the manufacturing control of the ferrite and magnetic material was not as refined as currently and much of the assembly was by hand and integral with testing. The high volumes required for the base station industry put emphasis on packaging for automatic placement on circuits. This has resulted in parts which are now readily available in common frequency bands, and which are small and cost effective. Isolators and circulators have three main functions, (a) to provide isolation between stages, (b) to protect circuits from reverse power, and (c) to give the amplifier acceptable output impedance (Figure 7.10). The circulator is a three port device consisting of a “snowflake” copper foil sandwiched between two ferrite layers with a magnet adjusted for the correct “biasing” of the ferrite. The magnet ensures that the fields are orientated correctly. The operation of the circulator is described in Figure 7.17. The behavior is due to the nonreciprocal nature of the ferrite material. The signal entering port 1 splits and travels around to the other ports in opposite directions. As the phase velocity depends upon the direction of travel, then addition or cancellation can be arranged at the appropriate port by correctly applying the magnetic field. The center conductor is patterned to ensure symmetry of the structure and impedance matching (the impedance in the ferrite section is less than 50 ), the wider the bandwidth the more intricate this structure. An isolator is a circulator with port 3 terminated in

7.4 Components

323

Signal Flow: Port 1-2 Port 3 Isolated Port 1

Port 2

Port 2-3 Port 1 Isolated Port 3-1 Port 2 Isolated Physically the circulator is symmetrical internally.

Port 3

Figure 7.17 Functional diagram of a circulator.

a load. Circulators can be made to handle power levels up to kWs; power handling is proportional to size, the higher the power the stronger the magnetic field and the larger the copper center conductor. In isolators the load often determines the maximum power rating. Circulators/isolators have a bandpass characteristic, but care should be taken in high-power applications, hysteresis in the magnetic fields results in circulators having nonlinear characteristics and hence they can generate harmonics at high power levels, which can cause intermodulation problems. In systems where there is substantial electrical gain there also tends to be a risk of oscillation if the reverse isolation between stages is inadequate. Attenuators between the stages can help, however throwing away power is anathema to PA design engineers. Isolators, which are low loss in the forward direction (typically <0.5 dB) and high loss in the reverse (∼20 dB), can be a better solution. In class C pulsed applications, the input impedance of devices changes with applied power. Therefore, the load impedance seen by the driving device changes during the rising and falling edges of the pulse. It can be difficult to ensure a completely stable network especially when frequency and temperature are also thrown into the mix. The problem is exacerbated as one moves down the amplifier chain as each device is not only producing a changing input impedance due to its own drive level, but the load it sees is also changing. An isolator in the middle of the line-up can reduce this problem dramatically. Where the isolator is being used to protect the amplifier then “smart” loads are becoming more popular. These incorporate a temperature sensor onto the load which can be used to trigger a shut-down sequence if the reflected signal is too high. Care must be taken when handling and storing isolators as they are magnetized components and their behavior depends on the strength of this field.

7.4.2

Passive – distributed components Distributed elements are those structures whose physical dimensions fundamentally determine their electrical characteristics. Hence, the tolerances and repeatability of the manufacturing processes have a direct effect on the performance. On alumina circuits capacitors and resistors can be incorporated directly during the circuit fabrication process. For resistors, as with their lumped element equivalents, resistive pastes can be used in thick film circuits or a NiCr layer in thin film. These resistive materials are specified in terms of /square and the resistance, R, is proportional to the ratio of the length, l, to the width, w. R = resistivity ×

l w

(7.10)

324

Microwave hybrid amplifier realization

The width can be adjusted to match that of connecting transmission lines. Common resistivities are 50 and 100 /sq. Capacitors can be incorporated by putting down a dielectric on top of conductors and then overlapping with a conductive paste/plating. Although these have been proposed for use in soft substrates, particularly using conductive inks, there has not been a large scale take up as yet. Inductors on microstrip can be difficult to distinguish from high impedance lines. The exception is where the line is wound in a spiral (round or square sided) as is popular in MMIC applications. This is used less frequently in hybrid applications due to the relatively large size and lower Q compared to wound components. Similarly, interdigital capacitors are used less often in hybrid circuits. An exception is when edge coupled lines used in some bandpass filter applications fulfil two functions, that of filtering and DC blocking. For narrow band applications where the volumes are extremely high, edge coupled lines may be justified on their own. The most common distributed components are transmission lines. As mentioned earlier, the impedance ranges that can be created are limited due to moding and etch tolerances. In practice, circuit structures are also limited by the ability to simulate them within design tools. Distributed circuits have re-entrant properties, that is, the impedances repeat (approximately) at multiples of 90 and 180◦ . The behavior of distributed components with frequency differs to that of pure elements. For example, at a specific frequency a shunt inductor of impedance XL can be replaced by a shorted transmission line of impedance, Z0 tan θ where Z0 is the characteristic impedance and θ is the electrical length. However, whereas XL increases linearly with frequency, the line impedance increases with tan θ, which is periodic. There are a variety of equivalents between lumped and distributed components, some of which are given in Figure 7.18. The realization of distributed series capacitors, as mentioned above, is very difficult in hybrid applications. An exception is where very small values are required which can be achieved by using narrow gaps. A short circuited transmission line or short-circuit stub, is basically a transmission line with one end terminated in zero impedance, but this becomes more difficult to achieve as frequency increases due to parasitics. Common methods of producing a short circuit include using a via hole, edge wrapping and a solid ground plane (with or without via holes). One of the benefits of a distributed circuit is that a short circuit at the end of a λ/4 line looks like an open circuit at the other end of the line at the design frequency. Thus, another way of creating a short circuit is to attach a λ/4 opencircuit stub at the point where a short circuit is desired. This is inherently a narrow band structure; to broaden the bandwidth a radial stub can be used. Even more effective is a double radial or butterfly stub [10]. These solutions are often adopted as frequency increases and the inductance/phase length of via holes has more impact, or when an RF short is required but not one at DC. In bias feeds it is required that DC current be injected into the circuit but that the feed arrangement not load the RF matching network. Although microstrip impedances are typically limited to between 25 and 90 , it is possible to create effectively lower impedances by adding two o/c stubs in parallel. A comparison of the performance of various distributed stubs is shown in Figure 7.19.

7.4 Components

Inductor

XL = ωL

Transmission Line (Series)

325

Transmission Line (Shunt)

Z = Z0sinθ Z = Z0tanθ

Capacitor

Transmission Line (Series)

Open Circuit Stub

XL = 1/(ωC)

Z = Z0sinθ Where θ<45°

Z = Z0cotθ For θ<<90°

In the special cases where θ = 90° (quarter wavelength) at the resonant frequency:

Z0 = ∏ωL/4

Z0 = 4ωL/∏

And when θ = 180° (half wavelength) at the resonant frequency:

Z0 = 2ωL/∏

Figure 7.18 Equivalent lumped and distributed circuits.

When designing with microstrip elements it is important to remember that the models used were developed and optimized for specific substrate thickness to line width ratios. There are often a variety of models for the same structures and it is important to choose the most appropriate one for the materials and frequency range used. Where appropriate models do not exist, the use of EM simulation is necessary. This can be used for a specific section of the design, as simulating a whole circuit in this way can be time consuming and difficult to optimize. Transistors have a natural gain slope in |S21 | of 6 dB/octave. A method for compensating for this is to use lossy stubs or equalizers. These do not provide a DC path to ground and hence do not upset device biasing. The basic version of this approach consists of a resistor connected to an o/c stub, as is shown in Figure 7.20a. By altering the

Microwave hybrid amplifier realization

Table 7.10 Equalizer behavior as a function of resistor value Worst-case return loss (dB)

25 50 75 100

5.9 3.4 2.4 1.8

6.1 9.6 12.2 14.1

Swp Max 8 GHz

0.

4

2. 0

0.6

1.0

Approximate slope (dB/octave)

0.8

Nominal resistor value ()

0 3.

S(1,1) Radial Stub

4.0 5.0

0.2 10.0

5.0

S(1,1) Via

10.0

4.0

0.6

0.4

0

0.2

S(1,1) OC Stub

–10.0

S(1,1) Butterfly Stub

.0 .0

S(1,1) Double Stub –1.0

–0.8

–0 .6

–2

.0

.0

.4

–3

–0

–4

2 –0.

–5

326

Swp Min 2 GHz

Figure 7.19 Relative performance of short-circuit elements.

resistance different slopes can be achieved as shown in Figure 7.20b and summarized in Table 7.10. In narrow band applications the equalizer can be used for stopping highfrequency oscillation by introducing loss at the problem frequency.

Couplers There are a number of cases in amplifier design where it is useful to have the ability to sample the signal. Running a track close to the transmission line will intercept some of the electrical fields from the main line and as a result power will be coupled; the closer the line, the higher the coupling. Also, the more field the main line “distributes” into the surrounding, the greater the coupling. A 3 dB coupler will transfer half of the energy to the coupled line, however this will require very tight coupling. As a rule of thumb, when the separation is of the order of the substrate thickness the coupling will be about −20 dB.

327

7.4 Components

PORT P= 1 Z=50 Ohm

ID=TL1 W=0.6 mm L=5.8 mm

ID=TL3 W=0.6 mm L=5.8 mm

MTEES ID=TL2 1

2 PORT P=2 Z=50 Ohm

3

MSUB Er=9.8 H=0.635 mm T=0.02 mm Rho=1 T and=0.0005 ErNom=9.8 Name= SUB 1

TFR ID=TL4 W=WR mm L=LR mm RS=50 F=5000 MHz

WS=0.6 LS=9.2

MLEF ID=TL5 W=WS mm L=LS mm

(a)

Lossy Equalizer

6 GHz –0.08673 dB

0

0

–1

–5

–2

–10

–3

–15

–4

–20

–5

DB (|S(2.1)|)(L) Equalizers

Return Loss (dB)

Insertion Loss (dB)

3 GHz –6.143 dB

–25

DB (|S(1.1)|)(R) Equalizers

–6

0

2 3 GHz –5.967 dB

4 6 Frequency (GHz)

8

–30 10

(b)

Figure 7.20 Lossy stub equalizer: (a) schematic of lossy stub; (b) performance, S21 and S11, as resistance is varied between 50  (faint traces) and 25  (bold traces).

Couplers are frequency dependent, (λ/4 long). To increase the bandwidth multiple sections can be used. In order to achieve tight coupling designers have moved away from planar microstrip structures to multilayer stripline. This allows very small gaps between the tracks on different layers separated by a thin dielectric layer. These have become standard discrete components that can be either surface mounted or bolted in a similar manner to flange mounted devices. In this way compact quadrature (90◦ ) hybrid

328

Microwave hybrid amplifier realization

Figure 7.21 Discrete quadrature (90◦ ) hybrid couplers, narrow and octave bandwidths from 2 to

8 GHz. Courtesy of SJ Technologie, www.sjtechnologie.com.

couplers have been produced which are very important in creating balanced amplifier designs which are described in Section 11.7. Wide bandwidth designs can be bought off the shelf, Figure 7.21, and standard products are available up to about 8 GHz, however for reasonable quantities (>1000 p.a.) a number of companies will be prepared to create a custom design.5 Figure 7.22 shows an MHPA utilizing these components. Where volumes are not sufficient and the standard products don’t meet the necessary performance there is an alternative product which can be easily customized to produce octave band, 3 dB couplers over the desired frequency range. Commonly known as R , these consist of two wires with a tightly controlled separation within a Wirelines 50  environment maintained by an outer jacket such that they look similar to a piece of semirigid cable, as shown in Figure 7.23. They have been successfully used in amplifiers up to at least 6 GHz, although careful attention to the wire connections is required to avoid the inductance of the wires reducing performance. Quadrature couplers can be created directly on the substrate as shown in Figure 7.24. The most basic approach is to use a Wilkinson splitter with a λ/4 line, Figure 7.24a, to produce a 90◦ phase difference between the output ports. The balance between the ports is excellent over a wide bandwidth; however the phase difference is frequency dependent. The resistor between the output arms is used to dissipate any imbalance in the voltages, it may be omitted (and often is in high-power applications) at the cost of degrading isolation

5

This approach has been successfully used in a 4–8 GHz amplifier application.

7.4 Components

329

Figure 7.22 MHPA incorporating quadrature couplers: (1) Surface-mount quadrature hybrid coupler; (2) bolt-in quadrature coupler; (3) edge coupler; (4) output circulator. Courtesy of Microwave Amplifiers Ltd., www.maltd.com.

Figure 7.23 Wireline couplers. Photo courtesy of Sage Laboratories Inc., www.sagelabs.com.

between the output ports. Part of the problem with this resistor is the associated parasitics, and as the power increases and the resistor gets larger, so the problem gets worse. For narrow band designs the resistor can be offset by λ/4 lines reducing the parasitic effects at the center frequency. The Branchline Coupler, Figure 7.24b has a number of advantages;

330

Microwave hybrid amplifier realization

Wilkinson

-0

-10

-0.1

-14

-0.2

-18

-0.3

-22

-0.4

-26

(a)

-30

-0.5 2

4

6

8

Frequency (GHz) DB(|S(2,1) |) (L) Wilkinson

DB(|S(1,1) |) (R) Wilkinson

DB(|S(3,1) |) (L) Wilkinson

Branchline

-2

0

-4

-10

-6

-20

-8

-30

-10

(b)

-40 2

6

4

8

Frequency (GHz) DB(|S(1,1) |) (R) Branchline

DB(|S(2,1) |) (L) Branchline

DB(|S(3,1) |) (L) Branchline

Large

0

0

-2

-5

-4

-10

-6

-15

-8

-20

-10

(c)

-25 2

4

6

8

Frequency (Ghz) DB(|S(2,1) |) (L) Large

DB(|S(3,1)|) (L) Large

DB(|S(1,1)|) (R) Large

Large SdB Back2Back

0

0

-2

-5

-4

-10

-6

-15

-8

-20

-10

(d)

-25 2

4

6

8

Frequency (GHz) DB(|S(2,1) |) (L) Lange Back2Back

DB(|S(3,1)|) (L) Lange Back2Back

DB(|S(1,1)|) (R) Lange Back2Back

Phase Difference 160 140 120 100 80

(e)

60 40 20 2

4

6

8

Frequency (GHz)

Figure 7.24 3 dB 90◦ Couplers and their characteristics: (a) Wilkinson splitter with 90◦ extension:

(b) branchline coupler: (c) 3 dB Lange coupler: (d) two back-to-back 8 dB Lange couplers: (e) comparison of phase performance.

7.4 Components

331

the load resistor is offset from the signal path, the phase is relatively flat over up to a 20% bandwidth (this can be extended by using multiple sections, however the loss increases proportionally), and the design can be adjusted to non 50  output impedances which can ease the problem of matching to a transistor. For octave and greater bandwidths, Lange couplers [1], Figure 7.24c, are extremely effective, the drawbacks are the small geometries that are required and the wire links between non adjacent “fingers.” One solution has been to produce the Lange on a separate substrate to the rest of the circuit, inserting it into pockets. Where the PCBs are soldered to the housing floor or a carrier then this can be done quite successfully. It is possible to wire-bond the links even on soft substrates, however soldering fine wires (the strands of 0.2/7 equipment wire are ideal) using solder paste and a microscope is also possible. A method used at 3 GHz involved winding several turns of wire around a needle and adjusting the spacing to match the pitch of the fingers. Applying solder paste to the appropriate area of the fingers, while holding the coil in place, the joints were made with a hot air soldering pencil. On alumina substrates wire bonding is the standard approach, although with processes that include air-bridges the links can be fabricated in situ. One solution [11] to the fine geometries is to produce two 8 dB Lange couplers “back to back,” Figure 7.24d. Wider bandwidths can be achieved in this way, at the expense of size, complexity and higher insertion loss.

7.4.3

Transistors Beware of headline power Figures! A certain amount of “gamesmanship” is played among power transistor manufacturers. Statements like “200 W CW Power Achieved,” need to be examined carefully, the key piece of data, “achieved in class A/B with a CDMA signal, under average power levels of 40 W,” is sometimes hidden away. There is no need to go over the exact specification arguments here, but in broad terms if anyone claims to be able to handle more that 40–45 W CW in a packaged device, alarm bells should start to ring. Very high PAEs and power outputs have been achieved [12], but these are in class B and over very narrow bandwidths. In broadband class A applications a GaAs FET’s efficiency and hence output power is greatly reduced due to thermal limitations. Although new wide bandgap devices offer higher power densities, it is actually current packaging technologies that limit the heat dissipation and hence the maximum output power. Wide bandgap transistors have maximum junction temperatures typically 75 ◦ C higher than GaAs, but the thermal resistance from the junction to the case tends to be higher as the active region of the GaN devices is smaller for the same RF power. Table 7.11 compares some of the main characteristics between 45 W GaAs and GaN packaged devices. It should be noted that the GaAs device has band-specific internal matching whereas the GaN device is intended for wideband operation and hence unmatched. Data sheets should also be examined with care as many parameters are quoted differently by manufacturers. For example, some quote linear gain, while others quote 1 dB compressed gain.

332

Microwave hybrid amplifier realization

Table 7.11 Comparison of commercial GaN and GaAs 45 W C band transistors Characteristic

GaN – CGH40045F

GaAs – TIM3742–45SL-341

Units

Gain P1 dB Drain source voltage (max.) Gate source voltage (max.) Operating voltage Operating current Thermal resistance Operating junction temperature Package size Manufacturer

12.1 @ 3.6 GHz 44 (typ.) 84 −10 to +2 28 3.5 2.8 225 20.5 × 6 Cree

11 @ 3.6 GHz 40 (min.) 15 −5 10 9.5 1.2 175 24.5 × 17.4 Toshiba

dB W V V V A ◦ C/W ◦ C mm

The choice of transistor technology essentially boils down to a “bucks/W” decision. This is more complicated than a simple comparison of transistor prices. The problem is simplest in the standard communications bands around 0.9, 1.9, 2.1 GHz, where devices are pitched at specific applications. LDMOS and GaN devices tend to run off + 28 V while most GaAs FETs are +10–12 V. Depending on the supply rail available the price of DC–DC converters may need to be included in the calculation and with GaAs and GaN a negative rail is also required. The application may not only specify a particular output power, but also the linearity at that level, in which case class of operation and technology will play a factor. The decision becomes harder away from the standard bandwidths. In this case the designer needs to look at the input and output impedances and their frequency dependence. Although improving, the ability of circuit models to predict large signal performance is not exact, and a number of manufacturers still only provide S-parameter data. Nonlinear data that does exist is only accurate over the frequency range and at the bias and power levels at which they were characterized, thus even if known they limit the design engineer’s ability to optimally use the device. Recent advances in active load– pull measurement systems [13] have enabled users to interactively characterize and test devices in synthesized impedance environments. Commercially, these have been limited to narrow band systems targeted at the communications frequencies. There are very little benefits in terms of performance for operating GaAs FETs pulsed. The primary limitations are the current capacity of feed networks and package leads, and the maximum breakdown voltage. Higher voltage devices such as LDMOS, silicon bipolar and GaN allow significantly higher power to be achieved within the average power package constraints. Pulsed radar and “L” band avionics are practically the only area that silicon bipolar still holds it own in the microwave region, although there is much work being done producing GaN devices and other new technologies such as high voltage vertical FETs [14]. The relatively low cost of silicon, the maturity of the processing, and the legacy systems still operating will ensure a requirement for silicon bipolar devices for some time.

7.5 Amplifier design

7.5

333

Amplifier design The amplifier is biased to provide the necessary power, gain and linearity performance. The output match is determined such that the necessary compression point, saturated power or PAE is achieved. This is done either from the device model by simulation or by direct measurement using load-pull systems. The input match may be such that the maximum amount of gain is achieved, a specific gain or set so that it provides a flat gain response with frequency. It may be necessary to deliberately mismatch the device at certain points to prevent that or subsequent stages from being overdriven. First, we will look at the topologies that are commonly employed and then we will take a more detailed look at how impedance matching can be realized for MHPAs.

7.5.1

Topologies The number of stages required in a line-up is a function of the overall gain, the technology used, the frequency range, and the topology. The gain of the output block determines the output power level from the preceding block and so on. In most cases it is important that the compression characteristics are determined by the final stage, thus the earlier stages do not limit the output performance of the whole amplifier. In the case of single ended line-ups, that is, when one device directly drives another, the determination of the required power from each stage is fairly simple. The output power of the driver equals the output power of the succeeding stage less the succeeding stage’s gain plus the required margin. Although at face value it may seem that the output device will be the largest power transistor available in the frequency range, in fact there are many benefits from choosing lower power devices and combining them in parallel to achieve the desired output power. Such reasons would include redundancy, bandwidth (higher power usually means lower output impedance hence more difficult matching), economics (output power is proportional to price, it may be more cost effective to standardize on one device and combine this is parallel), and spreading thermal loads. For example, a 1 kW 1–2 GHz CW amplifier has been constructed [15] from 128 10 W GaAs devices in parallel; one of the stated advantages is that a failure of any one device has no significant impact on the output power of the whole amplifier. If binary combining is used as shown in Figure 7.25a then the coupler loss is multiplied by the number of stages. This loss multiplication factor, n, is proportion to the number of output stages, s: n=

log s log 2

(7.11)

An alternative is to use a multiway combiner on the output as shown in Figure 7.25b. This will have less loss than the equivalent binary combiner and using, for example, N-way Wilkinson combiners without resistors it is possible to achieve wide bandwidths with simple if large layouts. The disadvantage is isolation; however this can be compensated for by using quadrature combining around the devices themselves. Single stage, multiway

334

Microwave hybrid amplifier realization

Figure 7.25 Parallel combining: (a) quadrature binary combination, output combiner losses increases with number of parallel stages; (b) quadrature stages combined using multiway combiner losses proportionally lower as the number of parallel stages increases.

combiners can be created [16] but these are nonplanar and thus more suitable for module combining. A disadvantage of using a balanced design is that the total output power is reduced by the insertion loss of the combiner. For narrow bands this can be as low as 0.2 dB, while for broader bandwidths the loss will increase. Some of the benefits such as spreading thermal loads have already been mentioned, for quadrature combiners there is a key

7.5 Amplifier design

335

additional benefit: match. In quadrature combiners (and dividers) there is a 90◦ phase relationship between the combining ports. This means that any reflected signals get dissipated in the load resistor, provided the phase and magnitude of the reflected signals are the same. The benefit of a good match of the combined channels, whatever their individual match (provided they are the same), is that deliberate mismatches can be introduced to achieve gain flattening across the amplifier bandwidth. This may be to ensure that the gain shape is flat, or prevent the device from being overdriven at one end of the band. Device gain reduces with increasing frequency; hence more drive power is required at higher frequencies for the same output power. In order to simultaneously achieve improved match and flat gain over wide bandwidths feedback can be employed. The theory has been well documented [17], for power amplifier applications series feedback is rarely used. With FETs shunt feedback must, by necessity, incorporate series capacitance as well as resistance to separate the gate and drain DC voltages. Both the capacitor and resistor will have parasitic inductance. This can actually be of benefit as by incorporating inductance in the feedback model, it can help to increase the RF impedance and increase the gain at the upper end. Leaded resistors, not normally used at microwave frequencies, can be specifically chosen to introduce the required inductance. Using shunt feedback, bandwidths of multiple octaves can be achieved. The feedback elements must be capable of handling the power levels of the signals travelling through them, but as they get larger to handle higher powers their parasitic components increase. One of the problems with introducing feedback to MHPAs is that of incorporating the feedback elements within the desired space. Not only are the gate and drains separated by several mm, but there is also usually a large flange. Sometimes it is possible to construct the feedback network in three dimensions, going over the top of the device rather than remaining planar. This approach is labour intensive and not suitable for automation. It also tends to be more susceptible to performance variations due to the lack of consistency in component forming and placement. Heat sinking of the feedback elements in the air or on top of the package is not easy. An alternative approach, suitable for narrower band applications has been outlined [18]; originally this was intended for low-noise applications to avoid the feedback introducing noise back to the input. However, it has the advantage for power applications of separating the feedback components and amplifying device. The circuit incorporates two λ/4 lines between the device and the feedback resistor. Thus, on a low-dielectric material (∼2.2) at 5 GHz, the feedback resistor can now be about 20 mm offset from the main track. The feedback arrangement is shown in Figure 7.26a. The low-pass filter is arranged such that there is a 180◦ phase shift at the operating frequency (or towards the top of the band in wider bandwidth applications), such that the feedback has little effect on the performance. At lower frequencies, the resistor is in band and adjusts the amount of feedback, thus reducing the bottom end gain. The device with feedback is matched with a transformer on input and output. The bias can be incorporated within the feedback loop Figure 7.26b. Although this approach improves stability over parts of the band, care must be taken to carry out a thorough stability analysis as at specific frequencies the feedback can actually cause oscillation. This approach also reduces the impact of different devices. The circuit of

336

Microwave hybrid amplifier realization

TLIN ID=TL2 Z0=25 Ohm EL=90 Deg F0=FF GHz

TLIN ID=TL1 Z0=100 Ohm EL=90 Deg F0=FF GHz

FF=6

TLIN ID=TL3 Z0=25 Ohm EL=90 Deg F0=FF GHz

SRC ID=RC1 R=RD Ohm C=C8 pF

CAP ID=C2 C=1000 pF

CAP ID=C1 C=10 pF

TLIN ID=TL4 Z0=100 Ohm EL=90 Deg F0=FF GHz

RF=800 C8=47

PORT P=2 Z=50 Ohm

PORT P=1 Z=50 Ohm

TLIN ID=TL1 Z0=ZB Ohm EL=LB Deg F0=3.5 GHz

SRLC ID=RC2 R=60 Ohm L=2 nH C=1000 pF

CAP ID=C3 C=10 pF

RES ID=R1 R=50 Ohm

SUBCKT ID=62 NET=”Feedback”

TLIN ID=TL2 Z0=ZB Ohm EL=LB Deg F0=3.5 GHz

(a)

PORT P=1 Z=50 Ohm

TLIN ID=TL4 Z0=Zip Ohm EL=Lip Deg F0=3.5 GHz

SUBCXT ID=63 NET=”mg0951p”

TLIN ID=TL3 Z0=Zop Ohm EL=Lop Deg F0=3.5 GHz

PORT P=2 Z=50 Ohm

(b)

Device Data_S21 & Stability

Gain and Stability

30

2

20

20

1.5

10

3

10

1

0

2

–10

1

0

–10 0.5

0.5

0 2.5

4.5

6

Frequency (GHz) DB(|S(2.1)|) (L) FLC 107WG

DB(|S(2.1)|) (L) MGF0951p

K( ) (R) FLC 107WG

(c)

–20 0.5

4

0 4.5

2.5

6

Frequency (GHz) K( ) (R) MGF0951p

DB(|S(2.1)|) (L) FLC 107WFBG

K( ) (R) FLC 107WGFB

K( ) (R) MGF0951pFB

DB(|S(2.1)|) (L) MGF0951pFB

(d)

Figure 7.26 Feedback amplifier: (a) feedback circuit; (b) device with feedback, bias feeds and simple input matching; (c) comparison of |S21 | and stability factor k between two devices; (d) comparison of gain and stability of the circuit with both devices.

Figure 7.26b was optimized for a Mitsubishi MGF0951 but also simulated with the Eudyna FLC107, Figures 7.26c and d.

7.5.2

Matching and stability Before starting to describe specific matching structures there are a number of common relationships that need to be established. From an amplifier point of view match is often described by return loss (RL), the ratio of incident to reflected signal in dB. When matching, reflection coefficient () and the actual impedances are more useful. The

7.5 Amplifier design

337

Table 7.12 , Return loss, transmission loss, and VSWR 

0.1

0.18

0.2

0.25

0.35

0.4

0.5

0.71

0.8

RL (dB) LT (dB) VSWR

20 0.04 1.22

15 0.14 1.43

14 0.18 1.50

12 0.28 1.67

9 0.58 2.1

8 0.76 2.33

6 1.25 3.00

3 3.0 5.85

1.9 4.44 9.00

relationships between these terms are given below and a summary of real values is given in Table 7.12. z − z0 = · (7.12) z + z0 R L (dB) = −20 log || ·

(7.13)

When a signal is reflected from a mismatch there is an associated loss in power transferred to the output; this loss, LT , in dBs can be related to the reflection coefficient:   L T = −10 log 1 − ||2 · (7.14) It can be seen from the table that in order to maximize the power output we must minimize the loss due to mismatch. Although this may seem trivial it is important to realize the implications of a particular match specification. The better matched a transistor the less power is required to meet a specification. Often an isolator will be added to the output of an amplifier in order to meet an output return loss specification, but this will typically have 0.5 dB of insertion loss and will do nothing in terms of translating the output impedance of the device to 50 . While there may be good system considerations for adopting an isolator (such as gain ripple on long cables), in MHPAs it loses hard won power. A solution based upon the best power match that can be achieved would be more efficient. Any real impedance can be matched to the system impedance at a single frequency, the difficulty is doing it over a bandwidth and all amplifier circuits need to have at least a limited bandwidth to account for changes in behavior with temperature. There are many combinations of matching elements able to move from an impedance on one part of the Smith Chart to another [19]. However, because they are largely treated as pure lumped elements their use in MHPAs is restricted to an understanding of the theory, in practice the matching elements used are complex. The most common matching elements are open and short-circuit stubs. Combined with a series transmission line these can match an impedance over a defined area, this is best explained graphically as in Figure 7.27. Microwave power device output impedances will typically lie within the shaded area, and so often an open circuit stub is the first matching element. When considering the effects of frequency one of the most useful considerations is the quality factor, or Q of the load. There are many uses of the term Q within the RF area and it is important not to get them confused. In this case, we refer to QT , the ratio

338

Microwave hybrid amplifier realization

PORT P=1 Z=50 Ohm

PORT P=2 Z=Zr Ohm

PORT P=1 Z=50 Ohm

PORT P=2 Z=Zr Ohm

Figure 7.27 Stub matching approaches. Left-hand side: short-circuit can match any impedance outside the shaded area; right-hand side: open-circuit can match any impedance within the shaded area.

of the reactance to the resistance of a series impedance, (for parallel admittance it is the ratio of the conductance to the susceptance). These can be plotted onto the Smith chart as Q curves. The closer matching networks stay to the real axis on the Smith chart the broader the bandwidth that can be obtained. The converse of this is that for any reactive matching there is a finite limit to the achievable bandwidth. Work into this relationship was conducted by Fano [20] who developed the theorem that where the source or load includes a reactive element the match cannot be perfect over a wide bandwidth no matter how many elements are used. For example, in the case of a parallel resistor-capacitor load (typical of most power devices) the formula is:  ∞ 1 π ln dω ≤ · (7.15) || RC 0 As  decreases, the value of the integral increases. For a finite frequency range the best achievable reflection coefficient,  min that can be achieved for a given load can be defined. This requires the use of another “Q” term, Ql defined as: Ql =

F0 · Fupper − Flower

min = e

−π Q l QT

·

(7.16)

(7.17)

Or, alternatively, the bandwidth we can achieve for a given  is 1 −π Fupper − Flower = = · F0 Ql Q T ln min

(7.18)

7.5 Amplifier design

20

4.435 GHz –15 dB

2.708 GHz –15 dB

339

7.292 GHz –15 dB

5.565 GHz –15 dB

Return Loss (dB)

0

–20

–40

–60

2

6

4 Frequency (GHz)

DB(|S(1,1)|) Single Section

8

DB(|S(1,1)|) Three Section

Figure 7.28 Comparison of bandwidth achieved from one and three-section quarter-wave transformers between the same resistive loads.

Due to increasing loss in the matching elements themselves, in MHPAs it is rarely worth going beyond three matching sections. This is not the case in filters where very high Q low-loss elements can be used and hence multi element structures are encountered. As a rough guide a single quarter-wave matching structure between impedances of a ratio of 6:1 can achieve a bandwidth of ∼22% (15 dB return loss). Using multiple sections this can be increased, e.g., matching the same load with three quarter-wave transformers, the bandwidth that can be achieved increases to ∼90%. Clearly, wider bandwidths can be achieved by reducing the impedance ratio; hence the benefit of using higher voltage and wide bandgap materials with higher output impedance and, conversely, why with technologies such as LDMOS with its high output capacitance, only narrower bandwidths can be achieved in the microwave region. Figure 7.28 shows the improvement from one to three sections, using ideal transmission lines and purely resistive loads. The impedance of the quarter wave matching line, ZT , is determined from the formula:  (7.19) Z T = (Z 0 × R L ) · For multiple sections one first needs to calculate the intermediate impedance between the sections, Zi(n) , [21] from: Z i(n) =  × Z i(n−1) lim N2 ,   N1 RL , = Z0

(7.20) (7.21)

where N is the number of steps, and RL the load resistance. In the case of the first step Zi(1) Z i(1) =  × Z 0 ·

(7.22)

340

Microwave hybrid amplifier realization

Figure 7.29 Single transformer matching space.

Using impedance transformers any impedance within the areas defined in Figure 7.29 can be matched. This assumes an infinite range of transformer impedances is available which, as has been explained earlier in microstrip, is typically limited to between 25 and 90 . Although the impedances can be determined mathematically [22], it is often simpler to put approximate values in a simulator and allow the optimizer to produce the best possible result within practical constraints. A number of other topologies offer impedance matching, without the size penalty of λ/4 structures. Similar performance to the λ/4 transformer can be achieved using two lines of impedances the same as the terminations [21], as shown in Figure 7.30. In this case the combined length of the two lines is less than that of a single λ/4 transformer with little sacrifice to the bandwidth. A similar version to this involves using a capacitively loaded λ/8 line. This is particularly useful if the load impedance that is being matched to has a capacitive reactance as this can be absorbed into the matching capacitance. Figure 7.31 shows the circuit for a λ/8 capacitively loaded transformer used to match 12.5 to 50 , where the capacitors and the line impedance were allowed to vary in the optimizer. If this approach were to be used to match to a load of 12.5 – j80.0 (a 0.4 pF shunt capacitor at 5 GHz) it would be possible to omit the shunt capacitor nearest the load and reoptimize Figure 7.31b, varying only the line impedance and the port 1 capacitor. A further advance on this is to replace the output shunt capacitor with an o/c stub, Figure 7.31b. In summary, common broadband matching strategies are: r compensated matching networks – at the cost of input match; r resistive matching networks – at the cost of loss in gain;

341

7.5 Amplifier design

TLIN ID=TL2 Z0=Z2 Ohm EL=A12 Deg F0=5 GHz

TLIN ID=TL1 Z0=Z1 Ohm EL=A12 Deg F0=5 GHz

PORT P=1 Z=Z1 Ohm

LOAD ID=Z1 Z=Z2 Ohm

Z1=50 Z2=8.3 A12=20.45

Shortened Double Transformer 0

Return Loss (dB)

–10

–20 –30

–40

DB(|S(1,1)|) Double Transformer

–50 –60 3

4

5

6

7

Frequency (GHz)

Figure 7.30 Double short transformer matching.

r negative feedback used to flatten gain, improve match and stability, at the expense of gain (and noise figure, although less important to MHPAs); r balanced amplifiers – can mismatch input of devices to flatten gain while still maintaining overall input match; r distributed amplifiers – a number of stages in cascade, reduced gain and hence poor efficiency, large surface area. Most amplifier textbooks describe the use of stability factor, k, and the use of stability circles to define the unstable impedance areas, i.e., those areas where if presented to the device there is the potential for oscillation. Although stability analysis should be carried out up to the maximum operating frequency of the device, in practice the data available will rarely go below 500 MHz and the likelihood of oscillation decreases as the frequency increases due to increasing circuit losses. Therefore, it is necessary

342

Microwave hybrid amplifier realization

PORT P=1 Z=50 Ohm

TLIN ID=TL1 Z0=59.8 Ohm EL=22.5 Deg F0=5 GHz

CAP ID=C2 C=0.9994 pF

LOAD ID=Z1 Z=12.5 Ohm

PORT P=1 Z=50 Ohm

TLIN ID=TL1 Z0=61.67 Ohm EL=22.5 Deg F0= 5 GHz

CAP ID=C2 C=1.02 pF

CAP ID=C1 C=0.2 pF

(a)

LOAD ID=Z1 Z=12.5 Ohm

TLOC ID=TL2 Z0=25 Ohm EL=38.21 Deg F0= 5 GHz

CAP ID=C1 C=0.4 pF

(b)

TLIN ID=TL1 Z0=61.86 Ohm EL=22.5 Deg F0= 5 GHz

PORT P=1 Z=50 Ohm

LOAD ID=Z1 Z=12.5 Ohm

CAP ID=C1 C=0.4 pF

(c)

Capacitively Loaded Line 0

Return Loss (dB)

–10 (d) –20

–30

DB(|S(1,1)|) Cap Load Eigth Wavelength DB(|S(1,1)|) Fixed Load Capacitance

–40

DB(|S(1,1)|) Open Circuit Stub

–50 3

4

5 Frequency (GHz)

6

7

Figure 7.31 Capacitort-loaded transformer matching: (a) optimized elements; (b) fixed capacitance; (c) open-circuit stub; (d) comparative performance of (a) to (c).

to design circuits which will inherently ensure stability at the low-frequency end and provide stable impedance terminations in the range up to where the |S21 | > 3 dB. To ensure low-frequency stability the main approach is to resistively terminate the bias networks. This may involve using large inductors in parallel so that the DC can still pass. It is important to remember that the AC coupling capacitors used between RF stages tend to have values in the pF range and that these will effectively be open circuits in the MHz region where transistors will have very high gain. Feedback can be applied between the gate and drain bias feeds away from the active RF circuits [22]. Where large inductors are used it is important to contain the RF fields as these can become a source of oscillation through coupling. Ferrite beads can be particularly useful in this respect. A low-value resistor in series with gate will raise the gate impedance at a cost of gain. To compensate for this a capacitor can be inserted in parallel to bypass the resistor at the operating frequency. Isolators have a DC path to 50  and hence are very effective for improving low-frequency stability. However, care should be taken to ensure that at

343

7.5 Amplifier design

8 to 10 GHz Isolator Match 0

–5

–10

–10

–20

DB(|S(1,1)|) (R) X Band Isolator

–15

–20

–30

DB(|S(2,1)|) (L) X Band Isolator

0

3

6

9

12

15

–40 18

Frequency (GHz)

Swp Max 18 GHz

Input Return Loss (dB)

Insertion Loss (dB)

8 to 10 GHz Isolator 0

S(1,1) X Band Isolator

Swp Min 0.01 GHz

Figure 7.32 Typical isolator performance. Note that away from the passband there are points where || is large.

higher frequencies the isolator does not present an unstable impedance, Figure 7.32 shows the impedance presented by an X-band isolator.

7.5.3

Internally matched device amplifiers For specific frequency bands, where volumes are high enough, manufacturers have developed tailored devices. Within these device packages several transistors are combined and some basic prematching incorporating the bond wires and shunt capacitors has been implemented. These are typically more cost effective at the target frequencies than can be produced using unmatched packaged devices as the matching is implemented within the package before the package parasitics. This may be best understood by considering the input impedance of the device. At the chip level this can be very simply approximated by a series resistor Rg and capacitor Cgs to ground. If the device is packaged this input circuit becomes much more complex because of the packaging parasitics. One suitable matching circuit for the Rg – Cgs load would be a series inductor and a shunt capacitor (arranged moving away from the device). This fits in well with the assembly of the chip into a package as the first element is the bond wire (series inductance) followed by the bond pad (shunt capacitive). Thus, by appropriately choosing the dimensions of these elements an improvement in the match can be obtained using parts already necessary to connect to the chip. Some internal matching is only intended to ease the job of matching the device, they raise the input or output impedance just enough to assist practical discrete matching. In other cases, particularly as frequency increases, the impedance is taken close to 50 . Another version of this solution is commonly known as “Pallet Amplifiers.” Here, the transistors are packaged as normal, but the device manufacturer takes the extra step of mounting them on a substrate (usually metal backed) with bias and matching circuits included. These are especially popular for radar bands, and the advantage that

344

Microwave hybrid amplifier realization

the manufacturers have is that they can select devices such that pairs have very similar characteristics.

7.5.4

Combining Different combining structures have been described earlier in the text. Besides the obvious benefit of achieving higher power, combining: r r r r

spreads the thermal dissipation; introduces redundancy; improves match; increases reverse (reflected) power handling.

A specific application of combining where it is used extensively is known as “corporate combining” [23]. In this case the corporate management pyramid structure is turned on its side so that the number of devices in each rank increases as the output is approached. In a specific version each device has identical performance and hence, there is a high degree of repeatability in the manufacture and tuning, which should introduce economies of scale. The number of devices in each rank is dependent on the gain of each stage. Combining can also be utilized to improve linearity. In the Doherty amplifier [22] one device is the main amplifier, on all the time, while the second device is arranged such that it only operates to handle the peaks in input signal.

7.5.5

Module size/system integration It is sometimes impractical to achieve the desired output power from a single module. This may be due to performance issues such as cooling or it might be due to the difficulties of testing. When a large number of devices are used within a module it is often difficult to establish the actual performance of an individual part. If the performance required is close to the boundary of what is achievable then it is critical that each part can be setup and proved to be working at its optimum. Offset against this is the additional losses that occur through interfacing modules together. Fault finding is easier in a modularized system. A module based approach can be a useful stage in system development, with changes easier to implement than in a highly integrated unit. For new product designs risk can be reduced by utilizing a building block approach. This can be applied both to reusing existing module designs in a new application or to developing new modules; different individuals can develop separate modules independently, which can be proved in isolation, hence speeding up development. Taken on a materials cost basis, the modular system is more expensive than a discrete design. However, as the power required increases, the benefits of a modular approach become greater.

7.6 Biasing and control

345

Table 7.13 Gate and drain bias circuit requirements Gate biasing circuit

Drain biasing circuit

Maintain constant voltage, Vg Supply required gate current, Ig

Maintain constant drain voltage, Vd . Supply a drain current, Id , up to that level required under maximum input drive. Provide low-frequency terminations to reduce the device gain in this range (improve stability). Isolate the supply rail from RF signals.

Protect the gate from damage by limiting Ig when the device goes into breakdown or forward bias. Stabilize the device in the presence of a negative input resistance. Provide low-frequency terminations to reduce the device gain (improve stability). Isolate the gate from signals coming from the drain bias circuit.

7.6

Biasing and control Too often the issue of transistor biasing is not given the priority it deserves, and leaving it towards the end of the chapter should not be confused with lack of importance. Correct biasing is application specific, from the relatively simple to temperature compensating, to envelope tracking. Classes of operation are dealt with in detail in Chapter 4, and it should be clear that different applications require different behavior from the amplifier, or put another way some characteristics are not always as critical. In radar applications, for example, linearity (where the amplitude and phase of an output signal from the amplifier is directly proportional to the input signal) is not a significant characteristic, power is the key driver. So in this case the amplifier is typically biased in class C and as a result there is a nonlinear relationship between input and output power. A limited amount of power control may be required, which can be achieved by adjustment of the supply rail. In another application where linearity is very important the supply rail may be adjusted to compensate for changes in signal level, but this is then a dynamic change as opposed to a set change. Some requirements of bias networks are common; device protection and stability. The main requirements of transistor bias circuits are summarized in Table 7.13. All rules are made to be broken, e.g., gate or drain voltage may be adjusted with temperature to provide active compensation (gain is inversely proportional to temperature). The isolation requirement between gate and drain also extends between transistors. Not only should the devices be isolated in terms of interference but also a fault in one device should ideally not affect the performance of others. Linear gain is relatively insensitive to drain voltage, but output power and linearity are strongly related to drain voltage. The basic bias configuration is shown in Figure 7.33a. The gate voltage, Vg is set by the potential divider R1 and R2 ; the drain voltage, Vd is provided by a fixed voltage “infinite” current source, the actual current drawn being determined by Vg . The Vd required will normally be specified by the device manufacturer. It needs to be such that at maximum output power under any load condition, the maximum breakdown voltage will not be

346

Microwave hybrid amplifier realization

–Vg

+Vd

+Vd

Rd

R1

R2

Rg

(a) (b)

+Vd

+Vs Fuse Mute

Drain Voltage Control

Current Sense

Zener –Vg

Voltage Regulator

DC–DC Converter

Sequencing Circuit

Gate Voltage Control

Noise Reduction (c) Figure 7.33 Transistor biasing: (a) basic bias arrangement; (b) bias compensation arrangement; (c) “bells and whistles” bias arrangement.

exceeded. Thus, it is possible to increase the recommended Vd if it can be guaranteed that a good load match will always be maintained, (usually this will only be the case when driving straight into an isolator). Alternatively, fold-back circuits are employed such that the output drive level is reduced if the load match degrades. The circuit in Figure 7.33a has a number of problems; first, there is no isolation of the drain from other devices so if that transistor fails the whole supply rail will be affected. Second, the gate of the transistor draws current, which varies with input drive level, and so the Vg will vary, this in turn causes Id to change. At low-signal levels the Ig is very low, (μA), and consists of leakage current. The gate is a Schottky diode and so when forward biased or when the reverse voltage breakdown is exceeded current will flow, thus the gate supply

7.6 Biasing and control

347

must be able to both sink and source current. In the case of reverse voltage breakdown the current increase would be dramatic if not protected by a resistor. Typically, the device manufacturer will recommend a gate resistance value, e.g., Toshiba recommends 28  maximum for TIM3742–45SL, while Cree suggests 4.7  for CGH35060F. It must be remembered that the recommended gate resistance includes the resistance in the DC path, not just that in the bias network. Hence, if this potential divider network is used with high-power FETs (∼40 W) with a typical value for Rg of ∼28 , and a negative rail of –5 V is used and Vg = −1 V, then the total series resistance of the divider chain will be of the order of 35  and draw about 150 mA of current. Often, the gate current is forgotten in PA design and the resultant “starving” of gate current will lead to reduced output power from the devices. The circuit in Figure 7.33 (b) has two advantages over 7.33a. First, the op-amp is a low-impedance source which can supply the current required and, second, it senses Id and adjusts Vg so that a constant Id is maintained. An important feature of the bias supply to FET devices is the correct sequencing of the rails. Vg must be established before the drain voltage is applied to prevent excess Id from being drawn. During bias switch on, as Vd rises so the gain and match of the device changes and the possibility of oscillation arises. In many text books, it is said that the correct sequence for biasing up a device should be as follows: 1. 2. 3. 4. 5.

Terminate the input and output in 50 . Apply negative bias to the gate, increasing until the pinch-off voltage, Vp , is reached. Increase Vd to the required level. Increase Vg (make less negative) until the desired Id is reached. Apply the RF signal.

The switch off routine is the reverse. While this is a sensible procedure for the lab and devices under evaluation, in practice there is little control over when the RF is applied (if this is critical for a device then the amplifier will need to interface with an input power control loop). The complexity of a bias circuit that first takes the Vg to Vp and then to the required Vg , is only necessary if there are problems with the power supply providing the required Id instantaneously. Some power supplies have a short-circuit sense trip circuit, in other cases too much inductance in the supply lines can induce voltage spikes during switch on. This sequencing requirement is one reason why often amplifiers have a single supply rail and for a voltage inverter circuit to be included. Bias circuits can be very complex, Figure 7.33c shows in block formation the parts of a comprehensive bias circuit, with a single primary voltage source Vs . The combination of a fuse and a Zener diode protects against reverse and over voltage. The Zener rating is dependent upon the fuse type. The fuse may be omitted if the primary power supply has a short-circuit trip. Self-resetting fuses are available6 (nonlinear thermistors), although these can cause confusion with some system monitoring circuits (appears as an intermittent fault). Fuses may be specifically excluded due to maintenance issues; however it is advisable for some form of input voltage protection to be included. 6

E.g., PolySwitch from Raychem, www.circuitprotection.com.

348

Microwave hybrid amplifier realization

DC–DC converter: required to produce the negative voltage rail. Available as single chip devices only requiring an external resistor and capacitor, this is a switching circuit and so it produces voltage ripple on the supply, which in turn modulates Vg and the hence the RF signal. When observed in the frequency domain it can be seen as sidebands on the RF signal. For filtering it is advisable that the switching frequency be as high as possible. Voltage regulator: it is important that the Vg is stable; if the DC–DC converter stability is not adequate a linear regulator can be incorporated. This can be configured to include temperature compensation. The regulator will provide some filtering of the voltage ripple. Sequencing circuit: provides a control signal to the drain voltage control, including a sufficient delay. It is important that this control signal is failsafe, i.e., in the event of a loss of the negative supply the drain will be quickly shutdown. Drain voltage control: in its simplest form this may consist of a “pass transistor” with appropriate biasing for the control. However, there are also low-drop out (LDO) voltage regulators with high current capability (∼7 A), adjustable voltage output, enable/control pins, and even an error flag that signals the output voltage has dropped below the expected value. One note of caution, these devices have a minimum load current and must be correctly capacitively decoupled to prevent oscillation. The enable line can be coupled to an external control to provide a mute function for the amplifier, but the switching time is typically slow (of the order of hundreds of μs) and thus not suitable for most modulation schemes. Where modulation is required a solution is to modulate the gate between Vg and Vp , however care must be taken not to introduce any spikes which exceed the gate breakdown voltage. Current sense: typically this will be a low-ohmic resistor, it is important that Vd is not greatly affected by the changing Id . Noise reduction: as discussed earlier the negative voltage generation creates spurious signals which impose directly on the wanted signal. This can cause severe problems in some circumstances. The noise can be reduced by filtering or in the extreme by active cancellation. Gate voltage control: the variation in transconductance and hence Id can be wide between devices. It is recommended that for class A operation Id is set to 50% of Idss (saturated Id – measured with a reduced Vd and a zero Vg ), typically for power devices this will be provided on the packaging. Vg is used to set the operating Id , so a method of adjustment needs to be incorporated. It is necessary to introduce the bias to the device without detrimentally affecting the RF performance. In the case of the drain the DC resistance of the feed must be kept as low as possible. For a high-power transistor this is especially important as the voltage drop along the feed line will reduce the output power. In contrast the RF impedance of the feed must be high. Therefore a good solution is to introduce the bias at a lowimpedance point as close to the device as possible. An alternative is to use short-circuit matching stubs, but replace the link to ground with a decoupling capacitor and join the inductor at this point. For lower microwave frequencies this can be done with several turns of 0.5 mm wire on a 2.5 mm former (five turns tightly wound is ∼40 nH and

7.6 Biasing and control

349

<0.01 ). Increasing the spacing between the turns decreases the inductance and the capacitance between the turns. The inductor can be tested using an SMA gold-plated flanged connector by soldering one end of the coil to the flange and the other to the trimmed center pin. Observing the S11 response on a VNA will show any resonances in the frequency band, altering the spacing of the coils can move these in frequency. The impedance of such a coil varies from ∼250  at 1 GHz to over a thousand at 5 GHz (ignoring any resonances). This method is suitable for broad bandwidths, however its repeatability is poor and it is not suitable for automated assembly. Air wound coils can be purchased from a number of suppliers, using standard compact footprints. As the frequency increases the number of turns required to make a high-impedance inductor decreases and at × band, single loops of wire may be sufficient. For narrow-band designs, a popular solution is to supply the bias through a 90◦ shortcircuit stub. This appears as an open circuit at the junction with the main line. In order to introduce a bias voltage the short must be open circuited at DC, which can be achieved by a number of methods e.g., 90◦ open circuit stub, radial stub or coupling capacitor, as shown in Figure 7.34. The relative bandpass characteristics can be seen in the graphs in Figures 7.34d and e. The bias voltage would be introduced at the points marked with a star. More complicated versions using several sections can be created for broader bandwidth characteristics. The impedance and length of the stubs may also be altered to assist with the device matching. Where the λ/4 lines are not wide enough to handle the DC current they can be selectively plated up or thicker wire soldered to the track to increase the DC current capacity without impacting the RF performance significantly. This wire can be “looped” off the board at the short-circuit point (star) to link to the bias feed or go to extra low-frequency decoupling. Not shown is the in-line DC blocking capacitor that is required to isolate the DC from the preceding and following stages. Bias can be introduced at the isolated port in Branchline couplers. The isolation resistor must be AC coupled and DC blocking in the output line must be able to handle twice the RF power of the standard configuration. This is not normally done on the input unless the devices are well matched as Vg is used to set Id . Besides analyzing the behavior of the devices over the operating frequency range it is important to consider what happens out of band, particularly at the low-frequency end. The gain of transistors increases dramatically as frequency is reduced and so it is important that signals (and noise) are correctly terminated. As discussed earlier the capacitors used for decoupling RF signals tend to be in the range of 1 to 20 pF for microwave frequencies, larger capacitors have significant parasitic inductance and multiple resonances. Thus, where wide bandwidth decoupling is required multiple capacitors of different types are used. In addition, the modulation bandwidth also needs to be considered. The increase in modulation bandwidth has increased the complexity of the bias circuit decoupling. In order to minimize the impact on the modulating signal it is necessary to present a constant impedance to these low frequencies. However, it may also be necessary to filter out specific frequencies (such as power supply switching) and to provide a high impedance to the RF signal. For non class A operation the supply must be able to provide the transistors with an alternating current as the devices are turned on and off by the RF signal. This must be done without also modulating the supply voltage as change

350

Microwave hybrid amplifier realization

Bias feed point

(a)

(b)

(c)

Bias Tees Broadband

0

–0.5 Insertion Loss (dB)

Insertion Loss (dB)

–5 –10 DB(|S(2,1)|) Bias Tee Capacitor

–15

DB(|S(2,1)|) Bias Tee OC stub

–20

DB(|S(2,1)|) Bias Tee Radial Stub DB(|S(2,1)|) Bias Network

–25 –30

Bias Tees Passband

0

0

2

4

6 8 Frequency (GHz)

(d)

5 GHz –0.04 dB

5 GHz –0.11 dB

–1 –1.5

DB(|S(2,1)|) Bias Tee Capacitor

–2

DB(|S(2,1)|) Bias Tee OC stub DB(|S(2,1)|) Bias Tee Radial Stub

–2.5

DB(|S(2,1)|) Bias Network

10

12

–3

3

4

5 Frequency (GHz)

6

7

(e)

Figure 7.34 Basic bias feed networks: (a) capacitor; (b) open-circuit stub; (c) radial stub; (d) broadband performance of bias networks; (e) passband performance of bias networks.

here will alter the transfer characteristics of the device and cause distortion. Analysis of bias decoupling has been well covered [22]. The design of the constant impedance bias networks can be treated as a filter problem. Figure 7.35c shows how the low-frequency impedance varies with frequency between a simple decoupling circuit and one designed for constant impedance. The parasitics of the components can be absorbed into the extra elements, for example the 0.5 nH parasitic inductance of the 10 nF capacitor shown in Figure 7.35b can be included in the 4.1nH inductance in Figure 7.35a. The effect of the low-frequency impedance can be seen in the sidebands of digitally modulated signals such as W-CDMA. Memory effects are a phenomenon in the time domain due to thermal transients and charge storage causing the bias conditions to change. It is quite common to see an arrangement of, for example, 1 pF, 1 nF and 10 μF capacitors on the end of a bias line. Very large decoupling values may be used to reduce spikes due to inductance in bias lines, especially when using test jigs. For below band

7.6 Biasing and control

ID = L2 L = 14 nH

ID = L1 L = 1e4 nH

PORT P=1 Z = 50 Ohm

IND CAP ID = L3 ID = C2 C = 8.2 nF L = 4.1 nH

RES ID = R2 R = 1.2 Ohm

RES ID = R1 R = 1 Ohm

(a)

CAP ID = C1 C = 1e4 nF

IND ID = L3 L = 0.5 nH

RES ID = R3 R = 1.2 Ohm

CAP ID = C3 C = 10 nF

PORT P=1 Z = 50 Ohm

(b)

CAP ID = C1 C = 1e4 nF

CAP ID = C1 C = 1e4 nF

(c)

Impedance

10000

16.5 MHz 0.83 Ohm

⎜Z⎜(ohms)

100

1

.01

⎜ZIN(1)⎜ (Ohm) ConstantZbias ⎜ZIN(1)⎜ (Ohm) SimpleDecoupling

.0001 .0001

.01

25 MHz 0.0074 Ohm

1 Frequency (MHz)

71.1 MHz 0.0013 Ohm

100

Figure 7.35 Constant impedance bias circuit: (a) constant Z bias; (b) simple de-coupling;

(c) impedance variation with frequency.

351

352

Microwave hybrid amplifier realization

signals it is often advisable to include a resistive termination. In the gate bias this can be applied in series for smaller devices and incorporate the gate limiting resistor. In the drain circuit this is not practical due to the high currents. Instead, the resistor is placed in series with one of the high value capacitors. Another factor to consider when operating devices in test fixtures run directly from laboratory power supplies is the resistance between the PSU and the device, especially if discrete bias “tees” are used. A total resistance (RPS ) of up to 1  would not be unusual and this could reduce the saturated output power by up to 0.5 dB. The highest power devices tend to be biased in higher efficiency classes than A, and as a result Id increases with drive power, although the PSU output voltage remains constant the voltage on the device will drop by Id × RPS . The changing bias voltages during switch-on may lead to oscillation. This can be seen by touching the circuit and killing the oscillation after the bias has stabilized. It may be possible to stop this oscillation by speeding up the rise time of Vd . If the oscillation frequency is substantially below the band of operation, additional decoupling of the bias lines may help. If the oscillation occurs above the operating band, a “lossy” stub may be required on either the input or the output. The big problem arises when the oscillation is within the operating region. This means that either the input or output matching impedance is presenting a load that is in the unstable region of the transistor’s operation, which is changing as the device Vd ramps. It is important to determine whether other stages are contributing to the unstable conditions. If there are a number of stages in series without any isolating elements then these will also present changing impedances during power on. Once it has been established which stage is causing the problem, a more complicated bias sequence may be required. Instead of Vg being set to the required voltage for operation it is set to Vp until the drain voltage has had time to establish, Vg is then adjusted to the value for the required Id . It is necessary to check for oscillations during switch on over the operating temperature range of the device, particularly the lower end where the gain is highest.

7.6.1

Control and interfacing There are a number of system functions that can be handled within the amplifier and it may make practical and economic sense to include them. Be aware though that the more customized an amplifier becomes, then costs rise, reliability falls, and the harder it is to find direct replacements. There is also a danger in adding features “because we can” rather than driven by need. On the other hand there are a number of system components that can be included within an amplifier saving size, weight and cabling. It may be advantageous from a system point of view to be able to shut down an amplifier. This can be done by removing Vd , or applying Vp to the gate, or by including an RF switch in the input of the module. This latter solution is applicable where very fast modulation of the amplifier is required, otherwise the other solutions can be provided with little extra cost. A disadvantage of using a switch at the input is that the amplifier remains on and hence is still amplifying noise. For this reason in some pulsed systems Vd is removed between pulses, to “quieten” intrapulse noise.

7.7 Tuning techniques

353

It may be useful from a system perspective to monitor the power levels at the input and output of the amplifier. Simple couplers can be incorporated within the amplifier, Figure 7.22. In the past it was common to include a diode detector circuit and return a voltage proportional to signal level. There are now single chip solutions up to 6 GHz.7 An alternative way to measure output power is to observe the current being drawn by the RF transistors. This has the advantage of not requiring any additional “real estate” in the RF section, putting the additional components in the bias side which tends to be lower cost. It is not as accurate and may change with time, however if the requirement is for a simple indicator it may suffice. It can also double as a device “health check”. In some amplifier systems the output coupler is used to monitor both the forward and reflected power. The signal from the reflected power monitor can be used to shut down the amplifier or reduce the output power if the amplifier is susceptible to damage from reflected signals. It may just be used as a warning indicator, for example that an antenna has not been connected, if the amplifier can withstand reflected power. If an isolator is fitted, then rather than having a load which is capable of handling full power temperature sensor can be fitted to the load, shutting down the amplifier in the event of excess heat (equivalent to excess reflected power). The purpose of the built in test (BITE) is to enable quick fault assessment and repair. This test should enable repair to be made to the appropriate level of replacement, but no further. There would be little point identifying to the repair technician which particular transistor had failed if they can only replace the module. The information on which transistor has failed may be required back at the factory, but in that case it is also possible to lift the lid and see inside (which will need to be done to replace the transistor anyway). Where individual transistor monitoring does pay off is in fault prediction. Looking at module performance as a whole it may be difficult to see the changes in one device. Monitoring the gate and drain currents (at known RF power levels) may anticipate device failure. However, this requires a sophisticated system and is probably only necessary where an extremely high level of availability is essential.

7.7

Tuning techniques Differences exist in the transconductance and the parasitic capacitances, Cds and Cgs , across semiconductor wafers, and even larger variations occur between them. As a result of this as well as other factors such as variations in mechanical placement, etching tolerances, passive component spreads, etc., it is frequently necessary to tune an amplifier to make it meet specification. Mechanically variable high Q capacitors are available for use in the lower GHz region; however, they are expensive and more sensitive to vibration. Some companies provide chip capacitors stuck to nylon rods that can either be pressed down on assembled capacitors to increase the effective capacitance or add capacitance to a circuit some place. Obviously, if this has a negative effect it implies that the capacitance needs to 7

E.g., Analog Devices, AD8363.

354

Microwave hybrid amplifier realization

Links

(b)

(a)

(c)

(e)

(d)

(f)

Figure 7.36 Common tuning methods: (a) and (b) short-circuit stub; (c) and (d) line extension; (e) open-circuit stub; (f) tuning array.

References

355

be decreased. If provision is made in the layout then capacitor positions can be altered, sliding them up and down a transmission line. Chip inductors are not easy to tune, but air wound inductors can usually have their spacing increased or reduced. Transmission lines have two parameters that can be altered, impedance and phase, which correspond to width and length, respectively. These can be changed by either an additive or subtractive process. Altering the width is usually the easiest change to make. There are different approaches for hard and soft substrates. Traces on hard substrates are difficult to remove without the use of special tooling, while a simple scalpel and a soldering iron (the adhesion of the tracks to the substrates reduces with heat) are all that is needed for soft substrates. Figure 7.36 shows some commonly used tuning approaches. For hard substrates the links are wire bonds. It is often easiest to bond all of the positions during initial build and then remove the links as necessary during tuning. For soft substrates it is simpler to add the links by soldering. It may be necessary to remove some tracks after links have been made, for example in Figure 7.36d). The tuning array in Figure 7.36f may seem like a “scatter gun” approach but it is very useful, especially in early prototypes. The tuning used can be accurately identified and then incorporated in revisions to the design. Tuning disks or squares can be either custom made in a variety of sizes or cut from copper shim. A favourite of many engineers is to use the bits of device leads (cut off in production) on cocktail sticks to move them about. In addition to solder and wire bonds, conductive paint has been used to link to tuning pads, however, there does not appear to be any data on the long term reliability of this approach. A final technique is to use dielectric overlays. These are layers of dielectric placed over the tops of circuit elements, particularly coupled lines.

References 1. J. Lange, “Interdigital stripline quadrature hybrid,” IEEE Trans. Microw. Theory Tech., vol. 17, pp. 1150–1151, Dec. 1969. 2. N. Sinnadurai, “Plastic packaging is highly reliable,” IEEE Trans. Rel., vol. 45, pp. 184–193, June 1996. 3. J. Schultz-Harder and A. Meyer, “Hermetic packaging for power multichip modules,” European Conference on Power Electronics and Applications, 2007, pp. 1–10. 4. E. F. Johnson, “Technique engineers the cavity resonance in microstrip housing design,” Microw. Syst. News. Commun. Feb. 1987. 5. P. Aaen, J. Pla, and J. Wood, Modelling and Characterisation of RF and Microwave Power FETs, Cambridge University Press, 2007. 6. B. Rosas, “50 GHz End Launch Connector Test Boards,” Horizon House, Microw. J., Mar. 24, 2008. 7. S. B. Durgin, “Understanding the basic thermal properties of SMT devices” www. ims-resistors.com/IMSthermalnote.pdf [Online] [cited: June 4, 2009.] www.ims-resistors. com. 8. V. F. Perna, The RF Capacitor Handbook, ATC Corp. pp. 2–5-17. 9. C. Bowick, RF Circuit Design, Newnes, 2008.

356

Microwave hybrid amplifier realization

10. F. Giannini, C. Paoloni, and M. Ruggieri, “ very broadband matched termination utilizing nongrounded radial lines,” 17th European Microwave Conference, 1987. 11. H. J. Louw and J. R. Nortier, “Cascaded Lange couplers,” Microw. J., Nov. 1989. 12. P. Wright, A. Sheikh, C. Roff, P.J. Tasker, and J. Benedikt, Highly efficient operation modes in GaN power transistors delivering upwards of 81% efficiency and 12 W output power, IEEE MTT-S Int. Symp. Dig., pp. 1147–1150, June 2008. 13. D. M. FitzPatrick, T. Williams, J. Lees, J. Benedikt, and P. J. Tasker, “Large signal device characterisation using active load-pull for improved MMIC design,” IET Seminar on RF and Microwave IC Design, pp. 1–7, 2008. 14. B. Battaglia, D. Rice, L. Phuong, B. Gogoi, G. Hoshizaki, M. Purchine, R. Davies, W. Wright, D. Lutz, M. Gao, D. Moline, A. Elliot, S. Tran, and R. Neeley, “A novel silicon high voltage vertical MOSFET technology for a 100 W L-band radar application,” 38th European Microwave Conference, 2008. 15. D. FitzPatrick, “1 kW, “L” Band, CW Solid State Amplifier for Pulsed Radar Immunity Testing,” IMS 2005 MicroApps, 2005. 16. D. I. Stones “A UHF 16-way power combiner designed by synthesis techniques,” Microw. J., June 1989. 17. B. S. Virdee, A. S. Virdee, and B. Y. Banyamin, Broadband Microwave Amplifiers, Artech House, 2004, pp. 133–135. 18. J. J. Pan and M. J. Russell, MESFET amplifier with RF feedback gives high performance, low noise,” Microw. Syst. News, June 1983. 19. R. Rhea, “The Yin–Yang of matching: part 1 – basic matching concepts,” Summit Technical Media, High Frequency Design, pp. Mar. 16–25, 2006. 20. R. M. Fano “Theoretical limitations on the broadband matching of arbitrary impedances,” J. Franklin Inst., Jan. 1950. 21. R. Rhea, “The Yin–Yang of matching: part 2 – practical matching techniques,” Summit Technical Media, High Frequency Design, pp. 28–40, April 2006. 22. S. C. Cripps, RF Power Amplifiers for Wireless Communications, 2nd Edn., Artech House, 2006. 23. E. D. Ostroff, M. Borkowski, and H. Thomas, Solid State Radar Transmitters, Artech House, 1985.

8

Monolithic power amplifiers Inder Bahl Cobham Sensor Systems

8.1

Overview of MMIC power amplifiers Over the past 30 years, microwave power amplifier (PA) technology has gone through a significant evolution to meet necessary requirements such as high-power, high-efficiency and high-voltage operation for lower-cost solutions, circuit miniaturization, improved reliability and high-volume applications. PA component size and weight are prime factors in the design of electronic systems for satellite communications, phased-array radar (PAR), electronic warfare, and other airborne applications, whereas high-volume and low-cost drive the PAR and consumer electronics market. Monolithic microwave integrated circuit (MMIC) power amplifiers are the key to meeting these requirements. In MMICs all active and passive circuit elements are fabricated together on a semiinsulating GaAs substrate. MMIC amplifiers are integral parts of most commercial and military systems. For radio frequency integrated circuit (RFIC) wireless applications, several Si-based device technologies including bipolar, CMOS, BiCMOS and SiGe HBT are being pursued to obtain an optimum solution in terms of performance and cost for low-power applications. In the Si based processes, Si wafers are larger and cheaper than GaAs wafers but the fabrication involves a relatively larger number of process steps. RFICs are generally partially matched and require off-chip elements to complete the matching. Both RFICs and MMICs have low Q passives, expensive nonrecurring engineering cost, long development cycle time and in MMICs no post manufacture tuning or “tweaking” to obtain the optimum performance. Power levels in an MMIC approach are much higher than those that can be realized using an RFIC technique because of breakdown voltage considerations. Therefore, Si based RFICs will not be included in this chapter.

8.1.1

Brief history of MMIC power amplifiers Building upon the success of microwave integrated circuit (MIC) technology, a new monolithic microwave GaAs semiconductor-based technology was introduced in the mid 1970s. It was in 1976 when Pengelly and Turner [1] applied the monolithic approach to an X-band amplifier based on the GaAs metal semiconductor FET (MESFET). By 1980 many MMIC power amplifier results using MESFETs for various applications had been reported. Since that time, tremendous progress has been made both in MMIC PA

358

Monolithic power amplifiers

developments and in system applications. Some of the early development milestones in MMIC PAs are listed below: r r r r r r

X-band power GaAs MESFET amplifier in 1979; Q-band GaAs MESFET power amplifier in 1986; X-band GaAs HEMT power amplifier in 1989; W-band HEMT power amplifier in 1992; C-band GaAs MESFET very high-efficiency power amplifier in 1996; X-band GaAs MESFET high-power amplifier in 2000.

The outstanding progress in MMIC technology is attributed to the following: r rapid development of GaAs material technology, including semi-insulating wafers, epitaxial growth, and ion implantation; r advanced photo- or E-beam lithography technology developed for Si ICs and directly applicable to GaAs ICs; r excellent microwave properties of semi-insulating GaAs substrates (high dielectric constant, εr = 12.9, and low-loss tan δ = 0.0005), which permit easy isolation of devices for high-level integration; r the development of power transistors operating at up to 100 GHz have provided MMIC designers with versatile active circuit components; r high electron mobility transistors (HEMTs) and heterojunction bipolar transistors (HBTs) which are, in addition to MESFETs, the other most common active devices used in MMIC power amplifiers. Pseudo-morphic HEMT (pHEMT) MMICs provide enhanced performance in terms of noise figure, power, PAE, bandwidth, and frequency range; r the development of accurate models for characterizing active devices and passive components; r the availability of commercial CAD tools for accurate linear and nonlinear simulations and optimization of power amplifiers; r the availability of on-wafer high-frequency test probes that permit both low-cost MMIC screening based on small-signal and large-signal S-parameters, and the collection of a large amount of statistically significant data without the cost and variability of packaging; r government funding for technology development and maturation; r expanding military and commercial applications.

8.1.2

Advantages of monolithic power amplifiers Whereas most MMIC amplifiers currently in production operate in the 0.5 GHz to 40 GHz microwave range, applications covering the millimeter-wave (mmW) spectrum from 30 GHz to 300 GHz are increasing. Monolithic technology is particularly suited for millimeter wave applications through the elimination of the parasitic effects of bond wires which connect discrete components in conventional hybrid microwave

8.2 Monolithic IC technology

359

50-Ω input line Air bridge

Inductor Bonding pad

G D

S

FET Via hole

Transmission- line inductor Thin-film Capacitor resistor

Semi-insulating GaAs substrate

Figure 8.1 Three-dimensional view of a MMIC amplifier. (After Bahl [23]. Reprinted with

permission of John Wiley.)

integrated circuits (HMICs). In MMIC-based mmW subsystems, the cost can be lowered by a factor of ten or more as compared to hybrid solutions. Advantages of MMIC amplifiers include low-cost, small size, light weight, circuit design flexibility, broadband performance, elimination of circuit tweaking, high-volume manufacturing capability, package simplification, improved reproducibility, radiation hardness, and improved reliability. MMIC power amplifiers have the following potential advantages as compared to commonly available internally matched power amplifiers: r r r r r r

8.2

multistage designs have higher gain (15–25 dB); higher overall PAE; better unit to unit amplitude and phase tracking; compact in size and lightweight; lower parts count, higher reliability, and lower in cost; no external biasing chokes required.

Monolithic IC technology In fabricating MMICs, all active and passive circuit elements and interconnections are formed together on the surface of a semi-insulating substrate (usually gallium arsenide). Basic active devices used in MMICs are MESFETs, HEMTs and HBTs [2–56]. Typically, MMICs use microstrip and metal-insulator-metal (MIM) capacitors for the matching networks, whereas at low microwave frequencies, lumped inductors and MIM capacitors are commonly used. Metal-filled via holes from the bottom of the substrate (ground plane) to the top surface of MMICs, provide low-loss and low-inductance ground connections. Figure 8.1 shows a 3D view of an MMIC.

360

Monolithic power amplifiers

Figure 8.2 Flow chart for multifunction self-aligned gate (MSAG) MESFET MMIC process.

8.2.1

MMIC fabrication Different methods are used to fabricate MMIC amplifiers. Most MMICs using MESFET, HBT, and HEMT are manufactured by a recessed-gate process. MESFETs are also manufactured by employing a self-aligned gate (SAG) FET process which permits the efficient fabrication of devices optimized for different functions (e.g., microwave small signal, microwave power, and digital) on the same wafer at the same time. The selfaligned gate process has demonstrated superior performance uniformity in a manufacturing environment. One particular embodiment of such a process is its state-of-the-art power amplifier performance. It is important for designers to have an appreciation for the complexity of MMIC manufacturing. A GaAs MMIC power amplifier process has over 250 individual process steps. As an example, a simplified flowchart for the GaAs SAG MMIC process showing major steps is depicted in Figure 8.2. The process includes the fabrication of active devices, resistors, capacitors, inductors, distributed matching networks, airbridges, and via holes for ground connections through the substrate. The process for recessedgate MMICs has many similarities. Basic process steps are similar for any MMIC technology. In general, GaAs MMIC processing is less complex than silicon RFIC. Because silicon has inherently lower frequency capability and poorer isolation properties for integration purposes, more exotic processing is required to compete in the frequency region of overlap with GaAs applicability. For example, a silicon bipolar complementary metal oxide semiconductor (BiCMOS) process for such IC applications may require 2–3 times as many mask layers, adding significantly to the cost.

361

8.2 Monolithic IC technology

Table 8.1 Comparison of transistor/monolithic integrated-circuit substrates1 Property

Silicon

SiC

GaAs

InP

GaN

Semi-insulating Resistivity (-cm) Dielectric constant Electron mobility (cm2 /V s) Saturation electrical velocity (cm/s) Radiation hardness Density (g/cm3 ) Thermal conductivity (W/cm-◦ C) Operating temperature (◦ C) Energy gap (eV) Breakdown field (kV/cm)

No 103 –105 11.7 1450 9 × 106 Poor 2.3 1.45 250 1.12 ≈300

Yes >1010 9.7 500 2 × 107 Excellent 3.1 3.5 >500 2.86 ≥2000

Yes 107 –109 12.9 8500 1.3 × 107 Very good 5.3 0.46 350 1.42 400

Yes ∼107 14 4000 1.9 × 107 Good 4.8 0.68 300 1.34 500

Yes >1010 8.9 800 2.3 × 107 Excellent 6.1 1.3 >500 3.39 ≥5000

1

Pure materials at room temperature.

One can find comprehensive information on the design, fabrication, and performance of monolithic microwave and millimeter-wave integrated circuits as well as their applications in IEEE Microwave and Millimeter-Wave Monolithic Circuits Symposium Digests published from 1982 to 1996, IEEE RFIC Symposium Digests published since 1997, and IEEE GaAs IC Symposium Digests published since 1980. Several other books listed [2–23] deal with this subject either partially or exclusively.

8.2.2

MMIC substrates Various substrate materials used for MMICs are bulk silicon, silicon carbide, GaAs, InP, and GaN. Their electrical and physical properties are compared in Table 8.1. The semi-insulating and high-thermal conductivity property of the substrate material is crucial to providing higher device isolation and lower dielectric loss, and a good heat dissipation path for power MMICs. Silicon dominates the marketplace and GaAs is used widely at RF, microwave, and mmW frequencies. For high-voltage, high-power and high-temperature applications, wide-bandgap materials with relatively high thermal conductivity, such as SiC and GaN, play a significant role as a substrate material. The recent development of high-voltage active devices with very high-power densities on a SiC substrate was only possible due to its high thermal conductivity, which is a prime requirement for any semiconductor material to be used as a substrate for high-voltage and high-power density devices and MMICs.

8.2.3

MMIC active devices The MESFET (0.25–1.0 μm gate lengths) has been the workhorse for analog integrated circuits (ICs) since 1976. MESFET based power MMICs demonstrate excellent performance at microwave frequencies. However, HEMT and HBT devices offer potential advantages in microwave and millimeter-wave IC applications, arising from the use

362

Monolithic power amplifiers

2b W

εr

(a)

W = 2a h

S

εr

(b)

Figure 8.3 Transmission lines for MMICs: (a) microstrip, (b) coplanar waveguide.

of heterojunctions to improve charge transport properties (as in HEMTs) or p–n junction injection characteristics (as in HBTs). HEMTs appear to have an advantage in ultralow-noise and mmW applications. The MMICs produced using novel structures such as pseudo-morphic, lattice-matched HEMTs, also known as pHEMTs, have significantly improved the power performance and high-frequency (up to 280 GHz) operation. AlGaN/GaN HEMT devices have demonstrated power densities greater than five times higher than that of conventional GaAs-based transistors [24, 25]. HBTs are vertically oriented heterostructure devices and are popular as power devices. GaAs HBTs are extensively used as power devices for high-volume wireless applications because of their high-gain, good efficiency, and single power supply low-voltage operation. They also offer better linearity and lower phase noise than do FETs and HEMTs. For power circuits, where one needs much higher current, either a large number of cells are employed or larger gate periphery devices are used. The performance of microwave transistors in MMIC technologies is improving every year. The upper frequency limit of MMICs is generally dictated by the active device technology used. The performance of these devices (FETs, HEMTs, and HBTs) depends on the substrate material, process type, and channel physical dimensions. A commonly used figure of merit for devices is known as the maximum frequency of oscillation and denoted by fmax . Generally, for amplifiers the maximum frequency of operation is about half of fmax [26]. As reported in the literature, the fmax values for a 0.1 μm gate-length pHEMT on an InP substrate is about 600 GHz, and for a 1 μm emitter HBT it is about 170 GHz. A three-stage amplifier fabricated using a 0.1 μm pHEMT on an InP substrate has exhibited about 12 dB gain at 153–155 GHz [27]. MESFETs, HEMTs, and HBTs have been described in detail in Chapter 2.

8.2.4

MMIC matching elements In addition to active devices, MMICs require high Q passive circuit elements. Like hybrid ICs, monolithic circuits use distributed as well as lumped matching elements. The microstrip line and coplanar waveguide (CPW) are the two most commonly used transmission media in MMICs. Microstrip is more popular because of its quasi-TEM nature and excellent layout flexibility. Microstrip line is exclusively used in MMIC amplifiers due to high current handling capability. Cross-sectional views of these lines with physical parameters are shown in Figure 8.3. Sections of microstrip lines and coplanar waveguide constitute the basic passive component building blocks of

8.2 Monolithic IC technology

363

Table 8.2 Microstrip data summary on GaAs substrate: h = 100 μm, t = 5 μm, tan δ = 0.0005, f = 10 GHz and εr = 12.9

W (μm)

W/h

Z0

εre

α (dB/cm)

Line capacitance (pF/100 μm)

Line inductance (nH/100 μm)

10 20 30 40 50 75 100 125 150 200 250 300 400 500

0.10 0.20 0.30 0.40 0.50 0.75 1.00 1.25 1.50 2.00 2.50 3.00 4.00 5.00

87.8 75.1 67.2 61.4 56.8 48.4 42.5 38.1 34.5 29.2 25.4 22.5 18.3 15.5

6.89 7.23 7.45 7.62 7.76 8.06 8.31 8.52 8.71 9.03 9.30 9.52 9.89 10.18

0.716 0.541 0.468 0.422 0.390 0.342 0.315 0.301 0.293 0.282 0.276 0.271 0.265 0.262

0.010 0.012 0.014 0.015 0.016 0.020 0.023 0.026 0.028 0.034 0.040 0.046 0.057 0.069

0.077 0.067 0.061 0.056 0.053 0.046 0.041 0.037 0.034 0.029 0.026 0.023 0.019 0.016

monolithic microwave integrated circuits. When the size of the microstrip section is reduced to dimensions much smaller than the wavelength, the section can be treated as a lumped element. Examples of lumped microstrip elements are spiral inductors, thin-film resistors, and interdigital capacitors. Microstrip sections in lumped and distributed forms are commonly used in passive and active monolithic microwave integrated circuits. To realize compact circuits, lumped element matching networks, or lumped-distributed circuit elements are utilized to transform device impedance to 50 . An overview of these circuit elements is given below [28].

Microstrip Several methods used to determine microstrip parameters are summarized in reference [28]. The microstrip propagation properties, such as the characteristic impedance (Z0 ), effective dielectric constant (εre ) and attenuation constant (α) are controlled by conductor width W and substrate height h for a given dielectric constant value (εr = 12.9 for GaAs). Table 8.2 summarizes Z0 , εre , α, line capacitance and line inductance data calculated for various line dimensions and for a GaAs substrate. As an example, for a 50  line on a GaAs substrate, the value of width-to-height ratio W/h is about 0.7. As shown in Figure 8.4, the characteristic impedance Z0 decreases and the effective dielectric constant εre increases when the strip W/h of the line is increased. The measured attenuation constant of microstrip as a function of line width on 100 μm thick GaAs at 1, 10, 20, and 30 GHz is shown in Figure 8.5. The attenuation in the line decreases with increasing line width. Wavelength in microstrip λ is related to εre by √ λ = λ0 / εr e where λ0 is the free space wavelength.

(8.1)

Monolithic power amplifiers

120

12

100

10 εre

80

Z0(Ω)

60

8 6 εre

Z0

40

4

20

2

0 0.01 0.02 0.05

0.1

0.2

0.5

1

2

5

0 10

W/h Figure 8.4 Variation of characteristic impedance and effective dielectric constant of microstrip versus W/h on 100 μm thick GaAs.

1.6

1.2 α (dB/cm)

364

0.8 f (GHz) 30 20 10

0.4 0 10

1

20

40

100

20

400

Line Width (μm) Figure 8.5 Measured attenuation constant of microstrip versus line width on 100 μm thick GaAs at 1, 10, 20, and 30 GHz.

The maximum frequency of operation of a microstrip transmission line is limited as a result of several factors including excitation of spurious modes, higher losses, pronounced discontinuity effects, low Q caused by radiation from discontinuities, effect of dispersion on pulse distortion, tight fabrication tolerances, handling fragility and, of course, technological processes. The maximum frequency of operation of a microstrip transmission line, the frequency at which significant coupling occurs between the dominant quasi-TEM mode and the lowest-order surface wave spurious mode, is given by [28],  150 fT = πh

2 tan−1 εr εr − 1

(8.2)

8.2 Monolithic IC technology

365

where fT is in gigahertz, h is in millimeters and the inverse of tangent is expressed in radians. The excitation of higher-order modes in a microstrip can be avoided by operating it below the cut-off frequency of the first higher-order mode, which is given approximately by fc = √

300 εr (2W + 0.8h)

(8.3)

where fc is in GHz, and W and h are in mm. This limitation is mostly applicable for low-impedance lines that have wide microstrip conductors. The calculated value for the maximum thickness of the GaAs substrate for microstrip circuits designed at 100 GHz is less than 0.3 mm. Since it is impossible to do tuning on GaAs MMICs, an accurate and comprehensive modeling of microstrip discontinuities is required to save expensive and time-consuming iteration of mask and wafer fabrication and evaluation. As the yield of MMICs depends on the size (the smaller the chip, the higher the yield), and the circuit’s acceptable electrical performance, discontinuities play an important part in the development of MMICs. The effect of discontinuities becomes more critical at higher frequencies. The discontinuities should be either taken into account or compensated for at the final stage of design. In most cases discontinuities are basically undesirable circuit reactances, and in a good circuit design, efforts are made to reduce or compensate for these reactances as discussed in reference [28]. In most high-frequency applications, the compact matching circuits are electromagnetic (EM) simulated.

CPW Several methods used to determine CPW parameters are summarized in reference [28]. CPW properties are controlled by the center conductor width W and the spacing between the strip and the ground-plane conductor denoted by S in Figure 8.3b. In CPW, the substrate thickness generally used is large so that if the substrate has a conductor backing to improve the mechanical strength, its effect is insignificant on the electrical characteristics of the CPW. Figure 8.6 shows the variation of Z0 and εre as function of the conductor width to gap separation ratio. The characteristic impedance of the line decreases with increasing a/b ratio. The measured attenuation versus characteristic impedance Z0 for CPW is shown in Figure 8.7. The attenuation in the line at 60 GHz has a minima when the characteristic impedance of the line is about 60 . For thick substrates the coupling of power from the dominant mode to higher-order modes takes place. The coupling to surface waves and radiation from unwanted (parasitic) modes contributes additional loss to the total loss of the CPW. The parasitic mode in a coplanar waveguide is the odd-mode with antiphase voltages in the two slots. This mode can be excited at discontinuities, and radiation may occur. Radiation from this mode can be minimized by maintaining symmetry of the circuits and thus avoiding its excitation or by using air bridges connecting the ground planes at regular intervals to short circuit it out. In a conductor-backed coplanar waveguide, the parallel-plate waveguide modes are other parasitic modes. Surface waves or the substrate modes are the TM and TE modes supported by the substrate. Excitation of these modes can be avoided if

Monolithic power amplifiers

160

7.5 h/b h/b 0.5 1.0

140

7.0

∞

120

6.5

∞ 1.0

6.0

100

εre

Z0(Ω)

0.5

80

5.5

60

5.0

40

4.5

20 0.01 0.02 0.05 0.1 0.2 0.5 a /b

4.0 0.01 0.02 0.05 0.1 0.2 0.5 a /b

1

1

Figure 8.6 Variation of characteristic impedance and effective dielectric constant of CPW versus slot dimensions on GaAs.

10 b (mm) = 0.10 0.15 0.20

5 α (dB/cm)

366

1 0.5

0.1 10

50

90

130

170

Z0 (Ω) Figure 8.7 Measured attenuation constant of CPW versus slot characteristic impedance on 100 μm thick GaAs at 60 GHz.

a thin substrate is used such that the cutoff frequency of the surface modes is pushed above the operating frequency. This is achieved if the substrate thickness h is chosen such that √ h ≤ 0.12λ0 / εr

(8.4)

where λ0 is the free space wavelength. Like microstrip discontinuities, CPW discontinuity effects must also be taken into consideration. CPW MMICs, compared with microstrip-based MMICs, can have lower loss at millimeter-wave frequencies with proper design of the matching networks, require

8.2 Monolithic IC technology

367

Figure 8.8 Microstrip lumped elements:(a) inductors and (b) capacitor.

S

W

Di

Do (a)

(b)

Figure 8.9 Coil inductor configurations:(a) circular and (b) rectangular.

no via-hole technology for RF ground connections, and are more suitable for flip-chip mounting.

Lumped elements A lumped element in radio frequency and microwave circuits is defined as a passive component whose size across any dimension is much smaller than the operating wavelength so that there is no appreciable phase shift between its input and output terminals. Generally, keeping the maximum dimension less than λ/20 is a good approximation. Lumped elements for use at RF and microwave frequencies are designed on the basis of this consideration, and the three basic lumped element building blocks are inductors, capacitors, and resistors. Figure 8.8 shows basic microstrip line inductors and a capacitor. Their simple forms are realized using microstrip sections. Among various inductor shapes, circular and rectangular spiral inductors, shown in Figure 8.9, and metal-insulator-metal (MIM) and interdigital capacitors, shown in Figure 8.10, are commonly used. A microstrip section realized employing a lossy conductor is used as a resistor. At RF, lumped inductors and MIM capacitors are widely used in MMIC matching networks. Lumped-element based power amplifier circuits have the advantage of smaller size, lower cost, and wider bandwidth characteristics. These are especially suitable for MMICs

368

Monolithic power amplifiers

Table 8.3 Coefficients for general inductance expression Inductor geometry

c1

c2

c3

c4

Square Hexagonal Octagonal Circle

1.27 1.09 1.07 1.00

2.07 2.23 2.29 2.46

0.18 0.00 0.00 0.00

0.13 0.17 0.19 0.20

Bottom conductor

Top conductor W 

d

εrd

(a)

(b)

Figure 8.10 (a) MIM capacitor, (b) interdigital capacitor and (c) equivalent circuit.

where real-estate requirements are of prime importance and applications where broadband is required. Currently, MMIC technologies have reached a mature stage; lumped elements working even up to 60 GHz are more suitable for low-cost circuit solutions. At frequencies below S band, MMICs using lumped inductors and capacitors are an order of magnitude smaller than ICs using distributed elements. At RF and the low end of the microwave band, the use of lumped elements makes the chip size significantly smaller without affecting the RF performance, increasing the number of PA chips per wafer, and giving improved visual and RF yields. All these factors can reduce the chip cost drastically. One can buy 1–2 W power amplifiers for as low as $5. Lumped element models can be developed using analytical, physics and EM, and measurement-based methods. A more general expression for inductance of arbitrary shape has been reported in the literature and reproduced as follows [20]  μ0 n 2 Dav c1  (8.5) n (c2 /χ ) + c3 χ + c4 χ 2 2 where coefficients ci for various geometries are given in Table 8.3, χ is the fill ratio and Dav is the average diameter of the inductor, and their expressions are given below L=

χ=

Do − Di Do + Di

(8.6)

1 (Do + Di ) (8.7) 2 MMIC capacitors are classified into three categories: microstrip (Figure 8.8b), MIM, and interdigital as shown in Figure 8.10. A small length of an open circuited low-impedance microstrip section can be used as a lumped capacitor with a low capacitance value (<0.2 pF) per unit area due to thick substrates. MIM capacitors are fabricated using a Dav =

8.2 Monolithic IC technology

369

multilevel process and provide the largest capacitance value (0.1–50 pF for monolithic on GaAs) per unit area because of a very thin dielectric layer sandwiched between two electrodes. The interdigital geometry has applications where one needs moderate capacitance (0.1–0.5 pF) and high Q values. The MIM capacitor structure might have two or more conductors. The capacitance, C (in farad), of a capacitor structure consisting of two conductors as shown in Figure 8.10a is expressed as: C = ε0 εrd

A W × = ε0 εrd d d

(8.8)

where W and  are the width and length of one of the plates, εrd is the dielectric constant of the capacitor dielectric film and ε0 is the free space permittivity. The above equation does not include the effect of fringing field. Equation (8.8) can be expressed in commonly used units as follows: W × d W × C = 8.85 × 10−6 εrd d C = 8.85 × 10−3 εrd

(pF), W , , and d in mm

(8.9a)

(pF), W , , and d in μm

(8.9b)

A detailed treatment of these components can be found in reference [20].

Electromigration requirements In MMICs the conductors are much thinner than in MICs. Therefore a special attention to current handling of such conductors in PAs becomes important. The current handling capability of a conductor is limited by the onset of [20] is the transport of material caused by the gradual movement of the ions in a conductor due to high current densities flowing through it. When the current density in the conductors is on the order of 106 A/cm2 or higher, has a continuous impact on the metal grain causing the metal to pile up in the direction of current flow. In thin conductors, electromigration-induced damage usually occurs in the form of voids and hillocks in the metal due to the depletion and accumulation of metal grains due to heavy flow of electrons. This also occurs in transistor gates, drain and source pads as well as in ohmic contacts. Voids mostly result in higher ohmic contact resistance. The effect of electromigration becomes more pronounced at elevated temperatures. The voids and hillocks due to electromigration grow over extended periods resulting in open circuits in conductors and short circuits between closely spaced conductors. In FETs, open circuits in gates give rise to limited control on drain-source current and higher drain-source current values. Growing hillock formations short circuit the fingers. The conductivity, thickness, and line width determine the current carrying capacity of the conductor. A safe value of maximum current density for gold conductors on a GaAs flat surface is 2.22 × 105 A/cm2 . Thus, for carrying DC current the electromigration requirements dictate the microstrip and inductor line widths. A current density of 2.22 × 105 A/cm2 translates to a maximum allowed current per unit line width of

370

Monolithic power amplifiers

Figure 8.11 Example of an MMIC design system.

10 mA/μm for 4.5 μm thick gold conductors and 20 mA/μm for 9 μm thick gold conductors. This dictates much wider conductors for bias lines in HPAs. For example, to carry 5A DC current, the microstrip (4.5 μm thick) width required is 500 μm.

8.3

MMIC design methodology The design of MMIC PAs requires state-of-the-art computer aided design (CAD) tools. The need for increased design sophistication arises from the fact that the post fabrication tuning flexibility available in conventional hybrid microwave circuits is no longer present in monolithically fabricated circuits. Consequently, a new design methodology is required. This includes development of accurately characterized standard library cells as well as subcircuits, accurate linear and nonlinear models for active devices, accurate passive component models, use of circuit topology and circuit elements that are more tolerant to process variations, tolerance centering of designs, proximity effect models, comprehensive simulation of complete circuits, and automatic RF testing of ICs on wafer. The latter is needed in order to characterize ICs before any design tweaking is performed.

8.3.1

CAD tools Numerous in-house and commercial CAD tools are being used to design MMIC power amplifiers. Figure 8.11 shows [29] an example of a comprehensive CAD tool consisting of device, circuit, and system simulators, accurate component models (including physicsbased and EM), and statistical design features. Commercial microwave CAD tools available to designers include Agilent’s ADS, Ansoft’s Designer, and Applied Wave Research’s Microwave Office, and Cadence. A comprehensive MMIC CAD tool provides efficient coupling between the circuit simulation, the schematic captive/text editor, and the layout generator, greatly improving overall accuracy and reducing design cycle time. With such a system, first-pass-design success for MMIC PAs is achievable.

8.3 MMIC design methodology

371

Figure 8.12 Typical flowchart for an MMIC power amplifier design.

8.3.2

Design procedure Typical MMIC power amplifier design generally follows the flow diagram shown in Figure 8.12. The design starts with the circuit specifications including frequency range, gain, input and output VSWR, output power, PAE, linearity, stability, thermal management and cost, which derive from the system requirements. The electrical and thermal requirements also dictate the circuit topology along with the types of passive element and active device to be used (e.g., distributed or lumped passive elements, power transistor sizes, substrate thickness). Comprehensive passive element and active device models developed by a foundry or by users are employed to simulate circuit functions. The final design is completed by taking into account layout discontinuities, interaction between the components, stability analysis of amplifiers, and circuit yield analysis by considering process variations. In the case of PA design, an accurate nonlinear model [30–37] for each device used is essential in order to design the circuit accurately. The thermal design of MMIC amplifiers is also a critical aspect for their success. Thus, MMIC power

372

Monolithic power amplifiers

amplifier design becomes an art, to meet several often conflicting requirements, and an experienced designer will outperform beginners. An overview of MMICs is given in references [16, 38].

8.3.3

EM simulators Electromagnetic [EM] simulators have become an integral part of MMIC CAD tools. They are mainly responsible for accurate modeling of passive circuit elements and components. These simulators, also known as field solvers, are commonly used to model circuit elements such as microstrip and coplanar waveguide structures, discontinuities, and coupling between transmission-line sections and discontinuities, structures using multilayer dielectric and plating, inductors, capacitors, resistors, via holes, and crossovers. Passive components, such as filters, couplers, resonators, power dividers/combiners, baluns, matching impedance transformers, and several types of interconnect and package are accurately simulated using EM simulators. Accurate characterization of active device-parasitic reactance also requires EM simulation. Another key and important role of EM simulators in successful MMIC PA design is the capability to analyze the junction effects involving wide conductors and parasitic coupling effects between various parts of the circuit layout. Accurate evaluation of radiation and surface waves can be performed using EM simulators only. These effects become increasingly important as MMIC designs become more compact, and are not easily incorporated using conventional network theory-based CAD tools. However, due to the very large computation time, only a small portion of a circuit is analyzed using EM simulators, and the numerical results are combined with conventional CAD tools to obtain the response of the complete circuit. Most EM simulators work in an integrated simulation environment (i.e., they can be interfaced with microwave computer-aided design and engineering tools). In the past decade, outstanding progress made on personal computers has lead to user-friendly and versatile commercial EM simulators. An overview of commercially available EM simulators is given in Table 8.4. More comprehensive information on these tools can be found in publications [39–44].

8.4

MMIC PA summary and examples MMIC power amplifiers are widely used in commercial and military applications. In recent years outstanding progress has been made in power amplifiers including narrowband with high power and high PAE, broadband, and high-voltage versions. These components are integral parts of most RF and microwave transmitters. Table 8.5 provides an overview of some narrowband and high PAE power amplifier examples. The output power and PAE values are typical. Monolithic technology is particularly beneficial to broadband amplifiers due to the elimination of the parasitic effects of bond wires and discrete components used in hybrid MICs. Progress in broadband MMIC power amplifiers is summarized in Table 8.6. Wide band-gap (WBG) semiconductors, such as SiC or

373

8.4 MMIC PA summary and examples

Table 8.4 An overview of some EM simulators being used for MMICs

Company

Software name

Type of structure 3-dimensional

Method of analysis

Domain of analysis

Agilent-EEsof

Momentum HFSS EM Unisim SFMIC

Planar Arbitrary Planar Planar Planar

Frequency Frequency Frequency Frequency Frequency

Planar Arbitrary

FEM FEM MoM Spectral domain MoM MoM FEM

Frequency Frequency

Planar

MoM

Frequency

Arbitrary

FEM

Frequency

IE3D Micro-Stripes

Arbitrary Arbitrary

MoM TLM

Frequency Time

XFDTD

Arbitrary

FDTD

Time

Sonnet Software Jansen Microwave

Ansoft Corporation

AWR MacNeal-Schwendler Corp. Zeland Software Kimberly Communications Consultants Remco

R Maxwell 2D R SI Maxwell Eminence 3D MWO: EM Simulator MSC/EMAS

Table 8.5 Some typical narrow-band high-efficiency power amplifier performance parameters [23] Frequency (GHz)

No. of stages

Gain (dB)

Power (W)

PAE (%)

Device

Technology

2.1–2.2 4.5–5.4 8–10 8–10 12–15 13.5–15 29–31 42–46 95

2 1 3 3 3 3 3 2 2

21 10 24 24 18 22 20 17 15

50 14 12 20 8 8 4 2.8 0.43

50 55 40 35 25 22 25 24 19

pHEMT MESFET MESFET MESFET MESFET pHEMT pHEMT pHEMT pHEMT

GaAs Monolithic GaAs Monolithic GaAs Monolithic GaAs Monolithic GaAs Monolithic GaAs Monolithic GaAs Monolithic GaAs Monolithic InP Monolithic

GaN, have basic material properties that are more favorable to very high-power amplifier realization than is possible in GaAs, by using high-voltage (HV) operation (typically 24–48 V). Considerable research effort is being invested in HV HPA development and has resulted in impressive progress as illustrated in Table 8.7. In this section we describe various types of MMIC power amplifier designed for narrow band, broadband, high-power and high-efficiency applications. Salient features of each design are discussed briefly.

374

Monolithic power amplifiers

Table 8.6 Summary of broadband MMIC power amplifiers. Performance listed is minimum over the frequency band. MMICs with greater than 1 W were selected for this comparison [23] Freq. range (GHz)

No. of stages

Gain (dB)

PO (W)

PAE (%)

Device technology

2–8 2.5–5.5 4.5–9 4.7–10 6–18 0.7–2.7 1.35–2.8 2.0–6.0 2.0–8.0

1 2 2 1 3 2 2 2 2

9 17 17 7 22 20 23 15 13.5

1.4 2 2 5 2.3 12 12 10 8

18 30 25 8 20 22 28 26 16

GaAs HBT GaAs MESFET GaAs MESFET GaN on Sapphire GaAs pHEMT GaAs MESFET GaAs MESFET GaAs MESFET GaAs MESFET

Table 8.7 HV MMIC HPA examples [23]

8.4.1

Frequency (GHz)

Supply voltage (V)

Output power (W)

Power density (W/mm)

PAE (%)

Technology

Year

0.9 2.0 3.3 3.5 10.0 10.0 16.0 31.0 33.0 35.0

28 12 24 55 20 40 31 20 13 24

25 50 50 36.3 8.0 20.0 24.2 11 2.2 4.0

––1 3 5 3.3 – – 2.3 3.3

60 45 40 20.6 36.7 25 22.2 – 18.6 23

HBT, GaAs pHEMT, GaAs FP FET, GaAS MESFET, SiC GaN HEMT, SiC GaN HEMT, SiC GaN HEMT, SiC GaN HEMT, SiC GaN HEMT, SiC GaN HEMT, SiC

2004 2004 2002 2004 2006 2002 2007 2004 2006

Narrowband power amplifier 7 W Ku-Band PA A 7 W Ku-band MMIC power amplifier based on MSAG MESFET was developed using the loadline method. The HPA is a three-stage design using two 1.8 mm gate periphery FETs at the input driving four 1.8 mm FETs that drive eight 1.8 mm FETs at the output [45]. The FET aspect ratio of 2:1 was used for maximum output power and PAE under saturation. Thermal analysis of these FETs is also given. The matching circuit microstrip lines are on 10 μm polyimide [46] in order to reduce the resistive loss of the output match. Figure 8.13 shows the photograph of the 7W MMIC HPA. The HPA include bias circuitry on-chip and requires bias supply from both sides. The Q-point was selected for Class AB operation (30% IDSS ). Typical measured CW Pout and PAE for the 7 W MMIC power amplifier at Vds = 8 V and Pin = 23 dBm are depicted in Figure 8.14. The

8.4 MMIC PA summary and examples

First stg. FETs

Second stg. FETs

375

Third stg. FETs

In

Out

Figure 8.13 Photograph of the three-stage 7 W Ku-band HPA. Chip size is 4.2 mm × 4.4 mm. (After Bahl [23]. Reprinted with permission of John Wiley.)

Output Power and PAE

50 Po (dBm)

40

PAE (%)

30 20 10 12.5

13.0

13.5

14.0

14.5

Frequency (GHz) Figure 8.14 Typical measured output power and PAE versus frequency at Vds = 8 V and Pin =

23 dBm.

amplifier has a large-signal gain of about 16 dB, greater than 38.5 dBm output power and better than 27% PAE over the 12.5–14.5 GHz frequency range. The measured second and third harmonic power levels were below –40 dBc and –75 dBc, respectively. During the test no additional matching circuitry or circuit tweaking was used.

376

Monolithic power amplifiers

First stage FETs

Second stage FETs

In

Out

Figure 8.15 Photograph of the two-stage 2 W broadband MMIC power amplifier. Chip size is 3 mm × 3 mm.

8.4.2

Broadband power amplifiers 2 W C-band PA Next, a 2 W C-band MMIC power amplifier for broadband applications is described. Based on the output matching network’s dissipative and mismatch loss and 0.8 W/mm power output at Vds = 10 V for the FETs, a total of 5 mm gate periphery for the output stage FETs to deliver 2 W was used. The first stage uses two 0.625 mm gate periphery FETs, resulting in a FET ratio of 4:1. In the IC design a binary matching scheme employing low-pass networks was used. Both lumped and distributed circuit elements for impedance matching networks were used. The low-pass matching sections consist of series high-impedance lines/inductors and shunt MIM capacitors. The design technique of the two-stage broadband amplifier is the same as that described in reference [47], i.e., using small signal and nonlinear FET models, and load-pull data obtained at the operating bias point. The Q-point was selected for Class AB operation (25% IDSS ) of the device in order to obtain the best compromise of power output, gain, PAE, linearity and variable power supply operation over the C band. Figure 8.15 shows a photograph of the broadband MMIC power amplifier. Typical CW measured output power, PAE and small signal gain for MMIC packaged chips at Vds = 10 V and IDQ = 360 mA are shown in Figure 8.16 as a function of frequency. The power and PAE numbers are at Pin = 19 dBm. The amplifier has better than 30% PAE with greater than 34 dBm output power and 18 dB gain over the 4.5 to 8.5 GHz frequency range. The input VSWR was better than 2:1.

8.4 MMIC PA summary and examples

377

Po, Gain and PAE

50 PAE (%)

40

Po (dBm)

30 Gain (dB)

20 10 4.5

5.5

6.5 7.5 Frequency (GHz)

8.5

Figure 8.16 Typical measured output power, efficiency, and small-signal gain versus frequency.

10 W X-band PA A 10 W X-band 3-stage high-efficiency MMIC power amplifier based on MSAG MESFET was developed [48]. The design used a FET periphery of two 0.94 mm devices (ten fingers each) in the input stage, four 1.5 mm devices (14 fingers each) in the interstage, and eight 2.5 mm FETs (24 fingers each) in the output stage. The design of the MMIC power amplifier was based on small signal and large signal FET models, and load-pull data obtained at the operating bias point. Here a reactive binary matching topology, employing low-pass and high-pass networks, was used which provided high power output and PAE. Both lumped elements and distributed circuit elements were used for impedance matching networks. In the first iteration design optimization using the load-line technique, four sets of S-parameter data, corresponding to low-gain, high gain, low current and high current, were used. These data files represent the possible fabrication changes and allowed the realization of a more process-tolerant design. Once again, the Q-point was selected for Class AB operation (25% IDSS ) of the device in order to obtain the best compromise of power output, gain and PAE over the X band. The GaAs substrate thickness was 75 μm. Figure 8.17 shows a photograph of the 10 W HPA. In the second iteration the circuit was further optimized using the Taguchi technique to improve the bandwidth and output power as described in Chapter 9 of reference [23]. Typical measured CW output power, PAE and gain versus frequency for a packaged die are shown in Figure 8.18. Power added efficiency of 34–43% and output power of 10 W were measured across the 8.5–11 GHz frequency band. The output power was 12 W with over 40% PAE across 9.5–10.5 GHz.

8.4.3

Ultra broadband power amplifiers Over the past two decades most of the MMIC power amplifier products have been developed for a bandwidth of less than 50%. Several applications such as broadband communications and electronic warfare require multioctave high-power amplifiers (HPAs). However, to date, limited work on multioctave MMIC HPAs has been reported in the published literature. Some of these examples are discussed next.

Monolithic power amplifiers

First stg. FETs

Second stg. FETs

Third stg. FETs

Out

In

Figure 8.17 Photograph of the three-stage 10 W X-band MMIC HPA. Chip size is 4.6 mm × 4.6 mm. (After Bahl [23]. Reprinted with permission of John Wiley.)

50 Po, Gain and PAE

378

Po (dBm)

40

PAE (%) 30 Gain (dB) 20 10

8

9

10

11

Frequency (GHz) Figure 8.18 Typical measured CW output power, PAE and gain of a 10 W HPA. Vds = 10 V and

Pin = 19 dBm. Baseplate temperature was 60 ◦ C.

15 W L- to S-band HPA A low-cost solution to broadband MMIC HPAs has been reported recently [49]. The design example was a 12 W two-stage amplifier operating over 0.7 to 2.7 GHz. The design methodology and test results for this HPA have also been described in reference [49]. Another high-power amplifier working over 1.2 to 2.4 GHz with a target output

8.4 MMIC PA summary and examples

First stg. FETs

Second stg. FETs

In

379

Drain bias busline

Out

Figure 8.19 Photograph of the two-stage 15 W L/S-band MMIC power amplifier. Chip size is 5.0 m × 8.0 mm. (After Bahl [23]. Reprinted with permission of John Wiley.)

power of 15 W was designed using a reactive/resistive matching technique and a 0.4 μm MSAG FET. The two-stage HPA consists of four 2.0 mm FETs at the input driving 16 2.0 mm FETs at the output. The HPA design was based on loadline data and a low-loss matching technique. The HPA includes bias circuitry on-chip and requires bias supply from both sides. The amplifier was operated at a nominal power supply voltage of 10 V. The Q-point was selected for Class AB operation (20–25% IDSS ). Figure 8.19 shows a photograph of the 15 W broadband HPA. Figure 8.20 shows the average measured CW output power and PAE of the broadband MMIC power amplifier. PAE was better than 29% with greater than 15 W saturated power output over 1.2 to 2.8 GHz. The small-signal gain was better than 20 dB and input and output VSWR were less than 2:1. This outstanding power performance was only possible because of high across-wafer uniformity of saturated drain-source current (IDSS ) and cut-off frequency ( fT ) for the MSAG process [49].

8 W 2–8 GHz HPA A two-octave bandwidth MMIC HPA developed using MSAG MESFET technology was reported in reference [50]. The ultra broadband MMIC HPA used two stages; eight 0.94 mm FETs in the input stage drive sixteen 0.94 mm FETs in the output stage. The output stage matching network used a 16-way binary reactive combining topology to

380

Monolithic power amplifiers

Figure 8.20 Typical measured CW output power and PAE at Vds = 10 V.

obtain two-octave bandwidth. A low-loss matching design technique, as discussed in Chapter 9 of reference [23], was used in the design of the two-stage power amplifier. The matching networks were realized using a multilevel plating MMIC process. Figure 8.21 shows a photograph of the 8 W broadband MMIC HPA. Typical measured CW output power and PAE for the MMIC power amplifier are shown in Figure 8.22. Over the 2–8.5 GHz frequency range Pout was greater than 37.6 dBm and PAE better than 16%. The dips in power and PAE at 4.5 and 7.5 GHz are due to higher mismatch loss as discussed in reference [50]. Over most of the frequency band, the output power and PAE were close to 8 W and 20–30%, respectively. The measured second and third harmonic power levels were below –13 dBc and –13.5 dBc, respectively.

2–18 GHz Distributed PA Next, an ultra-broadband 0.5 W 2–18 GHz two-stage distributed amplifier (DA) based on MSAG MESFET is described. Each stage is matched to 50  and uses five cells. In the first stage each FET has a gatewidth of 300 μm. In the second stage the device size is tapered to obtain the largest power bandwidth and PAE, and the FET sizes used are 630, 630, 470, 470, and 300 μm. By using small-signal S-parameters each stage was optimized for maximum gain, and good input and output VSWR. Figure 8.23 shows the physical layout of the broadband DA. The measured gain and saturated output power are shown in Figure 8.24. The measured saturated power and PAE in the 2–18 GHz band were 0.5–0.8 W and 10–15%, respectively.

8.4 MMIC PA summary and examples

Drain 1 bias bus line

381

Gate 2 bias bus line Drain 2 bias bus line

Tr. line balun

In

Out

Output Power and PAE

Figure 8.21 Photograph of the 2-stage 8 W S/C/X-band MMIC HPA. Chip size is 5.0 mm × 6.3 mm. (After Bahl [50]. Reprinted with permission of IEEE.)

50 Po (dBm)

40

PAE (%)

30 20 10

2

3

4

5

6

7

8

9

Frequency (GHz) Figure 8.22 Typical measured output power and PAE versus frequency of the 8 W ultra broadband MMIC HPA.

8.4.4

High-power amplifiers Although there are fundamental limitations to the power that can be generated from a single transistor, the achievable power levels can be significantly increased by combining a number of devices operating coherently or by accumulating the power from a number of discrete devices. Monolithic high-power amplifier design involves power combining as many devices as is practical in order to achieve increased power levels. A single

382

Monolithic power amplifiers

Stage 2

Out

In

Stage 1

Figure 8.23 Layout of the 0.5 W 2–18 GHz MMIC PA. Chip size is 3 × 3 mm. (After Bahl [23]. Reprinted with permission of John Wiley.)

Figure 8.24 Typical measured gain and output power versus frequency of the 2–18 GHz MMIC power amplifier.

large device is impractical on a MMIC because of the difficulty of matching the very low device input impedance. The cluster matching technique [23] has emerged as the optimum means of integrating the matching network into the splitting and combining manifolds. The MMIC chip width and the insertion loss of this output manifold impose a practical limit on the number of devices that can be combined – both for economical reasons (wasteful use of expensive chip space) and because the efficiency drops quickly

8.4 MMIC PA summary and examples

383

Figure 8.25 A 50 W 2.1–2.2 GHz MMIC power amplifier. Chip size is 10 mm × 10 mm. (After Akkul et al. [51]. Reprinted with permission of IEEE.)

as the combining loss increases. Much higher power levels are obtained by combining MMIC HPAs off-chip using matched combiners.

50 W S-Band HPA An example of a 50 W MMIC amplifier [51] is shown in Figure 8.25. The output match depicts the cluster matching technique. The two-stage 2 GHz design is based on 0.5 μm gate GaAs pHEMT devices and used sixteen 8 mm cell (128 mm total gate periphery) at the output stage. The measured CW power and efficiency, at a nominal 12 V supply voltage, were 50 W and 45% over a 10% bandwidth, respectively.

X-Band 20-W HPA Next, an example of power combining using two MMIC HPAs “on-chip” is described. The 20 W X-band HPA consists of two 10W power amplifiers fully matched to 50  and combined using a Wilkinson-type power splitter/combiner. The 10 W high-power amplifier design consists of three stages [52]. Binary corporate feed combining was used consisting of two 0.625 mm FETs driving four 1.1 mm FETs which finally drive eight 2.0 mm FETs. Each FET had 20 μm gate-to-gate pitch. The chip was designed to operate at a nominal supply voltage of 10 V. Figure 8.26 shows a photograph of the 20 W HPA. Typical measured CW output power and PAE data for a packaged die, taken at Pin = 18 dBm, are shown in Figure 8.27. The HPA was tested at 25 ◦ C base plate temperature. The measured PAE was better than 33% and greater than 43 dBm output power, over the 8 to 10 GHz frequency range was achieved. The large–signal gain was 25 dB.

Monolithic power amplifiers

Figure 8.26 Photograph of the 20 W X-band HPA. Chip size is 5 × 8 mm. (After Bahl [23]. Reprinted with permission of John Wiley.)

50 Output Power and PAE

384

Po (dBm)

20 W

40 PAE (%) 30 20 10

7

8

9

10

11

Frequency (GHz) Figure 8.27 Typical measured PAE and output power versus frequency at Vds = 10 V and Pin =

18 dBm.

14 W HPA with 60% PAE The current and voltage waveform clipping are the fundamental sources of compression in a power amplifier. Waveform clipping and other device nonlinearities result in harmonic generation at the input and output of the amplifier. Converting fundamental frequency signal into harmonic signals degrades the output power and PAE. If these harmonic signals are reactively terminated properly, i.e., superimposed on fundamental

8.4 MMIC PA summary and examples

385

Out

Second Harm. Term.

In Figure 8.28 Layout of the 15 W C-band HPA. Chip size is 3.7 × 6.4 mm. (After Bahl [23]. Reprinted with permission of John Wiley.)

43

65

60 Po (dBm)

41

50

40

39 4.4

55

4.6

4.8 5.0 5.2 5.4 Frequency (GHz)

PAE (%)

Output Power (dBm)

PAE 42

45 5.6

Figure 8.29 Typical measured PAE and output power versus frequency at Vds = 10 V and Pin =

32 dBm.

voltage and current waveforms with the desired phase at the input and output, the PAE of the amplifier can be enhanced by shaping the sinusoidal input signal into approximately a square wave signal. As discussed in Chapter 8 of reference [23], the most desirable termination conditions are: second harmonic short circuited and the third harmonic open circuited at the internal port of the device. Next, a narrowband single-stage MMIC HPA with state-of-the-art PAE obtained by harmonic tuning is discussed. The high-efficiency 15 W C-band MMIC power amplifier based on MESFET technology used 28 mm gate periphery and was matched to 25  input and output system impedance The circuit was optimized using the Taguchi technique and described in references [23, 53]. The chip was designed to operate at a nominal supply voltage of 10 V. The layout of the single-stage HPA is shown in Figure 8.28. Quarter-wave 25– 50  impedance transformers were used to test the HPA chip. Figure 8.29 shows typical measured CW output power and PAE over 4.4 to 5.6 GHz. The packaged HPA was

386

Monolithic power amplifiers

characterized at 25 ◦ C base plate temperature. The measured PAE was better than 55% with greater than 14 W output power over the 4.7 to 5.5 GHz frequency range. Greater than 60% PAE was obtained over a narrower band.

8.4.5

Millimeter wave 2.4 W PA Excellent progress has been made in millimeter wave MMIC PAs based on pHEMT technologies. A monolithic high-power and high-PAE two-stage amplifier operating from 27.5 to 29.5 GHz was reported for local multipoint distribution service. The amplifier was designed in a balanced configuration using Lange couplers. Each singleended HPA chip was designed with 50  input and output. The design was based on 0.15 μm gate-length pHEMTs operating at a power supply of 5 V [54]. The measured values for small-signal gain, output power and PAE were 16 dB, 1.6 W, and 35%, respectively. A peak output power of 2.4 W with PAE of 37% was reported.

8.4.6

Wireless 3 W power amplifier Next, an example of a GSM MMIC power amplifier based on GaAs HBT technology is described. Typical performance specifications are given below: Frequency range Power gain Output power PAE Input VSWR Supply voltage Control Current

880–915 MHz 30 dB 3W 50% 2:1 3.5 V 5 mA @ 2.7 V

The amplifier design was based on a 3 μm emitter width GaAs HBT monolithic technology [23]. HBT technology has gained acceptance as a cost effective alternative to MESFET power amplifiers and has several advantages over MESFET technology. An HBT power amplifier operates from a single positive DC power supply resulting in reduced overall amplifier design complexity. HBT power amplifiers are capable of very high power densities, which reduces the overall chip size and cost compared to MESFET/pHEMT power amplifiers. However, the thermal design of HBT power amplifiers is much more critical than with MESFET amplifiers. Great care must be taken to prevent thermal runaway in HBT power amplifier designs. To meet the target gain specification, the power amplifier requires three stages. The output stage is sized at 11,880 μm2 , which requires six parallel arms with 11 cells per arm as shown in Figure 8.30. Each cell consists of two fingers having a total area of 2 × 3 × 30 = 180 μm2 . The device size ratio of the last two stages is 6.6:1 and the device size ratio of the first two stages is 5:1. Figure 8.31 shows typical measured CW performance of this HBT PA design. PAE is 54% with output power of 35.5 dBm. Measured large-signal gain was greater than 30 dB. The input return loss was better than 10 dB.

8.4 MMIC PA summary and examples

387

Po, PAE, Gain and Return Loss

Figure 8.30 Layout of GSM MMIC power amplifier. (After Bahl [23]. Reprinted with permission of John Wiley.)

60 PAE (%)

50 40

Po (dBm)

Gain (dB)

30 20 10 -20

Input RL (dB) -15

-10 -5 0 Input Power (dBm)

5

10

Figure 8.31 Typical measured power, PAE, gain and input return loss versus input power of GSM power amplifier design.

8.4.7

High-voltage monolithic PAs At a nominal 10 V supply there is a limit on how many transistors one can combine in parallel in a single package to produce a high-power amplifier. At the low end of S band for discrete transistors this limit is 150–200 W, while for a single MMIC at 10 GHz, this

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Figure 8.32 Photograph of the 10 W 3-stage HVMSAG MMIC. The chip size is 3 mm2 . (After

Bahl [23]. Reprinted with permission of John Wiley.)

limit is about 20 W. This limit is caused by transverse resonance along the width and not being able to match the very low device impedance. With HV transistors this limit is extended by a factor of 5–10. HV operation for a given output power simplifies the MMIC chip and system current routing. Higher voltage operation will increase the load impedance, making it easier to achieve the necessary matching for output power and PAE over the operating frequency band. At RF and low microwave frequencies harmonic terminations and class-E operation are important design parameters in an HVHPA next to low-loss output matching network in order to obtain high PAE. MMIC power amplifiers using high-voltage devices have been developed working in S through Ka bands. Below 4 GHz, several devices including field plate (FP) MESFETs, HBTs, pHEMTs and GaN HEMTs have been used to develop MMICs, whereas above 4 GHz, MMICs are primarily based on GaN HEMTs [23]. Next, examples of MMIC HPAs based on HV devices are presented.

10 W GaAs HV FET MMIC amplifier A three-stage 10 W MMIC amplifier was reported based on HV MSAG FET [55]. The HV MSAG process is designed to operate at 24 V. The HPA used a 9.6 mm FET periphery at the output stage to achieve 10 W of output power. Figure 8.32 shows a photograph of the MMIC. Typical measured CW output power and PAE of the packaged chip at P1 dB are shown in Figure 8.33. PAE was greater than 30% with 10 W output power over 3–3.8 GHz band. The associated gain was 27 dB.

GaN HEMT MMIC on SiC amplifiers Since the early 2000s steady progress has been made in GaN HEMT-based MMIC power amplifiers. A 24 W MMIC power amplifier was reported using 0.4 μm gate GaN HEMT on SiC at 16 GHz and biased at 31 V. The two-stage amplifier was matched to 50  at the input and 25 at the output. The input stage used 3 mm driving 6 mm transistors at the output. A quarter-wave 25–50  impedance transformer was used to test the HPA chip. The measured output power and PAE at 16 GHz were 24.2 W and 22%, respectively [24].

Output Power and PAE

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50 10 W 40

Po (dBm) PAE (%)

30 20 10 2.7

2.9

3.1 3.3 3.5 3.7 Frequency (GHz)

3.9

Figure 8.33 Typical measured output Power and PAE of the 10 W HVMSAG MMIC.

The associated gain was 12.8 dB. Thus, a power density of 4 W/mm was demonstrated at Ku band. A 4 W power amplifier MMIC was developed using 0.18 μm gate length Al/GaN/GaN HEMT on SiC at Ka band. The two-stage design used two 0.6 mm gate periphery transistors at the output. The device aspect ratio in the two-stage design was 2:1 [56]. The chip was designed to operate at a nominal supply voltage of 24 V. The measured saturated output power and PAE at 35 GHz were 4 W and 23%, respectively. The associated gain was 12 dB.

8.5

Packaging of MMIC PAs The application of amplifiers in modern commercial and military systems requires cost-effective packaging solutions. For high-volume commercial applications, power amplifiers are generally housed in low-cost plastic packages whereas military and highpower amplifier applications often use semicustom/custom ceramic packages designed for performance, reliability, and low to medium volume manufacturing. RF packaging technologies are advancing rapidly in terms of modeling, frequency, bandwidth and cost. Some of these packages are usable up to 40 GHz. The topic of RF and microwave packaging has been treated in several books [57–62], book and handbook chapters [63– 70], and many other publications [71–75]. A brief history of RF and microwave packages is provided in reference [70]. The selection of a suitable package and assembly technique play an important role in the performance, cost, and reliability of MMIC power amplifiers. When amplifier circuits are packaged, the effect of package assembly techniques and package environment must be kept to a minimum. Minimizing package complexity is important for reducing package cost. Minimizing the number of dielectric layers and the overall size assists dramatically in the improvement of production yields and lowering costs. However, a tradeoff exists between simplicity and functional features of these packages. The packaging requirements depend upon the application at hand. For example, in wireless communications applications below 18 GHz, GaAs MMIC power amplifiers are

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Figure 8.34 Examples of MMIC ceramic packages. (After Bahl [23]. Reprinted with permission of John Wiley.)

being mounted into surface mount plastic packages in order to achieve low-cost goals. For applications with a relatively low-power operation, they are thermally acceptable. For high-frequency, high-performance, and high-power (including HV) applications, metal-base ceramic packages are often required as they have low thermal resistance, good hermetic properties, high-power capability, and good reliability.

8.5.1

Ceramic packages Numerous types of ceramic package were developed during the late 1970s and 1980s for transistors and MMICs. There are many types of ceramic package offered by manufacturers either in off-the-shelf or custom outlines. The most popular ceramic packages are for power transistors as well as for internally matched power amplifiers. Packages were developed both with and without leads. A ceramic package uses a ceramic material as the base material between the leads for high isolation and low loss. In ceramic packages, the amplifier die is usually mounted in an air cavity with a metal or ceramic lid on top. Also, the power amplifier die is soldered to a metal base for best heat transfer from the package. In power packages, the metal base or flange is then directly attached to a heatsink. Ceramic packages can be manufactured in such a way that the product will be either hermetic or nonhermetic depending on the environmental requirements. Hermetic seal can be one of the key advantages of the ceramic-based package, especially for challenging environmental requirements. Hermetic seal adds considerable cost though to the amplifier product. Several MMIC ceramic package styles are shown in Figure 8.34.

8.5 Packaging of MMIC PAs

(a)

391

(b)

Figure 8.35 (a) Photograph of a ceramic package for MMIC medium power amplifiers. (After Bahl [23]. Reprinted with permission of John Wiley.) (b) Photograph of an MMIC HPA in a large cavity ceramic package.

High performance, medium power (less than 5 W) ceramic packages in large quantity are available in the $2–3 range. Today, the most popular ceramic package is with leads and was developed for medium power MMIC amplifier applications having moderate volumes such as VSAT and pointto-point radio applications. A photograph of this type of package with a lid is shown in Figure 8.35a. A MMIC HPA mounted in a large cavity version of the aforementioned ceramic package is shown in Figure 8.35b.

Materials for ceramic packages Ceramic package substrate materials can be composed of alumina (Al2 O3 ), glass (SiO), glass alumina (LTCC and HTCC), aluminum nitride (AlN), boron nitride (BN), beryllium oxide (BeO), or silicon carbide (SiC). Among these, alumina is the most popular. Ceramic materials have very high melting points and chemical stability because of their strong bonds. Ceramic materials have an excellent combination of electrical, mechanical, thermal and dimensional properties. Kovar is the most popular lead frame or pin material for leaded ceramic packages. Kovar is an alloy with a composition of 53% Fe-17% Co-20% Ni. It has a good thermal expansion match with alumina, Si, GaAs and sealing glass but poor thermal conductivity. Due to its poor thermal conductivity the use of kovar is limited to package leads and, for low-power applications, as a package base or flange. The base or flange material for high-power applications is generally a composite metal such as CuW or CuMoCu.

Ceramic package design Packaging considerations for MMICs are similar to those for hybrid MICs. The package must pass electrical requirements as well as rigorous tests of hermetic properties, thermal and mechanical shock, moisture resistance, resistance to salt atmosphere, vibration and acceleration, and solderability. In order to minimize the effect of the package on MMIC performance, electrical, mechanical and thermal modeling of packages must be performed and included in the MMIC design.

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Cavity

Bonding pad

Feedthrough Metal base Metal layers Ceramic layers

Figure 8.36 A ceramic package configuration with feed through.

For RF and microwave packages, the important electrical characteristics are low insertion loss, high return loss and isolation, and no cavity or feed through resonance over the operating frequency range. When a chip or chip set is placed in the cavity of a package, there should be minimum degradation in the chip’s performance. Generally, this cannot be accomplished without accurate electrical and EM modeling of the critical package elements. Microwave design must be applied to three parts of the package: RF feed through, cavity and DC bias lines. Of the three, the design of the RF feed through is the most critical in determining the performance of packaged MMIC chips. Figure 8.36 shows a ceramic package with feed through. Salient features of MMIC package design are discussed next. The selection of the substrate material and thickness for ceramic packages depends on the electrical performance requirements, cost, and frequency range of interest. The substrate thickness is selected to match its height with MMIC thickness; otherwise, a pedestal for mounting MMIC chips is required because these chips are typically about 2–4 mil thick. Microwave packages generally use 10 to 20 mil thick alumina substrates, whereas millimeter-wave packages use 4 to 5 mil thick quartz. A low dielectric constant is generally preferred because it makes the package interconnects electrically insensitive and tolerant to microstrip dimensions, and it offers broadband frequency ranges, and it results in a high yield. The microstrip width and thickness determines the characteristic impedance and the DC resistance, whereas the spacing between the two conductors on the same plane controls the crosstalk because of coupling. Generally, sufficient space between the MMIC, the package walls, and the lid is provided in order to minimize any interactions. The effect of the package lid on the MMIC characteristics is kept to a minimum by keeping the lid above the MMIC surface by about five times the package substrate thickness. In the ceramic package design, the affect of the type of lid becomes critical in terms of amplifier stability. In high gain applications the use of a ceramic or plastic lid is preferred because the use of metal lid might need some absorber material to minimize the feedback between the output and input leads. Figure 8.37 shows several types of multilead ceramic package. An air-cavity surface-mount low-profile leadless

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Figure 8.37 Examples of leaded low-cost ceramic packages: (a) 6-lead, (b) 10-lead and (c) MMIC

package.

Cavity view

Lid view

Base view

Figure 8.38 Air cavity ceramic packages showing open, lid, and backside package views.

ceramic package is shown in Figure 8.38. The ceramic packages are surface mounted on to a PCB or are soldered into modules. Many styles of ceramic (alumina, beryllium-oxide, and aluminum nitride) packages with metal bases (copper, copper-tungsten, or copper molybdenum) are available for MMIC power amplifiers. Their cost depends upon the package size, frequency of operation, metal used, and volume. Some of these packages can be used up to 40 GHz. Packages working up to 20 GHz can be obtained for less than $3 in large volume. In small quantities, they cost between $20 and $50 not including nonrecurring engineering (NRE) tooling cost. Typically, the measured dissipative loss per RF feed is less then 0.3 dB at 20 GHz. These packages provide much higher frequency of operation, low lead-frame inductance, very low ground connection inductance, and much lower thermal resistance than the plastic packages. Ceramic-type packages are well suited for high-frequency and medium-power MMIC amplifiers.

Manufacturing ceramic packages There are several methods being used for manufacturing ceramic packages. These methods are similar to hybrid circuit fabrication techniques including thin film, thick film,

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Monolithic power amplifiers

Green tape forming

Cutting and punching

Screen printing

Laminating

Ni/Au plating

Lead frame brazing

Nickel plating

Co-firing

Figure 8.39 Typical flow process for manufacturing of ceramic packages.

SOIC

PQFN

Figure 8.40 Examples of plastic IC packages including SOIC and PQFN.

LTCC, and HTCC. Figure 8.39 shows a typical flow process for the manufacture of ceramic packages. Major suppliers of ceramic packages include Kyocera and NTK. Ceramic packages are shipped in plastic waffle trays.

8.5.2

Plastic packages The work on plastic packaging continues to make them more versatile, extend their frequency range to higher frequencies, to handle more power, and lower the cost. These developments have lead to surface mount plastic packages such as small outline integrated circuit (SOIC) packages. Low-cost and low-inductance requirements in the semiconductor industry were the driving force behind the enormous development of the high-performance leadless molded plastic packages. These packages are surface mount leadless packages (SMLP), also known as power quad flat no lead (PQFN) or simply QFN. These packages typically have leads on all four sides but newer very small outlines are two sided. PQFN packages come in a variety of sizes and lead frame configurations. Pitch, the distance between the leads, varies from 0.3 mm to 1 mm. The bonding pad size is 12 by 12 mm. Figure 8.40 shows examples of plastic IC packages including SOIC and PQFN. Plastic packaging, which includes both package and assembly, often costs less than $0.25 per package. In contrast to a ceramic package, the MMIC power amplifier die in a plastic package is encapsulated with a plastic molding compound so that no air-cavity or lid is involved. The molding compound can affect the amplifier frequency response, especially for frequencies above 3 GHz. High frequency designs should be simulated with the loading of the plastic compound on the matching networks. Leads in plastic packages have lower isolation (40 dB versus 60 dB) because of the material properties of the plastic.

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395

In addition, plastic packages are nonhermetic and are sensitive to moisture. However, they are substantially cheaper for high-volume applications. Innovations in package and molding compound design have allowed plastic packages to be used for high-gain and high-frequency amplifier products. In the plastic package, the lead frame (LF) is the central supporting structure to which the die is attached. The lead frame is stamped from a thin sheet of metal. The metal sheet is usually of Kovar for low-power application and copper/copper alloy for power packages. The LF carries the die throughout the assembly process. Plastic packages are mostly modified versions of standard lead frame designs including the molding material. Diced wafers are supplied to the plastic packaging manufacturer and they perform all the steps including pick-and-place, epoxy dispense, wire bonding, molding, marking and sawing packages. For power amplifier products, thermally as well as electrically conductive epoxy is required. Plastic packages are shipped in plastic tubes, in cans, and in tape and reel. Major suppliers of plastic packaging include Amkor, Carsem, Unisem, Asat, and Azimuth. The plastic packages are usually surface mounted on a PCB in their final configuration.

Plastic package design Plastic package design basically consists of two parts: LF and plastic polymer. The lead frame is the backbone of a plastic package. Generally both LF and polymer are available as standard items from plastic packaging manufacturers. The lead frame can be modified by paying an additional tooling cost to the manufacturer. The design of a lead frame comprises its material, package thickness, cavity size, total number of leads, and lead-to-lead pitch. The dielectric constant and loss tangent values of the organic molding compound are about 3.7 and 0.01, respectively. Several different types of lead frame material including nickel-iron and copper-based alloys are being used. Their selection for a particular application depends on factors such as cost, performance, and ease of fabrication. The desirable features for the LF materials are good strength, good thermal expansion match with Si and GaAs materials, and high thermal conductivity. The lead frame material may be grouped into three categories: nickel-iron, copper-clad strip, and copper-based alloys. Kovar and Alloy 42 (42% Ni58%Fe) are the most widely used LF materials for low-power applications but have poor thermal conductivity. Copper-based LF materials have very high thermal conductivity and are used for power amplifiers. Copper-clad LF materials were developed to match the mechanical properties of Alloy 42 while retaining copper’s high thermal conductivity. Cladded material is fabricated by rolling copper foil onto stainless steel. Copper alloys are obtained by mixing other metals into copper to obtain alloy properties suitable for plastic packages. The frames are either chemically etched or mechanically stamped from metal sheets. Typical sheet thickness is from 8 to10 mil. The portion of the lead frame which is to be wire bonded is silver plated.

Plastic packages For a given package size the only package design variable is the number of leads. For example, the 4 mm package is available in both 20 and 24 leads. There are several

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Monolithic power amplifiers

Table 8.8 Examples of PQFN packages with maximum MMIC die size

Package style

Max die size (mm2 )

4 mm PQFN-20LD 4 mm PQFN-24LD 5 mm PQFN-20LD 5 mm PQFN-28LD 6 mm PQFN-28LD

2.15 × 2.15 2.45 × 2.45 3.15 × 3.15 3.15 × 3.15 4.45 × 4.45

4 × 4 mm2

5 × 5 mm2

6 × 6 mm2

Figure 8.41 Top-side view of high-performance PQFN plastic packages.

versions of high-performance PQFN package which are available. Some of them are shown inFigure 8.41 and listed in Table 8.8 with preferred GaAs or Si die size for each package. The cavity size is slightly larger than the die size. Large cavity size is usually used for multistage medium power amplifiers. Plastic packages such as 4 mm PQFN-16LD can be used up to 18 GHz. and the measured loss in a PQFN package is on the order of 0.2 dB at 18 GHz.

8.5.3

Package assembly Die attach and wire bonding are two important steps in package assembly. In a MMIC power amplifier assembly the first step is to attach chip components onto carriers, pedestals/shims, package cavities and substrates or substrates onto carriers, etc. The chip attachment technique is called the die attach process. The important considerations for die attach are to have low thermal resistance and a strong mechanical bond. In the case of hybrid assemblies both die and surface mount packaged die including semiconductor chips, capacitors, inductors and resistors are used. The die form minimizes size, weight, the effect of parasitic reactance and die-to-die propagation delays. It is preferred to mount high-power chips first on to pedestals/shims and then solder them into packages.

Die attach Two methods are used for die attachment: epoxy die attach and eutectic die attach. Epoxy die attach process is commonly used for mounting passive components, and low and

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medium power devices. The epoxies are cured at relatively low temperatures, are easy to work with, are applied using automatic dispensers, and are military and space qualified. Epoxy is available in two types: silver (Ag) epoxy and gold (Au) epoxy. Ag epoxy is commonly used as it is less expensive than Au epoxy. Eutectic die attach is performed using a heated stage, and a commonly used solder material is gold tin (AuSn) with a ratio 80:20 with chips that have backside gold metallization. The metallization of 1 μm thick gold is good enough for eutectic soldering. For higher temperature operation, a gold-germanium (AuGe) eutectic solder can also be used. Eutectic solder material is available in the form of a preform and usually its size is slightly smaller than the chip size. The work stage or chuck is preheated. The temperature of the heating stage should be set such that the bonding area quickly rises to within 50–75 ◦ C of the melting point of the solder preform. A 1 mil thick preform is generally used. At the final solder step, a jet flow of heated forming gas or nitrogen which has the gas temperature of about 100 ◦ C above the solder melting point is used. The solder should melt in a few seconds after applying the air jet. A preform is placed where the die is to be soldered and it promptly melts. The die is placed on the melted preform with care and scrubbed back and forth. The carrier is removed from the heated stage and allowed to cool. The solder time is generally less than 5 minutes. If the chuck temperature or solder time or both are substantially increased, the die attach process might degrade the semiconductor chip performance. The thermal conductivity of commonly used gold-tin solder is 57 W/m ◦ C, whereas the thermal conductivity of silver epoxy materials Kidd AG-03HTL, Std Ablebond 84– 1LMISR4 (∼Ablebond 8360) and Ablebond RP-316–1 are 300, 2.8 and 10 W/m ◦ C, respectively. Among these materials Kidd AG-03HTL appears to be the best for packaging MMIC PA chips.

Die wire bonding After die attach process, discrete lumped elements and semiconductor devices (transistors or MMICs or both) are interconnected with each other or connected to package substrate pads or to leads using wire bonds. In wire bonding, two similar metals are “bonded” together under the influence of pressure and temperature at well below their melting point. Both the wire and pad are gold. If the wire is made from gold, the pad to be attached has to be of gold. This technique is also known as thermal compression bonding. Two methods for thermal compression wire bonding are used: ball bonding and wedge bonding. Wedge bonding is also performed by using ultrasonic techniques. The electrical model for single and multiple wires has been described in Chapter 4 of reference [20]. As a first-order approximation the lead frame parasitic capacitance can be combined with the wire bond inductance to realize a transmission line of characteristic impedance of 50 . When a wire bond is modeled as an inductor from the measured S-parameter data, it might result in a lower value than the actual value if one is not careful. This can be explained by using Figure 8.42. A simple model of a short wire bond is shown in Figure 8.42a. The series inductance may be split into two parts as

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Monolithic power amplifiers

L

L1 Cs

(a)

Z0

L1

L2 Cs

(b)

(c)

Figure 8.42 Simplified bond wire models.

shown in Figure 8.42b. A part of the series inductance L2 with shunt capacitance Cs is equivalent to 50  line, i.e.  (8.10) Z 0 = L 2 /Cs = 50  This is shown in Figure 8.42c. Thus, during de-embedding, a part of the inductance is absorbed in the de-embedding impedance, which lowers the series inductance value. In order to obtain an accurate model, one must carefully compare both the magnitude and phase of the modeled response with the measured S-parameter data. Also, by measuring the SRF, one can de-embed the shunt capacitance Cs . The SRF is given by f res =

1 √ 2π LCs

(8.11)

For example, two 30 mm long wires have L ∼ = 0.4 nH, Cs = 0.06 pF and SRF = 32.49 GHz.

Assembly of ceramic packages A ceramic package flow diagram example is depicted in Figure 8.43 [70]. The first step is to apply silver epoxy (low-power devices) or place a solder preform in the cavity of the package (power devices). In the latter case the package is placed on a hot plate. The next step is to place the semiconductor die to be packaged. In moderate and highvolume applications this step is usually done using an automatic pick and place machine. After this 100–200 pF RF bypass chip capacitors are attached with silver epoxy. This is followed by wire bonding and then the lid is attached to the package wall. The lid is made from ceramic, glass or metal. The lid is coated with solder material along its border and then thermally attached. Lids are also attached using brazing, glass sealing and welding. In the final step the product is marked using a laser scribing technique and the lead-frame trimmed if necessary.

Assembly of plastic packages Figure 8.44 illustrates an MMIC plastic packaging flow diagram [70]. The ICs are packaged using pick and place techniques. The first step is to apply silver epoxy. The next step is to place the semiconductor die to be packaged. This is followed by wire bonding and molding. Steps such as pick-and-place, epoxy dispensing, wire bonding and molding are performed by using automatic machines and robots for high reproducibility of performance and low cost. Then the product is marked and finally the lead-frame is

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Figure 8.43 Assembly flow for MMIC housed in a ceramic package. (After Bahl [23]. Reprinted with permission of John Wiley.)

Wafer Processing

Encapsulation

Pick and Place

Wire Bonding

Epoxy Dispense

Die Attach

Figure 8.44 Assembly flow for MMIC housed in a plastic package. (After Bahl [23]. Reprinted

with permission of John Wiley.)

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Monolithic power amplifiers

Figure 8.45 Illustration of a GaAs medium power amplifier die bonded to the lead frame of a plastic package. (After Bahl [23]. Reprinted with permission of John Wiley.)

sawn or punched to separate each plastic package. Figure 8.45 shows a medium power GaAs MMIC amplifier attached to a lead frame. The output power level is about 2 W.

Hermetic sealing and encapsulation Generally military, and sometimes commercial applications, require an MMIC package to be hermetically sealed. A ceramic package and a metal housing are hermetically sealed to protect from moisture and environment hazards. In this technique after mounting the die and wire bonding, a lid is attached to the top of the package housing. Only ceramic/glass packages and metal housings are considered hermetic. In some applications the package encapsulation comprises glob-top, molding and cavity fill techniques. In this method, the die and wires are covered with a polymer material. Package encapsulation is less complex and provides limited protection from environment hazards. Due to improved chemical purity of encapsulation materials, the reliability of plastic encapsulated circuits has been enhanced over the last decade [62].

Thermal considerations Thermal modeling of packages becomes very important when the packages are used with high-power ICs. Since thermal effects are frequency independent, thermal modeling techniques used for low-frequency packages can also be used for microwave packages. In HPAs and high-voltage HPAs (HVHPAs) where heat removal is of prime importance

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401

in packages and assemblies, thermal management becomes the predominant issue. The current heat spreaders comprise BeO, AlN, CuW, CuMo, CuMoCu, and SiC and their thermal conductivity values range between 150 to 350 W/mK. In GaAs and Si based transistor amplifiers the heat flux is in the range 100–300 W/cm2 . However, in HVHPAs the heat flux is much higher than 300 W/cm2 . These heat flux values are an order of magnitude higher than a high-power microprocessor’s heat flux level. To handle very high heat flux values one needs diamond-like materials or composite materials as heat spreaders with thermal conductivity values over 500 W/m K. The basics of thermal design of amplifiers are treated in Chapter 16 of reference [23] and Chapter 9 of this book. The power dissipation in MMIC HPAs is much higher than in low-power ICs. Therefore the thermal design of HPAs and their assemblies (the layer stack from amplifier die to heatsink) becomes the most critical aspect of their success. By properly designing the boundaries between the GaAs chip and the heat sink for a good thermal path, heat generated in the active devices can be efficiently removed. A thin GaAs substrate, a void free and reliable die attach, use of a high thermal conductivity base plate, and a good coefficient of thermal expansion match between GaAs and alumina is the basis for good thermal design. High power ICs generate large heat fluxes and in such cases high thermal conductivity flanges are designed to handle the dissipated heat. MMIC power amplifiers produced in large volume are housed in air-cavity ceramic or over-molded plastic packages. Achieving a uniform die attachment, at least under the active area of the device, is very critical for thermal management of dissipated power. Since voids in the die attach area have very low thermal conductivity, they either significantly degrade or damage transistors. The quality of die attach can be examined using scanning acoustic microscopy, also known as a sonoscan. In this method ultrasonic energy is applied at the back of the flange. Since the ultrasound signal will not pass through voids, they are detected using acoustic imaging.

8.6

MMIC power amplifier characterization The evaluation of a MMIC power amplifier is a lengthy multistep process that examines the performance of the device over frequency, temperature, input power, drain voltage, and bias point. Parameters collected include output power, drain current, gate current, harmonics, gain, noise figure, VSWR, TOI, IMD3, IMD5, and identification of spurious signals. MMIC power amplifiers may be characterized using one of the four methods outlined in the flow chart shown in Figure 8.46. The characterization of a MMIC power amplifier begins with the measurement of onwafer small-signal CW or pulsed (depending on the output power level of the amplifier) S-parameters tested by using RF probes over a very wide frequency range, typically 10 MHz to 20 GHz. The RF probes are normally calibrated using short-open-load-thru (SOLT) standards available on commercial sapphire substrates. To check the validity of measurements, gold standards or bench-mark circuits are generally used. A photograph

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Initial on-wafer screen

Shim mounted

Plastic/ceramic package

Carrier mounted

RF probe test

PC board

Fixure

Package/ Housing

Test

Test

Housing Test

Test

Figure 8.46 MMIC power amplifier characterization flow.

Figure 8.47 Typical on-wafer HPA pulsed power measurement setup. (After Bahl [23]. Reprinted with permission of John Wiley.)

of an on-wafer test setup is shown in Figure 8.47. On-wafer ultra-broadband testing often reveals stability issues that are not present or cannot be observed in the band of operation. These initial S-parameters are used to develop specifications for the input power level required for on-wafer pulsed power measurements before a detailed characterization of the part can begin in connectorized test fixtures or a housing. Pulsed power measurements using RF probes are performed to test power amplifiers on-wafer for screening before mounting on carriers or into packages. The large-signal S-parameter data is also used

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403

Figure 8.48 Connectorized Fixture used to characterize the power and IMD performance of MMIC HPAs under CW conditions. (After Bahl [23]. Reprinted with permission of John Wiley.)

for phase-matched binning of the power amplifier chips for off-chip efficient power combining using a hybrid approach. After “on-wafer” pulsed power screening, several MMIC amplifier chips are generally assembled on gold-plated Elkonite (Cu-W alloy) carriers for RF characterization. The power amplifier products are either tested by mounting them on shims/pedestals or inserting them into plastic/ceramic packages or a housing. The Elkonite material is chosen for its good thermal conductivity and good thermal expansion match to GaAs and alumina. The ICs are die attached using gold-tin (80/20 AuSn) at 300 ◦ C on a pedestal in order to keep minimum bond wire lengths between the chip and the input and output microstrip feed lines which are typically printed on 15 mm thick alumina substrate. To the same carrier, 100–200 pF border chip capacitors are mounted for good RF bypass. The test fixtures are fitted with high-performance microstrip-to-coaxial connectors having return loss greater than 20 dB up to 18 GHz. All chips are tested under CW conditions and the base plate temperature is kept at 25 ◦ C. The primary test vehicle for performing the power and IMD characterization is the connectorized fixture as shown in Figure 8.48. This fixture provides for improved grounding, excellent thermal management, and an opportunity to adequately bias the part. The carrier is generally bolted into a brass/copper fixture that includes RF SMA connector blocks, 0.01–0.1 μF capacitors to eliminate bias line instability, and DC connection points for bias application. During test, the fixture block is directly attached to a cold/hot

404

Monolithic power amplifiers

Power meter 1

Power meter 2

Source LPF

Power amplifier

Directional coupler 1

DUT

LPF

Directional coupler 2 Spectrum analyzer

Power meter 3

Figure 8.49 Schematic of typical Pout versus Pin measurement setup.

Figure 8.50 Photograph of Pout versus Pin measurement test station. (After Bahl [23]. Reprinted with permission of John Wiley.)

plate to maintain the required test temperature. Figure 8.49 shows a typical schematic of a Pout versus Pin measurement setup and a photograph of the test station is depicted in Figure 8.50. Power characterization is the first CW examination of the MMIC power amplifier product. This testing is performed over drain voltage, usually 4 to 10 V; bias point 10, 25, and 40% of IDSS ; input power -20 dB to + 5 dB of design P1 dB ; and temperature. In this case, the output power at the fundamental and harmonic frequencies is measured as a function of input power. The fundamental output power is usually measured using a power meter (CW or pulsed) while the harmonics are measured by employing a spectrum analyzer (SA). Also, the SA is used to monitor for oscillations during power testing. If no issues are found with the design, the results of this characterization are used in releasing the preliminary datasheet and for determining the on-wafer production test

8.6 MMIC power amplifier characterization

405

Figure 8.51 PCB used for testing MMICs in PQFN packages. (After Bahl [23]. Reprinted with permission of John Wiley.)

plan. This test plan defines the test conditions of frequency, bias, and input power and lists the measurements to be performed, e.g., small-signal gain, large-signal power, and gate and drain currents. The remaining undiced wafers are screened using the newly developed production test plan. Datasheets are transitioned from preliminary to final status when a statistically significant population of test data has been collected on a particular part. For die products, this data comes from on-wafer screening of a number of lots. Final data sheets establish min/max limits for parameters that are measured on 100% of the die product. Following the power characterization, TOI and IM3 testing is performed under the same set of conditions as that of the power characterization. Shim mounted die are used to measure the noise figure and CW S-parameters over temperature. Plastic packaged devices are also tested in tubes using automatic handlers. Plastic packaged power amplifiers are generally tested by mounting them on a printed circuit board (PCB). Figure 8.51 shows a PCB used for testing of PQFN packages. Ceramic packaged power amplifiers are characterized using fixtures. Figure 8.52 shows the test board for a commonly employed ceramic package used for driver power amplifiers. The MMIC power amplifier’s RF parameters are defined at the input and output as reference planes, DC bias conditions are at the suggested DC terminal points, and thermal interface is at the back of the chip or package. Other factors such as various support circuits including packages, couplers, filters, circulators, antennas, bias lines,

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Monolithic power amplifiers

Figure 8.52 Test fixture for testing ceramic packaged driver amplifiers. Bypass capacitors are 0.1 μF ceramic chip. (After Bahl [23]. Reprinted with permission of John Wiley.)

fixtures, and connectors will affect its performance. Any resistive loss or mismatch loss at the output, and the thermal setting can reduce the output power and PAE significantly. Under such conditions the final product amplifier performance must be re-evaluated and sufficient margins in the MMIC design must be considered.

References 1. R. S. Pengelly and J. S. Turner, “Monolithic broadband GaAs FET amplifiers,” Electron. Lett., vol. 12, pp. 251–252, May 13, 1976. 2. J. V. Dilorenzo, D. D. Khandelwal (Eds.), GaAs FET Principles and Technology, Artech House, Norwood, MA, 1982. 3. R. S. Pengelly, Microwave Field-Effect Transistors – Theory, Design and Applications, Wiley, Hoboken, NJ, 1982. 4. R. Soares, J. Graffeuil, and J. Obregon (Eds.), Applications of GaAs MESFETs, Artech House, Norwood, MA, 1983. 5. R. E. Williams, Gallium Arsenide Processing Techniques, Artech House, Norwood, MA, 1984. 6. R. A. Pucel (Ed.), Monolithic Microwave Integrated Circuits, IEEE Press, Piscataway, NJ, 1985. 7. D. K. Ferry (Ed.), Gallium Arsenide Technology, Howard Sams, Indianapolis, IN, 1985. 8. N. G. Einspruch, W. R. Wisseman, GaAs Microelectronics, Academic Press, New York, 1985.

References

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9. I. J. Bahl and P. Bhartia, Microwave Solid State Circuit Design, 2nd Edn., Wiley, Hoboken, NJ, 2003, ch. 15. 10. R. Soares (Ed.), GaAs MESFET Circuit Design, Artech House, Norwood, MA, 1989. 11. J. Mun (Ed.), GaAs Integrated Circuits: Design and Technology, New York: Macmillan, 1988. 12. P. H. Ladbrooke, MMIC Design: GaAs FETs and HEMTs, Artech House, Norwood, MA, 1989. 13. R. Goyal (Ed.), Monolithic Microwave Integrated Circuits: Technology and Design, Artech House, Norwood, MA, 1989. 14. F. Ali, I. Bahl, and A. Gupta (eds.), Microwave and Millimeter-wave Heterostructure Transistors and Their Applications, Artech House, Norwood, MA, 1989. 15. F. Ali, A. Gupta (eds.), HEMTs and HBts: Devices, Fabrication and Circuits, Artech House, Norwood, MA, 1991. 16. D. Fisher, I. Bahl, Gallium Arsenide IC Applications Handbook, Academic Press, San Diego, 1995. 17. R. Goyal (Ed.), High Frequency Analog Integrated Circuit Design, Wiley, Hoboken, NJ, 1995. 18. W. R. Deal, X. B. Mei, V. Radisic, W. Yoshida, P. H. Liu, J. Uyeda, M. Barsky, T. Gaier, A. Fung, L. Samoska, and R. Lai, “Demonstration of a 270 GHz MMIC amplifier using 35-nm InP HEMT technology,” IEEE Microw. Wireless Components Letts., vol. 17, pp. 391–393, May 2007. 19. K. Chang, I. Bahl and V. Nair, RF and Microwave Circuit and Component Design for Wireless Systems, Wiley, Hoboken, NJ, 2002. 20. I. J. Bahl, Lumped Elements for RF and Microwave Circuits, Artech House, Norwood, MA, 2003. 21. I. J. Bahl, “Monolithic microwave integrated circuits (MMICs),” in Encyclopedia of RF and Microwave Engineering, Wiley, Hoboken, NJ, 2005. 22. I. D. Robertson and I. J. Bahl, in R. C. Dorf (Ed.), “Solid state circuits,” in the Electrical Engineering Handbook, 3rd Edn, CRC Press, Boca Raton, FL, 2006. 23. I. J. Bahl, Fundamentals of RF and Microwave Transistor Amplifiers, John Wiley, Hoboken, NJ, 2009. 24. W. L. Pribble, J. W. Palmour, S. T. Sheppard, R. P Smith, S. T. Allen, T. J Smith, Z. Ring, J. J. Sumakeris, A. W. Saxler, and J. W. Milligan, “Applications of SiC MESFETs and GaN HEMTs in power amplifier design,” IEEE MTT-S Int. Microwave Symp. Dig., pp. 1819–1822, 2002. 25. R. S. Pengelly, “Improving the linearity and efficiency of RF power amplifiers,” High Frequency Electron., pp. 26–34, Sept. 2002. 26. J. M. Golio, Microwave MESFETs and HEMTs, Artech House, Norwood, MA, 1991. 27. H. Wang, R. Lai, Y. C. Chen, Y. L Kok, T. W. Huang, T. Block, D. Streit, P. H. Liu, P. Siegel, and, B. Allen, “A 155-GHz monolithic InP-based HEMT amplifier,” IEEE MTT-S Int. Microw. Symp. Dig., pp. 1275–1278, 1997. 28. K. C. Gupta, R. Garg, I. Bahl, and P. Bhartia, Microstrip Lines and Slotlines, 2nd Edn., Artech House, Norwood, MA, 1996. 29. M. B. Steer, J. W. Bandler, and C. M. Snowden, “Computer-aided design of RF and microwave circuits and systems,” IEEE Trans. Microw. Theory Tech., 50th Anniversary Issue, vol. 50, 996–1005, Mar. 2002.

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30. R. Anholt, Electrical and Thermal Characterization of MESFETs, HEMTs and HBTs, Artech House, Norwood, MA, 1995. 31. Special Issue on Process-oriented Microwave CAD and Modeling, IEEE Trans. Microw. Theory Tech., Vol. 40, July 1992. 32. Special Issue on Computer-aided Design of Nonlinear Microwave Circuits, Int. J. Microw. Millimeter-Wave Computer-Aided Eng., vol. 6, Jan. 1996. 33. Special Issue on Optimization-oriented Microwave Computer-aided Design, Int. J. Microw. Millimeter-Wave Computer-Aided Eng., vol. 7, Jan. 1997. 34. F. Bonani, S. D. Guerrieri, F. Filicori, G. Ghione, and M. Pirola, “Physics-based large-signal sensitivity analysis of microwave circuits using technological parametric sensitivity from multidimensional semiconductor device model,” IEEE Trans. Microw. Theory Tech., vol. 45, pp. 846–854, May 1997. 35. D. Estreich, “Nonlinear modeling for MMICs,” IEEE Microw. Millimeter-Wave Monolithic Circuits Symp. Dig., pp. 93–96, 1987. 36. R. J. Trew, “MESFET models for microwave CAD applications,” Int. J. Microw. MillimeterWave Computer-Aided Eng., vol. 1, pp.143–158, April 1991. 37. J. L. B. Walker (Ed.), High-Power GaAs FET Amplifiers, Artech House, Norwood, MA, 1993. 38. E. C. Niehenke, R. A Pucel and I. J. Bahl, “Microwave and millimeter-wave integrated circuits,” IEEE Trans. Microw. Theory Tech., 50th Anniversary Issue, vol. 50, pp. 846–857, Mar. 2002. 39. T. Itoh (Ed.), Numerical Techniques for Microwave and Millimeter – Wave Passive Structures, Wiley, Hoboken, NJ, 1989. 40. R. Sorrentino (Ed.), Numerical Methods for Passive Microwave and Millimeter-Wave Structures, Wiley, Hoboken, NJ, 1989. 41. Special Issue on Engineering Applications of Electromagnetic Field Solvers, Int. J. Microw. Millimeter-Wave Computer-Aided Eng., vol. 5, Sept. 1995. 42. Special Issue on Automated Circuit Design Using Electromagnetic Simulators, IEEE Trans. Microw. Theory Tech., vol. 45, Nov. 1997. 43. A. Conrad and J. Browne, “EM tools enhance simulation accuracy,” Microwaves RF, vol. 36, pp. 133–136, Nov. 1997. 44. D. Swanson and W. Hoefer, Electromagnetic Simulators, Artech House, Norwood, MA, 2003. 45. I. Bahl, “Ku-band MMIC power amplifiers developed using MSAG MESFET technology,” Microwave J., vol. 49, pp. 56–82, Feb. 2006. 46. I. J. Bahl, E. L. Griffin, J. Dilley, and M. Balzan, “Low loss multilayer microstrip line for monolithic microwave integrated circuits applications,” Int. J. RF and Microw. ComputerAided Eng., vol. 8, pp. 441–454, Nov. 1998. 47. I. J. Bahl, “Design of a generic 2.5W, 60 percent bandwidth, C-band MMIC amplifier,” Microwave J., vol. 45, pp. 54–70, Aug. 2002. 48. E. L. Griffin, “X-band GaAs MMIC size reduction and integration,” IEEE MTT-S. Int. Microw. Symp. Dig., pp. 709–712, 2000. 49. I. J. Bahl, “0.7–2.7 GHz 12-watt power amplifier MMIC developed using MLP technology,” IEEE Trans. Microw. Theory Tech., Vol. 55, pp. 222–229, February 2007. 50. I. J. Bahl, “2–8 GHz 8-watt power amplifier MMIC developed using MSAG MESFET technology,” IEEE Microw. Wireless Comp. Letts. Vol. 18, pp. 52–54, Jan. 2008.

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51. M. Akkul, M Sarfraz, J Mayock, and W. Bosch, “50 watt MMIC power amplifier design for 2 GHz applications,” IEEE MTT-S Int. Microw. Symp. Dig., pp. 1355–1358, 2004. 52. D. Conway, M. Fowler and J. Redus, “New Process enables wideband high-power GHz amplifiers to deliver up to 20 W,” Defense Electron., pp. 8–11, Feb. 2006. 53. W. L. Pribble and E. L. Griffin, “An ion-implanted 13 watt C-band MMIC with 60% peak power added efficiency,” IEEE Microw. and Millimeter Wave Monolithic Circuits Symp. Dig., pp. 25–28, 1996. 54. M. K Siddiqui, A. K. Sharma, L.G. Callejo, and R. Lai, “A high-power and high-efficiency monolithic power amplifier at 28 GHz for LMDS applications,” IEEE Trans. Microw. Theory Tech., vol. 46, pp. 2226–2232, Dec. 1998. 55. “High voltage low cost FETs technology for HPA MMIC applications,” Microwave J., vol. 47, pp. 16–128, Dec. 2004. 56. A. M. Darwish, K. Boutros, B. Luo, B. D. Huebschman, E. Viveiros, and H. A. Hung, “AlGaN/GaN Ka-band 5-W MMIC amplifier,” IEEE Trans. Microw. Theory Tech., vol. 54, pp. 4456–4463, Dec. 2006. 57. R. R. Tummala and E. J. Rayaszewski (eds.), Microelectronic Packaging Handbook, Van Nostrand Reinhold, NY, 1989. 58. L. T. Manzione, Plastic Packing of Microelectronic Devices, Van Nostrand Reinhold, NY, 1990. 59. J. E. Sergent and C. A. Harper (Eds.), Hybrid Microelectronics Handbook, McGraw-Hill, New York, 1995. 60. P. E. Garrou and I. Turlik, Multichip Module Technology Handbook, McGraw-Hill, New York, 1998. 61. T. K. Gupta, Handbook of Thick- and Thin-Film Hybrid Microelectronics, John Wiley, Hoboken, NJ, 2003. 62. R. K. Ulrich and W. D. Brown (Eds.), Advanced Electronic Packaging, 2nd Edn, John Wiley, Hoboken, NJ, 2006. 63. N. G. Einspruch and W. R. Wissemen (Eds.), VLSI Electronics Microstructure Science, Vol. 11, GaAs Microelectronics, Academic Press, New York, 1985, Chapter 8. 64. R. Goyal, (Ed.), Monolithic Microwave Integrated Circuits: Technology and Design, Artech House, Norwood, MA, 1989, Ch. 10. 65. A. Sweet, MIC and MMIC Amplifier and Oscillator Circuit Design, Artech House, Norwood, MA, 1990. 66. M. Golio (Ed.), RF and Microwave Handbook, CRC Press, Boca Raton, FL, 2000, Section 6.10. 67. I. J. Bahl, Lumped Elements for RF and Microwave Circuits, Artech House, Norwood, MA, 2003, Ch. 13. 68. Y. C. Lee et al., “Packaging RF devices and modules,” in K. Chang (Ed.), Encyclopedia RF and Microwave Engineering, vol. 4, John Wiley, Hoboken, NJ, pp. 3590–3614, 2005. 69. S. Pinel et al., “RF/wireless packaging,” in K. Chang (Ed.), Encyclopedia RF and Microwave Engineering, vol. 5, John Wiley, Hoboken, NJ, pp. 4516–4537, 2005. 70. I. J. Bahl, Fundamentals of RF and Microwave Transistor Amplifiers, John Wiley, Hoboken, NJ, 2009, Ch. 21. 71. K. Lim, S. Pinel, M. Davis, A. Sutono, L. Chang-Ho, H. Deukhyoun, A. Obatoynbo, J. Laskar, E.,M. Tantzeris, and R. Tummala, “RF-system-on-package (SOP) for wireless communications,” IEEE Microw. Mag., vol. 3, pp. 88–99, Mar. 2002.

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72. C. A. Tavernier, F. Valentin, M Mazouz, R. Vigo, W. Muffato, P. Maeder, and M. Havasi, “High performance multilayered high temperature cofired ceramic for wide band packaging,” IEEE MTT-S Int. Microw. Symp. Dig., pp. 2277–2280, 2003. 73. D. Fisher, and I. Bahl, Gallium Arsenide IC Applications Handbook, Academic Press, San Diego, 1995, Ch. 10. 74. I. J. Bahl and E. L. Griffin, “Semiconductor chip housing,” US Patent # 4701573, Oct. 20, 1987. 75. I. J. Bahl, “Microwave feedthrough apparatus,” US Patent # 5428327, June 27, 1995.

9

RF power amplifier thermal design Mali Mahalingam Freescale Semiconductor Inc.

9.1

Why thermal design deserves careful attention? A very large fraction of the energy consumed by the radio base station (RBS) of wireless infrastructure equipment ends up as waste heat. Power amplifiers consume the largest share of the energy used by the radio base station. From a system perspective, the efficiency of energy conversion (from drawn DC power to launched RF output power) in an RBS is very low, of the order of 1.2% [1]. Similar concerns prevail for radio/TV broadcast equipment and radar equipment. Thus, improving the efficiency of power conversion (DC to RF) and low-loss launching of the RF power are major drives in the industry. Even with such an on-going drive, efficient removal and disposal of the waste heat are vitally important to keep the temperature of the power amplifiers in control. Removal and disposal of this waste heat adds to the capital and operating expenditures for wireless infrastructure equipment makers and network providers who operate such equipment. In this chapter we will examine how thermal design and temperature control influence the cost, device electrical performance and reliability of RFPAs. Thermal management adds substantial cost to the reliable operation of an RBS. From the construction of an RFPA component, to managing various thermal interfaces, to the added heatsinks to reduce the heat flux, and to the ultimate disposal of the waste heat with the help of cooling equipment, many special materials, special manufacturing processes, and physical hardware are utilized, adding substantial cost to an RBS. Later sections will address in more detail such specialty materials, manufacturing and assembly processes and cooling hardware. Given the fact that waste heat removal and its disposal are a necessity, good thermal management practices in the construction and operation of an RFPA can potentially help reduce both the initial equipment cost and subsequent operational cost. Abundant literature establishes the close link between the increased temperature and the adverse electrical performance effects on the behavior of semiconductor devices in general. A few specific examples are initially cited here. For example, the reverse saturation current in a p–n junction increases with increasing temperature [2] making a reverse biased p–n junction electrically more leaky, thus reducing the electrical isolation in an integrated circuit (IC) at higher operating temperatures. This in turn could translate into poor electrical isolation between devices and unwanted, and thus wasted, power consumption in the semiconductor device. The switching speed of a metal-oxide

RF power amplifier thermal design

Bathtub Curve on Reliability

FIT

412

Infant Mortality Region

Random / constant Failure Rate Region

End of Life / Wearout Region

Time Figure 9.1 Reliability of a semiconductor device is typically described by the “bathtub” behavior. Failures in time is shown versus time.

semiconductor (MOS) device decreases with increasing temperature [3], thus lowering high-speed performance of such devices in digital switching applications. Beyond these known generalities, specifically in the case of an RFPA, elevated temperature adversely affects RF performance parameters such as gain, RF output power, and linearity [4]. As the device temperature of an RFPA increases then, typically, gain decreases, output RF power (for a given input drive) drops, and linearity degrades. Linearized power efficiency is very nearly the most critical metric in the choice of an RFPA for an RBS. Thus, a parameter such as temperature adversely affecting the output power and linearity of an RFPA needs to be well understood and managed. The dissipated heat in any electronic device results in a rise in its temperature. Abundant literature supports the close link between the increased temperature in an electronic component and the lowering of its reliability [5]. An approximate 10 ◦ C increase in temperature reduces the mean time between failure (MTBF) by a factor of two [6]. Various failure modes and the rates associated with them govern the reliability of an electronic component. Such failure rates are typically described by the “bath-tub” curve shown in Figure 9.1 which describes the failure rate with time. Reliability is discussed in depth in Chapter 10 but a brief summary is given here. There are three distinct regions identified in such a curve: (a) early, “infant mortality” region, (b) the middle “useful life” region, and (c) the final “wear-out” region. The “infant mortality” region is due to poor quality in the manufacturing processes and is usually weeded out by quality control and in some instances by a “burn-in” process. The final “wear-out” region, as the name implies, occurs after the useful life; the increased failure rate in this final region is driven by various wear-out mechanisms in the materials and in the interfaces between these materials. The “useful life” region is

9.2 RFPA thermal design – basics

413

of most interest here. The survival rate in this region can be described by the governing equation; R(t) = e− MTBF t

(9.1)

where R(t) is the survival rate at time t and MTBF = mean time between failure. Failures in this region are governed by various failure mechanisms such as electromigration induced failures in interconnects, electro-chemical corrosion-induced failures in interconnects, gate threshold voltage drift due to hot-electron injection in the gate oxide, interface failures due to diffusion of materials in the interfaces, metallurgical grain growth, and changed fatigue behavior. These failures occur randomly and are driven by various stressors such as temperature, humidity (water moisture), and electric field. Among these recognized stressors accelerating the failures, component operating temperature is the leading stressor. Substantial empirical and theoretical literature supports this statement [7, 8]. Thus, good thermal control is of paramount importance for reliable operation of any electronic equipment. RBS are deployed in remote locations and servicing them can be expensive. An expectation of 15 years MTBF is very typical for an RBS. As a summary, good thermal design and thermal management practices for RFPAs help reduce capital and operating costs for an RBS, improve RF performance, and enhance reliability.

9.2

RFPA thermal design – basics In this section we will describe at a high level the thermal design basics as they relate to RFPAs. Though our focus in this book is on high-power RFPAs as they relate to wireless infrastructure equipment, we will first take up RFPAs as they relate to portable products such as a mobile cell phone and briefly address thermal management issues pertaining to them.

9.2.1

RFPA thermal design in a typical portable product A typical handheld product, such as a cell phone, is shown in Figure 9.2 with a few of its major functional electronic blocks identified. The power amplifier as part of the Radio Frontend is one of the critical components enabling connectivity between the handset and the base station. The power amplifier in a handset is the most power consuming component. However, prevailing trends such as longer talk time with the battery, smaller size, and lighter weight in a handset have been putting continuing pressure on the handset PA to be more energy efficient. In cellular mode such as in GSM, the transmitter PA typically produces 29 dBm to 35 dBm (∼1 W – 3 W) RF power [9]. Figure 9.3 shows an exploded view of the cell phone with two such RFPA modules, one for GSM application and the other for WCDMA application. A typical RFPA module is packaged in a land grid array (LGA)-type package. The semiconductor die technology used for the handset PA is typically GaAs HBT or GaAs pHEMT or GaAs MESFET [10]. The package

414

RF power amplifier thermal design

Signal

Power Mgmt

Display

Figure 9.2 Generic mobile phone. RFPA is part of the “radio frontend.”

WCDMA PA Module

GSM PA Module

Thermal Vias Courtesy: Binghamton University

Figure 9.3 RFPA module–substrate with thermal vias.

module substrate is typically a two- to four-layer organic material. The RFPA device is typically bonded to the organic substrate with silver-filled epoxy for die attach. Typically, these handheld/portable products are sealed enclosures and rely solely on free convection for cooling. In general, the heat flow path in these types of product from the RFPA device to the external ambient is through a series of conduction, convection and radiation paths. Heat generated in the RFPA device is typically conducted to the substrate of the package with the help of thermal vias built into the substrate [11]. Such thermal vias are shown in Figure 9.3; the thermal vias are typically Cu plated thru-holes in the substrate; typically the vias are filled with epoxies to prevent the draining of the solder material through the vias during solder reflow operation; such filling also helps improve conduction heat transfer from the device to the substrate. From the RFPA module substrate, the heat is conducted into the printed circuit board (PCB), then to the outer enclosure walls of the portable phone. Heat transfer from

9.2 RFPA thermal design – basics

415

Figure 9.4 CFD simulated air flow pattern inside and outside of a mobile phone, including air flow

around the RFPA module. Courtesy: IEEE, Proceedings of the 44th Electronic Components and Technology Conference, pp. 411–420, 1994. The external flow approaches air velocities ∼ < 0.2 m/s (primarily free convection), the internal flows are nearly negligible.

the PCB to the outer case wall may occur by conduction, convection and/or radiation depending on the specifics of the enclosure. The heat is finally removed from the outer enclosure to the environment by free convection. Based on extensive work conducted by the author [12] using CFD (Computational Fluid Dynamics) thermal simulations and supported by experimental test results, the following summary describes the typical thermal behavior of a cell phone: 1. The external air flow approaches air velocities ∼ < 0.2 m/s, i.e., primarily free convection air flow pattern governs the cooling of the cell phone. 2. The air flow internal to the enclosure is nearly negligible; free convection fails to develop inside the confined space of a cell phone enclosure; thus the main mode of heat transfer inside a cell phone occurs by conduction. 3. Typically, the highest temperature in the phone enclosure occurs in the RFPA module. These air flow fields are shown in Figure 9.4. The temperature field pattern inside such a cell phone, including around the RFPA module, is shown in Figure 9.5.

416

RF power amplifier thermal design

28.3

24.1 32.4

36.5

40.6 86.1 81.9

86.1 98.5

77.8

RFPA Module

69.6 61.3

Temperature contours are in deg. C

53.0

48.9

44.8

Figure 9.5 Temperature pattern inside and outside of a mobile phone, including that of its RFPA module. Temperature contours are in ◦ C. Courtesy: IEEE, Proceedings of the 44th Electronic Components and Technology Conference, pp. 411–420, 1994.

9.2.2

RFPA thermal design in a typical radio base station In contrast to RFPA devices of about 1 W RF output power capability used in a handheld mobile phone, the RFPA devices used in wireless RBS typically deliver RF output power in the range of 37 dBm–54 dBm (5 W–250 W) [13]. Typically, these RFPAs are operated in a highly backed-off condition from their P1 dB compression point in order to meet the linearity requirements. In such a mode of operation of an RFPA, the RF efficiency is substantially reduced. Thus, depending on the operating mode, these high-power RFPA devices have an RF efficiency in the range of 10% to 65%, hence they output a large amount of waste heat, ranging from a few watts to in excess of 200 W from a single RFPA component. One faces many challenges in creating thermal solutions for such RFPA devices. In this section, we will briefly give an overview of thermal design and thermal control of such high-power RFPAs in an RBS. Examples of equipment used in various RBS are displayed in Figure 9.6. We will focus on the most common type, the macro RBS. A typical macro RBS antenna tower is shown with its three sector antennas. At the foot of such a tower, there is typically a building of

9.2 RFPA thermal design – basics

417

Towertop Amplifier

Tower Antenna Macro Radio Base Station Macro Radio Base Station Controller

Pico Basestation

Figure 9.6 Radio Base Stations. Courtesy: Freescale Semiconductor Inc., Radio Frequency

Division.

RBS Controller

Forced Air Cooled RFPA Rack

Figure 9.7 Radio Base Station Controller and a typical rack mounted RFPA pallet. Courtesy:

Freescale Semiconductor Inc., Radio Frequency Division.

about 5 × 3 × 3 m (15 × 10 × 10 ) in size which shelters various electronic equipment including the base station controller. Waste heat from the electronic equipment housed in such a building is typically removed by forced air cooling/conditioning. A typical Base Station Controller along with one of its forced air-cooled RFPA racks is shown in Figure 9.7. Cooling fans force air flow in the range of 1 m/s to 3 m/s (200 lfm to 500 lfm) over the cooling fins of a heatsink that are physically attached to the RFPA pallet. An end view of a typical pallet with the attached aluminum fin heatsink is shown in Figure 9.8. A simplified description of the thermal stack-up in an RFPA pallet is shown in Figure 9.9a and 9.9b. A high-power RFPA component is soldered or physically bolted to a metal insert, typically a Cu coin, in the RFPA pallet. The pallet consists of an RFPA pcb with all the supporting components with the Cu inserts. The thermal interface between the RFPA component and the Cu insert is solder or thermal grease or a mechanically compliant high thermal conductivity pad. The pallet is physically bolted to an Aluminum finned heatsink, again using thermal grease or a thermal pad at the interface. The Al

418

RF power amplifier thermal design

RFPA component RFPA pallet Al finned heatsink

Figure 9.8 A closer view of an RFPA pallet with its attached Al finned heatsink. Courtesy: Freescale Semiconductor Inc., Radio Frequency Division.

RFPA Die Thermal Grease or Compliant Thermal Pad

RFPA Package Flange PCB

Cu coin / Heat spreader

Aluminum Chassis / Heatsink (a) Tj Rjc Tc

Ta

Rinterface Rheatsink-to-air

(b) Figure 9.9 (a) RFPA pallet thermal stack-up pictorial view; (b) stack-up thermal resistance, Rja = Rjc + Rinterface + Rheatsink .

finned heatsink, in turn, is cooled by air flow driven by a fan. Heat flow from the device to the ambient is schematically described as through resistors marked as Rjc , Rinterface , and Rheatsink-air . Each of these thermal resistors will be discussed in greater detail in later sections. A typical RFPA component and its simplified physical construction are shown in Figure 9.10a and 9.10b. This component would be classified as an air-cavity metalceramic RFPA transistor. An alumina ceramic window-frame is brazed to a metal flange using a high-temperature brazing material such as CuAg, creating the air-cavity. Metal flanges are typically of WCu or Cu laminates having a thermal conductivity k ranging

9.2 RFPA thermal design – basics

419

(a)

Ceramic window frame

Ceramic Lid

Air cavity on die and wires

Multiple die. (b)

Plated leads

Metal flange

Figure 9.10 (a) RFPA component device: air-cavity metal-ceramic package; (b) RFPA component device: a simplified cross-sectional view.

from 180 W/m K to ∼250 W/m K. Multiple active RF transistors and passive matching components are bonded to the metal flange inside the air-cavity using metallurgical die attach materials such as AuSi eutectic or AuSn eutectic. These die bond materials have high k typically ranging from 100 W/m K to 50 W/m K. Wirebond interconnects and lid seal complete the package. From a heat flow viewpoint, dissipated heat from the active regions of the device flows through the thickness of the device, through the die attach interface, through the metal flange of the transistor, through interfaces such as solder or a conformable conducting material and finally into an external heatsink to which such high-power devices are typically attached, either by reflow solder or by being bolted down. Heat flow is by conduction, the flow is through a series of very low thermal resistance paths, thus assuring a very low overall thermal resistance.

9.2.3

Basic heat transfer processes and their role in an RFPA thermal performance In this section we will briefly review the basic physics related to thermal energy transfer in a material body or among material bodies. Four modes of heat transfer will be discussed:

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conduction, convection, radiation, and phase change. Along the way we will point out what role each heat transfer mode plays in the thermal performance of an RFPA.

Conduction The flow of thermal energy in an RFPA from the device junction through the rest of the device and subsequently into the component packaging structure and, finally, to the attached heatsink structures is mostly governed by the conduction heat transfer process. An excellent analysis of conduction heat transfer can be found in many text books. [14, 15]. As we briefly review conduction heat transfer, we will introduce material properties such as thermal conductivity and thermal diffusivity. Conduction heat transfer in a material body occurs when there is a temperature difference between two points in the body; it also occurs between two material bodies at different temperatures in contact with each other. Temperature difference is the driving force for the flow of thermal energy from a higher temperature region to a lower temperature region. At a microscopic level, conduction heat transfer is due to the flow of phonons (quantized lattice vibrations in the material body) and the flow of electrical carriers such as electrons. Conduction heat transfer can be in the steady state or in the transient mode in relation to time. In the case of steady state thermal conduction, the temperature distribution in the material body has reached a fixed value that does not change with time and thermal energy flows from a region of higher temperature to a region of lower temperature. In the case of transient thermal conduction, the temperature at any point in the heat flow path varies with time. In its simplest form, steady-state heat conduction along one dimension can be mathematically described as   dT (9.2) Q = −k A dX where Q is the heat transfer rate, (dT/dX) is the temperature gradient along the heat flow path, and A is the cross-sectional area for heat flow. k, the proportionality constant, is a macro property of the material called thermal conductivity. It is measured in units of W/m ◦ K. Materials with higher values for thermal conductivity support a larger flow of thermal energy through them for a given temperature gradient compared to materials with lower values. Metals have generally higher values for thermal conductivity compared to dielectrics. For real materials, thermal conductivity values range more than five orders of magnitude with diamond at the high end of the spectrum through to air at the lower end. Equation (9.2) can be generalized for heat flow in three dimensions in a material body where the temperature is changing with time and the material body includes heat sources and heat sinks       d kdT d kdT d kdT dT dX dY dZ + + + q = ρc (9.3) dX dY dZ dt where q is the heat energy generated per unit volume, ρ is the mass density of the material and c is specific heat of the material. For materials with homogeneous thermal

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conductivity (i.e., thermal conductivity is the same along the X, Y, and Z directions in the material), then the equation simplifies to d2T d2T d2T q ρc dT + + + = . d X2 dY 2 d Z2 k k dt

(9.4)

The material property k/ρc is called the thermal diffusivity. Thermal diffusivity is a macro material property in the description of transient heat flow by conduction in a material body. The larger this value is for a material, the faster will heat flow through that material. This property is measured in units of m2 /s. In a later section these properties will be discussed in some detail for those materials used in the creation of an RFPA.

Convection The flow of thermal energy from a finned heatsink attached to an RFPA pallet to the free air or the air flowing over or through it is by convection. Convection is the key heat transfer process in cooling the equipment in an RBS. Substantial expenditure is incurred in the hardware construction (finned heatsinks, air-moving fans, air-filters, and air cooling equipment) and its operation (fans, pumps, and refrigeration of air mass) to remove and dispose of the waste heat from an RBS. Detailed discussions on convective heat transfer are treated in various books [16, 17, 18]. As we briefly review convection, we will introduce the concept of convective heat transfer coefficient, a phenomenological parameter, measuring the efficiency of heat transfer. Heat transfer from a solid body to a fluid such as air or water at a different temperature is generally governed by convection. If the fluid in contact with the solid is stationary, then the heat transfer is still by conduction but if the fluid is in motion relative to the solid, then the temperature field in the boundary layer, that is the fluid layers in contact with the solid body, is affected by the fluid flow. In the simplest representation for the energy flow from the solid to a flowing fluid, Newton’s law of cooling can be used and is presented in an analogous manner to that of conduction: Q = h conv A(Twall − Tfluid )

(9.5)

where Q is the heat transfer rate, Twall is the surface temperature of the solid, Tfluid is the free stream temperature of the flowing fluid and A is the cross-sectional area for heat flow. hconv , the proportionality constant, is called the convective heat transfer coefficient. It is measured in units of W/(m2 ◦ C). It depends on many parameters including the fluid properties such as viscosity, thermal conductivity, specific heat and density. If the fluid flow adjacent to the solid wall is due to the density gradients in the fluid near the solid wall, the process is called natural convection or free convection. If the movement of the fluid is caused by external forces such as fans, pumps, the process is called forced convection. Typical values of convective heat transfer coefficient are summarized in the Table 9.1. Heat transfer efficiency for forced air cooling can be an order of magnitude superior to that from free air alone. The range shown for forced air is mainly due to the amount of air mass moved over the surface and the degree of turbulence (mixing) in the air created by the moving air. The heat transfer coefficient for liquid water can

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Table 9.1 Typical values of convective heat transfer coefficients Mode

hconv [ W/(m2 ◦ C)]

Free convection in air Forced convection in air Forced convection in water

10 10–100 100–1000

be an order of magnitude higher than that due to forced air. This improved heat transfer efficiency for water is primarily due to its very high heat capacity, ρc, compared to air. The flow of thermal energy from a heatsink attached to an RFPA to the external ambient, be it free air or by forced cooled air, is by convective heat transfer.

Radiation In the thermal control of electronic equipment in terrestrial applications, radiative heat transfer plays a relatively minor role; however, it is the dominant heat transfer mode in the disposal of waste heat in space applications. Detailed discussions on radiative heat transfer are treated in various text books [19, 20]. As we briefly review radiation, we will introduce the material property of emissivity and the concept of radiative heat transfer coefficient, a phenomenological parameter measuring the efficiency of radiative heat transfer. Unlike in the cases of conduction and convection where thermal energy transfer occurs through material mediums, radiative heat transfer can occur through vacuum. Thermal energy transfer by radiation is part of a general process known as electromagnetic (EM) radiation. In the large spectrum governing EM radiation from the long wave (wavelength ∼ meters) radio waves to very short wave length gamma rays (wavelength ∼ nano-meters), thermal radiation falls in the range of 0.1 to 100 micro-meters. Radiative energy emitted by a body can be described by the equation E = σ ε AT 4

(9.6)

where E is the energy radiated per unit time and per unit area, A is the surface area of the radiating body, T is its absolute temperature, σ is the Stefan–Boltzmann constant, and ε is a material property of the radiating body called its emissivity. The emissivity property ranges from 0 to 1; it is 0 for a perfectly reflecting body and 1 for a perfect black body. Most real radiating surfaces fall in between and generally are referred to as grey bodies. It is worth mentioning that the value of the emissivity ε is not based on a visual observation of how black or grey the radiating surface looks visually; it is how black or grey the body is at the wave length of 0.1 to 100 μm corresponding to thermal radiation. As in the case of convective heat transfer, it is a convenient practice to describe radiative heat transfer by: Q = h rad A1 (T1 − T2 )

(9.7)

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where A1 is the area of radiating body 1, T1 and T2 are the temperatures of the two bodies exchanging heat by thermal radiation, and hrad is the radiative heat transfer coefficient. Using this representation, it is easier to combine radiative heat transfer with convective heat transfer calculations. However, in this form the parameter hrad is a strong function of the temperature of the radiating body. As mentioned earlier, in terrestrial applications of an RFPA, hrad is very small in comparison to hconv and thus can be ignored without much error.

Phase change cooling The most commonly known example for phase change cooling is boiling of a liquid from a hot surface and the associated vaporization of the liquid. The evaporating liquid extracts thermal energy from the solid surface it is in contact with and undergoes a phase change from liquid to vapour. Boiling in the liquid occurs when the liquid is maintained at a temperature above its saturation vapour pressure temperature and driven by the temperature difference between the hot surface and the liquid’s saturation vapour pressure temperature. Boiling is a very complex phenomenon, with many stages starting as nucleate boiling, transitioning into unstable film boiling and finally reaching stable film boiling. Even now a full understanding has not been established in the unstable transition region of nucleate to film boiling and intensive research is on-going. Readers are referred to good discussions on boiling heat transfer in the references [21, 22]. Similar to convection and radiation, a simplified heat transfer coefficient hboiling can be assigned to boiling heat transfer as described in the following equation: Q = h boiling A (Twall − Tsat )

(9.8)

where Q is the heat flow rate, Twall is the surface temperature of the solid, Tsat is the temperature at which the liquid reaches its saturation vapour pressure and A is the surface area for heat flow. Boiling heat transfer rate (Q/A) can be in the range of 10 W/cm2 to 100 W/cm2 for water, one of the highest compared to other heat transfer modes. However, boiling heat transfer is not often used in RFPA cooling applications due to numerous challenges such as instability associated with nucleate boiling, material compatibility, hardware complexities, and long term reliability.

9.3

Thermo-physical properties of materials in an RFPA We have already introduced the definitions of the material properties thermal conductivity k and thermal diffusivity k/ρc in the context of explaining conduction heat transfer. Here, we will discuss in more detail these material properties as well as the thermomechanical property of coefficient of thermal expansion, CTE, for certain materials of interest in the construction and operation of an RFPA since they have a large impact on its thermal performance. Table 9.2 summarizes typical values for k of device materials (Si, GaAs, GaN and SiC), package substrate/flange materials (CuW, Cu Laminates, Cu, AlN, and BeO), die attach materials (AuSi, AuSn, PbSnAg, Ag-filled epoxy), thermal interface control

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Table 9.2 Thermo-physical properties of various materials used in the RFPA hardware construction

Material

Thermal conductivity (W/m K)

Silicon GaAs GaN

148 50 170

2.33 5.3 6.2

0.71 0.3 0.5

SiC (6H crystal)

460

3.2

0.7

AuSi (4% Si) AuSn (80/20) PbSnAg (high lead >90%) Ag epoxy WCu (80/20) Cu laminates (Cu-CuMo-Cu) Cu AlN Al2O3 (96%) BeO Diamond Thermal grease Thermal pad (graphite pad)

95 50 35 ∼10 180–200 220–250 390 60–190 20–30 210–230 500–2000 3 In plane: 240 Thickness Direction: 5 167

1.57

0.15

Al alloy (6061)

Density (g/cm3 )

Specific heat (J/g K)

15.6 8.95 3.5 3.8 2.1–2.5 3.5

2.7

0.385

0.9

CTE (ppm/K) 2.6 5.7 3.2 (orthogonal) 5.6 (parallel) 4.3 (orthogonal) 4.7 (parallel)

7.6 ∼8–9 16.5 4.5 6.5 6–8.5 ∼1.5 In Plane: ∼1 Thickness Direction: 30 24

Note: All properties are at 300 ◦ K. All values provided here should be considered as guidance; for rigorous design/research work, consult original literature.

materials (thermal grease, compliant thermal pad) and heat sink materials (Cu, Al alloy); in addition, it also has entries for a few other thermo-physical properties (such as density, specific heat and coefficient of thermal expansion). General references are cited [23, 24] to literature to look up the thermo-physical properties for many of these materials of interest. Some general discussions on the behavior of k are in order. Composition and purity of the material generally affect its k. Typically, the purer the material is, the higher its k. Typically, alloys and intermetallics have lower k compared to the pure elements that make up the alloy. A good example would be pure Cu versus alloys of Cu such as Cu-151 and Cu-194; all three Cu materials are typically used in RFPA packaging applications. Compared to pure Cu (k = 385 W/m K), these alloys have lower values of thermal conductivity e.g., Cu-151 has k = 350 W/m K while Cu-194 has k = 240 W/m K, 60% lower than pure copper. Added elements in the pure material to create the alloys typically create new grain structures; the grain boundaries cause more scattering centers for the phonons and electrons which are the carriers of thermal energy in the material body, leading to a reduced k value for the alloys. Increased temperature typically adversely

Thermal Conductivity (W/m/K)

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1.00E+03 8.00E+02 6.00E+02 4.00E+02 2.00E+02 0.00E+00 0.00E+00 1.00E+02 2.00E+02 3.00E+02 4.00E+02 5.00E+02 6.00E+02 7.00E+02

Temperature (K)

Figure 9.11 k of Si as a function of temperature.

affects k for certain classes of material. For example, k of Si drops from about 148 W/m K to about 100 W/m K as the operating temperature of Si rises from about 25 ◦ C to 150 ◦ C. As a consequence, the thermal resistance of the Si device will be higher at a higher operating temperature. This needs to be taken into account in the thermal design of a high-power RFPA using Si transistors dissipating substantial heat. In contrast, the thermal conductivity of some types of material do not show much dependency with temperature. Good examples are metals (Cu), metal alloys (Cu-194, Cu-151), metal composites (CuW, CuMo, and Cu-CuMo-Cu laminates), and intermetallics (AuSi, AuSn). For these classes of material, thermal energy is predominantly carried by the charge carriers such as electrons and scattering is dominated by the fixed grain boundaries in the material and not by the electron-phonon scattering, thus there is a weak to no dependency on temperature. Comparing the thermal conductivity of RFPA device materials (Si, GaAs, GaN, and SiC) at room temperature of 20 ◦ C, SiC has the highest value, about three times higher than Si, while GaAs has the lowest value, about 2.5 times lower than Si, and GaN is similar in value to Si. Thus, in a steady-state thermal flow situation with a similar device layout, the thermal resistance of a GaAs device will be the highest, the SiC device the lowest, and a GaN device will be comparable to a Si device. The detailed behavior of k versus temperature of Si is shown in Figure 9.11. In the thermal design of a high-power RFPA using Si transistors then such detailed knowledge must be taken account of. In an effort to reduce the thermal resistance in a high-power RFPA, the device package flanges use materials of increasingly higher k values. CuW with a k value of about 180 W/m K had been the work-horse for many years. This has been replaced in many applications [25, 26] by Cu laminates (Cu-CuMo-Cu and Cu-Mo-Cu) with a k value of about 250 W/m ◦ K. In certain cases, Cu with an even higher k value of 385 W/m ◦ K is used for RFPA package flanges. In the construction of an RFPA transistor package, materials of differing strength and coefficient of thermal expansion (CTE) are joined together at various temperatures. Typical examples are the joining of an alumina ceramic window frame to a metallic flange material such as CuW or Cu-CuMo-Cu using a high-temperature brazing material, e.g., CuAg, to create an air-cavity transistor package. Such a manufacturing process creates

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a very large stress due to the mismatch in the CTE values between alumina and the Cu-laminate flange and the high-temperature brazing. This can affect the robustness of the transistor package and can manifest itself in a dramatic manner such as ceramic window-frame cracking or severe de-lamination. It can also have a more subtle impact such as warping of the flatness of the flange, which can potentially result in higher interfacial thermal resistance between the RFPA component package and the next level assembly. Thus, the choice of package flange material is usually a compromise between the desire to get the highest k value for the flange material versus the need to closely match its CTE to the ceramic window-frame. Substantial technical and trade literature exists [27] on the topics of tailoring the compositions of CuW and CuMo, and of tailoring the relative thicknesses of the laminates such as Cu/CuMo/Cu, and of controlling the amount of cross-rolling various layers in creating the transistor flange material for an RFPA package header. In the making of very high-power RFPA devices, there are three very commonly used metallurgical material systems for joining the semiconductor device to the flange (commonly called die attach materials): AuSi eutectic hard solder, AuSn eutectic hard solder, and PbSnAg soft solder. Achieving a high-quality die attach joint is critical in realizing low thermal resistance for the device as well as for creating a robust product under power and temperature cycling stresses of the RFPA that it will be subjected to during its operational life. The thermal resistance of such joints and contacts will be discussed later in further detail. Since such joints are very thin, of the order of 5 μm for AuSi eutectic, 25 μm for AuSn preform- based attach, and 40 μm for PbSnAg solders, k alone does not play the main role in determining the joint’s thermal resistance; the quality of the joint (as determined by any voids at the interface and in the bulk of the die bond) plays an equally important role in determining the joint’s thermal resistance. As in the joining of a ceramic window frame to the metal substrate, the joining of the semiconductor device to the package flange material requires careful attention to minimizing the thermo-mechanically induced stresses in the device material and achieving the required flatness for the header. k values for the three joining materials are compared in the Table 9.2; AuSi has the highest k value (about 100 W/m ◦ K) and enables the lowest thermal resistance for the joint between the Si RFPA device and the package header; however, it is also one of the most demanding in manufacturing discipline to achieve a high-quality joint. AuSi, being a hard solder, is not forgiving in absorbing CTE mismatch induced stresses; thus extreme care must be taken in managing the CTE mismatch between the Si device and the package flnge material. This explains the development of various material systems such as CuW, CuMo, Cu-CuMo-Cu laminates where both CTE and k values are optimized to provide the best thermal solution for the package flange. PbSnAg soft solder, although having the lowest k value (35 W/m ◦ K) among the three metallurgical diebond materials mentioned, reduces the thermomechanical stress in the joint under low duty-cycle thermal fatigue stress conditions, thus enabling the joining of a thermo-mechanically mis-matched structure such as a Si device to Cu flange in a high-power RFPA device. Due to its desirable low duty-cycle fatigue behavior, PbSnAg-based soft solder die attach is extensively used in high-power Si RFPA device packaging. AuSn reform-based die attach is less commonly practiced for

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427

Si power devices; however, it is very commonly used in bonding GaAs and GaN RFPA devices to metal flanges. Typically, AuSn die attach thermal performance falls between that of AuSi eutectic die attach and PbSnAg solder die attach. Finally, there is another class of die attach material, outside the class of metallurgical die attaches, that is used in RFPA device construction; this is Ag-filled epoxy adhesives. They have relatively low k values (in the range of 5 W/m ◦ K to 10 W/m ◦ K) but these epoxies typically handle the mis-match induced thermo-mechanical stresses well. However, their bond strength typically degrades with moisture and increased temperature. Typical bond line thickness falls in the range of 25 μm to 50 μm. For these reasons, these Ag-filled epoxies are typically used for die attach in low-power RFPAs such as those used in portable products, general purpose amplifiers, and in predrivers in a high-power RFPA lineup. We described earlier that in typical use the high-power RFPA component is physically secured to a Cu pallet/heatsink to enable removal of the waste heat (Figure 9.9). If the RFPA component is not soldered to the Cu pallet, then it is mechanically fastened. In such a scenario, to reduce the thermal interface resistance between the RFPA component and the Cu pallet, thermal grease or a mechanically compliant thermal pad is used. Thermal grease is typically silicone fluid filled with metal oxide powders with an effective k value of ∼3 W/m ◦ K [28]. They fill the interstitial space between the two mating metal surfaces. The thermal interface consists of two parallel paths for heat flow, one through multiples of metal-metal point contacts and the other through multiples of interstitial space filled with thermal grease. The silicone fluid can be lost or the joint can become dry, thus their long-term effectiveness is a concern. The other class of material is a physically compliant thermal pad. Though there are numerous types, the most effective ones are pyrolytic graphite such as TgonTM [29]. Such thermal pads are polymeric material with embedded pyrolytic graphite fibers. They are available in various thicknesses, 0.125 mm to 0.5 mm. They have k values ∼200 W/m ◦ K in the planar dimension and ∼5 W/m ◦ K in the thickness dimension of the pad. In RFPA applications, metal foils (such as Indium or Cu or Solder) are also used.

9.4

Tools to characterize and predict the thermal performance of RFPAs A key metric in assessing the thermal performance of a component such as an RFPA is Rjc (or θ jc ), the junction-to-case thermal resistance. Rjc is pictorially explained in Figure 9.9b. This metric is analogous to the electrical resistance, R. The dissipated power in the device, P (analogous to the current I in an electrical circuit), flows from the device junction to the heatsink under the driving force of the temperature differential Tj –Tc (analogous to voltage difference in the electrical circuit), overcoming the thermal resistance Rjc (analogous to electrical resistance, R). For a quantitative determination of Rjc , one needs to determine the parameters Tj , Tc , and P. In this section we will address this area, with a focus on measuring and predicting Tj , the device junction temperature. Experimental thermal characterization and computer aided thermal modeling are two approaches to characterize and optimize the thermal performance of electronic devices and systems. Experimental thermal characterization usually can provide a direct and

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accurate measurement of device or package temperatures; however, assembling the experimental hardware, the effort to prepare samples, and the number of experiments needed all take up considerable time and expense. Also, any measurement has associated errors arising from calibration, methodology, operator, and sample distribution. On the other hand, advancements in modeling and simulation software as well as computing speed make thermal simulation effective in analyzing and predicting the thermal performance and thus offers an attractive alternative. However, the simplifications and assumptions made in constructing the computer model of the physical reality, and the uncertainties in our knowledge of material properties and boundary conditions, all impact the accuracy of the simulated thermal results. A careful use of both experimental characterization and computer-aided simulation can make up the deficiencies in each and provide realistic and accurate results. In this section we will review both approaches and their applications towards thermal characterization of high-power RFPAs.

Measurement: methods, tools, current status During experimental thermal characterization of an RFPA device, we typically measure the temperatures of the active device junction, the mounting chassis, and the ambient. In addition, we measure any relevant boundary condition such as air flow conditions. We will first address the measurement of surface temperatures of a component package or module or heatsink using a thermocouple thermometer. A thermocouple thermometer is a temperature sensing junction created by joining two dissimilar metals together. When such a thermocouple junction is heated or cooled, a voltage is produced that can be measured and correlated to temperature. Thermocouples are available as wires with different combinations of metals or calibrations. The four most common types of thermocouple are J, K, T, and E. As an example, Type J thermocouple is made of the dissimilar metals iron and constantan, and can be used in the temperature range of −40 ◦ C to +750 ◦ C and has a temperature sensitivity of 55 μV/◦ C. Excellent product information is available on thermocouples [30]. However, a number of precautions need to be taken in applying a thermocouple to measure surface temperatures accurately. The diameter of the thermocouple wire should be small such that heat loss along the wire does not cause an erroneous reading [31] of the surface being measured; gauge 36 or gauge 40 wire is preferred. The thermocouple bead should make good physical, and thus thermal contact, to the surface being measured. When we refer to device temperature, typically it is the device junction (also called channel) temperature; for many RFPA devices, the device junction is typically located close to the surface of the die (for an LDMOS device, it is about 10 μm below the surface), thus the surface temperature measured on the die is nearly the same as the junction temperature. Techniques to measure the operating temperature of a semiconductor device can be broadly grouped into two categories, direct and indirect methods. Direct methods include infrared (IR) thermometry [32, 33], liquid crystals [34], and thermographic phosphors [35] which allow direct mapping of the surface temperature of the device. Among these direct techniques, IR thermometry is the only technique capable of quantitative temperature measurement; the other two techniques are qualitative. The

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429

indirect techniques use a temperature sensitive electrical parameter of the semiconductor device (such as Vf for a diode, or Veb for a bipolar transistor, or Vds for a FET) to measure the device temperature [36]. However, this technique typically provides only an average temperature for the chip and is prone to many errors and difficulties when applied to RFPA devices. Thus, Infrared Thermometry is the most commonly used technique to provide direct, quantitative thermal mapping of an RFPA device. Before we address Infrared Thermometry in detail, we will briefly review other measurement techniques that are commonly used in characterizing the thermal performance of electronic devices, packages and modules in general. In the context of selecting or developing a suitable package to house a semiconductor device, one may use a thermal test chip or an active device to thermally characterize the package or module. In such an approach a calibrated (with respect to temperature) electrical parameter such as the forward-biased diode voltage (Vf ), or forward biased device junction voltage (such as Vds for a FET or Veb for a bipolar transistor) is used as temperature sensitive parameter to measure the device temperature. Abundant literature exists on this approach of using active devices [36, 37] and thermal test chips [38] to perform such a task. If one were to use a thermal test die to characterize a package or a module, the typical thermal test die will consist of a separate heating source (typically, a thin-film resistor deposited on the die) and temperature sensors e.g., diode, transistor or metal-film resistor, all integrated into the test die. Typically, such sensing diodes are calibrated for Vf versus T prior to use. They typically have a temperature sensitivity in the range of 2 to 3 mV/◦ C. To improve the accuracy in measuring the voltage drop across the temperature sensing diode, four-wire Kelvin contacts should be used (i.e., separate forcing and sensing lines are used to contact each sensing diode). In the absence of the availability of thermal test chips, active devices (transistors, ICs) can be used to provide both heating and temperature sensing functions. In such a situation, an electronic switching circuit is used to switch the device from a powering function to a sensing function. With the use of electronic switching, the time delay between powering and sensing can be made very short (of the order of a few tens of micro-seconds). Shorter delay times are preferred, but one needs to allow the electrical transients due to switching in the measurement region of the active device to die down so that one captures the true electrical signal representing the temperature effect. Nevertheless, the junction region will cool rapidly during this delay time. One needs to balance these two considerations in selecting a suitable delay time. There are known techniques to calculate and correct for the cooling that occurs in the sensing region before the temperature sensing is performed. Abundant literature exists on this methodology [39–41]. Getting back to IR thermometry, excellent IR measurement equipment is commercially available to perform accurate quantitative temperature measurements [42]. Figure 9.12 displays a state-of the-art IR microscope that is typically used in characterizing RFPA devices. Objects in the temperature range 0 ◦ C–200 ◦ C emit infrared radiation in the EM spectrum of wavelength 2 μm–10 μm. The emitted radiation is governed by: q = σ ∈ AT 4

(9.9)

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RF power amplifier thermal design

Figure 9.12 An IR microscope with an RF test bench.

where q is the radiant flux/unit area/unit solid angle in W/cm2 -ster, σ is the Stephan– ◦ Boltzmann constant (5.673 × 10–12 W/cm2 K4 ), ε the emissivity and T is the temperature in ◦ K. An IR transmitting (or reflecting) lens system collects the heat radiation from the device under test (DUT) and focuses it onto a liquid nitrogen cooled InSb detector. Stateof-the-art equipment uses focal plane array (FPA) detectors, thus a thermal image of the DUT’s entire surface is brought into focus. The signal from the detector is processed by suitable electronics and displayed as a color intensity map. The color intensity map is converted to a quantitative temperature map by a calibration procedure using a blackbody radiator. Various lens choices enable spatial resolution at the DUT level of the order of 2 μm and a temperature resolution of the order of 0.1 ◦ C for a DUT at about 80 ◦ C. Since the radiant energy from the DUT is a function of both the temperature and the emissivity of the surface, the emissivity needs to be known to arrive at the temperature from the image. Current day IR microscopes have special algorithms to determine the emissivity of a DUT pixel-by-pixel through measurement of radiant images at known temperatures. However, the emissivity determining procedures that are typically available as part of the measurement equipment can introduce errors for materials like Si that are IR translucent. To overcome this difficulty, typically the surface of a Si DUT is uniformly coated with an IR-opaque high emissivity paint. This procedure assures fixed emissivity for the surface of the DUT, thus simplifying the temperature determination and increasing the accuracy. The challenges in selecting a coating material and applying

9.4 Tools to characterize and predict the thermal performance of RFPAs

431

Si LDMOS RFPA at 20W output RF power

• Max die temperature (Tj max) = 129.7°C

• Case temperature (Tc) = 73°C • Calculated Pdiss = 72.93W

Rjc = (129.7 – 73)°C / 72.93 W = 0.78°C/W

0.0

43.2 86.5 Temperatrure (°C)

129.7

Figure 9.13 Temperature profile of an RFPA device captured by an IR microscope.

it to an RFPA device surface such that it has low to no impact on the RF performance of the device are addressed in the literature [43]. A typical infrared thermal profile for a Si LDMOS RFPA device is shown in Figure 9.13. An RFPA device may exhibit temperature nonuniformities; however, the highest measured device temperature (Tjmax ) is used in characterizing the thermal performance metric Rjc .

Modeling and simulation: methods, tools, current status The mathematical simulation of fluid flow and heat transfer involves solving simultaneously the conservation of mass (continuity equation), conservation of momentum, and conservation of energy equations. This involves seeking a solution for a set of coupled, nonlinear second-order, partial differential equations, involving variables such as u, v, and w for the velocity of the flowing fluid, P for the pressure, and T for the temperature. Needless to say, this is a very complex undertaking. However, state-of-the-art software tools exist today to handle this class of problem very well. There are two main approaches, one based on finite volume/difference methods (FVM) and the second based on finite element methods (FEM). FVM is used in many CFD tools. For electronic cooling applications, many CFD tools have been tailored to focus on fluid flow and heat transfer only. In the use of a CFD tool, the spatial domain is discretized into small cells to form a volume mesh; the conservation equations for these discretized volumetric spaces are expressed in algebraic form, then suitable algorithms solve the equations of continuity, momentum and energy simultaneously. The CFD tool not only determines the fluid field, but it also solves any solid conduction within the computational domain (conjugate solution). In CFD analysis, there is no need to assume convective heat transfer correlations at the solid-fluid boundaries; exact fluid fields external to the solid surfaces are predicted during conjugate analysis. Thus, CFD tools have greater appeal for system level thermal simulations. In the FEM approach, the conservation equations are solved by approximating continuous quantities at discrete points spaced into a grid or mesh. Generally, FEM can

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handle more complex geometrical shapes coupled with large differences in the thermomechanical properties. At the component level analysis where conduction is the dominant heat flow process and where reliable boundary conditions can be used, FEM has greater appeal since it can handle very complex shapes with large differences in levels of detail, from the die active area layout to a completely assembled component device, all in one model. Thus, at component level analysis, typically FEM tools are used; empirical convective and radiative heat transfer correlations are applied to all the boundary surfaces of the package/PCB. Thus, a-priori engineering knowledge/judgment is needed to achieve good results. Furthermore, temperature profiles obtained from such an FEM analysis can be directly used in subsequent thermo-mechanical analyses to assess the various structural stresses in the component. ANSYS [44], Abaqus FEA [45], MSC Sinda [46], COSMOS [47] are some of the R [48], ANSYS leading FEM simulation tools commercially available. FloTHERM Icepak [44], ANSYS FLUENT [44] are some of the leading CFD simulation tools. To execute efficiently on any of these simulation tools mentioned here, it is imperative to have good models that truthfully represent the physical reality. Key steps and tools in building good models are: R r producing a CAD geometry for the structure using a program such as AutoCAD [49]  R  R or Pro-E [50] and/or using ECAD programs such as Cadence Allegro Package R Designer [51] or Mentor Graphics [52]; r assigning material properties (thermal conductivity, mass density, specific heat, viscosity) to the various physical regions of the model; r assigning proper boundary conditions such as a fixed temperature (e.g., ambient) to a reference location, and convective and radiative heat transfer coefficients at the heatsink surface in an FEM approach; r creating the mesh/grid with the appropriate level of detail (balancing the desired level of physical details versus model size and simulation time); r post-processing to display and extract the information (temperature, heat flux, fluidflow profile, contour plots of temperatures and air flow, numerical tables, etc.). Many of these supportive tools have become smart and user friendly. Thus, model building and simulation have become an integral part of RFPA thermal management.

9.5

RFPA thermal design and management – advanced In this section we will discuss in greater detail the thermal design and thermal management of high-power RFPA components. Though much of the discussion will generally be applicable to various RFPA device technologies, we will focus on Si laterally diffused metal oxide semiconductor (LDMOS) devices. The Si LDMOS device technology has many advantages such as high RF power gain, good efficiency, excellent linearity, and ruggedness, requiring only a single supply voltage, inherently good thermal structure, and all at low cost. Figure 9.14 compares two Si technologies, bipolar versus LDMOS. Bipolar transistors require complex packages as the underneath side of the

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9.5 RFPA thermal design and management – advanced

Gate

LDMOS

Drain

Bipolar

Source

n+

n+

Base p

p+

n–

sinker

p – epi backside metal

collector V = ~26V

p+ substrate

n+ substrate Pkg Metal Flange

• Source at Ground Potential • Vertical current flow

Emitter n+

Dielectric (Beo or AIN) Pkg Metal Flange

Figure 9.14 Cross-sectional view of Si LDMOS and Si Bipolar RFPA devices.

die is the collector and hence it requires an electrical isolator such as BeO or AlN to be inserted between the die and the flange. Also, as the emitter is on the top of the die, a bond wire is required to connect it to the flange which adds inductance and lowers the RF gain. In contrast, LDMOS transistors can be bonded directly to the metal flange as the underneath side of the die is the source. This results in lower source inductance and hence higher gain, lower thermal resistance, and simpler packages which are lower cost. Si LDMOS device technology has almost totally replaced Si bipolar technology for RFPA devices in wireless infrastructure base-station applications, and increasingly also in other high-power RF applications such as wireless broadcasting, industrial and avionics. LDMOS device technology has continuously evolved since the first generation in 1993 to the current eighth generation device structures [53], improving upon many RF performance metrics, notably efficiency, power density (W/mm of gate periphery), linearity, and ruggedness. To achieve the lowest junction-to-heatsink thermal resistance for an LDMOS RFPA, an integrated and comprehensive approach from Si device layout, die thinning, package material selection, assembly manufacturing processes, to device mounting in the end application is required. We will address each of these areas. The basic LDMOS device structure has three electrodes – drain, source, and gate. Current flow between the drain and the source is controlled by the gate. Heat dissipation occurs in the current flow path in the high-resistance region, creating increased temperatures. A simplified view of this heat source description is shown in Figure 9.15, highlighting the heat dissipating structure, marked as a “heat source finger.” In creating an RFPA transistor, multiple device fingers are laid out, as shown in Figure 9.16. Thermal resistance due to the heat source layout can generally be understood using the “spreading thermal resistance” concept. Spreading thermal resistance is inversely proportional to the geometrical size of the heat source and the effective thermal

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Heat Source “Finger” Gate Metal

Gate Drain 4mil Thick Silicon

Source Metal

drain-source pitch “one finger” 0

Figure 9.15 Cross-section of an LDMOS device structure, describing the heat source.

Transistor fingers (channel) Cross section plane Periodicity

Figure 9.16 Representation of an LDMOS RFPA device, showing multiple heat source fingers laid out in parallel array.

conductivity of the semiconductor material and flange combination on which the heat source is laid out. It can be written as a (9.10) Rspreading = kdth where a is a constant, k is the effective thermal conductivity of the semiconductor material and flange combination, and dth is the equivalent thermal diameter representing the heat source. dth is proportional to the square root of the area of the heat source. Thus, to reduce the spreading thermal resistance arising from device layout, we need to increase the active area. Furthermore, for a given heat source area, maximizing the bounding perimeter of the area reduces the spreading thermal resistance. Thus, in laying out highpower devices, it is common practice to divide the total active area into multiple small segments (such as multiple parallel fingers) and utilize various meandering patterns (such as interdigitated rectangles). In the previous section under design tools, it was mentioned that the field of thermal model building and thermal simulation have become

9.5 RFPA thermal design and management – advanced

435

Line Trace

Temperature (°C)

124.00 110.00 100.00 90.00 80.00 70.00 60.00 50.00 0 Distance (um)

50 27576

100

150

200 Pixel #

250

300

350 382

Save Line Trace to Text File

Figure 9.17 IR thermal image and the temperature line profile of an RFPA device. Temperature nonuniformities among the three active Si transistor chips as well within each chip are shown. Peak die temperature = 124 ◦ C at Tcase = 70 ◦ C.

very robust and thus it is common practice to simulate and optimize device layouts for improved thermal performance using such computer-based thermal models. In a typical LDMOS device layout, a single heat dissipating finger is a few micrometers (∼2 μm) wide, a few hundred micrometers (∼300 to ∼1000 μm) long, and located a few micrometers (∼10 μm) below the Si surface. Multiples of such finger-like line structures are laid out with typical pitch between the fingers in the range of 20 to 100 μm. The author has carried out a systematic study of many such lay-outs, leading to some general guidelines: r finer pitch between heat source fingers results in a higher temperature for an array of fingers; coarser pitch results in lower array temperature; r for a given array finger design (i.e., width, pitch), temperature profiles along the fingers are similar for central and outer fingers; for any finger, temperature peaks near the center of the finger and falls to a lower value towards the end of the finger; r arrays with longer fingers result in a higher temperature uniformity along the finger. Thus, to maximize the uniformity of temperature across and along an array of fingers, the layout should use a large number of long fingers. To minimize the thermal resistance due to layout, coarser pitch should be used within any other constraints such as realizing adequate active area for the intended RF power in a given size Si chip. Even with careful attention to the layout of the active area to minimize temperature nonuniformities, such nonuniformities do exist in an RFPA device. Figure 9.17 is an IR image of an RFPA with three active Si chips, showing some level of temperature nonuniformity between the three chips as well as within each chip.

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Observed temperature nonuniformities could be due to: (a) nonuniform RF excitation of a multifinger device caused by small differences in the amplitude and phase of the input RF signal feeding the device; this causes an associated nonuniform Pdiss in such a multifinger device array, (b) even with uniform Pdiss in a multidie/multifinger layout, due to the geometrical effects associated with heat diffusion, temperatures in the interior die/structure tend to be higher compared to temperatures in the die/structure near the outer boundaries, (c) manufacturing defects such as a die bond void could create local hot spots, thus causing temperature nonuniformities in the device, (d) thermal spreading effect of the underlying substrate also contributes to the temperature nonuniformities seen in the active devices. Another contributor to the overall device thermal resistance is that from the finite thickness of the Si chip itself. This thermal resistance is directly proportional to die thickness. Typical Si thickness in high-power RFPA LDMOS devices is about 100 μm whereas in the main-stream semiconductor devices, the typical die thickness is about 300 μm. There are many manufacturing challenges to overcome in thinning large diameter (200 mm) wafers [54] to 100 μm thickness and subsequently handling the wafers through backside metallization, transport and sawing. However, new product requirements such as stacked memory in consumer products (e.g., mobile phone with camera) have made a favorable impact in the development of wafer thinning technologies in the semiconductor industry. Backgrinding is the most common method to thin wafers. Backgrind usually leaves grind damage such as micro-cracks on the wafer surface; back-grind also leaves sharp wafer edges which become the weakest part of the wafer. Additional stress relief processing such as polishing, dry etch, or wet etch is usually necessary following back-grind. Such a follow-up process typically reduces the grind damage, reduces wafer stress and thus warping and bow in the wafer, and improves wafer and die strength [55]. Producing strong Si die from the wafer thinning process is essential to realize a high-assembly yield and a reliable product as the Si chip is die bonded to CTE mismatched metal flanges. In earlier discussions on thermal conductivity, we had mentioned that GaAs has lower thermal conductivity by about 2.5 times compared to Si. Hence, high-power GaAs RFPA devices are thinned to 25 μm to 50 μm thickness to reduce the thermal resistance due to the GaAs substrate. Thus, considerable manufacturing investment is needed to enable leading edge performance in high-power RFPA devices. Next, we will consider thermal resistance in the die bond, the interface joint between the RFPA die and the underlying metal flange. We described in an earlier section the general properties of and the relative merits of four different die attach materials used in the RFPA industry: AuSi, AuSn, PbSnAg, and Ag filled epoxy. To lower the thermal resistance in the die bond, we seek a high k for the die bond material as well as a void-free and thin bond line. AuSi eutectic die attach can fulfill all these requirements. AuSi die attach for high-power RFPA Si devices is typically accomplished by an in-situ metallurgical reaction between Si (being supplied from the Si die) and Au (supplied by the Au metallization on the back of the die and on the flange surface). An SEM view of a AuSi die attach cross-section is shown in Figure 9.18. A nearly void-free die bond with a bond line thickness of about 5 μm can be typically achieved with AuSi eutectic die attach. Thus, AuSi die bond provides the best die bond method available for high-power

9.5 RFPA thermal design and management – advanced

437

Figure 9.18 An SEM image of AuSi die-bond of an LDMOS Si RFPA device to a W/Cu metal flange. Bond line is thin (∼5 μm), of uniform thickness, and void free.

RFPA Si devices. Furthermore, AuSi die attach does not show any hardening or fatigue behavior after long thermo-mechanical cycling since, being a hard solder, it behaves elastically. Understanding the stress created in the Si and designing for the stress to be well below the strength of Si is key in the successful practice of AuSi die attach in high-power RFPA devices. It is well known that any void in the die attach interface can add additional thermal resistance to the path and it usually manifests itself as a hot spot in the active region of the die [56, 57]. AuSn die attach is less common in bonding high-power Si RFPA devices. However, it is one of the most common die attach methods in bonding high-power GaAs and GaN RFPA devices. Typically, AuSn die attach is accomplished with the help of a AuSn preform or predeposited AuSn solder, thus the bond-line thickness is in the range of 25 μm. The AuSn die attach interface layer typically has a higher thermal resistance compared to a AuSi die attach interface layer both due to its lower k value (∼50 W/m ◦ K versus ∼100 W/m ◦ K) and larger bond line thickness. PbSnAg die attach is very common in bonding Si power devices to a CTE mismatched substrate such as Cu because PbSnAg soft solder has excellent thermal cycle fatigue behavior. PbSnAg die attach is typically accomplished by dispensing molten liquid solder or solder paste, thus the bond-line is thicker and typically in the range of 40 μm. The PbSnAg die attach interface layer typically has higher thermal resistance compared to AuSi die attach interface layer both due to its lower k value (∼35 W/m ◦ K versus ∼100 W/m ◦ K) and greater bond line thickness. Ag-filled adhesive die attach is most commonly used in the manufacture of low-power RFPAs for various mobile devices and in the manufacture of general purpose amplifiers (GPA) and predriver PAs that have lower thermal dissipation. Typical bond-line thickness ranges from 25 to 50 μm. Ag-filled adhesive die attach has the highest thermal resistance compared to the other three metallurgical die attach methods both due to it having the lowest k value (<10 W/m ◦ K) and the highest bond line thickness (∼50 μm). Next in the thermal stack-up let us consider the thermal resistance due to the component device substrate, typically a metal flange in the case of a high-power LDMOS

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RF power amplifier thermal design

TWO BARE SURFACES IN CONTACT: 1

1

K1

2

X 2

K2 POINT CONTACT

POCKET OF AIR

0 INTERFACE =

X X + (Keff)pt Apt Kair Aair

Keff = K1K2 /

K1 + K 2 2

Keff 1 TO 4 ORDERS OF MAGNITUDE HIGHER THAN Kair Figure 9.19 Pictorial description of thermal contact resistance.

transistor. We discussed in a previous section the thermo-physical properties for a few flange materials such as CuW, CuMoCu, Cu-CuMo-Cu and Cu. k values range from 180 W/m K to 385 W/m K. The selection of the flange material and its thickness are driven by more than thermal considerations alone. Thermo-mechanically induced stress in the active device due to die attach, in the window-frame material such as alumina ceramic due to brazing, and the flatness of the finished component package all deserve careful attention. The CTE of the flange material, its modulus, and its geometric thickness all play a role in determining the overall flatness of the RFPA component package. Typically, the flatness of finished packages is in the range of –25 μm to +40 μm. Flatness can influence the interfacial contact thermal resistance between the RFPA device component and the Cu coin/Cu insert in the thermal stack-up. In Section 9.2.2 we presented a simple description of the thermal stack-up in an RFPA pallet, see Figure 9.9. A high-power RFPA component is soldered or physically bolted to a metal insert such as a Cu coin bonded or inserted into the PCB of the pallet, thus a direct heat flow path from the RFPA component to an external heatsink through the Cu coin is established. If the RFPA component is soldered to the Cu coin, then the interface’s thermal behavior is like that of a bonded interface; we have already discussed the thermal resistance in bonded interfaces in the context of die attach. Bond line thickness, void level in the bond, and thermal conductivity of the solder together determine the joint’s thermal resistance for the bonded interface. If the RFPA component is mechanically bolted or clamped to the metal insert/coin, then the interface’s thermal behavior can be described in terms of contact thermal resistance. In the thermal stack up we have been discussing, typically the pallet in turn is physically bolted to an Aluminum finned heatsink; again this interface’s thermal behavior can be described as another contact thermal resistance. At this point, it is relevant to discuss the concept of contact thermal resistance in general, and in the context of RFPA thermal management in particular. When two solid surfaces are brought into contact as shown in Figure 9.19, the interface in reality is made up of many point contacts between the two solid bodies with the interstitial space filled with air or a heat-sink compound such as silicone grease. Heat flow from one

9.5 RFPA thermal design and management – advanced

439

solid body to the other occurs primarily through these solid-to-solid point contacts and secondarily through the entrapped air or heat-sink compound in the interstitial space. Since the thermal conductivity of air is typically four orders of magnitude smaller compared to the thermal conductivity of a typical solid, the major contribution to the contact thermal resistance arises from the interstitial gap. Contact thermal resistance theory and a detailed survey are discussed in references [58, 59]. The contact thermal resistance is influenced by three considerations: 1. The geometry of the mating/contacting surfaces, e.g., shape (flat versus convex versus concave) and surface finish (smooth versus rough). 2. The thermo-physical properties of the contacting surfaces, e.g., k of the mating surfaces, k of any fluid medium such as air or thermal grease filling the interstitial gap in the contact region. 3. The mechanics, e.g., contact pressure, micro-hardness of the contacting surfaces. From the above qualitative description of the contact thermal resistance, it can be stated that the contact thermal resistance can be reduced by: r filling the interstitial space with a material of higher thermal conductivity such as thermal grease rather than entrapped air; r increasing the applied joint pressure, which enables more solid–solid point contacts; r reducing the surface roughness of mating surfaces; r reducing the micro-hardness of the contacting surfaces through modifying the surface with coatings. In typical RFPA applications, the RFPA device component’s mating surface flatness is in the range of –25 to +40 μm; the metal substrate of the RFPA device is typically metallized with a NiAu, or flash of Au (as in NiPdAu) or Sn. The Cu coin/insert in the heat-sink typically has a machined surface with a roughness of ∼1 μm to 2 μm. In the assembly of the RFPA device component to the pallet, typically thermal grease [28] or a compliant thermal pad [29] is used to reduce the contact thermal resistance. The contact thermal resistance between the RFPA device component and the Cu coin/insert in the pallet in a typical application is <0.1 ◦ C/W. The RFPA pallet with the Cu coin is typically bolted to the base of a finned Al heatsink. The last item in the thermal stack-up for the flow of waste heat from the RFPA device to the ambient air is the thermal resistance associated with the heat-sink. In a macro base station, typically forced air cooling is used; in lesser power applications, such as micro/pico base stations and remote radio heads, free air-cooled heatsink surfaces are typically used. Sizing of the heat-sink (volume, surface area for heat transfer to the flowing air) and its design (base plate dimensions, fin configuration such as fin thickness, height and pitch) are typically dictated by two considerations, namely available thermal resistance budget for heat disposal and available pressure drop for air flow. Usually, an optimization exercise occurs in trying to maximize the surface area for heat disposal such as a denser pitch between fins, a large form factor for fins (i.e., higher value for the ratio between fin height to fin pitch), and minimization of the pressure drop for air flow (such as coarser pitch between fins) to enable the cooling air mass to reach the

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RF power amplifier thermal design

heatsink’s finned surfaces. Many helpful guides are available from suppliers of heatsinks [60]. Aluminum alloys are most commonly used for heatsinks. Extrusion, die-casting, forging, milling/machining, and bonded fin are the prevalent manufacturing methods for heat-sinks. The lowest cost heat-sinks are typically made from Aluminum alloys (k ∼ 160 W/m ◦ K) by an extrusion process. In typical basestation applications, the available temperature budget for the heatsink is ∼50 ◦ C (maximum Tambient air ∼ 40 to 50 ◦ C; maximum Theatsink-baseplate ∼ 90 to 100 ◦ C). Typical heat transfer efficiency from the heat-sink surface to the ambient air is ∼0.001 W/cm2 ◦ C for free air cooling and ∼0.003 W/cm2 ◦ C for forced air cooling. Thus, from 1 cm2 surface area of an Al finned heat-sink, about 0.05 W heat is disposed to the ambient air in free air cooling and about 0.15 W heat is disposed in forced air cooling. Thus, substantial surface area is built into the Al finned heat-sink to dispose the total waste heat, and so the heat-sink adds to the size, weight, and cost of the RFPA hardware.

9.6

RFPA thermal design – trends and prognostication The most important trend in the high-power RFPA space today is the drive to improve the linear efficiency. In earlier discussions it was pointed out that the efficiency of highpower RFPAs in wireless basestations ranges from 10 to 60% depending on the PA technology and mode of operation. Lower efficiency RFPAs translate into higher capital and operating expenses for the wireless network operators. There is an incessant drive to lower these costs to improve the profitability on the investment in the infrastructure. There is one estimate [61] that an average 3 G cell site in Europe costs $3200/year to operate; for a European operator running 20,000 cell sites, this will translate to $64 M/year in OPEX. Further, various potential regulatory measures are on the horizon to reduce the carbon foot-print of mobile communication products and services [62]. Information and Communication Technology (ICT) worldwide is estimated to contribute ∼2% to the greenhouse gas emissions [63]. Within this, the mobile communications sector has a small share, but it is expected to increase significantly [64] due to the expected growth in mobile data and internet traffic. Radio base stations are the main contributor to greenhouse gas emissions within the radio network. Higher efficiency RFPAs will help reduce the energy consumption, carbon foot-print, and OPEX for the basestation. Among the various higher efficiency amplifier choices, Doherty Amplifier configurations seem to have the most promise in the near future [65, 66]. In this approach, RFPAs will be configured to provide a certain average output RF power and when peak demands happen, an additional peaking amplifier will switch on to provide the extra output power. Conceptually, this approach is not all that surprising; similar approaches have been adopted for many years in the electric power utility industry on how they manage power capacity both for average and peak demands. Given this back drop of improved efficiency for RFPAs, looking toward the future, thermal management of high-power RFPAs in wireless infrastructure and broadcast equipment should be more manageable. Many of the established packaging materials, assembly processes, and hardware manufacturing technologies that are in current practice in providing thermal solutions for

9.6 RFPA thermal design – trends and prognostication

441

RFPAs should be able to meet the needs adequately. Furthermore, there are many niche technologies and solutions developed in the field of thermal sciences and engineering that can be tapped with ingenuity to address exceptions or special situations. We will briefly address some of those items. Another identified area for efficiency improvement in an RBS is to reduce the loss in the feeder cables. One estimate [1] gives this a multiplication factor of 17, i.e., one unit of energy saved in the energy delivered to the feeder cables could save 17 units of energy upstream due to amplifier losses. This is very dramatic. To realize this, RFPAs should move closer to the radiating antennas, thus there is increased interest in tower mount amplifiers (TMA) and remote radio heads (RRH). Furthermore, the RRH offers flexibility in the deployment of distributed base stations. A typical RRH is compact in size (∼40 × 50 × 30 cm), weighs in the range of 15 kg, and is packaged in an environmentally hardened box (as it is exposed to weather elements) with natural convection cooling. Thermal management practices prevalent in natural convection cooling are practiced in RRH, usually the outer case of the housing box incorporates the cooling fin structure. Next, let us consider trends in the power density [67] and thermal flux at device level. The leading Si device technology, LDMOS, as practiced in high-power RFPA applications at 2 GHz, 28–32 V operation has saturated CW RF power density in the range of 0.6 W/mm to ∼ <1 W/mm of gate periphery. At this power density level, the thermal flux density in the active area for practical devices of today is in the range of 3 × 107 W/m2 . It is interesting to compare this thermal flux at the device level with that on the sun’s surface (6.6 × 107 W/m2 ) [68]. The thermal flux in the active region of the RFPA device is one of the highest among semiconductor devices and is within a factor of two compared to what is believed to be on the sun’s surface. Though this is an attention catcher, thermal conduction in solids such as Si is able to support such an immensely large heat flux with the temperature gradients that are in the practical range. The power density for Si LDMOS will increase as the technology advances to higher voltage operation, from 32 V to 48 V operation; theoretically, the power density increase will be  2 proportional to the square of voltage [i.e., 48 ∼ 2X ]. The corresponding increased 32 thermal flux density at the device level will necessitate many evolutionary improvements such as improved device layouts, further thinning of the Si device, increased use of Cu as the package substrate material, and a search for cost-effective but improved k for the package substrate materials, all to provide the needed improvements in thermal management practices. However, device level power density is an area of concern for device technologies such as GaN RFPAs for possible future basestation and broadcast applications. GaN devices are capable of much higher power density (∼5 W/mm), thus potentially much larger thermal flux densities are likely with GaN devices. The SiC substrate on which typical GaN devices are built has a k value of about three times that of Si. Thus, GaN on SiC inherently will offer a superior thermal solution compared to a GaN device on a Si substrate. Taking this discussion further to package substrate materials, one can make a case that today’s commonly used package substrate materials (Cu-laminates with k values ∼250 W/m ◦ K) will be performance limiting for high-power GaN RFPAs in

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RF power amplifier thermal design

basestation applications. This will necessitate the need to use package substrate materials of higher k values such as Cu and potential new materials such as diamond and CuGraphite composites. There are numerous technical and economic challenges to solve before realizing such high k materials in RFPA products. Package materials, assembly processes, thermal interface controls, and cooling methods that are in current practice to meet the thermal challenges within the cost structure for high-power RFPAs in basestation applications are very well tuned. It is unlikely that any major shifts from the current practices to manage thermal challenges will occur in the near future, rather evolutionary improvements are more likely. Enhanced thermal management materials (such as natural and engineered diamonds, metal-diamond composites, graphite–copper composites, and carbon nano-tube structures), advanced manufacturing practices (thinning device material down to 25 μm, direct bonding to copper), and advanced cooling concepts (phase change cooling, liquid cooling, in-situ thermo-electric cooling) are researched in the technical literature. However, realizing them in basestations and broadcast applications will be severely challenged by the economics and the needed proof data on long term reliability. Hence, there will be continued pressure to improve the efficiency of RFPAs, to deploy smaller cell sites (pico cell, femto cell), and to seek other system level solutions at the RBS level to counter some of these extreme thermal challenges.

References 1. P. Misar, “Base station technologies, brainstorm: how can we improve power added efficiency and what role will high-power RF amplifiers play in achieving this goal?, Feb. 2009, www. wirelessdesignmag.com. 2. H. Taub and D. L. Schilling, Digital Integrated Electronics, McGraw-Hill, 1977, ch. 1, pp. 5–6. 3. W. N. Carr and J. Mize, MOS/LSI Design and Aplication, McGraw-Hill, 1972, ch. 3, pp. 85–89. 4. Technical Data, RF LDMOS Wideband Integrated Power Amplifier, Freescale Semiconductor Inc., MW4IC2020N (2006); MW5IC2030N (2006), MW6IC2040N (2008), MW7IC18100N (2009). 5. Reliability prediction of electronic equipment, US Dept. of Defense, MIL-HDBK-217B, NTIS, Springfield, VA, 1974. 6. D. S. Peck, “The analysis of data from accelerated tests,” Proceedings of the IEEE Ninth Reliability Physics Conference, 1971, pp. 69–78. 7. C. A. Harper, Handbook of Thick Film Hybrid Microelectronics, McGraw-Hill, NY, 1974. 8. J. W. Thornell, W. A. Fahley, and, W. L Alexander, “Hybrid microcircuit design and procurement guide,” Boeing Company, NTIS, Springfield, VA, 1972, Document # AD 705974. 9. “Power amplifiers for handsets” [Online]. Available: http://www.rfmd.com, http:// www.anadigics.com, http://www.triquint.com. 10. D. Pavlidis, “HBT vs PHEMT vs MESFET: what is best and why,” GaAs Mantech Dig., 1999. 11. “Thermal via farm in PCBs to improve thermal management” [Online]. Available: www. merix.com.

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12. T. Lee, B. Chambers, and M. Mahalingam, “Application of CFD Technology to Electronic Thermal Management,” IEEE Proceedings of the 44th Electronic Components and Technology Conference, pp. 411–420, 1994. 13. “High power amplifiers for wireless infrastructure, broadcast” [Online]. Available: ISM applications: http://www.freescale.com, http://www.nxp.com, http://www.infineon.com. 14. P. J. Schneider, Conduction Heat Transfer, Addison-Wesley Publishing Company, Inc., 1955. 15. H. S. Carslaw and J. C Jaeger, Conduction of Heat in Solids, Oxford University Press, 1959. 16. W. M. Roshenow and H. Choi, Heat, Mass and Momentum Transfer, Prentice-Hall, Englewood Cliffs, NJ, 1961. 17. E. R. G. Eckert and R. M. Drake Jr., Analysis of Heat and Mass Transfer, McGraw-Hill, NY, 1972. 18. W. H. McAdams, Heat Transmission, McGraw-Hill, NY, 1954. 19. F. Kreith, Radiation Heat Transfer, International textbook, Scranton, PA, 1962. 20. R. Siegel and J. R. Howell, Thermal Radiation Heat Transfer, Hemisphere, Washington, DC, 1981. 21. W. M. Roshenow, Ed., Developments in Heat Transfer, MIT Press, Cambridge, MA., 1964. 22. G. Leppert and C. C. Pitts, Boiling, Advanced Heat Transfer, vol. 1, 1964. 23. Reference to thermo-physical properties for electronic packaging materials: https:// cindasdata.com. Microelectronics Packaging Materials Database (MPMD): Database contains thermal, mechanical, electrical and physical properties of electronics packaging materials. 24. Good reference to material properties for the semiconducting device materials [Online]. Available: http://www.ioffe.ru/SVA/NSM/Semicond/index.html. 25. M. Mahalingam, M. McCloskey and V. Viswanathan, “Low Rth device packaging for high power RF LDMOS transistors for cellular and 3G base station use,” White paper, presented at CTIA, Mar. 2003. 26. Z. Radivojevic, K. Andersson, L. Bogod, M. Mahalingam, J. Rantala and J. Wright, “Novel materials for improved quality of RFPA in base-station applications,” SemiTherm Special Section, IEEE Trans. Compon. Packag Technol, 2005. 27. Technical trade literature on metal flange materials tailored for RFPA flanges [Online]. Available: http://www.allied-material.co.jp/e ; http://plansee-tms.com. 28. Data sheet on thermally conductive thermal grease [Online]. Available: http://www. dowcorning.com. 29. Data sheet on electrically and thermally conductive interface pads [Online]. Available: http://www.lairdtech.com/thermal. 30. Product technical information on thermocouples [Online]. Available: http://www.omega.com/ thermocouples.html. 31. JEDEC Standard, EIA/JESD51–2 [Online]. Available: www.jedec.org. 32. D. Peterman and W. Workman, “Infra-red radiometry of semiconductor devices,” Microelectronics and Reliability, Pergamon Press, 1967, vol. 6, pp. 307–315. 33. D. D. Griffin, “Infrared microradiometry – precision and accuracy considerations applicable to microcircuit temperature measurements,” Materials Evaluation, Am. Soc. Nondestructive Testing, Oct. 1968, pp. 215–220. 34. G. Fleurn, “Liquid crystal microthermography state of the art,” Proceedings of Semitherm, 1986. 35. D. J. Brenner, “A technique for measuring the surface temperature of transistors by means of fluorescent phosphors,” NBS tech. note 591, July 1971.

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36. D. Blackburn, “An electrical technique for the measurement of the peak junction temperature of power transistors,” Proceedings of the IEEE Reliability Physics Symposium, 1978, pp. 142–150. 37. S. Rubin and F. Oettinger, “Thermal resistance measurements on power transistors,” NBS Special Publication 400–14, US Department of Commerce, 1979. 38. F. Oettinger, “Thermal evaluationof VLSI packages using test chips – a critical review,” Solid State Technol., Feb. 1984. 39. Technical information: Analysis Tech’s website [Online]. Available: (www.analysistech.com). 40. Technical information: MicReD’s website [Online]. Available: (www.micred.com). [Online]. Available: 41. Technical information: TEA’s website [Online]. Available: (www.thermengr.com). 42. InfraScope II, Micro-thermal Imaging [Online]. Available: http://www.quantumfocus.com. 43. M. Mahalingam and E. Mares, “Thermal measurement methodology of RF power amplifiers” [Online]. Available: AN 1955, 2004, Freescale Semiconductor, http://www.freescale.com. 44. Technical information on software to perform modeling and simulation for Thermal, Structural and Fluid analyses [Online]. Available: www.ansys.com. 45. Technical information on software to perform modeling and simulation for Thermal and structural analyses [Online]. Available: www.simulia.com. 46. Technical information on software to perform modeling and simulation for Thermal analyses [Online]. Available: [Online]. Available: www.mscsoftware.com. 47. Technical information on software to perform modeling and simulation for Thermal and structural analyses [Online]. Available: www.cosmosm.com. R 48. Technical information on CFD software FloTHERM [Online]. Available: www.mentor.com. R 49. Technical information on CAD design software AutoCAD [Online]. Available: http://usa. autodesk.com. 50. Technical information on CAD design software Pro/ENGINEER [Online]. Available: www. ptc.com. R R Allegro Package Designer 51. Technical information on ECAD design software Cadence [Online]. Available: http://usa.cadence.com. 52. Technical information on ECAD design software from Mentor Graphics [Online]. Available: www.mentor.com. 53. W. Burger, “Recent advances in LDMOS technology,” IEEE IMS 2008 Workshop: Advances in High Power Devices and PA Architectures for Wireless Infrastructure. 54. S. Drews (SEZ America), “Wafer thinning,” IEEE CPMT Phoenix Section, April 2007, Technical Tutorial: Backend wafer processing technologies. 55. G. Hawkins, H. Berg, M. Mahalingam, G. Lewis, and L. Lofgran, “Measurement of silicon strength as affected by wafer back processing,” IEEE 25th Annual Proceedings Reliability Physics 1987. 56. M. Mahalingam, M. Nagarkar, L. Lofgran, J. Andrews, D. Olsen, and H. Berg, “Thermal effects of die bond voids in metal, ceramic and plastic packages,” IEEE 34th Electronic Components Conference 1984; Semiconductor International, Cahners Publishing Company, Sept. 1984. 57. M. Mahalingam and E. Mares, “Infrared Temperature characterization of high power RF devices,” Proceedings of IEEE MTT-S International Microwave Symposium, May, 2001. 58. M Yovanovich, “Four decades of research on thermal contact, gap, and joint resistance in microelectronics,” IEEE Transactions Compon. Packag. Technol., vol. 28, No. 2, June, 2005.

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59. H. Atkins, H. A. Blum, and C. J. Moore Jr., “Bibliography for thermal contact resistance studies,” ASME 68-WA/HT-18, Dec. 1968. 60. Product literature and design guides on heatsinks [Online]. Available: http://www. alphanovatech.com; http://www.heat-sink.com.tw. 61. S. Peera, Base station technology and trends, brainstorm: what are the greatest challenges today in deploying base stations and how can designers address it?, Feb. 2010 [Online]. Available: http://www. wirelessdesignmag.com. 62. O. Arnold1, F. Richter, G. Fettweis, and O. Blume, “Power consumption modeling of different base station types in heterogeneous cellular networks,” Proceedings of the Future Network and Mobile Summit 2010. 63. McKinsey & Company, “The impact of ICT on global emissions,” technical report on behalf of the Global eSustainability Initiative (GeSI), Nov. 2007. 64. G. P. Fettweis and E. Zimmermann, ICT energy consumption – trends and challenges,” Proceedings of the 11th International Symposium on Wireless Personal Multimedia Communications, Sept. 2008. 65. S. Bousnima, “Maximizing efficiency and linearity,” IEEE Microw. Mag., Aug. 2009. 66. W. H. Doherty, “A new high efficiency power amplifier for modulated waves,” Proc. IRE, vol. 24, no. 9, pp. 1163–1182. Sept. 1936. 67. C. E. Weitzel, “RF power devices for wireless communications,” IEEE MTT-S Dig., 2002, pp. 285–287. 68. N. Strobel, “The Sun and Stellar Structure,” Ch. 12 [Online]. Available: www.astronomynotes. com.

10

Reliability Bill Roesch TriQuint Semiconductor

10.1

Introduction This chapter provides an overview of basic reliability theories and presents some example data to illustrate concepts. The three key reliability precepts of understanding failure mechanisms, failure distributions, and acceleration factors are discussed in detail. Various reliability test methodologies and results are presented with respect to device processing and circuit elements that are likely to be included in amplifying devices. Some differences between compound semiconductor and silicon technology are covered from a reliability point of view. Additional reliability aspects of fabrication, application, and design are also discussed. It is hoped that the information presented here provides the basis for establishing reliable radio frequency power amplifiers. Reliability is as much a key to success in the microelectronics industry as is performance. Not only must a product perform as desired, it must work for years without fail. It does little good to make the world’s highest efficiency amplifier if after two weeks of operation it fails. With the complexity of today’s microelectronics, a phenomenal level of reliability must be maintained. For instance, if the probability of failure for a transistor is one in a million, and you have a million transistors in a circuit, the probability of failure is nearly certain. And yet, a modern microprocessor or memory circuit can have more than 10 million circuit elements. Therefore, for any acceptable reliability on the chip level, today’s circuit elements must be among the most reliable things ever built. In addition, reliability must continue to increase as the complexity increases and as performance improves. The semiconductor reliability we have enjoyed thus far has not come without considerable cost. Resources have been expended to solve the daunting problems facing reliability engineers designing integrated circuits. The few wear-out failure mechanisms that exist (metal contact interdiffusion, hot carrier degradation, time-dependent dielectric breakdown, and electromigration) have become understood well enough that we can model these effects with some of the advanced design tools. We know the countermeasures and de-rating factors to apply in order to delay any wear-out issues beyond the device’s useful life with margin to spare. However, to apply the countermeasures effectively, one must understand the limitations of the materials used to manufacture ICs, and work to ensure that products have adequate margin and a high probability of success. Overestimating the capabilities of the materials and the process could lead to catastrophic results, and underestimating capabilities could lead

10.2 Vocabulary and definitions (units, goals, and strategy)

447

to overdesign which would inflate costs beyond the limits of feasibility. Striking a balance between conservatism and judicious use of the process capabilities is necessary for continuous advancements, and can only be accomplished by obtaining empirical reliability data. Amplifiers must work relatively hard compared to other circuit functions. High currents, high temperatures, high-frequency operation, high voltages, and many thermal cycles eventually take a toll. Two types of reliability issues can degrade circuits: defectrelated problems and wear-out. Defect-related problems are induced by manufacturing flaws, such as a missing process step, contamination, undetected excursions, wide variation or narrow capabilities of fabrication processes. Even the best, most efficient, semiconductor fabrication lines suffer from an occasional defect related event. Wear-out is due to the degradation of aging, without any initial defects being present. Although it may seem that redundancy and insensitivity to a failure mechanism is up to the designer, and that defects are in the realm of the process engineer, in reality both types of mechanism must be addressed by designers and process engineers alike.

10.2

Vocabulary and definitions (units, goals, and strategy) There are two key parts to a definition of reliability. First, is a measure of “goodness” such as conformance to standards, meeting expectations, or compliance to certain specifications. Typically, measures of “goodness” are replaced by definitions of what is not good enough. For example, most semiconductor reliability engineers speak in terms of failure rates instead of success probabilities. As the word “rate” implies, the second major part of a reliability definition involves time. Expected periods of “goodness” may range from several seconds for a guidance system in a missile, to decades for a communications system in an airliner or satellite. Other significant parts of a definition might include environmental conditions and duty cycles. A succinct definition of reliability is a performance attribute that is concerned with the probability of success or frequency of failure and can be defined as: The probability that an item will perform its intended function under stated conditions, for either a specified interval or over its useful life. Another slightly different definition of reliability is: The ability of a product to function under given conditions and for a specified period of time without suffering performance degradation beyond a defined limit. Of course, the specific definitions of each word within the reliability definition can further complicate this definition of reliability. For example, measuring the “ability” of a product is often accomplished in terms of probability – as shown by the interchangeability of these terms in the two definitions above. Likewise, the “ability” is often measured by quality terminology and definitions. So, in general, reliability definitions will contain the following four aspects:

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r r r r

performance attributes such as ability, functionality, or probability; conditional attributes such as environment, bias, or operational description; failure description such as allowable degradation, specified limits; time component of an interval, warranty period, or general life expectation.

The simplest definition of reliability is: quality for a duration of time. So the components of performance, conditions, and failure criteria are wrapped within a simpler encompassing label of “quality.” Since time is so critically involved, reliability is often measured by a rate. But just as quality is usually measured in terms of rejects (or un-quality), reliability is often measured in terms of failures (or un-reliability). Reliability is a measure of a product’s performance. Too often performance is thought of only in terms of speed, capacity, range, and other “normal” electrical or physical measures. However, if a product fails so often that it is seldom available for use, then its speed, range, and capacity are less relevant.

10.2.1

Reliability goals Reliability goals are determined with respect to each of the four components expected within the definition of reliability. The elements of reliability goals are shown below with examples: r performance component: operation within specified data sheet parameters; r conditional component: at an operating transistor temperature of 150 ◦ C; r failure criteria: minimize or eliminate early failures. Keep the overall failure rates below 0.01%/1000 device hours (less than 100 FIT – see Section 10.8); r time component: extend the useful life of ICs to greater than 20 years (175,000 h). Therefore, a well-described reliability goal example might be: Power amplifiers are expected to operate within all data sheet parameters at an operating transistor temperature up to 150 ◦ C with less than a 100 FIT failure rate for a 20-year lifetime. Of course, reliability definitions could contain even more details and requirements, but they should not omit any of the four elements used to define reliability.

10.2.2

Semiconductor reliability strategy The strategy to accomplish and verify the reliability goals involves accelerated testing of the circuit and the individual building blocks of ICs [1]. These building blocks are labeled “elements,” and they consist of each metallization interconnect type, resistors, capacitors, contacts, and active elements of transistors and diodes. Element testing is optimal for a number of different reasons. It is essential to isolate and assess all the various failure mechanisms possible for an amplifier. Element testing is especially useful to the circuit designer because the data can be used to model the reliability performance of circuits based upon physical sizes and operating conditions of each portion of the

10.3 Failure criteria

449

design. Element tests are used to verify, and in some cases, modify design and layout rules. The strategy involves the following steps: 1. Conduct fundamental reliability studies to identify and measure wear-out mechanisms for each amplifier process. 2. Calculate failure rates of each amplifier element. Continue process improvements until each element’s reliability exceeds the goals. 3. Model how temperature, voltage, current density, and other operational conditions or environments affect the time to failure of each element. 4. Select the maximum ratings for each element, consistent with the reliability goals. 5. Verify compliance to reliability expectations with reliability qualification testing of the completed amplifier product. 6. Establish the maximum ratings and conditions with the amplifier description (datasheet). 7. Monitor amplifier reliability and compare results with reliability expectations based on element predictions. 8. Re-evaluate elements as necessary and life-test circuits as improvements or changes are made to processes and products. As part of the reliability investigation of amplifiers, many product reliability tests have been conducted and published. Outside of transistor elements, the individual elemental results are less published.

10.3

Failure criteria The definition of a failure is one of the most subjective and arbitrary aspects in the measurement of reliability. When failures are abrupt or catastrophic, the failure criteria has little effect on the outcome. However, when degradation is gradual or graceful, then the criteria used to decide the amount of change allowed can influence the results considerably. The selection of a measurement of interest is usually narrowed by two types of concern. One aspect is to consider parameters that are most affected by the aging method. For example, temperature can universally affect many types of degradation, but current stress will usually be monitored by measuring resistance. The other aspect of degradation is to consider the parameters that are most important for the operation of the device. For example, figures of merit for amplifiers are gain, 1 dB compression point, and the two-tone third-order intercept point [2]. However, efficiency, noise, and absolute power output are some of the many attributes that could be critical for any particular application. Obviously, the definition of “most important” is dependent upon the application and the user’s opinion. For the reliability engineer, the objective choice is to monitor as many different parameters as possible, and determine which parameter degrades most rapidly under the applied stress. Once the most rapidly degrading parameter is determined, then a significant level of change must be identified as the criteria. For some products, a simple test of significance

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Table 10.1 Example failure criteria Mechanism

Measurement

Failure criteria

General wear-out

Gain Power 1 dB compression

>1 dB decrease in gain >1 dB decrease in power out >1 dB change in input at 1 dB compression

Transistor wear-out

Channel current Beta Leakage current Breakdown

>20% decrease in channel current >20% decrease in beta >10 times increase in reverse current >10% reduction in breakdown voltage

Interconnect wear-out

Resistance

>10% increase in resistance

Capacitor wear-out

Leakage Capacitance

>10 times increase in leakage >10% change in capacitance/unit area

Resistor wear-rout

Resistance

>10% increase in resistance

is the specified value or datasheet limit. The use of a specification threshold as a failure criterion is easy to apply since it is clearly documented and most likely already part of an electrical measurement regimen included in the product testing routine. However, using a datasheet failure criteria is not a consistent gauge of degradation since the sample population could lie anywhere within the specification range. If the population was near the specification edge, then only a slight shift would be needed to result in a failure. If the population had excess margin, and was at the opposite extreme from the wear-out edge of the specification, then a large change in the parameter of interest would need to occur before the population would begin to exceed the data sheet limit. Thus, two samples from a common population may have the same rate of degradation, but different times-to-failure – if the failure criterion is an arbitrary specification limit. Table 10.1 shows several examples of criteria used for mechanisms and measurements selections. Whatever failure criteria is selected, the threshold must be easily discernable by the instrumentation. In most cases, it would be expected that measurement resolution should be at least 10 times better than the failure criteria. For example, if a 1mA change of channel current is equivalent to the 20% increase in channel current, then an instrument capable of resolving 100 μA (or less) would be needed to assess the failure criteria. The 10 times rule of thumb for resolving failure criteria can be more formally evaluated with a gage repeatability and reproducibility (GR&R) study of the measurement instrumentation [3]. An easy method of selecting appropriate failure criteria is one that matches with previous published results, but the best measure of failure criteria is one that correlates to customer findings and feedback.

10.4

Failure modes The failure mode of a device is a description of the symptom of failure that is observable from external evaluation. For example, a common failure mode is “output degraded.”

10.5 Failure mechanisms

451

Table 10.2 Some common failure modes and mechanisms Failure mode

Failure mechanism

Reduced output Reduced output Reduced output Reduced output Reduced output

Gate metal sinking on third-stage output transistor Q9 Electrostatic discharge damage between source and drain at transistor Q1 Die crack through capacitor C12 17 nA leakage through a gold filament between pad 14 and pad 15 Poor solder joint wetting on pad 15

The mode by itself does not provide sufficient information to understand the failure. The mode does not describe how much degradation, nor does it describe the cause of the degradation. The mode is an intermediate classification that provides a common vocabulary between the customer and supplier. Often, the customer will simply describe the failure as “the part is dead.” The failure analyst would prefer more descriptive failure modes, such as “the output power began to slowly degrade after 10 months of nominal use, and failed to meet minimum requirements in the 350th day of use,” or “the gain degraded with use and failed after long transmit sequences – the part would recover after cool down or if mechanical pressure was applied to the case of the circuit.” The failure mechanism describes what causes the degradation of the mode, preferably in terms of the physical location and the physics behind the degradation. Table 10.2 shows some examples of failure mechanisms for one particular failure mode. Although the failure mechanism may be a more specific description of a failure than the mode, the mechanism is not necessarily a description of the root cause.

10.5

Failure mechanisms Whether made from compound semiconductors or silicon, integrated circuits are susceptible to the same classes of failure mechanism. Failure mechanisms can generally be differentiated into three types of physical structure: metallization, dielectric, and semiconductor.

10.5.1

Metallization Interconnects are expected to be conductive, to be immune to electromigration, to be bondable, to be able to adhere to other circuit layers, to resist corrosion, to form good contacts, and to be patternable into the desired structure. Metallization failures result from degradation in one or more of these attributes. Silicon technology uses aluminum (with small percentages of copper and silicon added) almost exclusively for all metallization, which has some advantages. Adding about 2% silicon aids the formation of direct ohmic contacts to the silicon active regions without interdiffusion and contact spiking. The addition of small amounts of copper has become popular to increase aluminum’s immunity to electromigration as metallization feature sizes decrease.

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Because of its maturity, the aluminum processing used in silicon-based devices generally meets all the above mentioned criteria for metallization. There have been persistent aluminum problems with corrosion, intermetallic formation, and electromigration, but in modern processes these have been “controlled.” Compound semiconductor processing generally involves different specialized metallizations for ohmic contacts, Schottky gate formation, and interconnects (including capacitor electrodes). Naturally, each of these types of metal are designed to meet specific metallization properties, sometimes at the expense of other properties. Most commercial compound semiconductor ICs employ gold-based metals, principally with titanium and various other refractory metals. Gold/germanium is generally used for ohmic contacts. Aluminum has been used for the gates of discrete power MESFETs and for some interconnects, and some of the afore-mentioned aluminum problems have been observed. Gold-based connections avoid the possibility of the intermetallic problems that an aluminum/gold metallization introduces. Gold-based metals have therefore dominated compound semiconductor IC production. The performance of gold metallization in terms of conductivity, bondability, and adherence are probably about equal to that of aluminum used in silicon processing. These have not been mentioned as problems as long as the metal system has been primarily gold. Intermixing of gold and aluminum introduces the typical intermetallic problems such as purple plague [4]. Next, metallizations are expected to have an immunity to electromigration and resistance to corrosion. Tests on aluminum and gold metallized ICs have indicated susceptibility to both these mechanisms. As silicon geometries have decreased, aluminum electromigration issues have been alleviated by use of copper metals. However, copper is much more reactive and susceptible to corrosion, so protective metals are added to surround the copper and prevent reactions with subsequent process chemicals and with moist environments. Because of the increasing price of gold and because of the advent of copper bump technologies, some compound semiconductor metallizations are also converting to copper. Electromigration and corrosion are not considered to be primary failure mechanisms for gold interconnects but gold corrosion has been discovered in highly accelerated humidity testing. However, gold corrosion has not been reported after years of normal field use in nonhermetic packages. Metallizations should also be fairly inert with respect to other materials used in the processing. Aluminum probably has the edge in this category. Even though goldGaAs interdiffusion is essential in forming ohmic contacts, too much interdiffusion of gold, either on the ohmic contacts or the Schottky gates, is the primary wear-out mechanism in GaAs ICs. This interdiffusion may be at a “controlled” state, but the variety of existing metal schemes and process techniques would indicate there is no single, superior answer to the interdiffusion problem. Some gate metallizations are being produced from refractory metals which can withstand high temperatures without interdiffusion. But Au-Ge-type ohmic contacts, which are susceptible to interdiffusion after long high-temperature exposures, are still in widespread use. Copper is also a fast diffuser and would be detrimental to all semiconductor contacts if not separated by the moisture and diffusion barrier metals that accompany its use.

10.5 Failure mechanisms

453

Pattern definition of the metallization is performed differently for each of the metallizations. Because of the history of processing the aluminum metal used in silicon devices, dry etching is usually done on all layers. Compound semiconductor metals are usually formed by a liftoff process, at least at the ohmic, gate, emitter, base, and collector contact levels. Upper layers may be etched or plated, but sometimes liftoff is used for all metal layers. Liftoff is less complicated than the etch-back process because it usually requires no etching steps, but liftoff is a procedure that requires careful control. Both gold and copper are difficult metals to etch. Most copper patterning on silicon devices uses a chemical mechanical polishing (CMP) process to achieve planarization and patterning of their ever-decreasing feature sizes. So, aluminum, gold, and copper metallizations each have advantages and disadvantages, but all three have been proven to have adequate reliability for use in devices and ICs.

10.5.2

Dielectric The next classification of failures is related to dielectrics. For the most part, materials used to form dielectrics are quite similar, but their requirements are not. Silicon has the advantage of an ability to grow a stable, high-quality oxide which is used principally to form MOS gates and surface dielectrics. The silicon oxide is also used to isolate individual transistors and to form MOS capacitors. Above the surface of silicon, layers of nitride are generally used for interlevel dielectrics. Compound semiconductors have no useful oxide, therefore silicon oxide is often used in processing as a capping material or sometimes for interlevel dielectrics. Silicon nitride is the dielectric usually used in metal-insulator-metal (MIM) capacitors. Silicon nitride is also often used as the interlevel dielectric. The usual form of deposition is plasma enhanced chemical vapor deposition (PECVD). The silicon industry has devoted much work to the development of dielectrics because of their importance in gate formation and isolation. Compound semiconductor suppliers have taken advantage of this work even though the requirements of the dielectric are much more forgiving, because Schottky rather than MOS gates are used and the compound semiconductor substrates are self-insulating. For some compound semiconductor processes, interlevel dielectrics are not needed since airbridges are supported above the base interconnect and contact layers. Except for capacitors, some ICs could conceivably be constructed without any dielectric at all. The special challenges of power amplifier performance make the dielectric a critical consideration for silicon devices. The gate dielectrics are continuing to get thinner as silicon geomtries shrink. There is a number of gate dielectric degradation mechanisms that need to be considered in the design of a CMOS power amplifier and each can degrade during amplifier operation. There are three predominant degradation mechanisms that can result in silicon dielectric failure. Hot carrier injection (HCI) is the predominant degradation mechanism in NMOS devices whereas negative bias temperature instability (NBTI) dominates in PMOS devices. In addition, PMOS devices can also experience HCI. Time-dependent dielectric breakdown (TDDB) is a failure mechanism due to catastrophic failures of the transistor gate dielectric resulting in a hard failure of

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the device. TDDB failures are classified in two main categories: intrinsic and extrinsic failure modes. The extrinsic mode is a function of the defects in the oxide during the fabrication process. Usually, it results in infant mortality types of failure at a relatively low electric field of 2–4 MV/cm. The intrinsic TDDB mode corresponds to the technology capability and is a function of the transistor or capacitor design and also of the dielectric composition and quality. In the new process technologies, the intrinsic failure mode occurs for an electric field strength of >10 MV/cm. As one might expect, a variety of failure mechanisms affect this wide variety of dielectric materials, but the most important failure mechanisms are related to insulated gates and capacitors.

10.5.3

Bulk substrate material The final general physical category of failure mechanism involves the substrate material. The difference in resistance and mobility gives compound semiconductors some performance advantages in this area compared with silicon. The semi-insulating properties of compound semiconductors have, for the most part, eliminated first-order problems with isolation and latch-up which are constant nuisances for silicon. However, the complexities of compound semiconductor epitaxial layers make their transistors susceptible to traps, and circuit interactions called “backgating” or “sidegating” have been discovered. Semi-insulation may not be quite enough to prevent substrate conduction for microwave and radio frequency circuits, but many performance issues are significantly reduced compared to silicon devices. Of the three physical classifications for failure mechanism, the substrate is arguably the least significant for reliability issues.

10.5.4

Schottky gate FET failure causes The primary failure mechanisms for silicon technology generally involve gate oxide integrity, electromigration, corrosion, and isolation while gallium arsenide problems center around interdiffusion of metallizations. The FET is most often the center of attention in compound semiconductor circuits. Testing has revealed degradation of channel resistance and decreasing channel current as clear failure modes of metal semiconductor FETs (MESFETs) and high-electron mobility transistors (HEMT) at the end of their expected lifetimes. Early GaAs MESFETs suffered from direct channel burn-out. The shorting of the channel from gate-to-drain, gate-to-source, and drain-to-source resulted from a lack of consistent processing and poor substrate material. More recent studies have found this shorting to occur only when MESFETs are overstressed in terms of current density, voltage breakdown, and/or excessive power dissipation. Another reported failure mechanism which could often account for increased channel resistance and decreased saturation current was ohmic contact degradation. Interdiffusion of gallium and gold was a problem for manufacturers a few years ago. This interdiffusion often caused increased effective channel resistance and contact degradation. As manufacturers standardized on Au-Ge-Ni ohmic materials, instead of incorporating

10.6 Failure distributions

455

Cr or In, this problem subsided. Anecdotal evidence also seems to suggest that the deposition technique is also a key to stable ohmic contacts. Deposition of ohmic metals serially in distinct stacks has reportedly been more stable than ohmic contacts which are deposited simultaneously or from a precombined source of metals. As compound semiconductor development has progressed, the ohmic contacts have become less of a problem. Investigations into FET degradation on a device physics level has found that changes in pinch-off and/or transconductance often occur at the end of life and cannot be explained by ohmic contact degradation. Analysis generally also indicates an effective reduction of carrier concentration in the channel of the FET. At least three possible mechanisms could be responsible for this predominant failure mode. Changes in the carrier concentration of the FET can be caused by compensation from gate atoms, diffusion of carriers out of the channel, or effective reduction of the channel depth by the encroachment of the gate. Compensation can be measured by DLTS (deep level transient spectroscopy). Diffusion can be assessed by the effects of bias during life-testing, and movement of the gate into the channel can be confirmed by Auger or other destructive analytical techniques. The effects of burn-out, ohmic contact degradation, carrier compensation, carrier diffusion, or gate metal interdiffusion is specifically dependent on the manufacturer’s process. It is possible that several mechanisms at work simultaneously.

10.6

Failure distributions One of the keys to understanding reliability is an understanding of failure distributions. Any particular sample of devices will have a unique type of failure signature for each mechanism that causes degradation. Analysis of these distributions is necessary to characterize each type of failure mechanism, and to eventually predict expected lifetime for all the relevant environmental conditions. Separation of failure distributions is not always easy. When multiple failure mechanisms are causing degradation, it may be easier to physically separate the effects by breaking down a circuit into each of its elements. Testing of individual transistors, capacitors, and resistors can expose a single failure mechanism that is easier to analyze than a hodge-podge of factors causing ICs to degrade. However, further breakdown of the individual elements into even simpler individual contacts and interconnects, etc., may help to reveal more insight into the cause of the problem. The measurement of reliability for semiconductors generally involves failure rates. Traditionally, several classifications of failure types have resulted from the failure experience of large systems during their use. This experience is commonly translated to the “bathtub curve” [5] shown in Figure 10.1. Whether measuring computers, automobiles, or even human lifetimes early, random, and wear-out failure types are generally expected. Over many years experience, and across a wide variety of mechanical and electronic components, machines, and systems, people have measured empirical population failure rates as a function of time. If the population is large enough, each study will produce

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Reliability

Figure 10.1 Traditional reliability “bathtub” curve.

Figure 10.2 Human mortality rates (in %) for males and females in the USA c.1990. Source: “Age-specific death rates from the human mortality database (HMD)” from http://www.mortality.org.

results which mimic the human results shown in Figure 10.2. and are generalized by a graph with the shape of a bathtub shown in Figure 10.3. Because of the similarities in shape of these failure rate curves, the curve has become widely known as the “Bathtub” curve. The initial region that begins at time zero when a customer first begins to use the product is characterized by a high but rapidly decreasing failure rate. This region is known as the early failure period and is also referred to as infant mortality period (from the actuarial origins of the first bathtub curve plots). Burn-in can be used as a means of weeding out infant mortalities and this is discussed in Appendix 10.1.

10.6 Failure distributions

457

Figure 10.3 Alternate generalized bathtub curve composed of a “defective” failure distribution and a “wearout” failure distribution. The combined distributions result in a population exhibiting the traditional bathtub shaped failure rate.

Next, some systems have a period where the failure rate “levels off” and remains roughly constant (and hopefully very low) for the majority of the useful life of the product. This long period of a low failure rate is usually identified as the “random” failure period, and is sometimes called the stable failure period. The random failure period characterizes the useful life of the system where the lowest failure rate occurs. Random failures may be caused by infant mortality failure mechanisms which had extraordinary long lives or by devices which wear-out prematurely. Random failures may also be caused by misapplication of devices or by latent damage caused during manufacturing and use. Additional application problems have been noted, such as electrostatic discharge and failure to adequately heatsink higher power devices. As with infant mortality failures, inherent random failures eventually achieve undetectably low levels during the maturation of a new technology. Finally, if units from the bathtub curve population remain in use long enough, the failure rate begins to increase as materials wear out and degradation occurs at an ever increasing rate. This is known as the “wear-out” failure period. Gradual degradation in device parameters is typical for amplifying devices when subjected to extremely accelerated life-test conditions. Occasionally, this degradation leads to functional failure, but in all cases, catastrophic failure mechanisms are rare except when devices are overstressed, either by application or design. For the system designer, early, random, and wear-out failure risks must be considered for the selection of each component. The infant and random failure periods are dependent on device processing, testing and screening – and those risks should abate as technologies mature. It is debatable as to whether the bathtub curve represents a single distribution or an accumulation of multiple distributions. When examining semiconductors under various accelerated aging methods, the early and wear-out distributions are often distinguished. Ideally, the burn-in conditions would exclusively accelerate the early failure mechanisms without shortening the useful life of the device by accelerating the wear-out mechanisms.

458

Reliability

After 4380hrs at 260 °C

Typical FET Curve Idss = 94 mA Rds = 8.4 ohm

Baseline FET 3

Vp = – 1.310 V

10 mA

Idss = 19 mA Rds = 43.75 ohm Vp = –0.818 V

Aged FET 3 10 mA

500 mV

500 mV

200 mV

200 mV

per step

per step

gm = 50 m

gm = 50 m per div.

per div.

Reference Device (time = 0 hours)

Extreme Wearout after 26 week life test.

Figure 10.4 Electrical characteristics of MESFET degradation.

However, if the wear-out mechanisms have margin to spare, then the effect of burn-in may be negligible. For semiconductors, the failure rates of the bathtub curves are depicted with a log scale. The constant failure rate region may be simply the sum of the tails of the early and wear-out distributions. It is expected that systems spend most of their lifetimes operating in this very low failure rate portion of the bathtub curve, so it is sometimes called the “intrinsic” region. The wear-out failure distributions should not be detected until after the warranty lifetime of the product unless some form of accelerated life-testing is employed.

10.7

Acceleration factors

10.7.1

Thermal acceleration One of the primary failure mechanism for FETs is “sinking gates.” Sinking gates are caused by gate metal interdiffusion into the channel. This interdiffusion produces shifts in several MESFET parameters as the effective channel thickness is reduced. The largest parameteric change caused by gate sinking is in channel current. Therefore, a 20% change in channel current may be arbitrarily selected to define a FET failure. In addition, as the gate sinks, channel resistance increases and the magnitude of the voltage required to pinch-off a FET is reduced (this usually means pinch-offs are more positive). The sinking gate failure mechanism is gradual rather than a catastrophic failure mechanism. It is also self-limiting in a sense because as the channel current decreases so does the power in the FET and thus the temperature is lowered; causing the gates to sink more slowly. An example of the electrical and physical effects of extreme gate sinking is shown in Figures 10.4 and 10.5. Figure 10.4 shows the curve tracer characteristics for a typical MESFET and for a MESFET after exposure to 4380 h at 260 ◦ C under bias and RF stimulus. Identical

10.7 Acceleration factors

459

Figure 10.5 Focused ion beam (FIB) cross-sections of reference (left) and degraded (right) MESFETs subjected to 260 ◦ C lifetest. Gate metal width is approximately 0.5 mm. Note: the electrical parameters of these two FETs match those in Figure 10.4.

degradation was observed at the same temperature without bias or RF drive. This degradation is well beyond the 20% change failure threshold, but it was purposely induced to ensure that an accompanying physical change could be detected. The physical change which caused this electrical change is shown in Figure 10.5. As with the electrical data, a virgin gate is shown as a reference. Both of these cross-sections were made using a focused ion beam. The movement of the metal gate at the semiconductor surface is dramatic on the degraded transistor. Some voiding is also present in the degraded gate, probably because of the mass of material which has moved into the transistor channel. This is an extreme failure which resulted in a 2.2 dB change in the insertion loss of the MMIC, but remember, this occurred at 260 ◦ C. In a similar life-test at 250 and 225 ◦ C, less than 0.8 dB and 0.08 dB change occurred, respectively, for the same 4380 h test duration and similarly stressed MMICs. Operation at the maximum rated temperature (150 ◦ C) would be expected to exceed 2000 years before a 1 dB change could be observed. This expected longevity of sinking gates is acceptable in terms of common reliability goals, and is not considered as a threat to device lifetimes under normal operating conditions. To further analyze the sinking gate mechanism, an example of individual transistor life-testing will be used. The changes in channel current during a six month, 245 ◦ C life-test are shown in Figure 10.6. An arbitrary failure criterion of a 20% Ids reduction was chosen because in the amplifiers using this transistor, a 20% drop in channel current resulted in a 1 dB drop in output power. As shown in Figure 10.6, the time to failure is not constant. In fact, no failures occur in this sample until 1700 h have elapsed. The times to failure follow a distribution in time. If time is plotted on a log scale and failure accumulation on a normal scale, then a straight line results, and then a distribution can be characterized with just two simple parameters, a point and a slope. The result of plotting the time to failure data in Figure 10.9 is shown on a lognormal plot in Figure 10.7. The first parameter used to characterize this distribution is the median life (ML). It is determined by the time elapsed to cause half of the samples to become failures, or approximately 4770 h for this life-test. The median life is a point selected as a convenience, it has no particular significance in terms of the distribution, but it is a popular convention to select the median life since there is no zero on the normal scale

Degradation (% Change in Idss)

Reliability

+10 0.0 –10 –20

Failure Criteria

245 °C Life Test

–30 –40

1.0

0.5

1.5

2.0

2.5

Stress Duration (Thousands of Hours) Figure 10.6 Degradation in channel current for a 245 ◦ C FET lifetest. A total of 24 individual transistors were tested for 6 months, only the 12 fastest degrading samples are shown here for the first 2600 h of the accelerated lifetest.

100,000 Sigma

245 °C 10,000 1,000

Median Life

Test Time (Hours)

460

100 10

Normal Scale

1 10%

50%

90%

Cumulative Failure Percentage

Figure 10.7 Lognormal plot of time to failure for a 245 ◦ C FET lifetest.

so an axis intercept is not possible. During conversions and mathematical curve-fitting, the 50% failure point becomes the intercept because the normal scale is symmetric about it. Once the median life is selected as a reference point, the distribution can be fully described with a slope parameter, called sigma. Sigma is sometimes called the distribution’s “shape parameter” and it physically defines the spread of the distribution. The sigma for the data in Figure 10.7 is 0.90. Large sigmas (high slopes) indicate the distribution generates failures over a relatively long span of the test. For any particular failure mechanism, the sigmas should be similar, regardless of the stress temperature or resulting median lifetime. In order to predict lifetimes at lower stress i.e., lower temperature, then the acceleration factor of the stress must be determined. By common definition, the acceleration factor is the median life at low temperature divided by the median life at higher temperature.

10.7 Acceleration factors

100,000

Test Time (Hours)

10,000

Failure Criteria: 20% Idss Change

461

245 °C 260 °C

1,000

275 °C 100

290 °C

10 1

310 °C Biased at Idss 10%

50%

90%

Cumulative Failure Percentage Figure 10.8 Lognormal plot of degradation in channel current for five FET lifetests at different temperatures.

Acceleration factors for thermally accelerated failure mechanisms are typically found to follow the Arrhenius equation.  Ea  1 1  − − Acceleration Factor = e K T2 T1 (10.1) where Ea is Activation Energy (eV), K is Boltzmann’s constant (8.61423 × 10−5 eV), and T is absolute temperature (K). The median lives are determined by the methodology described in the previous section (using the lognormal distribution) and the temperatures are the life-test temperatures (converted to K). The remaining unknown value is the activation energy. With just two temperatures, the activation energy can be determined by direct substitution. If lifetests are performed at more than two temperatures, then the activation energy can be determined by performing a least squares linear fit as shown in the following example. Figure 10.8 shows the lognormal failure distributions for life-tests conducted at five different temperatures of 245, 260, 275, 290, and 310 ◦ C. These are all plotted using the failure criteria of 20% change in channel current – caused by the sinking gate mechanism. Whereas the transistors could last 4770 h at 245 ◦ C, they are degrading beyond the 20% limit in only 7.4 h at 310 ◦ C. Thus, lifetime is reduced by more than three orders of magnitude for a temperature increase of just 65 ◦ C. It is clear that the sinking gate mechanism is highly accelerated by temperature. Figure 10.9 shows a graph of median life versus junction temperature using a least squares linear fit. The activation energy, which in this case is 2.56 eV, is the slope of this line divided by K. Compared to failure mechanisms for silicon devices, which have activation energies from 0.3 to 1.2 eV, this activation energy is extremely high (remember, activation energy is an exponential term). Higher activation energy implies faster degradation in MTTF with increased temperature. Although high, it is not unexpected since the measured activation energy for the diffusion of Au and Ti in GaAs is 2.64 eV and 2.93 eV,

462

Reliability

Median Life (hours)

108

Biased at Idss

10K Years

107

1K Years

106

100 Years

2.56eV

105

10 Years

104 103 102

10 1 Hour

1 Year 1 Month 1 Week

Failure Criteria: 20% Idss Decrease 75 85 100

125

1 Day

150

175 200 225 250

300

Temperature (°C) Figure 10.9 Arrhenius-style plot showing median lifetime versus temperature extracted from Figure 10.8.

respectively, which is similar to the activation energy of sinking gates. Very similar results have been demonstrated for various FET devices, including pHEMTs. Now that a method of determining thermal acceleration factors has been defined, the previous question about predicting when failures will occur can be addressed. If the maximum specified operating peak hot spot temperature of a FET in a power amplifier application is limited to 150 ◦ C, then Figure 10.9 shows the projected median life for FETs at 150 ◦ C is about 1 billion hours, or 114,000 years! This prediction indicates that the sinking gate failure mechanism is not likely in need of improving, at least for the next few thousand years. One reason to use such a robust example to describe distributions and acceleration factors is to further delineate the difference between accelerated failure mechanisms and natural failure mechanisms. The accelerated test will often find the wear-out failure mechanism for the respective accelerated conditions, but the customer will experience failures caused by defects. We would not expect customers to ever see a sinking gate, and in fact they have not.

10.7.2

Current acceleration One of the principal wear-out failure mechanisms is electromigration. Electromigration is the mass transport of a metal due to the momentum transfer between conducting electrons and diffusing metal atoms. Discovered more than 100 years ago, electromigration became a concern only when the relatively severe conditions necessary for operation of integrated circuits made it painfully visible. Although electromigration exists whenever current flows through a metal wire, the conditions necessary for electromigration to be a problem simply do not exist on a macro scale. In bulk wires, such as those used for home appliances, the maximum current density is about 10,000 A/cm2 Any current density that exceeds this value will produce enough heat to melt a metal wire. However,

10.7 Acceleration factors

463

the driving force from electrons colliding into diffusing metal atoms would be insufficient to make electromigration a significant problem at those current densities used for industrial power distribution. All of this changed in 1966 when the integrated circuit was invented. Electromigration was rediscovered by semiconductor engineers. In circuits, electricity is conducted by interconnects that are miniature thin-film stripes that are capable of dissipating heat from very high current densities. Thin-film conductors can withstand current densities at least two orders of magnitude greater than traditional bulk wires. This allows current densities of nearly 106 A/cm2 without building-up enough heat to melt the interconnect. At current densities above 10,000 A/cm2, electromigration becomes a significant degradation mechanism. The first integrated circuits were constructed with metal lines made of pure aluminum, a material with a low melting temperature, which implies fast diffusion at low temperatures. Thin-film conductors on the semiconductor scale contain small grains with many grain boundaries that can be conduits for even more rapid diffusion. This combination of high current density and fast diffusion at low temperatures was disastrous for early circuits. Semiconductors were supposed to be very reliable compared to vacuum tubes, but when the first ICs were placed into service, they failed within weeks. The shock to the industry forced everyone to become an expert in understanding the electromigration failure mechanism. Since those early days the electromigration mechanism has not gone away, but it is now under control. Electrons flow through a metal film and collide with metal atoms. The collisions produce a force from momentum exchange on the metal atoms in the direction of electron flow for n-type materials (opposite for p-type materials). This force causes the metal atoms to move and this is termed electromigration. Electromigration is only significant at high current densities. The magnitude of the electromigration force is proportional to the current density, but Black [6] showed that electromigration failures have an inverse square dependence on current density J rather than the expected purely inverse dependence and that it is given by H t50 = A J −2 e( kT )

(10.2)

where t50 is the median time to failure in an ensemble of samples, A is a constant that needs to be empirically determined, and H is the activation energy for failure. Equation (10.2) is known as Black’s Law and has proven to be adequate even to the present day. To ensure that electromigration failure does not occur in the field, we need to limit the current density such that electromigration failure will not become significant until long after the projected useful lifetime of the circuit. This is a function of not only the current density in the metal lines and contacts, but also of temperature and other variables, such as interdiffusion, mechanical stress and the grain structure of the conductor. Interconnects and resistors also suffer from electromigration but the dependence on current density is no longer a pure inverse square law relationship. Thus, Black’s equation is generalized to median life =

Area ( Ea ) e kT Jn

(10.3)

464

Reliability

Median Life (Hours)

106

Plated Gold 250 °C n=4

105

NiCr Resistor 200 °C n=3

104 103 Ohmic Contact n=3.5 203 °C

102

n=1.5 Deposited Gold 300 °C

10 1 0.1

1.0 Current Density (M Amps/sq. cm.)

10

Figure 10.10 Current density acceleration factors for example metals used in amplifiers. Slope is

the current density exponent identified as “n” in equation (10.3).

30

60 40 20 0

40

Jc = 101 kA/cm2

100 80

Ic (mA)

Ic (mA)

120

20 10

0

2000

4000

6000

Time (Hours)

8000

0

Jc = 34 kA/cm2 0

2000

6000 4000 Time (Hours)

8000

Figure 10.11 L-Band HBT biased high-temperature operating lifetest degradation at a junction

temperature of 250 ◦ C and at two different current densities for transistor samples having 2.2 × 45 μm2 active area.

where J = current density, n = current density exponent, Ea = activation energy, K = Boltzmann’s constant, and T = temperature. Just as with the Arrhenius equation, the electromigration effects on lifetimes can be determined using a graphical approach. Figure 10.10 shows the graphed results for several example metallizations life-tested with different current densities applied. We can follow the same failure distribution and acceleration factor graphing technique for electromigration as we did for the metal interdiffusion mechanism of the sinking gate and extend the effect of current density into the realm of transistors. Many published results on HBT amplifiers have demonstrated that collector current density has a significant impact on transistor degradation. Most HBT suppliers recommend current density levels between 20 KA/cm2 and 50 KA/cm2 [7]. Degradation data for an L-Band HBT amplifier is shown in Figure 10.11. Plotting the time to failure versus the collector current using the data in Figure 10.11 results in the lognormal plots of the degradation distributions shown in Figure 10.12. Finally, the median times to failure for each HBT life-test done at different current densities as determined from Figure 10.12 will produce an estimate for the current density exponent if plotted against current density as shown in Figure 10.13.

10.7 Acceleration factors

100000

Time (Hours)

Time (Hours)

10000

465

1000

100

10000

1000

Tj = 250 °C Jc = 101 kA/cm2 10

10

2

30 50

70

90

98

Tj = 250 °C Jc = 34 kA/cm2 100 2

Cumulative % Failure

10

30 50 70

90

98

Cumulative % Failure

Figure 10.12 250 ◦ C Lognormal failure distributions of L-Band HBT biased HTOL degradation at

two different current densities.

Median Life (Hours)

106 HBT at 250 °C

105 104 n=1.5

103 102 10 1 10

100 Collector Current Density (K A/cm2)

1000

Figure 10.13 Current density exponent determination for 250 ◦ C L-Band HBT biased HTOL

degradation.

This plotting analysis exercise using Figures 10.11 to 10.13 demonstrates several important results. First of all, current density is an accelerating stress that degrades transistors in a similar way to interconnect metals. Second, HBT transistor reliability may be predicted by multiple applied current densities at constant temperature. Finally, HBT current handling capabilities are about an order of magnitude less than those of interconnects for roughly the same temperatures. These findings might indicate that even though HBTs are accelerated by thermal failure mechanisms, current density may be a more useful acceleration tool for measuring the reliability of these transistors.

10.7.3

Voltage acceleration factors (MIM capacitors are an important component of any RF circuit. As such, their long term reliability is an integral part of the overall dependability of an RF device. However, the accelerating stress for capacitors is almost entirely voltage. So unlike electromigration

466

Reliability

degradation, the effect of temperature as an accelerating stress is almost negligible. By employing the method of ramped voltage testing, almost any capacitor structure can be used to assess dielectric reliability. However, to measure defect density, larger capacitors are preferred. The expected failure mechanism for MIM capacitors is determined by measuring the TDDB. Ramped voltage testing is a viable process monitoring methodology which can be easily and effectively realized by on-wafer probing. Although thin dielectrics are used as gate dielectrics in silicon technologies, for the most part silicon nitride (SiN) capacitors with films less than 100 nm thick are uncommon in the compound semiconductor industry. However MIM capacitor thicknesses are expected to shrink, albeit at a much slower rate than gate dielectrics. For this example, we will examine a 50 nm thick silicon nitride capacitor. The bottom and top plates of these capacitors generally consist of sputtered gold metallizations. The bottom plate is built using the first local interconnect layer while the top plate is a restricted metal layer used solely for capacitors. The silicon nitride is a PECVDdeposited film with a dielectric constant of 6–8. These thin-film capacitors allow higher capacitance in a smaller chip area. While thinner nitride films are beneficial for on-chip density, they set a higher bar for manufacturability and long-term reliability. It then becomes essential to continuously monitor the quality of thinner nitride films and the over all capacitor fabrication process. Silicon nitride films are often categorized by their corresponding breakdown voltage. Different films have different breakdown voltage characteristics. In general, thicker nitride films exhibit higher breakdown voltages and are thus more forgiving of process and film variations. Thin MIM capacitors are more susceptible to deviations from the normal film quality as well as defectives introduced by the fabrication process. The robustness of a nitride film is generally characterized by an associated TDDB graph [8–10]. This is often used to predict a capacitor’s lifetime at a given voltage. Many publications on capacitor reliability have demonstrated the use of both constant voltage and ramp-to-breakdown methods in silicon nitride lifetime studies. The capacitance per unit area and leakage current at a set voltage are the typical parameters used as a figure of merit for MIM capacitors. The voltage-ramping of a capacitor to breakdown provides a means of monitoring capacitor quality, defect density, and allows TDDB analysis to predict MIM film robustness. Ramped TDDB studies are an accepted method of benchmarking capacitor reliability in today’s compound semiconductor industry. The capacitors used were manufactured using a mask set with MIMs of various sizes ranging from 1 × 103 μm2 to 8 × 105 μm2 . There were 6100 MIM capacitors on a wafer that could be individually probed and voltage ramped. Example ramping results on a population of capacitors is shown in Figure 10.14. When the results are ordered or plotted on a probability axis, the population of intrinsic and extrinsic devices is clearly obvious. Failure is defined to be when the leakage current exceeds 10 mA. This test is destructive. Voltage ramping is a powerful tool in the identification and classification of capacitor defects. For the ramp to breakdown measurements on large area capacitors, a ramp with voltage steps of 1 V was selected for convenience. The ramp rate was then adjusted

10.7 Acceleration factors

467

Process Variation 110

25 K um2 Capacitor

100

Intrinsic capacitor population (Good Capacitors)

Ordered Capacitor Data

Ordinal

90 80 70 60 50 40

Defect Density

Extrinsic capacitor population (Defect-driven)

30 20 10 0 0

5

10

15

20

25

30

35

40

45

50

55

60

Capacitor Fail Voltage (Volts) Figure 10.14 Ramp to failure data on a population of 25,000 μm2 capacitors.

to compensate for the size of the capacitor under test. Several intrinsic test capacitors were chosen and ramped to breakdown with at least two different voltage ramp rates to characterize the electric field acceleration factor, δ. Once this is known, the TDDB performance of the silicon nitride film can be predicted. For thinner SiN films the small area capacitors exhibit a small extrinsic population. The data was collected with a ramp that used 0.25 V steps. Based on these observations, the 5 × 103 μm2 capacitor was selected as the main test vehicle for ramped TDDB studies. In addition to limiting the maximum size to avoid extrinsic defects, a conscious effort was made to ensure a purely intrinsic population by including only voltages between the 5th and 95th percentile. Statistically, this did not affect the median voltage for each ramp rate but significantly improved the standard deviation of the data. The Table 10.3 shows the resulting median and standard deviation when the exclusion is applied to the data collected on various capacitors. Having selected an appropriately sized test capacitor and established a methodology to ensure an intrinsic population of capacitor breakdown voltages, several voltage ramp rates were investigated. Voltage steps of 1 V, 0.25 V, 0.1 V were utilized in combination with different time steps that varied from 5 ms to 200 s to achieve the desired ramp rates. Table 10.4 summarizes the different voltage and time steps that were used in the course of this investigation. This resulted in a broad distribution of voltage ramp rates. Early on it was evident that selecting the height of the voltage step dictated the granularity of the data. As such the use of steps of 1 V misleadingly quantized the distribution of capacitor breakdown voltages. The 1 V voltage step also necessitated longer time steps to achieve reasonable ramp rates negating one of the benefits of ramped voltage testing. Using this larger step size presented challenges to the test instrumentation. For

468

Reliability

Table 10.3 Comparison of median and standard deviation

Ramp rate

Cap size

Median

Std dev

Median exclude

Std dev exclude

0.5 V/s

1 K um2 5 K um2 10 K um2

46.75 46.50 46.00

0.88 0.92 1.32

46.75 46.50 46.00

0.47 0.45 0.47

5.0 V/s

1 K um2 5 K um2 10 K um2

51.25 50.25 50.00

0.81 2.12 0.73

51.25 50.25 50.00

0.43 0.45 0.36

50.0 V/s

1 K um2 5 K um2 10 K um2

54.50 54.00 53.75

7.34 1.05 0.94

54.50 54.00 53.75

0.38 0.42 0.37

Table 10.4 Voltage ramp rates Voltage step (V)

Time step

Ramp rate (V/s)

0.1

20 ms 40 ms 400 ms 1s

5.00 2.50 0.25 0.10

0.25

5 ms 50 ms 500 ms

50.00 5.00 0.50

1

20 ms 200 ms 2s 20 s 200 s

50.00 5.00 0.50 0.05 0.005

several combinations of time steps and capacitor sizes, the test system was erroneously reporting a higher voltage than what was actually being applied to the capacitor. For the TDDB studies, it was determined that smaller step sizes are more useful. Voltage steps of 0.1 V and 0.25 V provide a broad distribution of voltage ramp rates with reasonable test times. The selected voltage and time step combinations were successfully implemented by a parametric test system. Besides capacitance and breakdown voltage, the leakage through a capacitor is also measured. This is usually done at a single voltage and a shorted capacitor would be easily evident. The data collected from this measurement can be interpreted into a defect density number at that voltage. But by doing so, the only extrinsic defects that can be detected would be those which short the capacitor at voltages lower than or at the test voltage. The advantage of a ramped voltage test would be the ability to detect defects

10.7 Acceleration factors

469

99.9

Size 25 K um2 50 K um2 100 K um2 200 K um2 400 K um2 800 K um2

99

Population (Percent)

95 90 80 70 60 50 40 30 20 10 5 1 0.1 0

6

12

18

24

30

36

42

48

54

60

Ramp Failure Level (Volts) Figure 10.15 Capacitor breakdown voltage for various area capacitors.

at every voltage step. Its only disadvantage is that it is a destructive test which damages the capacitor. Figure 10.15 shows all the data collected from one of these reliability test wafers sorted by capacitor size. For the ramped voltage TDDB studies, three different wafers were used to collect the necessary data. Two of the wafers came from a single fabrication lot while another wafer was taken from a separate lot. All 50 nm capacitors measured in this study had the same SiN MIM film. This exercise was done to make certain of the consistency of the ramped voltage method across material. Figure 10.16 shows the ramped voltage data collected for 5 × 103 μm2 MIM capacitors using voltage steps of 0.1 V and 0.25 V. Ramp rates of 0.1 V/s, 0.25 V/s, 0.5 V/s, 2.5 V/s, 5 V/s, and 50 V/s were used. Table 10.5 summarizes the median and standard deviation of the capacitor breakdown voltage for the material subjected to the ramped voltage test. Using the data from Table 10.4, the electric field acceleration factor δ can be calculated using any combination of two different ramp rates and median failure voltages using the equation below:   1 ln Rate Rate 2 δ= (10.4) E1 − E2 The results of this calculation are shown below in Table 10.6. Different combinations of ramp rates and median failure voltages result in a consistent value for the electric field acceleration factor. This is also seen to be relatively constant when tested across different wafers.

Reliability

Table 10.5 Capacitor breakdown voltage

Material

Voltage step

Lot A, Wafer 1

Ramp rate

Median

Std dev

0.25 V

0.5 V/s 5.0 V/s 50.0 V/s

46.50 50.25 54.00

0.64 0.68 0.59

Lot B, Wafer 2

0.25 V

0.5 V/s 5.0 V/s 50.0 V/s

47.50 51.25 55.00

0.76 0.89 0.76

Lot B, Wafer 3

0.10 V

44.4 49.3 49.6 50.7

0.84 0.92 0.79 0.83

0.1 V/s 0.25 V/s 2.5 V/s 5 V/s

Table 10.6 Electric field acceleration factor δ

Ramp combinations Combination 1 Combination 2 Combination 3 Combination 4 Combination 5 Combination 4

Lot A, Wafer 1 0.25 V step

Lot B, Wafer 2 0.25 V step

Lot B, Wafer 3 0.10 V step

3.07E-08 3.07E-08 3.07E-08

3.07E-08 3.07E-08 3.07E-08

3.15E-08 3.12E-08 3.10E-08 3.11E-08 3.10E-08 3.05E-08

99.9 99

Population (Percent)

470

5 K um2 Capacitors

5.0 V/s 5.0 V/s

0.1 V/s

95 90 80 70 60 50 40 30 20 10 5 1 0.5 V/s

50.0 V/s

1.0 V/s 2.5 V/s

0.1 42

44

46

48

50

Ramp Failure Level (Volts) Figure 10.16 Ramped voltage data at various ramp rates.

52

54

56

10.7 Acceleration factors

471

1014 1013 1012

Time To Failure (Seconds)

1011 1010 109 108 107 106

Me

dia

105 104

n

103 102 10

100

1

pp

0.1 10–2

m

10–3 10–4

0

5

10

15

20

25

30

35

40

45

50

55

Applied Voltage (Volts) Figure 10.17 Lifetime prediction for capacitors relative to applied voltage.

Once the electric field acceleration factor is known, predictions of capacitor lifetimes can be made. Since all capacitor ramp measurements were made at room temperature, the TDDB equation does not need to include the Arrhenius portion, so lifetimes can be represented by Time to failure = e−δ E

(10.5)

where E is the electric field. Figure 10.17 shows the resulting lifetime prediction for capacitors with a constant voltage applied. Note that the median time to failure is plotted as well as the time to the first 100 parts per million (1 in 10,000 capacitors). Ramped voltage testing of capacitors across a wafer allows a process monitoring methodology that facilitates the improvement of capacitor yield and long-term reliability. Capacitor defect densities at a suitable voltage and capacitor operating lifetimes can be measured and monitored for a particular nitride film thickness. Just as current density is an important stress for HBT devices and ICs, applied voltage has been found to accelerate failure mechanisms in GaN HEMT devices. AlGaN/GaN HEMTs were investigated [11]. Standard life-tests were conducted at drain-to-source biases of 15, 20, 25, and 30 V at 10 GHz drive with the devices driven 3 dB into compression at room temperature. Under these stress conditions, the change in output power was monitored for 20 h and the results are shown in Figure 10.18. The degradation distribution of each group of the transistors was analyzed, and Figure 10.19 shows the resulting prediction of time to failure (1 dB failure criteria) for the respective channel voltages that were applied. The logarithmic relationship of lifetime to applied voltage is very similar to those found for capacitors. These HEMT results indicate that applied voltage with RF drive provides a viable stress for life-testing of AlGaN/GaN HEMTs. No temperature acceleration is needed to examine this degradation mechanism. In fact, a negative activation energy was observed

472

Reliability

0.2

Change in Power Out (dB)

0.0 –0.2 –0.4 Vds = 15 V –0.6 Vds = 20 V –0.8

Vds = 25 V Vds = 30 V

–1.0 –1.2 0

5

10

15

20

Stress Time (Hours) Figure 10.18 Change in output power for AlGaN/GaN HEMTs stressed with four different

channel voltages and under 3 dB compression at room temperature.

Time to 1 dB loss of Pout (hours)

10000

1000

100

10

1

30

25

20

15

Vdg in Volts Figure 10.19 Time to fail versus applied voltage to the transistor.

in thermal life-tests on these devices. Results are consistent with a hot carrier induced failure mechanism.

10.7.4

RF bias acceleration One aspect of accelerated reliability stress that is relatively new is RF biasing. Testing of individual transistors with RF bias has been conducted from time-to-time, but the concept of RF drive as a wear-out mechanism is new. Past RF drive tests have included

10.8 Reliability predictions (MTBF, MTTF, FITs, etc.)

473

6 5 Thick Gate Oxide 1dB compression

Projected Degradation (% Id sat)

7

4 3 2 1 0 –25

Thin Gate Oxide –20

–15

–10

–5

0

5

10

15

5 Year RF Input Drive (dB m) Figure 10.20 Model of % degradation of Ids after five years versus RF input power drive for thick

and thin NMOS devices. Note, this integrated power amplifier is at 1 dB compression at an applied input power level of +8 dB m.

temperature as the primary method of acceleration. Even though some RF drive conditions have added considerable power (and temperature) the tests would keep RF stimulus constant and conduct stress testing with multiple temperatures. As RF power continues to increase in commercial applications – such as for cell phones – interest in RF acceleration also increases. Some cell phone PA module qualification testing has recently shown that filters subjected to high RF drive levels will degrade while the active parts of the module seem to be relatively unaffected. The design models for the hot carrier injection failure mechanism in CMOS devices has progressed enough that a recent model was utilized to predict the degradation of a radio chip under various RF inputs [12]. The authors determined that the primary wear-out mechanism in their integrated power amplifier would be caused by hot carrier injection since the RF transistors in the amplifier core are NMOS devices configured in a cascade structure which was susceptible to Vds swings which were modeled for various RF drives and also for two different oxide thicknesses. Figure 10.20 shows the projected degradation after five years of stress. As more RF biased life-testing is conducted, perhaps more reliability relationships will be discovered for use in predicting lifetimes.

10.8

Reliability predictions (MTBF, MTTF, FITs, etc.) It is a basic belief of reliability engineers that failures must be generated to quantify product reliability. Failures are required to identify the root causes of reliability problems, or to evaluate the weakest link of an IC so that changes can be made to improve the

474

Reliability

reliability. Failures also provide the reference point for future comparisons. If life-tests are performed before and after a process change, and they both result in zero failures, there’s no way to decide if the process change improved or impaired the reliability. Most importantly: without fallout, a failure distribution cannot be determined. It is auspicious that the published work on amplifier reliability contains many thousands of failures. Just any failure will not do, however. The failure must be representative of degradation that occurs in actual use. To ensure the usefulness of the failures generated, a five-step procedure for evaluating devices is recommended: Step 1. Operational analysis. Step 2. Thermal analysis. Step 3. Step stress test. Step 4. Life-test. Step 5. Acceleration factor test. The five steps begin with an operational analysis. The operational analysis is simply an investigation into the normal operating conditions of a particular device. During the analysis, the proper biasing techniques to cause the device to be in a representative state are investigated. The operational analysis includes developing fixturing which can maintain the device in its desired state and engineering a technique or methodology for electrical measurements which will ensure repeatable and reproducible results throughout all the subsequent testing. Part of this first step includes an evaluation of the device as configured for testing. Specific checks are conducted to ensure that the device does not oscillate or otherwise switch into an anomalous state, especially at high temperature. Power supply interactions are also investigated as to the effects of proper power-up and power-down sequencing, overshoot at turn-on, soft shut-off, and the effects of glitches or other interruptions during operation. The second step in finding representative failures is a thermal analysis. This is an absolutely necessary step. Determining device temperatures is a key part of any reliability study, especially if acceleration factors are to be determined accurately. There are several possible methods for measuring temperature, each with different advantages and disadvantages. Temperatures of the entire IC package environment are best evaluated from case to hotspot. The hotspot temperature is important for accurate calculations, but the case is the best reference point for a packaged device. It has been determined that peak hotspot temperatures are the least ambiguous parameters to define because environmental effects such as air flow, humidity, and heat-sinking need not be examined. The measurement and calculation of die temperatures is discussed in detail in Chapter 9. Systems which exhibit constant failure rates may be characterized by a simple parameter – mean time between failures (MTBF). In such cases, the mathematics of reliability becomes very simple. However, the assumption of constant failure rates in systems is not correct for most integrated circuits, which instead follow more complex distributions of degradation that may vary significantly with the type of accelerating stress being applied and with the actual conditions the device experiences throughout its lifetime. Although well understood since the early seventies, nonuniform failure distributions were largely ignored by systems engineers in favor of the simpler constant failure

10.9 Wear-out versus defects (acceleration versus real life)

475

rate and MTBF calculations. Even today, the simpler calculations shown in equations (10.1) and (10.2) are preferred over the more complex relationships between failures and time as shown in equation (10.6) where Q(t) is defined as the probability that a device will fail in a time equal to or less than t (i.e., the fraction of the population that has failed up to time t) t Q(t) =

f (t)dt

(10.6)

0

where f (t) is the failure probability density function which, for a log-normal distribution, is given by   1 1  2 (10.7) f (t) = √ exp − 2 ln t tm 2σ 2π σ t where σ and tm are the standard deviation and median time to failure, respectively. The failure rate λ for a constant failure rate system is defined as the number of failures divided by the total time for these parts to fail and in this case MTBF = 1 λ (10.8) The reliability unit commonly used for failure rates today is the FIT. A FIT is a shorthand unit of measure for the rate of failures in time. Originally, reliability engineers measured the failure rate in units per hour. As the reliability of semiconductors improved, they changed this to % per 1000 h. Then when reliability improved beyond 0.01% per thousand hours, they made up a Failure unIT, which was equivalent to 0.0001% per thousand hours, and gave it the name FIT. Over the past 30 years, engineers switched the name from Failure unIT to the acronym Failures In Time, but they kept the units the same. So, the FIT is merely a rate unit of convenience, similar to measuring speed in MPH, a FIT has the units of failure fraction per hour. For mathematical convenience, we sometimes refer to a FIT as failures per billion hours – but even though that statement is easy to understand mathematically, failures per billion hours is not technically correct.

10.9

Wear-out versus defects (acceleration versus real life)

10.9.1

Thermal excursion example no. 1. Interconnect vias The focus of most reliability testing has been on high-temperature life testing. Several failure mechanisms are highly accelerated by temperature, so this methodology has produced data that is easy to analyze and straightforward to predict applicable – albeit very long – lifetimes. However, some devices actually fail for quite different failure mechanisms during typical use. This section will address a failure mechanism accelerated by thermal excursions such as temperature cycling, thermal shock instead of high temperatures. This short summary is intended to provide information on the methodology, implementation, and results of reliability assessments enacted by thermal excursion testing.

Reliability

Table 10.7 Standard thermal excursion definitions

Test

Type

JEDEC specification reference

Range

1 2 3 4 5

Infrared reflow Thermal shock Thermal shock Temperature cycle Thermal shock

JESD22-A113 JESD22-A106 condition D JESD22-A106 not specified JESD22-A104 condition G JESD22-A106 condition B

+25 ◦ C to −65 ◦ C to −40 ◦ C to −40 ◦ C to 0 ◦ C to

Cycles +240 ◦ C +150 ◦ C +125 ◦ C +125 ◦ C +100 ◦ C

<20 <20 <100 <500 <2500

250 225 200

Temperature (°C)

476

175

45 Seconds > 235 °C 150 125

180 Seconds > 183 °C 100 75 50 25

0

60

120

180

240

300

360

Time (Seconds)

Figure 10.21 IR reflow thermal profile.

Historically, accelerated tests such as temperature cycling are good at finding the same natural failure mechanisms discovered by customers and so thermal excursion testing is both important, and representative of what causes failure in devices under normal use in the field. As an example, a particular RF gain block IC was investigated to examine the consequences of using IR an reflow solder process on the device. Figure 10.21 shows the reflow profile. This particular IC suffered from a metal interconnect track going open circuit during the soldering process. Thermal excursion testing is accomplished by subjecting samples to temperature extremes. These extremes are generated by thermal conduction in air, immersion in inert liquids, or by infrared radiation. All of the excursion testing is designed to alternate rapidly between the extremes. Each of the three types of excursion testing used in this study is specified by JEDEC specifications (see Table 10.7). The test conditions are shown in Table 10.8. For each test, a sample of 100 parts was selected and measured.

10.9 Wear-out versus defects (acceleration versus real life)

477

Table 10.8 Thermal excursion profile data

Test

Type

Maximum transfer time

Minimum dwell time

Maximum time to temp.

1 2 3 4 5

Infrared reflow Thermal shock Thermal shock Temperature cycle Thermal shock

∼140 s 10 s 10 s 1 minute 10 s

20 s 2 minutes 2 minutes 10 minutes 2 minutes

6 minutes 5 minutes 5 minutes 15 minutes 5 minutes

120 #1. IR Reflow +25 °C to +240 °C #2. T/S –65 °C to +150 °C

Percent Fallout

100

#3. T/S & #4. T/C –40 °C to +125 °C

80

60 #5. T/S 0 °C to +100 °C

40 20

T/S = Thermal Shock T/C = Temperature Cycle

0 0

0.5

1

1.5

2

2.5

3

3.5

Thermal Excursion Log Cycles Figure 10.22 Thermal excursion failure distribution data for four stresses. Regression shown by dashed lines.

Samples were subjected to thermal shock using rapid transfer between two fluorinert liquid baths – one hot, one cold – and temperature cycling which involved air-to-air transfer of material between adjacent chambers at the two temperature extremes. The resulting failure distributions were analyzed and found to be logarithmic (not necessarily lognormal). In other words, the number of failures increased linearly with the log of the number of cycles as shown in Figure 10.22. Additionally, all of the excursion testing resulted in the same slope of failure accumulation except the most benign test, which had a slope half that of the others. This difference would indicate either a threshold of some type in the mechanism, or perhaps a different mechanism. When using the same temperature range, both the thermal shock and thermal cycling testing had the same results. Even though the delta (215 ◦ C) of temperatures in a simulated solder reflow (+25 ◦ C to +240 ◦ C) is the same as –65 ◦ C to +150 ◦ C, the reflow caused considerably more failures in the same number of excursions. The data indicates that the excursion delta is definitely an acceleration factor for

478

Reliability

Initial Percent Failure

60 50 40 30 20 10 0 0

50

100 150 Temperature Delta (°C)

200

250

Figure 10.23 Comparison of excursion delta to failure percentage after one excursion for cycling

and shock.

the mechanism in this study. The percentage of initial failures after one cycle at several test conditions is shown in Figure 10.23. For the failure mechanism in this study, there is no difference in sample degradation between thermal shock and temperature cycling stresses, at least for the conditions of –40 ◦ C to +125 ◦ C. Four of the tests had a slope of 20% failure per log cycle, and the fifth had a 10%/log cycle slope. It is clear from Figure 10.22 that for this particular failure mechanism, one reflow simulation is approximately equal to eight thermal shocks from –65 ◦ C to +150 ◦ C, or to 144 thermal shocks (or temperature cycles) from –40 ◦ C to +125 ◦ C, and to 4,989,000 thermal shocks from 0 ◦ C to +100 ◦ C.

10.9.2

Thermal excursion example no. 2. Copper bump Another example where thermal excursion testing is extremely valuable is flip-chip die attach. Flip-chip eliminates wire-bonds and the need for substrate vias so semiconductor processing and assembly is greatly simplified. Flip-chip can be implemented in practice by using copper solder bumps, and these are very effective at removing heat from the die since they are placed near the sources of heat. For this study, flip-chip was implemented in an existing commercial amplifier module application. The module includes a copper interconnect laminate base, an injection molded thermo-set epoxy overmold, standard GaAs HBT process die, with a copper plated bump, and tin solder. See the diagram in Figure 10.24. Note, Figure 10.24 is not to scale and does not represent overall size ratio of the components inside the module. In some experiments, the under-fill material is replaced by over-mold epoxy. A special test structure was designed and manufactured to investigate the primary failure mechanisms expected for the flip-chip construction. This type of Failure Mechanism Analysis (FMA) included consideration of all types of failure mechanism, i.e., die, assembly, and module. FMA also differs from failure modes and effects analysis (FMEA) because the failure modes, severity, and detection aspects are not considered.

10.9 Wear-out versus defects (acceleration versus real life)

479

Module Overmold Epoxy Flipped GaAs Die

Bond Pad

Passivation

Cu Under Bump Metal (UBM)

Sn

Solder Mask

Bump Underfill (Optional)

Cu

Solder Pkg Pad

Module Laminate Pkg lead Figure 10.24 Flip-chip technology description.

Overmold Epoxy

Semiconductor Die (Flipped)

Laminate Substrate

Figure 10.25 Cross-section of the flip-chip Test Structure.

Instead the mechanisms, the accelerating stresses, and the structures for detecting the mechanisms are of primary importance. Using the FMA approach, mechanisms are ranked by their likelihood, and then considered for incorporation into the test structure layout. The test structure developed for this example includes a daisy chain of 36 bumps, a special detector, and a 15 W heater. A polished cross-section of the test die, mounted in a module, is shown in Figure 10.25. The detector was designed for multiple purposes. It serves as a temperature monitor, a mechanical fracture detector, a solder creep detector, and a leakage monitor. A

480

Reliability

Table 10.9 Failure criteria Resistance values Structure Daisy chain (cold) Daisy chain hot Detector (cold) Detector hot Chain-detector Detector-heater Heater

Leakage

2X

Open

X X X X

X X X X

X X X

laminate-based substrate was designed to match up with the structure and form the bump-interconnect daisy chain. Normal manufacture includes a standard encapsulate. Various under-fill materials and bump configurations were investigated using the test structures. Thermal excursion testing was accomplished by subjecting samples to temperature extremes generated by thermal conduction in air, immersion in inert liquids, by convection, infrared radiation, or by power dissipated within the device. All of the excursion testing is designed to alternate rapidly between extreme temperatures. The reference level of testing used in this study was temperature cycling, per JESD22-A104 Condition G, –40 ◦ C to +125 ◦ C, 1000 cycles. In this study, excursions were accelerated and increased up to >250 ◦ C using on-chip power cycling. An on-chip thermometer verified average die temperatures. For the primary investigation, various power cycling conditions were applied to several different flip-chip lots. The cycling parameters of power, time on, and time off were varied and compared to results from the reference level test results. In addition to the variable of the applied stress, other parameters were also evaluated. For example, various solders, under-fills, and assembly pretreatments were investigated using population samples. Typically, resistance changes in a daisy chain were used to assess aging. The failure criteria shown in Table 10.9 were applied. Each of the three resistance paths (daisy chain, detector loop, and heater resistor) were measured at “room temperature” and immediately after a power cycle of the heater. Immediate measurements were generally within 20 ms of the heat pulse, although some “hot” measurements could be up to 0.5 s after the heat pulse. Changes in resistance were found to be relative to the time after heating. In some instances, resistances would increase upon cooling, but in other situations the opposite effect would occur. Obviously, this type of information is not usually available from standard temperature cycling where the devices are measured at set intervals. Figure 10.26 shows an example of data accumulated during power cycling on a single test structure. The failure mechanism for these devices was an open circuit in an interconnecting pathway. Average die temperatures could be easily monitored during the stress using the detector loop. As expected, increases in heater current resulted in failures with

10.9 Wear-out versus defects (acceleration versus real life)

481

10000

Max Die Temp = 202 °C

Detector Hot 512 cycles

Resistance (Ohms)

1000

Detector 673 cycles Heater Resistor: 448 to 400 ohms 856 cycles

100

Daisy Chain 277 cycles daisychain

Daisy Chain Hot 493 cycles

10

detector heater isolation daisychainHot

Isolation Fail at 703 cycles

detectorHot

1 0

200

400

600

800

1000

1200

Power Cycles (Heater = 2 sec ON, 20 sec OFF, 179 °C Rise)

Figure 10.26 Typical resistance changes observed during power cycling.

fewer power cycles. The intent of investigating such a range of stress parameters is to produce a representative type of degradation in the fastest possible time. Failure analysis was a key part of the investigation since anomalous failures were not the objective. Examples of anomalous failures generated in this study are: heater resistor burnout, device interconnect failure, and melting of dielectrics or overmold plastics. By adjusting the heater power and the heating time, all of these anomalies could be avoided, and legitimate mechanisms were consistently generated in a highly accelerated manner – in hours instead of weeks. Multiple failure mechanisms were generated using power cycling on the test structure. One of those generated was identical to failures observed during traditional air-to-air temperature cycling tests. In general, the mechanisms varied across each individual sample – depending on proximity to the on-chip heater. Cracking within the bump itself was never observed. The predominant type of daisy chain failures observed during power cycle aging was solder fatigue. This mechanism was also observed in traditional temperature cycling. Normally, the crack would form through the center of the solder, as shown in Figure 10.27. However, cracking was also observed nearer to the solder intermetallic compound (IMC) interfaces. The result of standard temperature cycling aging is the solder fatigue crack shown in Figure 10.28. This crack took 2000 cycles to form per the standard excursion and dwell times, and it is the expected failure mechanism for this structure under these aging conditions. No failures were noted at read points with fewer cycles. This aging took 42 days to complete. In contrast, the crack in Figure 10.27 took 81 minutes to generate in accelerated power cycling testing. Both cracks shown in Figure 10.27 and

482

Reliability

Copper Bump

Trace on Laminate

Figure 10.27 Typical flip-chip failure cross-section – separation within the solder after 153 cycles

of 2 s on, 30 s off with a 4.8 W heater.

Semiconductor Die

Copper Bump

Trace on Laminate Figure 10.28 Standard temperature cycle flip chip failure cross-section – note similarity to

Figure 10.27. This is a typical solder fatigue failure after 2000 temperature cycles or 42 days of thermal excursion aging.

Figure 10.28 measured open electrically at room temperature before cross-sectioning. Thus, thermal excursion failure mechanisms can be accelerated to assess flip-chip reliability using on-chip power cycling.

10.9.3

Defect amplification and K factors Regardless of the measured lifetimes, there have been few wear-out failures reported during use of the circuits. Instead, customers do report measurable defect rates and early life failures that often match-up with yield fallout failure mechanisms. This section investigates a particular defect that not only corresponds with many of the early life

10.9 Wear-out versus defects (acceleration versus real life)

483

failures, but is also unique to compound semiconductor manufacturing. The defect is generalized as liftoff metal shorting. Defects are those rare artifacts that are present in every process, but seldom discussed in reliability investigations. The important extrinsic reliability failures occur from defects that degrade to a complete failure under nominal aging and use conditions. The most prevalent defects which fall into this category are: r r r r r

capacitor dielectric defects; metal intralevel connection defects; adjacent contact short defects; metal interconnect short defects; contact or interconnect step coverage defects.

Although capacitor defects are among the most commonly reported types of defect, they have already been thoroughly reported for GaAs devices [13–15]. Intra-level (via or plug) type defects and their associated thermal excursion acceleration methods have been similarly discussed [16]. This leaves the next two defect types related to shorting of contacts and metal interconnects. In general, both contacts and adjacent interconnects are formed by the same process technique named liftoff. Liftoff is a metal deposition technique that involves no specific metal etching. The process involves these steps: 1. Apply photoresist. 2. Pattern the photoresist to define x and y dimensions of the metal. 3. Deposit the metal. Note that the metal covers everything including the remaining photoresist and open areas where the photoresist has been removed. 4. Remove the photoresist, and “liftoff” the unwanted metal on top of the photoresist. Metal remains in the patterned areas. This technique can be contrasted to the typical process of depositing a blanket metal, applying photoresist, developing the photoresist as an etch mask, and then “subtracting” the unwanted metal by etching the entire field except areas protected by the etch mask. Both techniques have benefits and issues, but because of the difficulties of etching gold, the liftoff technique is very commonly used for the gold-based metallizations utilized in compound semiconductors. The liftoff metallizations can include: (a) contacts (gate, ohmic, emitter, base, and collector); (b) interconnect layers (deposited layers which are primarily gold); and (c) resistors (usually thin-film type such as NiCr or TaN). Liftoff defects are introduced by excessive process or material variation, random contamination, or mechanical damage during handling. As an example, photolithography defects may cause electrical “near opens” or “near shorts.” Examples of “near opens” are rare for compound semiconductor metallizations (see Type V above). These would lead to the type of extrinsic failures that could be accelerated by increased current density resulting in electromigration at a reduced metal cross-section. The “near shorts” are more prevalent for compound semiconductors, and they are accelerated by electric field resulting in dielectric breakdown between contacts or metal stripes.

ef ec

t

Reliability

D

484

Metal Trace Yield Loss. (Shorts)

Reliability Concerns.

Unknown?

Figure 10.29 Shorting-type defects for liftoff metal lines with constant defect size and increasing

spacing.

For interconnect metallization, there are the same two main types of defect, namely shorts and opens. Figure 10.29 shows a simple example of intralayer shorting defects. In this case, the width of the metal and the defect remains constant but the spacing varies leading to different consequences. With the narrowest spacing, the presence of this defect will result in an electrical short. At moderate spacing, the shorts are less probable, but the reliability may be impacted. At the widest spacing, this single defect does not matter. Of course, changes in defect size and occurrence are significant factors. Various sizes of interconnect may also have a second-order effect. In this study, shorting type defects were examined. The defects are shorts or near shorts which occur in the liftoff metallization processes. Yield is normally considered a measure of the percentage of acceptable devices at time zero. As we plan to use both time and voltage as independent variables, the definition of yield will change with aging so we will use a very specific definition for yield, namely quality at zero age. This definition of yield will later emerge as the value of the y intercept for whatever aging measurement (voltage or time) is selected as the independent variable (x). Likewise, we will define reliability as a function of time, i.e., a rate of quality. This is more often defined as a rate of “un-quality,” or failure. In order to carry the reliability definition even further, we will need to remove the rate, and classify reliability as a “prediction of quality.” This is necessary, since we plan to use accelerations other than time. As we have defined yield as quality at age equal to zero, reliability will be defined as quality at age greater than zero. So, rather than use yield as a quality measurement across different variables, we will use quality as a measurement of nondefective (nonshorted) devices. Note that this definition of yield is different from other studies which often use yield to define and describe quality – regardless of the prior history or aging up the point of measurement. This study first quantified defectiveness in terms of quality and yield. Once the defects were characterized, the effect of age acceleration levels on the measured shorts could be examined. Voltage acceleration is well established for aging and measuring capacitor reliability, but voltage is not reported so much for metal shorting or for measuring yield relationships. As the occurrence of defects was found to be related to voltage, a relationship between quality and reliability could be derived.

485

Test Structure Quality Level (%)

10.9 Wear-out versus defects (acceleration versus real life)

Spacing Between Metals (Approximate 100 nm Units) Figure 10.30 Quality versus spacing in a comb-style test structure.

Using the spacing in Figure 10.29 as a variable, the dependence of quality can be characterized for various spaces between metal traces. Figure 10.30 shows how quality is affected by the spacing. Figure 10.30 would obviously be utilized to set layout design rules for optimum quality and circuit density. However, we will exploit our knowledge of this curve to amplify detection of defects for populations which follow this relationship. In Figure 10.30, we expect very high quality at the minimum allowed spacing (layout) limit. Eventually, with long enough adjacent traces of closely spaced metal there will be a defect. Assuming there is a practical limit to the adjacent metal periphery, another means of acceleration or amplification is sought. In order to increase the likelihood of detecting the rare defects, we propose a decrease in the spacing as an amplifier of defects. With decreased spacing, more and more defects can be detected, but there is a risk that the type of defect will change. For example, smaller and smaller defects will show up with narrowed spacing. These smaller defects may not ever be a concern for wide (nominal) spaced lines. Normally, the size of the defect and the location of the defect relative to metal patterns are the most important considerations. However, we have found that the applied voltage of the quality measurement is equally as important. In circuit layouts, the tightest nominal spacing occurs between transistor contacts. The proximity of these contacts makes them important for defect studies. However, the presence of the semiconductor makes the measurement of “quality” at high voltages impossible – as the semiconductor leakage will mask the detection of the shorts. highvoltage characterization of the shorting type of defects is possible for metal interconnect metallization as this is not in contact with the semiconductor but is not possible for transistor contact metals. Similarly, if the spacing is kept constant, and the voltage is increased the graph in Figure 10.31 results.

Reliability

Resulting Yield

486

Applied Voltage (Volts)

Figure 10.31 Quality versus voltage for different spacing between metal lines.

A logical relationship between quality and reliability has been pondered for many years. Investigations into relationships between yield and reliability began with the first defect characterizations by Stapper two decades ago [17, 18]. Later, a ratio of quality defects and reliability defects was proposed by Shirley [19] in the form K =

Reliability defect density Quality defect density

(10.9)

Shirley postulated that this ratio K is a constant, and that each failure mechanism has its own ratio. He also suggested the ratio was at least 1/100. Estimates for this ratio have expanded to a region between 1/100 to 1/1000 [20]. Simply put, for every 1000 Quality Defects, i.e., yield at age zero, you should expect between 1 and 10 reliability defects. Using the K ratio, many studies have investigated and optimized burn-in [21]. Estimating reliability from a sample population is difficult because there are few detectable reliability defects – particularly in the extrinsic region. There can be so many more failures available from the intrinsic region if the devices are accelerated to wearout. However, we are focused on the extrinsic failures for this study so the traditional acceleration methods and wear-out failures need to be avoided, or separated from the population of interest which is the defects i.e., the extrinsic population. Figure 10.30 provides the first important clue towards accelerating the detection of defects: narrow gaps generate more fallout. Figure 10.31 shows the second clue: higher voltage generates more fallout. A relationship between these two accelerations is intuitive since decreasing the gap is effectively increasing the electric field – at least for the defects that are nearly but not yet shorted in the gap of interest. Figure 10.32 shows the combination results of different gap sizes and increasing voltage measurements. All data is normalized for a constant periphery of 1 cm.

487

Test Structure Quality (% per cm)

10.9 Wear-out versus defects (acceleration versus real life)

Applied Aging Stress (Volts)

Figure 10.32 Quality versus voltage for various normalized gap spacing of interconnects.

Figure 10.32 indicates several relationships. Note that each of the gap experiments includes a sample of more than 70 structures, resulting in a population total of 500 for this data set. As expected, the number of defects increases as the gap between the lines decreases. The rate of defects per volt also increases with decreasing gaps. These relationships are predictable and monotonic for all the gaps – except the structure with the narrowest spacing we measured. This discrepancy at narrow gaps indicates that there is a limit to the spacing amplification. At this point, it could not be determined if the defect–gap–voltage relationships changed at wide spacing since the detectable defect level dwindles to such a meager level. Basically, the defect samples became undetectable at the upper gap edge of our data set. A different acceleration or more periphery is needed to characterize the lowest defectiveness region of these relationships. An interesting result of using voltage acceleration is that for constant gaps, the populations of defects are similar in behavior to the extrinsic population of capacitors [15, 22, 23]. But, the failure modes remain somewhat unique. For example, under constant voltage, capacitor leakage will decrease until a catastrophic short occurs [9, 24]. The metal line structures in this study exhibit either stable or slightly increasing leakage up to the catastrophic short. Nonetheless, the huge base of capacitor reliability knowledge is likely to be applicable if we remember the focus on extrinsic distributions. These results have unveiled the ability to measure defects and apply improvement techniques that have been established for other structures – such as capacitors. This opens up opportunities for measuring, monitoring and screening in ways not previously discussed for compound semiconductor devices. These results bridge the gap between quality and reliability. The focus is specifically on early life failures – the ones that customers actually experience. Progress on this type of failure is necessary to improve

488

Reliability

reliability on any maturing process. This work demonstrates that quality has a clear relationship with device reliability.

10.9.4

Environmental example – humidity activation energy Product reliability investigations typically include accelerated humidity testing. Originally, the standard test was a biased 85 ◦ C/85% relative humidity (RH) life-test for 1000 h. Recently, a substitute accelerated version of this test has been used. The accelerated version is called HAST (highly accelerated stress test). The HAST conditions are also biased, at 130 ◦ C, 85%RH, and approximately 18 PSI overpressure. The duration of the HAST test is normally 96–100 h – to be equivalent to the 85/85 test [25]. This section is intended to describe thermal acceleration in moisture and show that equivalent HAST tests on compound semiconductors are more highly accelerated and could be concluded much faster than indicated in the HAST standard. Compound Semiconductors utilize different metallizations, dielectrics, and contacts than silicon devices and so it should not be surprising that there are different failure mechanisms between the two technologies. The humidity acceleration factors were originally based upon typical silicon-based mechanisms, such as aluminum corrosion. GaAs substrates have a unique set of failure mechanisms. For example, the gold metallizations utilized for compound semiconductors are not as reactive as aluminum or copper, but gold can still be susceptible to moisture and bias if ions or other catalysts are available. The study of humidity acceleration factors has been extensive and complex. Testing in humidity is much more than just thermal life-testing overlaid with another environmental dimension. The addition of humidity demands attention to plastic encapsulation, to interactions between stress variables, and to complexities of moisture adsorption in complex packaging systems. These complexities can be simplified by focusing on one product, one package style, one bias, one failure mechanism, and several accelerated temperatures that are above 85 ◦ C. The product investigated here is a simple low noise amplifier with an RF switch in an MLF/QFN style lead frame plastic package. The device does include two separate die for optimum pHEMT and HBT functionality, but all the focus will be on the pHEMT die. This is not a special device or package that is designed to focus on specific aspects of humidity testing, instead it is an actual product. Humidity test biasing is often an under-reported aspect of the reliability testing methodology. Bias is very critical in two competing manners. Bias activates moisture failure mechanisms with electric potentials and current flow (leakage), and bias also provides power dissipation which drives moisture from plastic encapsulated devices. The balance of humidity, temperature, and bias conditions can be tenuous for any particular failure mechanism. In some humidity testing specifications, the bias is confined by power dissipation limits or by the maximum permitted temperature rise. This leaves the scientist plenty of room for creativity. The intent of bias seems simple: (a) to create an electrical potential at nominal levels across as many nodes as possible within the integrated circuit, and (b) to avoid any thermal gradients within the device that would tend

10.9 Wear-out versus defects (acceleration versus real life)

489

Table 10.10 Environment temperature and humidity data [26] Nominal environment Temp.

Environment +30 ◦ C

Rel. Hum.

Temp.

Rel. Hum.

BATON ROUGE LA. Summer 4 months Max. temp. (day) 90 ◦ F (32 ◦ C) Min. temp. (night) 71 ◦ F (21 ◦ C)

65% 90%

62 ◦ C 51 ◦ C

12% 15%

Remainder of the year Max. temp. (day) Min. temp. (night)

80 ◦ F (26 ◦ C) 45 ◦ F (7 ◦ C)

60% 85%

51 ◦ C 37 ◦ C

10% 13%

ALLENTOWN, PA. Summer 4 months Max. temp (day) 80 ◦ F (26 ◦ C) Min. temp. (night) 60 ◦ F (16 ◦ C)

60% 85%

56 ◦ C 46 ◦ C

11% 14%

Remainder of the year Max. temp. (day) Min. temp. (night) Air conditioning

65% 77% 50%

35 ◦ C 25 ◦ C 55 ◦ C

10% 10% 9%

40 ◦ F (5 ◦ C) 23 ◦ F ( −5 ◦ C) 72 ◦ F (25 ◦ C)

to prevent moisture from penetrating the device to locations which may be susceptible to degradation mechanisms. Consider the tradeoffs between bias and humidity within an IC. Peck and Zierdt [26] gave us an insight into this in their original paper. Table 10.10 is an excerpt from their standard-setting work. The data in Table 10.10 indicates that a uniform 30 ◦ C temperature rise will decrease relative humidity 40–75%. For individual thermal gradients, the humidity reduction is on the order of at least 1.5%RH for each degree increase in temperature. If biasing is allowed to raise the case temperature – even by less than 10 ◦ C – then gradients within the package may be significantly larger and the resulting local decreases in humidity could clearly exceed 15%. Accounting for all the thermal gradients within an IC would be a very complex task. If the part is biased with no thermal rise, then gradients can be ignored. Thus, full bias is applied as normal, but the part is controlled into the off state so that only leakage current is flowing. Some devices can also be turned-off hard, i.e., a voltage is applied above nominal levels, yet the device is held in the off state. This bias configuration has been previously designated as high voltage zero power moisture (HVZPM) [27]. Most processes, lots, and samples investigated over the past 20 years are not susceptible to degradation in moist environments. Both 85/85 and HAST test conditions are normally incapable of causing degradation for standard durations (1000 h for 85◦ /85% and 96 h for HAST). Even when devices are subjected to double the normal durations, measurable degradation is very rare. Occasionally, special lots and/or specific designs are found to be more susceptible to degradation in moist conditions. In this study, several of these special samples were investigated. These samples include HBT and pHEMT technologies utilizing GaAs substrates. However, the compound semiconductor

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material is not what makes these lots special; it is the metallization and specific layout configurations that determine susceptibility for this investigation. There are three main categories of failure mechanisms that afflict semiconductors in humid conditions. The first failure mode category is shorts. The mechanism is electrolytic conduction between electrically biased metallization paths. This type of degradation was first reported as migrated gold resistive shorts (MGRS) [28] by Shumka and Piet. They claimed three ingredients are essential for MGRS: r reactive chemicals such as halogens; r a layer of water to form an electrolyte between neighboring metal lines; r a bias for the electrochemical reaction to take place. Furthermore, Shumka and Piet found that there was a minimum threshold of water required for the failure (1.5% water vapor by volume in a cavity package). In a plastic package, 1.5% water vapor would be slightly below 100% relative humidity (RH) at 25 ◦ C. In their study, they also saw that the onset of failures was very rapid. Some 60% of the failures occurred in less than 50 h at 25 ◦ C. The second failure mode category is open circuits. This type of degradation ranges from chemical reactions to simple loss of adhesion between layers [29]. The failure mechanism is typically corrosion of metallization involving ionic contamination, water, and bias. Historically, the common example is the attack of chlorine on aluminum in a wet environment. Moisture penetration between dielectric layers or at interfaces between metals, dielectrics, and semiconductors can result in adhesion loss, increasing resistance, and eventually, open circuits. While testing pHEMTs, Ersland et al. [29] reported electrical behavior corresponding to increasing current (the mode of shorts), but the visual result was loss of adhesion of the silicon nitride passivation layer (the mode of opens). The third failure mode category is threshold malfunction without cumulative degradation. This failure mechanism is caused by charge separation of mobile ions to form parasitic gates. This mechanism is identified with MOS devices. In the course of standard device qualification testing, a special lot utilizing a new device design was produced. This lot was special because there was fall-out during the biased HAST conditions of 130 ◦ C/85%RH and 96 h. In order to measure precise the time to failure, small samples of devices from this lot were subjected to 85% RH, a “turned-off” bias, and various temperatures. The electrical conditions were nominal bias on all pins, with the control pins turned-off (grounded). These bias conditions were achieved by soldering each sample device to a small circuit board. Each board was monitored at periodic intervals during the aging. The chamber used for this study had only eight electrical feed-throughs, so the sample size was limited to three. The electrical degradation of these special devices was a fairly abrupt reduction of current. Once the devices were removed from the bias boards, the reduction in current was more apparent. Failure analysis determined that delamination within the metal layers caused increasing resistance, and eventual open circuits. All of the degradation measured during this study was caused by the open circuit mechanism. The special sample devices were tested under HAST conditions with various temperatures between 85–140 ◦ C. All

10.9 Wear-out versus defects (acceleration versus real life)

491

Table 10.11 Results of 85% RH testing Temp. (◦ C)

ML (H)

AF (10 ◦ C)

AE (eV)

N

140 130 120

12 32 150

2.7 4.68

1.4 2.10

N

140 130 120

11 29 132

2.64 4.55

1.39 2.07

Y

140 130 120

11 50 231.5

4.55 4.63

2.07 2.09

Lot

P/C

A

B

of the tests were pressurized, and at 85% RH. The accelerating effect of temperature was measured over these conditions and then activation energy was calculated. A 5% reduction in bias current was used as the failure criterion. The devices were monitored on a frequent basis during the first test. Monitoring involved a manual switch of the device mode from a turned-off state (only leakage current and bias board current) to a turned-on state (device current and bias board current). The static current through the bias board was large compared to the sample off-state current (nA), but insignificant compared to the on-state current (mA). This manual measurement took about 5 s to stabilize, so the device was on for 6 or 7 s to make a measurement. In measuring the devices during the initial test, it was discovered that once the devices began to degrade, the degradation could be temporarily suspended by the process of turning the device on for 5 s. In general, the samples would degrade at 140 ◦ C in less than a day, at 130 ◦ C in a couple of days, and at 120 ◦ C within about a week. To reduce the counter-acting effects of turning on the devices, monitoring intervals were extended to 3 h. Typically, plastic encapsulated devices are subjected to environmental testing after a preparation sequence involving an initial electrical measurement, dry bake, specific moisturization, three repetitions of solder reflow simulations, and a final electrical measurement. This pretreatment is called preconditioning (P/C). The mosturization parameters are defined by the moisture sensitivity level (MSL) designation of the package. For this study, the moisturization was 168 h at 85 ◦ C/85%RH, otherwise known as the MSL1 pretreatment. Because of the speed of the monitored test, samples were initially aged without preconditioning. A complete set of results could be obtained over the duration of the preconditioning. For one of the lots, testing was performed both with and without preconditioning. The overall results of this study are shown in Table 10.11. The monitored testing utilizes very small sample sizes. However, the time to degradation was very similar for most of the population samples. Once the current started to decrease, the degradation was very rapid – occurring in less than a couple of hours. For special samples without preconditioning, the onset of degradation appears to be significantly shorter. Based upon all other nonpreconditioned tests, we expected degradation in less than 7 h at 140 ◦ C, but it always took 11 or 12 h. This could be

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Reliability

Table 10.12 Acceleration factors for HAST Vs 85/85

Source (mechanism)

AF (85–130)

AE

Hours Needed for 1000 h @ 85 ◦ C /85%

Old standard (lore) Si (Al corrosion)[29] pHEMT (short) [28] pHEMT (open)

10.42 16.25 471 1865

0.647 eV 0.77–0.81 eV 1.7 eV 2.08 eV

96 h 61.5 h 2.13 h 32 minutes

explained if moisture penetration takes approximately 6 h at 140 ◦ C. Assuming the onset time is insignificant for results at 130 ◦ C and 120 ◦ C, the unexpected results at 140 ◦ C could be explained if the preconditioning reduces the time for penetration but doubles the lifetime. Testing on compound semiconductors has produced 85/85 HAST activation energies from 2.07 eV to 2.10 eV for the circuit and mechanism described here. Previously reported results [29] indicated the activation energy for shorting-type mechanisms in compound semiconductors is 1.7 eV. Based upon the degradation data of these special lots, and taking into account both short and open failure mechanisms, a three hour HAST test could be equivalent to 1000 h 85/85 tests. This is considerably faster than 96 h which has been specified for silicon devices. Equivalencies are shown in Table 10.12. All of the historical humidity acceleration factors were based upon silicon device testing and a primary mechanism involves aluminum interconnects. Since most reliability requirements claim that 96 h of HAST (130 ◦ C/85%) is equivalent to 1000 h of 85◦ /85, the expected acceleration factor (AF) is 10.42 and the activation energy is 0.647 eV. Actual measured results for 14 silicon humidity tests [30] found the silicon/aluminum corrosion failure mechanism to have an activation energy between 0.77–0.81 eV. Two results were especially interesting. First of all, the onset time for device degradation was found to be very short. Under nonsaturated conditions, we were surprised to see that degradation began as quickly as 11 h. Absorption times have previously been generalized at 24 h. Second, we found that the effect of preconditioning the parts (drying, moisturization, and soldering simulation) tended to extend the onset of degradation. This finding is particularly good news since the preconditioning is thought to simulate conditions that devices would experience in actual use. These results indicate that 96 h of 130 ◦ C/85% RH HAST is a more than adequate replacement for 1000 h of 85◦ /85% RH. The data in Table 10.12 shows that thermal acceleration factors for two compound semiconductor failure mechanisms in HAST are much higher than those reported for silicon devices experiencing aluminum metal corrosion. A “standard” HAST test of 96 h is actually equivalent to 5–20 years (45,216– 179,040 h) at 85◦ /85% RH conditions.

10.10

Process effects and influence The semiconductor manufacturing process includes various steps, such as etching, dielectric deposition, photolithography, metal deposition, alloying, cleaning, drying,

10.10 Process effects and influence

493

Table 10.13 Photoresist process effects on reliability Process affecting reliability

Related item on device

Related factors

Failure mode

Resist application

Transistor, diode,resistance, metallization,shape and size, contact

Characteristic failure, pinholes, large leakage current

Mask alignment

Transistor, diode,resistance, metallization, shape and size, contact Transistor, diode, resistance, metallization, shape and size, contact Transistor, diode,resistance, metallization, shape and size, contact Transistor, diode,resistance, metallization, shape and size, contact

Improper film thickness, poor uniformity, dirt, foreign particles, residual photoresist Misalignment, dirt, foreign particle adhesion, flaws

Exposure

Development

Etching

Insufficient/Excessive exposure

Characteristic failure, pinholes, large leakage current Characteristic failure

Insufficient/Excessive Development

Characteristic failure

Insufficient/Excessive etching, etching temperature faulty, insufficient washing

Characteristic failure, characteristic fluctuation

plating, annealing, substrate thinning, testing, wafer sawing, and inspection. These steps include various heat treatments, chemical treatments, mechanical stresses and electrical stresses that are applied to the devices. These steps involve a great number of factors that affect reliability. Factors that degrade reliability include processing variances (dimensions, parametric values, etc.) that inevitably occur during product manufacturing, defects and damage that occur in the manufacturing process, handling errors due to human error, and equipment operation errors. The semiconductor manufacturing process is extremely complicated, requiring great precision. In addition, because product characteristics are extremely sensitive, it is essential to fully understand the factors that affect reliability and take corrective actions to prevent each factor from occurring. Table 10.13 shows the factors affecting reliability that are related to the photolithography step in the semiconductor manufacturing process. The manufacturing procedure repeats several processes to form the elements of the semiconductor product, such as the transistors, resistors and capacitors that are placed on the semiconductor substrate, and then interconnects these elements to form a single circuit. These processes are adversely affected by contaminants and therefore take place in clean-rooms. It is critical that the particles that originate from equipment and instruments as well as the dust level inside clean-rooms should be controlled at the submicron level. Such contaminants greatly affect reliability as discussed in Section 10.9.2. The factors that are related to the semiconductor substrate are the most fundamental to the product reliability. Factors such as crystal defects, resistivity dispersion, surface contamination and surface flaws directly affect product characteristics. The assembly process begins with dicing followed by die bonding, wire bonding and, finally, sealing. All these processes are particularly critical. Die bonding and wire

Reliability

Yield at Zero Age (% per cm)

494

Space Between Adjacent Metals (micron)

Figure 10.33 Measured quality levels for different spaced metallization measured at 1 V

(normalized to a periphery of 1 cm).

bonding are the processes used to secure the chip and bond the electrodes to the exterior. Since junctions are formed between different materials, changes in temperature and other physical forces (such as vibration, shock, and acceleration) can result in die cracks or open faults, either of which can be fatal to the product. In the case of encapsulation, impurities in the sealing resin (such as sodium, potassium, or chlorine), moisture absorption, thermal expansion and mold shrinkage are critical. These can result in failures such as corrosion, characteristic failure, bonding wire breakage and die cracks. In the case of hermetic sealing, critical points include the moisture content and other impurities in the sealing gas, and the presence of conductive foreign matter. These can adhere to the chip surface and cause failures such as increased leakage current or faulty operation. Process aspects relate directly to reliability in terms of layout configurations. Using additional work from defect studies in Section 10.9.2, we can investigate the impact of metallization capability on reliability. We have seen that special test structures can help us bridge the gap between process manufacturability and defects. And we have seen that the K factor shows relationships between quality and reliability – particularly for defects. If we extend the findings from Figure 10.30 into the realm of quality, the relationship between process capability (in terms of spacing between patterned metal lines) and quality (in terms of yield measured at 1 V) will be defined by the curve in Figure 10.33. Figure 10.33 shows that a spacing below 0.7 μm would have very poor quality for adjacent metals sharing a 1 cm periphery. Spacings above 1.4 μm are likely to have very good quality. In this particular case, the quality is expected to be very good since the layout rules were set at 2 μm. However, knowing the acceleration effect of voltage (from Figure 10.31), we can make additional predictions on the effects of process capability on the number of defects and this is shown in Figure 10.34.

495

Fallout per Applied Volt (ppm.cm)

10.11 Design for reliability

Space Between Adjacent Metals (microns)

Figure 10.34 Predicted number of defects in ppm/cm V.

As line spacing changes then the number of defects changes at a rate of over 300 times per micron! Not only does this give process engineers an important yardstick, it shows designers the leverage of additional spacing on their layout.

10.11

Design for reliability Design for reliability is supported by a number of reliability tasks. Some of the pro-active techniques which have proven to be successful include: r environmental characterization (tailoring of design requirements to expected operating conditions); r parts selection and control (includes parts, components, assemblies and software); r parts application (i.e., derating, thermal and mechanical design management), thermal and mechanical analysis (reducing failure accelerating temperature/vibration conditions); r critical item identification and control (risk reduction); r modeling and simulation (design tradeoff techniques). It is important to emphasize, however, that designing for reliability should address not only the product, but also the processes used to develop and manufacture the product. Inadequate or deficient manufacturing processes, for example, may introduce defects that can lead to failures after delivery to the customer. The same is true for quality processes. In designing the processes that will be used to manufacture the product, consideration should be given to the defects that may result and the potential ways to eliminate them. Similarly, how the product will be operated and repaired is a major consideration in the design process.

496

Reliability

A reliability model, often in the form of a block diagram, is also recommended to improve the design process. Such a diagram can be used to identify reliability goals and determine if additional analyses will need to be performed. The model shows the functional relationships between components and assemblies within the product. The model is iterative in nature, and its validity can be assessed through a variety of simulation techniques. Comparison of the model to product reliability goals provides focus to potential design improvements. Reliability analysis techniques can serve a useful purpose beyond the simple assessment of progress in the design of the product. Analyses can also be effectively applied as a means of trading off design options and characterizing the impact of design decisions. Used in this manner, the supplier can have greater confidence in manufacturing a product that will operate failure-free and be tolerant of faults to the extent that the basic reliability objective can be achieved within the required business constraints. Verification and qualification testing also plays an important role in the design process. While often viewed as a “reactive” means of measuring reliability, certain types of testing may also be vital to successful product design. Incremental testing of critical parts, assemblies and functional performance of the design may be beneficial to understanding and making decisions about the product and process design. Design of experiments is an effective test process for optimizing product or process design characteristics in a cost effective manner. The use of test data for design improvement can be extended to more formalized test-analyze-and-fix or reliability growth test methodology. Reliability testing can prove useful in identifying necessary design changes in products that have a high degree of functional and/or physical complexity. Fabrication, application, and design are three major factors controlling the ultimate reliability of integrated circuits. Manufacturing processes must be capable of demonstrating inherent reliability regardless of device function or complexity. This aspect is handled by maintaining a controlled process which has been developed with reliability as an integral goal. Another key aspect of circuit reliability is the application or insertion of devices, with correct handling and assembly procedures, into an adequate environment for their intended use. This is the area that is least controllable by the semiconductor foundry, and is also usually somewhat removed from the design. Unfortunately, because of this detachment, many of the early users of RF and microwave power amplifiers had difficulties with application problems such as electrostatic discharge, improper heat-sinking, and poor impedance matching. Lastly, some aspects of reliability are controlled by the design of the circuits, since even the best processing can yield devices which fail prematurely in their intended applications. These “design-controlled” aspects are the major emphasis of this discussion on designing for reliability. In any technology, or at any foundry, the designer is given some guidelines or boundaries to increase the probability of successful designs. Most of the focus of these guidelines is on performance and functionality. However, some of the guidelines are imposed to improve the probability of quality and reliability as well. Both electrical ratings and layout definitions are key guidelines for reliability. Regardless of the technology, the

10.11 Design for reliability

497

Table 10.14 Example of maximum ratings (beyond which the useful life of the product may be impaired). Parameter

Limit

Storage temperature range Assembly temperature exposure

−65 ◦ C to +150 ◦ C +300 ◦ C, 5 minutes

FET and N− diode maximum ratings Channel temperature Drain-to-source voltage Gate-to-source voltage Gate-to-drain voltage Forward gate current Channel current (N−)

Tch = −55 ◦ C to +150 ◦ C 7.5 V (desired) 7.5 V (desired) 7.5 V (desired) 0.2 mA/μm of gate width 0.15 mA/μm of channel

Overlap or N+ diode maximum ratings Reverse voltage Forward current

0.2 V 0.2 mA/μm of diode width

Passive device maximum ratings Sputtered/evaporated metal current density Plated metal current density Nichrome resistor current density Gate metal current density Ohmic metal current density MIM capacitor voltage

2 mA/μm width 5 mA/μm width 1 mA/μm width 2 mA/μm width 2 mA/μm width 15 V

maximum electrical ratings must be maintained. Likewise, limitations on feature sizing, spacing, overlaps, exclusion boundaries and inclusion requirements are important. A thorough review of the ratings prior to design is strongly suggested. Table 10.14 shows some examples of electrical and thermal ratings. Transistor reliability guidelines. It is very important that the hottest transistor temperature does not exceed the maximum temperature rating. Furthermore, designing a circuit so that the transistors operate cooler will result in additional reliability and lower failure rates. For example, reducing a transistor channel temperature from 150 ◦ C to 100 ◦ C will improve its reliability by a factor of 9800 for a FET (assuming an activation energy of 2.5 eV). The projected median life values of FETs are (based on data from 300 μm interdigitated FET life-tests) are shown in Table 10.15. Other reliability guideline examples for transistors are: 1. Limit the power dissipation, so that the typical worst case transistor temperature is <125 ◦ C, and that the absolute worst case transistor temperature is less than 150 ◦ C. Note that in calculating channel temperatures, ambient temperature, package thermal resistance, and die attach must be taken into account. 2. Be sure that none of the current density maximum ratings for connecting metal and transistor contacts is exceeded. Also note that the maximum forward gate current in a FET transistor is limited by two factors: (a) the current carrying capacity of the gate metal cross-section; (b) the current carrying capacity of the semiconductor contact.

498

Reliability

Table 10.15 Temperature acceleration effects on FET lifetimes

Temperature

Determination

Lifetimes (hours)

Lifetimes (years)

310 ◦ C 290 ◦ C 275 ◦ C 260 ◦ C 245 ◦ C 150 ◦ C 125 ◦ C 100 ◦ C

measured measured measured measured measured projected projected projected

7.4 50.4 220 838 4770 10 × 109 7.4 × 1011 9.9 × 1013

negligible 1/200 1/40 1/10 1/2 1 million 84 million 11 billion

3. Do not exceed the maximum voltage ratings for any transistor. Exceeding the maximum voltage ratings may result in catastrophic failure. Also note that transistor breakdown voltages may decrease at high temperatures. Thin-film resistor reliability guidelines. Thin-film resistors such as nichrome may be the metals under the highest electrical stress in any technology or process. Do not exceed the maximum rated current density. Additionally, the resistor should never exceed 150 ◦ C. Check for any derating suggestions on temperature or current density. Exceeding the current density or the maximum temperature will accelerate the resistance value drift and may result in catastrophic failure. Note that the use of subsquare resistors is not recommended because of current crowding possibilities. Interconnect metal reliability guidelines. This section applies to the all interconnect metals and to transistor contact metals. Do not exceed the maximum current density ratings for these metals, not even on a transient basis. When current is passed through a conductor, the interaction of the electrons with the lattice produces a thermal energy equal to the product of the square of the current and the resistance. This is called Joule heating. Metal lines will heat up whenever current is passed through them. If the current is low, the heat is effectively conducted away, but there must be some temperature increase even if it is not detectable. When current densities approach 106 A/cm2 , Joule heating can produce enough energy to make the conductor lines heat up appreciably. Designers must realize that Joule heating is caused by root mean square (rms) current and not by the average current, as is electromigration. For a narrow pulse, the rms current can be much higher than the average current. The average current can be well within any guidelines that may be set for electromigration considerations, yet significant Joule heating can result. This can be more prevalent on upper level metallization, where heat must be conducted through several layers of interlevel dielectric, which is a poor thermal conductor. The problem with Joule heating is not the modest temperature increase, but the temperature gradients that result. Typically, at the current densities found in modern circuitry, temperature increases would range between a few and a few tens of ◦ C. This produces temperature profiles that decay within a few microns, so that temperature

10.11 Design for reliability

499

Figure 10.35 Rudimentary ESD input protection circuit.

gradients of 104 to 105 ◦ C/cm will be found. The temperature gradients produce flux divergences which tend to accelerate electromigration effects. RMS current density must then be limited below 106 A/cm2 because reliability of metal lines in the presence of temperature gradients cannot be accurately estimated. Temperature gradients can vary tremendously throughout a real structure, depending on subtleties of the geometry and on the use of the underlying semiconductor devices. The only way to deal with these issues is to take a conservative approach and forbid temperature gradients by limiting the rms current density to the levels suggested above. MIM capacitor reliability guidelines. Do not exceed the maximum voltage rating when using MIM capacitors. Also note that the layout rules defining the capacitor metals should be optimized to reduce defects and potential high field points around the edges. Also check to make sure that interconnects to capacitors are capable of handling the expected AC or RF current levels through the capacitor. Diode reliability guidelines. Do not exceed the maximum breakdown voltage. Do not exceed the forward current rating. Use the transistor-related maximum ratings for most styles of diode. ESD guidelines. ESD damage thresholds should be characterized using a simulator. Relative sensitivity should be known for each of the various circuit elements. It is recommended that designers plan to include ESD protection from the beginning, rather than attempting to “beef up” prototypes that are found to be weak. Typical shunt and blocking elements are available on all processes. In some processes, special ESD structures may be offered. The designer should plan to employ protection (see Figure 10.35) on every external pathway of his device. For circuits that cannot be protected in this manner, a special ESD sensitivity warning should be specified and included in device labeling. Use of all possible ESD countermeasures are encouraged when handling the fabricated devices, including wrist straps, floor mats, conductive floor and table mats, and conductive packaging materials. Optimizing for and ensuring reliability. The challenge to IC designers is to ensure reliability while squeezing as much performance out of the process as possible. Unfortunately, the requirements for these two goals are often conflicting. Higher performance means higher stresses within smaller structures, whereas reliability demands lower stress. Table 10.16 shows examples of mitigating factors for compound semiconductor failure mechanisms.

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Reliability

Table 10.16 Example failure mechanisms and acceleration factors in GaAs processes

Failure mechanisms FET gate metal “sinking” FET “burnout”

Metal interconnect interdiffusion

Current density Thermal exponent activation energy

Detection/ acceleration

Recommended prevention

N/A

2.44 eV–2.77 eV

High temperature

Do not exceed 150 ◦ C.

N/A

N/A

Overstress conditions

n = −1.5

2.2–2.5 eV

High temperature High current density

0.4 eV

High current density High temperature High temperature High current density High temperature High current density High voltage

Watch ESD/EOS obey current density rules Watch breakdown voltages Temperature management Current density rules Current density rules Layout rules Do not exceed 150 ◦ C Current density rules Do not exceed 150 ◦ C Current density rules Do not exceed 15 Volts Do not exceed 1 V/μm Do not exceed 150 ◦ C

Gold electromigration n = −3 to −5 Thin-film resistor interdiffusion Ohmic contact interdiffusion MIM capacitor breakdown PIN Diode, substrate conduction

n = −3

1.0 eV

n = −3.5

N/A

N/A

Low

N/A

N/A

High voltage High temperature

A conservative approach has been to generate design rules based on worst case scenarios. In this strategy, guidelines limit conditions to a certain value assuming that all the elements on the circuit are to be used at this high rating. The limiting values can be determined from extrapolating the failure times, usually fitted to a lognormal failure distribution, to some required level of reliability based on the chip complexity. This approach can be supplemented by a strategy known as “Reliability Budgeting.” As an example of budgeting for electromigration, all one needs to do is calculate how much power is dissipated by a chip running with every wire at the electromigration limit. It is often kilowatts. To perform reliability budgeting, we need to know how much current is going through each element. In today’s complex microcircuits, this is a daunting task, but the payback is significant. The allowable current density for critical circuit paths can be increased substantially while maintaining reliability, since the majority of circuit elements have little to no current flowing though them and are thus effectively immortal. If trouble spots can be eliminated then a more reliable circuit can be designed. The easiest thing a designer can do to increase reliability in his design is to set his default metal widths at some value above the minimum size geometries. In this manner, the designer must make a conscious choice to use the least reliable circuit features, instead of always having them at his fingertips.

10.12 Historical trends and technology comparisons

10.12

501

Historical trends and technology comparisons Occasionally, considerations of reliability are discussed when making technology choices. However, reliability dynamically improves as a function of maturity rather than because of an inherent property of silicon or compound semiconductor technologies. For the most part, there are very few applications where performance and cost attributes overlap between competing technologies for RF and power amplifier products. More often than not, if products can be developed using competing technologies that both meet the performance requirements, say for example gain-bandwidth, then the choice can easily be decided by a prioritization of additional performance parameters, such as noise or efficiency. Should all the attributes be in equilibrium through all aspects of performance, then price, delivery, quality, or familiarity will delineate a clear choice. For those situations where reliability might be considered as a critical aspect, then a direct comparison of lifetimes or failure rates is desired – at the equivalent operating conditions. However, few projects have the resources or the time to design, fabricate, stress, and analyze competing devices in parallel. However, this points out the difficulty in making a comparison any other way. Basing a reliability decision on arbitrary conditions of different applications is problematic. All reliability results are specific to the particular conditions, packages, environments, of a particular application. However, the variation or reliability across the application space is overshadowed by the variation of reliability that spans the technology maturation. In other words, a mature technology will most likely outperform a burgeoning technology – regardless of the operating conditions. The maturation of semiconductor reliability follows a process of experience. This learning cycle has been studied and discussed at length in the reliability community [31]. In general, the cycle follows a series of eras, which is repeated for each technology generation. The first era of reliability improvement is a focus on materials, specifically, the semiconductor, metallization, and dielectric. Once the material set is determined, then work begins on the second era, which is major reliability problems. This is basically a hard look at expected issues and experiences from the previous generation. The third era, which is reliability physics, is to gain an understanding of the failure mechanisms well enough to develop models. The fourth era is focused on prediction and prevention, where reliability engineering efforts such as design-in reliability and wafer level reliability efforts are applied. The fifth and final era is to reduce defects, add statistical control countermeasures, and detect mavericks. The eras start over with the introduction of new generations which have new material sets. In general, reliability improves by progress through these five eras of reliability science. The amount of improvement per era depends on the reliability limitations of any particular generation. While some aspects may solve certain problems, they may generate different problems in other eras. For silicon-based technologies, progress from generation to generation is driven by Moore’s Law. For compound semiconductors the progress is driven by materials. Table 10.17 shows these differences between silicon and compound semiconductor technologies. Technology comparisons over time. The generation-to-generation and era-to-era improvements in reliability and quality have been demonstrated over and over in the

502

Reliability

Table 10.17 Technology comparisons

Si C.S.

Performance

Reliability

Yield focus

Shrink physical size New materials

New materials Don’t shrink (good enough)

Defects Parametric

Figure 10.36 Summary of published reliability results for the past 30 years. New technologies will

typical report lower expected lifetimes, but improve with maturity.

history of reported results. Figure 10.36 shows this for compound semiconductor technologies. As technology improvements occurred for MESFETs, then HBTs, and currently GaN, each one of these cycles began with relatively low reliability, followed by improvements in the reported lifetimes. For specific cycles of cellular phone power amplifiers, the same improvement cycles were experienced. Figure 10.37 shows that subsequent generations learn from previous generations, and the cycle time for improvement can be accelerated. However, when the technology changes significantly, the cycle time can be extended. These cycles of learning are similar regardless of the technology. Figure 10.38 shows that even major mainstream silicon suppliers experience quality improvement cycles with each new step along the path of miniaturization. The previous three graphs all show that maturity gained within each generation has an impact on quality and reliability levels. However, the absolute level of reliability meets the requirements for use for each application.

10.13

Summary The highest performing power amplifiers are invariably constructed using some of the most advanced semiconductor processes. Semiconductor reliability issues have been

10.13 Summary

503

Die Yield

Figure 10.37 Example of reduction in fallout during RF product development.

Month (period of initial development)

Figure 10.38 Example of quality improvement during progress of shrinking node sizes.

around since the beginning of solid state technology and most of the problems are common regardless of the technology. Although it has a certain allure, new technology has unfortunately carried a suspicion of reliability risk. This chapter has discussed the basics of reliability and touched on some of the unique aspects of power amplifiers and the technologies that have been developed for radio frequency amplifiers over the past 20 years. The basics start off with vocabulary on units of reliability, roles of reliability in product development, and goals of reliability in end applications. Various failure mechanisms were described along with the three keys to reliability prediction:

504

Reliability

r knowledge of the root cause of failure mechanisms; r measurement of degradation distributions; r characterization of acceleration factors. Measurements in these three key areas were mentioned – with emphasis on reliability methodology, and results given for several specific examples. Product, technology, and package mechanisms have been considered. The importance of using the right acceleration was presented. If we are to make predictions about reliability, we must be able to accelerate the failure mechanisms without generating new issues brought on by the aging itself. Thermal acceleration is easy, but that doesn’t make it the right thing to do in all cases. An understanding of mechanisms and degradation distributions can help us to look where acceleration might be less understood. To help, we need to talk more with customers who use power amplifiers. Their use of the devices can give clues as to what types of acceleration are most applicable. For example, thermal excursions, voltage, current density, and humidity might be preferable to high-temperature acceleration. With few exceptions, the reliability investigations on power amplifier circuits over the past two decades have evolved to rely on thermally accelerated wearout failure mechanisms. Regardless of the measured lifetimes, there have been few wearout failures reported during use of the circuits. Instead, customers do report measurable defect rates and early life failures that often match-up with yield fallout failure mechanisms. This discussion has involved various mechanisms, while focusing on yield and reliability relationships which are intertwined with early lifetimes of products. There are a few obvious improvement strategies available to semiconductor reliability engineers. Some tactics are similar to those used by mainstream silicon engineers, and some are unique to the special power amplifier technologies. As the overall reliability improves, degradation becomes elusive. An example of an alternate method to predict failure rates is the consideration of yield correlations to reliability. If yield fallout also disappears with maturity, we can use new tricks such as physical amplification of defects in order to extend our predictive capability. Recent breakthroughs with innovative tests such as power cycling, high-voltage ramping, and RF biased lifetesting, are the kind of tactics that can put power amplifier reliability understandings ahead of the learning curve of our larger mainstream solid state relatives. We’ve touted the technology differences as defense for the power amplifier product niche; why not use the reliability differences as well? Because of the unique mechanisms and absence of the silicon scaling problems, power amplifiers have an opportunity to demonstrate exceptional reliability in the future.

Appendix 10.1 Brief discussion on burn-in Early or infant failures refer to systems which fail long before normal wear-out would be expected. Early failures are attributed to devices or assemblies with manufacturing

References

505

defects or problems. Consumers have been historically protected from these early failures by a warranty. If the early failure rate exceeds an acceptable level, then some form of infant mortality “control” may be needed. For electronics, this control is achieved by accelerating the population through the early failure rate region. This type of infant mortality failure rate reduction is called “burn-in.” For the first three decades of the electronic age, early failures were screened by the practice of burn-in, where devices or systems are turned-on for a short period of time before being delivered to customers. Occurrences of early failures decrease significantly as devices age, so burn-in was effective in preventing warranty failures. Over the years, burn-in was optimized by elevating the temperature. This thermal acceleration caused early failures to occur faster, and allowed manufacturers to ship products sooner. Over recent decades, semiconductor manufacturers have discovered that eliminating manufacturing flaws during fabrication is a more cost-effective method of reducing early failures than screening individual devices with burn-in. Although electronic assemblies and subsystems still routinely receive burn-in, integrated circuit burn-in is often phased-out during the early technology development. Mature amplifier production lines ordinarily do not experience significant infant failures. Early failure occurrences on mature technologies have been at an extremely low level. Aside from difficulties in repeatedly measuring devices operating at GHz frequencies, less than one amplifier per 10,000 has been found to be screenable by burn-in. Similarly, data from hundreds of different life-tests running in excess of millions of device hours show no indication of infant failure mechanisms. These infant mechanisms are expected to be eliminated by continuous improvement activities throughout the process flow used to construct amplifiers. For example, several processing steps are conducted at temperatures high enough to accelerate most early failure mechanisms to failure. So, many mechanisms are inherently screened by the fabrication and assembly processes used to construct amplifiers. Additional screens are often applied to amplifiers during final product tests. Biasing may be applied to products beyond the defined conditions that are used to validate compliance to the specified operating parameters of the device. For example, severe reverse bias leakage tests, extreme power-on shock tests, acute voltage supply bias, and high input RF drive tests may be included within the suite of verification tests applied to all circuits. For many early failure mechanisms, biased screening is much more effective than thermal burn-in.

References 1. W. J. Roesch and D. Stunkard, “Proving GaAs Reliability With IC Element Testing,” U.S. Conference on GaAs MANufacturing TECHnology, Nashville Tennessee, pp. 90–95, Nov. 1988. 2. D. Cerovecki and K. Malaric, “Microwave amplifier figure of merit measurement,” Measurement Sci. Rev., vol. 8, section 3, no. 4, pp. 104–107, 2008.

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3. Measurement Systems Analysis Manual (MSA), Automotive Industry Action Group (AIAG). See Gage Repeatability and Reproducibility source and description [Online]. Available at www.AIAG.org 4. W. J. Roesch, A. L. Rubalcava, and, R. A. Winters, “GaAs IC reliability returns: a story of abuse,” GaAs Reliability Workshop, Miami Beach Florida, pp. 30–34, Oct. 1992. 5. W. J. Roesch, “Reliability basics,” GaAs MANufacturing TECHnology Conference Workshop, Vancouver British Columbia Canada, pp.1–60 Part #3 Workshop Notes, April 1999. 6. A. Black, Jr., Electromigration – a brief survey and some recent results.” IEEE Transaction on Electron Devices, vol. 16, Issue 4, pp. 338–347, April 1969. 7. T. Henderson, “Physics of degradation in GaAs-based heterojunction bipolar transistors,”10th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis – ESREF,” Arcachon, France, pp. 1033–1042, Oct. 1999. 8. H. C. Cramer, J. D. Oliver, and R. J. Porter, “Lifetime of SiN capacitors determined from ramped voltage and constant voltage testing,” International Compound Semiconductor MANufacturing TECHnology Conference, Vancouver British Columbia Canada, pp. 91–94. April 2006. 9. M. J. Brophy, A. Torrejon, S. Petersen, K. Avala, and, L. Liu, “MIM’s the word – capacitors for fun and profit,” International Compound Semiconductor MANufacturing TECHnology Conference, Scottsdale AZ, pp. 57–59, April 2003. 10. J. Beall, K. Decker, K. Salzman, and G. Drandova, “Silicon nitride MIM capacitor reliability for multiple dielectric thicknesses,” GaAs MANufacturing TECHnology Conference, San Diego, CA pp. 145–149, April 2002. 11. R. Coffie, Y. Chen, I. P. Smorchkova, B. Heying, V. Gambin, W. Sutton, Y.-C. Chou, W.-B. Luo, M. Wojtowicz, and A. Oki, “Temperature and voltage dependent RF degradation study in AlGaN/GaN HEMTs” IEEE International Reliability Physics Symposium, Phoenix, AZ, pp. 568–569, April 2007. 12. M. Ruberto, O. Degani, S. Wail, A. Tendler, A. Fridman, and G. Goltman. Intel Corporation, “A reliability-aware RF power amplifier design for CMOS radio chip integration,” IEEE International Reliability Physics Symposium, Phoenix, AZ, pp. 536–540. April 2008, 13. J. Scarpulla, E. Ahlers, D. Eng, D. Leung, S. Olsen, and C. Wu, “Dielectric breakdown, defects, and reliability in SiN MIMCAPs,” GaAs Reliability Workshop, Atlanta, GA, pp. 92–105, Nov. 1998. 14. H. Cramer, J. Oliver, and G. Dix, “MMIC capacitor dielectric reliability,” GaAs Reliability Workshop, Atlanta, GA, pp.46–51, Nov. 1998. 15. B. Yeats, “Assessing the reliability of silicon nitride capacitors in a GaAs IC process,” IEEE Transactions Electron Devices, vol. 45, no.4, pp. 939–946, April 1998. 16. W. J. Roesch, “Thermal excursion accelerating factors,” GaAs Reliability Workshop, Monterey, CA, pp. 119–126, Oct. 1999. 17. C. H. Stapper, “Modeling of integrated circuit defect sensitivities,” IBM J. Res. Develop., vol. 27, pp. 549–557, Nov. 1983. 18. C. H. Stapper, F. M. Armstrong, and K. Saji, “Integrated circuit yield statistics,” Proc. IEEE, vol. 71, no. 4, pp. 453–470, April 1983. 19. C. G. Shirley, “A defect model of reliability,” IEEE International Reliability Physics Symposium, Tutorial #3, Las Vegas, NV, pp. 3.1–3.56, April 1995. 20. K. R. Forbes and P. Schani , “Characterization of the time-dependent reliability as a function of yield for a 130 nm SRAM device and application to optimize production burn-in,” IEEE International Reliability Physics Symposium, Phoenix, AZ, pp. 165–170, April 2004.

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21. J. A. Van Der Pol, E. R. Ooms, T. Van ’t Hof, and F. G. Kuper, “Impact of screening latent defects at electrical test on the yield-reliability relation and application to burn-in elimination,” IEEE International Reliability Physics Symposium, Reno, NV, pp. 370–377, March 1998. 22. J. Scarpulla, K. Kho, and S. Olsen, “Process monitoring for nitride dielectric defect density,” International GaAs MANufacturing TECHnology Conference, Vancouver British Columbia Canada, pp. 231–234, May 1999. 23. JEDEC Standard 35, “Procedure for the wafer-level testing of thin dielectrics,” (Figure A.1), April 2001. 24. I. C. Chen, S. Holland, and C. Hu, “A quantitative physical model for time-dependent breakdown in SiO2,” IEEE International Reliability Physics Symposium Orlando, FL, pp. 24–31, March 1985. 25. W. J. Roesch, R. Winters, A. L Rubalcava, and, B. Ingle, “Humidity resistance of GaAs ICs,” IEEE GaAs IC Symposium, Philadelphia PA, pp. 251–254, Oct. 1994. 26. D. S. Peck and C. H. Zierdt, “Temperature-humidity acceleration of metal-electrolysis failure in semiconductor devices,” IEEE International Reliability Physics Symposium, Las Vegas, NV, pp. 146–152, April 1973. 27. W. J. Roesch, S. Peterson, A. Poe, S. Brockett, S. Mahon, and J. Bruckner “Assessing circuit hermeticity by electrolysis,” International GaAs MANufacturing TECHnology Conference, Washington DC, pp. 121–124, May 2000. 28. A. Shumka and R. R. Piet, “Migrated gold resistive shorts in microcircuits,” IEEE International Reliability Physics Symposium, Las Vegas, NV, pp. 93–98, April 1975. 29. P. Ersland, H. Jen, and X. Yang, “Lifetime acceleration model for HAST tests of a pHEMT process,” GaAs Reliability Workshop – called the ROCS Workshop after 2003. San Diego, CA, pp. 3–6, Nov. 2003. (particularly Figure 3.) 30. D. S. Peck, “Comprehensive model for humidity testing correlation,” IEEE International Reliability Physics Symposium, Anaheim, CA, pp. 44–50, April 1986. 31. H. Stork, “Reliability challenges for sub-100 nm system on chip technologies,” IEEE International Reliability Physics Symposium, Phoenix, AZ pp. 1 (Keynote Address), April 2004.

11

Power amplifier applications ¨ Mustafa Akkul and Wolfgang Bosch ASELSAN A.S. and Graz University of Technology

11.1

Introduction Power amplifiers (PAs) are usually the last active component in the RF chain in modern radar and telecommunication equipment. Their nonlinear behavior has a significant impact on the overall system performance and quite often is the most limiting factor in modern radio systems. The purpose of a power amplifier is mainly to boost the radio signal to sufficient power levels suitable for a wired or wireless transmission from the transmitter to the receiver. Typically, they work at relatively high power levels and hence are a major power consumer in the overall transmitter system. However, their conversion efficiency from DC supply power to RF output power is traditionally very poor. Further, it is strongly dependent on the RF signal drive level and highest when the amplifier is operated in its most nonlinear region and the output RF power compressed or even saturated. Efficiency and linearity are severely contradicting power amplifier requirements and the most important parameters to be traded off. One of the biggest selling factors for mobile handsets is ‘talk time.” For other battery operated systems such as wireless sensor networks or even satellites the ‘time in operation’ is commercially a highly valued asset. For fixed wireless transmitter systems (e.g., base stations) the running cost and the electricity bill are commercially most relevant, they translate directly into carbon footprint and related CO2 emission. Most military platforms that are capable of carrying a modern radar system are limited in space, energy and cooling capability, hence the efficiency of the radar transmit power amplifier mostly determines the performance and size of the radar equipment that can be implemented on a given platform. The overall efficiency of a power amplifier subsystem is highly commercially relevant and detailed system requirements and tradeoffs need to be well understood when deciding on a power amplifier architecture. Major trends in power amplifier requirements can readily be observed when looking at the developments of the mobile telecom industry in the last twenty years. The first analogue cellular systems, such as the total access communication system (TACS) used an analogue frequency modulation scheme, which allowed the adoption of highly nonlinear PAs because of the constant or near-constant envelope of the RF signal modulation. However, even with the second generation of the European mobile telecom system global system for mobile communications (GSM) that still uses an almost constant envelope modulation, more stringent linearity requirements for the PA were put in place to counteract transmission phase errors, spectral re-growth and signal interference due to fast

11.2 System design parameter tradeoffs

509

power ramping. The introduction of more complex modulation schemes in 2.5G systems such as enhanced data rates for global evolution (EDGE) that uses the existing GSM spectra requires even higher power amplifier linearity resulting in a reduction in power amplifier efficiency. With the introduction of multipath resistant orthogonalf-frequencydivision-multiplexing (OFDM) multicarrier schemes and wideband code-division multiple access (WCDMA) systems the overall linearity requirements in 3G communication systems become overriding and very stringent, and therefore system power conversion efficiencies are frequently in the single digit region. The trend in the next generation 4G systems is towards even higher data throughputs, more efficient use of the spectrum, and higher robustness (e.g., utilization of MIMO technology), all requiring very linear amplifiers over a wide dynamic range. It is evident that for today’s 3G and future 4G communication systems a simple power amplifier design will not be sufficient to meet the linearity and efficiency requirements, hence more sophisticated power amplifier design techniques to either boost efficiency or to enhance the overall linearity have to be implemented. A very good understanding of the power amplifier design parameters and their impact at system level is crucial for overall product design success. The following sections will discuss some common system level parameter tradeoffs, highlight the most promising linearization and signal combining techniques, and will provide selected examples from commercial and military applications.

11.2

System design parameter tradeoffs

11.2.1

Output power–efficiency tradeoff The output power of a power amplifier is defined as the RF power that is delivered to the load. For maximum power delivery the load is typically conjugate matched to the output impedance of the amplifier and hence resistive only. The time average of the instantaneous output power is the average output power.  1 T /2 v (t) · i (t) dt. (11.1) Pout = T −T \2 In most cases only the output power at the fundamental frequency is of relevance, and in case of CW operation and a resistive load R the fundamental average output power simplifies to V02 (11.2) 2R where V0 is the amplitude of the sinusoidal output signal. The power conversion efficiency of power amplifiers is a key performance parameter and in the simplest form measured at a single frequency under CW operation. For a single gain stage the drain efficiency (or collector efficiency) is defined as: Pout =

Efficiency = η D =

Pout PDC

(11.3)

510

Power amplifier applications

The PAE is given by: Pout − Pin PDC

PAE =

(11.4)

where Pout and Pin are the RF power measured at the fundamental in CW operation. Typically, the maximum efficiency will be reached at maximum output power and will then drop with reduced drive signal. For Class A amplifiers in the ideal case it can be shown that the maximum efficiency is 50%. η D class A =

Pout V2 1 = 02 ≤ PDC 2 2 VD

(11.5)

where VD is the supply voltage. Hence, when reducing the input RF power in linear operation the output power will be reduced accordingly and the efficiency will drop with a linear dependence on the output power or the square of the envelope voltage as shown in Figure 11.1. For a Class B amplifier the efficiency in CW operation can be expressed by η D class B =

Pout π V0 π = ≤ PDC 4VD 4

(11.6)

Here the efficiency rises linearly with the voltage of the output signal and hence has a square root relationship to the output power. The instantaneous efficiency is defined as the efficiency at a specific output power level (typically measured at a specific CW frequency). For most amplifiers the maximum efficiency is reached at maximum output power and is a very useful and easy to measure benchmark when designing amplifiers. However, in typical communication systems, even with constant amplitude modulation schemes, the drive level may change significantly over time and the average efficiency is more of a concern and the determining factor for the overall system design. The average efficiency is defined as the time average of Pout (t) divided by the average input power Pin (t) [1]. η Davg =

Pout avg . PDC avg

(11.7)

For modulated band-pass signals the amplitude of the CW carrier frequency V0 can be expressed as the time varying envelope function A(t). The output power and DC power can then be expressed as function of the signal envelope A(t). The probability density function (PDF) of the envelope A(t) describes the relative amount of time the signal spends at a given amplitude. For uncorrelated multiple carrier signals, and also for random Gaussian processes, the envelope is Rayleigh distributed. p(A) =

A2 A · e 2σ 2 2 σ

and the average efficiency is then calculated as  A max ηD avg = η D ( A) · p(A) · d A · o

(11.8)

(11.9)

511

11.2 System design parameter tradeoffs

0.5

3.5 3

pdf(envelope)

efficiency

0.4 0.3 0.2 0.1 0 0

2.5 2 1.5 1 0.5

0.2

0.4 0.6 envelope

0.8

1

0 0

0.2

0.4 0.6 envelope

0.8

1

pdf of the efficiency

0.2 0.15 overall efficiency:4.0% 0.1 0.05 0 0

0.2

0.4 0.6 envelope

0.8

1

Figure 11.1 Average efficiency of a Class A power amplifier with a Raleigh distributed output

signal [3].

Figure 11.1 shows a visual example to calculate the average efficiency for the Class A amplifier under multicarrier operation. Assuming a peak to average ratio of 1:10 the average efficiency drops to only 4% from a peak efficiency of 50%. In case of the Class B amplifier with a maximum efficiency of 78% the average efficiency drops to 28% [2]. The peak efficiency and the dynamic relationship between efficiency and output power of an amplifier in conjunction with the PDF of the envelope strongly determine the overall efficiency performance of the PA system. Therefore, the initial power amplifier design aims to achieve the best peak efficiency for the required linearity. Typically, at a higher design level the amplifier is then put into a linearization system that enhances the linearity for a given efficiency and output power, or it is assembled into a Doherty configuration where a higher efficiency is kept even at lower drive level. For many communication and radar applications the output power of the amplifier is controlled and changes over time in order to adapt to the environment, or to conserve DC power in battery operated systems. Prior system knowledge and a good understanding of the application is key for an optimum amplifier design. In CDMA systems for example all users transmit at the same frequency at the same time. Constantly controlling the output power of all users to avoid interference and to equalize the receive signal levels at the base station is common practice to optimize the overall performance. In TDMA and FDMA systems the users have allocated time and frequency slots, hence output power

512

Power amplifier applications

0.8

PDF

0.6

TDMA/FDMA CMDA

0.4 0.2 0

–30

–20 –10 Pout /Pout,max (dB)

0

Figure 11.2 Measured PDF of the average output power in TDMA/FDMA systems and in CDMA systems [3].

is mainly adjusted to compensate for the distance to the base station and to conserve battery power. Figure 11.2 shows the measured PDF of the average output power in a TDMA/FDMA and a CDMA communication system. It is evident how dissimilar the RF power statistics of these systems are and that they require significantly different amplifier designs for optimum performance.

11.2.2

Linearity, modulation scheme, and crest factor The linearity of a power amplifier can be measured in many different ways in the time or frequency domain. The most useful but not fully comprehensive is the characterization of a nonlinear power amplifier in terms of the amplitude and phase distortion in relation to the the output or input signal power level. A nonlinear amplitude distortion results in an output amplitude or envelope of the signal that is not an exact amplified replica of the input envelope. In most cases the output signal will be compressed and the shape (slope) will have changed. A nonlinear amplitude to phase conversion is essentially a phase shift as a function of input drive and will cause an additional unwanted phase modulation of the output signal. Any nonlinear amplification will also cause additional frequency components in the output signal and an unwanted spreading of the output spectrum. Nonlinear distortion is caused by inherent nonlinear transistor effects, saturation effects, charge storage and thermal effects, and it also comes from the simple fact that every system is limited in output power and hence the amplitude of the output signal will be clipped at some point in time when it hits the limits of the system. As the efficiency is highest at the maximum output power of an amplifier people traditionally have operated the amplifer close to satturation and have used phase or frequency modulation schemes with constant enevelopes to achieve the best efficiency and linearity performance. Classic digital modulation systems such as FSK or PSK also have a constant envelope and utilize saturated amplifiers with the best efficiencies, but the phase/frequency signal transistion is quite aprupt and causes very wide spectral spreading. This is fine for the low data rates of the past, but for more modern systems a tradeoff between required data rate, available

11.2 System design parameter tradeoffs

513

spectrum, variation of the envelope amplitude and ruggedness towards amplitude and phase distortion has to be taken. Very commonly used in today’s communication systems is Gaussian minimum shift keying (GMSK) modulation, which is essentailly an offset QPSK modulation scheme that uses gaussian pulses instead of raised cosine filtering to reduce the modulation side lobes even further while still maintaining a quasi constant envelope. GMSK is used in GSM systems, in digital European cordless telephones (DECT), cellular digital packet data (CDPD) systems, the cellular phone systems digital communication systems (DCS) 1800, and in PCS1900 in the USA. The peak envelope power PEP of a given modulation scheme is one of the most important design figures in power amplifier designs. The size of the semiconductor devices, the maximum power and voltage ratings of all components, and the cooling capacity of the power amplifier assembly are all strongly dependent on the maximum output power required from the system. The ratio of peak signal power to average signal power (PAPR) is commonly used to determine the input power back-off that is required to provide good linearity. The PAPR is defined as: PAPR =

PEP Pavg .

(11.10)

and is often given as a logarithmic power ratio in dB: PAPRdB = 10 log

PEP Pavg

(11.11)

The voltage based expression of the peak to average ratio is defined by the Crest Factor CF, which is calculated by √ C F = PAPR. (11.12) Constant envelope signals such as frequency or phase modulated signals, unfiltered PSK, QPSK, GMSK, etc. have a PAPR = 0 dB. However, in multichannel applications where several modulated signals are combined and the composit signal is fed to the amplifier the signal envelope is not constant any more and will vary over time. For a two carrier signal the PAPR = 3 dB. It can be shown that for multicarrier signals with N independently modulated and not correlated carriers the peak to average power ratio is equal the number of carriers N. PAPR = N (number of carriers).

(11.13)

Many modern communication systems are using OFDM schemes where the data is transmitted by many closely spaced orthogonal subcarriers that are typically QPSK or PSK modulated. Although the subcarriers have a constant envelope, the composit OFDM signal has a wide variation in signal power. The number of subcarriers ranges from a few tens (e.g., 52 for WLAN) up to several thousands in DVB applications. Hence, the theoretical peak power could be very high (1000 times), but statistically very rarely occurs. In practice PAPR ranges from 10 dB to 16 dB. The large variation in power,

514

Power amplifier applications

and hence the required large power back-off, is one of the major drawbacks of OFDM systems. Recently, several methods have been developed to reduce the high PAPR of OFDM and other multichannel signals. Clipping and subsequent filtering techniques [4] remove the signal peaks and smooth the clipped signal. There are recursive methods [5] where clipping and filtering is repeated several times until the signal has the desired PAPR ratio. Clipping is inherently a highly nonlinear function and generates in-band distortion and out-of-band crosstalk, therefore there is always a tradeoff between PAPR and distortion. In the digital domain specific coding techniques e.g., Golay [6] or Reed–Mueller [7, 8] have been developed to avoid code constellations with high PAPR. Another method is to dynamically extend outer constellation points in data carrying channels in order to minimize the peak magnitude [9]. Similar techniques exist for CDMA and W-CDMA systems.

11.3

System level linearization techniques

11.3.1

Introduction to linearization techniques Linearization and efficiency enhancement techniques have been around since the 1935 and many variants have been developed and published since then. As the linearity and the efficiency of a power amplifier are contradicting requirements, quite often the applied technique either enhances the overall efficiency or it improves the linearity of the system. A simultaneous efficiency enhancement and linearity improvement is very difficult to achieve and usually requires the combination of several enhancement techniques. Typically, for a given linearity requirement of a system, the efficiency of the amplifier is enhanced or maintained over a wider dynamic range. Depending on the application the complexity of the linearization and/or efficiency enhancement technique can vary from a simple back-off system to a quite complex digitally predistorted Doherty amplifier. A predistortion scheme is primary a linearization technique that can vary in complexity and is put in front of an amplifier. The predistorter (linearizer) can also be combined with a subsequent efficiency enhancement scheme such as a Doherty system [10], an envelope elimination and restoration (EER) scheme [11] or a Chireix’s out-phasing (LINC) scheme [12]. In this way the efficiency and the linearity of the overall system can be improved, however these systems are very complex and costly. The most important enhancement schemes and their typical application are discussed in the following sections.

11.3.2

Digital baseband predistortion The concept of predistortion is similar to an audio equalizer that compensates for the acoustic characteristics of a system. However, the linearization for MW power amplifiers is not performed in relation to its frequency response, but to compensate the nonlinear

11.3 System level linearization techniques

Baseband Signal

FA(.)

X

515

PA

LO

Baseband Signal

FD(.)

X

PA

LO Figure 11.3 Basic principle of a linearized amplifier using predistortion

relationship of the input signal versus the output signal. It can be shown that in theory an nth-order nonlinear system can be compensated and linearized by cascading an inverse pth-order nonlinearity. The resulting system shows a linear transfer function up to the order of n*p, but then generates higher-order nonlinear mixing products, which typically are negligible. Figure 11.3 shows the basic block diagram of a linearized amplifier using a predistorter. In analog linearization systems the predistortion is typically implemented at RF frequencies. Using relatively simple RF circuit designs a gain expansion unit with an inverse phase characteristic is often realized that linearizes the power amplifier at the circuit level. The level of improvement is adequate for minor nonlinearities, however if there are strong linearity requirements, as is the case for multicarrier communication systems (CDMA and OFDM), then analog predistortion becomes very difficult. The inverse amplitude and phase characteristic have to be matched to the nonlinear PA characteristic very accurately (less then 0.1 dB in amplitude and a few degrees in phase) and need to be tracked over temperature, signal drive level, and ageing of the device. Therefore digital predistortion techniques with a feedback control loop have been developed. Digital predistortion techniques exploit the ever-increasing processing power now available from DSP devices, which allows them both to form and to update the required inverse nonlinear characteristic [13]. Typically, they operate with a digital baseband signal. The digital baseband predistortion (DPD) approach, as the name says, does not take into account the RF carrier frequency the PA is working at. It rather models the PA behavior by the following complex baseband model in which x and y are the complex envelopes of the RF input and output signal, respectively, and PA (|x|) is the complex amplifier gain depending on the input signal magnitude. y = x · PA (|x|)

(11.14)

Power amplifier applications

0

Power specturm denel

Power specturm denel

516

-20 -40 -60 -80 -100 -120 -3

-2 -1 0 1 2 Frequency / Hz

Baseband data

3

0 -20 -40 -60 -80 -100 -120 -3

-2 -1 0 1 2 Frequency / Hz

3

PA

Predistorter

LO

Figure 11.4 Illustrative block diagram of a predistorter.

Introducing PD (|x|) as the complex baseband predistorter gain depending on the input signal magnitude and M as the real PA gain, it can be described as follows. y = x · PD (|x|) · PA (|x|) · M

(11.15)

The entity forming the inverse nonlinear characteristic is the predistorter itself. There are several techniques to implement such nonlinear characteristics but all of them have in common that their output is calculated as an input magnitude-dependent function of their input. Thus, the predistorter produces a distorted signal out of its linear input signal. Beside the linear signal, the output signal contains the inverse intermodulation products, mainly of the 3rd, 5th, and 7th orders. Figure 11.4 illustrates the predistorter function. Taking the example of a single carrier UMTS signal, the distortion produced by the predistorter is depicted and the resulting linearity improvement at the PA output is shown with measured data. To enable this functionality, the predistorter system has to be implemented in such a way that it not only fulfils the Nyquist criteria according to the bandwidth of the incoming baseband signal but also the significantly higher one of producing the predistorted output signal. Furthermore, the linear baseband signal has to be sufficiently interpolated before it is fed into the predistorter. The higher bandwidth of the predistorted output signal has to be propagated up to the PA input, demanding suitable DACs and diligent analogue design. This can certainly be seen as the main drawback of digital baseband predistortion. One further issue for DPD is the determination of the nonlinearity applied to the baseband signal. The simple solution is to bring an example PA to a test bench, characterize its nonlinearities, calculate the inverse function, and program the predistorter with it. The linearity at the PA output will improve but effects such as device drift over temperature, aging, etc. are not considered. To overcome these severe limitations, adaptive DPD has been introduced. Figure 11.5 shows schematically the system in which a sample receiver is used which allows control of the PA output behavior instantaneously. Having feedback information from the PA output available within the DSP, an algorithm calculates the PA nonlinearity and hence its inverse function on a regular basis. Applying the calculated inverse nonlinearity to the predistorter, the difference between

11.3 System level linearization techniques

Baseband data

X

Predistorter

Y

PA

517

Z

LO Adaptation

Z′

LO′

Figure 11.5 Adaptive predistorter block diagram.

the baseband signal (X) and the sample receiver signal (Z’) is minimized. Such architecture is able to react to any changes in the behavior of the PA line-up mentioned above.

11.3.3

Memory effect compensation In wireless communication systems, the trend to higher bandwidths is unbroken due to multicarrier transmissions and new standards like LTE which support signal bandwidths up to 20 MHz. High PA output powers are also demanded to increase cell coverage. Unfortunately, with increasing signal bandwidth and higher output power, the PA shows dynamic semiconductor effects which are not covered by a single nonlinearity. These so-called memory effects are caused by thermal behavior, trapping effects and parasitic capacitances within the semiconductor. When compensating memory effects, it is not sufficient to consider only one single point in time in defining the PA characteristic. Hence, modeling and mitigating of such memory effects becomes more complex, especially when an additional variable such as time is taken into account. Figure 11.6 shows example measurements in three spectral plots which differ in the adjacent channels. Trace 1 shows the initial spectrum of a PA transmitting four carrier UMTS at approximately 40 W output power. The PA works with acceptable power efficiency but violates the applicable specifications for the adjacent channel leakage power ratio (ACLR) [14]. In trace 2, DPD is applied, resulting in higher linearity but still not fulfilling the specification in the alternate channels. The best linearization result is reached by applying DPD with memory effect compensation, as shown by trace 3. This signal now fulfils the specifications with a comfortable margin.

11.3.4

Impact on power efficiency In terms of power consumption, there is only a negligible amount required for DPD in DSP. The reason is that in most applications, a DSP unit already exists for other signal

518

Power amplifier applications

Figure 11.6 DPD performance plots.

Figure 11.7 Without DPD (10 W, 20 W, 40 W) left-hand side, 40 W with and without DPD right-hand side.

conditioning issues. This unit just has to be expanded to cover the digital baseband predistortion functionality. Fortunately, DPD can take advantage of the fact that the power dissipation of DSP decreases with the digital technology evolution. The power consumption of the DACs and the analogue circuitry also rises slightly because of the higher bandwidth to be transmitted. This supplementary effect is difficult to estimate but is in the region of a few watts. Hence, the amount of dissipated power to perform digital predistortion can be summarized as small and, furthermore, mostly independent of the PA output power. As a result, the power efficiency of a PA with DPD linearization increases with its output power. Figure 11.7 illustrates the power efficiency impact for an LDMOS PA module taking a single carrier UMTS transmission as an example. The left spectral plots show the behavior of a nonlinearized PA at different output powers and hence different power efficiencies. Trace L3 was measured when transmitting 10 W at about 8.0% power

11.4 Wireless communication power amplifiers

519

efficiency, trace L2 when transmitting 20 W at about 12% power efficiency, and trace L1 when transmitting 40 W at slightly more than 18% power efficiency. Whereas L3 and L2 fulfil the 3GPP ACLR specification, L1 violates it. Trace R1 on the right measurement plot shows the same measurement as L1 (40 W @ 18% efficiency). Trace R2 shows the result of applying DPD at the 40 W level. The PA now not only meets the ACLR specification, it also has higher output power and better efficiency than the nonlinearized amplifier when backed off to meet the spectral requirement (traces L2 and L3). This example shows that there is not only a power saving by applying DPD; transmitting 40 W at 18% efficiency with a single transistor instead of a nonlinearized 20 W at 12% saves a second semiconductor device and the combining network, which would be required to achieve a comparable output power of 40 W in the nonlinearized case. The overall DC power savings are more than 110 W. Even in this simple example the enormous benefit of introducing DPD can be seen. In cases where the PA has to transmit a wider signal bandwidths (e.g., four modulated carriers), quite often, memory effects of the amplifier degrade the performance such that even with a large back-off the ACLR specifications are violated and cannot be recovered. In those cases the utilization of a DPD scheme is absolutely required to make the system compliant (independently of the output power). Referring to Figure 11.6 a single DPD linearized PA is capable of transmitting a four-carrier UMTS signal and meeting the ACLR specifications, potentially saving up to three further PAs and a complex output combining network.

11.4

Wireless communication power amplifiers

11.4.1

Mobile radio communication today Today’s mobile radio communication is characterized by the coexistence of various different wireless communication standards such as GSM, UMTS and WiMAX. Soon this list will be supplemented by LTE which will be commercially introduced in near future. In the following, these main standards are briefly introduced.

Global system for mobile communication (GSM) GSM was the first standard of the so-called second generation (2G) mobile radio systems and enabled full digital radio communication, and was commercially introduced at the beginning of the 1990s. Today, GSM is still the most common standard in the world and is mainly used for telephony, packet switched data transmission, and short messaging (SMS). GSM works by means of different frequencies for uplink (transmission from user equipment to mobile radio network) and downlink (from mobile radio network to the user equipment). Later standard extensions which came along are HSCSD, GPRS, and EDGE (e.g., up to 220 kbit/s) allowing for faster data transmission.

Universal Mobile Telecommunications System (UMTS) UMTS was introduced as the third mobile communication standard (3G) with significantly increased data rates ranging up to 384 kbit/s in downlink. Standard extensions

520

Power amplifier applications

for increased data rates are, for example, HSDPA with up to 7.2 Mbit/s in downlink. Thanks to the increased data rates, UMTS supports audio- and video-telephony, internet access, etc. UMTS uses frequency-division-duplex (FDD) mode thus requiring paired frequency bands. The chip rate in FDD is 3.84 Mcps with a channel spacing of 5 MHz. Today, the 3GPP (third generation partnership project) consortium cares for UMTS and further standardization.

Long-term evolution (LTE) LTE (also called E-UTRAN or 3.9G) appears as a successor of the UMTS standard and was defined within 3GPP. LTE uses the so-called OFDM scheme and supports multipleinput-multiple-output (MIMO) techniques with the aim of enabling cheap high bit-rate data services and thus make mobile internet a mass market. Compared to UMTS, LTE supports different bandwidths (e.g., 3 MHz, 5 MHz, 10 MHz and 20 MHz) which make it more flexible for future use in different spectra. LTE is designed to operate in FDD mode as well as in time-division-duplex (TDD) mode.

Worldwide interoperability microwave access (WiMAX) WiMAX is used as a synonym for the IEEE 802.16 standard and can be regarded as being a competing standard to LTE. WiMAX networks can be used to connect GSM/UMTS base stations in the backhauling area or for wireless internet access. Unlike GSM, UMTS or LTE, WiMAX frequency bands are not globally standardized in a uniform manner and can also be used out of the usual mobile radio L and S bands up to high frequencies as e.g., 60 GHz. Three frequency bands in the range of 2.3 GHz, 2.5 GHz, and 3.5 GHz have been licensed by the WiMAX Forum which coordinates WiMAX policies. WiMAX is planned in FDD and TDD mode and supports different signal bandwidths up to 10 MHz. Like LTE, WiMAX is based on OFDM. The allocated frequency bands for mobile radio communication are mainly located in the UHF, L, and S bands between approximately 400 MHz and 4 GHz. Figure 11.8 indicates the placement of the mobile radio frequency bands compared to communication applications like point-to-point and satellite communication. Some frequency ranges allocated to the GSM-, UMTS-, WiMAX-, and LTE-standards are also shown. In the mobile radio frequency range the wavelength is still large enough to allow for hybrid amplifier realization, compared to the applications operating at even higher frequencies which more likely require MMICs. The current situation in mobile communication arose due to the sequential introduction of new standards which became necessary in order to satisfy the demand for the data rates which have been steadily increasing. These introductions needed to be performed without shutting down the preceding standards, at the same time observing regionally independent standards and frequency allocation or coverage requirements. Today’s and future standards increasingly use modern digital transmission techniques like W-CDMA (UMTS) or OFDM (WiMAX, LTE) in order to manage the continuously increasing data rates necessary to support mobile multimedia applications. Unlike GMSK used for GSM single-carrier application, the modulation schemes used in UMTS

11.4 Wireless communication power amplifiers

521

100 Power / [W]

Mobile Radio Communication

300 MHz

1 GHz

2 GHz

3 GHz

Broadband Wireless Access Sate PtP, PMP Com llite mun icat ion 4 GHz

8 GHz

12 GHz

18 GHz

27 GHz

30 GHz

40 GHz

Frequency

UHF L-Band S-Band SHF C-Band X-Band (Reference: ITU: Rec. ITU-R V4.31-7, Nomenclature of the Frequency And Wavelength Bands Used in Telecommunications) hybrid GSM LTE 0.9 GHz 0.45 GHz GSM CDMA

KU K Ka EHF

MMIC UMTS LTE LTE 2.1 GHz 2.6 GHz

1.8 GHz 2.5 GHz WiMAX GSM LTE

3.5 GHz WiMAX

(exemplarily overview only, collocation not exhaustive)

low

Energy Efficiency

High

Figure 11.8 Placement of mobile radio frequency range.

Increased signal PAR low (0 dB) 2G GSM

high (12 dB)

3G UMTS Speech and SMS only

low

4G WiMAX, LTE

Multimedia applications

Data Rate

high

(without application of linearization and reduction of signal dynamic)

Figure 11.9 Efficiency trend for different mobile radio standards.

or in future LTE are characterized by strongly varying signal envelopes with high peakto-average ratios (PARs) of > 10 dB. Figure 11.9 shows the effect of higher data rates on amplifier efficiency. While in the case of single-carrier GSM a relatively high efficiency can be obtained, the efficiency decreases significantly for modern standards like

522

Power amplifier applications

UMTS or LTE, due to high PAR. By applying signal dynamic reduction (clipping) techniques and linearization such as digital predistortion, this dramatic efficiency drop can be mitigated. These techniques have not been considered in Figure 11.9. Furthermore, the signal bandwidth clearly increases with increased data rates. In the case of the single-carrier GSM, a channel bandwidth of approximately 200 kHz is used, whereas for single-carrier UMTS, the bandwidth increases up to 3.84 Mc/s (5 MHz channel spacing). Usually, today’s base stations are capable of handling up to four WCDMA carriers resulting in a total signal bandwidth of 20 MHz. The total bandwidth allocated for UMTS in the core band is 60 MHz ranging from 2.11 GHz up to 2.17 GHz. LTE supports different bandwidths with up to 20 MHz per carrier.

11.4.2

System level and power amplifier requirements In addition to the previously mentioned requirements like frequency range and signal bandwidth, several further requirements either on system or amplifier level exist, which have to be fulfilled. In the following, some of the main requirements affecting the power amplifier are described in the case of the UMTS-FDD standard. Many important communication standard specific requirements are defined and put together by the particular standardization bodies in order to guarantee a sufficient quality of service as well as a widely undisturbed coexistence of different standards, and an undisturbed parallel operation in directly adjacent frequency bands of different operators. In order to assure this, very high linearity limits for adjacent channel leakage ratio (ACLR), or spectrum emission mask (SEM) are set by the 3GPP standardization bodies. In parallel, in-band linearity requirements such as error vector magnitude (EVM) or peak code domain error are defined by the standardization in order to secure a high quality of service. In order to meet the standard specific requirements and maintain high-energy efficiency, as well as due to technical limitations, today’s mobile communication market has usually to be supplied with frequency and communication standard specific solutions. This leads to the fact that system manufacturers have to provide a large product range resulting in a laborious development and logistic effort. Further system requirements arise from different application scenarios and cell planning aspects. Usually, indoor solutions support a smaller cell size compared to outdoor solutions which are designed for covering larger areas. Thus, the indoor solutions require lower transmit power levels, e.g., in the range of 20 dBm (0.1 W) or below. In contrast to this, macro base stations are in the range of 47 dBm (50 W) average transmit power per sector or even higher. In the 3GPP specifications [15] different power classes are defined as shown for UMTS-FDD by Table 11.1. During operation, a stable transmit average output power has to be guaranteed for the targeted output power, usually requiring an adaptive power control. The basestation power class directly controls the power amplifier dimensioning. Depending on the power class as well as on the application scenario, highly efficient solutions with limited power consumption are required. An application being highly critical with respect to energy efficiency and power consumption is, for example, a remote radio head solution. Such systems are preferably located at the antenna mast close to the antenna, thus

11.4 Wireless communication power amplifiers

523

Table 11.1 UMTS-FDD base station power classification Base station class

Rated output power

Wide area BS Medium range BS Local area BS Home BS

- (note) ≤ + 38 dBm ≤ + 24 dBm ≤ + 20 dBm (without transmit diversity or MIMO) ≤ + 17 dBm (with transmit diversity or MIMO)

Note: There is no upper limit required for the rated output power of the wide area base station similar to that for the base station for general purpose application in release 99, 4, and 5 (source: 3GPP TS 25.141 V8.6.0 (2009–03)).

requiring compact size, low weight as well as preferably no active cooling. An important benefit of such systems is that the cable losses of the antenna feeder can be drastically reduced leading to a clearly improved overall system efficiency compared to conventional solutions, where the base station is located further away from the antenna. Furthermore, with the clearly increased number of different mobile communication networks and also due to the improved coverage and complexity, the operating costs of the networks have clearly increased and constitute a large expenditure asset of the mobile operators which can’t be neglected. The ever-increasing wireless network causes a substantial share of worldwide energy consumption, affecting the utilization of natural resources and increasing significantly the carbon footprint. This situation highlights the need for highly efficient communication systems independent of technical requirements. Due to the fact that the base station load distribution has a clear influence on the base station energy efficiency, the demand for solutions maintaining high efficiency over a very wide dynamic range (e.g., down to 10 % load at night) becomes more and more important since maximum efficiency is achieved only at peak utilization for a limited period during the day. Advanced Doherty [16] techniques are resolving some of these problems by offering high efficiencies over a wider dynamic range. The Doherty principle is discussed in Section 11.9 of this chapter. An important requirement is also high reliability of all components in order to guarantee a long system lifetime with minimum defect probability. A mean time to failure of more than 10 million hours of operation within a specified temperature range is required from the power transistor.

11.4.3

Power amplifier design outline When designing a power amplifier for mobile radio communication, a plurality of parameters as well as the specific target application has to be taken into account. First the specific application-related requirements such as frequency band, power class, standardization requirements, efficiency, use of linearization techniques, etc. have to be collected. Against this list, a suitable semiconductor technology has to be chosen. Currently, silicon LDMOS is the most common technology for base stations due to good

Power amplifier applications

Power Amplifier

e.g. FPGA

(power amplifier output)

Design point with DPD

Vsat

Vout

Vin DPD Response

Overall System response Vout

Digital Predistortion

Vout

524

Vin PA Response

Signal Feedback (adaptive linearization)

Design point without DPD

Vin

Figure 11.10 PA design point when using digital predistortion.

efficiency, high linearity, and low cost. Because of the cost pressure in the telecommunication sector the power transistor price becomes an important decision factor, especially for high-power devices, and makes insertion and commercialization of new and more expensive semiconductor technologies like GaN-HEMT technology difficult, although GaN based devices show technical benefits such as higher transit frequencies, increased bandwidth capability and/or higher efficiency. GaAs FET devices are a third option but cost, power capability, and supply voltage limitations are the major factors why GaAs technology utilization is limited for base station power amplifiers in mobile communication compared to Silicon LDMOS devices. After suitable power transistors have been identified, a power and gain budget for the power amplifier line-up is prepared, taking the total required gain (influencing the required number of amplifier stages) and the potential use of a linearization scheme into account. Applying linearization procedures such as digital predistortion allows operating the power amplifier closer to its saturation point, increasing the efficiency, while still maintaining good linearity. Figure 11.10 indicates on the left-hand side the nonlinear response of the power amplifier as well as the related DPD response. On the right-hand side, the overall response and the amplifier design points without and with predistortion is shown. Without digital predistortion typically the 1 dB compression point is used as the design point for power capability in order to maintain sufficient linearity. The design point when using digital predistortion is shifted towards higher compression levels, typically the 3 dB compression point. In order to further increase the final stage amplifier efficiency and thus the overall efficiency, highly efficient power amplifier concepts such as Doherty or envelope tracking [17] are being evaluated. Doherty amplifier schemes are commonly already designed into products, but envelope tracking amplifiers are in the R&D phase and not yet as mature as standard Doherty PAs. The Doherty concept offers improved efficiency over a wider dynamic range by modulating the load. The basic symmetrical Doherty concept has a manageable increase in complexity compared to conventional Class AB amplifiers, and is the most popular concept for efficiency improvement in modern base stations. Limitations for the Doherty approach are the operational bandwidth (best suited for single-band applications), and the low-load efficiency improvement. In contrast, the envelope-tracking concept offers efficiency improvement through bias modulation.

11.4 Wireless communication power amplifiers

525

Conventional Class AB amplifiers are always operated with fixed supply voltages. Irrespective of the traffic load on the base station the full supply voltage is always supplied. In an envelope tracking amplifier a fast power supply modulator provides a modulated supply voltage to the RF transistor. The voltage is adjusted in relation to the signal envelope. Therefore the RF amplifier is always operated close to its saturation point and is thus highly efficient even at varying signal power levels. Compared to the Doherty scheme, the envelope-tracking concept requires higher complexity, specifically the addition of a high-power envelope modulator. However, the concept is inherently broadband and supports multiband applications. After the device and block diagram has been finalized, the amplifier design follows, usually supported by use of suitable computer aided design tools and transistor models provided by the semiconductor suppliers. Since the final power amplifier stage mainly defines the output characteristic (power, efficiency, etc.) of the whole line-up, the design process should be started with the final amplifier stage. In order to protect the final amplifier stage against reflected power (e.g., if the antenna is disconnected at full operation), usually an isolator whose insertion loss additionally has to be considered is placed after the power transistor. In order to enable adaptive predistortion, a coupler is additionally placed at the final power transistor’s output in order to feed a sample of the amplifier’s output signal back to the digital unit via an appropriate feedback path. This sample is a very low-power fraction of the output signal, hence avoiding a considerable degradation of the overall performance. For the design of the RF input and output matching networks, different techniques such as load-pull, load-line, and conjugate match based design are used. Figure 11.11 gives a basic overview of the RF power amplifier topology and the parameters which are affected by the particular building blocks. In the amplifier design an acceptable tradeoff between power, efficiency, and gain has to be found related to the respective application requirements. For example, linearity and efficiency are usually opponents, and linearity requirements are usually fixed by the standardization bodies for each standard and meeting them is thus mandatory. In order to squeeze the best efficiency out of the amplifier under this condition, the amplifiers are usually designed and operated close to these linearity requirements. Figure 11.12 illustrates this situation in a qualitative manner taking only ACLR as the linearity criterion into account. The dashed lines in the spectra plots indicate the linearity limits which are defined by the standardization organization. The measured single-carrier spectrum was obtained at the related power level. At low-output power levels the signal shows high linearity with a lot of margin with respect to the standardization requirements but with very low efficiency, the spectrum in the middle is at an increased output power level close to the linearity requirements and shows improved efficiency. The third spectrum on the right-hand side is measured at further increased output power with higher efficiency, but is violating the linearity requirements. As already noted earlier in this chapter, additional linearity parameters like EVM or Spectrum Emission Mask have in parallel to be considered and met. Once the final amplifier stage is designed, the driver and preamplifier stage design follows. It has to be ensured that the predriver and driver stages are powerful enough

Power amplifier applications

Biasing Networks affecting - maximum power - bandwidth Ouput - stability Bias

Input Bias

Output DC Feed

RFout

Input DC Feed

RFin

526

RF Block

Input Matching

Input Matching Network affecting - gain - bandwidth - stability

Power Transistor

Power Transistor affecting - maximum output power - energy efficiency - bandwidth

Output Matching

RF Block

Output Matching Network affecting - output power - bandwidth - energy efficiency

Figure 11.11 Main RF PA building blocks.

to drive the final amplifier stage, especially if digital predistortion is used since the final amplifier stage can be operated closer to its saturation point. Multistage packaged MMIC drivers are helpful in order to reduce design effort and allow for a more compact design since interstage RF matching is already included in the package and, additionally, the input and output impedance of such packaged drivers are 50  or close to it. Such multistage drivers are available in LDMOS technology. Figure 11.13 shows a three-stage amplifier line-up with the required matching networks. Additional electronic components for bias stabilization, gain control, and automatic shut down are usually used in order to guarantee a stable performance and safety for the power amplifier module and thus the whole base station. In summary, power amplifier design procedure has to address the three main subjects of semiconductor technology, power amplifier design concepts, and linearization and reduction of signal dynamic against the background of modern communication system requirements and standards in order to achieve the optimum performance of mobile radio communication amplifiers. All these three subjects have to be chosen specifically for the respective application, and have to be mutually optimized as indicated in Figure 11.14.

527

11.4 Wireless communication power amplifiers

ACLR requirement violated at ACLR limit

Power, Efficiency

ACLR

highly linear

poor linearity high efficiency Poutpk

at linearity limit increased efficiency

high linearity low efficiency

Poutav Efficiency ACLR 5 MHz

5 MHz ACLR limit

ACLR 10 MHz

10 MHz ACLR limit

Input Power

Input Matching

Pre-Amplifier Stage

Interstage Matching

Driver Amplifier Stage

Interstage Matching

Final Amplifier Stage

Output Matching

Load (Antenna Network, Antenna)

Source

Figure 11.12 Example of RF PA linearity and efficiency tradeoff.

Partially available as monolithic microwave integrated circuit

Figure 11.13 Multistage RF amplifier.

11.4.4

Doherty amplifier for efficient base stations In order to increase the efficiency of modern base stations in the field of power amplifiers, the Doherty concept (described in Section 11.9) is commonly used. Figure 11.15 shows a single-stage Doherty amplifier test board, based on AlGaN/GaN HEMT technology from FhG-IAF Freiburg.1 The amplifier was realized within a national funded research project.2 1 2

Fraunhofer Gesellschaft – Institute of Applied Solid State Physics in Freiburg, Germany The support of the German Ministry of Education and Research (BMBF) under contract 01BU600 is gratefully acknowledged.

528

Power amplifier applications

Figure 11.14 Holistic PA design approach.

Figure 11.15 Photo of a single-stage Doherty amplifier.

11.4 Wireless communication power amplifiers

529

Doherty Mode versus Balanced Mode @ 2.7 GHz

40

30

30

20

20

10

10

0

0

Drain Efficiency [%]

40

Pout (pk) - Doh Pout (av) - Doh Pout (pk) - Bal Pout (av) - Bal Efficiency - Doh Efficiency - Bal

–5

50

–7

50

–9

60

–2 5 –2 3 –2 1 –1 9 –1 7 –1 5 –1 3 –1 1

Power [dB m]

Clipped Single-Carrier W-CDMA Signal

60

Input Power (per amplifier) [dB m] Figure 11.16 Measured Doherty mode versus balanced mode characteristic.

The upper transistor in Figure 11.15 represents the main amplifier, the lower transistor constitutes the auxiliary amplifier, which is only active for high power levels. Since both transistors are of same gate width, it is a symmetrical Doherty amplifier. On the input side, a 3 dB, 90◦ hybrid coupler is used for signal splitting and feeding the signal to the input of the main and the auxiliary amplifier. On the output side, the matching network was manually tuned in order to guarantee a proper load modulation and thus achieve a satisfactory overall performance. The symmetrical GaN Doherty amplifier was designed for a center frequency of 2.7 GHz and for about 110 W peak output power. In order to evaluate the efficiency improvement enabled by the Doherty concept, the amplifier was measured in a Doherty configuration and subsequently in balanced mode configuration. This can be achieved by appropriate biasing of the power transistors. Figure 11.16 shows the measured average and peak output power as well as the drain efficiency for both configurations. Due to the fact that the Doherty configuration exhibits less gain compared to the balanced mode, the Doherty configuration was measured at up to 3 dB higher input power level. The measurement results show that for the available amplifier, a drain efficiency improvement of about 10% can be achieved at the 6 dB back-off range by applying the symmetrical Doherty concept. This constitutes a clear energy saving, especially for power amplifiers of mid and high power class. For these measurements, a single-carrier W-CDMA signal was used which had been reduced in its signal dynamic. Figure 11.17 shows a single-carrier W-CDMA spectrum measured at the output of the Doherty amplifier test board. For this measurement again a single-carrier W-CDMA signal with reduced signal dynamic was used. Additionally, digital predistortion was applied in order to meet the 3GPP ACLR linearity requirements combined with high efficiency. For the depicted measured output spectrum, the Doherty amplifier achieved

530

Power amplifier applications

Figure 11.17 Measured single-carrier W-CDMA output spectrum.

45 % drain efficiency at 44.9 dBm average output power, meeting the 3GPP ACLR specification.

11.5

Military power amplifiers

11.5.1

Radar Tx/Rx modules Tx/Rx modules are the most critical components of phased array radar systems. The basic block diagram of a T/R module is given in Figure 11.18. Functional blocks common to both Tx and Rx paths are a variable gain amplifier and variable phase shifter which are either duplicated or shared between the two signal paths as shown in Figure 11.18 by the use of Tx/Rx switches which are controlled by logic circuits. The duplexer, which is a ferrite circulator in general, provides three basic functions: r to provide a 3-port junction so that both the PA output and Rx path input can be simultaneously connected to the antenna without using a switch; r to protect the LNA device from damage when the Tx pulse is fired. X-band circulators have around 20 dB isolation between the Tx and Rx ports;

11.5 Military power amplifiers

531

Limiter TX

T/R Switch

LNA

Variable Attenuator Control Logic

Circulator Antenna

Variable Phase Shifter

RX

T/R Switch

HPA

Figure 11.18 T/R Module block diagram.

r PAs need to be presented with better than −20 dB load return loss otherwise the power output from the PA will degrade. In a phased array antenna system the impedance at the input of each antenna element is not a very well controlled parameter and changes with the phase state of each T/R module because of the moderate coupling levels between the antenna elements. Because the reflected power from the antenna element travels to the third port of the circulator independent of the antenna impedance, the power amplifier will always be presented with a matched load. Depending on the reflected power levels from the antenna element, either the LNA is designed to present a matched load in Tx or else a dual junction circulator is used with the fourth port terminated in a high-power load. The limiter prevents damage to the low-noise amplifier during transmit or whenever stray radiation is present. The limiter also provides a termination to the circulator during transmit to absorb power that is reflected from the antenna. The variable phase shifter is used to feed the antenna array elements with different progressive phase shift levels to provide the electronic scanning ability of the phased array. The variable attenuator is used to add an amplitude taper across the antenna array to reduce sidelobes. This is usually done in Rx , as in Tx one would like to radiate as much power as possible. The other function of the variable attenuator is to compensate for the insertion loss change of the variable phase shifter with the switched phase state. This is especially important in Tx , as the PA saturation level should be kept within some limits in order to protect PA devices from excessive forward gate currents which might have an adverse effect on device MTBF. The attenuator often performs a second function of aligning the amplitudes of the individual elements.

532

Power amplifier applications

The high-power amplifier (HPA) is the biggest and most expensive part of a T/R module. It also is the primary source of waste heat that you have to sink using a proper cooling arrangement. The HPA must be switched off after transmit to receive in a couple of 100 ns for two reasons: r the noise from the Tx path might de-sensitize the Rx degrading the sensitivity of the radar receiver; r keeping the HPA biased in Rx will degrade the overall efficiency of the T/R module. This is almost always done by circuitry that turns off the drain current to the HPA. It is theoretically possible to turn on/off the HPA using the gate voltage, but this is almost never done because any noise on the gate due to settling time of the modulation waveform will have a much larger effect than ringing on the drain voltage. p-channel MOSFETs are usually used to turn the amplifiers on and off. The p-channel MOSFET should have low on-resistance to keep the voltage drop as low as possible. Some of the important points to be kept in mind in drain switching are as follows: 1. Because the HPA needs to be quickly switched on and off between Tx and Rx modes, and because the power supply is electrically far away, properly sized charge storage capacitors must be used to supply the required current for the HPA devices during the RF pulse. The amplifier essentially runs off the capacitor during the RF pulse and the power supply merely supplies an average current to keep the capacitors charged up. Charge storage capacitors are nearly always tantalum because highdensity capacitance is needed in a small layout area. 2. The inductance between the charge storage capacitors and the HPA drain pads should be minimized in order to decrease the modulation on the drain voltage due to the . term V (t) = L ∂i(t) ∂t 3. The charge storage capacitors should not be placed between the p-MOSFET and the HPA because doing so will cause switching-off times of the HPA to be much longer. Although the p-MOSFET is switched off, the charge storage capacitors will continue to supply current to the HPA. 4. So the only solution is to keep the RF bypass capacitors (generally 10–100 nF) as close as possible to the HPA drain pads, place the p-channel MOSFET as close as possible to the HPA, and place the charge storage capacitors between the power supply and the p-MOSFET but as close as possible to the p-MOSFET. The size of the charge storage capacitors can be calculated as follows: Q = CV

(11.16)

where Q is the charge in Coulombs, C the capacitance in Farads, and V the voltage in volts. If we take the derivative of each side with respect to time then I (t) = C

∂ V (t) ∂t

(11.17)

11.5 Military power amplifiers

533

Table 11.2 Typical T/R module HPA performance requirements Frequency band

Bandwidth (MHz)

Power (W)

Efficiency (%)

S band X band

Up to 500 MHz Up to 1 GHz

Up to 1.6 kW Up to 20 W

40–50 30–40

where I(t) is the current in Amperes. Now we can re-arrange equation (11.17) to solve for CCS , the charge storage capacitance: CCS =

I t V

(11.18)

where I is the change in current in amperes with the RF pulse on and off, V the allowable voltage drop in volts between RF pulse on and off, and t the pulse width in seconds. Acceptable voltage droop levels are around 5%, which will drop the power by around 10%, equivalent to 0.45 dB. While selecting the capacitors one should make sure that the capacitors have a voltage rating of twice the drain voltage level. Also one should consider the derating factor when the HPA is required to operate at higher temperatures. T/R modules are physically connected to a phased array antenna and they should be sized to be below generally half wavelength of the operating frequency of the array in both dimensions including the space required for the cooling arrangement. For example, for a 3D array operating at 10 GHz the size of the T/R module needs to be less than 15 mm in both dimensions. The required power levels, bandwidths, and efficiencies from the HPAs to be integrated into a T/R module for S- and X-band radars are listed in table 11.2. The available devices in S band are LDMOS, GaAs pHEMT, and GaN pHEMT. 130 W LDMOS and GaAs pHEMT devices are commercially available from various vendors and if necessary then binary combining techniques, using balanced or Wilkinson structures, need to be used to reach the required power levels. GaN devices generating 400 W have been announced in recent years, which make even higher power levels achievable using less complicated combining structures. Most of the X-band radar systems developed in the last 5–7 years are based on 10 W GaAs pHEMT MMICs, which are available from various vendors. There are applications that combine two of these MMICs using Lange couplers or Wilkinson/Gysel combiners described in Section 11.6 to reach higher power levels. Some other important specifications for the T/R module, which have an impact on the HPA are: r amplitude droop across the pulse-width which is generally specified to be less than 0.5 dB. The two main causes are voltage droop and temperature rise of the device channel during the RF pulse; r phase droop across the pulse-width. This is generally specified to be less than 15◦ . r pulse-to-pulse phase stability. Generally specified to be less than −30/ −40 dBc and requires a complicated test setup to measure it. This is an important specification, as failure to meet the specification will result in a poor Doppler spectrum;

534

Power amplifier applications

r in recent years, radar communities are investigating complex modulation waveforms where not only the phase but also the envelope is changing within the pulse. This puts stringent linearity requirements on the HPA, i.e., an HPA cannot be operated at saturation and should have an acceptable AM–PM performance.

11.5.2

EW applications Power amplifiers find applications in jammer applications. Jammers are categorized as stand-off /Escort jammers and self protection jammers. Traditional designs generally incorporate high-power traveling wave tube amplifiers (TWTA) and high-gain directional antennas. There are two approaches; one is to use high-gain directional antennas on mechanical steering mechanisms and the second one is to use broader beamwidth lowgain fixed antenna installations. The drawback of using steerable high-gain directional antennas is the lack of ability to track and jam multi targets, and the drawback of using broader beamwidth low-gain fixed antennas is reduced effective radiated power (ERP). The solution to overcome these problems simultaneously is to use a phased array antenna system, and this configuration is favoured in more recent jammer designs. Obviously, there needs to be a tradeoff analysis in the size of the antenna system, the overall efficiency, and the available DC power from the platform where the jammer is going to be installed. The operating frequency range required from the stand-off jammer (SOJ) is generally 1–18 GHz and the frequency band is split into octave or broader bands, like 1–2 GHz, 2–6 GHz, and 6–18 GHz. Self protection jammers operate from 6 to 18 GHz. For a typical phased array configuration to achieve 70 dBm ERP level, the array size needs to be somewhere between 200 and 250 to guarantee 23 dB of array gain. Antenna elements are chosen to be omni-directional, a vivaldi antenna is a typical example, to minimize the scan loss across the azimuth and elevation coverage angles of the system, so total phased array antenna system gain will be identical to the array gain. To achieve 70 dBm ERP level, each power amplifier needs to deliver at least 50 W RF power. If each module is 50% efficient, then the total DC power and dissipated heat (for a 200 element array) will be 20 kW and 10 kW, respectively. It was not possible to design high-power and efficient octave band solid-state power amplifiers until recently, but advances in GaN pHEMT devices allows the achievement of greater than 50 W power levels in octave bands between 1–6 GHz. These high-voltage devices have breakdown voltage levels above 60 V, making it possible to operate with up to 30 V drain supply voltages and deliver 4–10 W/mm-gate periphery output power. By contrast, GaAs pHEMT devices operated from a 12 V power supply deliver typically 0.5 W/mm-gate periphery. As a result, for the same power level device sizes are an order of magnitude smaller in GaN technology. The major advantages of GaN devices over GaAs counterparts in practical implementations are summarized below: r load-line impedances to be presented to the GaN pHEMT devices are an order of magnitude higher, requiring a smaller impedance transformation ratio from the output matching circuit;

11.5 Military power amplifiers

535

Figure 11.19 1–2 GHz prototype power amplifier (courtesy of ASELSAN).

r Cds (output capacitance)/Pout (W) ratio is an order of magnitude smaller; r for a given power level, since the required gate periphery is smaller the real part of the input impedance is an order of magnitude higher and the input capacitance is an order of magnitude smaller compared to GaAs counterparts which makes the input matching circuit easier and broader band. The first two advantages allow the design of 50–100 W power amplifiers in octave bands. In addition, simple microstrip lines on soft-boards can be used in the output matching circuits, eliminating high-dielectric, low characteristic impedance components in the package. Two prototype circuits were developed for 1–2 GHz and 1.8–3.5 GHz jammer systems. The devices are packaged 45 W devices from Cree Inc and the power amplifier prototypes were designed on RO4350 soft-board. The single ended circuit developed for the 1–2 GHz system is shown in Figure 11.19. The parallel R-C circuit seen on the left side of the device is used to suppress low-frequency parasitic and parametric oscillations. Input and output matching circuits provide 50  impedance interfaces. Gain, power output at 3 dB compression, and efficiency are plotted in Figure 11.20. Gain is more than 15 dB from 0.8–2.2 GHz, power output greater than 55 W across 1–2 GHz, and efficiency is 55% average across the frequency band. The balanced circuit developed for the 2–3.6 GHz system is given in Figure 11.21. Input and output matching circuits provide 50  impedance interfaces. Gain, power output at 3 dB compression and efficiency are plotted in Figure 11.22. Gain is more than 12 dB across the band, power output greater than 65 W across 2–3.6 GHz, and the average efficiency is 45% across the frequency band.

22

80

19

65

16

50

13

35

10 0.8

0.9

1.0

1.1

1.2

1.3

1.4 1.5 1.6 1.7 Frequency (GHz)

1.8

1.9

2.0

2.1

Pout, Watts & Efficiency, %

Power amplifier applications

Gain (dB)

536

20 2.2

Figure 11.20 1–2 GHz prototype circuit performance plots (courtesy of ASELSAN),  gain,  power output,  efficiency.

Figure 11.21 2–3.6 GHz prototype power amplifier (courtesy of ASELSAN).

Gain (dB)

18.00

90.00

16.00

80.00

14.00

70.00

12.00

60.00

10.00

50.00

8.00

40.00

6.00

30.00

4.00

20.00

2.00

10.00

0.00 2.0

2.2

2.4

2.6 2.8 3.0 Frequency (GHz)

3.2

3.4

Pout, Watts & Efficiency, %

537

11.5 Military power amplifiers

0.00 3.6

Figure 11.22 2–3.6 GHz prototype circuit performance plots (courtesy of ASELSAN),  gain,  power output,  efficiency.

Figure 11.23 I/J band phased array jammer antenna (courtesy of ASELSAN).

An example of an I/J band phased array jammer antenna is shown in Figure 11.23. It has been designed for self protection. There are 16 modules per antenna and a photo of the PA module is shown in Figure 11.24. At the output stage, two 2 W GaAs pHEMT MMICs are combined to achieve at least 3.5 W across the frequency band using Lange couplers (see Section 11.7.2)

538

Power amplifier applications

Figure 11.24 I/J band 3.5 W module (courtesy of ASELSAN).

11.5.3

Anti-IED applications Military forces around the world face the threat of radio controlled improvised explosive devices (RCIED) used by terrorists to harm convoys and ground troops. A typical RCIED is composed of a large bomb, activated by an attached wireless device. After installing the RCIED in a main roadside, it can be activated any time by a wireless connection. They will most likely be activated when a large military convoy or vehicles pass by the bomb. Improvised explosive devices (IEDs) are attached to common wireless RF receivers, such as two-way radios, cellular phones, pagers and remote controls, etc., allowing the terrorists to use the transmitter remotely to detonate IEDs. One of the most common ways of countering IEDs and RCIEDs is using electronic countermeasures (ECM), known as jammers. A vehicle mounted IED jammer is installed in military anti-IED vehicles providing convoy protection. Portable IED jammers, like mobile phone jammers, are designed to prevent cell phone communication in designated areas, securing a small group of people. The cell phone jammer transmits RF signals which block the communication between the cell phone and the nearest cellular antenna, actively jamming cell phone frequencies within the blocking range of the jamming device. In order to be able to cover the possible wireless technology frequency bands, the PAs are generally broadband, but specific GSM or some other wireless communication standard higher power and narrower band PA designs are available in the market. Figure 11.25 shows a prototype 1 kW PA, designed to operate at HF/VHF (more than two-octave band) frequency bands for vehicle installation. Eight identical output stages are combined using the combining circuitry shown on the left hand side of the figure. Figure 11.26 shows a prototype 100 W PA, designed to cover VHF/UHF frequency bands for vehicle installation. This three-stage design has 50 dB gain with 1.5 dB frequency flatness and is stable into infinite VSWR at all phases.

11.6

In-phase power combining techniques

11.6.1

Wilkinson power combiners When it is necessary to deliver higher power levels to an antenna or a load, in-phase power combiners are important components of an RF or microwave transmitter. In this case a

11.6 In-phase power combining techniques

539

Figure 11.25 HF/VHF, 1 kW PA (courtesy of ASELSAN).

Figure 11.26 VHF/UHF, 100 W PA (courtesy of ASELSAN).

high level of isolation between the input ports is also required when identical amplitude and equal phase signals are combined. Combiners tend to get used as the last stage in a PA architecture, using the highest power devices available to reach even higher power levels. The insertion loss of the combining architecture is the most important factor in deciding the number of power devices to be combined using a Wilkinson combiner. The simplest one is the two-way combiner, where two input ports are combined √ using λ/4 transmission lines at band center, with a characteristic impedance of Z 0 2 where

Power amplifier applications

Z0√2 Z0 2Z0

Z0

Z0 Z0√2 Figure 11.27 Single-section Wilkinson divider/combiner.

Amplitude imbalance, dB 3

0

2

–10

1.5

–15

1

–20

0.5

–25

0 –3 –2.75 –2.5 –2.25 –2 –1.75 –1.5 –1.25 –1 –0.75 –0.5 –0.25

0

Pdiss (dB m)

–5

2.5

Ptotal (dB m)

540

–30

Figure 11.28 Effect of amplitude imbalance at the combined output. Both input signals are at the

same phase.

Z 0 is the reference impedance of the circuit. A typical single section Wilkinson power combiner is given in Figure 11.27. The effect of amplitude imbalance between the two input ports on the output port (combined output) is plotted in Figure 11.28. Total output power dissipated across the isolation resistor is shown in the lower trace referenced to the right. When two identical input signals are applied (i.e., 0 dBm each) the output power is 3 dBm and no power is dissipated across the isolation resistor. But if one of the signals is 1 dB less, than the total output reduces by approximately 0.5 dB and the rest is dissipated across the isolation resistor. The effect of phase imbalance between the 2 input ports on the output port (combined output) is plotted in Figure 11.29. When two identical input signals are applied (i.e., 0 dBm each) the output power is 3 dBm and no power is dissipated across the

541

11.6 In-phase power combining techniques

0

2

–5

1

–10

0

–15

–1

–20

–2

–25

–3

0

10

20

30

40

50

60

70

80

Pdiss (dB m)

Ptotal (dB m)

Phase imbalance, degrees 3

–30 90

Figure 11.29 Effect of phase imbalance at the combined output. Both input signals are at the same amplitude  total output power LH scale,  power dissipated in the isolation resistor RH scale.

isolation resistor. But if one of the signals is 30◦ out of phase, then the total output power is reduced by approximately 0.3 dB compared to the identical phase case and the rest is dissipated across the isolation resistor. The frequency bandwidth performance of a Wilkinson divider/combiner depends on the number of sections used. It can be thought of as a matching network stepping up the 25  impedance to 50  impedance at the combined output. So the transformation ratio is always two and the bandwidth performance can be improved by using multi quarter-wavelength lines with the impedance transformation ratio evenly distributed between the quarter wavelength line impedance transformation stages. Figure 11.30 shows the obtainable bandwidths for a single section (in triangles, straight line), two section (in squares, dotted line) and four section (thicker line) Wilkinson combiner. Taking 1.2:1.0 VSWR as a reference, which corresponds to -20 dB return loss, bandwidth can be improved from 30% to more than an octave by using a four-section Wilkinson combiner. An easy to follow design example of a three-stage 6–18 GHz Wilkinson Splitter is summarized in Figure 11.31. To obtain maximum bandwidth √ the intermediate impedances are set to give an equal impedance transformation ratio ( 3 2) at each stage. The intermediate impedance levels are 39.7  and 31.5 , respectively. The quarter wavelength frequency for the transmission lines is chosen to be 12 GHz. Figure 11.32 shows the layout of the 6–18 GHz Wilkinson splitter realized on a 15 mm thick alumina substrate and the performance is shown in Figure 11.33. Resistors are realized using 50 /sq NiCr material.

542

Power amplifier applications

Figure 11.30 Frequency bandwidth performance of two-way Wilkinson divider/combiner

 single-section,  two-section, ✖ four-section.

50 ohm

44.5 ohm

35.35 ohm

28.06 ohm

25 ohm

31.5 ohm

39.7 ohm

Figure 11.31 Design of a three-section 6–18 GHz Wilkinson splitter.

P1

Z1

Z2

Z3

λ /4

λ/4

λ /4

R1

R2

P2 R3 P3

Figure 11.32 Layout of the 6–18 GHz power splitter.

11.6.2

Gysel combiner The isolation resistors of the conventional Wilkinson combiner need to be small compared to the wavelength, and they are not grounded. Gysel [18] proposed a modification to the Wilkinson combiner in which the isolation resistor is replaced with a combination

543

11.6 In-phase power combining techniques

–3

–10

–3.2

–20

–3.4

–30

–3.6

–40

–3.8

–50

5

6

7

8

9

10

11

12

13

14

15

16

17

18

Insertion Loss (dB)

Return Loss and Isolation (dB)

0

–4 19

Frequency (GHz)

Figure 11.33 Performance of the 6–18 GHz splitter  insertion loss, – return loss, X isolation.

Z0 Z0 λ/4

Z1

Z0

λ/4 Z0

λ/2

Z2

λ/4 Z1

Z0

Z0

λ/4 Z0 Figure 11.34 Gysel high-power combiner.

of quarter wavelength lines and shunt connected 50  loads as shown in Figure 11.34. In this case each isolation resistor is connected to a corresponding output port through a transmission line. At the same time, all isolation resistors are connected to a common floating star point by the transmission lines. Thus, the Gysel combiner has the advantage of external isolation loads which can handle higher power levels. For a two-way Gysel combiner the 100  isolation resistor is replaced by two 50  resistors. The transmission

544

Power amplifier applications

P2

Z0

Open circuit

Z0

P2

Z0

λ/4

Z0 Z0 ohms Z0

Z0

λ/4

Short circuit

Open circuit

Z1

Z1 λ/4

λ/4

Z2

λ/4

λ/4

Open circuit

Z2

Short circuit

P1

P1 Z0

Z0

Open circuit

Short circuit

Z2

Z1

Z2

Z1

Open circuit

Short circuit

P3 Z0

Z0 Open circuit

Z0

P3

Z0 Z0

Z0 ohms

Z0

Figure 11.35 Even mode (a) and odd mode (b) excitation of the Gysel combiner.

lines characteristic impedances are given by: √ Z1 = Z0 2 √ Z2 = Z0 2

(11.19)

and Z 0 = R0 = 50  Figure 11.35 shows the even and odd mode circuits of the Gysel combiner. When the two input ports P2 and P3 are fed with even mode signals, the resultant circuitry is equivalent to the even mode equivalent circuit of a standard Wilkinson combiner. When the two input ports are fed with odd mode signals, identical amplitude but out of phase the combined port, P1, through quarter wavelength by 180◦ , P2 and P3 are connected to √ lines with impedance levels Z 1 = Z 0 2 and two real impedances Z0 = 50  are in shunt connection at each input port. So clearly the Gysel combiner is identical to a Wilkinson combiner at band center. The frequency response of a Gysel combiner is compared to a single section Wilkinson combiner in Figure 11.36. Taking 1.2:1.0 VSWR as a reference, which corresponds to −20 dB return loss, the bandwidth of a Gysel combiner is about 10% compared to 30% bandwidth obtainable from a single section Wilkinson combiner. This bandwidth reduction is due to the extra quarter-wavelength and half-wavelength transmission lines used in the Gysel topology. Also, the insertion loss of a Gysel combiner is higher than a Wilkinson combiner because of the longer transmission line connections to its inputs.

11.7

Quadrature-phase power combining – balanced amplifiers A balanced PA configuration is shown in Figure 11.37. Two identical power amplifiers are fed from an input quadrature 3 dB hybrid, which produces two signals in phase

11.7 Quadrature-phase power combining – balanced amplifiers

545

Figure 11.36 Input VSWR performance of Gysel combiner compared with a single-section Wilkinson combiner:  Gysel,  Wilkinson.

QUADRATURE 3 DB HYBRIDS

Z0

θ –3 DB

IN

IDENTICAL PA STAGES θ + 90deg Z0

OUT

–3 DB I

Figure 11.37 Balanced PA configuration.

quadrature, and the outputs of the amplifiers are recombined using a similar structure in reverse order. The main advantage of this configuration is that any reflections from the amplifiers cancel at the RF input/output ports and are dissipated in the loads connected at the isolated ports of the coupler structure. Obviously, in order for this balance to happen, the two amplifiers needs to be identical and the two paths through the coupler structure need to be identical in magnitude response and quadrature differential phase response. So the match seen at the input and output ports of a balanced amplifier will be perfect, regardless of the input/output impedances of the individual amplifiers. Before the invention of balanced structures, people were using bulky and expensive ferrite isolators at the input and output of single ended amplifiers with transistors having twice the transistor periphery.

Coupled and Direct ports (dB)

Coupled and Direct ports (degrees)

Power amplifier applications

Frequency (MHz)

Coupled and Direct ports (degrees)

(a)

Coupled and Direct ports (dB)

546

(b)

Frequency (MHz)

Figure 11.38 Quadrature coupler response for two different values of K. (a) Z0e = 125 , Z0o = 20 , K = 0.724 (−2.8 dB), (b) Z0e = 132 , Z0o = 18.9 , K = 0.75 (−2.5 dB)  coupled port insertion loss,  through port insertion loss, and X insertion phase of direct and coupled ports.

Balanced amplifiers are highly effective power combiners, a single ended design will need twice the transistor periphery to be able to deliver equivalent power levels to that of a balanced design. The other issue is that the required impedance transformation ratio needed in a single ended design will be twice that of a balanced structure as the

11.7 Quadrature-phase power combining – balanced amplifiers

547

input/output impedances will be halved as the transistor periphery is doubled, which will have an impact on the matching Q-factors, and consequently on the achievable frequency bandwidth. In this context, in most designs a balanced design is preferred. The 3 dB quadrature coupler structures are well established in RF and microwaves and detailed design information is supplied in the literature. The most basic example is a pair of quarterwave coupled lines, which are represented by their even and odd mode impedances, and the electrical length is chosen to be 90◦ at the design frequency. A pair of coupled lines is represented by two impedances Z0e and Z0o . Z0o is the characteristic impedance of the two strips under odd mode excitation and Z0e is the characteristic impedance of the lines under even mode excitation. The relationships between the even and odd mode impedances of a parallel coupled line pair, for a given coupling value K, are given as: Z 02 =



Z 0e Z 0o

K =

Z 0e − Z 0o Z 0e + Z 0o

(11.20)

Figure 11.38 shows the frequency response of a quadrature coupler for two different coupling values, K. As seen in the graphs, 90◦ phase difference between the two ports is always maintained, whereas the structure is narrowband in terms of the magnitude of the direct and coupled port signals. Figure 11.38a shows the performance when the coupling value K is chosen as −2.8 dB and Figure 11.38b shows the performance when K is chosen to be −2.5 dB at the band center. As K increases the achievable bandwidth appears to increase but at the expense of greater imbalance between the direct and coupled ports. Low values of Z0o represent very tight coupling between the two coupled lines, which is not physically possible with edge coupling. At RF frequencies the availability of multilayer PCB boards and via hole processing technologies enables miniature couplers to be realized by using broadside coupled lines in stripline configurations. An alternative is to use commercially available miniature coupler structures as separate components on the PCB. Generally, microwave hybrid PA designs require single-layer realizations which can be provided by branch-line quadrature hybrids, rat-race hybrids, Wilkinson splitter with a 90◦ phase lag in one arm, or Lange couplers. All the above structures can be realized using standard PCB techniques except the interdigitated Lange coupler as it requires very tight coupling between the lines and requires thin-film techniques to be realized.

11.7.1

Branch-line quadrature hybrid [19] For a fully matched case with standard 50  source and load impedances, the characteristic impedances of its transverse branches are 50  and the characteristic impedances of its longitudinal main lines are √502 = 35.35 . Figure 11.39a shows a 3 dB branch-line coupler for which power in P1 divides evenly between P2 and P3 with a phase differential of 90 ◦ C. P4 is the isolated port and, unless a mismatch exists at P2 and P3, ideally no power is delivered to this port. When identical load mismatches exist at the output ports

Power amplifier applications

P1, in Z0

P2, out Z0

Z0/√2 λ/4 Z0

λ/4

λ/4

Z0

λ/4 Z0 Z0

–2

0

–2.5

–5

–3

–10

–3.5

–15

–4

–20

–4.5

–25

–5 0.6 (b)

P3, out

Z0/√2

0.7

0.8

0.9

1

1.1

1.2

1.3

Isolated port (dB)

(a)

Direct and coupled ports (dB)

548

–30 1.4

Frequency (MHz)

Figure 11.39 (a) Microstrip branch-line quadrature hybrid, (b) performance  S12 ,  S13 ,  S14 .

P2 and P3, then all reflected power from these two ports is dissipated in the load at the isolated port and no power is reflected from the input port. The frequency response of a single section branch-line hybrid coupler is shown in Figure 11.39b, where all transmission lines are quarter-wavelength long at the band center. As can be seen, the operational frequency bandwidth of the branch-line hybrid is limited to 10–15% due to the quarter-wave transmission lines. When the output ports of the branch-line hybrid are different than 50 ohms, which is usually the case with balanced PA designs, the structure can be reconfigured to do the impedance transformation as well. In Figure 11.40, the output impedances of the hybrid are kZ0 , where k is any positive real number and the input port is matched to Z0 , usually 50 . In this case new quarterwave line impedances forming the branch-line hybrid can

11.7 Quadrature-phase power combining – balanced amplifiers

P1, in Z0

549

P2, out kZ0

Z2 λ/4 Z1

λ/4

λ/4

Z3

λ/4 Z0

P4

kZ0 P3, out

Z2

Figure 11.40 Impedance transforming branch-line coupler.

Conductor Length (L)

Input Port

Conductor Width (W)

Isolated Port

Conductor Spacing (S)

Coupled Port

Direct Port

Figure 11.41 Lange coupler.

be calculated using an even and odd mode analysis [20]. Z1 = Z0 Z0 √ Z2 = √ k 2 Z3 = k Z0

11.7.2

(11.21)

Lange coupler The Lange coupler is a four port, interdigitated structure developed by Dr. Julius Lange in 1969 [21]. The couplers are widely used as power combiners and splitters in RF amplifiers as well as in mixers and modulators. Lange couplers consist of very narrow coupled lines of a quarter wavelength coupled in parallel to allow fringing on both sides of the line to contribute to the coupling. Bond wires are used to connect nonadjacent lines in parallel. The resultant coupler will have a large bandwidth of at least an octave. Typically, the number of conductors or fingers (N) is even. The geometry for N = 4 is shown in Figure 11.41. The length of the fingers (L) is set by the desired center frequency (f0 ) of the filter. The device is relatively broadband, with a flat frequency response around f0 . The finger

550

Power amplifier applications

length is equal to the quarter wavelength (λs ) of f0 in the substrate, i.e. L = λs 4 where c λs = √ f 0 εeff

(11.22)

The effective dielectric constant is a function of the dielectric constant of the substrate as well as its thickness (h), the conductor width (w), and conductor thickness (t). The wavelength (λs ) can also be computed as the average of the wavelengths of the odd and even modes. The initial analysis involves calculating the odd and even mode impedances and then calculating the line width and spacing from:      C 1 Z 0o 2 (11.23) Z 0e = R = (C + 1)(N − 1) −1 + 1 + C 2 − 1 (N − 1) CdB

where N = number of coupled lines, C is the coupling coefficient given as C = 10 20 , and CdB is the coupling coefficient in dB.   Z 0 (N − 1 + R) ((N − 1)R + 1) Z 0e Z 0o = (11.24) (1 + R) where Z0 is the characteristic impedance of the coupler. Lange couplers have been used from UHF to Q band, perhaps even higher. But as the frequency goes up, the substrate height needs to decrease to prevent higher-order transmission modes in microstrip. The thickness of the substrate needs to be limited to 10% of the wavelength. Thus, 0.015 alumina is good up to 25 GHz, 0.004 GaAs is good up to 82 GHz, and 0.005 quartz is good up to 121 GHz. Reduced height means reduced strip width, which is the ultimate limitation. At some point the strips get so narrow that even if they do not fail the design rules, the conductor losses will start to limit the performance. Lange couplers on alumina are usually restricted to applications where the substrate is at least 0.015 thick i.e., the coupler will not operate above 25 GHz. If 0.010 alumina was used the strip widths would need to be less than 0.001 (25 μm). In MMIC applications, Lange couplers can be made on 0.004 thick substrates which will be good up to 80 GHz. If one attempted to make a Lange on 0.002 thick GaAs, then the strip widths would need to be about five microns which would making it too lossy. Figure 11.42 shows the measured performance of a 6–18 GHz Lange coupler realized on 15 mil thick alumina substrate. In Figure 11.42a, the insertion loss between the input port and direct/coupled ports are plotted in the lower traces scaled to the left axis, isolation and return loss responses are plotted in the upper two traces scaled to the right axis. In Figure 11.42b, solid lines shows the insertion loss imbalance between the direct and coupled ports scaled to the left and the dashed line shows the phase imbalance scaled to the right axis.

551

Frequency (GHz)

(b)

Phase diff btw direct and coupled ports (dB)

Imbalance btw direct and coupled ports (dB)

(a)

Direct and Coupled ports (dB)

Isolation and Return Loss (dB)

11.7 Quadrature-phase power combining – balanced amplifiers

Frequency (GHz)

Figure 11.42 Performance of the 6–18 GHz Lange coupler realized on 0.015 thick alumina substrate (εr = 9.8). (a)  coupled port and X direct port amplitude responses,  isolation, and  return loss responses, (b) amplitude and phase imbalance between direct and coupled ports.

552

Power amplifier applications

Input Balun

50 ohm

Zs, int

Input Impedance Matching

Output Impedance Matching Zs, opt

Zload, opt

Output Balun

50 ohm

Figure 11.43 Push–pull power amplifier schematic.

11.8

Anti-phase power combining – push–pull amplifiers Fundamentally, a push–pull circuit uses a pair of separate transistors operating 180◦ out of phase. If both signals in each half of the power amplifier are amplitude and phase balanced, then an RF ground will exist at the midpoint. This approach leads to several advantages over both single-ended and balanced designs: 1. Input and output impedances for each side are halved, also halving the required impedance transformations. 2. Ideally, zero even-order harmonics at the output of the push–pull amplifier. 3. Twice the power output for the same impedance transformation ratio which means achieving wider bandwidth compared to the equivalent single ended design. 4. Reduced Common Lead Inductance leading to higher gain. The most significant disadvantages are the need for differential RF excitation and the fact that excellent symmetry is required in both the matching circuit and the device itself. A generic push–pull circuit configuration is shown in Figure 11.43. Push–pull operation requires splitting the RF signal at the input, along with a reciprocal operation at the output to be able to combine the powers generated on each side. Circuit elements that provide this function are referred to as baluns (balanced to unbalanced). The ideal balun would split the signal into two halves of equal amplitude, along with providing a 180◦ differential phase shift across the frequency of operation. There are various approaches to realize the baluns, such as conventional coil transformers, transmission line transformers [22], and microstrip structures (Wilkinson divider; line and ring hybrids). The method of implementation heavily depends on frequency. For HF (up to 30 MHz) magnetically coupled coil transformers are suitable. Above these frequencies, leakage inductance and parasitic capacitance degrades the performance making them a poor choice. VHF and UHF circuits (30 MHz – 1 GHz) most commonly employ transmission line balun structures, built from coaxial cable or twisted pairs. Microstrip structures such as Wilkinson dividers also offer very good performance, but these are limited by their physical size (in the order of λ/2) and are therefore only practical at higher frequencies. Substrates with high dielectric constants can mitigate this problem to some extent. After the balun the input and output matching networks are usually calculated by conventional means treating each half of the transistor as if it were a single ended

11.8 Anti-phase power combining – push–pull amplifiers

553

Zout = N 2Zin / 2 Zout = N 2Zin

Zin

Zout = N 2Zin

Zin

Zin Zout = N 2Zin / 2

nout / nin = N

Figure 11.44 Some coupled coil transformer circuits: (a) autotransformer, (b) conventional transformer, (c) center tapped secondary.

device. The only important point to note is that the balanced (drain to drain) impedance should be twice the unbalanced (drain to ground) impedance.

11.8.1

Coupled coil transformers In a coupled coil transformer, the primary and secondary windings are coupled through a suitable magnetic material. For an ideal transformer, the relationship between impedances on the primary and secondary side is:   n in 2 (11.25) Z in = Z out n out where nin and nout are the number of coupled coil turns at the primary and secondary side, respectively. This implies that any impedance transformations can be realized, depending on the turns ratio. When the parasitics are negligible (i.e., up to 30 MHz) coupled coil transformers are often used where wideband resistance transformation is required. Various winding topologies are possible, and are chosen depending on whether DC isolation and/or balanced signals are required. Figure 11.44 shows the simplest coupled coil configurations. The autotransformer in Figure 11.44a has a tapped continuous winding and provides a DC short between input and output. Figure 11.44b shows a more conventional transformer with DC isolation between primary and secondary windings. Other arrangements can allow for balanced-unbalanced operation. The center tapped secondary transformer in Figure 11.44c is a balanced signal splitter which also provides an N 2 /2 impedance transformation. Higher permeability ferrites are usually preferred for improved coupling, but it should be kept in mind that high permeability cores will saturate more easily than those with lower permeabilities. Permeability can also vary as a function of current level, frequency, and temperature. Two-hole balun cores and toroids are the most commonly used ferrite structures. The choice of wire also affects performance. Thicker wire will increase the coupling, but it will also increase the parasitic winding capacitance. In practice, all transformers suffer from parasitic effects that cause their behavior to deviate from the ideal. The schematic

554

Power amplifier applications

CW

RWP

LLEAK_P

LLEAK_S

ZIN

RWS

ZOUT CP

LMAG

CS

RCORE

Figure 11.45 Practical transformer equivalent circuit.

l

l V

50 ohm

25 ohm (0°)

2V V

25 ohm (180°)

l Figure 11.46 Guanella transmission line balun.

in Figure 11.45 shows the equivalent circuit of a transformer. The ideal transformer is represented inside the dashed lines. Series resistances RWP and RWS are the resistances of the primary and secondary windings. Although these are negligible at DC, the skin effect will increase the resistance in proportion to the frequency as the frequency increases. RCORE models the loss of energy in the ferrite material due to eddy currents and hysteresis effects. Leakage inductances represented by LLEAK_P and LLEAK_S model the magnetic flux generated outside the ferrite core. LMAG limits the low-frequency response of the transformer and it has its physical origins in the finite magnetizing inductance in the coils. As the permeability of the ferrite increases, LMAG also increases such that it can be ignored. So for low-frequency applications higher permeability will be preferred. At higher frequencies, the capacitive effect between windings and between the turns of each winding will be the dominant factor limiting the performance.

11.8.2

Transmission line transformers Figure 11.46 shows the basic building block of a transmission line transformers – the 1:1 unbalanced to balanced transformer first introduced by Guanella in 1944 [23]. Note that this provides no impedance transformation, but each side of the balanced load has an impedance level which is half of that seen at the input. This is effectively an RF transmission line equivalent of the center-tapped transformer used at lower frequencies. The choice of transmission line largely depends on the characteristic impedance as dictated by the choice of balun or transformer. Coaxial cables of fixed values are freely

11.8 Anti-phase power combining – push–pull amplifiers

555

L = λ/4

ZIN

Z0 = √(ZIN*ZOUT)

ZOUT/2

ZOUT/2 Figure 11.47 Coaxial quarterwave tranmission line transformer.

2l Ri l

l

V V

Ro l

l

V

Figure 11.48 Ruthroff 1:4 unbalanced–unbalanced transformer.

available, and these can be combined to make transmission lines of varying impedances. As with most UHF/VHF transmission line transformers, Teflon insulated coaxial cable is preferred. The power handling capability is generally limited by the maximum allowable temperature, which is itself a function of dielectric material and cable diameter. The simplest type of transmission line transformer is the λ/4 line. Since the impedance match is dependent on the presence of a quarter wavelength standing wave, these transformers are inherently narrowband. They also require a transmission line of characteristic impedance which is the geometric mean of the input and output impedances to be matched i.e.:  (11.26) Z 0 = Z IN Z OUT This can limit the practicality of this technique since many types of transmission line are only available in a limited range of impedances. However, cables can be combined to achieve intermediate Z0 values. As well as the impedance matching function, the λ/4 line can be used as a balun in the same way as above – by grounding one conductor on the unbalanced side and connecting each conductor to one half of a balanced load on the other side. Figure 11.47 shows an implementation of this using coaxial cable. As well as the narrowband λ/4 transformer, a single transmission line can be used as an unbalanced to unbalanced (unun) transformer. This is capable of providing wideband 1:4 impedance transformation ratios by connecting it in the so called “bootstrap” configuration as shown in Figure 11.48. Here, the two conductors which constitute the transmission line are used as the primary and secondary windings in a similar way to the conventional autotransformer. If a voltage V is present across the input, the same voltage will be impressed across the lower conductor of the transmission line. The

556

Power amplifier applications

RIN

ROUT Zo = 2*RIN

RIN

ROUT

Figure 11.49 1:4 Unun coaxial and toroidal implementations.

3I

I

RL/9 RL

V

3V

Figure 11.50 1:9 Ruthroff unbalanced–unbalanced transformer.

voltage across Ro is therefore the sum of these voltages i.e., 2 V. If the current I is to flow through the load, it must also flow through the upper conductor. But again, since both conductors have the same voltage across them, the currents through each must be identical. Therefore, since Ro = 2 V/I and Ri = V/2I, then Ri = Ro /4. Calculations show that maximum power transfer occurs for this transformer with the optimum transmission line impedance of Z0 = 2Ri . For best performance the transmission line should be kept as short as possible. Figure 11.49 shows two practical implementations of the 1:4 balun using coaxial cable and wire-wrapped toroid configurations. Obviously, these devices are bilateral and simply reversing the ports will provide 4:1 step-down transformations. This technique can be extended to other transformation ratios by adding extra transmission lines. Figure 11.50 shows a 1:9 transmission line schematic alongside an implementation using coaxial cable. 1:16 transformations can be realized by adding a third conductor pair and connecting them in the same way as the second. One of the prime factors limiting high-frequency performance is the phase error caused by the arbitrary length of the transformer’s interconnections. If these connections were made using a transmission line of the same length, velocity factor, and impedance as the transformer line itself, then the phase error would be eliminated. An additional advantage is that the physical shape of the transformer is also no longer restricted by the need to bring connecting points close together. Devices of this type are referred to as equal delay transformers. Figure 11.51 shows how the principle is applied to the 1:4 Ruthroff [24] unbalanced-unbalanced transformer seen before in Figure 11.48. In push–pull circuits, impedance transformations between a balanced source and a balanced load are also often required. By combining a number of basic building

557

11.8 Anti-phase power combining – push–pull amplifiers

Interconnecting Line

ROUT/4

ROUT

Ferrite Figure 11.51 1:4 Equal delay Ruthroff unbalanced–unbalanced transformer.

Parallel (Low Z )

Series (High Z ) V

l

Parallel (Low Z )

Series (High Z ) l

3l

2l 2V

V

V

3V

2l l l 1:4 Transformer

3l 1:9 Transformer

Figure 11.52 1:4 Balanced–balanced transformer (left) and 1:9 balanced–balanced transformer

(right).

blocks in a range of parallel/series combinations, balanced to balanced impedance ratios of 1:n can be achieved. The diagrams in Figure 11.52 show 1:4 and 1:9 Guanella transmission line transformers based on this principle. Like the quarter-wavelength transformer, the optimum transmission line impedance is the geometric mean of input and output; however, small deviations from this can be permitted if some bandwidth degradation is acceptable. These transformers are often constructed of coaxial cable, and it is good practice to form the cable into a suitable shape to keep the interconnects as short as possible. The limitation of squared integer impedance ratios can be avoided to some extent by combining the conductors in more complex arrangements, but the benefits of doing this must be weighed against the practicality of the design and the possible loss of bandwidth.

11.8.3

RF/microwave push–pull amplifier Most high-power microwave LDMOS, GaAs FET, or GaN pHEMT devices consist of two independent sides without any internal transversal connection between the two sides. Though often called push–pull devices, the two sides can be combined in a variety of configurations created by external components such as 180◦ splitters/combiner

558

Power amplifier applications

zsource 25 ohm

50 ohm

25 ohm

zload

zseries

zseries

2Zp

2Zp

zseries

zseries

25 ohm

25ohm

50 ohm

Figure 11.53 Conceptual block diagram of microwave push–pull amplifier.

λ/4 @ band center 50 ohm coaxial line

Input (unbalanced) 50 ohm

Output (balanced) 50 ohm Z>>50 ohm

Input (unbalanced) 50 ohm

Figure 11.54 Coaxial balun structure.

(baluns), 3 dB quadrature couplers (like branch line or Lange couplers), and in-phase couplers (like Wilkinson couplers). Push–pull configurations are extensively used for high-power GaAs FETs for relatively narrow band commercial applications from UHF to S band. Figure 11.53 shows the conceptual block diagram of a microwave push–pull amplifier. Figure 11.54 shows a balun structure used at RF and microwave for push–pull amplifiers. One of the key requirements is to keep the balun structure sufficiently away from the ground such that the impedance from either end of the balanced outputs to ground is as high as possible. This structure was originally developed to feed antenna structures where balanced dipole ends need to be fed from an unbalanced source. The advantages of a push–pull amplifier can be summarized as follows: r four times higher device impedance (Zin gate–gate and Zout drain–drain) in comparison to single-ended device impedances with the same output power, which makes it easier to match and also obtain broader bandwidths; r a virtual ground exists across the symmetry plane which can be used for more compact and simpler matching structures; r cancellation of even products and harmonics, such as f2 − f1 , 2f1 , 2f2 , f1 + f2 , etc.

11.9 Doherty combining

559

The disadvantages of a push–pull amplifier are: r poor input and output external match due to the fact that the baluns used for push–pull amplifiers do not eliminate the input and output power reflected by the device, unlike in balanced configurations; r with conventional baluns, isolation between the two sides of the part is theoretically only 6 dB; this poor interdevice isolation can cause instability and loop oscillation problems; r manually made coaxial baluns are simple to make for laboratory use, but in production they require considerable labor that makes mass production expensive, and repeatability of the performance is not trivial. Surface mount baluns are available but add cost and tend to occupy more real estate than equivalent quadrature couplers. Another option for a microwave PA designer is the microstrip rat-race coupler shown in Figure 11.55. This is a planar structure and does not suffer from the same production, precision, and performance repeatability problems as the coaxial balun counterpart. However, it should be noted that rat-race ports are all at the Z0 (50 ) level, making the balanced impedance 2Z0 ; in this respect the rat race is not a true balun. Thus, the rat-race coupler does not provide the impedance transformation properties of a true coaxial balun and it has a narrower bandwidth, but the bandwidth is still large enough to satisfy the needs of various wireless power amplifiers.

11.9

Doherty combining An ideal Class-B amplifier schematic is given in Figure 11.56. The device’s Vgs is biased to its pinch-off value and the RF voltage magnitude is large enough to drive the gate–source junction such that the device delivers maximum drain current at the output terminals. There is a high-Q resonator tuned to f0 so the impedance presented to the drain terminals of the device is perfectly real at f0 and 0  at all harmonics. The load resistor is chosen carefully to maximize the power output from the device. The high-Q resonator allows all harmonic currents to flow through the device drain-source terminals, but allows only the fundamental voltage to exist across the device which results in a sinusoidal voltage and a half sinusoid current waveform. The peak current is Imax so the amplitude of the fundamental frequency component of the drain current is Imax /2. The voltage waveform swings from 0 to 2Vdc , so the optimum load impedance presented to the device terminals is: 2Vdc Imax

(11.27)

Vdc Imax 4

(11.28)

Ropt = The RF output power is given by: PRF =

560

Power amplifier applications

Isolated port

Output Port 1

l /4

l /4

Input port

l /4 Output Port 2

3l /4

(a)

(b)

Figure 11.55 (a) Rat-race coupler, (b) performance of rat-race coupler.

and because the DC value of the half sinusoid current waveform is Imax /π , the DC supply power is given by: PDC =

VDC Imax π

(11.29)

which gives a drain efficiency of: η= or 78.5%.

PRF π = PDC 4

11.30

561

11.9 Doherty combining

Let us now consider what happens when the input power level is backed off. Figure 11.56 shows the resulting waveforms when the input RF voltage swing is halved (power input is 6 dB backed off ). In this case the output current and output voltage swing magnitude scales down by the same amount. So in the general case, assuming that the gate-source input voltage swing is reduced by a factor p, then the fundamental component of the output current will be: I1 =

Imax 2p

(11.31)

and the output voltage swing will be given by: V1 =

Imax Imax 2VDC VDC = Ropt = 2p 2 p Imax p

(11.32)

Hence, the RF output power, DC supply power, and the resulting efficiency will be: VDC Imax 4 p2 VDC Imax PDC = pπ π1 η= 4 p PRF =

11.33

For example, a 6 dB reduction in RF input power level corresponds to p = 2 and the efficiency drops from π /4 to π /8 (from 78.5% to 39.3%). This is where the debate starts between the RF power amplifier designers and the telecommunications society. As the available frequency spectrum gets narrower there is a requirement to be able to accommodate higher data rates in smaller frequency bandwidths. In recent years new spectrum-efficient modulation techniques have been invented with the widespread use of available wireless technologies. Nowadays the information is not only stored in the phase but also in the envelope of the RF carrier signals. QPSK, QAM, and OFDM modulation schemes are a few of the modulation techniques developed so far. The two main requirements from the power amplifiers are efficiency and linearity. Linearity means small EVM in the modulation domain and low adjacent power levels. In a simple Class-B amplifier the only solution to sustain linearity under these complex modulation schemes is to back-off the signal, where the required back-off level depends on the amount of PAR level. This will have a negative impact on the average efficiency of a Class-B power amplifier as the efficiency degrades by the square root of the power back-off level. In order to get a better understanding of the requirements of a power amplifier which needs to be designed for a WIMAX (802.16e) basestation, let’s have a look at a couple of basic parameters: Pout, avg = 2W, EVM<2% and ACPR
Gate Voltage

Vds

2 Id + DC Block Vds –

1 + Vin –

Vo

Hi-Q Resonator @ fo

RL

6 dB backed-off + Vout –

Vp

3 ZL=RL+j0 @ fo ZL=0 @ (2fo, 3fo,...)

Vgs

0

0.5

Drain Current

1 Time (ns)

1.5

2

Drain Voltage

Imax 6 dB backed-off 1

Vds Imax/2

0

0.5

1 Time (ns)

Figure 11.56 Ideal class-B PA and its waveforms.

1.5

1 2

0

0.5

1 Time (ns)

1.5

2

11.9 Doherty combining

563

full rail-to-rail voltage swing at the output is maintained, and the maximum efficiency can still be preserved. This is the principle of the Doherty amplifier [25]. If the load impedance could be scaled to pRopt , then: R p = Ropt p =

2VDC p Imax

VDC Imax 4p VDC Imax PDC = pπ π η= 4 PRF =

(11.34)

The efficiency can be seen to remain constant at 78.5%. In fact, the solution is not that simple because even if such a challenge can be solved, the amplifier will be nonlinear. As seen from the above equations, when the input power level is scaled down by p2 the output power drops by only p. Leaving the linearity aside for a moment, the main problem is how to be able to dynamically adjust the load resistance to follow the amplitude changes in the envelope modulation of an RF signal. We require the load impedance to increase as the input signal to the amplifier decreases to maintain constant efficiency. The key issue we are dealing with when a signal has a varying envelope with time is that the full power capability of the PA is only needed at the envelope peaks, and when the envelope dips to a lower amplitude the PA capabilities are wasted to a greater extent. Another possibility not to waste the PA capability is to alter the DC supply voltage linked to the envelope variations. This falls into a bias adaptation category, which can be used for both efficiency restoration and linearity. Yet another possibility would be to modify the effective gate periphery of the device, but it is not a viable choice for a single packaged device as normally all the internal cells are wired together and this technique can only be considered if a distributed PA topology is used and cell combining is designed in a way to allow this technique to be applied. In 1936 Doherty devised a method of dynamically adjusting the load impedance using two separate amplifiers, one called the main amplifier and the other called the auxiliary amplifier. The original Doherty amplifier was concerned with very high-power tube amplifiers generating tens of kilowatts for high-frequency broadcast stations. The Doherty amplifier in its basic form looks like an active load-pull technique. The main principle is that the effective impedance of a load can be modified by applying some current from an external phase-coherent source. To get more insight into the concept we better look at the load-pull concept first. In Figure 11.57, current source 1 sees a load resistance of R if current source 2 is set to give zero current. But if current source 2 starts delivering a current I2 , then the voltage developed across R will be: V = R(I1 + I2 )

(11.35)

564

Power amplifier applications

l1

l2 +

Current source 1

R

V

Current source 2

–

Figure 11.57 Active load–pull schematic.

So the effective impedances seen at the terminals of current source 1 and current source 2 will be:     V I 1 + I2 V I 1 + I2 and R2 = (11.36) R1 = =R =R I1 I1 I2 I2 For example, R1 can be made larger than R if current source 2 delivers phase coherent current, and can be made smaller if current source 2 delivers antiphase current. As a result, if the two current sources are assumed to be two separate transistors, with phase coherent input drives, then the effective impedance presented to one of the devices can be modified by the amount of current delivered from the other device. Figure 11.58 shows the RF implementation of Figure 11.57. The two current generators represent the transistors; the left one being termed the main amplifier and the right one the auxiliary or peaking amplifier. The main amplifier is operational over the entire range of voltages applied to its gate terminal whereas the auxiliary amplifier only turns on above a certain threshold of applied RF input voltage, which in Figure 11.58 is assumed to be at half the maximum voltage applied to the main amplifier i.e., at 6 dB back-off, although other values can be chosen. Also, it is assumed in the following that identical transistors are used for both the main and auxiliary amplifiers, although this is not always the case. From equation (11.36) it can be seen that the load impedance seen by the main amplifier would increase as the auxiliary amplifier turns on whereas we require it to decrease so an impedance inverter is inserted between the load and the main amplifier as shown in Figure 11.58. It can be shown [25] that the RF drain voltage is constant in region 2 in the main amplifier at the frequency at which the transmission line is λ/4, and so the main amplifier maintains constant efficiency of 78.5% over the entire 6 dB back-off range from full power. While the main amplifier maintains constant efficiency, the auxiliary amplifier only operates at maximum efficiency at full output power and below that its efficiency follows that of a normal class B amplifier, assuming a class B amplifier is used for the

11.9 Doherty combining

ZmT

Zm

565

Zx

ZT, 90deg@fo

Vo = Vx

Vm

Ropt /2

laux = lx

lmain = lm

Fundamental frequency current

lmax/2 lm

lmax/4 lx

Vmax/2 Region 1

Vmax Region 2

Figure 11.58 Basic representation of a Doherty combiner.

auxiliary amplifier which is not always the case. It can be shown [25] that the overall Doherty amplifier efficiency is given by 

 vin 2 π Vmax  η=  vin 2 −1 3 Vmax

(11.37)

in As seen in equation (11.37), efficiency peaks are located at Vvmax = 1/2 and 1, corresponding to the-6 dB point and full power point, respectively. The efficiency makes a dip

Power amplifier applications

Main and Auxiliary PA voltages (left) and currents (right) 0.35

14 13

0.5

Main PA voltage

11

0.25

10 Aux PA voltage

9

0.2

8 7

0.15

6 5 Main PA current

4

0.1

3 Aux PA current

2

0.05

Current across device terminals (A)

12 Voltage across device terminals (V)

566

1 0 0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0 1.0

vin/Vmax

Figure 11.59 Main and auxiliary devices voltages and currents.

between these two points and the minimum can be found by equating the first derivative of the equation (11.37) to zero, i.e.   2 ∂η vin   =0 (11.38) = which gives vin Vmax 3 ∂ Vmax Substituting equation (11.38) into equation (11.37 gives a minimum efficiency of 69.8% in region 2 as shown in Figure 11.60. As noted earlier, the output power from the main amplifier changes linearly with input RF voltage rather than with input power and hence is nonlinear. However, not only does the auxiliary amplifier maintain constant efficiency from the main amplifier, it also overcomes this nonlinearity issue. It can be shown that the total RF output power from a Doherty amplifier has a linear dependence on the RF input power when the contribution from the auxiliary amplifier is taken into account– a remarkable result. Figure 11.59 shows the main and auxiliary amplifier voltages and currents for an ideal device with Imax = 500 mA and operating from 12 V DC supply voltage. Ropt is calculated to be 48 . The fundamental frequency component currents through the devices are drawn in dashed lines and scaled to the right y-axis. The terminal voltages are shown in solid lines and scaled to the left y-axis. The main amplifier terminal voltage reaches Vds when vin /Vmax = 0.5, which corresponds to -6 dB, and stays there for higher values of vin /Vmax . But since the main amplifier current continues increasing, the main side continues to contribute to the total output power.

567

11.10 Conclusions

3.5

84.0% efficiency

3

72.0%

2.5

60.0%

48.0% Total power Main PA power

1.5

36.0%

1

efficiency

Pout (W)

2

24.0%

0.5

12.0% Aux PA power

0 0.0

0.1 (–10 dB)

0.2

0.3

–6 dB

0.4

0.5

0.6

0.7

0.8

0.9

0.0% 1.0

(Vin/Vmax)^2

Figure 11.60 Power output and efficiency of the Doherty amplifier.

Figure 11.60 shows the RF power contributions from both the main and auxiliary amplifiers as a function of (vin /Vmax )2 , i.e., power input to the devices. The main, auxiliary, and total RF output powers are plotted in solid lines with square, triangle and diamond markers, respectively, and all scaled to the left y-axis. Efficiency is plotted in dashed lines and scaled to the right y-axis. The minimum value of the efficiency, between 0 dB and -6 dB points, is 69.8% and occurs at vin /Vmax = 2/3.

11.10

Conclusions Power amplifiers are usually the last active component in the RF chain and their performance has a significant impact on the overall system in terms of performance and cost. In particular the output power capability, the efficiency and the linearity are contradicting amplifier requirements. These are the primary parameters, which need to be traded off. In addition application specific design parameters, such as the PAR of the signals, the average efficiency, the dynamic range and/or the operational bandwidths need to be considered when deciding for the optimum amplifier architecture for a specific application. Starting from the system requirements for a typical 3G basestation an optimized power amplifier design with digital baseband predistortion has been discussed and measured result presented. Utilizing a baseband predistortion scheme, which compensates for memory effects, the overall amplifier performance can be enhanced by up to a factor of two compared to the non predistorted case. Further several designs of power amplifiers

568

Power amplifier applications

for phased array radar, jammer and other military applications are discussed. In particular the system aspects and their impact on the amplifier design are highlighted. In many cases the required output power for a given system cannot be obtained from a single transistor, therefore dedicated combining techniques have to be utilized. The advantages, the major draw backs and comprehensive design details are discussed for the in-phase, the balanced and the push–pull amplifier configurations. Finally the design guidelines for the more sophisticated Doherty combining technique, which significantly enhances the efficiency dynamic range of class B power amplifiers, is derived and presented.

Acknowledgments A significant number of professionals have been contributing to this chapter. In particular we would like to mention Dirk Wiegner and Thomas Bohn from Alcatel Lucent for their contribution. In addition some of the material in this chapter was adopted from the EU funded Network of Excellence TARGET (Top Amplifier Research Groups in a European Team). We would like to thank the TARGET team, in particular Gottfried Magerl and Martin O’Droma for their support. Finally we also would like to thank Aselsan A.S. (www.aselsan.com.tr) for providing the application pictures.

References 1. F. H. Raab, “Average efficiency of power amplifiers,” Proceedings of the RF Technology Expo 1986, Anaheim, CA, Jan. 1986, pp. 474–486. 2. F. H. Raab, P. Asbeck, S. Cripps, P. B. Kenington, Z. B. Popovic, N. Pothecary, J. F. Sevic, and N. O. Sokal, “RF and microwave power amplifier and transmitter technologies – part 1,” High Frequency Electron, pp. 22–36, May 2003. 3. P. Reynaert and M. Steyaert, RF Power Amplifiers for Mobile Communications, Springer 2006, pp. 25–26. 4. J. Armstrong, “Peak-to-average power reduction for OFDM by repeated clipping and frequency domain filtering,” IEE El. Lett., vol. 38, no. 5, pp. 246–247, Feb. 2002. 5. A. Saul, “Comparison between recursive clipping and active constellation extension for peak reduction in OFDM systems,” Proceedings of the International Symposium on Wireless Personal Multimedia Communications, Yokusuka, Japan, Oct. 2003. 6. K. Sathananthan and C. Tellambura, “Coding to reduce both PAR and PICR of an OFDM signal,” Commun. Lett., IEEE vol. 6, issue 8, Aug. 2002. 7. K. G. Paterson, “Generalized Reed–Muller codes and power control in OFDM modulation,” IEEE Trans. Inf. Theory, vol. 6, no. 1, pp. 104–120, Jan. 2000. 8. J. A. Davis, J. Jedwab, “Peak-to-mean power control in OFDM, Golay complementary sequences, and Reed-Muller codes,” IEEE Trans. Inf. Theory, vol. 45, no. 7, pp. 2397–2417, Nov. 1999. 9. Byoung-Jo, C. and Hanzo, L., ”Crest factors of complementary-sequence-based multicode MCCDMA signals,” IEEE Trans. Wireless Commun., vol. 2, no. 6, pp. 1114–1119, 2003. 10. W. H. Doherty, “A new high efficiency power amplifer for modulated waves,” Proc. IRE vol. 24, pp. 1163–1182, Sept. 1936.

References

569

11. L. R. Kahn, “Single sideband transmission by envelope elimination and restoration,” Proc. IRE, vol. 40, 803–806, July 1952. 12. H. Chireix, “High power outphasing modulation,” Proc. IRE, vol. 23, no. 11, pp. 1370–1392, 1935. 13. F. H. Raab, P. Asbeck, S. Cripps, P. B. Kenington, Z. B. Popovic, N. Pothecary, J. F. Sevic, N. O. Sokal, “RF and microwave power amplifier and transmitter technologies – part 4, High Frequency Electron., pp. 38–49, Nov. 2003. 14. 3GPP TS 25.104 V8.4.0 (2008–09) specification [Online]. Available at http://www.3gpp.org 15. 3GPP TS 25.141 V8.6.0 (2009–03 specification [Online]. Available at http://www.3gpp.org 16. S. C. Cripps, Advanced Techniques in RF Power Amplifier Design, Artech House, 2002. 17. D. Wiegner, G. Luz, P. Juschke, R. Machinal, T. Merk, U. Seyfried, W. Templ, A. Pascht, R. Quay, and F. Van Raay, “AlGaN/GaN-based power amplifiers for mobile radio applications: a review from the system supplier’s perspective,” Int. J. Microw. Wireless Technol., vol. 2, no. 1, pp. 95–104, 2010. 18. U.H. Gysel, “A new N-way power divider/combiner suitable for high Power applications,” IEEE MTT-S Int. Symp. Dig., 1975, pp. 116–118. 19. R. Levy and L. Lind, “Synthesis of symmetrical branch-guide directional couplers,” IEEE Trans. Microw. Theory Tech., vol. MTT-16, pp. 80–89, Feb. 1968. 20. R. K. Gupta, S. E. Anderson, and W. J. Getsinger, “Impedance-transforming 3 dB 90◦ Hybrids,” IEEE Trans. Microw. Theory Tech., vol. MTT-35, pp. 1303–1307, Dec. 1987. 21. J. Lange, “Interdigitated stripline quadrature hybrid,” IEEE Trans. Microw. Theory Tech., vol. 17, pp. 1150–1151, 1969. 22. J. Sevick, Transmission line transformers,” Newington, CT, USA, American Radio Relay League, 1987. 23. G., Guanella, “Novel matching systems for high frequencies,” Brown–Boveri Rev., vol. 31, Sept. 1944, pp. 327–329. 24. C. L. Ruthroff, “Some broad-band transformers,” Proc. IRE, vol. 47, Aug. 1959, pp. 1337– 1342. 25. S. C., Cripps, RF Power Amplifiers for Wireless Communications, Artech House, Norwood, MA, 2006, pp. 290–298.

12

Amplifier measurements Michael Hiebel Rohde and Schwarz GmbH & Co. KG.

12.1

Introduction The measurement results obtained in this chapter are the major factors that justify the price of an RF amplifier. The first test results of a new prototype are used for optimization purposes. Once the product is released, production-line testing with a manageable test depth takes place. Important properties are tested on each sample during final productionline testing. Inaccurate testing can lead to additional cost-intensive design cycles or negatively affect the relationship between the manufacturer and customer. It may even lead to legal consequences. Accurate RF testing is a complex topic, and this chapter can only provide an overview. The information provided in this chapter was prepared with utmost care but it cannot be assumed to be complete or free of errors. This chapter is meant to be academic in nature; it cannot replace engineering or other professional services. The power levels covered in this book make it necessary to consider national and international safety regulations, e.g., for nonionizing radiation. The reader is advised to consult the applicable versions of the regulations.

12.2

Power measurements Due to their modest price, power sensors are the first choice for built-in monitoring systems or for realizing automatic gain control (AGC). Because of their simple design, power sensors can be built to be more stable than instruments such as spectrum analyzers, which involve approximately 25 to 150 analog components in their RF path. On the other hand, power sensors are subject to some restrictions due to their wideband implementation, their absence of phase information, and their comparatively slow response time.

12.2.1

Typical power sensor principles A power sensor’s main task is to convert the applied RF power to a measurable DC signal. Three principles can be distinguished:

Diode sensors One or two semiconductor diodes can be combined to form a circuit that works like a rectifier. Zero-bias Schottky barrier diodes with low threshold voltage are customarily used to build these

12.2 Power measurements

V1 RF Input P

R5

R4

R3

V2 R1

571

R6

Vout

R2 C1 C2

Termination (50 Ω)

C3

Rectifier Charging Decoupling capacitors

Figure 12.1 Simplified circuit diagram of a diode sensor [1].

diode sensors (see Figure 12.1). They exhibit high sensitivity down to 10 −10 W but cannot be used at very low frequencies. The frequency range is always limited by the charging capacitors which, in conjunction with the DC resistance of the diodes, form a highpass filter for the trapped RF voltage.

Thermal sensors Thermo-measurement cells are typically placed on a thin silicon substrate (see Figure 12.2). They use a thin layer of tantalum nitride or chromium nickel to convert the RF power into heat. The heat, in turn, is transformed into a very low DC voltage of just a few microvolts. The sensitivity of these thermal sensors is limited to about 10−6 W.

Thermistor sensors The bolometer principle is based on thermistors and barretters like the thermistor power meter shown in Figure 12.3. Two thermistors with a high negative temperature coefficient combine the functions of termination and temperature sensor. They simultaneously absorb the RF power to be measured and a DC power. In a bridge circuit, the DC resistance is measured and kept constant by varying the DC power. Any increase of the RF power is thus always compensated by an equivalent reduction of the DC power and vice versa. The DC power can easily be measured.

Each principle exhibits typical advantages and disadvantages, which are summarized in Table 12.1. Diode sensors are often equipped with an internal attenuator pad to improve their matching and to fill the gap between pure diode sensors and thermal sensors. Power sensors can be used to verify modulated signals (see Figure 12.4): 1. Diode sensors can be optimized for a short response time to detect the envelope power Pe (t) of a modulated signal. The sensor averages the power over only a few periods of the carrier. It is therefore possible to detect changes in the envelope power. 2. Fast diode sensors can be combined with a peak hold circuit. The maximum envelope power is then detected. It is referred to as the peak envelop power (PEP) of, for example, a TV sync pulse or a TDMA radio signal. 3. Thermal power sensors have a slow response time but they feature a direct relationship between RF power and output voltage. Therefore they indicate the average power Pavg of both CW and modulated signals.

572

Amplifier measurements

8

Output – +

1 mm

11 10 2

7 6 Input

4

5

3 1 9

Figure 12.2 Sectional view of measurement cell with silicon substrate (1), membrane (2), RF feed layer (3), termination (4), thermocouple (5), metal contact (6), highly doped silicon (7), cold junction (8), insulating layer (9), metallized ground (10), bump (11) [1].

Coaxial RF connector

P

Vdif

IRF IDC Vref

Figure 12.3 Principle of a thermistor power meter [1].

Diode sensors operate over a wide input power range. Within this range, two different regions can be identified: 1. The square-law region is reserved for very low power levels. The current-voltage characteristic of the diodes exhibits a dominant square term which causes rms

12.2 Power measurements

573

Table 12.1 Comparison of typical power sensors

Frequency range sensors are offered Typical frequency range examples

Sensitivity Dynamic range Precision Response time Input match Peak envelope power measurement

P PEP

Diode sensor

Diode sensor including an attenuator

100 kHz to 220 GHz 100 kHz to 8 GHz 10 MHz to 18 GHz −20 dBm to −70 dBm 50 dB − 1 ms 6 dB to 10 dB can be used

Thermal sensor

Bolometer/ thermistor

100 kHz to 67 GHz

DC to 67 GHz

DC to 2 THz

100 kHz to 8 GHz 10 MHz to 18 GHz +50 dBm to −40 dBm 40 dB + 1 ms >30 dB can be used

DC to 40 GHz

DC to 18 GHz 75 GHz to 2 THz

+20 dBm to −30 dBm 40 dB ++ 0.1 s to 1 s >25 dB cannot be used

+20 dBm to −30 dBm 20 dB +++ 1 s to 100 s >25 dB cannot be used

Pe(t)

Pp

Pavg 0

tp

t T

Figure 12.4 Typical properties of a (pulse) modulated signal [1].

rectification. The DC voltage of the detector circuit is approximately proportional to the input power. CW and modulated signals are converted according to their power. The voltage obtained is about 10−10 V to 10−5 V. 2. With increased power levels, the square-law region will be exceeded. Highly stable, noise-free measurements are possible due to output voltages of approximately 10 mV to a few volts. Compared to the square-law region, the sensor becomes very fast but measures the RF voltage instead of the RF power. It behaves like a diode rectifier, weighting the peak of the RF voltage, which is approximately proportional to the peak envelope power of the RF. Nevertheless, today’s sensors can be calibrated so that their output voltage is interpreted as an (average) power level, but this is based on the assumption that the signal to be measured is a pure unmodulated CW signal.

574

Amplifier measurements

Table 12.2 Power sensor side effects and compensation techniques Effect

Compensation technique

Drift of zero value Thermal drift of temperature-dependent parameters Aging of sensitivity Calibration factor K( f ) Power linearity at 23 ◦ C Noise Mismatch effect Connector repeatability

Zeroing Built-in temperature sensor and sensor-specific data of temperature effects Reference oscillator of the power meter Sensor-specific data supplied with sensor Sensor-specific data supplied with sensor Averaging, video filter ** Compensation usually not done! ** ** Compensation not possible! **

Power sensors are of a broadband design. They therefore exhibit a limited dynamic range of typically 30 dB to about 50 dB depending on the type of sensor. However, a high dynamic range up to 90 dB can be achieved by implementing the following techniques: 1. Average several measurement values by using digital signal processing (DSP). 2. Introduce a video filter at the DC part of the sensor, which is actually implemented by a DSP. 3. Use a chopper amplifier within the DC part to overcome the zero drift of the signal chain. 4. Combine several detectors with different sensitivities in a single power sensor. A large dynamic range for modulated signals is obtained by operating each detector exclusively in its square-law region, and by using only the optimally driven detector for the measurement.

12.2.2

Typical sources of measurement uncertainties Power sensors are accompanied by various side effects (Table 12.2). To increase measurement accuracy, techniques for compensating for these effects are available. Zeroing and compensation using a reference oscillator can be performed by the operator on site. All of the other compensation techniques require sensor-specific data (e.g., stored in an EEPROM) that have to be measured in a traceable, commonly accepted manner by the sensor manufacturer or at an accredited calibration service. The compensation techniques listed in Table 12.2 leave some residual uncertainties, e.g., due to the uncertainty of the sensor-specific data. Unfortunately, the mismatch effect usually is not compensated for even though it is the dominant effect in the residual measurement uncertainty. Therefore, it deserves a closer look. The port that the power sensor is connected to and all RF circuitry in front of the power sensor’s reference plane can be considered to be an equivalent generator. The measurement task is to quantify the nominal source PZ0 . It is the power that the equivalent generator would deliver if terminated by the reference impedance Z0 (e.g., 50  or 75 ). Ideally, the power sensor would exhibit this impedance.

12.2 Power measurements

575

Pd Pi

Pr G

Equivalent generator

ΓG

ΓL L

Power sensor

Figure 12.5 Power flow between equivalent generator and power sensor.

However, the actual situation is more complicated, as shown in Figure 12.5. The power sensor’s impedance ZL is not exactly equivalent to the reference impedance Z0 . Therefore, it exhibits a reflection coefficient  L = 0, where L =

Z L − Z0 Z L + Z0

(12.1)

A portion of the power Pi incident to the power sensor is reflected as power Pr and travels back toward the generator. The power Pd dissipated by the power sensor remains as: Pd = Pi − Pr = Pi (1 − | L |2 ).

(12.2)

A typical equivalent generator will have a source impedance ZG somewhat different from Z0 , and it will therefore exhibit a reflection coefficient of  G = 0. G =

ZG − Z0 ZG + Z0

(12.3)

Consequently, the power Pr traveling back toward the generator will not totally be absorbed by the equivalent generator. The electromagnetic (EM) fields related to the powers Pr and PZ0 will superimpose with one another. Assuming a real-valued characteristic impedance Z0 this can be described by the powers Pr and PZ0 instead of using the relevant wave quantities introduced later in Section 12.4.1. Assuming  L < 1 and  G < 1, this process can be described as follows: Pi = PZ 0

1 |1 − G  L |2

(12.4)

Not all the power dissipated as Pd will be converted to the measured power Pm . A factor called effective efficiency ηe has to be introduced: Pm = ηe · Pd

(12.5)

Using equations (12.2) to (12.5), the relation between the measured power Pm and the nominal source power PZ0 is calculated as follows: Pm = ηe (1 − | L |2 ) ·

1 · PZ 0 |1 − G  L |2

(12.6)

576

Amplifier measurements

The first factor ηe (1 − | L |2 ) is the calibration factor K( f ). It is based on the sensor’s inherent properties and is independent of the equivalent generator. It is determined as a function of frequency using an ideal generator G = 0 with known nominal source power PZ0 and known CW frequency f. In practice, a calibration system formed from traceable components such as a precision power sensor (traveling standard), a precision power splitter and a generator involving an automatic level control (ALC) is used. Once factor K( f ) is known, the following relation between measured power Pm and the nominal source power PZ0 applies. PZ 0 =

1 · |1 − G  L |2 · Pm K( f )

(12.7)

Most modern power sensors provide phase and magnitude information of  L ( f ) as premeasured data that are referenced to the power sensors reference plane. If the complex coefficient  G of the equivalent generator is known, then correction for the factor |1 −  G  L |2 is possible. This technique is called gamma correction of the power meter. However, the phase of the generators reflection coefficient is often unknown and it will be changed due to adapters and other things introduced between the generator and power sensor. Thus, it is only possible to determine the uncertainty that is introduced by the factor |1 −  G  L |2 using the magnitudes | G | and | L | and the following relation: (1 − |G | | L |)2 · ≤

PZ 0 K ≤ (1 + |G | | L |)2 Pm

(12.8)

A power sensor cannot accurately measure the nominal power PZ0 of a mismatched source unless it is ideally matched itself. In other words, the magnitude | L | is a very important quality criterion of a power sensor.

12.2.3

High-power RF measurements and directional power Measurements One approach to connecting a power sensor to a high-power RF source is to use an attenuator to adapt the level between RF source and sensor. The following is an example of how to measure a 60 W output power of a GSM base station amplifier. The attenuator (Figure 12.6) consists of several stages for distributing the power dissipation between the stages in nearly equal amounts of approximately 20 W. The last stage has the most attenuation (d3 = 15 dB). In contrast to other stages, it is designed as a -circuit because it is more convenient than the T-circuit if an attenuation value di above 10 dB is required. This attenuator design has a dedicated input and output port. Interchanging these ports would dramatically alter the power distribution between stages. The stage with the 15 dB attenuation would then have to cope with ≈58 W of dissipated power and burn-out. Although attenuators are reciprocal devices (S21 = S12 ), most high-power attenuators can only handle a fraction of their nominal power rating when being operated in the reverse direction!

12.2 Power measurements

577

Table 12.3 Multistage implementation of a high-power 20 dB attenuator

Stage

Attenuation di

Power dissipation

Stage output power

1st 2nd 3rd Cumulated values

2 dB 3 dB 15 dB 20 dB

22.14 W 18.93 W 18.33 W 59.40 W

37.86 W 18.93 W 0.60 W (28 dBm)

R1

R1

Input

R3

R3 R4

R2

1st Stage

G Equivalent generator

R5

2nd Stage

S11 Z0

R6

S21

Output R5

3rd Stage

S22

S12 High-power attenuator

Z0 Power sensor

Figure 12.6 Implementation of the high-power attenuator.

Assuming a source/load impedance of Z0 = 50  and ideal matching S11 = S22 = 0, resistors R1 to R6 in Figure 12.6 can be calculated as follows: R1 = Z 0

1 − 10−d1 /20dB 1 − 0.794 = 5.73  = 50  −d /20dB 1 1 + 10 1 + 0.794

R2 = Z 0

2 · 10−d1 /20dB 2 · 0.794 = 215.24   2 = 50  −d /20dB 1 − 0.63 1 − 10 1

(12.10)

R3 = Z 0

1 − 10−d2 /20dB 1 − 0.708 = 50  = 8.55  −d /20dB 2 1 + 10 1 + 0.708

(12.11)

R4 = Z 0

2 · 10−d2 /20dB 2 · 0.708 = 141.93  2 = 50   −d /20dB 1 − 0.50 2 1 − 10

(12.12)

1 + 10−d3 /20dB 1 + 0.178 = 50  = 71.63  1 − 10−d3 /20dB 1 − 0.178 2  1 − 10−d3 /20dB 1 − 0.032 = 136.14  = 50  R6 = Z 0 −d /20dB 3 2 · 10 1 − 0.178 R5 = Z 0

(12.9)

(12.13) (12.14)

578

Amplifier measurements

Transmission lines between individual stages can be used to distribute the attenuators on the heat sink. The characteristic impedance of these interconnections should be Z0 . In contrast, connections within a single stage should be as short as possible to avoid any unwanted impedance transformation. The mechanical dimension of a single stage is the limiting factor on its maximum frequency. A compromise between RF performance and thermal requirements must be found. The power dissipation of a single stage is shared between its resistors. Exactly how this is done depends on the attenuation value and the source/load impedance. The worst-case scenario needs to be considered: a source impedance of 0  (equal to doubled input voltage) and simultaneously a load impedance of 0  or ∞  (depending on the resistor to be considered). However, not all commercially available attenuators can be assumed to comply with this worst-case dimensioning. Therefore, source and load mismatch must be kept within specification when applying the maximum rated power to an attenuator. Self-heating of the attenuator may cause a temperature drift if improper resistor material is used. An attenuator input reflection coefficient S11 very close to 0 is a further prerequisite for low measurement uncertainty. Its role can be compared to  L of equation (12.8). The attenuator’s output reflection coefficient S22 is not as critical if the power sensor is well matched and the attenuation S21 is somewhat greater than 15 dB. The frequency response of S21 ( f ) can be measured by a network analyzer. But the small-signal values typically obtained from such measurements are not valid for high-power operation. A compromise to partially mimic the high-power scenario is to use a DC-bias that provides the necessary power to the attenuator under test and to simultaneously measure the frequency response using the network analyzer. Based on these measurements a calibration factor K( f, Pm ) dependent on the frequency and measured power can be calculated. High-power measurements with an attenuator have some drawbacks: 1. The measurement range is limited to approximately 1 kW, while liquid-cooled dummy loads are available up to approximately 300 kW. 2. No in-circuit test using the original operating load is possible. 3. Monitoring mismatch to detect critical load situations is not possible. This is why directional power sensors have been developed. Versions with a measurement range up to several kW are available. As shown in Figure 12.7, these sensors are connected between source and load to measure the power flow in both directions. The built-in high-power dual-directional coupler provides a small fraction of incident power Pi and reflected power Pr to separate power sensors. A typical directional power sensor exhibits an insertion loss of less than 0.5 dB between its RF connectors. For frequencies below 100 MHz, a more compact lumped-coupler design by Buschbeck [2] or further developments [3] are mostly used. VSWR bridges are not recommended because of their significant insertion loss of 6 dB. Due to the coupling effect, directional power sensors are limited in bandwidth, covering a range of one octave to about two decades.

12.2 Power measurements

579

Pr Pi G Directional coupler

Generator

Dummy load or antenna

Secondaryline terminations and frequencyresponse compensation Rectifier

V~Pi To power meter

V~Pr

Figure 12.7 Application of a directional power sensor [1].

A directional power meter (also called power reflection meter) is used to operate the power directional sensor. It involves automatic functionality for calculating the magnitude | L | of the load reflection coefficient from formula (12.2). It can also convert this value to the voltage standing wave ratio VSWR. VSWR =

1 + | L | 1 − | L |

(12.15)

The mismatch uncertainty of terminating power sensors (see Section 12.2.2) can be overcome. The reflection coefficient at the RF ports of the directional power sensor and its insertion loss are usually negligible. But there are two effects introduced by the directional coupler: 1. The electrical length at the reference plane where the directional power sensor is inserted will change. As a consequence, the phase relations compared to the operating conditions without the sensor will not be the same. This can lead to significant power changes if the generator and load are mismatched. Built-in couplers that remain in the circuit are one solution. 2. The coupler’s capability to separate incident and reflected power is limited by its directivity D (for details, see Section 12.3.2).

12.2.4

Power measurements using a spectrum analyzer Spectrum analyzers measure the power density spectrum. Integrating the power density spectrum over a specific frequency range can be done to identify the power present in this range. The following properties of spectrum analyzers are significant:

580

Amplifier measurements

1. The measurement is performed based on a heterodyne concept with a selectable resolution bandwidth (e.g., 1 Hz to 40 MHz). As a consequence, the dynamic range is far beyond that of power sensors. 2. Spectrum analyzers are able to unambiguously correlate a specific receive power to a specific frequency. Techniques such as a high first IF or a tracking filter for higher frequencies are involved here. But the use of additional harmonic mixers to extend the frequency range leads to image reception and spurious responses. 3. Spectrum analyzers exhibit a quasi-continuous, or seamless, sweep. They are designed so that the power displayed as a measurement point involves the power spectral density toward its adjacent points. This makes them different from the receivers of vector network analyzers and prevents the user from “overlooking” spectral components hidden between the measurement points. 4. Supplementing the spectrum analyzer with a precision power splitter and a power sensor helps to yield the advantages of both instruments. This can, for example, lead to a measurement uncertainty of <0.1 dB even at low levels. Spectrum analyzers can be implemented in other ways such as the following, but dynamic range will be reduced as a result: 1. A direct receiving concept consisting of a tunable bandpass filter, a preamplifier and a detector. 2. For low frequencies, an FFT analyzer working like a digital oscilloscope but with an integrated FFT algorithm that computes the power spectral density from a set of recorded time domain samples can be used.

12.3

S-parameter measurements In the microwave range, neither current nor its phase shift can be accurately measured. Fortunately, wave quantities and S-parameters are widely accepted and can be measured very precisely as described in this section.

12.3.1

The concept of S-parameters The wave quantities, sometimes referred to as (normalized) voltage waves, are assigned the measurement unit of square root of watt. A distinction is made between three different wave quantities on a two-port device (see Figure 12.8): r incident wave a1 (propagating from the source toward the DUT); r reflected wave b1 (reflected at the DUT traveling back to the source); r transmitted wave b2 (propagating from the DUT’s output to a load), If the two-port device is operated in reverse direction, a2 becomes the incident wave and b2 the reflected wave and b1 the transmitted. If the DUT is a one-port device, there is no transmitted wave.

12.3 S-parameter measurements

581

b2

a1 s21

G s11 Generator

a2

b1

Perfect match

Two-port DUT

Pi

Pt

Pr Two-port DUT

Figure 12.8 A two-port DUT operated in forward direction.

The incident power Pi , the reflected power Pr and the transmitted power Pt in Figure 12.8 can be calculated from the corresponding complex wave quantities Pi = |a1 |2

(12.16)

Pr = |b1 |2

(12.17)

Pt = |b2 |2

(12.18)

The following discussion in Sections 12.3 and 12.4 is based on a small signal description assuming a linear circuit model. Therefore, a linear relation between wave quantities can be assumed. The complex scattering parameters (S-parameters) s11 , s12 , s21 , and s22 are defined as the ratios of the respective wave quantities assuming that only one of the ports is stimulated (according to the operation direction) and all others are terminated by a perfect match (i.e., am = 0).  bi  sik = ak  am = 0 ∀ m = k

(12.19)

In contrast to Figure 12.8, real-world circuits do not exhibit a perfectly matched environment, therefore operation in forward and reverse direction appears simultaneously. This can be described by a superposition of both single directions, leading to the following matrix equation. 

b1 b2





s = 11 s21

s12 s22



a1 a2

 (12.20)

For one-port devices, formula (12.20) simplifies to the complex product b = L · a using the reflection factor  L introduced in equation (12.1).

(12.21)

582

Amplifier measurements

G Generator s31

1

a1 2

b2

s22

a2

a DUT

3 Power meter

Power sensor

DUT

b3

b DUT Γ DUT

Directional element

Figure 12.9 Scalar reflection measurement.

12.3.2

Scalar network analyzers and their limitations Directional elements exhibit dedicated transmission directions and decoupled signal paths. As shown in Figure 12.9, they can be used to perform scalar reflection measurements. The directional element in Figure 12.9 is fed at its input port 1 by a generator and connected to a power sensor at its isolated port 3. Its port 2 is connected to a DUT that is either a one-port device or a two-port device which should be terminated by a match. The magnitudes of the incident wave |a1 | and of wave |b3 | can be calculated from the generator’s power setting and from the power meter’s indication, respectively, using formulas (12.16) and (12.17). Following the signal path from the generator to the power meter, three observations can be made: 1. The directional element functions as a roundabout, forwarding a1 to b2. 2. The DUT reflects a portion of its incident wave aDUT (= b2 ) as bDUT (= a2 ). 3. The directional element again functions as a roundabout, forwarding a2 to b3. The measured value |M|, which is limited to the magnitude information due to the scalar setup, is defined as |M| =

|b3 | |a1 |

(12.22)

For steps (1) and (3) above, transmission coefficients s21 and s32 of the directional element must be considered. These coefficients form a complex quantity called reflection trackingR = s21 · s32 . Using R, a very simplified relation between the unknown reflection coefficient  DUT and the measured value M can be stated. M = R · DUT

(12.23)

Due to the scalar setup, only the magnitude information |R| is accessible. Therefore, the DUT is replaced by an open standard ( DUT ≈ +1) and the measured value |M| is stored as |R|. Formula (12.23) is then resolved for |DUT |, yielding: | DU T | = |M| / |R|

(12.24)

12.3 S-parameter measurements

583

Γ –3 dB

–3 dB –6 dB –9 dB –12 dB –15 dB –18 dB –21 dB

1 GHz 1.5 GHz

2 GHz

2.5 GHz

3 GHz

3.5 GHz 4 GHz

Figure 12.10 A scalar measurement of a short standard after reflection normalization.

This method is also called reflection normalization. It was applied in Figure 12.10, and a short standard ( L ≈ −1) was selected as the DUT. Obviously, a ripple of approximately ±1.8 dB occurs at the trace, which differs from the operator’s expected constant value of approximately 0 dB corresponding to | L | ≈ 1. This occurred because the directional element does not provide a perfect match s22 = 0 at its port 2 (see dashed signal path s22 in Figure 12.9). The quantity s22 is commonly referred to as “test port match S.” To obtain the trace of Figure 12.10, a directional element with a test port match of S = 0.2 was used. In conjunction with highly reflective DUTs like the open or short standard, the test port match S causes multiple reflections between the device and the directional element. This effect is not covered by reflection tracking. Equation (12.23) must be expanded as follows: M = R·

DUT 1 − S · DUT

(12.25)

Although the operator may only be interested in the magnitude information | DUT |, complex numbers for R, S, and M are necessary in order to resolve formula (12.25) for | DUT |. This cannot be achieved by using a scalar setup. Therefore, a test port match S = 0 cannot be compensated for in this context. Another parasitic effect in Figure 12.9 is that the decoupled signal path from port 1 to 3 is not completely isolated (dashed S-parameter s31 ). This means that the measurement functionality is bypassed with s31 . To compare this to the desired behavior of the directional element, a ratio known as directivity D is introduced. D=

s31 R

(12.26)

Amplifier measurements

Directivity Test port match

30 dB

20 dB

–4 40

dB

–3 10 dB

50

–2

dB

14 dB

–1 2 0

d 26 d B B

0

dB

1

26 dB B 20 d B d 4 1

2

10

Measurement uncertainty (dB)

584

50 dB

3

10

20 Measured return loss (dB)

dB

dB

dB

0

40

30

20

4

30

40

Figure 12.11 Measurement uncertainty as a function of directivity, test port match, and measured

value [4].

With the directivity D formula (12.25) can be expanded to  M = R·

DUT D+ 1 − S · DUT

 (12.27)

The superposition of the directivity D can be resolved only if the directivity and other values are vectorially known (as complex numbers) which is not provided by a scalar setup. If a match standard with reflection coefficient | M |  |D| is connected as the DUT and R ≈ 1 is assumed, the magnitude information of the directivity will be measured as |M| = |D|. Within the scalar setup, magnitude values of directivity D and test port match S are used in order to estimate the measurement uncertainty. The test port match limits the measurement accuracy for high-reflection DUTs, whereas the directivity D limits the measurement accuracy for well-matched devices. To keep the measurement uncertainty within a practicable range, D should be 10 dB better than the measured value M. Assuming a live example with a measurement value |M| of 20 dB, a directivity |D| of 30 dB and a test port match |S| of 10 dB, the operator uses Figure 12.11 to state the expected range of the value | DUT | as 17.6 dB to 23.3 dB (calculated from 20 dB – 2.4 dB = 17.6 dB and 20 dB + 3.3 dB = 23.3 dB). As a second example, if the measured value is |M| = 2 dB, Figure 12.11 would then lead to | DUT | from 0 dB to 3.6 dB (calculated from 2.0 dB – 2.0 dB = 0 dB and 2.0 dB + 1.6 dB = 3.6 dB).

12.3 S-parameter measurements

585

Table 12.4 Typical implementations of the directional element

Implementation

Frequency range

VSWR bridge

2–3 decades of 40 kHz to 4 GHz wideband 1 GHz to 40 GHz

Planar directional microstrip coupler Asymmetric coaxial to strip line coupler Wave guide directional coupler Lumped-element coupler Circulator

less than one octave of 400 MHz to 18 GHz less than one octave of 350 MHz to 500 GHz less than one octave of 50 MHz 1 GHz less than one octave of 500 MHz to 40 GHz

Insertion Coupling loss s21 loss s32 (typ.) (typ.)

Test port match S (typ.)

Directivity Max. power D (typ.) rating (typ.)

6 dB

>20 dB

>38 dB

0.5 W

<0.5 dB 10 dB to 30 dB

>16 dB

>18 dB

1 W to 10 W

<0.3 dB 20 dB to 40 dB

>15 dB

>10 dB

several kW

<0.5 dB 10 dB to 60 dB

>28 dB

30 dB

<3 dB

>16 dB

>16 dB

50 W to 100 kW depending on frequency 1 W to 10 W

>16 dB

20 dB

2 W to 100 kW

6 dB

3 dB to 25 dB <0.5 dB <0.5

Table 12.4 provides a typical frequency range, test port match S and directivity D for several directional elements. The values stated as insertion loss and coupling loss can be added together to yield the reflection tracking R. A coupling of 3 dB is possible for most of the devices but, as shown with the lumped-element coupler, it would lead to an insertion loss of 3 dB or more, which is not acceptable when performing power amplifier testing. To perform scalar transmission measurements, a signal generator is connected to the input of the DUT and the power sensor is connected at its output. Usually, transmission normalization is carried out using a through-connection instead of the DUT and by storing the measured power as a reference value and normalizing all further measurements to this value. If the generator output match (source match  1 ) or the matching of the power sensor (load match  2 ) is not sufficient or if the DUT exhibits reflection coefficients s11 or s22 with a magnitude close to 1, multiple reflections at the DUT’s input or the output will occur. This is described by the following formula, where M represents the measurement result of the transmission coefficient s21 .     1 −  1 2   |s21 | (12.28) |M| =  (1 − 1 s11 ) (1 − 2 s22 ) − s12 s21 1 2  To compensate for the effect of  1 = 0 and  2 = 0, both quantities and all S-parameters of the DUT have to be known vectorially. But this information can not be provided by a scalar measurement setup. The only possibility to improve the measurement uncertainty is to keep the reflection factors  1 and  2 as small as possible (e.g., by adding attenuator pads or circulators to the measurement setup). Equation (12.28) can be used to estimate the worst-case measurement uncertainty.

586

Amplifier measurements

Typical pseudo response –20

Measurement result using a setup with power sensors

–40 –60 –80 –100

Measurement result using a vector network analyzer or a spectrum analyzer with a (tracking) generator

–120

Start 2 GHz

Stop 6 GHz

Figure 12.12 A high-rejecting bandpass filter measured in different ways.

Typically, reflection measurement values are not below –40 dB because of unavoidable parasitic reflections. However, transmission measurements range from approximately +40 dB (amplifier) to –130 dB (total isolation with leakage of shielding). This dynamic requirement cannot be covered by a power sensor. If a simple bandpass filter is to be tested, a power sensor’s dynamic range of approximately 40 dB may just be sufficient. But all signal generators exhibit spurious and harmonic products in their output signal. Typical suppression values for these unwanted spectral components are 20 dBc to 50 dBc depending on the spectral component and the generator. If the generator is operating above the upper corner frequency of the bandpass filter (DUT), a subharmonic component of the generator can find its way through the filter (DUT) and cause the power sensor to measure a pseudo response such as shown in Figure 12.12. This is usually not acceptable because the DUT may be examined for unwanted side lobes of its transmission behavior, which would result in a similar effect on the trace. The considerations can be extended to harmonic components of the generator and a generator operation below the lower corner frequency of the DUT (not shown in Figure 12.12). A spectrum analyzer, due to its narrow-band reception, can be used to avoid these problems. A very compact solution is a spectrum analyzer with a built-in tracking generator especially designed for these needs. It can be supplemented by a directional element to do reflection measurements as well. But the setup has to be disconnected and reassembled several times to measure all four S-parameters, and the drawbacks stated for scalar measurements by equations (12.27) and (12.28) still remain. To overcome these problems a vector network analyzer (VNA) is required even if only the S-parameter’s magnitude information is of interest.

12.3.3

Vector network analyzers Measuring not only the magnitude of S-parameters but also their phase offers several benefits such as applying system error correction, the usage of embedding and

12.3 S-parameter measurements

587

Receiver attenuator Measurement channel b1 Reference channel

a1

Test port 1 LO

Stimulus generator

G

Generator attenuators

DUT Test port 2

Reference channel

a2

Measurement channel b2

Generator and receivers

Receiver attenuator

Test set

Figure 12.13 A bidirectional two-port VNA.

de-embedding, representation in the Smith chart, calculation of group delay, time domain transformation and others. The fundamental blocks of a conventional VNA are shown in Figure 12.13. Depending on the measurement direction, the stimulus generator is either routed toward port 1 or 2. The incident wave is tapped to generate a reference channel (e.g., by a power splitter). At the test ports, the separation of incident and reflected wave is done by a directional element (see Section 12.3.2). This complete part of the instrument is called the test set. Its implementation depends on the frequency range (coupler versus VSWR bridge), the reference impedance to be used (50 , 75 , or others), and the possibility to handle signals with superimposed DC (active test set) or no DC (passive test set). Measurements performed include frequency sweep, power sweep, or time sweep (CW stimulus). To implement a coherent down-conversion, a common local oscillator (LO) is distributed to all receivers (see Figure 12.13). This means that all the measured wave quantities will have added a common phase shift which is caused by the phase difference between the LO- and RF-generator. When the VNA calculates the raw S-parameters, the common phase shift cancels out, as can be seen from equation (12.19). With standard S-parameter measurements, only one port is fed by the stimulus generator. It is then called the active test port while the other test ports are kept passive (ideally sending no incident wave to the DUT). Assuming that port 1 is the active port, formula (12.19) would lead to the raw S-parameters s11 and s21 . After this partial measurement (forward measurement) is finished, the source switch is changed and the other port becomes the active port. This reverse measurement reveals the S-parameters s22 and s12 . Optional receiver step attenuators (Figure 12.13 dashed) can be used to extend the instrument’s 1 dB compression point, so that precise measurements can be done up to typically +27 dBm power level (e.g., measurements of medium-power amplifiers). The optional generator step attenuators (Figure 12.13 dashed) extend the output

588

Amplifier measurements

aG2

Error two-port G e10 bG1 a1

Reference plane s21

b2 aH1

Error two-port H e32

bH2

DUT e00

e11

bG2

s11

e01

e22

s22

e33 aH2

a2 bH1

aG1 b1 s12

e23

Error network

Ideal vector network analyzer

Figure 12.14 The seven-term error model [4].

power range down to about −120 dBm, e.g., to analyze low-noise amplifiers. Modern VNA architectures involve more than just a single stimulus generator so that advanced measurements such as hot S-parameters are possible (for details, see Section 12.5.5). The source switch is able to route more than just one port. These modern VNAs came with four, six or eight ports. In certain applications (e.g., hand-held instruments) the opposite goal, a simplified VNA architecture, is desired. As a consequence, reduced performance must be accepted (some of the important drawbacks are stated in brackets): r a VNA with only one common reference channel, obtained between stimulus generator and the source switch. (seven-term calibration cannot be used); r a unidirectional VNA that has only one active port, whereas the other ports do not exhibit any directional elements or reference receivers. (The load mismatch at the passive ports can generally not be corrected by means of system error correction.); r a multiport configuration that is built by a two port VNA and a switching matrix to interface to a multiport DUT with N > 2 ports. (Extended sweep time, reduced performance for dynamic range, directivity and test port match). A detailed discussion on VNA architectures can be found, for example, in reference [4] p. 22.

12.3.4

Introduction to system error correction Within the context of VNAs, systematic errors can be compensated for. Besides the parasitic effects of R, S, and D of the directional element discussed in Section 12.3.2, this technique also covers systematic errors introduced by the receivers and other parts of the VNA. To point out this extended coverage, R, S, and D are dropped and the error terms e00 , e01 , . . . , e33 have been introduced. They form an error model (see Figure 12.14). The real-world VNA can be separated into an ideal VNA and an error network.

12.3 S-parameter measurements

589

The topology of the error network varies: the three-term model only applies to oneport measurements (no error two-port H). The seven-term term model can only be applied if each test port has its own reference channel (state-of-the-art). It exhibits eight error terms eij . One of these parameters (which should not be equal to zero) can be used to normalize all the parameters (here, e32 is used and, therefore, e32 = 1). This means that the seven-term error model contains seven independent error terms, hence its name. A suitable calibration technique must be performed to determine the error terms. Afterwards, system error correction will compensate for the error twoports G and H. The seven-term error model applies to many calibration techniques. The calibration technique defines the standards (see Table 12.5) that must be used to perform the calibration. During calibration the VNA measures the complex S-parameters of the calibration standards and compares them to the complex characteristic data provided with the standards. Finally this yields the complex values of the error terms. These terms are sometimes called the VNA’s raw system data. Table 12.6 provides a glimpse of some typical raw system data. Its last two columns list the reference to the 7-term model. Applying system error correction means that the error two-ports G and H are removed from the measurement results and the S-parameters become referred to the reference plane. Due to unavoidable uncertainties, residual systematic errors (referred to as effective system data) will remain (for details, see Section 12.3.8). It is useful to name the calibration techniques based on the first character of the standards involved and to unambiguously define the sequence of these characters. Through tradition other names have crept in (see row titled “Other names” in the following overview).

12.3.5

Calibration with different connector types Numerous coaxial connectors and waveguide flanges of all kinds are available featuring individual benefits. An overview of typical coaxial connectors is provided by Figure 12.15 and Table 12.8; more details can be found in reference [5]. A power amplifier may use diverse connector types on its RF ports (e.g., port 1 SMA and port 2 N connector). This type of DUT is often called a noninsertable device. A calibration strategy is required that deals with this situation:

Strategy 1: adapter inserted after calibration One approach that can often be seen but offers reduced precision is one in which the adapter is inserted after calibration and approximately compensated for by its insertion length. In our example, it means that calibration takes place at two SMA compatible test ports 1 and 2 (see Table 12.8 for compatibility). However, there are no SMA calibration kits available, just a PC3.5 calibration kit that has the same reference plane and is mechanically compatible and can therefore be used. After calibration has been completed, a suitable adapter from N to SMA is inserted. The adapter’s insertion length is the electrical distance between its two reference planes. In other words, it is the length that has been introduced by the adapter. Its phase shift can be compensated

590

Amplifier measurements

Table 12.5 Typical calibration standards Standard

Char

Explanation and parametric description

Short standard

S

Open standard

O

Match standard

M

Sliding match

M

Through

T

Unknown through Reflect

U

Line standard

L

Symmetrical network

N

Attenuator

A

Using coaxial and waveguide technique, this standard can be built with nearly ideal total reflection || = 1. Its reflection coefficient is thus dependent only on its length offset l. Standards featuring a frequency range >24 GHz may come up with polynomial coefficients L0 , L1 , L2 , and L3 for characterizing their parasitic inductance. This standard exhibits a length offset l and parasitic fringing capacitances, which are characterized by a set of polynomial coefficients (C0 , C1 , C2 , and C3 ). The open standard cannot be realized in waveguide systems. It is then usually “replaced” by an offset short. This precise broadband impedance is matched to the system impedance. In the past, it was commonly assumed to be ideal ( = 0) and was not modeled. If it is supplemented with characteristic data then the precision can be raised close to that achieved by a sliding match. An air line with specified characteristic impedance can be manufactured more accurately than a broadband match. A cylindrical ferrite rod that is introduced into the air line absorbs a large portion of the magnetic energy starting from a minimum frequency of approximately 2 GHz. If the ferrite rod is moved along the line, the length offset and therefore the phase changes but the magnitude remains nearly constant. Operators typically orient themselves on the marks on the sliding match. The corresponding reflection coefficients lie on a circle around the air line’s characteristic impedance. The through is a two-port standard that allows a suitable low-loss connection of both test ports. It is characterized by its delay or electrical length, its loss and its characteristic impedance. In some cases (e.g., sexless connector system), a direct connection of test ports with electrical length 0 mm is permissible. Any two-port whose S-parameters fulfill the reciprocity condition (s21 = s12 ) can serve as an unknown through. This one-port has a reflection coefficient of || > 0. The exact reflection value is not needed. However it must be identical at both test ports. To characterize the standard, its behavior at low frequencies is classified as more capacitive (Im{}< 0) or more inductive (Im{}< 0). The electrical length is relevant if it alters the classification at higher frequencies. In coaxial systems, this two-port standard is implemented as an air line. Its characteristic impedance has to be well matched to the system impedance. The difference in electric length between through and the line standard must not be equal to an integer multiple of half of the wavelength. Start versus stop frequency is therefore restricted to 1:8. This can be overcome by using multiple lines and a fixed match for lower frequencies. This two-port has symmetrical reflection coefficients s11 = s22 = 0 and any transmission coefficient, even 0 or 1. Similar to the reflect standards, a classification for more capacitive or more inductive is necessary. This two-port standard has to be well matched on both sides. Unlike the through, it should have an unknown insertion loss which is in the range 10 dB to 55 dB.

R

12.3 S-parameter measurements

591

Table 12.6 Typical raw and effective system data of a VNA

System data

Raw system Effective data system data

Forward measurement

Reverse measurement

Reflection tracking Directivity Source match Transmission tracking Load match

≤2 dB ≥29 dB ≥22 dB ≤2 dB ≥22 dB

e10 e01 e00 e11 e10 e32 e22

e23 e32 e33 e22 e01 e23 e11

≤0.04 dB ≥46 dB ≥39 dB ≤0.06 dB ≥44 dB

Note that directivity e00 , e33 in this table and directivity D in Section 12.3.2 are defined differently. D = e00 − (e10 e01 ) or D = e33 /(e23 e32 ). The error terms e00 and e33 are similar to s31 of Figure 12.9.

(a)

(b)

(c)

(d)

(e)

(f)

Figure 12.15 Typical coaxial RF connector types (for a, b, c, . . . , see Table 12.8).

for by an offset length assigned to test port 2. The offset length has to be increased because of dielectric inner conductor support or discontinuities between the inner and outer conductor. An alternative is to mount an N-type short standard on the open end of the adapter to use the auto length functionality of the VNA to obtain an estimated overall length. Taking into account the offset length of the N-type short, the adapter’s insertion length can be calculated and the length offset can be modified accordingly. Nevertheless, strategy 1 does not compensate for the frequency-dependent attenuation of the adapter and is therefore limited in frequency range. The s11 and s22 of the adapter have a significant influence on the test port match and the directivity obtained (for a similar discussion, see s11 and s22 of the attenuator used in Section 12.3.7). If available, a high-quality adapter from a calibration kit should be chosen.

Strategy 2: UOSM calibration with mixed test port types The adapter is mounted prior to calibration, and calibration will therefore compensate for it. A suitable calibration kit is required for each of the connector types involved. The calibration kit must include, at a minimum, the standards that are needed for oneport calibration. In addition to the adapter that has been mounted at test port 2, a second adapter to be used only during calibration is required. The purpose of the second adapter is to establish the unknown through. This adapter does not have to feature good matching. It merely has to satisfy the reciprocity condition (s21 = s12 ). To ensure proper results, the second adapter’s insertion loss should not exceed 20 dB. Strategy 2 even

592

Amplifier measurements

Table 12.7 Properties of the various calibration techniques [4] Calibration Technique Other names Error model DUT type Suitable for transmission measurements No band limitation due to singularities Indirect plausibility check Partially unknown standards Consideration of DUT depended cross talk Usage of standards with different gender Suitable for noninsertable DUTs Possible usage of sliding match Well-suited for on-wafer measurements Effective directivity attained Number of receivers in N-port VNA Minimum number of calibration standards Contacts3 in two port VNA

OSM SOL,OSL 3-term one-port

✓

TOM TRM TRL OLT LRM1 LRL1 7-term two-port or multiport ✓ ✓ ✓

TNA TAN

UOSM TOSM SOLR SOLT 12-term

✓

✓

✓

✓

✓

✓

✓

✓

✓ ✓

✓

✓

✓

✓

✓2

✓2

✓2

✓

✓

✓

✓

✓ ✓

✓

✓

✓ ✓ ✓

✓

+ N+1 3

+ 2N 3

+ 2N 3

+++ 2N 3

+ 2N 3

+ 2N 4

+ N+1 4

3

6

6

6

6

8

8

The through (which may exhibit a length l = 0) is replaced by a line standard l > 0. Assuming that the standards produce symmetrical reflections. 3 The number of “contacts” is used to assess the amount of work involved in the calibration procedure. By contact, we mean setting up an electrical connection. For example, mounting a one-port standard requires one contact. Mounting a two-port standard requires two contacts. 1 2

works with frequencies above 40 GHz (if the connectors involved are suitable for these frequencies) or with adapters between media (e.g., coaxial to waveguide or coaxial to coplanar), which usually exhibit greater frequency-dependent behavior than intercoaxial adapters. Strategy 2 can even be used to characterize the unknown through and to store its S-parameters. Once characterized, the second adapter can be used in strategy 4 or 5.

Strategy 3: adapter removal technique The UOSM calibration technique is based on a seven-term error model. Vector network analyzers that exhibit a reduced architecture with a common reference channel cannot be described by the seven-term error model. A calibration technique based on the 12-term model and referred to as the adapter removal technique has to be used instead of strategy 2 (details may be found in operating manuals of older VNAs that have been based on a three-receiver architecture).

593

12.3 S-parameter measurements

Table 12.8 Typical coaxial RF connector types and their properties

Connector type

Figure

fmax GHz

Z

Mechanically compatible with

Ttyp 2 Nm

7/16 DIN 14 mm

a –

7.5 GHz 8.5 GHz

50 50

– –

25.0 4.0

N

b c

7 mm SMA PC 3.5 2.92 mm (K)1 2.4 mm 1.85 mm (V)1 1.00 mm

– d e – – f –

50 75 50 75 50 50 50 50 50 50 50

–

BNC

18 GHz 4 GHz 4 GHz 1 GHz 18 GHz 18 GHz 34 GHz 40 GHz 50 GHz 67 GHz 110 GHz

1 2

– – 3.5 mm; K SMA; K SMA; 3.5 mm 1.85 mm 2.4 mm –

1.36 – 1.36 0.56 0.90 0.80 0.90 0.90 0.45

Note high power high power sexless medium power bayonet coupling sexless – – – – – –

The names “K Connector,” “V Connector” are trademarks of Wiltron/Anritsu Corporation. The torque Ttyp can vary between manufacturers.

Strategy 4: de-embedding the adapter As in strategy 1, the adapter is mounted on test port 2 after calibration. In strategy 4, however, all four S-parameters of the adapter are available as a function of frequency and entered into the VNA (e.g., by data file). A technique called de-embedding is applied to port 2. This technique is internally based on a transmission matrix calculus. It compensates the adapter in a more precise way than is done in strategy 1. Within the relevant frequency range, the transmission characteristic of the adapter should not exhibit any zeros or any attenuation values above 20 dB. This is due to signal-to-noise aspects. The advantage of strategy 4 is that once the through is characterized, no second calibration kit (N-connector in the example here) is necessary. Plus, the user may choose any calibration technique preferred (e.g., the one-path, two-port technique suggested in Section 12.3.7). But the VNA is not informed if the adapted port is connected to a dispersive media (e.g., waveguide), which would be necessary in some cases.

12.3.6

Calibration with PCBs, test fixtures, and wafer probers With printed circuit boards (PCB), an adaptation of their microstrip design to the coaxial connectors of the VNA is necessary. This can be achieved by using SMA connectors and a test PCB as shown in Figure 12.16 left. This test board carries all calibration standards necessary to perform several calibration techniques and two bays for inserting one-port or two-port DUTs. The fringing capacities at the open end of the microstrip line and the parasitic inductances introduced by the ground vias of the short and match standard have to be calculated by an EM solver or using [6, 7]. The microstrip lines are

594

Amplifier measurements

l Cross section with fringing capacitances

Open Via Short Via + 100Ω Match

Equivalent circuit without DUT

Via + 100Ω One-port DUT Through

Cross section with Two-port DUT 2l Two-port DUT Ground (Amplifier)

DUT

(Bias)

l

l Two-port DUT with capacitances

Line standard 2l

x

Figure 12.16 Test PCB carrying microstrip calibration standards and DUTs bays.

designed to have a characteristic impedance of 50 . A minimum distance of l = 20 mm to 50 mm (depending on the wavelength) must be maintained on the PCB between the coaxial connector and the reference plane so that the higher modes that arise at the transition from the coaxial system to the PCB can fade away. If all of the standards are implemented with the same distance l and if the through-connection is made by a length of 2l, a length offset of 0 mm can be specified in the characteristic data of the standards. In this case, the bays of the DUTs must have exactly the same distances l from the SMA connectors in order to locate the reference plane at the component’s edge. For frequencies above 6 GHz, the TRL calibration technique is strongly recommended. The line standard can be characterized by its additional length x. To overcome the frequency restriction that comes with the value of x (see Table 12.5 row “line standard”), the match can be included in the TRL calibration to allow an extension down to 0 Hz. One-port devices can be measured in the one-port or two-port bay. In the first case, the parasitic inductance of the ground via may be relevant. Fringing capacities and parasitic inductance are dependent on the PCB material and via diameter, respectively. For universal use in electronic design automation tools, a characterization without these influences is required. The following guidelines are therefore recommended:

12.3 S-parameter measurements

595

1. Low-impedance one-port devices can be measured in the one-port bay as fringing capacitances will not have any significant influence, which means that it is sufficient to de-embed just the parasitic inductance of the via. In this special case, the location of the DUT and parasitic inductance can be assumed to be interchangeable (necessary for one-port de-embedding). 2. High-impedance, one-port devices and all two-port DUTs have to be measured in the two-port bay. Before mounting, the DUT measurements on the four S-parameters of the empty bay have to be carried out and the values of the parasitic capacitors and resistors have to be calculated (see Figure 12.16, right-hand side). After measurement, the parasitic component values have to be de-embedded. Substrates like Al2 O3 are very brittle, therefore connectors cannot directly be mounted on to them. A test fixture employed for these requires a reproducible contacting of the microstrip, coplanar or grounded coplanar waveguide. A test fixture typically has two clamping jaws that are placed on the front sides of the substrate. One of the jaws can be adjusted in both horizontal directions. This makes it possible to adapt the test fixture to different substrate sizes and also to handle diagonally arranged contact interfaces. The jaws consist of two strip-shaped ground contacts that squeeze the substrate. In the upper ground contact, an inner conductor is opened up to adapt to a coaxial line system. During calibration, different substrates with different standards are used. To ensure correct results, care must be taken to ensure that the inner conductor contacts the substrate at the proper position. Test fixtures generally have a mechanically rugged design, but their inner conductors do require careful handling. The TNA calibration technique is particularly well-suited for measurements using a test fixture. The primary benefit of this calibration technique lies in the minimum requirements that are placed on the properties of the standards. A microstrip calibration kit includes a straight 50  microstrip section with length 2l that is characterized as a through with length 0 so that l becomes the distance of the reference plane on both sides of the substrate. It also requires a symmetric network standard that can either be an empty substrate or the test fixture left opened without any substrate, and an attenuator standard which can be manufactured with extreme precision on substrates using thin-film technology with laser-trimmed resistors. To obtain the best possible interface to the coaxial system, a suitable ground connection must be provided at the transition to the substrate. In the case of on-wafer measurements, the circuits are not accessible from their backside; they are only accessible via their top side. To ensure a suitable ground connection at the contact point, coplanar waveguide (CPW) ground (G), signal (S), and ground (G) contacts are situated on the top of the wafer and have dimensions of less than 0.1 mm. A special micromechanical manipulator, referred to as a wafer prober, is necessary to contact the GSG pads. Characterized calibration standards are defined on a substrate known as an impedance standard substrate (ISS). The TRL calibration technique is awkward with wafer probers because of the multiple line spacing necessary to establish the through (T) and line (L) standard so the TRM calibration technique is preferred. The match standard necessary can be provided by laser-trimmed small resistors and modeled as a constant resistance with a series

596

Amplifier measurements

VNA Booster amplifier

Receiver and generator section of the VNA

Test port 1

Test port 1

Test port 1 Reference plane 1

to b1 channel Reference plane 1

Reference plane 1

SA22 S∏12 R

Power sensor

Reference plane 2

Reference plane 2 S∏21

Reference plane 2

S∏22

to b2 channel e33

to b2 channel

Test port 2

Test port 2

Test port 2

Configuration with reduced precision

Optimized high-power configuration

Optimized high-power configuration with boosted source

Figure 12.17 High-power setup with and without significantly reduced precision.

reactance. The through can be very short so that its matching is not a critical issue. The reflect standard need have no known properties and can be implemented with the probes in the air.

12.3.7

Calibration consideration for high-power setups With DUTs such as power amplifiers, the output power of the DUT may exceed the linear input range of the VNA. As an example, the test port input power should be kept below 0.2 W so as not to exceed the linear range of the VNA. Suppose the amplifier had an output power of 20 W, then a 20 dB attenuator pad between the amplifier output and test port 2 would be just sufficient enough to prevent any overdrive. However, this attenuator would have significant disadvantages as described below. The amplifier and attenuator can be described by their S-parameter matrix SA and Sπ , respectively. The VNA’s test port 2 is characterized using directivity D, test port match S and reflection tracking R. The reference plane of the measurement should be located at the input and output of the amplifier. This means that it is located prior to the attenuator and that the attenuator becomes part of the test set (see Figure 12.17, left). This combined test set at port 2 is described using directivity D , test port match S and reflection tracking R . During reflection measurements at port 2, the signal passes the reflection tracking (R), the 20 dB attenuator two times (sπ 12 = sπ 21 ), and the output reflection coefficient sA22 of the DUT (see Figure 12.17, left). The reflection tracking R is thus altered by the attenuator to R  = sπ2 21 · R.

(12.29)

12.3 S-parameter measurements

597

The test port match S revealed to the amplifier is dominated by the reflection coefficient sπ 11 of the attenuator because of its high attenuation (20 dB) i.e., S  = s11

(12.30)

The parasitic crosstalk e33 = R · D is a bypass to the measurement functionality of the directional element. In this case, an additional crosstalk path is formed by R · sπ 22 , thus contributing to the overall crosstalk. Obtaining the directivity D’ requires taking the quotient of the overall crosstalk R · D + R · sπ 22 and the reflection tracking R from formula (12.29). Thus, D =

R · D + R · sπ 11 D + sπ 11 = 2 R · sπ 21 sπ2 21

(12.31)

Using typical system raw data as stated in Table 12.6, and assuming an attenuator with a return loss of 20 dB and an insertion loss of 20 dB, the raw directivity is degraded by 33 dB which is the most unwanted effect of this setup. It is hardly possible to compensate this using a calibration technique because of influences like thermal drift, connector repeatability and phase stability of the cabling. There are two workarounds that can help. 1. If the output match of the amplifier needn’t be measured, then choose the one-path two-port calibration technique. It is a combination of a complete one-port calibration on test port 1 and transmission normalization. It is a unidirectional error correction which means that the same test port (test port 1 in this case) is always operated as active port. It does not correct any reflection at test port 2 and it does not correct for any multiple reflections caused by the attenuator. Therefore the attenuator should exhibit a return loss better than 25 dB in this case. 2. If information regarding the output reflection coefficient sA22 of the amplifier is needed, then choose a setup with an external directional element (see Figure 12.17 middle). The reference channel can be tapped inside the VNA as before, but the directive element is placed directly behind the power amplifier in order not to risk any degradation of directivity. An introduction on how to design the necessary highpower coupler can be found in reference [8]. Because it is only needed for the small operating frequency range of the amplifier, a circulator is often preferred instead of the coupler. Before the signal is fed into the VNA via an external receiver input, level adjustment has to be done using a second attenuator. In some respects the configuration can be compared to Figure 12.13 if the receiver and generator attenuators (dashed) are present, but the components of Figure 12.13 are designed for medium-power measurements. Power amplifiers typically require significant RF input power, more than can usually be provided by a VNA. A booster amplifier (see Figure 12.17 right) can be used to raise the source level. To make sA11 measurements, an external coupler is required for the measurement of channel b1 . If the linearity of the booster amplifier is not sufficient or if it exhibits drift effects then the reference channel a1 should also be monitored by an

598

Amplifier measurements

external coupler. This coupler (not shown in Figure 12.17) has to be located between the booster amplifier and the b1 -coupler. To control the actual input power to the DUT, a power calibration at reference plane 1 (using a power sensor) is strongly recommended. Afterwards, one of the calibration techniques described above has to be applied.

12.3.8

Residual errors and measurement uncertainties Every measurement result is subject to some uncertainty that characterizes the expected deviation of the measured value from the true value. According to reference [9], a distinction must be made between two types of uncertainty: Type A is caused by random measurement errors, while type B is generated by systematic errors and can be compensated for as shown in Sections 12.3.4 to section 12.3.7. Uncertainties of type A cannot be compensated for, but instruments are designed to keep them at a minimum. The following guidelines should be observed to minimize type A uncertainties: 1. A warm-up time should be observed to ensure that the equipment is operated in thermal equilibrium. Once the equipment has warmed up, an environment with a stable temperature helps to keep thermal drifts as small as possible. 2. Connectors are subject to wear. Using the applicable tightening procedure (torque wench, rotating the connecting nut but not rotating the connector) and careful cleaning reduce wear to a minimum. Regular inspections also involving a pin depth gauge help to detect faulty connectors. 3. The noise superimposed on the measured values can be reduced using a smaller IF bandwidth or increasing (if possible) the stimulus power. If the measurement or reference receivers are operated near their upper power limit, compression effects will occur and cause avoidable uncertainties. 4. Calibration techniques can be used to overcome systematic errors. Although a calibration is done in the correct manner, some small errors will remain. The calibration kit involved and the precision of its characterization are the primary factors with a modern VNA. Calibration kits are available with different capabilities and should be selected based on the accuracy requirements. The time intervals between calibrations should be kept according to influences such as stability of temperature, etc. The network analyzer settings used for calibration and measurement should vary only to a certain extent. The residual errors form an error model similar to that shown in Figure 12.14 but exhibit the effective system data e’ik instead of the error terms eik . For typical values, see Table 12.6. A distinction must be made between effective system data and faulty calibrations that arise as a result of operator errors, defective network analyzers and damaged standards. The implicit plausibility check provided in the TOM calibration technique helps to detect a faulty calibration early on in the process. The T-check (see [10]) and the Beatty standard serve the same purpose. A common misinterpretation is that the same set of standards used for calibration can be reconnected to detect faulty calibrations. In fact, this measurement only provides information about reproducibility. A second calibration kit providing other sets of the standards (not involved in the

12.4 Further linear measurements

599

calibration) can be used to detect faulty calibration. If the calibration is double-checked by measuring all standards of the second calibration kit, the effective system data e’ik of the present calibration can be calculated. But this verification would be based upon the characteristic data of the second calibration kit and the uncertainties of these data. Since these data items are normally in the same order of magnitude as the expected effective system data, this method is only of academic value. In practice, a verification kit has to be used. It involves standards that are especially designed to meet the high accuracy demands, e.g., air lines without the need for an inner conductor support, precision attenuators and mismatch standards.

12.4

Further linear measurements A vector network analyzer is mainly designed to perform S-parameter measurements. Based on these measurements further linear descriptions can be calculated, either by the operator or the analyzer (e.g., using trace mathematics).

12.4.1

Amplifier gain definitions The first step is to consider a simple circuit consisting of a source  S and a load  L . At the source, a distinction must be made between the following r available power PA , which is the maximum power that can be drawn from the source under power matching condition ( S =  L * ). The quantities PA and  S are sufficient to characterize the RF source by a linear model. r delivered power PD , which is the power transmitted to any arbitrary load considering the mismatch caused by source and load reflection coefficients (i.e., PA − PD = power lost due to mismatch). The next step is to consider an amplifier connected between an RF source with reflection coefficient  S and a load with reflection coefficient  L . The power flow diagram Figure 12.18 shows this scenario, using four important RF power definitions: r r r r

available power of the source PAS ; delivered power from the source PDS ; available power of the amplifier’s output PAO ; delivered power from the amplifier’s output PDO .

Based on the four power definitions, various amplifier gains can be stated. The transducer gain GT is an overall quantity that regards the mismatch at the input, the RF power added by the amplifier, and the output mismatch. Therefore, it is well suited for power optimization design techniques. The operating power gain GP and the available power gain GA disregard the input or output mismatch, respectively. The gain measured by a VNA is G0 = (s21 )2 or 20log(s21 ) dB in dB scale. This gain can be considered as the transducer gain GT under the constraint that the amplifier is embedded in an environment offering a port impedance exactly equal to the

600

Amplifier measurements

GP

Different gain definitions: GA GT RF power flow chart:

PDS

PAS

PAO Power loss due to mismatch at input

Power added by the amplifier

PDO

Power loss due to mismatch at output

Figure 12.18 Power flow and gain definitions of an amplifier.

system impedance Z0 (generally 50 ). Most amplifiers exhibit an input and output impedance that is notably different from Z0 . This means that mismatch will occur if they are directly connected to the test ports of a VNA. In order to operate the amplifier economically, the application circuits are designed to minimize mismatch, thus achieving the maximum possible transducer gain. A similar situation arises for the operating power gain GP and the available power gain GA . The values of the different gains GT , GP , and GA can be calculated from the amplifier’s S-parameters, the source reflection coefficient  S , and the load reflection coefficient  L if the amplifier behaves linearly as follows:    |s21 |2 1 − | S |2 1 − | L |2 PD O GT = = (12.32) PAS |(1 − s11  S ) (1 − s22  L ) − s12 s21  S  L |2   |s21 |2 1 − | S |2 PAO = GA = PAS |1 − s11  S |2 − |s22 −  S det(S)|2

(12.33)

  |s21 |2 1 − | L |2 PD O GP = = PDS |1 − s22  L |2 − |s11 −  L det (S)|2

(12.34)

where det(S) = s11 s22 − s21 s12 It should not be overlooked that formulas (12.31) to (12.34) are based on a linear assumption which makes them insufficient for strong nonlinear behavior, necessitating load-pull techniques (see Section 12.5.4) for accurate measurements. But the formulas do consider the fact that the matching condition of the output affects the input impedance of the amplifier and, vice versa, the input matching affects the output impedance. This is a consequence of the finite s21 s12 term. In some cases, if s21 s12 is small enough or if additional elements are used to neutralize the parasitic elements responsible for s12 = 0, the amplifier can be assumed as unilateral (s12 = 0). This means that input and output

601

12.4 Further linear measurements

–1 dB 0 dB cT 2 dB

rT

3 dB

Direction of (s22)∗

Figure 12.19 Example for constant gain circles of GL .

matching can be optimized independently of one another, and formula (12.32) can be split into three independent factors GT =

1 − | S |2 1 − | L |2 2 |s | · · if s12 = 0. 21 |1 − s11  S |2 |1 − s22  L |2     GS

(12.35)

GL

In this special case the source and load reflection coefficients that yield the maximum transducer gain GTMAX are given by the conjugate complex values of the amplifier’s input and output reflection coefficients. G T MAX =

1 1 · |s21 |2 · 2 1 − |s11 | 1 − |s22 |2

if s12 = 0,  S = (s11 )∗ , L = (s22 )∗ . (12.36)

The optimum value of the load reflection coefficient  L = (s22 )* can be marked in the  L -Smith chart as a single point (see Figure 12.19 point “3 dB”). If the factor GL of formula (12.35) is set to a specific value (e.g., GL = 1 equals 0 dB), then GL can be solved for  L . This leads to solutions in the form of a circles with the center located along the vector (s22 )* at a distance cT from the origin  L = 0. The circle’s radius is rT . cT =

rT =

G L |s22 | 1 + G L |s22 |2

  1 − G L 1 − |s22 |2 1 + G L |s22 |2

(12.37)

(12.38)

The same considerations are possible concerning factor GS of formula (12.35), i.e., replacing s22 by s11 and GL by GS in formula (12.37) to (12.38). The insertion gain is a figure of merit that compares the situation of the source and load connected without the amplifier to the situation with the amplifier in between. The

602

Amplifier measurements

insertion gain GINS is defined as the ratio of the power PDO that is delivered at the amplifier’s output to the load  L versus the power that is delivered from the source  S if the load  L is directly connected to the source. G INS =

|s21 |2 |1 −  S  L |2 |(1 − s11  S ) (1 − s22  L ) − s12 s21  S  L |2

(12.39)

For reflection coefficients  S =  L = 0, as occurs ideally with a VNA, the insertion gain becomes equal to G0 = (s21 )2 .

12.4.2

Efficiency factor Low power consumption is an important requirement not only for battery-operated power amplifiers but also because lost power is converted to heat. The efficiency describes the percentage of applied power that is converted to RF power. The drain efficiency is simply the ratio of the output RF power to the DC input power necessary to bias the amplifier. This definition does not consider the incident RF power that is fed to the amplifier’s input, and that may be a substantial value in the case of a power amplifier. The (PAE) is a more adequate measure. It is the ratio of the RF power added by the amplifier to the DC bias power. The RF power added is the difference between the power PDO delivered to the load at the output and the power PDS delivered to the amplifier’s input. The DC power is calculated from bias voltage v DC and bias current iDC using PDC = v DC · iDC . PAE1 =

PD O − PDS · 100%. PDC

(12.40)

An alternative definition of the PAE considers the amplifier’s input power using the available power PAS instead of the delivered power PDS , as a consequence this definition counts mismatch loss at the amplifier’s input as a degrading effect on the efficiency, which is more realistic. PAE2 =

|b2 |2 − |a1 |2 PD O − PAS · 100% = · 100%. PDC PDC

(12.41)

A VNA with an active test set can directly bias an active device through its test ports without the need for a bias network between test port and DUT. In this case, characterization of the active device can be done without a degradation in directivity and without the need for de-embedding the bias network. Modern VNAs have special DC measurement inputs for measuring the DC power consumption of the amplifier under test. The voltage v BS can usually be applied directly to these inputs. However, the current iBS must be measured indirectly as a voltage drop across a precision resistor. The efficiency can be calculated automatically from the DC measurements and the wave quantities. It should not be overlooked that nonlinear effects cause the efficiency of a power amplifier to be dependent on several parameters: 1. The PAE can be improved by optimized input and output terminations for fundamental frequency and higher-order harmonics. 2. The PAE typically reaches its maximum near the 1 dB compression point.

12.4 Further linear measurements

0 0

f0

f1

f2

603

f

τG

arg(s 21(f ))

Figure 12.20 Definition of the group delay.

3. The PAE depends on the operating frequency (similar to gain). 4. The PAE is strongly related to the bias conditions. A VNA offers frequency sweeps, power sweeps or CW sweeps helping to search for the best operating parameters. Optimizing the PAE experimentally over input and output impedance requires the load and source pull technique (see Section 12.5.4).

12.4.3

Linear distortion, phase and group delay measurement A two-port network is free of linear distortion in a specific frequency range f1 to f2 if it meets the following requirements in this frequency range: r constant group delay τ G in the interval f1 to f2 (see Figure 12.20); r constant magnitude of the transmission coefficient | s21 ( f0 )|. Under these circumstances, the group delay τ G is a measure of how long it takes the modulation components of a signal with frequency f ∈ [f1 , f2 ] to propagate through the amplifier. These spectral components can be observed in the time-domain as the envelope curve of the modulated signal. The group delay τ G is typically calculated from the transmission coefficient s21 . The group delay τ G ( f0 ) is defined as the slope of the phase arg(s21 ( f0 )) at the frequency f0 . This slope is scaled by the factor –1/(2π) or –1/360◦ , yielding the physical unit of the group delay to be the second (s). τG ( f 0 ) = −

1 d arg (s21 ( f 0 )) 360◦ d f

(12.42)

Academic examples are based on algebraic expressions which can be directly inserted in to formula (12.42) to derive them by algebraic means. In contrast, a network analyzer measures S-parameters over a discrete frequency axis. This frequency axis has a step size of f. Therefore, the derivative d/df must be approximated numerically by a difference quotient. For greater flexibility, it is useful to distinguish between f and a frequency step size of fd = κ · Df, which is used for calculating the difference quotient, known as the aperture. The factor κ is then called aperture stepwidth. τG ( f 0 ) ≈ −

1 arg (s21 ( f 0 + f d /2)) − arg (s21 ( f 0 − f d /2)) 360◦ fd

(12.43)

604

Amplifier measurements

Trc1

S21 Delay 30 ns/ Ref 80 ns

1

S21 Aperture selected optimal

200 170 140 110 80

Aperture selected too large

50 20 10 –40

Aperture selected too small

Ch1 Center 2.222 GHz

Pwr 16 dB m

Span 60 MHz

Figure 12.21 Examples for group delay measurements of a bandpass filter with a VNA [4].

0

f arg(s21(f 0)) − arg(s21(0)) f0

arg(s21 (f ))

Figure 12.22 Definition of the phase delay.

The selected aperture fd has an influence on the calculated group delay curve τ G ( f ). A value that is too large results in a loss of details, while a value that is too small will overemphasize the influence of the noise that is superimposed on the measured values (see Figure 12.21). Unfortunately, there is no general rule for selecting the aperture. The necessary value must be determined empirically and should be stated with the result. The phase delay τ P ( f ) is a function of the absolute phase at frequency f. It is normally calculated from the transmission coefficient s21 . The phase delay τ P ( f ) is proportional to the phase range covered between 0 Hz and the observed frequency point f divided by the frequency of observation. In this computation,

12.4 Further linear measurements

605

the phase at 0 Hz is assumed to be arg(s21 (0 Hz)) = 0 even if it is theoretically not defined because of s21 (0 Hz) = 0. τP = −

1 arg(s21 ( f )) − arg(s21 (0 Hz)) 3600 f

(12.44)

In a dispersion-free network, the phase delay remains at a constant value that is specific for this network (e.g., a TEM transmission line). This value indicates the time delay in seconds experienced by any sinusoidal component when passing through the network. Thus, the phase delay is strongly related to the length of a transmission line. Typical transmission lines exhibit a phase delay of a few ps up to a few ns for longer lines. Network analyzers typically use the phase value at the start and stop frequency of the sweep instead of the phase value at 0 Hz and f. Consequently, they use the difference between the stop and start frequency in the denominator of formula (12.44).

12.4.4

Linear stability considerations Instability is a basic risk with any power amplifier (PA). In an unstable state, the amplifier acts like an oscillator and will produce an (undesired) output signal even if there is no input signal present. In the rest of the frequency range, the oscillation will reduce the gain in most cases. For amplifiers measured far below their saturation power, it is important to know that when the amplifier starts oscillation it typically produces an output power with a level up to its saturation power. If the measurement equipment is not designed for that power, it may be damaged. The stability considerations have to be applied for all potential oscillation frequencies and not only for the operating frequency band in which the amplifier is intended to be used. The active circuit elements (transistors) exhibit a unity gain frequency fu upon which they turn into passive devices. Therefore, it is sufficient to consider the frequency range [0; fu ] for stability analysis. The calculations presented here are based on a pure linear circuit model and on the assumption that all parameters are accessible (this is violated in a multiple stage amplifier which requires a separate analysis for each individual stage). The first step is to consider a simple circuit consisting of a source (reflection coefficient  S ) being connected to a load  L (Figure 12.23a). The initial wave launched by the source is reflected by the load  L and travels back to the source. At the source, in turn, it is reflected back with  S . This complete cycle exhibits a weight of  S ·  L . The power during a cycle obviously increases if | S ·  L | > 1. This is equivalent to unstable behavior. However, the circuit can be predicted as stable if | S | | L | < 1

(12.45)

The next step is to consider an amplifier that exhibits two loops, one at the input and one at the output (see Figure 12.23c). Formula (12.45) must be rewritten as | S | · | IN | < 1 for the input loop and as | L | · | OUT | < 1 for the output loop. The source and load are assumed to have positive resistance, which is equivalent to |S | ≤ 1

(12.46)

606

Amplifier measurements

Simple loop Source a0 1

Amplifier

Source

ΓIN

Load a0 1

a

Γs

ΓL b

Load

Γs

a1

s21

s11

s22 s12

Input loop b2 ΓL a2

b1

Equivalent circuits

a0 1

a1

Γs

Output loop a′0 1

a2

ΓIN ΓOUT b1

ΓL b2

ΓOUT

Figure 12.23 Signal flow chart for determining stability.

and | L | ≤ 1

(12.47)

Applying the constraint (12.45) for a stable condition to the input and output loops leads to | IN | < 1 and | OUT | < 1, respectively. It is now necessary to redraw the amplifier’s signal flow chat (Figure 12.23b) to the simplified equivalent chart (Figure 12.23 c) used above.  IN has to consider the s11 -parameter but also the output embedding  L · s11 as it is passed through the amplifier by s12 and s21 . A similar consideration holds for  OUT . Consequently, the conditions | IN | < 1 and | OUT | < 1 can be expanded to     s11 + s12 s21  L  < 1 (12.48)  1 − s22  L      s22 + s12 s21  S  < 1 (12.49)  1 − s11  S  The independent variable to solve equation (12.48) is  L . The boundary case (using “= 1” instead of “<1”) leads to a solution in the form of a circle with a center at cs and a radius rs in the Smith chart of the load reflection coefficient  L (see examples in Figure 12.24). cS = rS =

∗ s22 (det(S))∗ − s11 |det(S)|2 − |s22 |2

(12.50)

|s12 s21 | |det(S)|2 − |s22 |2

(12.51)

Inserting a test value, e.g.,  L = 0, makes it possible to determine whether the stable region is inside the circle (Figure 12.24 b, d) or outside the circle (Figure 12.24 a, c). With the initial condition (12.47) in mind, the next step is to construct the intersection with the unity circle of the Smith chart to obtain the stable region. If the unity circle is not completely in the area pointed out by the stability circle (see Figure 12.24 c, d), the amplifier is only conditional stable for L . That means it is

12.4 Further linear measurements

607

rS cS cS

rS (a)

(b)

rS

rS cS

= Stable region

cS

(c)

(d)

Figure 12.24 Different cases of stability circles.

only stable for specific values of  L . All considerations have to be repeated with  s by changing s11 and s22 in formulas (12.50) or (12.51). If the unity circle of both Smith charts  L and  s is inside the corresponding stability circle (see Figure 12.23 a, b), the amplifier is called unconditional stable. In other words, it is stable for all passive load and source reflection coefficients (see formulas 12.46 to 12.47). Another linear approach is the stability factor k, by Rollet [11]. It is well known in the literature and is directly supported by most VNAs. k=

1 + (det(S))2 − |s11 |2 − |s22 |2 2 |s12 s21 |

(12.52)

However, the condition k > 1 is required but not sufficient for unconditional stability. To become a required and also sufficient criterion, then either |s12 s21 | < 1 − |s11 |2

(12.53)

|s12 s21 | < 1 − |s22 |2

(12.54)

or

Alternatively, a different definition of stability factors μ1 or μ2 known from the literature [12] can be used. For the unconditional stability of linear two-port devices, it is necessary

608

Amplifier measurements

Single ended transmission lines (a) (c) (b)

GND

GND

GND

(d)

GND

(e)

GND

Symmetrical transmission lines with ground (f)

GND

GND

(h)

(g)

GND

(i)

GND

(j)

GND

Symmetrical transmission lines ground suspended (m) (k) (l)

Figure 12.25 Typical single-ended and symmetrical transmission lines; (a) coaxial line,

(b) microstrip line, (c) triplate line (strip line), (d) coplanar line, (e) grounded coplanar line, (f) shielded twisted pair, (g) symmetrical microstrip line, (h) symmetrical triplate line, (i) symmetrical coplanar line, (j) symmetrical grounded coplanar line, (k) twisted pair, (l) suspended ground symmetrical microstrip line, (m) suspended ground strip line.

and sufficient to check one of the factors either μ1 > 1 or μ2 > 1 offering a compact criterion.

12.4.5

1 − |s11 |2  μ1 =  ∗ s22 − s11 det(S) + |s21 s12 |

(12.55)

1 − |s22 |2  μ2 =  ∗ s11 − s22 det(S) + |s21 s12 |

(12.56)

Mixed-mode S-parameters Symmetrical transmission lines (see Figure 12.25 f–m) are used in several applications because, when compared to single ended designs (see Figure 12.25 a–e), they offer improved immunity against EM interference and they come with reduced radiation due to mutual compensation of both symmetric conductors. Many antenna designs (dipole antenna, loop antenna) are based on differential feeding. To avoid the necessary balun with its imperfections and to benefit from differential design, a comprehensive concept including a power amplifier with differential ports and symmetrical transmission to the antenna offers a promising alternative to traditional single-ended concepts. If a signal is transmitted over a pair of symmetrical coupled conductors, interferences can be expected to be coupled into both lines equally. On the other hand, if the wanted signal is fed into one conductor with 0◦ phase shift and into the other conductor with 180◦ phase shift, it is very easy to distinguish the arising differential signal from the commonmode interferences. In the real world, however, a ground is usually present near the line.

12.4 Further linear measurements

609

Therefore, not only the desired differential-mode signal, but also a common-mode signal can propagate along the transmission line. A mode conversion between common and differential mode must be avoided since otherwise a clear distinction between the wanted signal and the interference is no longer possible. These considerations can be expanded to any four-pole structure used for differential signals (including differential power amplifiers). A description is required that allows a separate observation of the differential and common modes and that provides information about the mode conversion. Two physical ports with single-ended wave quantities a1 , b1 and a3 , b3 are combined to form a balanced port. From the four-pole theory the differential mode voltage v d = v 1 − v 3 , the differential mode current id = 1/2(i1 − i3 ), common mode voltage v c = 1/2(v 1 + v 3 ) and the common mode current ic = i1 + i3 are known. However, voltage and current are awkward in the microwave range. To adapt these to wave quantities ac , bc (commonmode wave quantities) and ad , bd (differential wave quantities) the well-known relation a = (v + iZ0 )/(4Z0 )−1/2 and b = (v − iZ0 )/(4Z0 )−1/2 with the related system impedances Z0 (single-ended), Z0c (common mode), or Z0d (differential mode) can be used to form a direct relation between single-ended and common-mode wave quantities or single-ended and differential-mode wave quantities: ∗

   (2Z 0 + Z 0d ) (a1 − a3 ) + (2Z 0 − Z 0d ) (b1 − b3 ) √ ad = 4 Z 0d Z 0

(12.57)

∗

   (2Z 0 − Z 0d ) (a1 − a3 ) + (2Z 0 + Z 0d ) (b1 − b3 ) √ bd = 4 Z 0d Z 0

(12.58)

∗

   (Z 0 + 2Z 0c ) (a1 + a3 ) + (Z 0 − 2Z 0c ) (b1 + b3 ) √ ac = 4 Z 0c Z 0

(12.59)

∗

   (Z 0 − 2Z 0c ) (a1 + a3 ) + (Z 0 + 2Z 0c ) (b1 + b3 ) √ bc = 4 Z 0c Z 0

(12.60)

The parts of formulas (12.57) to (12.60) that are marked with an asterisk will disappear if the differential mode system impedance Z0d and the common mode system impedances Z0c are selected so that they meet the following relation with the single-ended system impedances Z0 . Z 0d = 2Z 0

(12.61)

Z 0c = Z 0 /2

(12.62)

and

This means that single-ended and balanced-wave quantities can be transformed into one another without any mixing between incident and reflected waves. This is equivalent to a matched transition between a single-ended design (e.g., the test ports of VNA with Z0 = 50 ) and a symmetrical transmission line (e.g., offering characteristic impedances

610

Amplifier measurements

Z0d = 100  and Z0c = 25 ). Using the relations stated above, a VNA can measure balanced S-parameters by calculating them from single-ended measurements. This method is known from [13] as modal decomposition. During these measurements, the number of active ports is always one. But certain nonlinear balanced devices are sensitive to the excitation scheme, necessitating a true differential stimulus. This stimulus involves two active ports with the same stimulus frequency but adjustable phase relation, e.g., 180◦ (differential mode excitation) or 0◦ (common mode excitation). A balanced one-port device has two physical ports. Equivalent to formula (12.21), it can be described by means of reflection coefficients.      dd dc ad bd = (12.63) bc cd cc ac Reflection coefficients  cc and  dd describe reflections that are within common or differential mode, whereas reflection coefficients  cd and  DC describe transmodal reflections that have incident and reflected waves belonging to different modes. A balanced two-port consists of four physical ports 1–4 that can be grouped as balanced port 1 (physical port 1, 3) and balanced port 2 (physical port 2, 4). The following is the multimode equivalent of formula (12.20). ⎡ ⎤ ⎡ ⎤⎡ ⎤ bd1 sdd11 sdd12 sdc11 sdc12 ad1 ⎢ bd2 ⎥ ⎢ sdd21 sdd22 sdc21 sdc22 ⎥ ⎢ ad2 ⎥ ⎢ ⎥ ⎢ ⎥⎢ ⎥ (12.64) ⎣ bc1 ⎦ = ⎣ scd11 scd12 scc11 scc12 ⎦ ⎣ ac1 ⎦ bc2

scd21

scd22

scc21

scc22

ac2

The upper left and the lower right quadrant of the mixed mode S-parameter matrix (12.64) describe S-parameters that belong to one certain mode. In contrast, the upper right and lower left quadrant describe intermodal S-parameters that have incident and reflected waves belonging to different modes. An ideal differential amplifier should exhibit those S-parameters as 0. Input and output reflection should be sdd11 = sdd22 = scc11 = scc22 = 0. The S-parameter sdd21 is responsible for the desired differential mode gain, while scc21 belongs to the common mode gain. Assuming the assignment of physical ports as above, the multimode S-matrix can be calculated from single-ended measurements (matrix S) as follows: ⎤ ⎤ ⎡ ⎡ ⎤ ⎡ ⎤⎡ bd1 1 0 −1 0 1 0 1 0 ad1 ⎥ ⎢ bd2 ⎥ 1 ⎢ 0 1 0 ⎢ ⎢ −1 ⎥ 1 0 1⎥ ⎥ ⎢ ⎢ ⎥ ◦ S ◦ ⎢0 ⎥ ⎢ ad2 ⎥ (12.65) ⎣ bc1 ⎦ = 2 ⎣ 1 0 1 ⎦ ⎣ ⎦ ⎣ ac1 ⎦ 0 −1 0 1 0 bc2 ac2 0 1 0 1 0 −1 0 1 A description of cascaded balanced systems and balanced de-embedding techniques can be found in reference [14]. Active or passive baluns are three-port devices that are used as an interface between the single-ended and the balanced world. Assuming port 1 as single-ended and

12.5 Nonlinear measurements

611

ports 2, 3 to form the balanced port 2, the following mixed mode S-parameter matrix can be stated. ⎤ ⎡ ⎤⎡ ⎤ ⎡ sss11 ssd12 ssc12 as1 bs1 ⎣ bd2 ⎦ = ⎣ sds21 sdd22 sdc22 ⎦ ⎣ ad2 ⎦ (12.66) bc2 scs21 scd22 scc22 ac2 The parameter sds21 describes the conversion from single-ended to differential mode and ssd12 describes the opposite direction. The matching of the balun is stated by sss11 , sdd22 , scc22 . The parameter scs21 and ssc12 are the unwanted transmissions. Assuming the assignment of physical ports 1–3 as above, the multimode S-matrix can be calculated from single-ended measurements (matrix S) using ⎤ ⎡√ ⎤⎡ ⎤ ⎤ ⎡√ ⎡ as1 bs1 2 0 0 2 0 0 1 ⎣ bd2 ⎦ = ⎣ 0 (12.67) 1 −1 ⎦ ◦ S ◦ ⎣ 0 1 1 ⎦ ⎣ ad1 ⎦ 2 bc2 ac2 0 1 1 0 −1 1 The common-mode rejection ratio CMRR characterizes how much the separation of the differential mode and the common mode is maintained when the signal passes through the balun. It can be directly calculated from (12.66) depending on the direction of signal flow. |sds21 | (12.68) CMMR = 20 log10 |scs21 | or |ssd12 | CMMR = 20 log10 (12.69) |ssc12 |

12.5

Nonlinear measurements Power amplifiers are typically operated in the nonlinear region. Therefore, nonlinear measurements are of primary importance.

12.5.1

Intermodulation distortion (IMD) and harmonic distortion (HMD) Nonlinear distortions have been discussed extensively in previous chapters. IMD and harmonic distortion are explained by a Taylor series model of the DUT considering two-tone or single tone excitation, respectively. Figure 12.26 shows a typical output spectrum of an amplifier fed by a two-tone signal. The level differences DIM2 , DIM3 (in dBc) between LOUT (in dBm) at fundamental frequencies and a second- or third-order intermodulation product LIM2OUT or LIM3OUT (in dBm) are referred to as intermodulation suppression DIM2 , DIM3 . DIM2 = L OUT − L IM2OUT

(12.70)

DIM3 = L OUT − L IM3OUT

(12.71)

612

Amplifier measurements

20

LOUT/dB m

LOUT/dB m DIM3/dBc

15 10

DH3/dBc

DIM2/dBc

LIM3OUT/dB m

DH2/dBc

5 0

LIM2OUT/dB m

LH 3/dB m

–5

LH 2/dB m

–10 –15 f1 – f2

2f1 – f2 f1 f2 2f2 – f1

–20

2f1

2f2

3f1

f1 + f2

Ch1 Start 10 Hz

3f2

2f1 + f2 2f2 + f1 Stop 10 GHz

Figure 12.26 Spectrum analyzer readout with intermodulation products.

Two important properties that characterize the DUT are the second-order intercept point (SOI) IP2 and the third-order intercept point (TOI) IP3 . They can be related either to the input level LIN (in dBm) or to the output level LOUT = LIN + G (in dBm). Generally, intercept points IPn of nth order can be defined for higher-order intermodulation suppression DIMn (in dBc) according to L IP2IN = DIM2 + L IN DIM3 + L IN 2 DIMn = + L IN n−1

(12.72)

L IP3IN =

(12.73)

L IPnIN

(12.74)

L IP2OUT = L IP2IN + G = DIM2 + L OUT DIM3 + L OUT 2 DIMn +G = + L OUT n−1

(12.75)

L IP3OUT = L IP3IN + G =

(12.76)

L IPnOUT = L IPnIN

(12.77)

The level LIP3IN corresponds to the fictitious input level at which the output level LOUT of the fundamental frequencies and the output level LIM3OUT of the third-order intermodulation product are the same value. IP3 is not attained in most cases due to saturation effects, but it is useful for a global characterization of the DUT. Using it, the two straight lines for LOUT and LIM3OUT can be constructed immediately without requiring

12.5 Nonlinear measurements

613

LOUT dB m IP2 LIP 2OUT IP3

LIP 3OUT

LOUT

LOUT

2 dB m

1 dB m

LIM 3OUT

1 dB m

LIM 2OUT Saturation

3 dB m

DIM 2(Lx)

DIM 3(Lx)

1 dB m

1dB m

Lx

LIP3IN

LIP2IN LIN dB m

Figure 12.27 Second- and third-order intercept points [4].

any additional information (see Figure 12.27), and the intermodulation suppression DIM3 for various input levels can be predicted. On the other hand, the intercept points IP2 and IP3 can be determined graphically using the straight-line slopes outside the saturation area in order to construct the point IP3 (LIM3IN , LIM3OUT ) in the power sweep (Figure 12.27). However, measurements are typically performed as shown in Figure 12.26, yielding the values (LOUT , DIM2 , DIM3 ) only for a certain input level LIN . When applying formulas (12.72) to (12.77), the user must make sure that the DUT has not been measured in its saturation area. The two-tone stimulus can be generated using two RF generators with the same output level. All instruments should be synchronized to a common frequency reference, e.g., the internal reference of generator 1 (see Figure 12.28). Lowpass filters can be applied to reduce higher harmonics of the driving signals beyond the 50 dBc of a highend signal generator. One main aspect is to avoid any significant intermodulation in the instrumentation so that measured values can clearly be assigned to the DUT. A difference of at least 10 dB between DUT and instrumentation is a rule of thumb. Typical problems experienced in a measurement setup are as follows: 1. The mutual intermodulation between the two signal generators must be reduced by applying a coupler or Wilkinson divider and optional isolators. 2. A booster amplifier to amplify the two-tone signal should be avoided. Instead, separate amplifiers should be used for each tone.

614

Amplifier measurements

Generator 1 Lowpass Frequency f1 Driver Magnitude A1=A(optional) (optional)

Bias source

10 MHz Reference

G

Isolator (optional) 10 MHz Reference

Combiner network Isolator (optional)

High-power attenuator or coupler with dummy load

DC

Z0

Amplifier under test

Spectrum analyzer

Two-tone stimulus

Z0 Typical combiner networks Power splitter Coupler or Wilkinson Power divider

G

Generator 2 Driver Lowpass Frequency f2 (optional) (optional) Magnitude A2=A

Z0 Z0

Matching towards DUT Matching towards inputs

typ. > 20 dB typ. < 12 dB

Isolation between inputs

typ. < 12 dB

Insertion loss

typ. > 6 dB

Z0/3 Z0/3 Z0/3

Z0

typ. > 20 dB typ. > 20 dB

typ. > 20 dB typ. > 20 dB

typ. < 6 dB

typ. > 20 dB

typ. > 6 dB

typ. > 3 dB

Figure 12.28 Measurement setup for intermodulation measurements.

3. Passive intermodulation (PIM) occurs in passive devices. If connectors are not tightened properly or if their contacts are dirty, oxidized or made of two galvanically unmatched metals, these junctions form a weak nonlinear transition. If circulators or transformers are operated to saturation, they also behave as nonlinear components. The PIM is typically below −110 dBmc, and high power levels are required for these effects to occur. 4. To assess the intermodulation of the spectrum analyzer, its step attenuators can be used. Since these mechanical attenuators consist of passive resistor networks, their intermodulation effects are negligible. If the step attenuator is increased, the input level of the internal receiver will decrease. The attenuator setting is compensated on the display so that displayed power remains constant. Inter-modulation products that are generated outside the spectrum analyzer will behave the same. In contrast, intermodulation generated in the spectrum analyzer will vary by more than the attenuator setting and can therefore be distinguished. For some devices (e.g., FET), the IPn also depends on the input level because these devices defy a Taylor series approximation. A simplified setup can be achieved by reducing Figure 12.28 to only one signal generator to measure the harmonic distortion (HMD). Because no second tone is present, only harmonics LOUT , LH2 , LH3 , . . . , LHk at f1 , 2f1 , 3f1 , . . . , kf1 will occur at the measurement

12.5 Nonlinear measurements

615

result (Figure 12.26). The harmonic suppression DHn (in dBc) can be calculated from the output level LOUT (in dBm). D H n = L OUT − L H n .

(12.78)

As with equations (12.74) and (12.77), an nth order intercept point for harmonics can be calculated using DHn instead of DIMn . A quite different approach is to use the harmonic suppression values DH1 and DH2 to predict the intermodulation suppression DIM2 and DIM3 as presented in reference [15] or [16]. Based on the DIM2 and DIM3 values an intercept point related to intermodulation can then be predicted. However, this calculation assumes that the Taylor series is a valid approximation of the DUT, which may be doubtful in the context of power amplifiers. D H 2 = DIM2 + 6.02dB

(12.79)

D H 3 = DIM3 + 9.54dB

(12.80)

The total harmonic distortion (THD) is calculated from the sum of all higher harmonic powers divided by the power at fundamental frequency. It can be calculated from the output level at fundamental frequency Lout (in dBm) and the higher-order harmonic levels LHn (in dBm). ⎛$ ∞

10(L H n /10)

⎞

⎜ n=2 ⎟ ⎟ THD = 10 log10 ⎜ ⎝ 10 L OUT /10 ⎠

12.5.2

(12.81)

Compression point The saturation effect seen on the fundamental frequency (see Figure 12.27) is used to define the 1 dB compression point. This is the point (LIN1 dB , LOUT1 dB ) at which the level LOUT is 1 dB less than the expected value assuming a linear increase. Most power amplifiers are specified by the output level LOUT1 dB and not the input level LIN1 dB of the 1 dB compression point. A VNA supplemented by high-power setup (see Section 12.3.7) and calibrated using a power meter is a convenient way to achieve a power sweep and to find the compression point on the s21 trace as a drop by 1 dB (see Figure 12.29). This can be automated by marker functions providing LIN1 dB and LOUT1 dB levels. It is also common practice to define a 0.1 dB compression point. In some literature e.g., [15], the relation between the output-related 1 dB compression point LOUT1 dB and the output-related third-order intercept point LIP3OUT may be found as LOUT1 dB = LIP3OUT −10.63 dB. However, it is only valid if the Taylor series approximation holds true for the DUT, which is typically not the case for power amplifiers. As a rule of thumb a difference of typically 10 dB to 15 dB is observed in real-world examples.

616

Amplifier measurements

File Trace Channel Display System Window Info Help Compression Level:

1 dB

Trace Punct Trace Statist Min/ 1 Max/ Peak-Peak

Close 1 dB Compression Point

Trc1 S21 dB Mag 1dB/ Ref 0 dB •Mkr 1 –14.40 dB m

S21 26

Trace Statistics Cmp In: Cmp Out

25

2.826 dB Mean/ Std Dev 11.7 dB m 23.5 dB m RMS

24 Mkr 1

Phase Delay/ El Length Cmp

22

Compression Point

21

Define Compression Value... Eval Range ...

20 –21 –22

Ch1 Mix Start -15 dB m

Freq 4 GHz

Stop 15 dB m

- Menu UpLOCAL

Figure 12.29 A power sweep with automated compression point measurement [4].

12.5.3

Large-signal network analysis A current application of harmonic measurements is to reconstruct the time domain signal at the input and output of a DUT. Time domain analysis provides deep insight into an amplifier’s operating class (A, B, AB, etc.) and helps to select the optimum bias point. Traditional time domain analysis involved oscilloscopes and was restricted to a maximum frequency in the GHz range and had a dynamic range of about 30 dB. This is not sufficient for up-to-date needs. A VNA operating in the frequency domain offers a dynamic range beyond 130 dB and a maximum frequency of 67 GHz or even higher. A VNA is able to measure absolute power levels but the phase is always measured relatively between test ports. It is not possible to yield meaningful phase information when displaying the phase of a wave quantity versus frequency. The phase will alter from sweep to sweep because there is no fixed phase relation between stimulus generator and the LO (see Figure 12.13). This is sufficient for S-parameter measurement because, from equation (12.19), the common arbitrary phase offsets of the wave quantities bi and ak cancels out. To obtain a stable phase for wave quantities, one of the receivers must be freed up so that it can receive the comb spectrum generated by the synchronizer. The synchronizer is driven by a fixed frequency that is adjusted prior to the measurement setup, and defines the frequency spacing of the comb spectrum (see Figure 12.30). The comb spectrum provides a set of constant phase relations for different frequencies which all wave quantities can be related to. This setup is often called a large signal network analyzer (LSNA).

617

12.5 Nonlinear measurements

LO generator Generator

3 GHz + fIF

1st Stimulus generator

2nd Stimulus generator

1 GHz

3 GHz

1 GHz

1 GHz

IFb1

IFa1

IFa2

IFb2

IFphase

Receiver section

Test set

Test port 1

1 GHz

External termination

Test port 2

3 GHz

DUT

Synchronizer

Figure 12.30 A VNA supplemented to form a LSNA according to reference [17].

After the comb generator has been configured, a receiver and stimulus level calibration must be performed using a power sensor followed by a receiver phase calibration using a precision phase reference. These calibration steps also involve the use of a standard calibration kit. The following formulas are based on the Fourier series and the permissible assumption of real-valued time-domain wave quantities a(t), b(t).   N −1  2π nm 2 |a( f 0 · n)| cos a(t · m) = + arg(a( f 0 · n) 2N − 1 n=1 2N − 1

(12.82)

  N −1  2π nm 2 |b( f 0 · n)| cos b(t · m) = + arg(b( f 0 · n) 2N − 1 n=1 2N − 1

(12.83)

t =

1 f 0 (2N − 1)

(12.84)

In the above equations, the time resolution t is based on the fundamental frequency f0 and the number of harmonics N. Applying techniques such as windowing or extrapolation with linear prediction to the frequency-domain samples may lead to further improvement. The time-domain voltage v(t) and current i(t) can be calculated from the wave quantities a(t) and b(t) and the reference impedance Z0 and the DC values measured from the bias condition (v DC , iDC ):  v(t) = Z 0 (a(t) + b(t)) + v DC (12.85) 1 (12.86) i(t) = √ (a(t) − b(t)) + i DC . Z0 An example of v(t) and i(t) of an AB class amplifier is shown in Figure 12.31.

Amplifier measurements

7

160 m

6

140 m 120 m

5 4

A

V

100 m 80 m

3

60 m

2

40 m 20 m

1

0 0

500 p

1n Time (s)

1.5 n

2n

0

500 p

1n Time (s)

1.5 n

2n

Figure 12.31 Voltage and current at an Excelis EPA120B amplifier output driven with 1 GHz

sinusoidal input, courtesy of [17].

160 m 140 m 120 m V(m)

100 m A

618

80 m 60 m 40 m 20 m 0 0

2

4

6

V

Figure 12.32 Dynamic load line corresponding to Figure 12.31, courtesy of reference [17].

The waveform of the output current is typically described using the conduction angle α (in ◦ or rad). It represents the proportion of the RF cycle for which the device is active. Figure 12.31 displays a conduction angle α = 360◦ · 700 ps/1 ns = 252◦ . A typical visualization tool is the dynamic load line as shown in Figure 13.32. The tuple of drain voltage and current (vD (t), iD (t)) of a complete RF cycle are plotted on top of the DC IV curves that have been precharacterized for different gate voltages. Figure 13.32 uses a color code (reprinted in gray scale) to assign the relevant gate voltage to all measured voltages. It reveals that a gate voltage down to −1.8 V is used and that a phase shift between dynamic gate voltage and static IV curves occurs. By changing the external termination in Figure 12.30 from match to open the influence of load termination on the dynamic load line can be studied, which leads to the topic of the next section.

12.5 Nonlinear measurements

619

Load/source-pull principles Passive Principles

Solid-state tuners

Active principles

Mechanical tuners

Active loop

Source signal splitting

DUT DUT

Slide screw tuner Slug

y

Stub tuner y

y

x

Mechanical sketches

x

Short or open

Iy Z0 I0 - Ix

Zy

Z0

Iy

Ix

Single screw tuner x and y movement necessary

Equivalent circuits

Z0 Z0 Ix

Multiple screw tuner

Prematching tuner Combines 2 slugs to yield high Γ

Z0 I0 – Ix

Single stub tuner x and y movement necessary

Non-varying x tuner 2-3 slugs to avoid x movement

Multiple stub tuner

Prematching tuner Combines 2 stubs to yield high Γ

Non-varying x tuner 2-3 stubs to avoid x movement

Figure 12.33 Source- and load-pull principles.

12.5.4

Load- and source-pull measurements A good power amplifier design utilizes the power capability of an active device with good efficiency for a specified complex modulated signal. One of the main tasks is to design optimal input and output matching. A straightforward approach is to determine the required impedances by varying the source impedance  S and load impedance  L provided to the active device using a measurement setup called a load- and source-pull system. Figure 12.33 provides an overview of principles that can be applied. Active systems are based on injecting signals with adjustable phase and magnitude to mimic the reflected wave of a specific load impedance. The required signal can be generated from an active loop or branched from the stimulus source. These techniques offer the unique capability to synthesize load impedances with || = 1 or (to compensate

620

Amplifier measurements

Bias DUT

Tuner 3f0 influences f0

Tuner 2f0 influences f0

Power sensor

Tuner f0

Figure 12.34 The cascaded tuner method of harmonic load-pull.

Bias Power sensor

Tuner f0 DUT

Triplexer (losses, band limitation)

Tuner 2f0

Match

Tuner 3f0

Match

Figure 12.35 The triplexer method of harmonic load-pull.

for losses) even || > 1. However, active systems include the risk of oscillation due to a loop architecture or when || > 1 is directly applied to the DUT. Passive tuners operate like adjustable line transformers. They employ cascaded transmission lines, where some of them have adjustable impedances and positions (slide screw tuner) or a variable shunt susceptances of one or more short-circuited variable length lines (stub tuner). The number of elements (slugs or stubs) can be increased to eliminate x movement or to yield a high VSWR value of approximately 200:1 from a combination of medium VSWR elements. Tuners can be operated manually or automated by precision stepping motors. Alternatively, several fixed stubs can be combined by a PIN-diode switching network to eliminate the mechanical problems (response time, wear-out) but with the tradeoff of additional losses and reduced power handling capability. An amplifier’s efficiency is considerably improved by shorting its higher harmonics 2f0 and 3f0 which means that reflection factors of ideally | L (2f0 )| = 1 and | L (3f0 )| = 1 with an adjustable phase are required. Fundamental tuning, which controls only the load condition  L ( f0 ) at the fundamental frequency f0 , can be expanded by additional hardware to control the load condition at one or more harmonics (harmonic tuning). With a cascaded structure (Figure 12.34), the harmonic tuners 3f0 and 2f0 are typically placed next to the DUT to avoid unnecessary degradation of | L (2f0 )| and | L (3f0 )| due to losses. Stub tuners or prematching tuners used for this purpose are optimized. But tuning the harmonics has a significant effect on the fundamental impedance, requiring its re-tuning after the harmonics are set and vice versa. This may lead to an iterative process. The triplexer method (Figure 12.35) uses filters to decouple the tuners and allows independent tuning of f0 , 2f0 , and 3f0 . The main disadvantage of this method is limited bandwidth caused by the filters/triplexer. Active harmonic pull (Figure 12.36) can be achieved in several ways. It can even be combined with passive tuners to boost their | L (2f0 )| and | L (3f0 )| values.

12.5 Nonlinear measurements

621

3f0 2f0 f0 Bias DUT

Figure 12.36 Harmonic active load-pull setup.

Dual channel power meter

PC

Automatic bias supply Remote control Tuner controller Power Booster sensor and “A” isolator (optional) RF source

High-power Filter and attenuator (optional) isolator (optional) Tuners

DUT

Power sensor “B”

Tuners

Input block

Output block

Figure 12.37 Source- and load-pull setup for performing power measurements.

The block diagrams can be supplemented to form the complete load- and source-pull setup shown in Figure 12.37. It is used to perform typical power measurements. During a precalibration step with a VNA directly connected to the input or output block, the S-parameters of various tuner settings are obtained. After calibration, a required load and source impedance combination can be synthesized automatically by the tuner control software. The DUT measurement relies on the power measurements performed by two power sensors and a correction scheme that calculates the available input power PAS at the DUT from the available gain of the input block (see formula (12.33)) and the readout of power sensor A. By taking the delivered power (power sensor B) and the operating power gain (see formula (12.34)) of the output block, the delivered power PDO from the DUT can be calculated. Using these two corrected measurement values, the transducer gain can be calculated as follows: G T,DUT =

PAS PD O

(12.87)

622

Amplifier measurements

Other typical properties can be analyzed as a function of the load/source match: r PAE2 calculated from formula (12.41); r harmonic distortion using a spectrum analyzer instead of power sensor B; r intermodulation distortion by replacing the RF source with a two-tone source as described in Figure 12.28 and using a spectrum analyzer; because tuners synthesize the desired impedances only in a narrowband manner, spacing of the two-tone signal must be selected carefully. The impedance setting of the tuner cannot be monitored during DUT measurement. The measurement relies on the repeatability of the tuner. One means of verification is to replace the DUT by a through with known S-parameters. Using formula (12.32), the transducer gain GT of the through can be predicted for various source- and load-pull settings ( S ,  L ). These values are then compared to the transducer gain measured as described above. Before the delivered input power at the DUT can be calculated, the input reflection factor of the DUT must be determined. This measurement also reveals that the input reflection factor depends on both the power level and the load matching. To do this, power sensor A and its coupler are replaced by the test set of a VNA. The VNA is calibrated to the input of the source tuner, and the reference plane is then shifted to the DUT, thus de-embedding the input block by its known S-parameters. Similar measurements can be done at the output to obtain the available power of the DUT. The tuner and coupler can be interchanged so that the coupler is next to the DUT. For greater insight, this arrangement can be used with a LSNA (see Figure 12.30). The influence of the LSNA’s test set has to be included in the source/load block characterization (precalibration step of tuners). The test set’s loss may prevent the system from applying the tuner’s maximum || to the DUT.

12.5.5

Hot S-parameters The characteristics of PAs are power-level dependent, especially since the amplifiers are operated near their 1 dB compression point. Besides the gain compression of s21 as shown in Figure 12.29, other changes in characteristic values like s22 can be recognized. It is therefore necessary to perform measurements under real operating conditions. As described in Section 12.3.3, a standard s22 parameter measurement would be performed in reverse operation. This means that the stimulus at port 1 is switched off, and port 2 becomes the active port instead. This does not correspond to the original operating condition. In the hot s22 measurement, the amplifier has an input signal at the operating frequency f1 applied to it. The level of this signal is configured such that the amplifier exhibits the output power level that it is designed for. At the same time, a reflection measurement is performed at the output at the probe frequency f2 = f1 + f. The power used for this probe tone is significantly lower than the amplifier’s output level (typically −30 dB lower). The a2 -wave and b2 -wave are recorded at the probe frequency f2 . Depending on the shape of IF filter used in the VNA, the frequency spacing f should be three

623

12.6 Modulated measurements

S22

S22 without stimulus at port 1

0

Hot S22 -10 -20 Port Configuration -30

#

-40 -50

Receiver

Meas Physic Source Gen

Frequency

Frequency Result

Power

Power Resu Frequency Frequency Result

Port 1

fb

1.4 GHz … 3 GHz

Pb

12 dB m

Port 2

fb + 10 MHz

1.41 GHz … 3.01 GHz

0 dB m - 20 dB

-20 dB m

Port 3

fb

1.4 GHz … 3 GHz

Pb

12 dB m

Port 4

fb

1.4 GHz … 3 GHz

Pb

12 dB m

fb + 10 MHz

1.41 GHz … 3.01

-60 -70

Displayed Columns…

Balanced and Measured Ports…

Measure "a" Waves at Receiver Frequency

Freq Conv Off

Source Frequency Stimulus…

Same Connector Type at All Ports

-80 OK

Arb Start 1.4 GHz

Pwr -25 dB m

Cancel

Help

Stop 3 Ghz

Figure 12.38 Hot s22 measurement performed using a state-of-the-art VNA and the DUT present between port 4 (input) and port 2 (output).

to ten times the value of the IF bandwidth to ensure sufficient separation between operating frequency and probe tone. Nevertheless, the S-parameter measured at f2 is close enough to f1 to determine the output impedance of the amplifier at f1 under regular forward operating conditions. The example in Figure 12.38 has been measured with a state-of-the-art VNA, which involves two internal stimulus generators configured in the dialog additionally shown. System error correction is used to ensure traceable results. The concept of hot S-parameters can be expanded to use it in a load-/source-pull environment [18]. A further extension is to use the intended modulation pattern at frequency f1 , as the real-world operating signal of the amplifier [19]. This will lead to the discussion in the next section.

12.6

Modulated measurements For wireless information transmission, a sinusoidal carrier is modulated by a baseband signal that contains the desired information. The most significant effect for power amplifiers is that modulation usually causes a time dependent variation of the carrier magnitude which is referred to as “modulation envelope.” The nonlinearities described in Section 12.5 cause imperfect reproduction of the amplified signal resulting in distortion and channel interferences. This section describes the measurement of the relevant figures of merit.

624

Amplifier measurements

12.6.1

Crest factor and CCDF The peak-to-average power ratio (PAR) describes the relation between the peak power and the average power of an RF signal and is usually stated in dB. Instead of the power the crest factor (CF) may use other parameters such as voltage or current. In this case, the average value has to be replaced by the rms value. Assuming the related impedances to be independent of the level (linear approach), then the resulting crest factors will be the same as those derived from the power ratios. The first definition calculates the crest factor CF1 based on the highest amplitude peak power PMAX that occurs in the modulated carrier signal and its average power value PAVG .   PMAX C F1 = 10 log10 (12.88) PAV G The second approach, which leads to a smaller crest factor CF2 , uses the ratio of the peak envelop power PPEP of the modulation envelope to its average value PAVG (see Figure 12.4 of Section 12.2.1).   PPEP (12.89) C F2 = 10 log10 = C F1 − 3.01 dB PAVG The crest factor of periodic signals (e.g., CW, regular pulsed CW) can be measured by comparing the results of a peak power sensor and a thermal power sensor. But this is not the case with random modulated signals such as OFDM, CDMA, and WCDMA. Due to their statistical nature, a very long observation time (e.g., several years) would be necessary until their exact peak power occurs again in the signal. A compromise using a practical observation time (seconds or minutes) is necessary. For these measurements, high-end spectrum analyzers provide the necessary functionality. They also display the measured complementary cumulative distribution function (CCDF), which describes the statistical probability of the occurrence of signal peaks that are greater by a factor of k in dB than the average value. Here, too, it is important to distinguish whether values are related to the carrier or the envelope. The CCDF helps the operator to consider the right observation time and makes it possible to compare the degradation of the CCDF due to compression or clipping effects. Aside from multiple carrier modulation techniques (e.g., OFDM), other applications such as satellite repeaters or cellular base stations require simultaneous amplification of multiple signals by multicarrier power amplifiers (MPCPA). An MPCPA has to cope with an increased crest factor different from that of single carrier operation, even if the individual signals exhibit a crest factor of CF2 = 0 dB (e.g., constant amplitude modulation pattern). Therefore testing of an MPCPA must be performed with an adequate multicarrier signal. Considering thermal issues the average power PAVG is most important. However, the highest amplitude peak power PMAX or its related voltage are responsible for flashover and possibly a standing arc as well as intermodulation effects.

12.6 Modulated measurements

625

RBW 10 MXs Ref 11.7 dB m

Att 40 dB

ACT 312.5 xs

0.1

A 0.01 1 SA CLRWR

2 SA VIEW

1E-3 1E-4

Before predistortion

After predistortion

1E-5 1E-6

Center 690 MHs

2 dB/

Mean Pwr + 2c dB

Comlementary Cumulative Distribution Function (10000000 samples) Trace

Mean Peak Crest 10% @ 1& @ .1% @

1

Trace

2

-3.54 dB m 6.10 dB m 9.64 dB

-3.55 dB m 5.60 dB m 9.16 dB

3.65 dB 6.47 dB 7.92 dB

3.65 dB 6.28 dB 7.53 dB

Figure 12.39 CCDF of a DVB-T signal (OFDM) measured at a PA output (envelope related values) before and after predistortion [20].

Figure 12.40 Influence of a nonlinear amplifier on a multitone signal.

12.6.2

Adjacent channel power ratio (ACPR) Each wireless device operates in a specific frequency channel to which it has been assigned, which will be temporary when using frequency hopping. Leakage of the channel power can lead to interference with other services. A two-tone approach to mimic the scenario was introduced in Section 12.5.1. The third-order intermodulation products have been identified as particularly disruptive since they are relatively close to the useful signal and are difficult to suppress by filtering. Therefore, they normally affect adjacent channels. To obtain a more realistic scenario, the number of tones with equal amplitudes has to be increased to N  2. Assuming the tones are equally spaced with f, the Taylor series model will lead to a spectrum similar to that in Figure 12.40. The third-order intermodulation products form a spectral re-growth of N − 1 tones on both sides of the N-tone channel.

626

Amplifier measurements

Simplified block diagram of a spectrum analyzer:

Remote control (Optional e.g. for Sweept ACPR Measurements)

PC

Step Attenuator

1st IF

RF -18 dB m RMS -6 dB m peak

10 MHZ

Q

I=44.1 MHz, P=-18dB m Modulation: ON IQ Input : EXTERN Ref. Osc. : INTERN

-18 dB m RMS -6 dB m peak

-19.3 dB m RMS -9.3 dB m peak

Spectrum analyzer

Baseband generator Data

Analog filter Log. Amp. & DSP 3rd IF

1st mixer

TRG

I I Q RF

: 44.1 MHz

Stop Att Ref. Osc. Rof. Level RBN SWP Tine Detector

: 30 dB : EXTERN : 0 dB : 30 kHz : 2s : RMS

RF

19 dB m (RMS) 31 dB m (peak)

DUT

I/Q-Modulated RF generator

Contor

Amplifier under test (e.g. with Pull-environment)

High-power attenuator (optional)

Figure 12.41 Typically setup to perform ACPR measurements.

The ACPR or adjacent channel leakage ratio (ACLR) is a commonly accepted metric for quantifying the effect of spectral regrowth for digitally modulated signals. The ratio is usually expressed as the total power over a certain frequency band B adjacent to the main channel versus the total power in the main channel. The total powers can be determined by integrating the appropriate power spectrum p( f ) over the relevant frequency ranges. In some cases, an frequency response H( f ) of the pulse-shaping filter (typically raised cosine) is applied. The ACPR has the unit dBc. It depends on the signal characteristic (e.g., modulation standard, power, frequency channel, number of coded channels in OFDM). Usually a distinction is made between upper ACPR and lower ACPR referring to the leakage above or below the main channel. A typical example of spectral leakage caused by an amplifier is sketched in Figure 12.41 at the DUT’s output. Additionally, an alternate channel power ratio (ACPR2) is specified using a higher frequency offset than the ACPR. The integrated and weighted adjacent channel powers can be expressed by the levels LUP (in dBm) or LLOW (in dBm) of upper or lower channels, respectively. The integrated and weighted main channel power is stated by the level LCH (in dBm). ⎞ ⎛ ( p( f ) |H ( f )|2 d f ⎟ ⎜lower channel ( (12.90) ACPRLOW = 10 log10 ⎝ ⎠ = L LOW − L CH p( f ) |H ( f )|2 d f ⎛

main channel

(

⎜upper channel ( ACPRUP = 10 log10 ⎝

p( f ) |H ( f )|2 d f p( f ) |H ( f )| d f 2

⎞ ⎟ ⎠ = L UP − L CH

(12.91)

main channel

The integrated bandwidth method uses a spectral integration to calculate the channel level LCH . It can be performed using a spectrum analyzer with the resolution bandwidth

12.6 Modulated measurements

627

BRBW set narrow compared to the channel bandwidth BCH (typically BRBW /BCH = 0.5 to 5%). The minimum time tSWP necessary for one frequency sweep of F can be estimated using a typical factor C = 3 and the following formula. tSWP = C

F 2 BRBW

(12.92)

Because of the modulated signal’s random nature an RMS detector and a manually increased sweep time of about 15 · tSWP is required to yield a stable trace. To calculate the level LCH the individual levels Ln of the N frequency samples in the relevant frequency range have to be summed up according to formula (12.93). A correction factor KRBW = 1.06 to 1.14 is used to obtain the noise equivalent bandwidth from the resolution bandwidth BRBW . The term |H(f · n)|2 with the frequency step-width f is used to implement the spectral weighting.

N  BCH 1 (12.93) · |H ( f · n)|2 · 10 L n /dBm L CH PWR = 10 log10 K RBW · BRBW N n=1 The levels LLOW and LUP can be determined in a similar way. Automatic spectrum analyzer functionalities are available for these numeric calculations. A typical setup for performing ACPR measurements on a power amplifier is shown in Figure 12.41. It consists of an IQ-modulated RF source (depending on the modulation scheme using an external baseband generator) and a high-end spectrum analyzer. A trigger signal (see Figure 12.41 signal “TRG”) or a broadband level detector inside the spectrum analyzer (RF trigger) has to be used when measuring TDMA systems. These systems pulse their signal power to provide timeslots for other services. Measurement values should only be recorded within the active timeslots (burst) and the sweep must be paused outside the active timeslots. The ACPR caused by the transient effects cannot be detected correctly by the integrated bandwidth method due to the fact that its narrowband resolution filter (BRBW ) causes a comparably long settling time. An alternative method described in the next paragraph is preferred in these cases. The method of channel power measurement in time-domain is a different approach that omits formula (12.93). Using digital signal processing then any type of channel filter H( f ) can be digitally implemented in the spectrum analyzer. This allows channel power measurements in the time domain with the spectrum analyzer working like a tuned receiver. In this way it is possible to obtain a short measurement time. The method yields much better reproducibility of results and detects transient signals (e.g., from TDMA systems) correctly. If several channels are to be measured the spectrum analyzer successively tunes to the respective channel center frequencies. One main aspect of all the methods is to avoid any significant ACPR from occurring in the spectrum analyzer. A simplified block diagram of a spectrum analyzer is shown in Figure 12.41, upper right. The available dynamic range of the spectrum analyzer has to be considered to ensure minimal phantom reception in the adjacent channels: The peak power of the measured channel has to be within the linear region of the first mixer and the stages in front of the IF filter (RBW). The step attenuator can be used to

628

Amplifier measurements

ACPR/dBc −50 −55 −60 −65

Total ACPR

−70 −75 −80

ACPR due to inherent spectral regrowth

ACPR due to inherent noise floor

−85 −90 −95 −24

−22

−20

−18

−16

−14

−12

−10

−8

−6

−4

Mixer Level/dB m

Figure 12.42 Contributions for inherent ACPR of a high-end spectrum analyzer dependent on its

input mixer level [22].

optimize the peak envelope power level at the first mixer to a value 10 dB below the 1 dB compression point of the first mixer. The noise floor determines the lower limit for power measured in the adjacent channels. A spectrum analyzer’s noise figure NF is typically in the range of 13 dB to 19 dB. A correction factor KH( f ) is used to obtain the noise equivalent bandwidth for the pulseshaping filter H( f ). The thermal noise power level NCH within the channel bandwidth BCH can be calculated according to the following formula.   K H ( f ) BC H dB + NF (12.94) NCH = −174 dBm + 10 log10 1 Hz In this example a noise figure of NF = 15 dB, a channel bandwidth of BCH = 4.096 MHz and a correction factor K ≈ 1 (typical K for all common H( f )) is assumed. Therefore, formula (12.94) leads to a noise power level of NCH = −92.8 dBm. The phase noise of the spectrum analyzer’s internal local oscillators leads to an inherent noise in the adjacent channel (reciprocal mixing). The spectrum analyzer assumed in this example exhibits a contribution of 85 dB below the transmit carrier which can be neglected. The dynamic range can be visualized as shown in Figure 12.42. The horizontal axis of the diagram shows the channel power at the first mixer. This is the signal power at the spectrum analyzer’s RF input minus the step attenuator setting (see Figure 12.41, upper right). The vertical axis shows the inherent contribution of the spectrum analyzer

629

12.6 Modulated measurements

Ref Lvl –30 dB m

Marker 1 [T1] -102.04 dB m 1.99250000 GHz

RBW vBW SWT

30 kHz L MHz 2s

−30

1

−40

RF Att Unit

[T1]

CH PWR ACPR Up ACPR Low

−50

0 dB dBm

–102.04 dB m 1.99250000 GHz –17.99 dB m –62.60 dBc –62.64 dBc

−60 1RM −70 −80 −90 −100 −110 −120 cI1

cI1

CO

CO

cu1 cu1

−130

Center 2 GHz

1.5 MHz

Span 15 MHz

Figure 12.43 Display of ACPR test result [21].

to the ACPR for a channel bandwidth of BCH = 4.096 MHz (in this example). The contribution due to the spectrum analyzer’s thermal noise floor reduces with increasing input level and is described by a slope of −1 dBc/dBm. The ACPR due to inherent spectral re-growth increases with a 2:1 slope like third-order intermodulation products (see multitone approach at the beginning of this section). The 2:1 slope will be shifted vertically depending on the crest factor of the signal applied. This is due the fact that the horizontal axis relates to the channel power while the spectrum analyzer’s inherent intermodulation depends on the peak power applied. In Figure 12.42 a wideband CDMA signal with a crest factor CF2 = 12 dB was assumed. This value also depends on the type and number of coded channels. The power contribution of all these inherent effects can be combined to form the total inherent ACPR. The optimum total ACPR of 73 dBm is obtained with a first mixer input level of −16.2 dBm. An example using an −18 dBm channel power level and a step attenuator setting of 0 dB is shown in Figure 12.43. The measured ACPR values of about −62.6 dBc can clearly be assigned to the DUT’s broadband noise because Figure 12.42 reveals an inherent ACPR contribution of 72.6 dBc. This is 10 dB below the measured value and causes an error of approximately 0.5 dB.

630

Amplifier measurements

I

Intended vector

Error vector

Actual vector Q

Figure 12.44 Illustration of the error vector.

12.6.3

Noise–power ratio (NPR) As pointed out in Figure 12.40, the third-order intermodulation products of a multitone signal with N > 2 tones also affect the in-band level of the N-tone channel as the third-order intermodulation products coincide with some of the in-band signals. The noise–power ratio (NPR) assumes the amplifier is driven with Gaussian noise and a notch placed in one segment of its input spectrum. Nonlinearities cause power to appear in the notched band of the spectrum when the signal passes the amplifier. The NPR is the ratio of the notch power to the total signal power. The numeric calculation presented with formula (12.93) can easily be adapted to the needs of this measurement. The RF source of Figure 12.41 has to be replaced by a suitable Gaussian shaped noise source and a notch filter. To prevent the mismatch of the stop-band of the notch filter at the amplifier’s input from interfering with the amplifier, an isolator should be inserted between the filter and the amplifier under test.

12.6.4

Error vector magnitude (EVM) and constellation diagram The EVM is a convenient metric of how intermodulation products, memory effects and noise contributions affect the detection process in the baseband. At the output of a power amplifier (which is located at the beginning of the transmission chain) noise contributions should be negligible. Memory effects are described in later sections. The EVM is defined as the distance between the intended and the actual signal vectors, normalized to a fraction of the signal amplitude (see Figure 12.44). The EVM is thus stated in percentage. It is important to distinguish whether values are specified as peak or RMS value. Typical modern communication standards require an EVM of 22 to 30% peak and 7 to 12% rms depending on the communication standard (details may be found in the applicable standards). A setup similar to that of Figure 12.41 can be used to measure the EVM, but the spectrum analyzer has to be replaced by a vector signal analyzer as shown in Figure 12.45. The first analog stages of both instruments are very similar. The samples obtained from

631

12.6 Modulated measurements

Re{X} Step attenuator RF

1st IF

A

3rd IF

D

I Digital filter

A/D converter

Analog filter

1st mixer

RAM

X

90°

NCO

Analog section

Q

Im{X}

Digital filter

IQ-Samples (baseband)

IQ Reference signal

Modulator

Demodulator

− + Synchronization

IQ

Fitting

IQ Error signal IQ Measurement signal

Figure 12.45 Block diagram of a modern VNA.

the digital IQ down-conversion process are stored in a random-access memory (RAM) instead of feeding them to the selected detector as normally occurs in a spectrum analyzer. A vector signal analyzer employs a digital-signal processor (DSP) to perform the following steps on the readout of the RAM. A combination of demodulator and modulator blocks is used to generate an undistorted IQ reference signal by employing the bit level between both blocks. The synchronization block compensates the measured signal (RAM readout) for center-frequency offsets, phase and symbol timing. The measured synchronized signal is then fitted to the undistorted IQ reference signal. The magnitude and phase parameters applied in this process correspond to the RMS value of the EVM. Finally, a comparison between the undistorted IQ reference signal and the measured IQ signal is carried out to provide magnitude and phase error versus time. The measurement values obtained in Figure 12.45 can be used to plot a constellation diagram. This diagram is the baseband representation of the individual symbols normalized to a complex plane spanned by −1 to + 1 and –j to + j. The transients between symbols may not be plotted. Ideally, each symbol is assigned to a single discrete point of the diagram. Practical measurements show a cloud pattern around each ideal constellation point. The size of the clouds and their center positions give important information (e.g., saturation effects will shift the outer constellation points towards the origin of the diagram or insufficient phase synchronization will lead to sickle shaped constellation points). Alternatively, the ideal and measured I or Q signals can be plotted versus time. This can help to detect certain symbol sequences that lead to maximum error, e.g., caused by memory effects.

632

Amplifier measurements

conscellation diagram 1 0.8 0.6

Imaginary part

0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 −1 −1

−0.8 −0.6

−0.4 −0.2

0

0.2

0.4

0.6

0.8

1

real part

Figure 12.46 Constellation diagram for a [21] DVB-T signal.

12.6.5

AM/AM and AM/PM measurements The various levels applied by high-order digital modulation schemes can be used to plot the amplitude error as a function of the ideal levels provided by the undistorted IQ reference signal. This diagram is also called AM/AM distortion characteristic. If the signal power is in the vicinity of the 1 dB compression point, the amplitude error can be used to predict a dynamic 1 dB compression point. A similar diagram called AM/PM distortion characteristic can be obtained from plotting the phase error instead of the amplitude error. A setup similar to Figure 12.41 involving a vector signal analyzer (Figure 12.45) can be used to perform the AM/AM and AM/PM measurements. The measurement result of Section 12.5.2, Figure 12.29 is very similar to the AM/AM measurement above. Instead of the magnitude in Figure 12.29 the phase of s21 also can be displayed leading to an AM/PM diagram. But the main difference to the discussion presented above is that the power sweep applied in Figure 12.29 exhibits a comparatively slow time gradient. For a memory-less amplifier the approaches of Sections 12.5.2 and 12.6.5 should lead to the same results.

12.6.6

Memory effects The Taylor series model assumed in Section 12.5 did not consider any dynamic effects. However, memory effects exist and create another type of distortion. Memory effects

12.6 Modulated measurements

633

are identified using variable-rate swept AM/AM measurements or applying pulsed measurements with variable pulse repetition rate. Memory effects also come to attention through the asymmetry in the output intermodulation products. Another result of memory effects is the AM to PM conversion. Memory effects can be classified as long-term and short-term. Long-term memory effects are caused by electro-thermal interactions, varying power supply, and electron traps. Short-term memory effects are a result of the transistor’s time delays that are modeled by energy storage elements such as capacitances or inductances. Nonlinear charge functions result in an instantaneous phase angle that is modulated due to the level-dependent instantaneous capacitance. Even linear charge functions combined with nonlinear conductance result in an instantaneous phase angle that is modulated by the varying instantaneous conductance.

12.6.7

Pulsed measurements Pulsed operation can be compared to a very simple modulation scheme that switches the carrier on and off (on-off keying). Radar applications use a very short RF burst of several tens of nanoseconds. Amplifiers for the mobile communication market such as GSM mobile phones are often designed for pulsed operation using their bias voltage to realize the “on” and “off” state. Continuous operation would damage the amplifiers due to overheating. The desired performance of these amplifiers can only be studied under pulsed conditions and measurements must be adapted to this requirement. A periodically pulsed signal can be described by its carrier frequency fc , pulse width tp and pulse period T (see Section 12.2.1 Figure 12.4). Some related parameters are the duty cycle D = tp /T and the pulse repetition frequency PRF = 1/T. The following measurements can be performed using a modern VNA. The point-in-pulse method, acquires the measurement data only during the on-state of the RF bursts. Therefore, it is necessary that the sampling time to acquire the measurement data is shorter than the pulse width tp . The sampling time is mainly determined by the measurement bandwidth of the analyzer. To obtain a sampling time of 200 ns (too long for some of the radar applications) a measurement bandwidth of at least 5 MHz is required. A sampling time of 0.500 ms (sufficient for most GSM mobiles) can typically be achieved with a 300 kHz measurement bandwidth. The resulting dynamic range (noise floor) is dependent on the measurement bandwidth used in the analyzer and therefore related to the pulse width tp . The dynamic rage can be improved using averaging, while keeping the measurement bandwidth to its needs. A trigger signal is necessary to ensure that data acquisition is done only during the on-state of the RF bursts. The point-in-pulse method is not suitable to analyze the very short transient state of the amplifier under test. In order not to acquire data during the transient state a trigger delay must be used and the acquisition time must be short enough to make sure that data sampling is only done at the settled roof of the pulse. The average pulse method uses a totally different approach. The pulsed signal can be described as a CW signal of frequency fc that is multiplied by a LF signal. The LF signal toggles between “0” and “1” state with the pulse repetition frequency PRF and a duty

634

Amplifier measurements

cycle D. The multiplication in the time domain is a convolution of the spectra of CW and LF signals in the frequency domain, i.e. a1 ( f ) =

∞  sin (π Dk) A1 (δ( f − f c ) + δ( f + f c )) ∗ D δ( f − k · PRF) 2 π Dk k=−∞

(12.95)

The convolution of equation (12.95) can be simplified. If a single sideband description is used (only frequencies f ≥ 0 are exclusively considered) then one would obtain a1 ( f ) =

∞  sin (π Dk) A1 D δ( f − f c − k · PRF) 2 k=−∞ π Dk

(12.96)

This is a comb spectrum that has a sin(x)/x envelop and is centered on the carrier frequency fc . To perform S-parameter measurements it is sufficient to observe the same specific tone in both wave quantities ak and bi (see formula (12.19)). For this purpose the spectral component at the carrier frequency fc is used because it exhibits the maximum power. The sin(x)/x envelop becomes 1 at this component. Thus, the magnitude obtained at frequency fc is scaled by the duty cycle D (see formula (12.96)). The measured power is therefore quadratically related to the duty cycle D. A duty cycle of D = 1% thus reduces the signal-to-noise ratio by 40 dB. The distance between two adjacent spectral components δ( f – fc– k · PRF) is given by the pulse repetition frequency PRF. In order to suppress all spectral components different from δ( f – fc ) a measurement bandwidth considerably smaller than the pulse repetition frequency must be selected (typically BRBW < PRF/10). To achieve a suppression of 40 dB and more, special high selectivity filters may be used. If necessary, the carrier frequency and the pulse spectrum can be shifted and the measurement can be repeated at that different carrier frequency. Proceeding like this yields a swept measurement result. The additional tones of the pulse spectrum are only used to support realistic operation conditions, like applying the correct bias voltage. The pulse profile method is intended to analyze the time dependent behavior of the DUT during a burst including analysis of the rise and fall time as well as overshoot and drop. For this purpose the measurement must have a time resolution significantly shorter than the pulse duration. To overcome the time resolution limit known from point-in-pulse method a variable trigger delay and a time window is used to “chop up” the pulsed signal into slices with different timing positions within the pulse. The trigger delay is kept constant over some hundred pulse instances. As a consequence the measurement bandwidth can be selected according to the average pulse method. The trigger delay is then increased and the next set of slices with a constant trigger delay is measured. Finally, the pulse waveform is reconstructed from the measurement results obtained at different trigger positions. The results measured on a pulsed power transistor are shown in Figure 12.48. The measurement was performed using two external couplers and a booster amplifier as described in Section 12.3.7 (Figure 12.17 right). The pulsed signal can be provided by a pulse modulator connected into the vector network analyzer’s generator path or by use of an external RF source that can be pulsed. In the lower half of Figure 12.48 an overshoot

635

12.6 Modulated measurements

Moment of observation

Pulse envelop of a1

t τD

τD “Sliced” pulses of a1

τD

2τD

2τD

2τD

3τD

3τD

3τD

Measurement with const. trigger delay

Floating trigger delay

t

Figure 12.47 An example of pulse chopping [23].

Trc6 S21 Phase 1°/ Ref 80 ° Cal Math S21

TRG

M4

M3

Ch1 Profile Start -10 μs

Freq 1.3 GHz Pwr 0 dB m

2 M1 20.0000 μs 81.277 M2 200.0000 μs M3 260.0000 ns 81.119 M4 2.0000 μs 82.969

Stop 20 μs

Trc7 S21 dB Mag 0.2 dB/ Ref21 dB Cal Trc8 b2 dB Mag 0.2 dB/ Ref51 dB m Math 3 M1 20.0000 μs 20.600 dB b2 TRG 51.8 M2 200.0000 μs M3 260.0000 ns 20.891 dB 51.6 M4 2.0000 μs 20.612 dB 51.4 M1 20.0000 μs 50.420 dB m 51.2 M2 200.0000 μs M3 M3 260.0000 ns 50.653 dB m 51.0 M4 2.0000 μs 50.261 dB m M3 M4 50.8 50.6 M4 50.4 50.2 Ch1 Profile Start -10 μs

Freq 1.3 GHz Pwr 0 dB m

Stop 20 μs

Figure 12.48 Pulse profile measurement of an radar transistor [22].

of s21 at the beginning of the pulse can clearly be identified as well as a phase deviation of approximately 2◦ that gradually settles.

12.6.8

Bit error ratio (BER) and symbol error ratio (SER) The figures of merit described in this section are related to signal quality. Digital modulation techniques allow some degradation of signal quality while causing almost no loss of information. Describing systems on a more abstract level requires a metric that

636

Amplifier measurements

characterizes the transmission quality. The BER is the number of erroneous bits received divided by the total number of bits transmitted. The SER is defined in the same way but considers the symbols which typically encompass several bits (e.g., 6 bits per symbol for the constellation diagram Figure 12.46). The measurement of the BER and SER is done using a bit error tester. For amplifier test a setup similar to Figure 12.41 is used. The baseband generator is used to form a pseudo random binary sequence (PRBS) that modulates the RF generator. The output signal derived from the amplifier under test is demodulated using a spectrum analyzer or another suitable receiver. The decoded bit stream is fed back to the baseband generator and synchronized. The data bits are checked for errors. The total of the transmitted bits and the faulty bits are counted. If the stream contains headers or guard bits, the counting process should be paused for those bits.

12.7

Noise measurements Active and passive circuits are subject to noise. Noise occurs in various forms such as thermal noise, Schottky noise, etc. Those that are relevant to RF amplifier design exhibit nearly uniform noise power spectral density. The thermal noise power PN0 that is available from a resistor at temperature T0 = 290 K (= 16.8 ◦ C = 62.3 ◦ F) to a matched load can be calculated as follows using Boltzmann’s constant k = 1.38 · 10-23 Ws/K and the noise equivalent bandwidth B: PN 0 = kT0 B = 4 · 10−21

W ·B Hz

(12.97)

corresponding to  N0 = −174 + 10 log10

B Hz

 dBm

(12.98)

The available noise power PNO (not the delivered noise power) is independent of the noise source impedance. The temperature T0 = 290 ◦ K used above has been set as a reference value by IEEE standards. The noise power PN typically exhibits very small values and is cumbersome to express. Since most noise calculations are based on summing up linear values, the dBm scale of N cannot serve as an alternative. The most convincing answer offering convenient values is to describe the noise power by a fictitious temperature. This noise temperature T does not mean that the device is at that physical temperature. PN = kTB

(12.99)

N = 10 log(kTB/1mW )

(12.100)

corresponds to

12.7 Noise measurements

12.7.1

637

Amplifier noise factor and noise figure This approach considers an amplifier embedded in a matched environment with a system impedance Z0 . The amplifier’s available gain Ga applies to both the signal power PSin and noise power PNin present at the input. In addition, the amplifier internally adds some inherent noise power PNa . Hence, the noise power exiting the amplifier’s output is PNout = G a PNin + PNa .

(12.101)

The signal-to-noise ratio PS /PN compares the signal power and the noise power, and this ratio will degrade when the signal passes through an amplifier. The noise factor F is the ratio of the signal-to-noise power ratio PSin /PNin at the input divided by the signal-tonoise power ratio PSout /PNout at the output. By definition, the input noise power is given by equation (12.97). The linear assumption PSout = Ga PSin and equation (12.101) yield the following: F=

PSin /PNin PNa =1+ PSout /PNout kT0 BG a

(12.102)

The dB representation of the noise factor F is called the noise figure NF (unfortunately, this looks like the product N · F, but it isn’t). The output noise power exiting two cascaded amplifiers deserves a closer look. The noise power PNa1 internally added by stage 1 is amplified through stage 2 while the noise power PNa2 added by the last stage is directly present in the output signal. Consequently, the noise power PNout2 present at the multistage output can be calculated from the input noise power PNin , the available gains Ga1 , Ga2 and noise powers PNa1 , PNa2 of amplifier stages 1 and 2, respectively. PNout2 = PNin1 G a1 G a2 + PNa1 G a2 + PNa2

(12.103)

The noise factor definition (12.102) can be applied to multiple stage systems. The overall system noise factor Fsys can be derived from formulas (12.102) and (12.103) leading to the Friis [23] equation: Fsys = F1 +

F2 − 1 G a1

(12.104)

where F1 , F2 are the individual noise factor and Ga1 is the gain of the first stage. The second stage contribution ( F2 − 1)/Ga1 can be reduced if the first stage exhibits a high gain Ga1 . That is one reason why low-noise amplifiers should be put close to the signal source (antenna) and why they are chosen to have a relatively high gain of 25 dB to 50 dB.

12.7.2

Noise figure measurement To perform direct noise measurement, the output noise power of the DUT is measured using an input termination at room temperature (approximately 290 ◦ K). If the gain Ga and noise equivalent bandwidth B of the amplifier under test are known, the noise factor can be determined using formulas (12.101) and (12.102). This method is limited

638

Amplifier measurements

Table 12.9 Typical noise power and noise temperature values PN related to B = 1 Hz ≈ 1.06 × 10−21 W

≈ 4.08 × 10−21 W

≈ 5.15 × 10−21 W

typ.138 × 10−21 W

N related to B = 1 Hz Noise temperature T Remark

≈ −174 dBm ≈ +296 K Resistor at room temperature (23 ◦ C)

≈ −173 dBm ≈ +373 K Resistor in boiling water (100 ◦ C)

typ. − 159 dBm typ. + 10,000 K Biased solid state noise source

≈ −180 dBm ≈ 77 K Resistor in liquid nitrogen (−196 ◦ C)

Noise meter

Through

ENR

Y

F2 Noise source

T h , Tc

DUT F1

Nh , Nc

Figure 12.49 Measurement setup for Y-factor method.

to devices with a very high noise figure of >20 dB because only these devices exhibit an output noise power that can be detected with a reasonable measurement uncertainty. The Y-factor method relies on an input termination that can be operated in two states: “cold state” offering noise temperature Tc and “hot state” offering noise temperature Th . Originally, a resistor cooled in liquid nitrogen or warmed in boiling water was used as input termination. The excess noise ratio (ENR) describes the change in noise temperature between hot and cold state relative to the standard noise temperature T0 = 290 ◦ K. ENR =

Th − Tc T0

(12.105)

According to Table 12.9, ENR ≈ 1 is calculated when using liquid nitrogen and boiling water. The need to perform automatic measurements and the fact that measurement accuracy can be improved by higher ENR values led to the use of solid state noise sources. Without bias, they exhibit noise generated at room temperature Tc ≈ T0 . Common noise sources use external 28 V for the “hot state” in which they generate a noise equivalent to Th = 4T0 , . . . , 1000T0 depending on the type of source. Commercially available models can be divided into three groups: low ENR (5 dB to 7 dB) for measuring low-noise figures (<3 dB), medium ENR (13 dB to 16 dB) as a standard noise source, and high ENR (20 dB to 30 dB) for high noise figures (10 dB to 30 dB). Except for the high ENR sources, all others incorporate an integrated attenuator to improve their source match and to reduce the impedance change from hot to cold state. The output noise power of the amplifier under test is measured for the “hot state” as PNh and for the “cold state” as PNc . The ratio of these measurement results is called the Y factor. Y =

PNh PNc

(12.106)

12.7 Noise measurements

639

Table 12.10 Typical noise figures and effective input noise temperatures Noise factor F

Typ. 1.41

Typ. 2.8

100

Typ. 1000

Noise figure NF Temperature Te 1 Remark

typ. 1.5 dB typ. 120 K Low noise amplifier 30 dB

typ. 4.5 dB typ. 527 K PA 4 W, 6 Hz to 18 Hz

20 dB 28,710 K Attenuator pad 20 dB

typ. 30 dB typ. 289,710 K Spectrum analyzer

1

The effective input noise temperature Te is the temperature difference that must be added to T0 of the source impedance connected to a noise-free implementation of the amplifier under test to yield the same output noise as from the amplifier under test. It is Te = Na /kGa B = T0 ( F − 1).

The system noise factor Fsys involving the DUT and power indicator can be calculated from the ENR and the Y factor. Fsys =

ENR Y −1

(12.107)

A calibration measurement using a through-connection instead of the DUT reveals the noise factor F2 of the noise meter. One possible implementation of the noise meter is a modern spectrum analyzer. To obtain correct measurement results, the properties of the DUT (noise factor F1 , gain Ga1 ), the noise source (excess noise ratio ENR) and the noise meter (noise factor F2 ) must comply with the following relation. ENR > F1 > F2 /G a1

(12.108)

The noise figure of a spectrum analyzer used as a noise meter can be improved with a low-noise preamplifier. Assuming the example values of Table 12.10, the noise factor of the spectrum analyzer is improved from 1000 to 2.41. Noise measurements are based on very low RF levels, and the best possible shielding is an important requirement. If the noise source uses a standard laboratory power supply, then a low-pass filter in front of its bias connector is important. Some spectrum or network analyzers may come with an integrated AGC. To keep the gain control from altering the noise figure F1 of the instrument, this automatic feature should be switched to manual operation. Unlike spectrum analyzers, most network analyzers have a double side-band architecture, whereby the received noise is actually measured at two frequency bands and internally correlated in the analyzer, which may lead to considerable deviations. Noise is random in nature, which makes noise reading unstable. Averaging the rms values of several measurements instead of using a very small bandwidth can help to overcome this. A reduced bandwidth may help to improve the noise figure of the analyzer but may require a higher number of averages to yield a stable readout. The measurement bandwidth should be selected to be smaller than the DUT’s bandwidth because otherwise the calibration measurement (through-connection) would differ in bandwidth as compared to the DUT measurement. The ENR values of a noise source vary over frequency. They have to be provided with the source. Typical uncertainties for these values are in the range of 0.15 dB. But the characterization of the ENR values is done at temperature T0 , where the application exhibits a room temperature different from T0 . More important is the fact

640

Amplifier measurements

that characterization relies on a noise meter with 50  input impedance while typical DUTs exhibit different input impedances. This mismatch error is the most important contribution to measurement uncertainty. A similar problem is the remaining impedance difference between hot and cold state which is significant for high ENR sources because they are not equipped with an internal attenuator. The Y factor method relies on relative level measurements. Therefore, the linearity of the noise meter is a very important prerequisite that can be violated using an improper preamplifier. The DUTs discussed here (PAs) are typically operated in the nonlinear region. This would lead to intermodulation between carrier signal and noise. Furthermore, it will violate the constant gain assumption that has been made on the right hand side of equation (12.102). This topic far exceeds the scope of this section; a recent discussion can be found in reference [24].

12.7.3

Noise parameters The simple noise figure is based on the assumption that the noise PNa internally added by the amplifier under test is constant. But practical measurements show that this is affected by the source impedance. The actual noise figure performance of the device in its operating environment will be determined by the match of adjacent system components. The noise factor F of an amplifier depends on the complex source reflection coefficient  s as stated by the following equation   s − opt 2 4Rn F = Fmin +     Z 0 1 + opt 2 1 − |s |2

(12.109)

where Fmin is the minimum noise factor,  opt is the optimum complex reflection coefficient, Rn is the noise resistance and s is the complex source reflection coefficient. The quantities Fmin ,  opt , and Rn are referred to as the noise parameters. With given noise parameters and a fixed expected noise factor F, formula (12.109) leads to a circle in the  s Smith chart similar to those presented in Figure 12.19 (Section 12.4). But the minimum noise figure does not necessarily occur at either the system impedance Z0 or at the conjugate match impedance that maximizes gain Ga . To determine the three noise parameters and since  opt is complex, a total number of at least four scalar noise figure measurements involving four different source impedances is necessary. The impedance transformation of the noise source can be performed using a microwave tuner. Alternatively, [25] suggests using a 10 dB coupler and three selectable impedance standards to achieve different source reflection coefficients. A calibration measurement must be carried out to determine the noise parameters of the measurement equipment so that they can be separated from the measurement based on formula (12.104). The cold-source method found in reference [26] is a direct noise measurement method that uses the noise source most of the time in its “cold state.” The “hot state” is used only when a scaling factor is required for the procedure.

12.8 Conclusions

641

Through Noise meter Noise source

Th , Tc

DUT

Figure 12.50 Noise parameter measurement setup.

12.8

Conclusions The functional principle of the transistors used to build solid state power amplifiers is based on semiconductor physics. What happens inside the transistor is primarily described by electrical fields and charge flows. Taking the integral over these parameters leads to voltage and current as the first choice description. On the other hand, neither current nor its phase shift can be accurately measured in the microwave range whereas wave quantities are directly accessible by means of vector network analyzers. S-parameters and wave quantities provide an easy understanding of power flows between source, active component and load. Due to the high frequencies measurements must be done in the frequency-domain and in a narrow-band manner to meet the dynamic requirements. It can not be overlooked that S-parameters have not been intended to model nonlinear effects. A mathematical embedding using S-parameters is not generally valid within the context of power amplifiers. Furthermore, observed S-parameters will depend on the applied power levels and modulation patterns. But a valid S-parameter description can be measured for a specific set of operating parameters. Consequently, traditional network analyzers can be supplemented by the following components: r a load- and source-pull system to provide the embedding physically to the DUT (e.g., to determine the optimum  L and  G from several S-parameter measurements); r a power sensor as a traveling standard for power calibration (e.g., to determine the 1 dB compression point from an s21 power sweep); r a modulated or pulsed signal source to mimic the application-specific driving signal (e.g., to observe pulsed S-parameters or to carry out hot S-parameter measurements); r a monitored DC supply to observe DC current and voltage (e.g., to calculate the PAE). Besides S-parameters, other frequency domain parameters like harmonic distortion and intermodulation distortion can be measured. These parameters rely on the multifrequency response that is generated by the nonlinearities from a single or two-tone stimulus. If performed by a large-signal network analyzer these multifrequency responses can be combined to form a time-domain result. It is than possible to plot voltage and current versus time which are the most meaningful parameters to observe the functionality of a power amplifier (class A, class AB, class B identification, conduction angle, and dynamic load line). Finally, applications come with their own specific quality criteria like adjacent channel power ratio, noise-power ratio, error vector magnitude, bit error ratio and symbol error

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ratio. These are defined on particular measurement setups using a specified modulation pattern and channel coding. This chapter has provided an overview of not only what is meant by these various measurement parameters but, more importantly, how they are actually measured in practice, what equipment setup is needed to perform the measurement, and what errors exist in the measurement process and how these can be minimized.

References 1. T. Reichel, “Voltage and Power Measurements”, Rohde & Schwarz GmbH & Co. KG, Munich, Germany, Sept. 1999 [Online]. Available at: www.rohde-schwarz.com. 2. W. Buschbeck, “Hochfrequenz-Wattmeter und Fehlanpassungsmesser mit direkter Anzeige [translation: RF power meter and mismatch tester with direct indication],” Hochfrequenz und Elektroakustik vol. 61, no. 4, p. 93, 1943. 3. K. Hupfer, “Anordnung zum Messen der vor- und r¨ucklaufenden Welle auf einer Hochfrequenzleitung [translation: Configuration for measurement of incident and reflected wave of a transmission line],” patent DE 42 39 740 C1, grant of patent 23. June 1994. 4. M. Hiebel, “Fundamentals of Vector Network Analysis,” Rohde & Schwarz GmbH & Co. KG, Munich, Germany, 4th Edn., 2008, sample chapter at: www.books.rohde-schwarz.com. 5. Anonymous, “IEEE standard for precision coaxial connectors (DC to 110 GHz),” The Institute of Electrical and Electronics Engineers Inc. IEEE-Standards Board, IEEE Std 287TM-2007, Sept. 2007. 6. G. A. Kouzaev, M. J. Deen, N. K. Nikolova, H. Ali and A. H. Rahal, “Cavity models of planar components grounded by via-holes and their experimental verification,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 3, pp. 1033–1042,. March 2006. 7. V. Sokol and K. Hoffmann, “Improvement of microstrip open-end calibration,” Radioelektronika 2003 – Conference Proceedings Brno: VUT v Brne, FEI, Ustav radioelektroniky, 2003, pp. 245–248. 8. N. Benahmed and N. Benmostefa, “Design directional couplers for high-power applications,” Microw. & RF, pp. 90–98, Oct. 2006. 9. Anonymous, “ISO/IEC Guide 98-3:2008 Uncertainty of measurement – Part 3: Guide to the Expression of Uncertainty in Measurement” (GUM, 1995), International Organization for Standardization, Geneva, Switzerland, first edition 2008, reissue with minor corrections of the 1995 version of Guide to the Expression of Uncertainty in Measurement (GUM), International Organization for Standardization, Geneva, Switzerland 10. O. Ostwald “T-check accuracy test for vector network analyzers utilizing a Tee-junction,” Application Note 1EZ43, Rohde & Schwarz GmbH & Co. KG, Munich, Germany, version 0E, June 1998 [Online]. Available at: www.rohde-schwarz.com. 11. J. M. Rollet “Stability and power gain invariants of linear two-ports,” IRE Trans. Circuit Theory, vol. CT-9, no. 3, pp. 29–32. Mar. 1962. 12. M. L. Edwards and J. H. Sinsky “A new criterion for linear 2-port stability using a single geometrically derived parameter,” IEEE Trans. Microw. Theory Tech., vol. 40, no. 12, pp. 2303–2311, Dec. 1992. 13. D. E Bockelman and W. R Eisenstadt, “Combined differential and common-mode scattering parameters: theory and simulation,” IEEE Trans. Microw. Theory Tech., vol. 43, no. 7, pp. 1530–1539, July 1995.

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14. J. Frei, X.-D. Cai, and S. Muller, “Multiport S-parameter and T-parameter conversion with symmetry extension,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 11, pp. 2493–2504, Nov. 2008. 15. S. Winder, “Single tone intermodulation testing,” RF Des., pp. 34–44, Dec. 1993. 16. D. Agahi, W. Domino, and N Vakilian: “Two-tone versus single-tone measurements of secondorder nonlinearity,” Microw. J., pp. 82–94, Mar. 2002. 17. M. Van den Bossche, “Workshop: ZVxPlus application – PA design,” NMDG nv, Cesar van Kerckhovenstraat 110 – Bldg 5, B-2880 Bornem, Belgium [Online]. Available at: www.nmdg. be/ZVxPlus.html 18. T. Gasseling, D. Barataud, S. Mons, J.-M. Nebus, J. P. Villotte, J. J. Obregon, and R. Quere, “Hot small-signal S-parameter measurements of power transistors operating under large-signal conditions in a load-pull environment for the study of nonlinear parametric interactions,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 3, pp. 805–812, Mar. 2004. 19. J. Martens and P. Kapetanic, “Probe-tone S-parameter measurements,” IEEE Trans. Microw. Theory Tech., vol. 50, no. 9, pp. 2076–2082 Sept. 2002. 20. B. Kaehs, “The crest factor in DVB-T (OFDM) transmitter systems and its influence on the dimensioning of power components,” Application Note 7TS02, Rohde & Schwarz GmbH & Co. KG, Munich, Germany, Jan. 2007, version 2E [Online]. Available at: www.rohde-schwarz. com. 21. J. Wolf, “Measurement of adjacent channel power on wideband CDMA signals,” Application Note 1EF40, Rohde & Schwarz GmbH & Co. KG, Munich, Germany, Mar. 1998, version 0E [Online]. Available at: www.rohde-schwarz.com. 22. R. Minihold: “Testing S-paramters on pulsed radar power amplifier modules,” Application Note 1MA126, Rohde & Schwarz GmbH & Co. KG, Munich, Germany, Feb. 2009, version 0E [Online]. Available at: www.rohde-schwarz.com. 23. H. T. Friis, “Noise figures of radio receivers,” Proc IRE, vol. 32, no. 7, pp. 419–422, July. 1944. 24. L. Escotte, E. Gonneau, C. Chamborn, and J. Graffeuil, “Noise behavior of microwave amplifiers operating under nonlinear conditions,” IEEE Trans. Microw.Theory Tech., vol. 53, no. 12, pp. 3704–3711, Dec. 2005. 25. L. F. Tiemeijer, R. J. Havens, Randy de Kort, and A. J. Scholten, “Improved Y-factor methode for wide-band on-wafer noise-paramater measurements,” IEEE Trans. Microw. Theory and Tech., vol. 53, no. 9, pp. 2917–2925, Sept. 2005. 26. A. C. Davidson, B. W. Leake, and E. Strid, “Accuracy improvements in microwave noise parameter measurements,” IEEE Trans. Microw. Theory Tech., vol. 37, no. 12, pp. 1973– 1978, Dec. 1989.

About the authors

Mustafa Akkul Mustafa Akkul achieved BSc, MSc. and Ph.D. degrees in Electrical and Electronics Engineering from Middle East Technical University, Ankara-Turkey in 1989, 1991, and 1999, respectively. Currently employed as the manager of Microwave Products Division, Aselsan A.S.-Turkey. Major interest areas are MIC/MMIC power amplifiers for radar and EW applications, Tx /Rx modules for phased array systems, transceiver and multifunction module designs for military applications.

Inder J. Bahl Inder J. Bahl received his Ph.D. degree in Electrical Engineering from the Indian Institute of Technology, Kanpur, India in 1975. He joined the ITT Gallium Arsenide Technology Center in 1981 and has been working on microwave and millimeter wave GaAs ICs since then. At Cobham (formerly ITT GTC/Tyco Electronics), in his present capacity as a Distinguished Fellow of Technology, his interests include device modeling, highefficiency high-power amplifiers (HPAs), broadband HPAs, high-power limiter/LNAs, compact and low-loss multibit phase shifters, 3D MMICs, and development of MMIC products for commercial and military applications. Dr. Bahl is the author/coauthor of over 155 research papers. He authored/coauthored 14 books and holds 16 patents. He is an IEEE Fellow and a member of the Electromagnetic Academy. He is the Editor of the International Journal of RF and Microwave Computeraided Engineering.

¨ Wolfgang Bosch In March 2010 Professor Dr. Wolfgang B¨osch joined the Graz University of Technology in Austria to establish a new Institute for Microwave and Photonic Engineering. Previously he has been the CTO of the Advanced Digital Institute in the UK, a not-forprofit organization to promote research activities in the Yorkshire/Humberside Region. He has also been the Director of Business and Technology Integration of RFMD UK. For more than nine years he has been with Filtronic plc as Chief Technology Officer

About the authors

645

of Filtronic Integrated Products and Director of the Global Technology Group. Prior to joining Filtronic, he held positions in the European Space Agency (ESA) working on amplifier linearization techniques for space applications, MPR-Teltech in Canada working on MMIC technology projects and in 1991 he had joined the Corporate R&D group of M/A-COM in Boston where he worked on advanced topologies for high-efficiency power amplifiers. From 1996 to 1999 he was with DaimlerChrysler Aerospace in Germany, working on T/R Modules for airborne radar. Wolfgang received his engineering degrees at the Technical University of Vienna and Graz/Austria. He finalized his MBA with distinction at Bradford University School of Management in 2004. For several years he was on the Supervisory Board of the EMRS Defence Technology Centre in the UK, he is a Senior Member of the IEEE, a Fellow of the IET and a panel member of the EPSRC. He has published more than 40 papers and holds four patents. He was a Non-Executive Director of Diamond Microwave Devices (DMD) and is currently a Non-Executive Director of the Advanced Digital Institute (ADI) and VIPER Company.

Wayne Burger Wayne Burger received a Ph.D. in Electrical Engineering from the Massachusetts Institute of Technology in 1987, with his thesis work focusing on the deposition and characterization of low temperature silicon epitaxial films. After working on front-end process integration for BiCMOS SRAMs at National Semiconductor for two years, he joined Motorola’s Semiconductor Product Sector (which later became Freescale Semiconductor) in 1990. Early projects at Motorola include 0.60 μm CMOS, 0.35 μm BiCMOS, and SiGe bipolar development. He has been manager of the RF-LDMOS Device Development team at Freescale Semiconductor since 1994. During this time, RF-LDMOS has evolved into the dominant RF power transistor technology for the cellular infrastructure market, and is now expanding into adjacent RF power markets. Wayne has authored, coauthored, or presented at numerous conferences, workshops, and technical journals on the topic of RF-LDMOS device technology and applications. He is a Distinguished Member of the Technical Staff at Freescale and a member of the IEEE.

Steve C. Cripps Dr Steve C. Cripps obtained his Ph.D. from Cambridge University, England. He worked for Plessey Research (now GECMM) on GaAsFET hybrid circuit development. Later he joined Watkins-Johnson’s solid state division, Palo Alto, CA, and has held Engineering and Management positions at WJ, Loral, and Celeritek. During this period, he designed the industry’s first 2–8 Ghz and 6–18 Ghz 1 W solid state amplifiers, and in 1983 published a technique for microwave power amplifier design, which has become widely adopted in the industry. In 1990 he became an independent consultant and was active in a variety of commercial RF product developments, including the design of several cellular telephone power

646

About the authors

amplifier MMIC products. In 1996 he returned to England, where his consulting activities continue to be focused in the RF power amplifier area. In 2006, Dr. Cripps published a second edition of his best-selling book, RF Power Amplifier Design for Wireless Communications (Artech House). He is currently vicechair of the High Power Amplifier subcommittee of the Technical Co-ordination and Technical Program Committees of the IEEE Microwave Theory and Techniques Society, and writes the regular “Microwave Bytes” column in the IEEE Microwave Magazine. He is the recipient of the 2008 IEEE Microwave Applications Award. Dr. Cripps is a professorial research fellow at Cardiff University, UK. He is a Fellow of the IEEE.

Rob Davis Rob Davis is a senior manager at RF Micro-Devices in County Durham, UK. His primary technical interests lie in the areas of III–V semiconductor device engineering and the development of compact models for circuit design. He received B.Sc. and Ph.D. degrees in Physics from the University of Lancaster in 1983 and 1987, respectively. He began his career at the Royal Signals and Radar Establishment at Malvern in 1986 where he was engaged in device research gaining experience in a variety of compound semiconductor FET and bipolar devices. In 2000 he joined Filtronic Compound Semiconductors Ltd., now RFMD (UK) Ltd. Here his work has included the development of GaAs pHEMT MMIC processes and he currently leads the device and test engineering functions.

Christopher P. Dragon Christopher P. Dragon received a bachelor’s degree in Electrical Engineering from Louisiana State University and went on to receive a Masters of Engineering in Microelectronic Engineering from Rochester Institute of Technology. In 1991, he began his career in an RF development division of Motorola’s Semiconductor Products Sector in Phoenix, Arizona. It was at this time that the first RF-LDMOS transistor was developed and launched into production. Chris has remained working on the development of RF-LDMOS devices for cellular basestation applications throughout his career up to the present where the work continues at Freescale Semiconductor in Tempe, Arizona. He has been involved with and overseen the development of eight generations of RF-LDMOS devices. Chris is a Senior Member of the Technical Staff at Freescale Semiconductor and a member of the IEEE.

Dominic FitzPatrick Dominic FitzPatrick has been involved with the design of solid state microwave amplifiers for over 25 years. He graduated from the Portsmouth Polytechnic, England, in 1984

About the authors

647

joining Pascall Electronics and in 1988 returned to Portsmouth to undertake a Masters in Solid State Microwave Physics. After working for a small consultancy, he joined Wessex Electronics, eventually becoming Technical Director. In 1999, he joined Milmega to head up the engineering department, and early in 2004, he was part of the successful management buy-out team. Leaving at the end of 2006 Dominic returned to academia to pursue a Ph.D. in Novel Wideband Amplifier Design Techniques at Cardiff University.

Michael G. Hiebel Michael G. Hiebel was born in Munich (Muenchen) Germany in 1970. He received the diploma degree in Electrical Engineering from the Munich University of Technology. Since 2003 he is a member of the Institute of Electrical and Electronics Engineers IEEE and senior member since 2011. Mr. Hiebel is a member of the VDE (German Electrical Engineering Association), as well. He has been employed by Rohde & Schwarz GmbH & Co. KG in Munich since 1999 and is currently a senior development engineer, focusing on vector network analyzers. His main interests are vector network analyzer calibration techniques, nonlinear device measurement (mixers, power amplifiers, and oscillators) and millimeter wave network analysis. Since 2006 he is involved as a teacher in the company’s professional training program. He contributes to a periodic course on RF engineering at the Carl-Cranz-Gesellschaft in Wessling (Southern Germany). He has written a number of articles, scientific contributions, white papers, and application notes. He is author of the book Fundamentals of Vector Network Analysis (c.420 pages), which is published by Rohde & Schwarz in English, German, Chinese, and Russian.

Stephen Maas Stephen Maas received BSEE and MSEE degrees in Electrical Engineering from the University of Pennsylvania in 1971 and 1972, respectively, and a Ph.D. in Electrical Engineering from UCLA in 1984. He joined the National Radio Astronomy Observatory in 1974, where he designed the low-noise receivers for the Very Large Array radio telescope. Subsequently, at Hughes Aircraft Co. and TRW, he developed low-noise microwave and millimeter-wave systems and components, primarily FET amplifiers and diode and FET mixers, for space communication. He has also been employed as a Research Scientist at The Aerospace Corp., where he worked on the optimization of nonlinear microwave circuits and the development of circuit-design software based on harmonic-balance, Volterra-series, and time-domain methods. Dr. Maas joined the UCLA Electrical Engineering Faculty in 1990, left it in 1992. He is currently Chief Scientist of AWR Corp. and also consults independently. Dr. Maas is the author of Microwave Mixers (Artech House, 1986 and 1992), Nonlinear Microwave Circuits (Artech House, 1988 and 2003), The RF and Microwave Circuit Design Cookbook (Artech House, 1998), and Noise in Linear and Nonlinear Circuits (Artech House, 2005). From 1990 until 1992 he was the editor of the IEEE Transactions

648

About the authors

on Microwave Theory and Techniques, and from 1990–3 was an Adcom member and Publications Chairman of the IEEE MTT Society. He received the IEEE MTT Society’s Microwave Prize in 1989 for his work on distortion in diode mixers and its Application Award in 2002 for the invention of the FET resistive mixer. He is a Fellow of the IEEE.

Mali Mahalingam Mali Mahalingam received the Ph.D. degree in Physics from Carnegie-Mellon University. Currently, he is manager of Packaging Operations, Radio Frequency Division, Freescale Semiconductor Inc. focusing on high-power RFPAs for wireless markets. He has 31 years of experience in packaging, assembly, and manufacturing technologies in the semiconductor industry of which the initial 25 years were with Motorola Inc. Mali has made numerous contributions to both technology development and their successful implementation in products. His technical accomplishments are spread to thermal, mechanical, materials, electrical, simulation/validation and computer-aided design disciplines. He has earned world-class recognition for his pioneering work in thermal technology applied to micro-electronics. He has published 70 + technical papers and has three issued patents. Mali has taught professional courses on packaging and thermal technology at universities and electronic manufacturing plants. He has mentored graduate level research at universities. He is an IEEE Fellow.

Daniel P. Myer Daniel P. Myer is President and Founder of Communication Power Corporation (CPC, www.cpcamps.com). He received his B.S. in Electrical Engineering from Polytechnic University in Brooklyn, New York, and an A.A.S. from S.U.N.Y. Farmingdale, New York. Mr. Myer is the author of over 15 technical papers, coauthored several books (Classic Works in RF Engineering, Artech House 2006, coeditor/author, Encyclopedia of Magnetic Resonance, John Wiley, coauthor) and has been issued two US patents. In 1990 and 1992, he introduced a new topological network synthesis procedure for equal delay transmission line transformers along with the fundamental realization criteria. Prior to founding CPC, Mr. Myer was an RF design engineer at M/A-COM Microwave Power Devices (MPD) and Comtech/PST where he codesigned high-power solid-state RF amplifiers for high-profile military programs such as Rivet Rider (Commando Solo), employed in the USAF’s Airborne EC-130E based, psychological warfare programs. In addition, Mr. Myer codeveloped RF amplifiers for use in marine search radar, missile command/destruct, L-band airborne radar tracking, submarine position emergency radio beacon and multicarrier feed-forward networks for cellular phone/wireless base-stations.

Bill Roesch Bill Roesch has a bachelor of science degree in Electrical and Computer Engineering from Oregon State University. He started his engineering career at Tektronix;

About the authors

649

scrutinizing purchased component reliability for five years. In 1985, Bill joined TriQuint Semiconductor to explore aging, stressing, analyzing, and improving GaAs devices. Bill is a 25-year contributing member of JEDEC and he is also a member of the IEEE. Bill has numerous publications, tutorials, and conference presentations on Compound Semiconductor reliability and he has received nine different best paper awards. For his innovative reliability techniques and device physics insight, Bill was recently inducted into the Oregon State University Academy of Distinguished Engineers. For twelve years, Roesch guided the quality and reliability engineering group at the Hillsboro, Oregon, factory. In 2007, he moved from management back onto the technical ladder and in 2009, Bill was designated a TriQuint Senior Fellow in Reliability.

Robert J. Trew Robert J. Trew is the Alton and Mildred Lancaster Distinguished Professor of Electrical and Computer Engineering at North Carolina State University, Raleigh. He received his Ph.D. degree from the University of Michigan in 1975. He has served as the ECE Department Head at North Carolina State University, Virginia Tech, and Case Western Reserve University. Dr. Trew is currently serving as the Director of the Electrical, Communications, and Cyber-Systems Division in the Engineering Directorate of the US National Science Foundation. From 1997 to 2001 he was Director of Research for the US Department of Defense, with management oversight responsibility for the $1.3 billion yearly basic research programs of DOD. Dr. Trew served as Vice-Chair of the US Government interagency committee that planned the US National Nanotechnology Initiative (NNI). Dr. Trew is a Life Fellow of the IEEE, and was the 2004 President of the IEEE Microwave Theory and Techniques Society. He is currently the editor-in-chief of the IEEE Proceedings and previously served as editor-in-chief of the IEEE Transactions on Microwave Theory and Techniques and was founding coeditor-in-chief of the IEEE Microwave Magazine. Dr. Trew was twice been named an MTT Society Microwave Distinguished Lecturer. Awards received by Dr. Trew include the 2001 IEEE-USA Harry Diamond Memorial Award, an IEEE Third Millennium Medal Award, the 1998 IEEE MTT Society Distinguished Educator Award, the 1991 Alcoa Foundation Distinguished Engineering Research Award, and a 1992 NCSU Distinguished Scholarly Achievement Award. He received an Engineering Alumni Society Merit Award in Electrical Engineering from the University of Michigan in 2003. He has published over 170 articles, 21 book chapters, and has given over 390 conference/workshop presentations. Dr. Trew has 10 patents.

John Walker John Walker received his BSc, MSc, and Ph.D. degrees from the University of Leeds in 1971, 1972, and 1976, respectively. In 1974 he joined GEC Hirst Research Centre where he worked on the design of microwave transistor amplifiers before becoming Group Leader of IMPATT diodes and oscillators and, finally, Chief Engineer of the

650

About the authors

Compound Semiconductor laboratory. In 1984 he joined Thorn-EMI Electronics as Microwave Hybrids Manager. In 1995 he moved to Semelab as RF Division Manager where he was responsible for all commercial and technical aspects of the company’s RF power transistor products. In 2011, he became European Sales Manager for Integra Technologies, Inc. He is the editor and coauthor of the books High-Power GaAs FET Amplifiers and Classic Works in RF Engineering, both published by Artech House. John is a Fellow of the IEE and a Senior Member of IEEE.

Index

Abaqus FEA, 432 acceleration factors, 446, 458–473, 504 current, 462–465 current density, 464 determination, 460–461 in gallium arsenide processes, 500 highly accelerated stress test, 492 humidity, 488–492 see also electric field acceleration factor; RF bias acceleration; thermal acceleration; voltage acceleration acceptance test procedures (ATPs), 282 ACLR see adjacent channel leakage power ratio (ACLR) ACPR see adjacent channel power ratio (ACPR) activation energy, 461–462 active harmonic load-pull, 620, 621 active load-pull schematics, 563–564 active systems, 619–620 adapters de-embedding, 593 inserted after calibration, 589–591 removal techniques, 592 adhesives, electrically conductive, 285 adjacent channel leakage power ratio (ACLR), 110–111 limits, 522 specifications, 517 adjacent channel power ratio (ACPR), 625–629 code division multiple access, 629 concept of, 625 determination, 626 measurements, 626 spectrum analyzers, 627, 628 test results, 629 adjacent channel powers integrated, 626–627 weighted, 626–627 admittance (Y) parameters, 189 applications, 206 in database models, 212 AGC (automatic gain control), 570 air flow fields, mobile phones, 414–415

ALC (automatic level control), 576 ALC (automatic level controlled) loops, 283 AlGaAs see aluminium gallium arsenide (AlGaAs) AlGaN/GaN HFETs see aluminium gallium nitride/gallium nitride heterostructure field effect transistors (AlGaN/GaN HFETs) Allegro Package Designer, 432 AlN (aluminium nitride), applications, 316–318 Alodine, 294 aluminium advantages, 452 applications housings, 294, 311 metallization, 451–452 electromigration, 30–31 surface treatment, 294 thermal conductivity, 311 aluminium alloy 4047, applications, housings, 294 aluminium alloy 6061, applications, housings, 294 aluminium gallium arsenide (AlGaAs) bandgap, 43 crystal structure, 43–44 properties, 43 aluminium gallium nitride/gallium nitride heterostructure field effect transistor amplifiers, 123–125 current waveforms, 139–142 drain current, 138 efficiency, 138 gain, 138 operation, 136–137 performance, 123–125 RF, 123, 124, 137–139 RF drain current, 140, 142–143 RF drain voltage, 139–142 RF gate current, 139, 143 RF gate voltage, 139–142 RF power input, 138, 139 output, 123–124, 138 source resistance, 142, 143 nonlinear, 143 voltage waveforms, 139–142

652

Index

aluminium gallium nitride/gallium nitride heterostructure field effect transistors (AlGaN/GaN HFETs) advantages, 119–120, 123 applications, 105–106, 110–111 microwave power amplifiers, 105 power amplifiers, 111 avalanche ionization, 145 background, 108–111 channel current, 146, 148 current conduction degradation, 145–146 current–voltage relationships DC, 137 gate and drain, 150–151 development, 110–111 drain current, 150–151 electric field magnitudes, 144–145 electron tunneling, 144–145 fabrication, 108–110, 119–120 future trends, 152–153 gate current, 148, 150–151 gate edge, electric fields at, 149 gate electron leakage paths, 145 gate leakage, 146 current paths, 149 gate tunnel leakage model, 147–148, 150 gate-to-source capacitance, 135 materials, parameters, 114 performance, 108–110, 124–125 polarization effects, 110 power output, changes, 472 resistances drain, 135–136 source, 135–136 resistivity, 132 RF power, output, 124, 146 saturation fields, 114 space-charge effects, 133 structure, 119 sudden reliability problem, 146–147 surface trap-to-trap hopping conduction, 149, 150 virtual gate effect, 145 aluminium nitride (AlN), applications, 316–318 AM/AM measurements, 632 AM/PM measurements, 632 amplifiers bias screening, 505 booster, 597–598 burn-in, 505 Class H, 161 classification classes A to S, 159–186 development, 159 and efficiency, 160 historical background, 159

inverted modes, 179–180 issues, 184–186 multimodes, 184–186 current waveforms, 185 defect-related problems, 447 distributed, 340–341 gain definitions, 599–602 humidity acceleration factors, 488–492 measurements, 570–642 reliability issues, 447 switch modes, 159 voltage waveforms, 185 wear-out, 447 see also aluminium gallium nitride/gallium nitride heterostructure field effect transistor amplifiers; Class A amplifiers; Class AB amplifiers; Class B amplifiers; Class C amplifiers; Class E amplifiers; Class F amplifiers; Class G amplifiers; Class J amplifiers; Class S amplifiers; Doherty amplifiers; hybrid amplifiers; power amplifiers (PAs); push-pull amplifiers; 4H-silicon carbide metal semiconductor field effect transistor amplifiers; transistor amplifiers amplitude–phase conversion, nonlinear, 512 Angelov–Chalmers model, 86 ANSYS, 432 ANSYS FLUENT, 432 ANSYS Icepak, 432 antenna towers, 416–417 apertures and group delay, 603–604 stepwidth, 603–604 Arrhenius equation, 460–461 ATPs (acceptance test procedures), 282 attenuators diode sensors, 571 high-power, 577 in high-power RF measurements, 576–579 disadvantages, 578 and power sensors, 576–577 scattering parameters, 596 self-heating, 578 step, 587–588 AutoCAD, 432 automatic differentiation, applications, 222 automatic gain control (AGC), 570 automatic level control (ALC), 576 automatic level controlled (ALC) loops, 283 autotransformers, 553 avalanche breakdown, 25 concept of, 23 use of term, 18 average efficiency, 278

Index

Class A amplifiers, 164 definition, 510 determination, 510–511 average power, 624 average pulse method, 633–634 back substitution, 191 backgating, 454 balanced mode configuration, vs. Doherty configuration, 529 balanced one-port devices, 610 balanced power amplifiers, 340–341, 544–550 configurations, 544–545 as power combiners, 546–547 balanced two-port devices, 610 balanced–balanced transformers, 556–557 ballast resistors, 216 baluns, 552 active, 610–611 configurations, 556 Guanella, 554 passive, 610–611 structure, 558 two-hole cores, 553–554 bamboo regime, use of term, 31–32 bandpass filters, 586, 604 barretters, 571 base stations see radio base stations (RBSs) bathtub curves, 412, 455–456, 457 regions, 412–413, 456–457 Beatty standard, 598–599 BeO (beryllium oxide), applications, 316–318 BER (bit error rate), 635–636 beryllium oxide (BeO), applications, 316–318 bias decoupling, 349–352 bias networks, 350 configurations, 345–347 constant impedance, 351 FETs, 249–250 GaAs FETs, 250 GaN FETs, 250 in microwave hybrid power amplifiers, 345–353 requirements, 345 transistors, 345, 346 bias screening, amplifiers, 505 biasing narrow band designs, 349 sequences, 347 vs. RF performance, 348–349 bipolar junction transistors (BJTs), 249 applications, RF power amplifiers, 161–162, 282 cross-sections, 433 disadvantages, 246–247, 255 materials, 106 stable thermal operating points, 216, 217

653

see also heterojunction bipolar transistors (HBTs); 4H-silicon carbide bipolar junction transistors (4H-SiC BJTs) bit error rate (BER), 635–636 BITE (built in test), applications, 353 BJTs see bipolar junction transistors (BJTs) black-box models, 89 Black’s equation, 30–31, 33, 463 generalization, 463–464 parameters, 32 bolometers, principles, 571 bond wires DC fusing current, 220 impedance determination, 220 as inductors, 219–220 models, 399 in power amplifier models, 219–221 booster amplifiers, 597–598 bootstrap configuration, 555–556 box truncations, 224 branchline couplers, 328–331, 349 impedance transforming, 549 branchline quadrature hybrids, 547–549 characteristic impedance, 547–548 frequency response, 548 output impedances, 548–549 performance, 548 breakdown curves, on-state vs. off-state, 24 breakdown voltage–frequency relationships, 45–46, 47 breakdown voltages, 57–58 capacitors, 469, 470 definition, 57 RF power transistors, 246, 248 silicon nitride films, 466 see also drain-to-source breakdown voltage (BVds ); gate-to-drain breakdown voltage (BVgd ); gate-to-source breakdown voltage (BVgs ) breakdown walkout, use of term, 59 breathing, and moisture ingress, 296 built in test (BITE), applications, 353 burn-in, 457–458, 504–505 amplifiers, 505 use of term, 504–505 BVds see drain-to-source breakdown voltage (BVds ) BVgd see gate-to-drain breakdown voltage (BVgd ) BVgs see gate-to-source breakdown voltage (BVgs ) CAD see computer-aided design (CAD) Cadence, 432 calibration adapters inserted after, 589–591 with different connector types, 589–593 high-power setups, 596–598

654

Index

CAD (cont.) with PCBs, test fixtures and wafer probes, 593–596 standards, 590 techniques, properties, 592 through–open–match, 598–599 see also unknown–open–short–match (UOSM) calibration capacitors applications, 318–320 breakdown voltages, 469, 470 chip, 265–267 closed-form models, 209–210 defects, 483 as distributed components, 324 equivalent circuits, 209 high-Q, 353–355 ideal, 320 interdigital, 367, 368–369 lifetimes, predictions, 471 losses, 219 lumped, 367 microstrip, 368–369 in microwave hybrid power amplifiers, 318–321 in MMICs, classification, 368–369 modeling, 315 plate orientation effects, 318–320 quality factor, 320 ramp to failure data, 467 scattering parameters, 206–207 voltage acceleration, 487–488 see also metal–insulator–metal (MIM) capacitors; multilayer capacitors (MLCs); silicon nitride capacitors; single-layer capacitors (SLCs) capillary action, and moisture ingress, 296 cascaded tuner method, 620 castings, housings, 303 CCDF (complementary cumulative distribution function), 624, 625 CDMA see code division multiple access (CDMA) CDPD (cellular digital packet data), 513 Cds see drain-to-source capacitance (Cds ) cell interconnections, modeling, in large devices, 213–214 cell phones see mobile phones cellular digital packet data (CDPD), 513 cellular telephony see mobile telephony ceramic packages air-cavity surface-mount, 392–393, 394 applications, in MMIC PAs, 391, 392, 393 assembly, 398 flow, 400 configuration, 393 cost factors, 393 design, 391–393 issues, 391

development, 390–391 low-cost, 394 manufacture, 393–394 flow processes, 396 materials, 391 properties, 391 multi-lead, 392–393 properties, 392 substrates, 392–393 types of, 390–391 ceramics, applications, packaging, 82, 390–394 CFD see computational fluid dynamics (CFD) CFs see crest factors (CFs) Cgd see gate-to-drain feedback capacitance (Cgd ) Cgs see gate-to-source capacitance (Cgs ) channel power measurement, 627 see also adjacent channel powers chemical mechanical polishing (CMP), 453 chromate conversion, 294 circuit analysis applications, 205 methods, 188–205 integration, 205 software and electromagnetic analysis software, 229 power amplifiers, 188 see also harmonic-balance analysis; linear analysis; nodal analysis; time-domain analysis circuit components, losses, in power amplifier models, 219 circuit metallizations losses calculations, 219 factors affecting, 218–219 in power amplifier models, 217–219 multilayer, 218 circuit simulation accuracy, and passive circuit structures, 205–213 see also nonlinear circuit simulation circulators functional diagrams, 323 in microwave hybrid power amplifiers, 322–323 Class A amplifiers, 162–164 advantages, 164 applications, 161 characteristics, 160 and Class AB amplifiers compared, 164–165 current–voltage relationships, 162 efficiency, 163–164 average, 164, 511 maximum, 510 under power back-off conditions, 164, 180 output power, 163–164

Index

waveforms, 163 zero-knee assumption, 163–164 Class AB amplifiers, 164–171 applications, 161 and Class A amplifiers compared, 164–165 design, 171 issues, 165–166 early studies, 160 efficiency, under power back-off conditions, 169 linearity, 170 issues, 169–170 operation, 170–171 output capacitance, 171 output voltage, 165, 166, 618 supply voltages, 524–525 topology, 170 waveforms, 165 Class B amplifiers, 161, 164–171 efficiency, 166–168, 186, 510, 561 under power back-off conditions, 168–169 inverted mode, 179 operation, 166–168 schematics, 559 waveforms, 167, 562 voltage, 173 zero-bias condition, 168 Class C amplifiers, 160, 171–173 applications, 173 disadvantages, 172–173 efficiency, 160 input voltages, excess, 172 operation, 171 RF power reduction, 171–172 waveforms, 172 Class D amplifiers audio, 161 use of term, 183 Class E amplifiers, 181–183 circuits, 181–182 current waveforms, 181–182 efficiency, 183 operation, 181 research, 183 waveforms, 182 Class F amplifiers, 161, 173–176, 186 design, 176 inverted, 179–180 clipped variations, 181 waveforms, 179, 180 knee region, 175 operation, 173 output capacitance, 175–176 research, 173 topology, 176 voltage waveforms, 173–174 zero-grazing, 174–175

655

waveforms, 175 Class G amplifiers, 161 use of term, 180 Class H amplifiers, 161 Class J amplifiers, 176–179 advantages, 178–179 circuits, 178–179 operation, 176–177 topology, 178 waveforms, 178 voltage, 177–178 Class S amplifiers, 161, 183–184 concept of, 183 configuration bogus, 184 viable, 184 design issues, 183–184 operation, 183 clipping, 514 closed-form models, 208–210 applications, 209 capacitors, 209–210 characteristics, 208–209 planar spiral inductors, 209 strip transmission lines, 210 CMP (chemical mechanical polishing), 453 CMRR (common-mode rejection ratio), 611 CNC machines (computer numerically controlled) machines, applications, housing construction, 303 coaxial connections, 311–312, 554–555 interfacing issues, 595–596 overview, 589 power handling calculations, 312 printed circuit boards, 312, 313 properties, 593 transition parameters, 314 types of, 591, 593 code division multiple access (CDMA), 110–111, 331 adjacent channel power ratio, 629 power output control, 511–512 see also Wideband Code Division Multiple Access (W-CDMA) coefficient of thermal expansion (CTE), joining materials of different, 425–426 cold-source method, 640 cold-wall, use of term, 311 COM (component object model), 229 comb spectra, 634 combining advantages, 344 applications, 344 in Doherty amplifiers, 344 in microwave hybrid power amplifiers, 344 parallel, 334

656

Index

commercial markets, RF power amplifiers, 236 common-mode rejection ratio (CMRR), 611 common-mode signals, 608–610 compensation techniques, 574 complementary cumulative distribution function (CCDF), 624, 625 component object model (COM), 229 components active, 315 integrated, in microwave hybrid power amplifiers, 322 lumped, equivalent circuits, 324, 325 in microwave hybrid power amplifiers, 315–332 passive, 315 distributed, 323–331 lumped, 315–323 reliability, and temperature, 305 see also capacitors; diodes; distributed components; inductors; resistors; transistors; vacuum tubes compression points, 615, 616 computational fluid dynamics (CFD), 431 applications, 431 computer numerically controlled (CNC) machines, applications, housing construction, 303 computer-aided design (CAD) MMIC PAs, 370 power amplifiers, 188–230 tools, 370 condensation, equipment vulnerability to, 294–295 condition numbers, 227 conduction steady-state, 420 and thermal performance, RFPAs, 420–421 three-dimensional, 420–421 see also reduced conduction angle conductors in printed circuit boards, 289 substrate attachment, 289 see also interconnects; vias conformal coatings, 296 conservation of energy equation, 431 conservation of mass equation, 431 conservation of momentum equation, 431 constellation diagrams, 630–631, 632 construction, 631 contact printing, in GaAs FET fabrication, 76 contact thermal resistance concept of, 438–439 factors affecting, 439 pictorial description, 438 reduction strategies, 439 continuation methods in nonlinear circuit simulation, 223 use of term, 223 continuity equations, 128–129

convection heat sinks, 421 and thermal performance, RFPAs, 421–422 convective heat transfer coefficients, 421–422 coplanar waveguide (CPW) applications, 292 in MMICs, 362–363, 365–367 attenuation coefficient, 366 characteristic impedance, 365, 366 dielectric constant, 366 disadvantages, 292 discontinuities, 366–367 modes, 365–366 parameters, 365 copper applications, conductors, 289 electrodeposition, 289 electromigration, 30–31 interdiffusion, 452 metallization, 453 pattern definition, 453 rolled, 289 thermal conductivity, 311 copper bumps, thermal excursions, 478–482 correction factors, 626–627 corrosion, and metallization, 452 cosimulation, 229 COSMOS, 432 coupled-coil transformers, 553–554 equivalent circuits, 553–554 impedances, 553 performance, limitations, 553–554 winding topologies, 553 couplers characteristics, 330 discrete quadrature hybrid, 328, 329 as distributed components, 326–331 in microwave hybrid power amplifiers, 353 rat-race, 559, 560 Wireline, 328, 329 see also branchline couplers; Lange couplers; power combining; quadrature couplers CPW see coplanar waveguide (CPW) crest factors (CFs), 512–514, 624 definition, 513 determination, 624 periodic signals, 624 CTE (coefficient of thermal expansion), joining materials of different, 425–426 current definition, 113–114 see also snapback current current acceleration, 462–465 current density acceleration factors, 464 exponent determination, 465

Index

current density equations, 128–129, 131, 132–133 current distribution, and metal losses, 218 current sense, 348 current transport, DMOSFETs, 10–11 D1020UK (MOSFET) datasheet, 257 drain current vs. temperature, 257, 258–259 gate voltage vs. temperature, 257–258 input/output impedance, 259, 260 thermal tracking circuit, 258 data rates, and efficiency, 520–522 database models, 212 datasheets D1020UK, 257 interpretation issues, 331 RF power transistors, 244–246 DC–DC converters, 348 DCS1800 system, 513 DDE (dynamic data exchange), 229 de-embedding, adapters, 593 DECT (Digital Enhanced Cordless Telecommunications), 513 defect amplification, 482–488 defect-related problems, amplifiers, 447 defects capacitors, 483 liftoff, 483 predicted, 495 types of, 483 vs. wear-out, 475–492 see also failures depletion region, 17–18 GaAs FETs, 61 silicon LDMOSFETs, 5 design balanced, MHPAs, 334 ceramic packages, 391–393 issues, 391 GaAs FETs, 63–74 gallium nitride wide bandgap transistors, 118–125 heat sinking, 308–309 HFETs, 64–65 hypothetical RFPA subsystem modules, 252 MESFETs, 64–65 MHPAs, 333 MMIC PAs, 370–372, 525–526 pHEMTs, 64–65 plastic packages, 395 power amplifiers holistic, 526, 528 overview, 523–526

657

parameter trade-offs, 509–514, 525, 567–568 processes, 525 power FET cells, 67–69 for reliability, 495–500 RF power transistors, 1 RFPAs, 242 silicon carbide wide bandgap transistors, 118–125 silicon LDMOSFETs, 27–39 silicon VDMOSFETs, 27–39 see also computer-aided design (CAD); thermal design design flow barriers to, 229 in nonlinear circuit simulations, 228–230 design for manufacturability (DFM) studies, 282 designers, and failure mechanisms, 447 device junction temperature, 428–429 device pitch, issues, 28–29 devices under test (DUTs) heat radiation, 429–430 power input, 622 power output, issues, 596 radiant energy, 430–431 temperature control, 21 two-port, 581 wave propagation, 580 dew point, 294–295 DF (dissipation factor), 318–320 DFM (design for manufacturability) studies, 282 die attach eutectic, 397 materials, 397, 426–427 methods, 396–397 in MMIC PA package assembly, 396–397 solders, 426–427 thermal resistance, 436–437 uniform, 401 see also flip-chip die attach; gold–silicon die attach; lead–tin–silver die attach die bonding, 493–494 die thickness, and thermal resistance, 436 dielectric constants, and temperature, 287 dielectric layers, in GaAs FET fabrication, 79–80 dielectrics degradation mechanisms, 453–454 failure mechanisms, 453–454 gate, 453–454 properties, 320 dies, in silicon LDMOSFET construction, 2–5 differential equations, in time-domain analysis, 202

658

Index

differential-mode signals, 608–610 diffusion assessment, 455 measurement, 295 and moisture ingress, 295 see also interdiffusion digital baseband pre-distortion (DPD), 514–517, 524, 567–568 block diagrams, 515, 516, 517 disadvantages, 516 feedback loops, 515, 516–517 performance plots, 517, 518 and power amplifier design, 524 power dissipation, 517–518 principles, 515–516 requirements, 516 Digital Enhanced Cordless Telecommunications (DECT), 513 digital-signal processors (DSPs) applications, 515 power consumption, 517–518 diode sensors, 570–571 attenuators, 571 circuit diagrams, 571 fast, 571 input power ranges, 572–573 optimization, 571 diodes DC voltages, 194–195 reliability guidelines, 499 Schottky, 345–347 sinusoidal voltages, 196–198 Zener, 347 directional elements, 582 directivity, 585 frequency range, 585 functions, 582 implementations, 585 test port match, 585 directional power measurements, 576–579 directional power meters, applications, 579 directional power sensors applications, 579 development, 578 directivity, 584, 596–597 determination, 583–584 directional elements, 585 raw, 597 discontinuities coplanar waveguide, 366–367 microstrip, 205, 206–208, 209, 365 simulations, 212 and RF connections, 314 waveguides, 211–212

dispersion-free networks, phase delay, 605 dissipation factor (DF), 318–320 distortion nonlinear, 512–513, 611 see also harmonic distortion (HMD); intermodulation distortion (IMD); linear distortion; pre-distortion distributed amplifiers, 340–341 distributed components, 323–331 capacitors as, 324 couplers as, 326–331 definition, 323–324 equivalent circuits, 324, 325 resistors as, 323–324 transmission lines as, 324 DMOSFETs see double diffused metal–oxide–silicon field effect transistors (DMOSFETs) Doherty amplifiers, 1, 514, 524–525 combining in, 344 development, 563 efficiency, 564–566, 567 for efficient radio base stations, 527–530 future trends, 440–441 main and auxiliary voltages and currents, 566 peaking stage, 173 power output, 566, 567 principles, 561–563 single-stage, 528, 529 Doherty combining, 523, 527, 559–567 efficiency improvement, 529 representations, 563–564, 565 Doherty configuration, vs. balanced mode configuration, 529 double diffused metal–oxide–silicon field effect transistors (DMOSFETs) advantages, 1–2 breakdown voltage, 17–22 current transport, 10–11 current–voltage responses, 10 development, 1–2 device physics, 10–27 heat generation, 33–34 historical background, 1–2 hot carrier injection, 17–22 linear regime on-resistance, 17–22 operating voltage, issues, 26–27 operation, 10 linear region, 19 saturation region, 19 parasitic elements, behavior, 12–17 ruggedness, 22–26 snapback, 22–26 terminals, 10–11 types of, 2

Index

see also lateral double diffused metal–oxide–silicon field effect transistors (LDMOSFETs); vertical double diffused metal–oxide–silicon field effect transistors (VDMOSFETs) DPD see digital baseband pre-distortion (DPD) drain efficiency, 33, 110–111, 559–560 broadband, 279 definition, 36–37, 509–510, 602 drain engineering and ruggedness, 24 use of term, 17 drain switching, high-power amplifiers, 532–533 drain voltage control, 348 drain-to-source breakdown voltage (BVds ), 2–5, 57–58 DMOSFETs, 17–22 high, designing for, 18 increase, 56 LDMOSFETs, 5 mechanisms, 17–18 optimization, 65–66 and ruggedness, 23 use of term, 17 drain-to-source capacitance (Cds ), silicon LDMOSFETs, 5, 15–16 DSPs see digital-signal processors (DSPs) DUTs see devices under test (DUTs) dynamic data exchange (DDE), 229 dynamic load lines, 618 dynamic range, 628–629 power sensors, 574 RF power amplifiers, 237–238 vector network analyzers, 616 ED see electrodeposition (ED) edge coupling, 290–291 EDGE (Enhanced Data Rates for Global Evolution), 508–509 EEFET3 model, 86 EEHEMT model, 86 EER (envelope elimination and restoration) schemes, 514 efficiency and amplifier classification, 160 Class A amplifiers, 511 collector, 509–510 and data rates, 520–522 Doherty amplifiers, 564–566, 567 enhancement, 514 and gain, 36–37 instantaneous, 510 measurement, 602–603 peak, 511 power amplifiers, 508, 524–525, 567–568 factors affecting, 602–603

659

improvements, 620 power conversion, 509–510 radar, 508 RF power transistors, 244 RFPAs, 238, 282, 416, 440 see also average efficiency; drain efficiency; maximum efficiency; power efficiency; power-added efficiency (PAE) efficiency factor, 602–603 EIA (Electronic Industries Association) (US), 321 EL2 (electron level 2), definition, 44 electric field acceleration factor, 470 determination, 469 electric field spreading, 58–59 electrical ratings, 496–497 electrodeposition (ED) advantages, 289 applications, in printed circuit board manufacture, 289 electromagnetic analysis software, and circuit analysis software, 229 electromagnetic compatibility (EMC), 268–269 RF power amplifiers, 235, 241 electromagnetic simulation applications, 210 models from, 210–212 electromagnetic simulators, 210–212 in MMIC PA design, 372, 373 three-dimensional, 211–212 three-dimensional predominantly planar, 211 two-dimensional, 210–211 see also plant simulators electromigration definition, 462–463 design issues, 30–32 HBTs, 464–465 integrated circuits, 463 interconnects, 463–464 and lifetimes, 464 mechanisms, 463 and metallization, 452 metals, response differences, 30–31 performance enhancement, 31–32 prevention, 463 requirements, in MMICs, 369–370 resistors, 463–464 vs. temperature, 33 electron gas two-dimensional electron mobility, 114 sheet charge density, 114 electron level 2 (EL2), definition, 44 Electronic Industries Association (EIA) (US), 321

660

Index

electronic warfare (EW) communications jamming, hypothetical RFPA subsystem, 252–282 power amplifiers in, 534–537 RF power amplifiers in, 252 see also jammers electrostatic discharge (ESD) guidelines, 499 input protection circuits, 499 electrothermal equivalent circuits, 214–215 element testing, 448–449 EMC see electromagnetic compatibility (EMC) emissivity, 422, 430–431 definition, 422 encapsulation, MMIC PAs, 400 Enhanced Data Rates for Global Evolution (EDGE), 508–509 ENR see excess noise ratio (ENR) envelope analysis, 201–202 computational costs, 202 envelope elimination and restoration (EER) schemes, 514 envelope tracking, 161 concept of, 524–525 environmental testing, plastic packages, 491–492 epitaxial layers, growth, 111 epoxies, and screw locking, 304 equalizers, 325–326 behavior, 326 lossy stub, 327 equivalent circuits capacitors, 209 coupled-coil transformers, 553–554 distributed components, 324, 325 electrothermal, 214–215 GaAs FETs, 60–61, 85 GaN wide bandgap transistors, 125–127 gate finger, 68 gate manifold, 68 large-signal models, 85–86 limitations, 127 lumped components, 324, 325 reduced, 127 resistors, 318 small-signal models, 84–85 two-port networks, 125–126 transistors, 125–127 see also tee-equivalent circuits equivalent generators, and power sensors, 574–576 error models 3-term, 589 7-term, 588, 589, 592 error vector magnitude (EVM), 522, 525, 630–631 definition, 630 measurement, 630–631

ESD see electrostatic discharge (ESD) etch-stops, 77–78 etching dry, 78 issues, 290–291 mesa, 76–77 wet, 78 see also gate etching eutectic systems, for die attach, 426–427 EVM (error vector magnitude), 522, 525 EW see electronic warfare (EW) excess noise ratio (ENR), 638–640 determination, 638 F see noise factor (F) failure criteria, 449–450, 480 measurement selection, 450 specification thresholds, 449–450 failure distributions, 446, 455–458 HBTs, 465 separation, 455 thermal excursions, 477 failure mechanism analysis (FMA), 478–479 failure mechanisms, 446, 451–455 bulk substrate materials, 454 definition, 451 designers and, 447 dielectric, 453–454 in gallium arsenide processes, 500 metallization, 451–453 Schottky gate FETs, 454–455 semiconductors, humidity, 490 failure mode and effects analysis (FMEA), 282, 478–479 failure modes, 450–451 definition, 450–451 failure rates, 447 definition, 475 semiconductors, 455–456, 458 see also mean time between failure (MTBF); mean time to failure (MTTF) failures definition, 449 early, 504–505 evaluation procedures, 473–474 infant, 504–505 probabilities, 446 see also defects failures in time (FIT), 475 fans, reliability issues, 311 Faraday’s Law, 128–129 fast Fourier transforms (FFTs), 204 FDD (frequency-division duplexing), 519–520 FDMA (frequency division multiple access), 511–512

Index

feedback in microwave hybrid power amplifiers, 335, 336 issues, 335–336 resistive-inductive-capacitive networks, 251, 274, 315 in RF power amplifiers, 251, 267–268 see also gate-to-drain feedback capacitance (Cgd ) FEM see finite element method (FEM) FETs see field effect transistors (FETs) FFTs (fast Fourier transforms), 204 FIB (focused ion beam), applications, 459 fiberglass, applications, substrates, 285–286 field effect transistors (FETs) applications, RF power amplifiers, 161–162 bias networks, 249–250 characteristics, idealized, 162 current–voltage relationships, 162 degradation, 455 failure mechanisms, 454 gate-to-source capacitance, 134–135 life testing, 460, 461 lifetimes, temperature effects, 498 metal–insulator–semiconductor, 110 nonlinear source resistance, equivalent circuits, 134–135 power device models, 213 reliability guidelines, 497–498 RF power output, 124 sinking gates, 458 source resistance, 133–134 tee-equivalent circuits large-signal, 128 small-signal, 126 transconductance, 134–135 see also gallium arsenide field effect transistors (GaAs FETs); heterostructure field effect transistors (HFETs); metal semiconductor field effect transistors (MESFETs); metal–oxide–silicon field effect transistors (MOSFETs) field plates concept of, 18–19 effects, 8 in GaAs FETs, 66–67 in 4H-SiC MESFETs, 108 in silicon LDMOSFETs, 7–8, 18–19 finite element method (FEM), 431 applications, 431–432 finite impulse response (FIR) models, 201 finite volume method (FVM), 431 FIR (finite impulse response) models, 201 FIT (failures in time), 475 flares, 29, 30 flashing, 289 flip-chip die attach failure cross-sections, 481–482

661

failure mechanisms, 478–479 technology, 479 test structure, 479 thermal excursion testing, 478 FloTHERM, 432 fluid flows, simulations, 431 FMA (failure mechanism analysis), 478–479 fmax see maximum oscillation frequency (fmax ) FMEA (failure mode and effects analysis), 282, 478–479 focal plane array (FPA) detectors, 429–430 focused ion beam (FIB), applications, 459 forced air, and heat sinking, 310–311 Fourier transforms, 196–198, 204, 227 fast, 204 FPA (focal plane array) detectors, 429–430 frequency and gain, 37 see also maximum oscillation frequency (fmax ); transition frequency (fT ) frequency division multiple access (FDMA), 511–512 frequency modulation schemes, analog, 508–509 frequency sets box truncations, 224 in nonlinear circuit simulation, 224–225 rectangular truncations, 224 triangular truncations, 224 use of term, 224 frequency-division duplexing (FDD), 519–520 frequency-domain models, 204 frequency-shift keying (FSK), efficiency, 512–513 FSK (frequency-shift keying), efficiency, 512–513 fT see transition frequency (fT ) fuses, 347 FVM (finite volume method), 431 2.5G (mobile phone standard), 508–509 3G (mobile phone standard), 508–509, 519–520 power amplifiers, 509 4G (mobile phone standard), 508–509 power amplifiers, 509 GaAs see gallium arsenide (GaAs) GaAs FETs see gallium arsenide field effect transistors (GaAs FETs) GaAs HBTs (gallium arsenide heterojunction bipolar transistors), development, 42 GaAs MESFETs see gallium arsenide metal semiconductor field effect transistors (GaAs MESFETs) gain definitions, 599–602 and efficiency, 36–37 flatness, 237, 253 and frequency, 37 GaAs FETs, 61–63

662

Index

gain (cont.) hypothetical RFPA subsystem modules, 253 independent factors, 600–601 insertion, 601–602 linearity, 237, 253, 254 RF power amplifiers, 237 RF power transistors, 244 temperature stability, 237 transducer, 599–600 see also unilateralized gain (U) gain circles, constant, 601 gain compression, 622 gallium, interdiffusion, 454–455 gallium arsenide (GaAs) bandgap, 43 charge carrier mobility, 113–114 crystal structure, 43–44 disadvantages, 44–45 and hydrogen poisoning, 295 processes acceleration factors, 500 failure mechanisms, 500 properties, 43–45 resistivity, 44 thermal conductivity, 436 wafers, 357 see also aluminium gallium arsenide (AlGaAs); indium gallium arsenide (InGaAs) gallium arsenide field effect transistors (GaAs FETs), 42–91, 249 applications, 161–162 in RF power amplifiers, 282 band diagrams, 50 bias networks, 250 breakdown, 57–58, 66 mechanisms, 58–59 optimization, 58–59, 65–66 ratings, 59–60 RF vs. DC, 60 capacitances gate-to-drain, 60 gate-to-source, 60 parasitic, 60 channel temperature, 72–73 characteristics, 332 current–voltage characteristics, 51–52 detailed behavior, 51–52 dynamic, 53–54 idealized, 51, 52 practical, 53 pulsed, 53–54, 87 real devices, 52 depletion region, 61 design, 63–74 epi-layer, 64–65 FET channel and recess, 63–67

gate-recess, 65–66 power devices, 63 power FET cells, 67–69 thermal, 72–74 development, 42 doping profiles, 64 drain lag, 55 efficiency, 331 equivalent circuits, 60–61, 85 fabrication, 74–84 backside processing, 80 device isolation, 76–77 dielectric layers, 79–80 gate etching, 77–78 gate-shrink approaches, 81 interconnect metals, 80 liftoff, 76 lithography, 75–76, 81 low-cost, 81 ohmic contacts, 77 overview, 74–75 packaging, 81–84 process monitoring, 80 processes, 75–81 Schottky gate electrodes, 78–79 field plates, 66–67 figures of merit, 61–63 gain, 61–63 gate lag, 55 gate sinking, 72 historical background, 42 junction temperature, 72, 74 loadlines, 51–52 class A, 52 class B, 52 materials, properties, 43 models, 84–89 device, 84 gate-charge, 86–87 large-signal, 56, 85–89 load-pull, 89 small-signal, 84–85 packaging, 81–84 physics, 51–63 pulsed operation, 332 resistances, parasitic, 60 thermal resistance, 74 thermal simulation, 73–74 trapping effects, 53–54 consequences, 54–57 minimization, 54 types of, 46–51 gallium arsenide heterojunction bipolar transistors (GaAs HBTs), development, 42 gallium arsenide metal semiconductor field effect transistors (GaAs MESFETs) applications, 357–358

Index

dynamic characteristics, 115–117 failure mechanisms, 454 gallium arsenide technology, advantages, 42 gallium nitride (GaN) applications, 105–106, 161–162 charge carrier mobility, 113–114 hole mobilities, 115 gallium nitride field effect transistors (GaN FETs), 249 applications, in RF power amplifiers, 282 bias networks, 250 characteristics, 332 development, 42 efficiency, 331 gallium nitride RF power amplifiers (GaN RFPAs) applications, 441–442 die attach, 437 gallium nitride wide bandgap transistors, 103–153 breakdown, 112–113 development, 104–105 device design, 118–125 future trends, 152–153 large-signal effects, 130–152 gate leakage, 144–146 nonlinear source and drain resistances, 133–143 reliability and time-dependent performance degradation, 146–152 space-charge limited current transport, 130–133 material parameters, 111–115 models, 125–130 equivalent circuits, 125–127 physics-based large-signal, 128 properties, 112 RF performance, 118–125 thermal conductance, 112–113 GaN see gallium nitride (GaN) GaN FETs see gallium nitride field effect transistors (GaN FETs) GaN RFPAs see gallium nitride RF power amplifiers (GaN RFPAs) gasket sealing, 298, 299 approaches, 297 disadvantages, 297–298 gate capacitance, charge conservation, 86–87 gate dielectrics, degradation, 453–454 gate etching approaches, 78 in GaAs FET fabrication, 77–78 gate finger arrays, 27, 28 gate resistance, 347 gate taps, 28 concept of, 27–28 gate voltage control, 348 gate-to-drain breakdown voltage (BVgd )

663

definition, 57–58 optimization, 65–66 as two-terminal test, 57–58 gate-to-drain feedback capacitance (Cgd ) GaAs FETs, 60 silicon LDMOSFETs, 16 silicon VDMOSFETs, 16 gate-to-source breakdown voltage (BVgs ) definition, 57–58 as two-terminal test, 57–58 gate-to-source capacitance (Cgs ) AlGaN/GaN HFETs, 135 FETs, 134–135 GaAs FETs, 60 silicon LDMOSFETs, 16 gauge repeatability and reproducibility (GR&R), 282, 450 Gaussian minimum-shift keying (GMSK), applications, 513 gds (output conductance), dispersion, 55 generalized minimum residual (GMRES), 193, 199–200 Global System for Mobile Communications (GSM), 508–509, 513 standards, 519 gm see transconductance (gm ) Gmax curves, 62, 90–91 GMRES (generalized minimum residual), 193, 199–200 GMSK (Gaussian minimum-shift keying), applications, 513 gold applications, metallization, 452 electromigration, 30–31 interdiffusion, 452, 454–455 gold–silicon die attach applications, 437 thermal resistance, 436–437 goodness, measures, 447 3GPP see 3rd Generation Partnership Project (3GPP) GR&R (gauge repeatability and reproducibility) studies, 282, 450 grounding, printed circuit boards, issues, 285, 291 group delay and apertures, 603–604 calculation, 603–604 definition, 603 measurements, 603–605 GSM (Global System for Mobile Communications), 508–509, 513 Guanella baluns, 554 Gysel combiners, 533–534, 542–544 advantages, 542–544 frequency response, 544 layouts, 542–544 modes, 544 and Wilkinson power combiners compared, 545

664

Index

h parameters, 90 h21 , determination, 90 Hall mobility measurements, 114 HALTs (highly accelerated life tests), 270, 271 handset amplifiers, simulations, 219, 220 hard substrates, 285 dimensional issues, 289 mounting, 292 harmonic distortion (HMD), 239, 611–615 measurement, 641 harmonic load-pull active, 620, 621 cascaded tuner method, 620 triplexer method, 620 harmonic matching, 185–186 harmonic suppression, determination, 614–615 harmonic-balance analysis, 193–202 applications, 205 large circuits, 196–198 convergence failure, 195 convergence testing, 195–196 development, 193 improvements, 199–202 envelope analysis, 201–202 error equation weighting, 200 Krylov subspace methods, 199–200 multitone excitations, 200–201 norm reduction, 199 Semanskii iteration, 199 multidimensional problems, 196–198 performance, 195 procedures, 194–195 scattering parameter models in, 207–208 SPICE models in, 226 HASL (hot air solder leveling), 289 HASTs see highly accelerated stress tests (HASTs) HBTs see heterojunction bipolar transistors (HBTs) HCI see hot carrier injection (HCI) heat sinking design issues, 308–309 and forced air, 310–311 housings, 293, 305–311 heat sinks construction, 309–310 convection, 421 fin alignment, 310–311 RFPAs, 417 thermal resistance, 439–440 types of, 309 heat transfer efficiency, 421–422 mobile phones, 414–415 PCBs, 414–415 simulations, 431 and thermal performance, in RFPAs, 419–423

see also conduction; convection; phase change cooling; radiation heat transfer coefficient, 421–422 heatpipes, 311 HEMTs see high-electron mobility transistors (HEMTs) hermetic sealing, 295, 296–297 approaches, 297 MMIC PAs, 400 heterojunction bipolar transistors (HBTs) applications, 161–162 in MMICs, 361–362, 386 development, 358 electromigration, 464–465 failure distributions, 465 life testing, 464 thermal stability, 216 heterostructure field effect transistors (HFETs), 47 band diagrams, 50 gate bias effects, 51 current–voltage relationships, DC, 137 depletion mode, 135 design, epi-layer, 64–65 developments, 48 fabrication, 74–75 gate leakage, 144 materials, 104–105 models, large-signal, 147 resistances drain, 136 source, 136 structure, 46–48 see also aluminium gallium nitride/gallium nitride heterostructure field effect transistors (AlGaN/GaN HFETs); high-electron mobility transistors (HEMTs) HFETs see heterostructure field effect transistors (HFETs) high-electron mobility transistors (HEMTs), 47 applications, in MMICs, 361–362 band diagrams, 49–50 channel mobilities, 48–49 development, 161–162, 358 doping profiles, 64–65 fabrication, 74–75 failure mechanisms, 454 indium gallium arsenide-based, RF performance, 103–104 modulation doping, 48–49 structure, 48 voltage acceleration, 471–472 see also pseudomorphic high-electron mobility transistors (pHEMTs) high-frequency devices, 105–106 high-power amplifiers (HPAs), 374–375, 388 applications, 532

Index

drain switching, 532–533 multi-octave, 377–380 single-stage, 385–386 thermal management, 400–401 high-power attenuators, 577 high-power RF measurements, 576–579 high-temperature life testing, 475 high-voltage integrated circuits (HVICs), 37–39 development, 37 performance, 38–39 two-stage, 37–38 high-voltage p region (PHV) implants silicon LDMOSFETs, 6–7 silicon VDMOSFETs, 19 high-voltage zero-power moisture (HVZPM), 489 highly accelerated life tests (HALTs), 270, 271 highly accelerated stress tests (HASTs), 83–84, 489–490 acceleration factors, 492 applications, 488 HMD see harmonic distortion (HMD) hole current density, simulations, 25 hot air solder leveling (HASL), 289 hot carrier injection (HCI) characterization, 19 stress testing, 21 degradation mechanisms, 453–454 DMOSFETs, 17–22 LDMOSFETs, 2–5 levels, 7–8 mitigation, 21–22 occurrence, 19–21 and RF bias acceleration, 473 sensitivity, 21–22 housings connections, 293 construction, 299–305 construction methods, 303–304 castings, 303 machining, 303 piece parts, 304 cost reductions, 303–304 heat sinking, 293, 305–311 hermeticity, 294–299 interference issues, 293 internal corners, 303 materials, 294, 311 microwave hybrid power amplifiers, 293–315 mountings, 293 protection, 293, 294–295 factors affecting, 295 standards, 295 RF connections, 311–315 screw locking, 304 sealing, 294–299 thermal issues, 305–311

665

thermal performance, 306 water cooling, 311 see also packaging HPAs see high-power amplifiers (HPAs) humidity semiconductor failure mechanisms, 490 and temperature, 488–489 humidity acceleration factors, 488–492 humidity activation energy, 488–492 humidity testing bias, 488–489 HVICs see high-voltage integrated circuits (HVICs) HVZPM (high-voltage zero-power moisture), 489 hybrid, definition, 284 hybrid amplifiers markets, 284 substrates, parameters, 286 use of term, 284 see also microwave hybrid power amplifiers (MHPAs) hybrid parameters, h21 , 62, 63 hydrogen poisoning, 295 hypothetical RFPA subsystem modules, 252–282 altitude, 253, 254 antenna load, 253 bandwidth, 252, 253 breadboards, 271, 272 capacitors chip, 265–267 coupling, 265–267 feedback, 274 design preventative measures, 273 processes, 252 efficiency, 278, 279 feedback networks, 267–268 frequency response, 253 gain, 253 flatness, 253 linearity, 253, 254, 274–278 gaskets, 273 gate bias/temperature tracking/compensation networks, 257–259 hardware, design/realization, 254–255 input/output impedance matching networks, 259–267 input/output RF/DC coupling/decoupling networks, 259 components, 259 mean time to failure, 253, 254, 280, 281 overview, 252 phase linearity, 254, 274–278 physical construction, 271–273 power output, 252, 253, 255 radiated emissions, 253, 254 RF transistor selection, 255–257 schematics, 273–274

666

Index

hypothetical RFPA subsystem modules (cont.) shock/vibration, 253, 254 specifications qualitative delineation, 252–253 quantification, 253–254 stability, 253, 279 susceptibility, 253, 254 system block and wire diagrams, 254–255 temperature range, 253, 254 temperature stress tests, 279–280 test data, 281–282 test results, 273–280 test setup configuration/analysis, 268–270 block diagrams, 268–269, 270 transformation ratios, 260–261 transformers, output, 272 two-port small-signal responses, 274, 275 vibration tests, 279–280 voltage standing wave ratios, load, 253, 278–279 ICs see integrated circuits (ICs) IEDs see improvised explosive devices (IEDs) IIR (infinite impulse response) models, 201 IMD see intermodulation distortion (IMD) IMFETs see internally matched field effect transistors (IMFETs) impact ionization, 58–59 impedance matching hypothetical RFPA subsystem modules, 259–267 microwave hybrid power amplifiers, 337 power field effect transistor cells, 71 RF power transistors, 250–251, 259–267, 283 HF, 250 UHF, 250 VHF, 250 stubs, 338 transistor amplifiers, 117 impedance range, and substrate materials, 289 impedance standard substrates (ISSs), calibration standards, 595–596 improvement cycles, mobile phones, 502 improvised explosive devices (IEDs) countermeasures, power amplifiers in, 538 jammers, 538 see also radio-controlled improvised explosive devices (RCIEDs) incident power, 581 incident waves, 580 magnitude, 582 indefinite admittance matrices, 190 indium gallium arsenide (InGaAs) bandgap, 43 crystal structure, 43–44 in HEMTs, RF performance, 103–104 in pHEMTs, 48–49 properties, 43

inductance, general expression, coefficients, 368 inductors air-cored, advantages, 322 bond wires as, 219–220 configurations, 367 losses, 219 lumped, 367 in microwave hybrid power amplifiers, 321–322 modeling, 315 planar spiral, closed-form models, 209 industrial markets, RF power amplifiers, 235 inexact Newton methods, 199–200 infinite impulse response (IIR) models, 201 infrared (IR) microscopes, 429, 430 infrared (IR) reflow thermal profiles, 476 infrared (IR) thermometry, 428–429 InGaAs see indium gallium arsenide (InGaAs) insertion gain, 601–602 insertion loss minimization, 321 transmission line transformers, 264–265, 266 instability, power amplifiers, 605 integrated circuits (ICs) design, reliability issues, 496 electromigration, 463 fabrication, reliability issues, 496 materials, limitations, 446–447 microwave, 357–358 in microwave hybrid power amplifiers, 322 see also high-voltage integrated circuits (HVICs); monolithic microwave integrated circuits (MMICs); radio frequency integrated circuits (RFICs) intercept points, 611–613 interconnects electromigration, 463–464 metallization failures, 451, 484 metals, 80 reliability guidelines, 498–499 see also vias interdiffusion copper, 452 gallium, 454–455 gold, 452, 454–455 interferences common-mode, 608–610 transmission lines, 608–610 intermodulation distortion (IMD), 235, 611–615 measurement, 641 minimization, 236 RF power amplifiers, 239 intermodulation measurements, 614 intermodulation suppression, 611–613 internally matched field effect transistors (IMFETs) characteristics, 71 topology, 73

Index

ion implantation, in GaAs FET fabrication, 77 IR (infrared) microscopes, 429, 430 IR (infrared) reflow thermal profiles, 476 IR (infrared) thermometry, 428–429 Iridite, 294 isolators issues, 323 in microwave hybrid power amplifiers, 322–323 performance, 343 ISSs (impedance standard substrates), calibration standards, 595–596 Jacobian matrices, 197–198, 226 poor conditioning, 227–228 jammers in electronic warfare, hypothetical RFPA subsystem, 252–282 I/J band, 537, 538 power amplifiers, 534 broadband, 538 prototypes, 535, 536, 537 for radio-controlled improvised explosive devices, 538 RF power amplifiers, 234 junction temperature, reduction, 311 junction-to-case thermal resistance (Rjc ) definition, 427 determination, 427 K factors, 482–488 determination, 486 kink effect, 56–57 mechanisms, 56–57 Kirchhoff’s current law, 194–195, 196–198 knee regions, negligible impacts, 162 Kovar applications in ceramic packages, 391 housings, 294 hermetic sealing, 297 properties, 294 Krylov subspace methods, 193, 199–200 λ parameter, 131 Lambert W function, 132 land grid arrays (LGAs), 413–414 land mobiles applications, 34–35 markets, 34–35 Lange couplers, 287–288, 330, 547, 549–550 advantages, 328–331 applications, 549 characteristic impedance, 550 development, 549

667

frequency range, 550 frequency response, 549–550 limitations, 550 performance, 550, 551 Laplace transforms, 204 large devices, cell interconnections, modeling, 213–214 large-signal models attributes, 86 black-box, 89 compact, 87 comparisons, 86 development, 87, 129–130 direct large-signal measurements, 88–89 equivalent circuits, 85–86 limitations, 127 for GaAs FETs, 85–89 HFETs, 147 for large periphery devices, 88 nonlinear, 127 physics-based, 128 table-based, 88 and trapping effects, 87–88 large-signal network analysis, 616–618 calibration, 617–618 large-signal network analyzers (LSNAs), 616, 617 set up, 622 lateral double diffused metal–oxide–silicon field effect transistors (LDMOSFETs), 249 cross-sections, 434 see also silicon lateral double diffused metal–oxide–silicon field effect transistors (silicon LDMOSFETs) LDO (low drop out) voltage regulators, 348 lead frames (LFs) materials, 395 in plastic packages, 395, 402 types of, 395 lead–tin–silver die attach, 426–427 applications, 437 thermal resistance, 437 LFs see lead frames (LFs) LGAs (land grid arrays), 413–414 life testing FETs, 460, 461 HBTs, 464 high-temperature, 475 highly accelerated, 270, 271 MESFETs, 459 transistors, 459–462 lifetimes capacitors, predictions, 471 and electromigration, 464 FETs, temperature effects, 498 vs. temperature, 462

668

Index

liftoff, 453 defects, 483 in GaAs FET fabrication, 76 metallizations, 483 processes, 483 LINC systems see linear amplification using nonlinear components (LINC) systems linear amplification using nonlinear components (LINC) systems, 160, 514 applications, 161 linear analysis, 188–193 early, 188 nodal incidence matrices, 188 two-port, 125–126 see also nodal analysis linear distortion measurement, 603–605 two-port networks, 603 linear measurements, 599–611 linear stability issues, 605–608 linear regime on-resistance (RDSon ) DMOSFETs, 17–22 factors affecting, 19 minimization, 19 silicon LDMOSFETs, 5 linear two-port circuit analysis, 125–126 linearity Class AB amplifiers, 169–170 enhancement, 514 gain, 237, 253, 254 limits, 525 phase, 237, 254, 274–278 power amplifiers, 512–514 measurement, 512 linearization techniques overview, 514 power efficiency impacts, 517–519 system level, 514–519 see also digital baseband pre-distortion (DPD); memory effect compensation liquid crystals, operating temperature measurement, 428–429 lithography electron-beam, 76 in GaAs FET fabrication, 75–76 optical steppers, 76, 81 stepper-based, 79, 81 types of, 76 load lines, dynamic, 618 load-pull measurements, 619–622 active harmonic, 620, 621 set up, 621 see also harmonic load-pull local oscillators (LOs), 587 Long Term Evolution (LTE) bandwidths, 517

standards, 520 LOs (local oscillators), 587 low drop out (LDO) voltage regulators, 348 low temperature co-fired ceramics (LTCCs), 315 developments, 322 LSNAs (large-signal network analyzers), 616 LTCCs see low temperature co-fired ceramics (LTCCs) LTE see Long Term Evolution (LTE) LU decomposition, 191, 199 computational loading, 191 lumped elements advantages, 367–368 definition, 367 microstrip, 367 in MMICs, 367–369 lumped-element models development, 368 vs. scattering parameter models, 208 machining, housings, 303 MAG curves (maximum available gain) curves, 62 magnetic resonance imaging (MRI), RF power amplifiers, 235 magnetic resonance spectroscopy (MRS), RF power amplifiers, 235 Mason’s invariant gain see unilateralized gain (U) matching harmonic, 185–186 see also impedance matching; transformer matching materials AlGaN/GaN HFETs, 114 bipolar junction transistors, 106 ceramic packages, 391 properties, 391 die attach, 397, 426–427 GaAs FETs, 43 HFETs, 104–105 housings, 294, 311 lead frames, 395 limitations, 446–447 metallization, 451–452 microwave, 286 pHEMTs, 48–49 radio absorbent, 304–305 RFPAs, thermo-physical properties, 423–427 substrates, 289 soft, 285–286 thermal conductivity, 423–424 at room temperature, 425 behavior, 424–425 wide bandgap, 284 see also thermoset materials mating surface flatness, RFPAs, 439

Index

matrices indefinite admittance, 190 port, 191 processing, 192–193 sparse, 192–193 storage issues, 192–193 see also Jacobian matrices; LU decomposition; nodal matrices maximum available gain (MAG) curves, 62 maximum efficiency Class A amplifiers, 510 power amplifiers, 510 maximum norms, 227 maximum oscillation frequency (fmax ), 63 definition, 62–63 determination, 90 limitations, 63 maximum ratings, 497 maximum stable gain (MSG) curves, 62 MBE see molecular beam epitaxy (MBE) mean time between failure (MTBF) applications, 474–475 and bathtub curves, 412–413 temperature and, 412 mean time to failure (MTTF) and electromigration, 30–31 hypothetical RFPA subsystem modules, 253, 254, 280, 281 microwave hybrid power amplifiers, 305 RF power amplifiers, 241 measurements AM/AM, 632 AM/PM, 632 amplifiers, 570–642 directional power, 576–579 group delay, 603–605 Hall mobility, 114 high-power RF, 576–579 of interest, selection criteria, 449 intermodulation, 614 nonlinear, 611–623 pulsed, 633–635 requirements, 641 scalar reflection, 582 transmission, 586 uncertainties, 598–599 sources of, 574–576 see also linear measurements; load-pull measurements; modulated measurements; noise measurements; power measurements; scattering (S) parameter measurements; source-pull measurements median, and standard deviation compared, 468 median lives (MLs), 459–460 determination, 461, 463–464 transistors, 461

669

median time to failure see mean time to failure (MTTF) medical heating, RF power amplifiers, 235 medical markets, RF power amplifiers, 235 memory effect compensation, 517, 567–568 memory effects, 56, 259, 630 modulated measurements, 632–633 Mentor Graphics, 432 mesa etching, in GaAs FET fabrication, 76–77 MESFETs see metal semiconductor field effect transistors (MESFETs) metal alloys, development, 285 metal organic chemical vapor deposition (MOCVD), applications, 75 metal semiconductor field effect transistors (MESFETs), 45, 47 applications, in MMICs, 361–362 band diagrams, 49–50 gate bias effects, 51 channel mobilities, 48–49 degradation, 458–459 electrical characteristics, 458 design, epi-layer, 64–65 doping profiles, 64 fabrication, 74–75, 107–108, 360 ion implantation, 77 failure mechanisms, 454 lifetests, 459 structure, 46–48 see also gallium arsenide metal semiconductor field effect transistors (GaAs MESFETs); 4H-silicon carbide metal semiconductor field effect transistors (4H-SiC MESFETs) metal–insulator–metal (MIM) capacitors, 367, 368–369 dielectrics, 453 reliability guidelines, 499 structure, 369 time-dependent dielectric breakdown, 466–471 voltage acceleration, 465–466 voltage ramping, 466–471 see also silicon nitride capacitors metal–insulator–semiconductor field effect transistors (MISFETs), 110 metal–oxide–silicon field effect transistors (MOSFETs), 249 advantages, 246–247, 257 applications, RF power amplifiers, 282 availability, 282 see also double diffused metal–oxide–silicon field effect transistors (DMOSFETs) metallization, 451–453 and corrosion, 452 and electromigration, 452 interconnects, 484 liftoff, 483

670

Index

metallization (cont.) materials, 451–452 pattern definition, 453 and reliability, 494–495 semiconductors, 488 metals imperfections, 218 oxidation, 218 resistivity, 218–219 bulk, 289 surface roughness, 218 MGRS (migrated gold resistive shorts), 490 MHPAs see microwave hybrid power amplifiers (MHPAs) Microsoft Windows component object model, 229 dynamic data exchange, 229 microstrip, 80, 218 alternatives to, 292 attenuation constant, 364 in calibration, 593–594 characteristic impedance, 363, 364, 392–393 data, 363 design issues, 325 dielectric constant, 364 discontinuities, 205, 206–208, 209, 365 simulations, 212 loss models, 218 lumped elements, 367 in MMICs, 359, 362–365 operating frequency, 364–365 parameters, 363 rat-race couplers, 559 tee junctions, 229 transmission-line models, 229 wavelength, 363 microwave absorbers, 304–305 microwave devices, 105–106 microwave hybrid power amplifiers (MHPAs), 284–355 applications, 284 balanced design, 334 disadvantages, 334–335 biasing, and control, 345–353 broadband matching strategies, 340–341 cavities orthogonal, 300 resonant frequencies, 304–305 components, 315–332 configurations, 299–300 H-section, 300, 301 orthogonal cavities, 300, 301 planar, 301–303 side-by-side, 302 split section, 301 wrap around, 300, 301, 302

construction, 299–305 control and biasing, 345–353 and interfacing, 352–353 couplers, 353 design, 333 balanced, 334 combining, 344 internally matched device amplifiers, 343–344 issues, 284 matching, 336–343 module size, 344 number of stages, 333 risk reduction, 344 stability, 336–343 system integration, 344 topologies, 333–336 fault finding, 344 feedback, 335, 336 issues, 335–336 housings, 293–315 impedance matching, 337, 339–341 interfacing and control, 352–353 thermal resistance reduction, 307–308 mean time to failure, 305 modules, configurations, 299–300 operating temperatures, 299 reduction, 307 printed circuit boards, 285, 293 substrates, properties, 287 thermal resistance, 305 tuning techniques, 353–355 see also components; housings; printed circuit boards (PCBs) microwave integrated circuits (MICs), development, 357–358 microwave materials, properties, 286 microwave power amplifiers developments, 357 RF power performance, 105 see also monolithic microwave integrated circuit power amplifiers (MMIC PAs) microwave power field effect transistors power-frequency limit, 45–46 thermal resistance, 73–74 microwave systems solid-state transistors in, 103 vacuum tubes in, 103 MICs (microwave integrated circuits), development, 357–358 migrated gold resistive shorts (MGRS), 490 MIL-STDs (military standards) (US), 295 military markets power amplifiers, 530–538, 567–568 RF power amplifiers, 234–235

Index

military standards (MIL-STDs) (US), 295 MIM capacitors see metal–insulator–metal (MIM) capacitors MIMIC program (US), 42 MIMO (multiple-input–multiple-output), 520 MISFETs (metal–insulator–semiconductor field effect transistors), 110 mixer sets, 224 MLCs see multilayer capacitors (MLCs) MLs see median lives (MLs) MMIC PAs see monolithic microwave integrated circuit power amplifiers (MMIC PAs) mobile phones air flow fields, 414–415 block diagrams, 413–414 exploded views, 413–414 heat transfer, 414–415 improvement cycles, 502 sealing, 414 talk time, 508 temperature field patterns, 414–415, 416 thermal behavior, 414–415 thermal design, 413–415 mobile radio communications efficiency trends, 520–522 networks, operating costs, 523 power amplifiers, 519–522 design, 523–524 standards, 519 mobile telephony applications, 35 base stations, RF power amplifiers, 236 historical background, 508–509 power amplifiers, 509 MOCVD (metal organic chemical vapor deposition), applications, 75 modal decomposition, 608–610 MODFETs see high-electron mobility transistors (HEMTs) modulated measurements, 623–636 memory effects, 632–633 modulated signals, properties, 573 modulation doped field effect transistors (MODFETs) see high-electron mobility transistors (HEMTs) modulation envelope, use of term, 623 moisture ingress and breathing, 296 capillary action, 296 diffusion, 295 and sealing, 295–296 moisture sensitivity level (MSL), 491–492 moisture vapor transmission rate (MVTR), 295 molecular beam epitaxy (MBE) applications, 75 development, 161–162

monolithic microwave integrated circuit power amplifiers (MMIC PAs), 357–406 advantages, 358–359 broadband, 372–373, 376–377 2W C-band, 376, 377 10W X-band, 377, 378 performance, 373 characterization, 357, 401–406 power, 404–405 procedures, 401–403 test fixtures, 403–404, 405, 406 tests, 403–406 design, 370, 525–526 CAD tools, 370 electromagnetic simulators, 372, 373 flowcharts, 371 issues, 370 methodology, 370–372 procedures, 371–372 developments, 358 evaluation, 401 examples, 372–389 high-power, 372–373, 381–386 14W with 60% PAE, 384–386 15W C-band, 385–386 20W X-band, 383, 384 50W S-band, 383 design, 381–383 power output, 385–386 high-power-added efficiency, 372–373 high-voltage, 372–373, 374, 387–389 10W GaAs HV FET, 388, 389, 390 GaN HEMT-based, 388–389, 391 limitations, 387–388 operation, 388 historical background, 357–358 millimeter wave 2.4W, 386, 387 narrowband, 372–373, 374–375 7W Ku-band, 374–375 performance, 373 operating range, 358–359 overview, 357–359 packaging, 389–401 assembly, 396–401 ceramic, 390–394 plastic, 394–396 requirements, 389–390 selection criteria, 389 power dissipation, 401 RF parameters, 405–406 summary, 372–389 technology, 359–370 three-dimensional views, 359 ultra-broadband, 376–377 2–18 GHz distributed, 380, 382 8W 2–8 GHz, 379–380, 381

671

672

Index

monolithic microwave integrated (cont.) 15W L- to S-band, 378–379, 380 power output, 379 wireless 3W, 386, 387 design, 386 measured performance, 386, 388 performance specifications, 386 stages, 386 monolithic microwave integrated circuits (MMICs) active devices, 359, 361–362 conductors current-carrying capacity, 369–370 dimensions, 369 coplanar waveguides, 362–363, 365–367 electromigration requirements, 369–370 fabrication, 360–361 processes, 360 recessed-gate process, 360 frequency limits, 362 literature, 361 lumped elements, 367–369 matching elements, 362–370 microstrip, 359, 362–365 performance, 362 and radio frequency integrated circuits compared, 357 substrates, 359, 361 technology, 359–370 transmission lines for, 362 mortality rates, 456 MOSFETs see metal–oxide–silicon field effect transistors (MOSFETs) MPCPA (multiple pulses chirped pulse amplification), 624 MRI (magnetic resonance imaging), RF power amplifiers, 235 MRS (magnetic resonance spectroscopy), RF power amplifiers, 235 MSC Sinda, 432 MSG curves (maximum stable gain) curves, 62 MSL (moisture sensitivity level), 491–492 MTBF see mean time between failure (MTBF) MTTF see mean time to failure (MTTF) multilayer capacitors (MLCs) applications, 320–321 use of term, 318–320 multiple devices, advantages, 307 multiple pulses chirped pulse amplification (MPCPA), 624 multiple-input–multiple-output (MIMO), 520 multitone analysis, 204–205 multitone excitations, 200–201, 625 MVTR (moisture vapor transmission rate), 295

National Institute of Standards and Technology (NIST) (US), 268 NBTI (negative bias temperature instability), 453–454 negative bias temperature instability (NBTI), 453–454 network analyzers for S parameter measurements, 641 see also large-signal network analyzers (LSNAs); scalar network analyzers; vector network analyzers (VNAs) Newton’s method, 194–195 inexact, 199–200 issues, 221–222 modified, 197–198 rules, 221 NFs see noise figures (NFs) NIST (National Institute of Standards and Technology) (US), 268 NMR (nuclear magnetic resonance) spectroscopy, RF power amplifiers, 235 nodal analysis, 188 advantages, 188–189 disadvantages, 189 procedures, 189–191 nodal matrices, 190–191 factoring, 191 singular, 191 noise sources of, 636 thermal, 636 noise factor (F), 637 minimum, 640 noise figures (NFs), 637 assumptions, 640 measurement, 637–640 spectrum analyzers, 628 typical, 639 noise floor, 628 noise measurements, 636–640 direct, 637–638 noise parameters, 640 measurement, 641 noise power, 637 values, 638 noise reduction, 348 noise temperature input, 639 values, 638 noise–power ratio (NPR), 630 noninsertable devices, 589 nonlinear circuit simulation analysis characteristics, 223–226 continuation methods, 223 convergence improvement, 223 design flow, 228–230

Index

frequency sets, 224–225 model characteristics, 221–223 numerical issues, 227–228 practical issues, 221–230 problem size minimization, 226–227 solution optimization, 226–227 termination criteria, 225–226 nonlinear distortion, 512–513, 611 nonlinear measurements, 611–623 norm reduction, 199 NPR (noise–power ratio), 630 nuclear magnetic resonance (NMR) spectroscopy, RF power amplifiers, 235 numerical derivatives, applications, 222–223 O-rings, rubber, sealing performance, 296 OFDM (orthogonal frequency-division multiplexing), 508–509, 513–514, 520 ohmic contacts degradation, 454–455 in GaAs FETs, 77 on-wafer tests, 401–403, 404 open circuits, 490 operational analysis, reliability predictions, 474 orthogonal frequency-division multiplexing (OFDM), 508–509, 513–514, 520 oscillations, minimization, 352 output conductance (gds ), dispersion, 55 package assembly die attach, 396–397 in MMIC PAs, 396–401 thermal issues, 400–401 wire bonding, 396, 397–398 packaging ceramics, 82, 390–394 environmental protection, 83–84 GaAs FETs, 81–84 MMIC PAs, 389–401 hermetic sealing and encapsulation, 400 plastics, 82–83, 394–396 silicon VDMOSFETs, 9 thermal models, 400–401 types of, 81 see also ceramic packages; housings; plastic packages; surface mount leadless packages (SMLPs) PAE see power-added efficiency (PAE) pallet amplifiers, 343–344 PAPR see peak-to-average power ratio (PAPR) parameters hybrid, 62, 63 monitoring, 449 most rapidly degrading, 449–450 see also noise parameters; scattering (S) parameters

673

parasitic bipolar effect (PBE), 58–59 parasitic crosstalk, 596–597 parasitic elements, behavior, 12–17 parasitic extraction, 212–213 software, 212 Parker–Skellern model, 86 PAs see power amplifiers (PAs) passive circuits, structures, and simulation accuracy, 205–213 passive intermodulation (PIM), 613–614 passive tuners, 620 pattern definition, metallization, 453 PBE (parasitic bipolar effect), 58–59 PBO see power back-off (PBO) PCBs see printed circuit boards (PCBs) PCDE (peak code domain error), 522 PCMs (process control monitors), 80 PCS1900 system, 513 PDF (probability density function), 510–511, 512 peak code domain error (PCDE), 522 peak envelope power (PEP), importance of, 513 peak power, 627–628 peak-to-average power ratio (PAPR), 513–514, 624 definition, 513 reduction, 514 PECVD (plasma enhanced chemical vapor deposition), applications, 453 PEP (peak envelope power), importance of, 513 performance power amplifiers, 567–568 and reliability, 448 and semiconductor properties, 111 vs. temperature, 411–412 see also thermal performance periodic signals, crest factors, 624 Pf2 (power-frequency) limit, 45–46 phase, measurement, 603–605 phase change cooling, and thermal performance, RFPAs, 423 phase delay definition, 604 determination, 604–605 in dispersion-free networks, 605 phase-shift keying (PSK), 513–514 efficiency, 512–513 see also quadrature phase-shift keying (QPSK) phased array antennas, 533, 534 PHD (poly-harmonic distortion) models, 88–89 pHEMTs see pseudomorphic high-electron mobility transistors (pHEMTs) photoresists, 483, 493 PHV implants see high-voltage p region (PHV) implants physical amplification, 504 piece parts, in housing construction, 304 PIM (passive intermodulation), 613–614

674

Index

plant simulators, 211 advantages, 211 open vs. closed formulations, 211 plasma enhanced chemical vapor deposition (PECVD), applications, 453 plastic packages, 398 applications, MMIC PAs, 394 assembly, 398–400 flow, 402 design, 395 developments, 394 environmental testing, 491–492 lead frames, 395, 402 molding, 394–395 tests, 405 plastics, applications, packaging, 82–83, 394–396 plated-through holes (PTHs), 291 PMMA (polymethyl methacrylate), applications, resists, 78–79 point-in-pulse method, 633 trigger delays, 634 Poisson’s equation, 130–131 solutions, 129–130 poly-harmonic distortion (PHD) models, 88–89 polymethyl methacrylate (PMMA), applications, resists, 78–79 polytetrafluoroethylene (PTFE) applications, substrates, 285–286 dielectric constant, 286–287 disadvantages, 286–287, 291 port matrices, 191 power amplifiers (PAs) applications, 508–568 anti-improvised explosive device, 538, 539 electronic warfare, 534–537 jammers, 534 military, 530–538, 567–568 mobile telephony, 509 wireless communications, 519–530 broadband, 538 circuit-analysis software, 188 computer-aided design, 188–230 crest factors, 512–514 design holistic, 526, 528 issues, 619 overview, 523–526 parameter trade-offs, 509–514, 525, 567–568 processes, 525 devices, 105–106 efficiency, 508, 524–525, 567–568 factors affecting, 602–603 improvements, 620 power conversion, 509–510 functions, 508 instability, 605

linearity, 512–514 limits, 525 measurement, 512 linearization techniques memory effect compensation, 517 overview, 514 power efficiency impacts, 517–519 system level, 514–519 models bond wires, 219–221 circuit component losses, 219 circuit metallization loss, 217–219 ideal, 162 special issues, 216–221 modulation schemes, 512–514 nonlinearity, 508 output power–efficiency trade-off, 509–512 performance, 567–568 power combining anti-phase, 552–559 Doherty, 559–567 in-phase, 538–544 quadrature-phase, 544–550 power output average, 509, 522–523 control, 511–512 definition, 509 prototypes, 535 reliability, 504, 523 reliability goals, 448 requirements, 522–523 trends, 508–509 responses, nonlinear, 524 solid-state, applications, 284 in telecommunications systems, 508 see also balanced power amplifiers; high-power amplifiers (HPAs); microwave hybrid power amplifiers (MHPAs); microwave power amplifiers; push-pull amplifiers; RF power amplifiers (RFPAs) power back-off (PBO) Class A amplifiers, 164, 180 Class AB amplifiers, 169 Class B amplifiers, 168–169 power combining anti-phase, 552–559 balanced power amplifiers in, 546–547 Doherty, 559–567 in-phase, 538–544 see also couplers; Gysel combiners; quadrature-phase power combining; Wilkinson power combiners; Wilkinson splitters power consumption, low, 602 power conversion, efficiency improvements, 411 power cycling, thermal excursions, 480–481

Index

power density definition, 2–5 silicon LDMOSFETs, 441 trends, 441 power device models, 213 thermal effects, 214–216 see also self-heating models power efficiency impacts, 518–519 linearization effects, 517–519 power field effect transistor cells combination, 71 common-lead inductance, 68–69 design, 67–69 modeling, 69 dies, 71 gate finger equivalent circuits, 68 gate manifold equivalent circuits, 68 gate width, 67 images, 72 impedance matching, 71 layouts, 69, 71 manifold issues, 67–68 performance, 70 power field effect transistors field plates, 66–67 packages, 82 Schottky gate electrodes, 78–79 topology, 68–69, 73 see also microwave power field effect transistors power flow, 600 diagrams, 599 power sensors, 575 power measurements, 570–580 directional, 576–579 high-power RF, 576–579 spectrum analyzers in, 579–580 uncertainties, sources of, 574–576 power quad flat no lead (PQFN) packages see surface mount leadless packages (SMLPs) power sensors advantages, 571 applications, 570 modulated signal verification, 571 attenuators, 576–577 comparisons, 573 compensation techniques, 574 disadvantages, 571 dynamic range, 574 and equivalent generators, 574–576 impedance, 574–576 limitations, 570 power flow, 575 principles, 570–574 side effects, 574 see also directional power sensors

675

power supply–device resistance, 352 power-added efficiency (PAE), 509–510 definition, 36–37, 602 in MMIC PAs, 384–386 power-frequency (Pf2 ) limit, 45–46 PQFN packages see surface mount leadless packages (SMLPs) pre-distortion concept of, 514–515 schemes, 514 see also digital baseband pre-distortion (DPD) preconditioners, 199–200 preconditioning, 491–492 printed circuit boards (PCBs) alignment with housing, 292–293 calibration with, 593–596 guidelines, 594–595 coaxial connections, 312, 313 conductors, 289 dielectric losses, 288–289 etching, issues, 290–291 flange-mounted components, 292–293 ground path effects, 292–293 grounding issues, 285, 291 heat transfer, 414–415 lamination, 285–286 manufacturing issues, 290–291 in microwave hybrid power amplifiers, 285, 293 mounting, 291–292 solder, 292 patterning, 285 resistive losses, 288–289 resistors, integration, 285 RF connections, 312, 314–315 substrates, mounting issues, 285 thermal conductivity, 288–289 through-holes, 291 types of, 285 see also substrates Pro-E, 432 probability density function (PDF), 510–511, 512 process control monitors (PCMs), 80 process effects, 492–495 production-line testing, 570 prototypes jammers, 535, 536, 537 optimization, 570 power amplifiers, 535 pseudomorphic high-electron mobility transistors (pHEMTs), 47 applications, in MMICs, 361–362 band diagrams, 49, 50–51 current–voltage characteristics, pulsed, 53 design, epi-layer, 64–65

676

Index

pseudomorphic high-electron mobility (cont.) development, 358 gain, 61–62 humidity acceleration factors, 488–492 materials, 48–49 gallium arsenide vs. gallium nitride, 534–535 structure, 48–49 PSK see phase-shift keying (PSK) Psy-Ops (psychological warfare operations), RF power amplifiers, 235 psychological warfare operations (Psy-Ops), RF power amplifiers, 235 PTFE see polytetrafluoroethylene (PTFE) PTHs (plated-through holes), 291 pulse chopping, 635 pulse profile method, 634 transistors, 634–635 pulse width modulation (PWM), and Class S amplifiers, 183 pulsed measurements, 633–635 pulsed operation, principles, 633 push-pull amplifiers, 552–559 advantages, 552 baluns, 552 disadvantages, 552 operation, 552 schematics, 552 see also RF/microwave push-pull amplifiers PWM (pulse width modulation), and Class S amplifiers, 183 pyrolytic graphite, 427 Q see quality factor (Q) QFN (Quad Flat No leads) packages see surface mount leadless packages (SMLPs) QPSK see quadrature phase-shift keying (QPSK) Quad Flat No leads (QFN) packages see surface mount leadless packages (SMLPs) quadrature couplers, 328–331 frequency response, 546, 547 structure, 547 quadrature phase-shift keying (QPSK), 513–514 offset, 513 quadrature-phase power combining, 544–550 branchline hybrid, 547–549 qualification testing, 496 quality criteria, 641–642 and reliability, 447–448, 486 vs. spacing, 485, 494 vs. voltage, 486–487 see also reliability quality factor (Q), 318–320 load, 337–338

radar duplexers, functions, 530–531 efficiency, 508 limiters, 531 phased array, 530 RF power amplifiers, 235 transmitter/receiver modules, 530–534 block diagrams, 530, 531 performance requirement, 533 phased array antennas, 533 specifications, 533–534 variable phase shifters, 531 radiation, and thermal performance, RFPAs, 422–423 radiative energy, 422 radiative heat transfer, determination, 422–423 radiative heat transfer coefficient, 422–423 radio absorbent materials (RAMs), 304–305 radio base stations (RBSs), 417 bandwidth, 522 carrier capacity, 522 controllers, 417 efficiency, 440 improvements, 441 efficient, Doherty amplifiers for, 527–530 energy consumption, 411 power classification, 523 power output, 416 measurement, 576–577 RFPAs for, 411–412 running costs, 508 technologies, 523–524 thermal design, 416–419 thermal management, 411 waste heat, 411 removal, 416–417 radio frequency integrated circuits (RFICs) applications, 357 and monolithic microwave integrated circuits compared, 357 radio-controlled improvised explosive devices (RCIEDs) construction, 538 jammers, 538 ramped voltage testing, 466, 470 advantages, 468–469 disadvantages, 468–469 see also voltage ramping RAMs (radio absorbent materials), 304–305 rat-race couplers, 559, 560 ratings, maximum, 497 RBSs see radio base stations (RBSs) RCIEDs see radio-controlled improvised explosive devices (RCIEDs) RDSon see linear regime on-resistance (RDSon ) realizable ratio, use of term, 260

Index

recessed-gate process, 360 reconstruction filters, use of term, 183 rectangular truncations, 224 reduced conduction angle concept of, 171 in RF power amplifiers, 164, 166, 167 reduced surface fields (RESURF), 18 concept of, 19–21 LDMOSFETs, 2–5 reflected power, 581 reflected waves, 580 reflection coefficients, 337, 574–576, 596–597, 605–606, 610 complex source, 640 hot, 622 load, 600–601 optimum complex, 640 reflection measurement, values, 586 reflection normalization, 582–583 reflection tracking, 582–583, 596–597 relative gas permittivity, 295, 296 relative humidity testing, 491–492 reliability, 446–504 amplifiers, 447 analysis, 496 definitions, 447–449 issues, 447–448 design for, 495–500 design-controlled, 496–497 and device application, 496 estimation, 486–487 fans, 311 future trends, 504 gallium nitride wide bandgap transistors, 146–152 goals, 448 components, 448 goodness measures, 447 historical trends, 501–502 importance of, 446 and metallization, 494–495 models, 496 optimization, 499–500 overview, 446, 503–504 and performance, 448 power amplifiers, 504, 523 and quality, 447–448, 486 semiconductors, 446, 502–503 strategies, 448–449 silicon carbide wide bandgap transistors, 146–152 sudden reliability problem, 146–147 technology comparisons, 501–502 terminology, 447–449 vs. temperature, 412 components, 305

677

see also quality; ruggedness reliability budgeting, 500 reliability predictions, 473–475, 503–504 evaluation procedures, 473–474 operational analysis, 474 thermal analysis, 474 reliability tests, methodologies, 446 remote radio heads (RRHs), 441 residual errors, 598–599 resistive-inductive-capacitive (RLC) feedback networks, 251, 274, 315 resistivity AlGaN/GaN HFETs, 132 bulk, metals, 289 gallium arsenide, 44 metals, 218–219 substrates, 44 resistors ballast, 216 chip, 316 as distributed components, 323–324 electromigration, 463–464 equivalent circuits, 318 lead-length inductance, 316 lumped, 367 in microwave hybrid power amplifiers, 316–318 modeling, 315 in printed circuit boards, 285 scattering parameters, 318 in silicon LDMOSFETs, 36–37 in silicon VDMOSFETs, 36–37 surface mount, 316–318 thick-film, 318 thin-film, 498 resists, 78–79 photoresists, 483, 493 Restriction of Hazardous Substances (RoHS), 294 RESURF see reduced surface fields (RESURF) return loss (RL), 336–337 RF bias acceleration, 472–473 applications, 472–473 and hot carrier injection, 473 RF connections current maximization, 314 and discontinuities, 314 housings, 311–315 printed circuit boards, 312, 314–315 RF performance, vs. biasing, 348–349 RF power, definitions, 599 RF power amplifiers (RFPAs) altitude, 240 AM–AM distortion, 237 AM–PM distortion, 237 applications, 1, 233 commercial, 236 industrial, 235

678

Index

RF power amplifiers (RFPAs) (cont.) medical, 235 military, 234–235 radio base stations, 411–412 scientific, 235 basic elements, 242–243 building blocks, 526 capacitors, input/output coupling/decoupling, 250, 259 classes A to S, 159–186 active device models, 161–162 inverted modes, 179–180 multimodes, 184–186 variances, 186 concurrent power, 247 conducted/radiated emissions, 241 conducted/radiated susceptibility, 241 design future trends, 282–283 hypothetical, 252–282 issues, 1 procedures, 242 redundancy, 247 system level overview, 242–252 thermal, 411–442 distortion harmonic, 239 intermodulation, 239 dynamic range, 237–238 efficiency, 238, 282, 416, 440 trade-offs, 527 equipment, 416–417 fall time, 238 feedback networks, 251, 267–268 frequency response, 236–237 gain, 237 gain flatness, 237 gain linearity, 237 gain temperature stability, 237 hardware, realization, 234, 241–242, 254–255 heat flows, 419 heat sinks, 417 historical background, 160 inductors, coupling/decoupling, 250, 259 input/output coupling/decoupling networks, 250, 259 IR images, 435 linear, 160 linearity, trade-offs, 527 markets, 1, 232–233 materials, thermo-physical properties, 423–427 mating surface flatness, 439 maximum power transfer, 282, 283 mean time to failure, 241

modules block diagrams, 243, 244 design overview, 243–246 hypothetical, 252–282 multilevel breakdown, 256 physical construction, 271–273 test results, 273–280 multistage, 527 noise floor, 239 operating temperature range, 240 pallets, 417, 418 thermal stack-up, 417–418, 438 phase linearity, 237 physical construction, 418–419 power output, 236 practical realization, 232–283 overview, 232 processes, 233–242 RF power transistor selection, 243–244 processes, 243 pulse droop, 238 pulse overshoot, 238 rack-mounted, 417 reduced conduction angle, 164, 166, 167 ringing/settling time, 238 rise time, 238 shock/vibration, 240–241 specifications qualitative delineation, 233–236, 252–253 quantification, 234, 236–241, 253–254 realization, 241–242 stability, 239–240 system block and wire diagrams, 242–243, 254 temperature profiles, 430–431 thermal design, 411–442 advanced, 432–440 basics, 413–423 future trends, 440–442 importance of, 411–413 in portable products, 413–415 thermal management, 251–252, 432–440 thermal performance characterization and prediction tools, 427–432 conduction and, 420–421 convection and, 421–422 and heat transfer, 419–423 phase change cooling and, 423 radiation and, 422–423 topology, 525 voltage standing wave ratios input, 239 load, 239 see also gallium nitride RF power amplifiers (GaN RFPAs); hypothetical RFPA subsystem modules; microwave hybrid power amplifiers (MHPAs)

Index

RF power transistors absolute maximum ratings, 244, 247 applications, 39, 244, 247 bias/thermal tracking networks, 249–250 breakdown voltages, 246, 248 capacitances input, 246, 249 output, 246, 249 reverse transfer, 246, 249 classes, 249, 255–257 datasheets, 244–246 design issues, 1 efficiency, 244, 248 electrical characteristics, 244 frequency range, 244, 247–248 future trends, 282–283 gain, 244, 248 as ideal current sinks, 165 impedance input, 248–249 output, 248–249 impedance matching, 250–251, 259–267, 283 HF, 250 UHF, 250 VHF, 250 joining processes, 426–427 large signal impedance, 246 load mismatch tolerance, 246 power output, 244, 247, 255 scattering parameters, 246, 249 selection, 243–244, 255–257 applications and, 246 class, 246 process guidelines, 246–249 thermal performance, 32 thermal resistance, 244, 248 threshold voltages, 246, 248 transfer function plots, 249 typical, 246 RF testing, 430 accurate, 570 automatic, 370 on-wafer, 80 RF/microwave push-pull amplifiers, 557–559 advantages, 558 balun structures, 558 block diagrams, 557–558 disadvantages, 559 RFICs see radio frequency integrated circuits (RFICs) RFPAs see RF power amplifiers (RFPAs) Rjc see junction-to-case thermal resistance (Rjc ) RL (return loss), 336–337 RLC (resistive-inductive-capacitive) feedback networks, 251, 274

679

RoHS (Restriction of Hazardous Substances), 294 Root model, 88 RRHs (remote radio heads), 441 ruggedness, 22–26 and drain engineering, 24 factors affecting, 23 measurement, 22–23 Ruthroff unbalanced–unbalanced transformers, 555, 556, 557 S parameter measurements see scattering (S) parameter measurements S parameters see scattering (S) parameters safety regulations, 570 SAGs see self-aligned gates (SAGs) satellite down converters, gasket-sealed, 299 saturation effect, 615 scalar network analyzers limitations, 582–586 measured values, determination, 582–583 parasitic effects, 583–584 scalar reflection measurements, 582 scalar transmission measurements, 585 scattering (S) parameter measurements, 580–599 requirements, 641 uncertainties, 598–599 scattering (S) parameters, 88–89 applications, 206 attenuators, 596 capacitors, 206–207 concept of, 580–581 in database models, 212 DC, 208 definition, 581 dummy, 207–208 hot, 622–623 limitations, 641 magnitudes, measurement, 586–587 mixed-mode, 608–611 models, 206–208 in harmonic-balance analysis, 207–208 interpolation, 206 issues, 206–208 vs. lumped-element models, 208 phase, measurement, 586–587 resistors, 318 RF power transistors, 246, 249 SCDs (source control drawings), 248 Schottky barrier gate, 45 Schottky diodes, 345–347 Schottky gate electrodes, 78–79 Schottky gate field effect transistors, 45 failure mechanisms, 454–455 materials, 45 scientific markets, RF power amplifiers, 235

680

Index

screw locking epoxies and, 304 housings, 304 torques, 308 sealing housings, 294–299 issues, 294 mobile phones, 414 and moisture ingress, 295–296 see also gasket sealing; hermetic sealing second-order intercept (SOI) point, 611–613 self-aligned gates (SAGs) multifunction, 360 process, 360 self-heating models, 214–215 disadvantages, 215–216 self-resonant frequencies (SRFs), 320–321 SEM (spectrum emission mask), 522, 525 Semanskii iteration, 199 semiconductor equations, 128–129 semiconductors electron velocity vs. electric field transport characteristics, 113 failure mechanisms, humidity, 490 failure rates, 455–456, 458 manufacture, processes, 492–493 metallization, 488 operating temperature, measurement, 428–429 properties, 112 and performance, 111 reliability, 446, 502–503 strategies, 448–449 RF output power vs. frequency, 104 see also diodes; transistors sensors temperature, 258, 429 thermistor, 571 see also diode sensors; power sensors; thermal sensors sequencing circuits, 348 SER (symbol error rate), 635–636 shape parameter, definition, 459–460 shooting methods, 203–204 short standards, 582–583 short-term signal level scorecards, 281 Shubnikov–DeHaas mobility measurements, 114 SiC see silicon carbide (SiC) 4H-SiC BJTs see 4H-silicon carbide bipolar junction transistors (4H-SiC BJTs) 4H-SiC MESFETs see 4H-silicon carbide metal semiconductor field effect transistors (4H-SiC MESFETs) sidegating, 454 sigma (shape parameter), 459–460

signal flow charts, stability, 606 signal-to-noise ratio (SNR), 637 significance testing, 449–450 silicon thermal conductivity, 425 wafers, 357 silicon bipolar transistors historical background, 1 limitations, 1–2 silicon carbide (SiC) applications, 105–106 charge carrier mobility, 113–114 hole mobilities, 115 4H-silicon carbide bipolar junction transistors (4H-SiC BJTs) fabrication, 106 gain, 106–107 high-power, 106–107 performance, 106 4H-silicon carbide metal semiconductor field effect transistor amplifiers, 120–122 current gain, DC, 121 performance, 122 RF, 121, 122 power gain, DC, 121 power gains, 121–122 small-signal current gains, 121–122 4H-silicon carbide metal semiconductor field effect transistors (4H-SiC MESFETs) advantages, 118–119 applications, microwave power amplifiers, 105 background, 106–108 current–voltage relationships, DC, 120 development, 107–108 fabrication, 107–108, 118–119 field plates, 108 future trends, 152–153 limitations, 108 performance, 107–108, 120 structure, 119 β-silicon carbide nanowires, applications, 108 silicon carbide transistors, background, 106–108 silicon carbide wide bandgap transistors, 103–153 breakdown, 112–113 development, 104–105 device design, 118–125 future trends, 152–153 large-signal effects, 130–152 gate leakage, 144–146 nonlinear source and drain resistances, 133–143 reliability and time-dependent performance degradation, 146–152 space-charge limited current transport, 130–133

Index

material parameters, 111–115 models, 125–130 equivalent circuits, 125–127 physics-based large-signal, 128 properties, 112 RF performance, 118–125 thermal conductance, 112–113 silicon lateral double diffused metal–oxide–silicon field effect transistors (silicon LDMOSFETs), 1–39 advantages, 2, 432–433 applications, 39, 433 50V and higher, 35–36 land mobiles, 34–35 mobile telephony, 35 radio base stations, 523–524 bondpad manifolds, 29, 32 breakdown voltages, 5, 17–22 capacitances, 15–16 drain-to-source, 5, 13, 15–16 gate-to-drain feedback, 16 gate-to-source, 16 parasitic, 12–15 channel doping profiles, 19 construction, 2–8 dies, 2–5 cross-sections, 4, 23, 32, 433 current flows, 11, 31 current paths, 11 current transport, 10–11 current–voltage characteristics, 20 depletion region boundaries, 5 design, 27–39 metal, 30–32 thermal, 32–34 device physics, 10–27 disadvantages, 2 doping profiles, 6, 14–15 drain metallization, 7–8 drain resistance, 14–15 drain structure optimization, 5 drain-to-source pitch, 28–29 efficiency, 34 electrodes, 433 electromigration, 30–32 enhancement mode, 135 field plates, 7–8, 18–19 effects, 8 frequency issues, 36–37 frequency limits, 42 frequency optimization, 37 frequency responses, 12–14 gate construction, 5–6 gate finger arrays, 27, 28 gate length, 5–6, 36–37 gate oxides, 5–6

gate resistance, 5–6, 14–15 gate width, 27, 36–37 limitations, 37 heat dissipation, 433 historical background, 1–2 hot carrier injection, 2–5, 17–22 levels, 7–8 infrared scans, 34 layout, 3, 27–39 top-down finger, 27–29 linear regime on-resistance, 5, 17–22 market domination, 39 multiple heat source fingers, 433, 434 n-drift region, 2–5, 7–8 and field plates, 18–19 length change, 25–26 long, 26–27 operating voltage, issues, 26–27, 34–36 overview, 1–2 P + sinker, 7, 28–29 p-epi region, 5, 26–27 packaging, 82–83 parasitic drain resistance, 7–8 parasitic elements, behavior, 12–17 PHV implants, 6–7 power density, 441 power levels, 34 power output, 27 quiescent current degradation, 22 reduced surface fields, 2–5 regions, 6–7 resistances, parasitic, 12–15, 33–34 resistors, 36–37 ruggedness, 22–26 snapback, 22–26 source, 7 terminals, 10–11, 29 thermal design, 432–440 thermal flux, 441 thermal performance, 32–33 thermal resistance, 433 spreading, 433–436 thermal scans, 35 silicon LDMOSFETs see silicon lateral double diffused metal–oxide–silicon field effect transistors (silicon LDMOSFETs) silicon nitride, applications, dielectrics, 453 silicon nitride capacitors structure, 466 voltage acceleration, 466–471 silicon nitride films breakdown voltages, 466 characterization, 466 silicon VDMOSFETs see silicon vertical double diffused metal–oxide–silicon field effect transistors (silicon VDMOSFETs)

681

682

Index

silicon vertical double diffused metal–oxide–silicon field effect transistors (silicon VDMOSFETs), 1–39 advantages, 2 applications, 39 50V and higher, 35–36 bodies/substrates, 8–9 bondpad manifolds, 29 breakdown voltages, 17–22 capacitances gate-to-drain feedback, 16 gate-to-source, 16 parasitic, 12–14, 16 construction, 8–9 cross-sections, 9 current flows, 12 current paths, 11 current transport, 10–11 design, 27–39 metal, 30–32 thermal, 32–34 device physics, 10–27 disadvantages, 2, 9 drain, 8–9 drain voltage, 8–9 drift region design, 9 efficiency, 34 electromigration, 30–32 frequency issues, 36–37 frequency optimization, 37 frequency responses, 12–14 gate finger arrays, 27 gate length, 36–37 gate width, 27, 36–37 limitations, 37 historical background, 1–2 hot carrier injection, 17–22 layout, 27–39 top-down finger, 27–29 linear regime on-resistance, 17–22 market domination, 39 n drift, 8–9 n-drift region, length change, 26 operating voltage, issues, 26–27, 34–36 operation, high voltage, 26 overview, 1–2 packaging issues, 9 parasitic elements, behavior, 12–17 PHV implants, 19 power levels, 34 power output, 27 resistances, parasitic, 8–9, 12–14, 16, 33–34 resistors, 36–37 ruggedness, 22–26 snapback, 22–26 source-to-gate pitch, 28–29

terminals, 10–11 thermal performance, 32–33 simulators three-dimensional, 211–212 see also electromagnetic simulators; plant simulators single-layer capacitors (SLCs) applications, 318–321 structure, 318–320 sinking gates FETs, 458 mechanisms, 459–462 skin depth determination, 288–289 use of term, 288–289 skin effects, and metal losses, 218 SLCs see single-layer capacitors (SLCs) small-signal models equivalent circuits, 84–85 for GaAs FETs, 84–85 Smith charts, 337–338, 586–587, 600–601, 606–607, 640 SMLPs see surface mount leadless packages (SMLPs) snapback, 22–26, 59 effects, 58–59, 60 prevention, 24 use of term, 23–24 snapback current characterization, 25–26 increase, 24 and ruggedness, 23 snapback voltage, 23–24 characterization, 25–26 SNR (signal-to-noise ratio), 637 soft substrates, 285 dimensional issues, 289 materials, 285–286 moisture absorption, 293 use of term, 285–286 SOI (second-order intercept) point, 611–613 solders, for die attach, 426–427 solid-state devices models, 213–216 thermal effects in, 214–216 solid-state power amplifiers (SSPAs), applications, 284 solid-state transistors applications, microwave systems, 103 upper frequency limits, 103–104 and vacuum tubes compared, 103 source control drawings (SCDs), 248 source stepping, use of term, 223 source-pull measurements, 619–622 set up, 621 spacing, vs. quality, 485, 494

Index

sparse matrices, 192–193 specification thresholds, as failure criteria, 449–450 spectrum analyzers, 268 adjacent channel power ratio, 627, 628 applications, 586 power measurements, 579–580 implementation, 580 intermodulation products, 612 noise figure, 628 properties, 579–580 spectrum emission mask (SEM), 522, 525 SPICE models, 222, 223 development, 205 in harmonic-balance analysis, 226 SRFs (self-resonant frequencies), 320–321 SSPAs (solid-state power amplifiers), applications, 284 stability linear, issues, 605–608 signal flow charts, 606 stability circles, 606–607 stability factors, 341–343 definitions, 607–608 standard deviation, and median compared, 468 static induction transistors (SITs) applications, 107 fabrication, 107 operation, 107 Stefan–Boltzmann constant, 422 step attenuators, 587–588 stubs distributed, 324 impedance matching, 338 lossy, 325–326, 327 open-circuit, 325–326, 354 short-circuited, 324, 326, 349, 354 substrates backings, 291 metal, 291 ceramic packages, 392–393 dielectric constant, 287–288 factors affecting, 293 dielectric losses, 288–289 impedance standard, calibration standards, 595–596 isotropy, 287–288 materials, failure mechanisms, 454 materials selection, and impedance range, 289 MMICs, 359, 361 comparisons, 361 mounting, 292 parameters, for hybrid amplifiers, 286 properties, 287 resistivity, 44 and test fixtures, 595 thermal resistance, 437–438

683

thickness, 289 issues, 289 trace dimensions, 290 types of, 285 see also hard substrates; soft substrates success, probabilities of, 447 sudden reliability problem, 146–147 surface mount devices, heat transfer, 307 surface mount leadless packages (SMLPs), 83, 395–396, 399 construction, 82–83 development, 394 types of, 394 sweet spot, use of term, 261–262 symbol error rate (SER), 635–636 system error correction 3-term error model, 589 7-term error model, 589, 592 overview, 588–589 in vector network analyzers, 588 T-check, 598–599 TACS (Total Access Communication System), 508–509 Taguchi technique, 377 talk time, mobile phones, 508 tantalum nitride, applications, 316 Taylor series, 201, 611, 614–615, 625, 632–633 TDDB see time-dependent dielectric breakdown (TDDB) TDMA see time division multiple access (TDMA) technology comparisons over time, 501–502, 503 of reliability, 501–502 tee-equivalent circuits, 126–127 large-signal, 128 small-signal, 126 telecommunications systems, power amplifiers in, 508 temperature and component reliability, 305 and dielectric constants, 287 and humidity, 488–489 and mean time between failure, 412 vs. electromigration, 33 vs. lifetimes, 462 vs. performance, 411–412 vs. reliability, 412 see also noise temperature temperature acceleration effects, on FET lifetimes, 498 temperature field patterns, mobile phones, 414–415, 416 temperature monitors, 479–480 temperature profiles, RFPAs, 430–431 temperature sensors, 258, 429

684

Index

temperature-humidity-bias (THB) test, 83–84 termination space, multidimensional, 185–186 test fixtures calibration with, 593–596 and substrates, 595 test port match, 583–584 directional elements, 585 testing element, 448–449 environmental, plastic packages, 491–492 inaccurate, 570 on-wafer, 401–403, 404 production-line, 570 qualification, 496 relative humidity, 491–492 significance, 449–450 three-terminal, 57–58 two-terminal, 57–58 verification, 496 wafer acceptance, 81 see also devices under test (DUTs); highly accelerated stress tests (HASTs); life testing; ramped voltage testing; RF testing TFE (thermionic field emission), 58–59 Tgon, 427 THB (temperature-humidity-bias) test, 83–84 THD (total harmonic distortion), 614–615 thermal acceleration, 458–462 factors, determination, 462 thermal analysis, reliability predictions, 474 thermal characterization, experimental, 427–428 thermal conductivity, 420, 423 gallium arsenide, 436 homogeneous, 420–421 materials, 423–424 at room temperature, 425 behavior, 424–425 see also conduction thermal cycling, 477–478 thermal design mobile phones, 413–415 radio base stations, 416–419 RF power amplifiers, 411–442 silicon LDMOSFETs, 432–440 thermal diffusivity, 420, 423 thermal droop, 52, 53 thermal effects, in solid-state device models, 214–216 thermal excursions copper bumps, 478–482 failure criteria, 480 failure distributions, 477 interconnect vias, 475–478 power cycling, 480–481 profile data, 477 standards, 476

testing, 476 thermal flux, trends, 441 thermal greases, 427 thermal inertia (TI), 305–307 thermal load, spreading, 307 thermal management cost overheads, 411 future trends, 442 radio base stations, 411 RFPAs, 251–252, 432–440 see also heat sinking; heat transfer thermal modeling, computer-aided, 427–428 thermal noise, 636 thermal pads, 427 thermal performance and heat transfer, in RFPAs, 419–423 housings, 306 LDMOSFETs, 32–34 measurement, 428–431 modeling, 431–432 RF power transistors, 32 RFPAs characterization and prediction tools, 427–432 conduction, 420–421 convection, 421–422 phase change cooling, 423 radiation, 422–423 simulation, 431–432 VDMOSFETs, 32–34 thermal ratings, 496–497 thermal resistance (TR) determination, 305–307 die attach, 436–437 and die thickness, 436 factors affecting, 436 heat sinks, 439–440 lead–tin–silver die attach, 437 microwave hybrid power amplifiers, 305 microwave power field effect transistors, 73–74 reduction, 307–308, 425 RF power transistors, 244, 248 silicon LDMOSFETs, 433 spreading, 433–436 substrates, 437–438 vias, 307 see also contact thermal resistance; junction-to-case thermal resistance (Rjc ) thermal scaling, 214–215 thermal sensors, 571, 572 applications, 571 thermal shock, 477–478 thermal test chips, 429 thermal vias, 414 thermionic field emission (TFE), 58–59 thermistor power meters, 571 principles, 572

Index

thermistor sensors, 571 thermocouple thermometers, 428 thermographic phosphors, in operating temperature measurement, 428–429 thermoset materials advantages, 286–287 dielectric constant, 286–287 thick-film resistors, 318 thin-film resistors, reliability guidelines, 498 third-order intercept (TOI) point, 611–613 3rd Generation Partnership Project (3GPP), 519–520 power classes, 522 specifications, 518–519 three-dimensional simulators, 211–212 three-terminal tests, 57–58 threshold malfunction, 490 through–open–match (TOM) calibration, 598–599 TI (thermal inertia), 305–307 time division multiple access (TDMA), 511–512 measurement, 627 time in operation, wireless sensor networks, 508 time-dependent dielectric breakdown (TDDB), 453–454 measurement, 465–466 MIM capacitors, 466–471 time-domain analysis, 202–203 applications, 616 computational costs, 203 differential equations, 202 procedures, 202–203 variants, 203–205 frequency-domain models, 204 multitone analysis, 204–205 shooting methods, 203–204 TLPGs (transmission line pulse generators), applications, 25–26 TMAs (tower mount amplifiers), 441 TOI (third-order intercept) point, 611–613 TOM (through–open–match) calibration, 598–599 toroids, 553–554 Total Access Communication System (TACS), 508–509 total harmonic distortion (THD), 614–615 tower mount amplifiers (TMAs), 441 TR see thermal resistance (TR) track dimensions, 290–291 transconductance (gm ), 60, 353 compression, 53 dispersion, 55 FETs, 134–135 transducer gain, 599–600 determination, 621–622 maximum, 600–601 transformer matching, 339–341 capacitor-loaded, 342 double short, 341

685

transformers autotransformers, 553 balanced–balanced, 556–557 input, 265 output, 272 quarter-wave, bandwidth, 339 see also coupled-coil transformers; transmission line transformers; unbalanced–unbalanced transformers transistor amplifiers configuration, 115 two-port network, 115 current–voltage relationships DC, 115–117 RF, 117 efficiency, 117–118 impedance matching, 117 operating principles, 115–118 power delivery, 115–117 RF performance, 117 transistors, 331–332 bias networks, 345, 346 channel current degradation, 460 degradation, 461 life testing, 459–462 median lives, 461 models, 125–130 equivalent circuits, 125–127 physics-based large-signal, 128 out-of-band performance, 349 performance, false claims, 331 properties, 112 pulse profile method, 634–635 reliability guidelines, 497–498 screw fixing issues, 308 selection criteria, 332 silicon carbide, background, 106–108 time to failure vs. voltage, 472 see also bipolar junction transistors (BJTs); field effect transistors (FETs); high-electron mobility transistors (HEMTs); RF power transistors; solid-state transistors; static induction transistors (SITs); wide bandgap transistors transition frequency (fT ) definition, 62–63 determination, 90 limitations, 63 transmission coefficient, 585, 603–604 transmission line pulse generators (TLPGs), applications, 25–26 transmission line transformers, 250–251, 259–261, 262–265, 554–557 building blocks, 554 coaxial quarterwave, 555 input insertion loss, 264–265, 266

686

Index

transmission line transformers (cont.) maximum power transfer, 556 mutually coupled inductances, 263, 264 parasitic models, 262 topological synthesis, 261 transmission lines cascaded, 620 as distributed components, 324 in high-power RF measurements, 578 interferences, 608–610 for MMICs, 362 parameters, 355 selection criteria, 554–555 single-ended, 608 strip, closed-form models, 210 symmetrical, 608 thickness, factors affecting, 288–289 as unbalanced transformers, 555–556 see also microstrip; stubs; waveguides transmission loss, 337 transmission measurements, 586 transmission normalization, 585 transmitted power, 581 transmitted waves, 580 trapping effects, 53–54 consequences, 54–57 breakdown voltage increase, 56 drain lag, 55–56 gate lag, 55–56 kink effect, 56–57 large-signal model inaccuracies, 56 memory effects, 56 output conductance dispersion, 55 power output reduction, 54–55 transconductance dispersion, 55 and large-signal models, 87–88 minimization, 54 traveling-wave tube amplifiers (TWTAs), 534 triangular truncations, 224 trigger signals, 627 triplexer method, 620 Triquint TOM models, 86–87 tuners, passive, 620 tuning disks, 355 tunneling, 58–59 two-dimensional simulators, 210–211 two-port networks, linear distortion, 603 two-terminal tests, 57–58 two-tone signals, 613–614 generation, 613–614 measurement issues, 613–614 TWTAs (traveling-wave tube amplifiers), 534 U see unilateralized gain (U) UGW see unit gate width (UGW)

UMTS see Universal Mobile Telecommunications System (UMTS) unbalanced–unbalanced transformers, 555–556 Ruthroff, 555, 556, 557 uncertainties measurements, 598–599 sources of, 574–576 types of, 598 unilateralized gain (U) curves, 62, 90–91 definition, 62 unit gate width (UGW) definition, 27 large, 27–28 unity circles, 606–607 Universal Mobile Telecommunications System (UMTS) bandwidth, 522 base station power classification, 523 standards, 519–520 Unix, pipes, 229 unknown–open–short–match (UOSM) calibration and 7-term error model, 592 with mixed test port types, 591–592 UOSM calibration see unknown–open–short–match (UOSM) calibration vacuum tubes applications, microwave systems, 103 RF output power vs. frequency, 104 in RF power amplifiers, 160 and solid-state transistors compared, 103 valves see vacuum tubes VCVSs (voltage-controlled voltage sources), 191–192 vector network analyzers (VNAs), 264–265, 586–588, 604 applications, 268, 586 scattering parameter measurements, 599 architecture, 587–588 building blocks, 587, 602–603, 631 calibration, 622 dynamic range, 616 effective system data, 589, 591 raw system data, 589, 591, 597 sweeps, 603 system error correction, 588 two-port, 587 velocity-field curves, nonlinear, 131 verification testing, 496 Verilog A, 222 vertical double diffused metal–oxide–silicon field effect transistors (VDMOSFETs), 249 see also silicon vertical double diffused metal–oxide–silicon field effect transistors (silicon VDMOSFETs)

Index

vias manufacture, 291 thermal, 414 thermal excursions, 475–478 thermal resistance, 307 see also interconnects virtual gate effect, 145 VNAs see vector network analyzers (VNAs) voltage vs. quality, 486–487 see also breakdown voltages; snapback voltage voltage acceleration, 484 capacitors, 487–488 factors, 465–472 HEMTs, 471–472 MIM capacitors, 465–466 silicon nitride capacitors, 466–471 voltage ramping, 468 MIM capacitors, 466–471 see also ramped voltage testing voltage regulators, 348 low drop out, 348 voltage standing wave ratios (VSWRs), 337 RF power amplifiers input, 239 load, 239 in ruggedness testing, 22–23, 25–26 voltage waves, 580 voltage-controlled voltage sources (VCVSs), 191–192 VSWRs see voltage standing wave ratios (VSWRs) W-CDMA see Wideband Code Division Multiple Access (W-CDMA) wafer acceptance test (WAT), 81 wafer probes, calibration with, 593–596 waste heat disposal, 411, 427 radio base stations, 411, 416–417 WAT (wafer acceptance test), 81 water cooling, housings, 311 water vapor and sealing, 295 thresholds, 490 wave propagation, devices under test, 580 waveform balance approach, 201 waveguide flanges, 589 waveguides, 299, 311–312 discontinuities, 211–212 see also coplanar waveguide (CPW); stubs; transmission lines wear-out, 457 amplifiers, 447 mechanisms, 462–463 vs. defects, 475–492

687

wide bandgap materials, applications, 284 wide bandgap semiconductors, 372–373 wide bandgap transistors advantages, 111, 118 applications, 105 electron saturation velocities, 118 properties, 112 see also gallium nitride wide bandgap transistors; silicon carbide wide bandgap transistors Wideband Code Division Multiple Access (W-CDMA), 349–352, 508–509 handset amplifier simulations, 219, 220 output spectra, 529–530 Wiebull analysis, 282 Wilkinson power combiners, 334, 533–534, 538–541 amplitude imbalance, 540 applications, 538–540 frequency bandwidth performance, 541, 542 and Gysel combiners compared, 545 phase imbalance, 540–541 single-section, 540 Wilkinson splitters, 328–331, 547, 552 design, 541, 542 layouts, 541, 542 performance, 543 WiMAX see Worldwide Interoperability Microwave Access (WiMAX) wire bonding methods, 397 in MMIC PA package assembly, 396, 397–398 modeling, 397–398 procedures, 397 wireless communications power amplifiers, 519–530 design, 523–526 requirements, 522–523 requirements, system level, 522–523 wireless sensor networks, time in operation, 508 Wirelines, 328, 329 Worldwide Interoperability Microwave Access (WiMAX), 38–39 frequency bands, 520, 521 standards, 520–522 X-parameters, 88–89 Y parameters see admittance (Y) parameters Y-factor method, 638–640 setup, 638 yield, measurement, 484 Zener diodes, 347 zeroing, 574