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p/2 then hW>hE and the observed contact angle increases (wetting degrades) as roughness increases. Wenzel’s equation is derived under a set of assumptions that are typically not strictly satisfied [90], so Eq. (47) is an approximate relationship and does not always yield accurate predictions. For instance, Eustathopoulos et al. point out that experimental observations show that advancing contact angles increase with increasing roughness for both nonwetting liquids (e.g., Hg on SiO2) as well as certain wetting liquids (e.g., H2O on SiO2). Given the fact that there are numerous surface finishes on substrates used in microelectronics soldering processes, each with its own roughness properties, Wenzel’s equation alerts to the possibility of altered wetting characteristics. c. Random Roughness Effect on Wetting. Realistic surface roughness takes the form of randomized sharp peaks and troughs, rather than the idealized sinusoidal rough surface discussed above. It is well known that contact lines can arrest or pin on geometrical eccentricities. Consider a contact line as it advances from point A to point C in Fig. 27. The solid surface has a discontinuity in slope at point B. If the contact line is advanced sufficiently slowly, then the value of the dynamic contact angle along AB remains approximately hE and the L/V interface shape
FIG. 27 Contact line pinning at a geometrical eccentricity on a rough surface.
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remains unchanged as the line moves from A to B. When the line arrives at point B, it becomes pinned at B despite attempts to advance it. However, the L/V interface shape begins to change and the contact angle h increases continuously from its equilibrium value hE to the value hE+/. When h=hE+/, the L/V interface makes an angle of hE with the solid surface BC (measured within the liquid), and this is the condition for the line to unpin and to begin moving along the surface BC, again with constant angle. The pinning in the advancing case produces an observed angle greater than hE. If the contact line had instead been receding with motion from point C to point A, the pinning at B would have caused an observed angle less than hE. In this way, surface eccentricities in randomized roughness can produce hysteresis in the measured contact angle. d. The Effect of Dissolution on Roughness During Wetting. In metal–metal systems, the process of dissolution, particularly of the solid surface in the spreading liquid metal, is conjectured to dramatically alter the influence of roughness on wetting. The interactions of a spreading metal with a rough solid surface are obviously an extremely complex process. However, it is clear, for example, that a liquid metal contact line momentarily pinned on a ridge of roughness can potentially dissolve the ridge. The rate at which the ridge can be dissolved depends on many things, particularly the mass transport near the contact line, which itself depends on how far the liquid is from saturation. Clearly an understanding of how a liquid metal spreads on a rough metal substrate awaits understanding of the much more simple problem of how metals spread on perfectly smooth substrates. e. Effect of Grain Boundaries. Grain boundaries in polycrystalline metallic solids constitute a particular type of roughness. The enhancement of wetting by grain boundaries oriented normally to the contact line seems to be much more significant than the retardation of wetting by pinning on grain boundaries oriented parallel to the contact line. The enhancement of metal– metal wetting by normally oriented grain boundaries has been studied by a number of investigators [12,92,93]. The general idea is that a grain boundary can potentially serve as an open capillary through which liquid metal is wicked away from the contact line (which essentially serves as a reservoir) toward the unwetted solid. Eustathopoulos et al. [12] show that for the infiltration of a grain boundary to occur, the dihedral angle of the grain must be smaller than the value h* given by: h coshE sinhE sin * ¼ 2 hE
ð48Þ
1. Large grains vs. small grains—Given that 0
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SINGLER ET AL. during secondary spreading of Sn on Au, Rft1/2, where R is the effective radius of the drop. Meschter hypothesized that an undetermined diffusion mechanism was controlling the wetting kinetics. The contact line in Fig. 11 during the secondary spreading regime appears to be ragged as one might expect with contact line advance due to grain boundary infiltration. Because various surfaces finishes are routinely utilized during the soldering of microelectronics assemblies, further investigation is required to verify the role of their grain boundaries in advancing the solder contact line.
VI.
FLUX CHEMISTRY AND TECHNOLOGY
A.
History
Soldering with fluxes has been practiced for thousands of years by artisans and metal workers, but only began developing as a technology with the industrial revolution [94,95]. Even beyond the middle 20th century, much soldering was practiced as a skilled trade in plumbing, radiator repair, and electronic wiring. It is interesting to note that the metals still primarily involved, such as copper, tin, lead, iron, silver, and gold, were known to the ancients. Tin plating of iron was mentioned by Theophrastus as early as 320 BC and Herodotus discussed the sources of tin and amber, a fossil resin, in his ‘‘History’’ [96]. It is also interesting to note that one of the organic acids common in modern fluxes, succinic acid, was known in the 16th century as a distillation product of amber [97]. So it appears that joining of metals with solders and utilizing natural resins as part of the procedure were practiced in antiquity. Modern solder and flux technology began in the 20th century with the demands of the electronics industry. For most of the century, the most extensive utilization encompassed tin–lead solders and rosin-based fluxes. Early fluxes were used to clean surfaces in preparation for coating metals, but these were highly corrosive and required extensive washing. They consisted of strong acids and inorganic acid salts soluble in water. Electronic requirements brought about the development of rosinbased fluxes whose residues do not cause excessive corrosion. These, however, require organic solvents for postsolder operations that eventually became an environmental concern leading to a demand for ‘‘water-soluble’’ and ‘‘no-clean’’ fluxes.
B.
Definitions
1. Solder The American Welding Society defines soldering as metal coalescence below 427jC (800 jF) [94]. Therefore, the solder must be a metallic element, mixture, or alloy, which will melt, wet, spread at or below this temperature, and serve as a method to bond the metals being joined. Perhaps a more functional definition from an electronics assembly viewpoint is that soldering is a low-temperature, reversible joining process that allows rework without damaging substrates and other temperature-sensitive components [98]. For electronics applications, it is essential that bonding and electrical conductivity be maintained at operating temperatures, and withstand thermal stresses caused by environmental and power on/off cycles throughout the life of the product. Lead (mp 327jC) and tin (mp 232jC) form a eutectic alloy (mp 183jC) that has been universally utilized to attach components to printed circuit boards for more than 50 years. Some of this popularity is likely due to its compatibility with organic packaging because of its low-meltingpoint eutectic temperature, and because the Pb–Sn system allows for a hierarchy of melting temperatures, which is often useful in manufacturing electronic assemblies. With the advent of regulations leading to the elimination of lead (Pb) from solders, there are substantial challenges to obtaining the level of success and reliability that has been achieved with lead (Pb)-containing solders in the electronics industry. The choice of metallic elements in the periodic table from which a substitute solder can be derived is very limited, and a drop-in replacement appears unlikely. Examination of a few lead-free solder alloys in Table 11 reveals that some of the more
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TABLE 11 Comparison of the Melting Point and Range of Several Lead-Free and Common Sn–Pb Alloys Solder Sn–37Pb Sn–90Pb Sn–95Pb Sn–58Bi Sn–9.0Zn Sn–0.7Cu Sn–3.5 Ag Sn–2.5Ag–0.8Cu–0.5Sb Sn–3.5Ag–4.8Bi Sn–2.0Ag–7.5Bi–0.5Cu Sn–2.0Ag–4.0Bi–0.5Cu–0.1Ge Sn–3.5Ag–1.5In Sn–2.8Ag–20In
Melting point (jC) 183 308–312 268–302 138 198.5 227 221 217 213–218 205–210 217–218 210–217 175–187
likely candidates will require soldering melt temperatures 30–40j higher than eutectic Sn–Pb. This poses significant challenges in terms of organic packaging and flux effectiveness. For more examples of lead-free solder candidate alloys, see Refs. 99 and 100. 2. Flux The word flux is derived from a Latin word meaning ‘‘to flow.’’ A flux is usually required to facilitate the wetting of the bonding surfaces and the flowing of solders. Typically, flux is defined as a substance capable of cleaning or removing the oxide from a metal surface [101]. This definition is somewhat simplistic because the metallic oxides are seldom actually removed during soldering of electronic components. Most soldering processes are performed with fluxes and oxides left on the surfaces to be soldered. In fact, the flux–oxide reaction product becomes an integral component in facilitating the wetting and joining process. Removal only occurs if the oxides are reacted (typically as an acid–base reaction with the flux), dissolved in a solvent system, and rinsed away by additional solvents. Except for some special processes, which will be described briefly, the metal oxides are only displaced by flux during the temperature cycle. Flux is sometimes thought of as a catalyst that lowers the surface tension between the molten solder and a metal surface [98]. In reality, the chemistry of flux interactions at oxide surfaces can be very complicated and involve acid–base, oxidation–reduction, and coordination-type and adsorption-type reactions discussed in later sections [102–104]. Spalik prefers to think of most fluxes used for electronic soldering as substances that react as Bronsted–Lowry acids with metallic oxides to form their respective salts and water, and that the salts serve as surfactants that promote solder wetting. 3. Activity Fluxes contain an agent(s) that chemically reacts with the surface tarnish on a metal surface so that it can be wetted by solders. The reaction results in the formation of a chemical compound(s) that is soluble in the liquid flux, exposing the surface so it can be wetted by the molten solder. Some agents are more efficient than others in removing tarnish layers based on their physical and chemical characteristics, generally referred to as a flux’s activity. 4. Thermal Activation The activity of agents added to a flux to remove surface tarnishes is temperature-dependent. That is, a temperature level must be attained before the material becomes active (i.e., the activation temperature). For example, this may coincide with a dissociation temperature that provides
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species that react with tarnishes as is the case with amine hydrohalides. In other cases, as occurs with rosin fluxes, activation is initiated when changing from a solid to a liquid form. The same is true for gaseous fluxes such as hydrogen, which must be heated to elevated temperatures before it can be effective in reducing metal oxides. However, in some cases, particularly with organic activators, the flux activity can be altered due to thermal exposure and become progressively less active and ultimately inactive. A common flux (water-white rosin) utilized in the solder reflow attachment of flip chips to their carriers exhibits this characteristic. Also, evaporation can deplete the activator to the point where its concentration is too low to be effective (i.e., an excessive hold at temperatures just below the solder melting temperature can render a flux ineffective). It is essential that the reflow thermal profile be optimized to take advantage of an activator’s most effective activity temperature range. 5. Solder Wetting The parameters associated with and the mechanism of solder wetting are described in great detail in other sections of this chapter. It is necessary for a flux to chemically clean the mating solder and metal surfaces at their mutual interface to assure intimate contact that promotes chemical bonding between the solder and metal surfaces. Cleaning of the surface at the interface through the action of the flux serves to alter the surface energy equilibrium in a way that favors exchanging the solid/flux and solid/solder interfaces for a solid/solder interface—in other words, driving the reaction in a direction that favors solder wetting.
C.
Purpose and Function
In soldering applications, the primary purpose of a flux is to promote the solder wetting of the interfaces to be joined, and assist in the formation of good solder joints. The interfaces may consist of a molten solder in contact with a solid metal as Cu, or two solders in contact with each other, in which case at least one is molten. To achieve reaction (i.e., wetting and bonding), the flux typically lowers the surface energies by reacting with the oxides on the surfaces of both the solder and the metal the solder is to wet. To promote solder wetting, the flux must first dissolve materials that may be absorbed in the uppermost surface layers of a solid such as surface gases, water vapor, or materials from upstream processes. Even gold surfaces that do not have tarnish can have adsorbed materials at the surface that can inhibit solder wetting. Metal surfaces left in the ambient react to form a tarnish layer that is an oxide(s), but can be carbonates, sulfides, or a combination of these. Flux must free the surface of these contaminants in order for the solder to bond with the underlying base metal. Once the base metal is exposed, the flux must act as a protective layer to prevent the ambient gases from reacting with the surface metal to reoxidize and form a new tarnish layer before the solder wets the surface. In addition to promoting wetting, some fluxes may also facilitate heat transfer to the joint area. Also, the tackiness of flux is utilized to physically maintain the alignment and position of components and devices on electronic assemblies between the time they are placed and the time they are reflowed. Flux is an important ingredient of solder pastes and is a major factor contributing to a paste’s stencil printing characteristics and quality of print. The flux can be designed to support solder microspheres to prevent slumping.
D.
Flux Requirements
In order for a flux to achieve its purpose and function, it must meet or possess certain characteristics. Some requirements are fundamentally common to all flux materials, whereas others are application-specific: 1. Stability at soldering temperature—A flux may possess sufficient activity to remove a tarnish layer from a surface, which is to be wetted by solders. However, if the evaporation or sublimation rate of the active ingredient in a flux is too rapid, the surface may be left unprotected. If there is sufficient time for the surface to reoxidize before solder wetting has occurred due to the reaction with ambient gases (particularly oxygen)
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at elevated soldering temperatures, wetting to the surface will be marginal at best, subsequently when the solder becomes molten. Fluxes must therefore be relatively stable at the soldering temperature to maintain the pristine solder-wettable characteristics of the base metal after the tarnish has been removed. 2. Slow degradation rate at soldering temperature—A flux may have sufficient activity to remove tarnish from a surface to be soldered and good stability at the soldering temperature (i.e., low evaporation or sublimation rate), but still not be adequate. Fluxes typically lose their activity over time at the soldering temperature, and more rapidly at higher temperatures due to chemical (i.e., structural) changes that the active ingredient undergoes. Although some degradation is acceptable, this process must be sufficiently slow at the soldering temperature to allow a flux to remove a surface tarnish in proper preparation for solder wetting to occur. Depending on the flux system, this condition can sometimes be mitigated. For example, if the active ingredient is rosin, a flux material with fairly low activity, it may be possible to add a more active ingredient depending on circumstances. In this way, a tarnish may be removed before the rosin decomposes into a charred mass that prevents wetting and subsequently becomes difficult to clean. 3. Easily displaced by solder—A flux must have the capability to dissolve the tarnish layer from both the solder and any surface to be soldered because the mating interface must be pristine to assure optimum wetting. As noted, the flux must prevent reoxidation of the mating interface surfaces. The solder proceeds to start wetting the clean metal surface below the flux flowing in an outward direction. But in order for wetting to proceed, the flux must be displaced (i.e., pushed ahead of the solder front). The ability of the flux to maintain a viscosity that allows the displacement process to continue, thus enabling complete wetting, is clearly a key requirement. 4. Easily removed if desired—As will be discussed, some fluxes are formulated with the intent of not removing them postsoldering. It is desirable that the raw flux, the vapors given off during soldering, and the residue formed during soldering all exhibit a low tendency to corrode the solder joint, the printed circuit board traces, and the interconnects of components and attachments. This may not always be the case, so in high-reliability and other applications, the capability must exist to easily and thoroughly remove residues and condensed vapors. As discussed in Sec. VI.E, fluxes typically consist of various ingredients, each providing a particular attribute. As noted, fluxes have several key requirements. Typically, no single ingredient provides a flux with all the required characteristics. Conversely, a flux formulated with ingredients that have only some of the required attributes will not provide optimal solder wetting, if at all.
E.
Major Flux Components
Although there are hundreds—perhaps thousands—of flux formulations, most are formulated from ingredients having similar chemical properties, with each ingredient added to meet a basic criterion. There are, of course, many ideas of how to best achieve each of these criteria, hence the numerous flux formulations. An ideal flux would be capable of meeting the manufacturing requirements, be effective in promoting wetting or joining, and leave no residues. No one flux meets these requirements for all applications, so it is necessary to make tradeoffs, or to circumvent some undesirable characteristics. The major classes of ingredients in flux are: Active species—This is usually an acid capable of reacting with the metal oxide to form salt and water. An inorganic acid forms an inorganic salt, and an organic acid forms an organic (carboxylate) salt. Solvents—Because many active species are solids, which must be solubilized for dilution and dispensing, this ingredient is selected for its ability to dilute the active ingredient, and to provide a viscosity suitable for application requirements.
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SINGLER ET AL. Activators—This component generally stimulates the flux’s interaction with the metal oxide and is usually a strong acid in the form of an amine hydrochloride that is released as the soldering temperature is approached. Surfactants—This group of compounds usually comprises polyalcohols that serve to promote wetting by reducing the interfacial surface tension between two liquids, or between a liquid and a metal surface, and helps solubilize the residues. The major categories are: detergents, emulsifiers, and wetting agents. Their function can be compared to detergents whose purpose is to solubilize both polar and nonpolar materials. Viscosity modifiers—These are substances (thickening agents) that increase the viscosity of liquid mixtures. They can gel to maintain stability in solder pastes by their emulsifying properties, have the ability to liquefy with shaking or stirring (thixotropy), and are effective in small concentrations that can be easily removed or leave no corrosive residue. The major classifications of thickening agents are: (a) starches, gums, casein, gelatin, and phycocolloids; (b) cellulose derivatives such as carboxymethylcellulose; (c) polyvinyl alcohol and carboxyvinylates; and (d) bentonite, silicates, and colloidal silica. Tackifiers—These materials help hold the components in position where they were placed before and during reflow.
Several excellent texts devote chapters to fluxes [105–108] and, although somewhat dated, one text [109] lists many formulations from patent literature. Patents and Material Safety Data Sheets (MSDS) are additional sources of flux compositions; however, it should be recalled that many suppliers keep their formulations proprietary.
F.
Flux Types
To accommodate special requirements, numerous flux formulations have been developed, many of which are either proprietary or patented [107]. There are literally thousands of flux formulations based on vendor literature, MSDS, patents, and texts [109] from which to categorize functions and deduce characteristics. Given the availability of choices, it is not unusual that often hundreds of flux formulations are evaluated when developing or optimizing solder processes. Therefore, a fundamental understanding of flux compositions is essential in selecting a flux for process optimization. Several flux classification systems that identify them as inorganic, organic, resin-based, and rosin-based fluxes are utilized. ANSI standard J-STD-004, ‘‘Requirements for Soldering Fluxes,’’ further distinguishes each classification into six more categories of low, moderate, and high activity, with and without chloride, for a total of 24 types as listed in Table 12 (i.e., the designation ROM1 specifies a rosin flux, moderately activated, with a weight percent of chloride of between 0.5% and 2.0%) [110].
G.
Inorganic Fluxes
Inorganic fluxes are composed of inorganic salts and acids. They are very active and generally used to join difficult-to-solder surfaces. These fluxes require thorough cleaning after soldering because they are very corrosive. Some common inorganic materials used as activators in fluxes are listed in Table 13. Because of their corrosive nature, fluxes based on these materials are not to be used for electronic purposes. Some exceptions are: the use of inorganic gases (i.e., dry H2) for solder bump reflow of flip chips in the wafer form after solder deposition by evaporation or plating, and inorganic additives to enhance the activity of organic fluxes. Use of fluxes based strictly on inorganic salts and acids will not be discussed in detail. However, it is instructive to examine the role of chlorides in fluxing applications and to attempt to relate it to the carboxyl group in organic fluxes. There is an extensive history of the development of halide-activated fluxes used in the electronics industry largely based on resins derived from rosin. It was recognized early on that rosin-based fluxes activated with inorganic salts (e.g., zinc and ammonium chlorides) are very effective in providing rapid wetting, but also
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ANSI Flux Classification System and Guidelines
Flux
Symbol
Activity
Type
Rosin
RO
Resin
RE
Organic
OR
Low (0%) Low (<0.5%) Moderate (0%) Moderate (0.5–2.0%) High (0%) High > (2.0%) Low (0%) Low (<0.5%) Moderate (0%) Moderate (0.5–2.0%) High (0%) High > (2.0%) Low (0%) Low (<0.5%) Moderate (0%) Moderate (0.5–2.0%) High (0%) High > (2.0%) Low (0%) Low (<0.5%) Moderate Moderate (0.5–2.0%) High (0%) High > (2.0%)
L0 L1 M0 M1 H0 H1 L0 L1 M0 M1 H0 H1 L0 L1 M0 M1 H0 H1 L0 L1 M0 M1 H0 H1
Inorganic
TABLE 13
In
Some Inorganic Activators Utilized in Fluxes
Active ingredient in flux Inorganic salts (zinc chloride, ammonium chloride, tin chloride)
Inorganic acids (hydrochloric, orthophosphoric acids)
Inorganic gases (dry hydrogen, hydrogen chloride)
Characteristics/requirements Removes heavy tarnishes Fast-reacting Active when molten Stable at soldering temperatures Mostly water-soluble Easily neutralized Must remove residues/condensed fumes Remove any common tarnish Fast-acting Stable/active at soldering temperature Very corrosive before and after soldering Must remove residues/condensed fumes Easily removed with aqueous solutions Only active at elevated temperatures Require clean, debris-free surface Hazardous, require special equipment
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that corrosion can take place almost immediately [111]. Development of organic-based hydrohalides overcame gross corrosion problems experienced with inorganic halides. 1. Counter Ions in Organic vs. Inorganic Fluxes As discussed earlier, the primary reaction of the active species in fluxes is an acid–base reaction resulting in the formation of a salt and the evolution of water. Both inorganic and organic acids share a common feature, the positive hydrogen ion H+, but the counter ions (negative ions that balance the electronic charge) are different. Almost universally, the counter ion in inorganic fluxes is a halide (fluoride, chloride, or bromide) and, by far, the most common is the chloride (Cl) ion. On the other hand, the counter ion (carboxylate) in organic acids is different for each organic acid, yet it serves the same purpose—to form a salt with the metal ions at the surface of the solder and mating-solderable surface. 2. Acid Strength Another difference between inorganic acids and organic acids is the acid strength. Generally speaking, inorganic acids are much stronger than organic acids. The concept of acidity is discussed in Sec. VI.K.1. It is generally thought that acidity or acid strength is an important factor in flux activity, and properties such as acid number and acid strength are often reported relative to flux effectiveness. Sufficient acid (hydrogen ion, H+) is required to react with the oxygen on the surface of the solder to form water. But, with the evolution of water, the counter ion must take the place of oxygen and form an organometal salt. Because the salts are the species remaining at reflow temperatures, the properties of these salts with respect to solder wetting are more important than acidity. 3. Eutectic Systems The phase diagrams (Fig. 28) of the chloride salts of Sn, Pb, Cu, Ag, and Zn depict four pairs of inorganic salts forming eutectic mixtures. It is interesting to note that they are molten and
FIG. 28 Binary equilibrium phase diagrams of Pb, Sn, Zn, and Cu chlorides.
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thermally stable within the temperature range of most soldering operations [112]. This is a significant factor with respect to the high activity of chloride containing fluxes because it confirms the fact that chloride salts remain in contact with solderable surfaces during reflow. Also, the effectiveness of chloride additions to fluxes is well documented [111,112]. Molten solders react with metallic salts in fluxes and influence solder wetting of the base metal. Surface adsorption of heavy metal ions promotes wetting (e.g., copper salts enhance wetting on copper surfaces and nickel salts enhance wetting on nickel surfaces). Because the molten eutectic chloride salts are known to be effective, it is reasonable to expect that carboxylate salts forming binary eutectics with carboxylic acids and organic solvents would also be effective. Copper stearate enhances wetting on copper surfaces [112]. Tin(II) ethylhexanoate has been reported to improve the wetting of copper by tin–zinc eutectic [113]. These salts are formed when the flux reacts with metal oxides. It would be useful if future research addressed carboxylate salts to provide the type information (e.g., melting, boiling, and decomposition temperatures) discussed for chloride salts. 4. Role of Organic Salts Little has been reported on the thermal properties of organic salt mixtures in relation to common solder metallurgy. Several handbooks [114–117] list the physical properties of inorganic and organic compounds and it is easy to find the melting, boiling, and decomposition temperatures of many substances. However, there is scarcity of data on organic salts of common solder metals. Perhaps part of this is due to the tendency of many organic salts to sublime, decompose, or be catalytically altered in this temperature range. There is also the difficulty in obtaining pure samples of these salts for analysis. Salts of organic acids play a role similar to chloride salts. Typically, they are soluble in their respective organic acid, and serve as surfactants to promote solder wetting. 5. Analytical Tools It would be valuable to know the thermal behavior of various flux constituents, particularly those of organic acids. Utilization of techniques such as differential scanning calorimetry (DSC), thermal gravimetrical analysis (TGA), and TGA coupled with Fourier transform infrared spectroscopy (TG/FTIR) or mass spectrometry (TG/MS) provides the opportunity to study flux reactions, and the properties of organic salts during solder reflow operations [118]. It has been shown that evaporation rates and reaction products are different in air than in nitrogen. A brief description of these techniques is given in Ref. 119. Utilizing these and other techniques, it will be possible to apply more scientific approaches to optimizing fluxes and reflow thermal profiles.
H.
Organic (Rosin-Based Fluxes)
1. Description Rosin is a natural resin mixture referred to as colophony [
Gum rosin—This is the residue left after the distillation of turpentine oil from the oleoresin (Latin oleum, oil) from living trees.
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SINGLER ET AL. Wood rosin—This material is obtained by extracting pine stumps with naphtha and distilling off the volatile fraction. Tall oil rosin—This is a byproduct of the fractionation of tall oil (Swedish: tallolja; tall, pine+olja, oil), which in turn is a byproduct of paper manufacturing. It consists of about 50% resin acids and 50% unsaturated fatty acids, mainly oleic and linoleic acids.
a. Rosin Grades. There are several grades of rosin, of the lowest to the highest quality, based on color and are designated as: B, D, E, F, G, H, I, K, L, M, N, W-G, W-W, and X [106,122]. The criteria for rosin quality and acceptability depend upon the application. It is interesting to note that the quantities used for flux applications are so small compared with other industrial applications that they are scarcely mentioned in many rosin information sources. For electronics applications, the key indicators of resin quality are color, softening point, and acid number. Those with the lightest color, highest softening point, and highest acid number are of the highest quality. The grade selected for electronic soldering is a ‘‘gum’’ rosin, lightest in color of all the designations and is called water white (W-W) rosin, which consists of 80–90% abietic acid [105]. The reason this particular rosin is selected as a flux for electronic soldering applications is because of its cleanliness and effectiveness. 2. Unique Properties and Characteristics Much of the history of electronic soldering is based on various rosin fluxes due to their effectiveness in creating good solder joints with termination pad metallizations (e.g., Au, Cu, and Ni), and the benign nature of rosin with respect to corrosion. Rosin is a noncrystalline (glass) solid at room temperature, with a usual softening point in the range of 70–80jC, with the higher end representing better quality. A higher softening point is an indication of higher purity. It does not have a melting point, but starts to become liquid at about 150jC, and is fully molten at eutectic Sn–Pb soldering temperatures. Because rosin is a solid at room temperature, it is usually necessary to dissolve it in a solvent such as benzyl or isopropyl alcohol. a. Excellent Tackiness. Several features of rosin fluxes are worth noting, especially because some of these attributes typically are useful in nonrosin flux compositions as well. They are soluble in a wide range of alcohols and can be diluted for easy application by spray, brush, or syringe. Rosin fluxes exhibit excellent tackiness if not diluted excessively. These fluxes are very efficient in holding chips, solder balls, and components in place during reflow. Even with high dilution and solvent evaporation, these rosin-based fluxes are sufficiently tacky to hold chips and small components in place. Complete solvent evaporation leaves a nontacky protective coating on ready-to-solder surfaces. b. Aids in Self-Alignment. Rosin appears to facilitate the self-alignment of chips, solder balls, and small solder ball-based components with respect to copper termination pads and pins so that exact placement is not critical. A study was conducted by Spalik to define the role of resin in providing self-alignment of components with their mating I/O pads. To observe the effect of flux in correcting the problem, 10/90 Sn–Pb solder balls were purposely misplaced on nonsolderable surfaces (ceramic and polyimide) up to 5 mm away from their intended location adjacent to a Cu pin head I/O connection surrounded by a land pattern on a pinned chip carrier. In practice, the solder wets the pin head and land pattern, providing both good electrical and mechanical connections between them. Because this reflow operation is normally carried out under a nitrogen atmosphere at temperatures greater than 330jC, and it is desirable to make observations in real time, the substrate and solder balls were reflowed under N2 in a microhot stage oven, with a viewing port (Fig. 29). The experimental setup was capable of replicating manufacturing reflow temperature profiles. The solder balls were observed to move toward the intended Cu pin if a flux trail extended between the ball and the pin. Fig. 30a and b presents sequential time lapse photographs, taken as a solder ball was observed to approach a pin and as wetting began. This property may be unique to fluxes with a high concentration of abietic acid
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FIG. 29 An example of a microreflow furnace for observing and monitoring real-time reflows.
because similar results could not be achieved with glycerine and other fluxlike materials that were investigated. It may also coincide with abietic acid’s ability to transport tin through flux without solder wetting, as described Sect. 6.8.2.3. c. Transports Tin. Rosin also has the ability to transport tin (Sn) through a rosin flux over copper surfaces beyond the extent of the solder spread. In other words, rosin can transport Sn from a Sn–Pb or other Sn-based solder surface to a relatively distant copper surface without an intervening layer of solder. The Sn forms a Cu–Sn intermetallic, and no Pb or other species are transported. This phenomenon, described as a halo by some investigators, appears as a grayish cast on the Cu surface, preceding and extending beyond the solder spreading front. Three mechanisms have been proposed: electrochemical deposition, condensation, and surface diffusion. These halos have been reportedly made with very active ammonium chloride–zinc chloride fluxes, but also slowly with urea and pure dimethylammonium chloride [123].
FIG. 30 Sequence of time-lapse photographs: (a) taken prior to reflow, where the solder balls were purposely misplaced; (b) after reflow, illustrating how solder balls follow a flux path to Cu pins.
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d. Phenomenon Verified. A study was conducted by Spalik using the apparatus depicted in Fig. 31 to verify that tin (Sn) can be transported through rosin flux, over a copper surface, without the assistance of any solder spreading. Tin–lead (90/10) solder and flux were heated in the test tube-like apparatus to evaporate the solvent so only the rosin remained and then heated to 350jC in a purged nitrogen atmosphere. A cleaned Cu wire was introduced through the top vent with the end dipped slightly into the molten solder. The dip time intervals ranged from 10 sec to 4 hr. Fig. 32a–d depicts a solder on the tip of the wire, and the appearance of the halolike substance on the Cu wire that was immersed with the rosin above the molten solder. The left side of the wire shown in Fig. 32a is bright and shiny, where it was wetted by the Sn–Pb solder. However, the wire has a dark appearance on the right side, where it was in contact with only the rosin. A SEM backscatter image of the same areas of the wire depicted in Fig. 32a is given in Fig. 32b. A SEM image (Fig. 32c) of the portion of the wire immersed in the rosin (i.e., dark-appearing area of the wire in Fig. 32a) is not characteristic of the structure of copper wire. It was determined via energydispersive spectroscopy (EDS) analysis (Fig. 32d) that the material on the surface of the wire in contact with the rosin consisted of Sn and Cu, but not Pb. Sn could only have arrived at that location on the wire due to the rosin having participated in its transport. e. Reducing Activity Due to Isomerization. Rosin flux increases in activity up to temperatures around 285jC but loses its effectiveness (i.e., reduces in activity) when exposed to elevated temperatures over time. In addition to the loss in activity, the tin transport phenomenon described in Sec. VI.H.2.d does not occur with rosin exposed to elevated temperatures for extended periods. Both are believed to be due to changes that abietic acid undergoes. Rosin used for soldering has been reported to consist of 70–85% abietic acid and 10–15% pimeric acid [124]. Another source reports an abietic acid concentration of 80–90% [125]. Abietic acid undergoes
FIG. 31 Apparatus utilized to demonstrate that Sn is transported through flux and that Sn is oxidized by Pb ions.
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FIG. 32 Series of images that relate to a substance with a halolike appearance on a copper wire. (a) Optical image of Cu wire showing the left, bright-appearing end that was immersed in solder and the right, dark-appearing end with transported Sn. (b) SEM backscatter image of Cu wire showing the same area as in (a). (c) High-magnification image of a section of Cu wire that was only immersed in rosin. (d) Energy-dispersive spectroscopy analysis spectrum from the section of Cu wire shown in (c), showing only the presence of Sn and Cu but not the Sn transported in the region in contact with the resin.
changes due to isomerization at 300jC (Fig. 33). In the case of abietic acid, the rearrangement of double bonds from an alternating double–single–double bond, referred to as a conjugated double-bond structure, in adjacent rings results in a more dispersed structure as noted in the various compounds due to the rearrangement that takes place (Fig. 33). The redistribution due to thermal isomerization results in an equilibrium concentration of only 10–20% abietic acid. f. Disproportion of Abietic Acid. Rosin also undergoes disproportionation [127,128], a proess in which a radical transfers a hydrogen atom to another radical. It occurs more readily on catalytic surfaces, which results in some molecules of abietic acid being dehydrogenated, and other molecules being hydrogenated to give dehydroabietic, dihydroabietic, and tetrahydroabietic acids as depicted in Fig. 34. g. Other Considerations. The conjugated double-bond structure of abietic acid may assist in transporting Sn more readily through coordination—the sharing of electronegative electron pairs on carbon atoms with electropositive Sn ions—because of the higher electron density and mobility of electrons in the conjugated bond region. It is important to note that this type of rearrangement can take place even in synthetic fluxes containing molecules of similar structures, during heating. Therefore, it is possible that they also can exhibit variability in composition and performance depending on their thermal history.
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FIG. 33 Isomerization of abietic acid due to heating.
3. Relationship Between Thermal Stability and Activity Rosin oxidizes in air and darkens when heated to soldering temperatures, but can withstand degradation at temperatures up to 400jC, for several hours, without significant discoloration or charring in very low oxygen (<10 ppm) atmospheres (N2). It appears to evaporate quite rapidly when its surface-to-volume ratio is large, and more rapidly in air than in nitrogen. The difference in evaporation rates is likely due to bonds breaking under the influence of oxygen. During the Spalik study of Sn transport by rosin, the rosin was observed to change in color from light amber to a very pale, transparent yellow as a liquid and became a light yellow solid upon cooling. It could be remelted and held between 350jC and 400jC for several hours without a visible change if a N2 flow was maintained, but charred and blackened quickly if the N2 flow was
FIG. 34 Disproportionation of abietic acid on a catalytic surface.
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interrupted. The evaporation rate during this study was low. However, as discussed in Sec. 6.8.2, isomerization and disproportionation (Figs. 33 and 34) occur as the temperature approaches 300jC, which decreases the activity of the flux. Activity increases with temperature until disproportionation of abietic acid becomes significant. Therefore, it is generally preferred that the temperature profile consist of a steep ramp in the range of solder melting, especially for alloys that melt near or above 300jC. Typically, the ramp of a reflow temperature profile increases slowly to allow solvents to evolve, has a ‘‘soak’’ plateau between the solvent boiling point and solder melting temperature, and has a rapid ramp to the solder melting temperature. Fluxes based on only rosin dissolved in alcohols typically exhibit high surface insulation resistivity (SIR), so flux residues are often left without concern for corrosion and electrical leakage. But disproportionated rosins left after reflow display even higher surface insulation resistivities than normal rosins [129]. This property is advantageous when cleaning is difficult. However, it is important to note that residues resulting from high levels of tarnish, oxidation, and charring accelerated by atmospherical oxygen may have significantly lower SIR values. 4. Acid Number Rosins are organic acids and their fluxing effectiveness depends on their acid number; a high acid number (and saponification number) is an indication of good fluxing action. A higher acid number indicates a greater ratio of acidity to inert material in the rosin. Because it is the acid functionality that provides the flux activity with respect to solder metal oxides, it is very important that the acid concentration in the flux is sufficient to react with all the oxides present. The best rosins to be used as a flux material for soldering usually have an acid number in the range of 160–170. The acid number is the number of milligrams of potassium hydroxide (KOH) required to neutralize 1 g of rosin. Table 14 lists the acid numbers of several types of rosin compared with pure abietic acid [122,130]. Theoretical acid numbers for organic acids can be easily calculated by dividing the formula weight of KOH (56.11) by the formula weight of the acid and multiplying by 1000. Using abietic acid (302.44) as an example gives 56.11/302.441000=185.52. This might appear to be a theoretical limit for rosin, but a rather rare resin acid derived from P. merckussi (Vietnam) can be 190 or more. For the acid number to be higher than 185, the rosin must be comprised of acids with low formula weights. The detailed resin acid composition of rosin is usually of little consequence or interest to the end user, only that the acid number is sufficiently high. It is, therefore, not surprising that rosins are classified by their acid numbers. 5. Rosin-Based Classification System A flux classification system for rosin fluxes that has been in use for many years defines the use of additives to a rosin base to increase the flux activity. Some applications require stronger fluxing action than is provided by rosin alone. Therefore, compositions with an increased activity have been formulated. The system consists of the designations R, RA, and RMA for rosin, activated
TABLE 14 Materials
Acid Numbers of Several Rosin
Rosin Abietic acid Gum rosin Wood rosin Hydrogenated rosin Dehydrogenated rosin Polymerized rosin Dimerized rosin
Acid number 185 168 163 160 154 144 140
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rosin, and mildly activated rosin, respectively. Table 15 provides guidelines for comparing the equivalency of these fluxes to ANSI designations [110,131].
I.
Halogen-Free Organic Fluxes
As was noted with rosin-based fluxes, the activators added typically contain halides such as chlorides and bromides, which are fairly corrosive. There are, however, several categories of milder, halide-free activators such as organic acids and amine compounds. Because these fluxes are less aggressive, they are slower-acting and do not have the ability to remove thicker tarnish layers. For these fluxes to be effective, it is necessary to provide pristine solderable surfaces. 1. Carboxylic Acid Fluxes A carboxylic acid always contains the carboxyl (–COOH) functional group and is the primary active ingredient in OR classification. There can be one or several carboxyl groups on a single molecule, and are designated as monocarboxylic, dicarboxylic, tricarboxylic acids, etc. Many fluxes are composed of simple monocarboxlyic and dicarboxylic acids, as depicted in Fig. 35a and b. The stick figure illustrations indicate that both oxygen atoms are attached to their adjacent carbon atom and that the ionizable hydrogen is attached to an oxygen atom. Resonance or electron sharing (also referred to as delocalization) between the carbon atom and the two oxygen atoms is the reason that the hydrogen is able to be more easily ionized. Although depicted as being attached to one oxygen atom, the hydrogen atom (ion) is really shared by both. These diagrams illustrate the similarity in structure of some organic acids commonly used in fluxes. This class of fluxes typically undergoes what is described as simple acid–base reactions with metal oxides, although chelation, coordinate covalent bonding, (i.e., formation of complexes), and electrochemical interactions (i.e., oxidation and reduction) may also be involved [102,104]. These types of reactions will be explained later. However, there can be subtle yet significant differences in performance related to molecular structure, carbon chain length, melting point, and boiling point. a. Melting and Boiling Points. A flux can consist of a single carboxylic acid or a combination of these acids that exhibit melting and boiling points consistent with the reflow temperature of a particular solder alloy. It is necessary that the acid and/or its respective salt be present in a liquid state during reflow. That is, the molten acid, salt, or both should coat the solderable interfaces through the reflow process in order to achieve good fluxing. For example, if the acid remained solid, the reaction rate would be too slow, and if it evaporated too quickly (before reflow), it could not participate in the reaction. The melting and boiling point trends of the first members of the monocarboxylic and dicarboxylic acid series are illustrated in Figs. 36 and 37. From the graphs, it can be seen that most of the monocarboxylic acids are liquids at room temperature, but all the dicarboxylic acids are solids. Also, the boiling points of most monocarboxylic acids are below reflow temperatures of solders utilized in electronic assemblies but are above solder reflow temperatures for dicarboxylic
TABLE 15 ANSI Flux Designations and their Equivalent R Classification Designations ANSI flux designations L0 L1 M0 M1 H0 H1
Equivalent R classification fluxes All R, some RMA, some low solids no-clean Mostly RMA, some RA Some RA, some low solids no-clean Mostly RA None Mostly water-soluble and synthetic-activated
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FIG. 35 Structural formulas of straight-chain (a) monocarboxylic acid and (b) dicarboxylic acid.
FIG. 36 Plot illustrating the monotonic increase of the boiling points of monocarboxylic acids with increasing carbon atoms in the chain. Their boiling points do not exhibit a trend.
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FIG. 37 Plot that indicates the increase in boiling points, and oscillating trend of melting points with the number of carbon atoms in the chain of dicarboxylic acids.
acids. It is important to remember that for an acid to be active in the role of a flux, it must be molten or in solution. 1. Monocarboxylic acids—It should be noted that the temperature range between melting and boiling is important because a greater range provides more time for fluxing during a reflow operation. For monocarboxylic acid series, there is an initial downward trend in the melting point due to hydrogen bonding, followed by an increase as a result of longer carbon chain lengths. Corresponding with the trend in melting points, there is a monotonic increase in boiling points with carbon chain length. Also, even with the slight oscillation in melting points, the melting point range is noted to generally broaden with increasing numbers of carbon atoms. This suggests that for monocarboxylic acids, a higher-molecular-weight acid is better suited for eutectic solders. 2. Dicarboxylic acids—The boiling points of dicarboxylic acids fall within a relatively narrow range, and it appears that they are all nearly equivalent. Note that the melting points of dicarboxylic acids not only decrease, but oscillate downward—those with oddnumbered carbon chains melting at much lower temperatures compared to adjacent even-numbered carbon acids. These large excursions are not expected based on molecular weight or carbon chain length alone. It is beyond the scope of this text to delve into all of the factors affecting melting points, but it is important to be cognizant of these characteristics because a flux’s activity is initiated when the acid melts. Thus, those dicarboxylic acids with lower melting points allow more time for flux action before the solder melts. Also, evaporation due to sublimation increases with temperature during a typical reflow profile. The vapor pressure [132] and, consequently, evaporation rate vs. temperature are quite similar for several dicarboxylic acids (Fig. 38). For example, adipic, pimelic, and suberic acids will evaporate at approximately the same time during a typical furnace reflow profile, but because pimelic acid melts earlier, it provides more time for fluxing before it is vaporized. 3. Early evaporation concern—Boiling points for the first three dicarboxylic acids are not depicted in Fig. 37 because oxalic acid sublimes at 157jC, malonic acid decomposes at mp 130–35jC, and succinic acid decomposes at 235jC. Sublimation is defined as the process of evaporation directly from the solid state. It is important to be aware of the fact that evaporation of liquids occurs below their boiling points, and that the rate of evaporation increases with temperature. It is possible for a flux to evaporate completely before its boiling point, and for that matter before the solder reflow temperature is attained, in which case the flux will be ineffective. This is illustrated by the TGA plots of Fig. 39a and b that show pimelic acid (bp 342jC) and palmitic acid (bp 351jC)
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FIG. 38 Vapor pressure plots of dicarboxylic acids illustrating that they have very similar evaporation rates.
commencing rapid evaporation at about 200jC and are completely evaporated before 300jC. In no-clean fluxing operations with flip chips it is important to apply sufficient flux to assure its presence and effectiveness during reflow, but not so much that an excess remains postsoldering. Boiling points indicated for the rest of the acids are the temperatures at which their vapor pressures reach 760 Torr, in accordance with the definition of boiling point. However, they evaporate quite rapidly before reaching their respective boiling points and are sometimes described as subliming even though they are in the liquid state. This can be advantageous for no-clean fluxes used for flip-chip attachment because excess flux components evaporate, leaving very little residue. b. Relationship Between Properties and Parameters. Several properties are discussed when trying to correlate the effectiveness of a flux component to solderability. Among these are the activation energy (Ea), as described below; the acidity constant (Ka), described in Sec. 6.11.1; and wetting rates. Wetting rates are determined by measuring the increase in force vs. time using a specially designed analytical balance of solders wicking up on a specified solderable coupon. This procedure is described in detail in this chapter. It would be useful if these and other properties could be related in such a way that flux design and solderability could be predicted on the basis of scientific principles, but, unfortunately, attempts to correlate flux effectiveness with chemical structure, ionization constants, activation energy, and wetting rates have been generally unsuccessful. Kinetics—The activation energy for a reaction is the energy that must be supplied to reacting molecules before they can attain the transition state. For a chemical reaction to take place, it is often necessary for the reacting species to pass through a higher energy state than they are in originally before any product can be formed. This is known as the transition state or activated complex. The products formed will have a lower energy than the maximum energy required to initiate the reaction. Reaction rates are related to activation energy and temperature by the equation:
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FIG. 39 Thermal gravimetric analysis plots illustrating that volatilization begins before 200jC and complete loss begins before 300jC.
Ea
Rate ¼ Ae RT
ð49Þ
where A is a constant which assumes that other variables and concentration are fixed, e is the base of the natural log 2.718. . ., R is the gas constant (8.31 J/mol K), and T is the absolute temperature. Higher activation energies represent greater energy barriers [i.e., the energy that must be added (DHact) to raise the energy of the reacting species to the increased energy level to achieve the transition state] (Fig. 40a and b). Note that according to the equation, the rate increases with temperature and that the reaction rate with respect to temperature is greater for lower activation energies. Therefore, low activation energies predict high wetting rates and more complete reflow within a process time window. Catalysts are substances that can facilitate the formation of a transition state having a lower activation energy than one formed in the absence of a catalyst. It is possible that the metal surfaces, solder alloys, and other flux components provide a catalytic effect. For example, a high activation energy barrier is observed to exist when reflowing solders in a H2 atmosphere. Temperatures over 400jC are required to
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FIG. 40 Potential energy plots illustrating the energy change during the progress of (a) an exothermic reaction, and (b) an endothermic reaction.
overcome the activation energy barrier [157]. Reflowing in the presence of hydrogen with Quadrol has been shown to significantly reduce the required reflow temperature, but it has not been verified whether or not this is a reduction in the hydrogen activation energy or simply a fluxing effect imparted by the Quadrol. However, platinum (Pt) and palladium (Pd) are well-known catalysts that significantly reduce the energy barrier. Hydrogen reflow occurs more easily when these elements are near or in contact with the solder to be reflowed. Electrodeposition and vapor deposition of a seed layer under or over solder bumps reduces the temperature at which H2 reflow can
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SINGLER ET AL. be achieved. Some promising high-vacuum results are believed to have resulted from using Pt on flip chips under bump metallization [66,67]. Lack of parametrical relationships—Table 16 illustrates an attempt to establish a parametrical relationship or trend upon which to predict wettability based on the carbon chain length and other parameters of dicarboxylic acids [133]. The dependence of wettability was measured on copper substrates with Sn–Pb eutectic solder. The correlation of the effectiveness of the flux with activation energy, acid ionization constants, or chemical structure has not been successful. Note in particular that although adipic, pimelic, and suberic acids appear to follow a trend in wetting rates and activation energies, this trend does not hold for the other acids listed. Also, although the acid ionization constants are very similar for all of the acids above n=2, there are substantial differences in wetting rates. Oxalic acid with a pKa of 1.23 and a wetting rate of 1988 dyn/cm/sec is not very different from suberic acid with a pKa of 4.52 and a wetting rate of 1892 dyn/cm/sec. Noteworthy is the fact that adipic acid has the lowest wetting rate and highest activation energy but is used in many fluxes because it performs well in practice. In addition, pimelic acid, which does not have significantly different parameters compared to the other acids listed in Table 15, is the active species in a flux that has provided satisfactory results for the assembly of flip chips to their carriers for many years [134]. Although it is useful to observe fundamentals and attempt to correlate them with soldering effectiveness, such empirical studies are generally unsuccessful at predicting soldering effectiveness when other parameters are changed a priori. This example, which attempts to correlate a series of measurements with chemical structure and other parameters, illustrates the fact that it is very difficult to predict a best candidate for a flux in a particular application, and underscores the need to investigate a variety of formulations using screen tests, but to test the final candidates under actual manufacturing reflow conditions.
2. Amines Amines are organic bases having the general formula R-NH2, R2NH, and R3N referred to as primary, secondary, and tertiary amines, respectively. Lower-molecular-weight primary amines, although water-soluble, have boiling points too low to be useful for soldering. Because hydrogen bonding is mainly responsible for raising boiling points and water solubility, it should be expected that secondary and tertiary amines would be even less soluble because they have less hydrogen. Boiling points and solubility are also affected by the hydrocarbon part of the molecule (e.g., TABLE 16 Acid
Key Parameters of Several Dicarboxylic Acids Structure (n)
(Dibasic) HOOC(CH2)nCOOH Oxalic 0 Malonic 1 Succinic 2 Glutaric 3 Adipic 4 Pimelic 5 Suberic 6 Azelaic 7 Sebacic 8 Fumaric HOOCCHjCHCOOH (Monobasic) CH3(CH2)nCOOH Myristic 12 Palmitic 14 Searic 16
Activation energy, Ea (kJ/mol)
Wetting rate (dyn/sec at 233jC)
13.22 11.19 14.15 16.20 42.84 32.60 12.72 18.54 40.07 12.29
1988 1891 1178 1274 456 930 1892 930 888 1069
46.89 34.23 43.06
340 540 340
pKa1
pKa2
1.23 2.83 4.19 4.35 4.43 4.48 4.52 4.53
4.19 5.69 5.48 5.42 5.42 5.42 5.40 5.40
3.02
4.38
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longer carbon chains increase boiling points and decrease water solubility). Above six carbon atoms, amines have borderline water solubility and become difficult to remove. Compounds that have more than one amine group are called diamines, triamines, and tetraamines. Some examples are ethylenediamine (NH2CH2CH2NH2) and ethylenetriamine (NH2)2CH2CH2NH2. Generally speaking, increasing the number of hydrogen atoms attached to nitrogen atoms infers increased water solubility, and increasing the number of carbon atoms infers decreased solubility. a. Use of Amine Derivatives. Ordinary amines are not employed in fluxes, but their salts and derivatives are. The salts are crystalline materials that decompose before or upon melting and leave a basic low-water-soluble amine residue. Although amines do not contain halides, they are still corrosive and must be removed because they are able to react to form carbonates, chlorides, and sulfides. Due to this characteristic, they increase the potential for failure due to reduced surface insulation resistance (SIR), and difficult-to-remove carbonate and sulfide residues. b. Effect of Sulfides. With respect to sulfides, it is worth mentioning that liquid propane (LP) and natural gas used for heating contain odorants, mercaptans, and organic sulfides that are released in sufficient quantity to tarnish metal surfaces quite rapidly. This is the reason why silverware darkens quickly in homes that use gas for cooking. It is important to be aware of this fact when storing components. Materials such as urea, ethylenediamine, monoethanolamine, and triethanolamine, and derivatives such as aniline phosphate are extensively utilized as activators in fluxes. These materials are also temperature-sensitive and, as noted above, have the potential to leave difficultto-remove residues [102,135]. Structural and empirical formulas of several amine and derivative amine compounds, emphasizing functional features, are given in Fig. 41. c. Charging with HCl. Amines are bases that can be charged with hydrogen chloride (HCl) gas according to the reaction: R NH2 þ HCl ! R NH2 .HCl
ð50Þ
to form amine hydrochlorides. Each molecule of an amine can retain one molecule of HCl. Amine hydrochlorides release HCl when heated, which in turn reacts with the metal oxide. Amine constituents of a flux can be fully or partially charged with HCl to achieve a desired level of
FIG. 41 amines.
Structural representations of amines, amine hydrochlorides, amine carbonates, and alcohol
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activity. Although such species highly activate the flux, they must be removed quickly postsoldering because they have the potential for corrosion. It has been demonstrated that the Cl ion can reduce Cr–Cu line adhesion rapidly at elevated temperature and humidity [136]. Amines can also form coordination complexes with metals, thus increasing solubility [102,103]. 3. Amino Acids Amino acids contain both the –NH2 (amine) and the –COOH (carboxyl) groups. They are classified as acidic, neutral, or basic depending on which functional group is predominant, as indicated in Fig. 42. In contrast to amines and carboxylic acids, they are crystalline, nonvolatile solids that melt upon decomposition at fairly high temperatures. The acidity constants of neutral amino acids are extremely low compared with organic compounds of similar structure having only carboxylic acid functionality. Their properties are consistent with dipolar saltlike ion structures depicted below: 2 3 3 2 3 R R R ½OH ½Hþ 5 4 5f4 5f4 j j j H2 O H2 O H3 Nþ-CH-COO H3 Nþ-CH-COOH H2 N-CH-OO 2
Basic Salt form ðNaþ þ OH Þ
Neutral Salt form
Acid Salt form ðHþ þ Cl Þ ð51Þ
FIG. 42 Structural representations of neutral, acidic, and basic amino acids.
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That is, they are ionic and water-soluble, and can form basic, neutral, or acidic salts. Typically, they are weaker than acids [137], having only the carboxyl group functionality, but can form coordination complexes with metals by the sharing of lone pairs of electrons on nitrogen and oxygen atoms with metal ions. This can help to solubilize metal ions in the flux and help in their removal in postsolder cleaning [102]. 4. Alcohol Amines Alcohol amines contain the –OH (hydroxyl) group in addition to the amine group as depicted by the formulas in Fig. 41. These compounds are bases that rapidly form salts with acids, and have good solubility in both aqueous and organic systems. Therefore, they serve to help solubilize and emulsify flux components and reaction products [102]. An important feature of alcohol amines is their ability to help solubilize residues and form complexes. a. Inductive Effect and Its Role in Acidity. In symmetrical organic molecules such as ethane, a nonpolar, covalent bond exists between atoms of equal electronegativity. But it is also not unusual for covalent bonds to exist between elements of compounds such as methyl chloride, where there is a difference in electronegativity. So in the methyl chloride case, the bonding electrons are closer to chloride than to carbon because the chlorine has a higher electronegativity. In cases where there is a shift in the bonding electrons, the bonds exhibit a slightly polar character. The chlorine end of a methyl chloride molecule has a small negative charge, whereas the carbon has a small positive charge. 5. Increasing Acidity (Activity) The strength of acids and bases is affected by molecular structure, steric effects, resonance, inductive effects, hydrogen bonding, and solvation. a. Inductive Effect and Its Role in Acidity. The inductive effect is illustrated by the fact that acidity is increased by a substituent that withdraws electron density away from the carboxyl group, and is decreased by a substituent that releases electrons to the carboxyl group. A more electronegative atom adjacent to a carbon atom attached to the carboxyl group increases acidity. The effect of halogens on acidity can be observed in Table 17 by noting the trend in pKa values with the electronegativities and number of electronegative substituents attached to the carbon adjacent to the carboxyl group. Acidity and pKa notation are discussed in Sec. 6.11.1, but suffice it to note here that the pKa notation is a logarithmical representation of the degree of ionization of the H+ ion at equilibrium with an integer change indicating a 10-fold reduction in acidity (e.g., an acid with a pKa=1 is 10,000 times stronger than one with a pKa=5). Note the trend with respect to electronegativity (F>Cl>Br) for the monohalide acids (e.g., fluoroacetic is the strongest). The addition of electronegative atoms increases the inductive effect (i.e., induces or causes an increased withdrawal of electron density from the carboxyl group). The size of electronegative substituents is also a contributing inductive factor that results in tribromoacetic acid being the
TABLE 17
Effect of Halogens on Acidity
Acid Fluoroacetic Chloroacetic Bromoacetic Difluoroacetic Dichloroacetic Dibroboacetic Trifluoroacetic Trichloroacetic Tribromoacetic
Formula
pK1
FCH2COOH CICH2COOH BrCH2COOH F2CHCOOH Cl2CHCOOH Br2CHCOOH F3CCOOH Cl3CCOOH BR3CCOOH
2.59 2.87 2.90 1.33 1.26 1.39 0.50 0.52 -0.15
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strongest acid (pKa=0.15), as listed in Table 17. It is preferable to state that increased acidity is due to the stabilization of the conjugate base (i.e., the negative ion) of the acid. b. Effect of Number and Spacing of Carboxyl Groups. Acidity also increases with the number of carboxyl groups; thus, a tricarboxylic acid is stronger than a dicarboxylic acid, and a dicarboxylic acid is stronger than a monocarboxylic acid, etc., as long as the groups are in close proximity to each other. If the carboxyl groups are widely separated, the inductive effect will be mitigated, and the acid strength of the first ionization step will be similar to that of a monocarboxylic acid. c. Effect of Successive Ionization. The notation pKa1, pKa2, pKa3, etc., represents successive ionization constants [i.e., they represent successive stepwise ionization (i.e., H+ ion release) of the carboxyl groups]. It should be noted that successive stages of ionization, as each H+ ion is removed, correspond with an increase in negative charge on the conjugate base. An increase in negative charge further destabilizes the conjugate base, and makes it more difficult to remove successive H+ ions, thus resulting in successively weaker acids. In other words, each successive H+ ion-releasing species becomes a weaker acid. d. Effect of Oxygen. Oxygen atoms increase acidity by the inductive effect and double bonds increase acidity by resonance stabilization. These effects are illustrated by the pKa values listed under the structural formulas of Fig. 43. Compare, for example, propionic acid (pKa=4.874) with similar monocarboxylic acids and note that the influence of an additional oxygen atom attached to the carbon next to the carboxyl group causes a 10-fold increase in acidity for 2-hydroxypropionic (pKa=3.858) and methoxy acetic (pKa=3.570) acids. Resonance and the inductive effect combine in 2-oxopropionic (pKa=2.49) to increase the acidity by another order of magnitude. e. Effect of Solvents and Surfactants. Hydrogen bonding and solvation are additional factors affecting acidity and are important in the selection of solvents and surfactants. Changing the solvent system or surfactant can significantly change flux effectiveness. Typically, the solvent or surfactant in a flux formation is an alcohol, glycol, polyol, etc., having one or more (–OH) groups. In addition, there may be (–CH2–O–CH2– or R-O–CH2CH2–) type functional groups
FIG. 43 Structural formulas illustrating the effect of substituent groups on the acidity (pKa) of carboxylic acids.
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(e.g., Tween, Brij, Igepal) as depicted in Fig. 44. It is beyond the scope of this work to detail the function and importance of solvents, but their importance should not be underestimated. Care must be exercised not to render a flux ineffective due to excessive dilution. Some flux compositions have a small amount of water added to increase effectiveness. It is important to select the right combination of organic acid, solvent, and surfactant for optimum performance. These combinations are very difficult to reverse engineer (i.e., chemically analyze), part of the reason so many proprietary formulations continue to exist. Another factor contributing to flux activity is the ability of some species to form stable coordination complexes with heavy metal ions [103]. Compounds containing nitrogen, classified as amines, ethylenediaminetetraacetic acid (EDTA), and N,N,NVNV-tetrakis(2-hydroxypropyl)ethylenediamine (Quadrol) (Fig. 45), and triethanolamine are able to form multiple bonds with a metal ion (central atom) as depicted in Fig. 46. The species forming the bonds are called ligands, the arrangement around the central atom is the coordination sphere, the number of bonds formed is the coordination number, and the species contributing the pair of electrons are the ligands. Any species having a pair of nonbonded electrons (e.g., nitrogen and oxygen) can be a possible ligand in solution, but to be effective in fluxing, it must be stable at reflow temperatures. Species having nitrogen and oxygen atoms connected by an ethylene (–CH2CH2–) linkage have the preferred structure to enclose the central atom, and to satisfy the coordination number. Synthetic fluxes discussed in Sec. 6.10 are examples that illustrate the application of these concepts.
J.
Synthetic Fluxes
The concept of synthetic fluxes derives from the desire to control the composition of natural fluxes. It is generally conceded that good process control requires that the composition of materials entering a process be consistent. Additionally, synthetic mixtures can be modified to provide chemical and physical properties that meet the needs of specific fluxing requirements. For example, Figs. 47 and 48 illustrate two commercial flux systems formulated for high-temperature stability, sufficient tackiness, and amenability to aqueous cleaning. Note how the formula structures and combination of ingredients reflect the principles discussed in Sec. VI.I.5. That is,
FIG. 44 Structural representations of alcohols. The OH functionality is important in water solubility and surfactant properties.
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FIG. 45 Examples of two important nitrogen-containing molecules that illustrate the electronegativity effect.
FIG. 46 Examples of coordination complex formation by nitrogen-containing molecules.
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FIG. 47 Some components of a commercial, nonvolatile, water-soluble flux.
polycarboxylic amino acids provide good fluxing activity and the possibility of forming stable complexes with metal ions, whereas the polyalcohols provide tackiness, viscosity control, temperature stability, and water solubility for postsolder cleaning.
K.
Chemical Reactions Involving Flux
The most frequently suggested role of a flux in soldering is oxide removal. Except for a few circumstances, that typically is not what occurs. Terminology such as ‘‘the purpose of flux is to dissolve the tarnish’’ or ‘‘remove the oxide,’’ frequently used to describe the role of flux, should be understood to mean a chemical reaction that converts the metal oxide to a species that promotes solder wetting. Flux reacts with oxides, making them more easily displaced by the liquid solder. It is thought that the salt formed remains at the solder surface and acts as a pseudo-surfactant that actually facilitates a reaction at the metal interfaces. Chemical reactions that take place during soldering may be very complex. Usually the reactions can be described as acid–base neutralizations, but also can involve electrochemical reduction and the formation of coordination
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FIG. 48 Some components of a commercial, nonvolatile, water-soluble, tacky flux.
complexes. Also, it should be remembered that metallic tin is very important as a reducing agent, and is known to reduce Pb [138] and Cu oxides. A brief review of relevant chemical principles follows. 1. Acid–Base Reactions, pH and pK Theories on the nature of acids and bases are presented in most general chemistry texts [139]. The Arrhenius theory proposes that an acid is a material that releases protons (H+), and a base is a material that provides hydroxyl (OH) ions in solution. It follows that the combination of these ions produces water: Hþ þ OH ! H2 O
ð52Þ
Because H+ is solvated in water, it is usually shown as H3O+, and the equation becomes: H3 Oþ þ OH ! 2H2 O
ð53Þ
For the reaction of a strong acid (completely ionized) (e.g., HCl) with a strong base (e.g., NaOH), the equation is: Base Salt Water Acid H3 Oþ þ Cl þ Naþ þ OH ! Naþ þ Cl þ 2H2 O
ð54Þ
Because the Na+ and Cl are unchanged on both sides of the equation, they are considered ‘‘spectator’’ ions and may be left out of the equation, which then becomes identical to the previous equation. a. Bronsted–Lowry Theory. Flux–metal oxide interactions are better described by the Bronsted–Lowry theory, which defines an acid as a proton donor, and a base as a proton acceptor. Utilizing this concept, a metal oxide (MOx) reacts with an acid (HA):
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Metal Acid Metal Water Oxide Salt MOx þ 2xHA ! MA2x þ xH2 O
ð55Þ
yielding a salt and water. b. Dissociation Constant. The ability of a weak acid to dissociate into its conjugate acid and base is characterized by its acid dissociation constant Ka or pKa, where ‘‘p’’ is an operator log10[x] or log10[1/x] (take the negative of the base 10 logarithm of Ka). The dissociation constant is a measure of the strength of an acid (i.e., its ability to ionize in solution). It is determined by taking the product of the activities of the right-hand species, dividing them by the activities of the left-hand species. Consider the case of water that dissociates into its component species: H2 OWH3 Oþ þ OH ðUse of Gibbs free energy of formation tables and the carbon small positive charge electronegativity added algebraicallyÞ The chemical activity is described as: H3 Oþ ½OH Ka ¼ ¼ 1 1014 ½H2 O2
ð56Þ
ð57Þ
Because the activity of H2O in its standard state is defined as unity, the equation may be simplified to: ½Hþ ½OH ¼ 1 1014
ð58Þ
Applying the operator ‘‘p’’ to all terms gives: pH þ pOH ¼ 14; or pH ¼ pOH ¼ 7
ð59Þ
Consider now the case of weak acids such as acetic acid (CH3COOH) (i.e., those acids that do not dissociate completely in water compared to HCl that does). For convenience, the formula for acetic acid can be abbreviated as HOAc, in which case the equation for its dissociation in water can be written as: HOAc þ H2 OWH3 Oþ þ OAc and the equilibrium constant expression is: H3 Oþ ½OAc ¼ 1:8 105 Ka ¼ or ½HOAc½H2 O
ð60Þ
pKa ¼ 4:7
ð61Þ
Extensive tables of dissociation constants for inorganic and organic acids, bases, and amino acids are listed in Refs. 140 and 141. 2. Decomposition Reactions When either the initial components of a flux or the products formed from the interaction with surface oxides are heated during reflow, it is possible that they polymerize, revert to the original species, decompose to carbonaceous (charred) residues, or convert to volatile effluents. Table 18 lists several reactions and possible residues left after peak reflow temperatures for some typical chloride salts and a general organic salt. These residues remain in the vicinity of the solder connection. Organic residues are usually innocuous chemically and electrically, but may interfere with adhesion of underfill materials used with flip chips and some chip scale and ball grid array components. Principle exceptions are amine and chloride residues that must be removed. Highermolecular-weight, thermally stable acids such as abietic acid remain as a mixture of both acid and
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TABLE 18 Residues That Can Be Formed by the Reaction of Tin and Copper Oxides with Chloride Salts and an Organic Salt Reaction
Residue
SnO+2HCl=SnCl2+H2O SnO+2NH4Cl=SnCl2+H2O+NH3 SnO+2RNH2HCl=SnCl2+2RNH2+H2O CuO+2HCl=CuCl2+H2O
SnCl2 SnCl2 SnCl2 CuCl2
CuO+HCOOH=Cu+CO2+H2O
Cu
PbO+2HCl=PbCl2+H2O
PbCl2
SnO+RCOOH=Sn(RCOO)2+H2O
Sn(RCOO)2
Properties Stable (mp 247jC, bp 652jC)
Stable chloride at most soldering temperatures CuO reduced to oxide-free metal by formic acid Stable chloride salt at most soldering temperatures Many possible decomposition products depending on the properties of the particular carboxylic acid and its respective carboxylate salt, ambient oxygen levels, and solvent Possible products may volatilize, polymerize, or char Adipic and pimelic carboxylates can form volatile ketones
FIG. 49 Flux reaction with SnO and decomposition with glutaric acid.
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FIG. 50 Flux reaction with SnO and decomposition with pimelic acid.
salt. An interesting example of dibasic acid decomposition that is very desirable for no-clean, flipchip applications is illustrated in Figs. 49 and 50. In this type of decomposition, the carboxylate salt reverts to SnO, and the organic species is evolved harmlessly. Polyfunctional acids can polymerize, leaving nearly impossible-to-remove residues, but they can also be innocuous. There are ongoing efforts to produce fluxes for flip chip applications that polymerize after solder reflow to serve as underfill adhesives as well. A flux that can serve this dual purpose must possess good solder wetting properties, polymerize after reflow is complete, have high electrical resistivity, and be reworkable. 3. Redox Reactions Reactions that involve electron transfer are defined as reduction–oxidation or, simply, redox reactions. Reduction is defined as the gain of electrons by one species, with a corresponding increase in negative charge; and oxidation is the loss of electrons, with a corresponding increase in positive charge. Because it is impossible to have a gain of electrons by one species without a corresponding loss of electrons by another, it is useful to write the equations as pairs of half-cell reactions indicating the direction of electron (e) transfer. Reduction always occurs at the cathode, and oxidation always occurs at the anode of either electrolytic or galvanic cells. Hence, half reactions are sometimes designated as cathodic for reduction, or anodic for oxidation. Extensive tables of half-cell reactions are readily available [142,143] listing standard reduction potentials (SRPs) compared with a standard hydrogen cell. The SRP for a half-cell reaction is the ‘‘voltage’’ produced by an electrochemical cell in which the species of interest [e.g., a Cu electrode in a solution of copper ions (Cu2+) at a concentration of 1 mol/L at 25jC] is compared with a standard hydrogen cell having a Pt electrode in a hydrogen ion H+ concentration of 1 mol/L under a hydrogen H2 pressure of 1 atm. Strictly speaking, the effective concentration (activity) should be unity. The standard hydrogen electrode potential is defined as 0.000 V, and in this example, the measured Cu electrode potential is 0.337 V. In these tables, the half-cell reactions are tabulated as reductions for convenience, so that the most favorably reduced species is at the top and the least favorable is at the bottom. a. Determining Reaction Viability. The species with a higher (more positive) reduction potential is theoretically capable of oxidizing the lower (less positive) species. The tables are
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useful in predicting the spontaneous direction of a reaction, and in determining the corrosive effect of one metal upon another: 1. Use of reduction potential tables—It can be determined which species is reduced or oxidized in a redox couple from standard tables, as exemplified by the brief listing given in Table 19. The cathode and anode half-cell reactions are noted and added algebraically as noted for Pb and Sn. Note that the algebraic sign of the Sn electrode potential is also reversed (i.e., from 0.136 to +0.136): Cathode
Pb2þ þ 2e 5 Pb0
0:126 V
ð62aÞ
Anode
Sn0 ! Sn2þ þ 2e
0:136 V
ð62bÞ
Net ionic reaction
Pb2þ þ Sn0 ! Pb0 þ Sn2þ
0:010 V
ð62cÞ
The sum of the two half-cell reactions gives the net ionic reaction and the overall cell potential with a positive algebraic sign, signifying that Pb2+ (from PbO) is spontaneously reduced to elemental Pb0 by elemental Sn0. It is also possible to determine potentials at other concentrations, or to determine equilibrium concentrations by the use of Nernst equation. This will not be discussed here, but can be reviewed in most undergraduate level college chemistry texts (e.g., Ref. 144). 2. Use of Gibbs free energy of formation tables—The Gibbs free energy is also a measure of the tendency of a reaction to proceed in the direction indicated by the equation. It is directly related to the electrochemical potential by DG0f =no¨o˜, where n is the number of moles of electrons transferred, o¨ is the Faraday constant (96,485 C/mol), and o˜ is the potential of the cell in volts. One volt coulomb is equal to 1 J and the Gibbs energies in Table 19 are given in kilojoules per mole at 25jC. To determine if a reaction is feasible, subtract the sum of the energies of formation of the reactants from the products of a chemical reaction. If the numerical value of the result is less than zero, the reaction will proceed. Consider an example based on the oxides of Sn and Pb, and their free energies of formation from Table 19. Free energies of formation of the elements in their standard states are defined as zero, so the example may be stated as: Sn þ PbO ! Pb þ SnO ð0Þ þ ð188:0Þð0Þ þ ð257:0Þ
ð63Þ
Summing the free energies as directed gives: ð0 257:0Þ ð0 188:0Þ ¼ 69:0 kJ=mol
ð64Þ
indicating that Sn0 can reduce PbO to Pb0. Tin, however, is capable of reducing both
TABLE 19 Table of Reduction Potentials for Contaminants Commonly Encountered in Soldering Electronic Assemblies Half-cell reaction
Standard reduction potential (V)
Ag++e!Ag0 Cu2++2e!Cu0 2H++2e!H02(g) Pb2++2e!Pb0 Sn2++2e!Sn0 In3++3e!In0 Zn2++2e!Zn0
0.779 0.339 0.000 0.126 0.136 0.338 0.763
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copper and lead oxides, whereas hydrogen can reduce copper oxide but not tin oxide. This illustrates the important role that tin plays in soldering copper surfaces. It is useful to be familiar with free energy and standard reduction potential tables [145–147], and how they can be used to predict the direction of reactions. For electrochemical reactions involving metals and metal ions, tables of electrode potentials are most convenient, but for reactions involving organic species, it is generally easier to find free energy data. Many undergraduate college texts provide reviews of the principles of thermodynamics (e.g., Ref. 148). b. Tin Depletion Mechanism. This example illustrates that, during reflow in the presence of flux, Sn0 reduces PbO to Pb0, resulting in a change in alloy composition. This is the basis for the observation that the Sn0 concentration of Sn–Pb solders in C4 bumps and other solder joints decreases with successive flux-and-solder reflows. At the beginning of each reflow, both SnO and PbO are present on the surface of the solder. They react with the flux acid during reflow, forming a flux–salt solution. Although in solution, Pb2+ ions oxidize an equivalent amount of Sn0 to Sn2+ from the underlying base solder. Sn2+ replaces Pb2+ in the salt solution, and Pb2+ is reduced to Pb0 and becomes part of the alloy. The sequence is repeated with successive reflows and the amount of Sn0 depletion depends on the degree of oxidation between reflows. This phenomenon, which also occurs with In–Pb solders, is often misinterpreted as the ‘‘leaching of Sn and In from solders’’ by flux, but is predicted correctly by the application of electrochemical principles [149– 151] (Table 20). Spalik conducted a study to determine whether flux or the oxidation of Pb0 in the solder caused the decrease in tin concentration observed with flip chip solder joints (C4) that experienced multiple reflows. Differential scanning calorimetry analyses made on 90Pb–10Sn solder samples both before and after heating to about 350jC in the presence of a rosin flux for more than 24 hr showed no detectable change in the tin content. This result was consistent with the requirement that in order for a metal to dissolve in an acid, H2 must be evolved. In other words, the following reaction must occur: 2C19 H29 COOH þ Sn0 ! Sn2þ þ 2C19 H29 COO þ H2ðgÞ z
ð65Þ
Hydrogen was not evolved in the Spalik study. It was determined that the reduced tin content observed in flip chip solder joints subjected to multiple reflows was the result of lead (Pb) whose TABLE 20 Gibbs Free Energy of Formation for Common Solder Oxides Reaction 2Ag+1⁄2O2!AgO Cu+1⁄2O2!CuO Pb+1⁄2O2!PbO Pb+O2!PbO2 H2+1⁄2O2!H2O Sn+1⁄2O2!SnO Sn+O2!SnO2 Zn+O2!ZnO 2In+3⁄2O2!In2O3 2In+3SnO!Sn+In2O3 Sn+PbO!SnO+Pb Sn+CuO!SnO+Cu H2+SnO!H2O+Sn H2+PbO!H2O+Pb H2+CuO!H2O+Cu C+1⁄2O2!CO C+O2!CO2 CO+SnO!Sn+CO2
DGof (kJ/mol) 11.2 129.0 188.0 219.0 237.0 257.0 521.0 319.0 832.0 121.0 69.0 128.0 20.0 49.0 108.0 137.2 394.3 3.0
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oxidized surface was reduced by metallic tin, which subsequently dissolved in the excess flux. It is more noticeable when the surface-to-volume ratio is large, as is the case for flip chip solder joints. Spalik provided additional verification of this mechanism by dissolving lead(II) acetate in the flux and repeating the experiments. In this case, Spalik observed a substantial reduction in tin content. Based on this observation, a flux composition that could reduce the concentration of Sn0 in low Sn0 solders (e.g., 5/95 or 3/97 Sn–Pb) by 1–2% was formulated [138], thereby significantly increasing the ductility and resistance to thermal fatigue of flip chip solder joints, while maintaining the wetting characteristics of the higher-Sn-content solder. c. Potential as Gaseous Fluxes. With regard to oxide reduction by the active organic species in a flux, Table 21 shows the Gibbs free energy of formation DG0f of some carboxylic acids, and the results of free energy calculations for their reduction reactions with Sn and Cu oxides. As noted earlier, this information is useful in predicting whether or not a reaction is feasible. Using
TABLE 21 Gibbs Free Energies for the Reduction of Solder Oxides by Carboxylic Acids DG0f (kJ/mol)
Reduction reaction Formic O H-C OH
þ CuOý Cu þ CO2 þ H2 O
361.4
129.0
0
394.3
237.0
140.9
Oxalic O O C-C þ SnO ý Sn þ 2CO2 þ H2 O OH HO 697.9
257.0
0
394.3
237.0
70.7
Formic O H-C OH
þ SnO ý Sn þ CO2 þ H2 O
361.4
257.0
Acetic H
O
H-C-C OH
H 390.0
0
394.3
237.0
12.9
þ 4SnO ý 4Sn þ 2CO2 þ 2H2 O
257.0
0
394.3
237.0
155.4
Succinic H
O
H
O
C-C-C-C HO 747.4
H
H 257
OH
þ 7SnO ý 7 Sn þ 4CO2 þ 3H2 O2
0
394.3
237.0
258.2
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the example of succinic acid as a potential reducing agent for SnO, as depicted in the table, the calculation is: Products Reactants ½7ð0Þ þ 4ð394:3Þ þ 3ð237:0Þ ½ð747:4Þ þ 7ð257:0Þ ¼ 258:2 kJ=mol which shows clearly that reduction of SnO by succinic acid is not possible, and thus reaffirming the more likely acid–base type of reaction described previously. This is of interest because gaseous formic and acetic acids have been considered potential candidates for ‘‘clean’’ gaseous fluxing. Based on the large negative free energy (right-hand column), formic acid easily reduces CuO, but the reduction of SnO is not nearly as favorable. Even though some reactions may be feasible, other factors may take precedence. For example, formic acid can also react with SnO as an acid and produce tin(II) formate. So instead of a clean reduction reaction, a carboxylate salt is produced. Oxalic acid can also reduce SnO, but acetic acid and those having more carbon atoms cannot. These data indicate that reduction of oxides is only feasible for several organic acids. Only those reactions for which the calculations result in a negative value are feasible. d. No Relationship. It should be noted that electrochemical potential and Gibbs free energy are not related to activation energy. Activation energy represents an energy barrier to an otherwise spontaneous reaction. A catalyst can lower this barrier, but cannot cause a nonspontaneous reaction to proceed. 4. Typical Flux Reactions The primary reaction of a flux (acid) with a metal oxide (base) is to form a salt at the surface of the solder, and water that is evolved with heat during reflow. A study of the reaction products of abietic acid with SnO, PbO, and CuO identified carboxylate salts [152]. It should be emphasized that the product of this reaction is an organic salt, and should not be referred to as a complex to distinguish it from coordination complexes. The salt acts as a surfactant (i.e., it lowers the surface tension of the liquid solder, much as soap lowers the surface tension of water, and promotes the reaction of the metals). The pairs of chemical equations listed in Table 22 illustrate representative reactions of SnO and CuO with different potential flux activators and the reaction products. In general, other activators and oxides could be substituted into these equations. Observe in (1) and (2) of Table 22 that gaseous reaction products would be evolved at reflow temperatures, leaving only their respective liquid chloride salts to promote wetting. If left on the surface, they could potentially cause electrical failure, but because of their good water solubility, they are easily removed. Example (3), on the other hand, leaves an insoluble residue. Zinc oxide is not electrically conductive, but makes it difficult to completely remove any excess ZnCl2. As noted in Sec. 6.7, these activators are not used in electronics applications. The amine chloride (hydrohalide) noted in Eq. (4) illustrates that these activators are not classified as inorganic and fall under the RMA and RA classifications in Table 15. The respective chloride is water-soluble; however, the amine residues may or may not be water-soluble. The lower-molecular-weight compounds (typically less than six carbon atoms) are water-soluble, but also quite volatile; whereas those with more than six carbon atoms are less water-soluble. In any event, chloride and amine residues must be completely removed. It is only necessary to provide a minimum amount of HCl as an activator. For example, a no-clean paste that contains less than 100 ppm of organic bromide was developed [111]. However, if an amine derivative is selected as the activator in a flux, it must be one that provides good water solubility for the residue. Amino alcohol residues have been shown to be significantly easier to remove [102]. The carboxylic acid (Eq. (5)) illustrates the formation of a general salt (R indicates any hydrocarbon) and water. The salt may be innocuous, as in the case of water white (W-W) rosin, and need not be removed if permitted by the application. Other salts may be water-soluble, as noted in the example fluxes of Figs. 47 and 48. Volatile decomposition products (Figs. 49 and 50) that are desirable for no-clean applications may also form. The redox reactions illustrated in example (6) are the only reactions that truly leave no residue. When applicable, they have the advantage over oxide removal techniques such as reduced oxide
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TABLE 22 Representative Reactions of SnO and CuO with Several Potential Flux Activators Representative flux reactions (1) Hydrogen chloride SnO+HClýSnCl2+H2O(g) CuO+HClýCuCl2+H2O(g) (2) Ammonium chloride SnO+2NH4ClýSnCl2+H2O(g)+NH3(g) CuO+2NH4ClýCuCl2+H2O(g)+NH3(g) (3) Zinc chloride SnO+ZnCl2ýSnCl2+ZnO CuO+ZnCl2ýCuCl2+ZnO (4) Amine hydrochloride SnO+2RNH2HClýSnCl2+H2O(g)+2RNH2 CuO+2RNH2HClýCuCl2+H2O(g)+2RNH2 (5) Carboxylic acid SnO+2RCOOHýSn(RCOO)2+H2O(g) CuO+2RCOOHýCu(RCOO)2+H2O(g) (6) Redox SnO+COýSn+CO2(g) CuO+COýCu+CO2(g) SnO+H2ýSn+H2O(g) CuO+H2ýCu+H2O(g) SnO+HCOOHýSn+CO2(g)+H2O(g) CuO+HCOOHýCu+CO2(g)+H2O(g)
soldering activation (ROSAk) discussed in Sec. 6.13.2 in that the oxide is removed at the time of reflow. 5. Effect of Surface Tension and Surface Oxides To achieve proper solder joints, the molten metal must be in direct contact with the metal surface to be joined. For bonding to occur, some form of interaction must take place at the interface. In the case of Sn–Pb solders bonding to Cu, Sn must diffuse into the Cu surface, forming the intermetallic compounds Cu3Sn and Cu6Sn5 with the bulk of the solder alloy bonded to this layer. Solder-to-solder bonding results from alloy reacting at the liquid interfaces. Oxides and surface tension present a barrier to the spreading and reaction of liquid metals in contact with solid metals. The oxide presents a crustlike layer that restricts the flow of molten metal across the interface. Surface tension is the result of unequal forces acting upon the surface atoms. Both oxides and surface tension act to inhibit the transport of one metal into the other. a. Surface Modification Required. The surface layer must be modified for solder wetting to proceed. In addition, surface energies must be favorable for wetting, such that the total free energy of the system is lowered as a result of solder wetting. In the case of solder-to-solder systems, the total free energy is lowered by interaction and minimization of the surface area of different or identical alloys. For solders with different elemental compositions or concentrations, the lower-melting-point solder becomes liquid first and dissolves the other, creating an intermediate composition or concentration at the interface. The increase in entropy of mixing results in lowering of the total free energy of the system. If the solders are of the same concentration, the joining at the solder surfaces results in a reduced area, and thus lowers the total surface energy. This situation is also encountered when a solder paste melts and interacts with a solder used as a lead finish or solder balls on components (ball grid array), or flip-chip solder bumps when attached to chip carriers.
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The primary role of the flux is to interact with surface oxides to form salts, which in turn either assist the oxide layer to be displaced, or act as wetting agents in conjunction with the remaining liquid flux components. In electronic applications, flux should not be expected to clean contamination resulting from poor handling and atmospherical conditions. An R-type rosin or R-type equivalent synthetic flux, now designated ROL0, REL0 or ORL0, is capable of dissolving small amounts of atmospherical contamination and reacting with thin oxides of Cu and Sn. This type of flux can be quite effective with SnO, but not SnO2. Other metal/metal oxide systems such as nickel require additional activity, such as that provided by an amine hydrochloride. However, HCl-activated fluxes are not typically used in high-reliability electronics applications. In these situations, Ni is overcoated with Au and a nonactivated flux is usually adequate.
L.
Choosing a Flux
1. Activity Based on Application The primary consideration in selecting a flux is the intended application. The Institute for Interconnecting and Packaging Electronic Circuits (IPC) has devised a classification consisting of three categories (Table 23) based on application. These categories range from least critical applications such as consumer electronics to those requiring a very high degree of reliability. In general, as the required reliability increases, the activity and potential for corrosion or reducing surface insulation resistance. In applications requiring reduced level activity, fluxes also require more care to assure that parts are properly prepared for adequate solder wetting. Only tin tarnishes can be removed by low-activity fluxes. In addition to selecting a flux that is prudent for the application, there are other considerations as well. Among these are the method utilized to apply the flux, whether the flux is to be removed, and how it is to be removed. 2. Reduced Rosin Content: No-Clean Fluxes There is an ongoing emphasis to eliminate postsolder cleaning operations, particularly those that contain organic species that have been identified as harmful to the environment. Using cleaning agents that contain harmful species adds significant cost to treat and recycle these solvents to comply with local, state, and federal environmental requirements. Accordingly, the so-called lowsolids-content fluxes have been developed, commonly referred to as no-clean fluxes. There are two categories of no-clean fluxes. The first category contains approximately 10–15% resin by volume. These fluxes are used when aesthetics are not a priority, as they leave a visible residue. They are particularly useful in cases where an inerting atmosphere (N2) is usually required because they typically produce acceptable solder joints without the need for a protective environment.
TABLE 23 Flux Activity Based on Application According to IPC Specification IPS-5-815 Class (allowable activity)
Product type
1 (Moderate to high)
Consumer
2 (Low to moderate)
Industrial
3 (Very low to low)
Critical/uninterrupted operation
Product examples Electronic games Hand-held communications Home entertainment systems Laptop/desktop computers Telecommunications Business/industrial electronics Noncritical military Work station/server computers for industry, business, and government
Reliability level required Low to moderate
Moderate to high
High to very high
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However, a class of fluxes containing 3–5% rosin is the most widely utilized low-solids fluxes (LSFs). It is important to always be cognizant of the fact that no-clean fluxes are not no-residue fluxes; rather, they are fluxes that leave a minimal quantity of residue postsoldering that is also benign in terms of reliability. Even though all of the components of a flux may be volatile at reflow temperatures, the chemical reaction with the oxide surface usually produces salts which remain. Figs. 49 and 50 illustrate the reactions of two dicarboxylic acids with SnO through a reflow profile. Also, most ingredients contain impurities of up to 2%. Therefore, it is preferable to use only a sufficient quantity of flux to assure satisfactory results. 3. Increased Rosin Content and Activity As already noted, one way to increase the activity of rosin-based fluxes is to increase the activity of the activator material, hence the progression of R to RMA to RA fluxes. Another less drastic approach is to increase the rosin content, which is typically 35–45%. Because rosin is mostly abietic acid as noted earlier, increasing the rosin content increases activity. Doing so, of course, increases the potential for corrosion. If a rosin flux was not removed postsoldering for an application, it may be necessary to remove it if the rosin content is increased. 4. Aqueous Clean A cleaning approach between utilizing an organic solvent and a no-clean flux is to utilize a watersoluble flux. It may be desirable to utilize a flux that also leaves residues that are a potential reliability concern, and so must be removed. A class of materials consisting of organic acids that is water-soluble has been formulated. These fluxes were originally dispensed as aqueous solutions, but now as alcohol solutions similar to rosin fluxes to reduce the tendency to form solder balls due to ‘‘spitting.’’ Cleaning essentially involves a wash to remove the residue, a rinse to remove the contaminated wash water and solvent, and a drying step to remove leftover moisture [153]. Like all cleaning solvents, a flux system that is compatible with the product design must be selected (i.e., capable of removing residues from closely spaced components, leads, and from beneath components with a small board-to-component gap height as occurs with flip chips and chip scale packages). For aqueous clean fluxes, isomers of carboxylic acids, solvents, and other ingredients can be selected for heat stability in the temperature ranges of interest [154], tackiness, and aqueous solubility. For no-clean applications, the activators and solvents can be chosen so that by optimizing flux quantity, very little residue remains, and postreflow oxygen plasma treatment can offer an effective nonsolvent method for removing low-residue solids associated with a no-clean flux in assembling flip chips on organic carriers [155].
M.
Fluxless Soldering
The advantage of fluxless soldering is that no residues are present postsoldering. If the only impediment to wetting and spreading required for successful soldering was the presence of an oxide surface layer, the simple reduction with forming gas or organic acid vapor would be sufficient to achieve coalescence. 1. Hydrogen Not Practical Utilizing hydrogen to reduce the metal oxides (MO+H2=M+H2O) would be a good candidate for fluxless soldering. However, the reaction is too slow at the standard eutectic Sn–Pb reflow temperature (approximately 220jC) and only becomes effective above 350jC, which would damage many components and degrade the board material [156,157]. Although it has been reported that a lower-temperature reduction can be achieved in high vacuum [158,160], this would be a cumbersome and expensive approach in high-volume manufacturing. 2. Other Possibilities Reduced oxide soldering activation is another method being evaluated [161,162]. Oxides of Sn, Pb, and Cu are reduced by placing the component in a solution of vanadous ion under a blanket of nitrogen. The half-cell reactions are:
SOLDER WETTING AND SPREADING Reduction Oxidation
SnO2 þ 4Hþ þ 4e ¼ Sn þ 2H2 O 2þ
4V
¼ 4V
3þ
þ 4e
415 ð66Þ ð67Þ
The solution is regenerated electrolytically: Cathode Anode
N.
4V3þ þ 4e ¼ 4V2þ þ
2H2 O ¼ 4H þ O2 þ 4e
ð68Þ
ð69Þ
Flux Perspectives for Joining with Lead-Free Solders
Ideally, a drop-in replacement for lead-based soldering would be highly desirable. However, finding a lead-free alloy with properties identical to the commonly used lead alloys now appears to be unlikely. Metals do not form an unlimited number of compounds, and in their liquid state are usually just mixtures of metallic elements. The number of solder alloys with melting points low enough to form eutectics near the Sn–Pb eutectic is very limited. The most promising alloys have melting points 30–40j higher than eutectic Sn–Pb and are more difficult to solder. Because all soldering processes require temperatures exceeding the solder melt temperature, sometimes referred to as super heating, it is necessary to raise the peak reflow temperatures as well. For example, Sn–Pb assembly operations are traditionally carried out at temperatures that range from about 210jC to 230jC. For lead-free solders that melt at about 217jC, the reflow temperature must be about 235–245jC. These temperatures are borderline for some components and organic materials utilized in microelectronics assemblies before they start to suffer some degradation. Some maintain their integrity to 250jC and beyond. Most fluxes were developed for the Sn–Pb system, particularly eutectic Sn–Pb. Their chemistry was developed through years of experience and trial-and-error to accommodate a variety of soldering requirements. Many of these fluxes have provided robust processes, and several were utilized during the initial stages of implementing lead-free solders, but typically have not performed as well as they did with Pb-based solders. There is a strong need to develop new fluxes that become active at higher temperatures, are closer to lead-free alloy melting points, and peak at reflow temperatures to improve wetting. Some possibilities involve steps to minimize oxide thickness by methods such as the addition of organic salts based on common solder metal ions and polycarboxylic acids.
O.
Flux Application
1. Methods There are many ways of applying flux depending on flow characteristics and manufacturing requirements, some of which are listed in Table 24. Among these are: brushing, rolling, dipping, spraying, foaming, and wave fluxing, to name a few that are not particularly sensitive to quantity. For some applications, however, it is necessary to dispense an accurate flux volume. For example, an automated tool is used to dispense a predetermined droplet in the center of a microsocket array of a chip carrier for the placement and subsequent reflow attachment of flip chips. The flux spreads out evenly over the surface of the carrier, owing to the excellent wetting properties of the flux/carrier system. It was noted in Sec. VI.L.3 that one method to increase the activity of a rosin-based flux is to increase the rosin concentration in the flux. It should be noted that high-solids-content fluxes typically do not readily form foam. Wave fluxing is often used to dispense flux for high-solidscontent fluxes. A tradeoff analysis is necessary if raising the solids level to increase activity results in the need to change the method of flux application. 2. Quantity Only the amount of flux needed to cover the solderable surfaces at reflow temperatures is generally required. Beyond meeting a minimum requirement, most soldering operations are not overly sensitive to flux quantity. There are some, however (such as flip chips, passives, and other
416 TABLE 24
SINGLER ET AL. Some Commonly Used Flux Application Methods
Method
Description
Dipping
Bring board in contact with flux reservoir
Brushing
Circular brush located between a pan or reservoir containing flux and the bottom of a circuit board Brush dips into flux, rotated to contact board underside as board passes by Action is continuous Very similar in concept to wave soldering Underside of board passes over a flux wave Several variations, but all resulting in a fine mist of flux directed at the board One or a number of nozzles can be utilized to address larger-sized boards, increase throughput Small flux bubbles are created by forcing air through porous tubes housed in an A-shaped fixture Bubbles exit the top of the A-shaped fixture Similar to wave soldering, bubbles contact the bottom of a board they passes over the A-shaped fixture
Wave fluxing
Foam fluxing
Comment Simple Low cost Poor flux volume control Simple Flux volume control is poor
Flux volume can be excessive Typically more uniform and better volume control than dipping, brushing, and wave fluxing Maintenance issues (e.g., clogged nozzles) Simple Low cost Applies thin, very reproducible flux coating
Compatible with no-clean low-solids fluxes
low-mass components), where excessive quantities can create problems (i.e., ‘‘float away’’ the component). Typically, the optimum flux volume must be determined empirically using process equipment and controlled dispense techniques. The optimum amount, of course, depends on the application; but generally speaking, a quantity sufficient to cover the solderable surfaces is all that is necessary. The flow characteristics of a flux are chosen or optimized for a specific application by diluting the base flux with a solvent to provide the desired viscosity, tackiness, and evaporation and wetting properties to assure that the active ingredient is well distributed primarily over the wettable surfaces. It has been suggested that with some fluxes, a thin layer gives better spreading than a thick layer [163]. A flux is optimized not only in relation to a specific set of ingredients but also in relation to the solids content; in other words, specific gravity and viscosity are optimized for various application purposes. Therefore, manufacturing quality procedures must be put in place to maintain these parameters within an acceptable process window. a. Excess Amount. The negative consequences of too much flux are increased residues and floating of components. From a cleaning perspective, excess flux leaves more flux residues, which become increasingly difficult to remove from beneath components, or from flip chips with large numbers of dense (i.e., tight pitches) area array interconnections. In automated lines, excess flux is typically removed by utilizing a low-pressure air knife, similar to the removal of excess solder during wave soldering. In no-clean flux applications, excess flux residue is of particular concern because it has been shown to impede the adhesion of underfill materials that facilitate improved solder joint reliability. b. Insufficient Amount. It is essential that enough flux be present when reflow begins to assure that the joining surfaces have sufficient active material to react with the complete oxide
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surface during the period of time the solder is molten. Too little flux may not assure that all of the solder bumps on an entire flip-chip site are covered, or may result in the active ingredient evaporating before reflow is complete and result in partial or nonwet conditions.
P.
Test on Basis of Manufacturing Conditions
Although much has been interpreted from empirical data about flux action and soldering, it is still an inexact science. In 1958, Milner [164] wrote ‘‘that scientific principles which govern the behavior of fluxes are not known.’’ Even with the knowledge of various flux chemistries, that opinion largely is still true today. In other words, knowing the acidity (pH and pKa) values, wetting rates, wetting angles, activation energies, etc., does not guarantee success in formulating or selecting a flux for a particular application. Although useful, most of the techniques applied in evaluating fluxes are a little more than tabulating and comparing results. With even limited knowledge of the chemistry of fluxes, it is relatively easy to select a few ingredients and formulate a flux that exhibits substantially satisfactory wetting. However, the development of a flux that is optimized for a particular application requires a fairly detailed understanding of chemical principles and requires extensive testing of many formulations. To a large extent, the formulation of fluxes is still conducted as an art, which, perhaps, is why there are so many proprietary formulations. Wetting rates, wetting angles, area of spread, activation energy, etc., provide convenient means of comparing formulations and narrowing the field of candidates. However, reflow profiles, heating rates, oxygen levels in N2 blanketed reflow furnaces, and solder metallurgy all affect performance, so it remains necessary to conduct final testings on manufacturing equipment. An understanding of the chemistries and function of flux ingredients is extremely valuable as a starting point. Testing on manufacturing equipment with the actual product is time-consuming, expensive, and potentially problematic (contaminating equipment), causing downtime and a throughput reduction, so it may be beneficial to conduct tests by offline methods. Although there are numerous methods to evaluate the effectiveness of fluxes, it is still most informative to observe the effect of a particular flux under actual reflow conditions. Hot plate experiments can simulate reflow furnace temperature ramp rates and are rapid, but atmospherical oxygen may cause results to be different from that which would occur in a reflow furnace under a nitrogen atmosphere. Hot plate-type studies allow the observation of component movement due to the action of the flux when heated, whereas these movements could not be observed by just examining the component position after passing through a reflow furnace. Observation in real time also can help to evaluate evaporation rates, solder spitting, and phase changes that occur as the volatile components boil off, as well as determine the effects of different temperature ramp rates. Therefore, hot plate-like studies and those that address manufacturing aspects are both necessary to evaluate the adequacy of a flux for a particular application.
VII. A.
NO-LEAD SOLDERS Pb–Sn Solders (Benchmark)
To most effectively identify candidate no-lead tin-based replacement alloys for the Pb–Sn alloy system, it would be helpful to have an understanding of the effects of Pb on wetting in the Pb–Sn system. However, as was discussed in Sec. V, the role of Pb and other secondary constituents in wetting is not precisely understood. Notwithstanding, a brief review of certain aspects of Pb–Sn wetting is presented here. 1. Tin Addition to Lead (Pb) It is interesting to consider the topic of this subsection from the perspective of the effects of the addition of Sn starting with pure Pb. The focus is on the industrially important ternary system Pb–Sn–Cu. Liu and Tu [165] studied the wetting of the Pb–Sn alloy system on Cu with both molten alloy and solid substrate immersed in RMS flux. The experiments were conducted at 10jC
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of superheat for each alloy. For the case of pure Pb, they measured a value of hEf115j. This value of the contact angle differs strongly from the result quoted by Naidich [10] in Sec. 2.5.1, but the reader is reminded that measurements there were made in a gaseous H2 environment, whereas here measurements were made using an RMA liquid flux environment. They found that hE decreases monotonically with increasing weight percent of Sn to a minimum equilibrium angle at approximately 60 wt.% Pb where hEf8j. However, further increase in Sn content resulted in a monotonic increase to hEf37j for pure Sn; thus, there is a distinct minimum. The value of the contact angle for the smallest Sn addition is hEf39j, corresponding to 95 wt.% Pb [165]. In the absence of wetting data for even lower concentrations of Sn, one could conjecture that smaller concentrations of Sn than 5 wt.% would have a similarly strong effect on the contact angle. The beneficial effects of the presence of Pb may be seen for the particular case of (eutectic) 37 wt.% Pb in Fig. 51, which shows spreading kinetic data for pure Sn at 250jC (18jC superheat) plotted against eutectic Pb–Sn at both 200jC (17jC superheat) and 250jC. The superior wetting of the Pb–Sn alloy over pure Sn is clear and is consistent with the above contact angle results of Liu and Tu [165]. In their result for pure Pb, cos hE<0, so that from Young’s equation, rSF
FIG. 51 The wetted radius R vs. s for pure Sn and eutectic Pb–Sn spreading on 12-Am sputtered Cu.
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419
phases decreases with increasing temperature, and the q-phase formation eventually becomes favorable due to the low Sn supply. They, therefore, note that the q-phase forms at large values of superheat whereas the D-phase forms at smaller values of superheat. The D-to-q transition occurs at different temperatures for Pb–Sn alloys of different compositions, and they conjecture that at extremely low Sn levels, little or no superheat may be necessary to form the q-phase. As the Sn content increases, however, all forces act to favor D-phase formation. Once Sn is present in the alloy, the value of rSF approximately corresponds to the interface either of Cu3Sn or Cu6Sn5 in equilibrium with the corresponding liquid phase. Unfortunately, there is no experimental data providing unambiguous values of rSL for either of the two intermetallic/ liquid interfaces or for the liquid Pb/solid Cu interface. However, Boettinger et al. [17] used a wetting balance to show that a 60Sn/40Pb weight percent solder wets pure Cu, Cu3Sn, and Cu6Sn5 equally well in the presence of an RMA flux at 235jC. All three cases exhibited nearly identical wetting force vs. time traces, terminating with the same steady-state value of the force. At first, this may seem like a controversial result, implying that the energetics of the three interfaces plays an insignificant role in wetting. However, the reader is reminded that the experiments of Boettinger et al. were carried out on preformed intermetallic compounds, which are quite different from intermetallic compounds formed during and as a consequence of wetting. Furthermore, the initial alloy composition is far from being in equilibrium with the three interface compositions. 3. Effect of Some Fluxes The changes in rSL are not the only possible changes occurring in the system as the Sn content is increased. Recall from the discussion in Sec. V that there may exist a mode of transport of Sn ions in some types of flux. Thus, when Sn is introduced into the system, Sn atoms could possibly migrate from the liquid alloy through the flux to the flux/Cu substrate where they cannot only adsorb to the Cu surface but subsequently react to form Cu3Sn (assuming that the supply of Sn by adsorption is very low). Again, there exists no experimental data for the corresponding change in rSF between the flux/Cu and flux/Cu3Sn interfaces other than that it is clear that the latter must be less than the former. It would also be possible that not all adsorption sites would be filled ahead of the advancing contact line, with the result being a chemically heterogeneous surface whose surface energy could be estimated according to Eq. (45) in Sec. V.D.8. Thus, the contact line may in fact be moving over an Sn–Cu intermetallic compound instead of Cu and this would alter the contact line kinetics. This scenario of Sn–Cu compound formation ahead of the contact line is fundamentally different than the surface diffusion of Pb scenario postulated by Smith and Lea [8] and presented in Sec. V. Evidence of Sn–Cu intermetallic halos or side bands preceding the contact line was presented by Liu and Tu [165]. Apparently, the topic of halos is an area of some controversy but an extremely important one as it has profound implications with regard to wetting and spreading in metallic systems. Several other phenomena associated with increased Sn content should be mentioned. The first is the effect on the surface tension (whether it be of Pb–Sn alloy in contact with liquid flux or inert gas). The surface tension of Pb–Sn alloy increases monotonically with increasing weight percentage of Sn. Thus, from the perspective of surface tension, increased Sn reduces the driving force of wetting. Additionally, Prakash and Sritharan [166] note that there is a difference in the morphologies of the intermetallic compound liquid/alloy interface that depends on the initial concentration of the Pb–Sn alloy. These different morphologies manifested different surface areas and hence affected the total interfacial energy associated with the liquid alloy/intermetallic compound surface. This would also affect the wetting dynamics. Finally, if the intermetallic compound formation is extensive, the original composition of the Pb–Sn alloy could change, particularly in localized regions, due to the consumption of Sn as a reactant. It is the confluence of all of the above phenomena and the uncertainties associated with them that have prevented wetting and spreading, even in an established alloy/substrate system such as Pb–Sn–Cu, from being completely understood.
420 B.
SINGLER ET AL. Pb-Free Wetting
In the identification of a suitable Pb-free alloy, it is desirable to select an alloy, which has wetting performance similar to the Sn–Pb alloy system on Cu-based and Ni-based substrate metallization. Most Pb-free candidate alloys have a high Sn fraction with some secondary constituents such as Ag, Bi, Cd, Cu, In, Sb, and Zn added. From a wetting perspective, it is important to understand the manner in which these secondary constituents influence the physical and chemical properties (e.g., melting point, viscosity, surface tension, density, substrate dissolution, and intermetallic formation). Consider, for a moment, adding constituents to liquid Sn to improve its wetting performance on Cu. Feng et al. [167] investigated the effect of electronic structure on the wetting of Sn-based alloys on Cu. They suggest that spreading of Sn on Cu was expected to improve when Sn was alloyed with an element that reinforces the electron orbital interaction between Sn and Cu. In addition, it may be possible to improve the spreading by adding a species that lowers the overall liquid surface tension. Some possible alloying options are Bi, Pb, and Sb, which have a lower liquid surface tension than Sn. Also, Cu substrate dissolution can be reduced if a small amount of Cu is added to the liquid alloy. Unfortunately, with the simple guidance offered above, it is not presently possible to predict the spreading characteristics of a proposed Pb-free alloy. In fact, there are indications that Ag, Sb, and Cu additions may result in reduced wetting (Figs. 52–54).
FIG. 52 (a) Spreading area measurements for various lead-bearing alloy and lead-free solder alloys spreading on Cu with a rosin flux. (b) Corresponding experimental peak reflow temperature. (From Ref. 167.)
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FIG. 53 Wetting equilibrium contact angles of various Pb-free solder alloys. (a) Cu substrate with RMA (GF-1235) flux. (From Drewin et al. Ref. 169.) (b) Cu substrate with RMA (Alpha 611) flux f40jC superheat over the liquidus temperature. (From Vianco et al. Ref. 170.) (c) Cu substrate with RMA flux at f30jC superheat over the liquidus temperature where the liquid alloy is dispensed onto a heated substrate. (From Pan et al. Ref. 171.)
The many interdependent factors involved in wettability assessment make experimental evaluation of various alloys essential. Reviewing the body of experimental spreading data, considerable variation in wetting performance exists for the various Pb-free alloys tested. These variations arise from differing experimental techniques, experimental temperatures, substrate types, and flux types. In the present discussion, wetting measurements that report equilibrium contact angle and use an RMA (mildly activated rosin) flux on a copper substrate were used wherever possible. Some of the wetting data presented here were obtained from a database being compiled by a National
FIG. 54 Comparison of the contact angles on Cu of Sn–Bi eutectic, and 1% addition of ternary elements. A 200jC peak reflow temperature and Kester 197 rosin flux were utilized. (From Ref. 173.)
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SINGLER ET AL.
FIG. 55 Contact angles on Cu of various lead-free solder alloys utilizing Kester 197 rosin flux at a peak reflow temperature of 250jC. (From Ref. 173.)
Institute of Standards and Technology project [168] and, in those cases, original data references were cited. 1. Spreading Characteristics A comparison of the spreading area measurements for various lead-bearing and lead-free alloy is given in Fig. 52a. The reported peak reflow temperature, which varies with alloy (Fig. 52b), is generally 30 to 50jC above the alloy melting temperature. Fig. 52a shows that increasing Bi content in Sn-Bi solders decreases spreading. In contrast, increasing Pb content in Sn-Pb solders (up to the eutectic composition) improved spreading. The various alloys were ranked according to their wetting characteristics in order from best to worst as: Sn–Pb, Sn–In, Sn–Ag, Sn, Sn–Sb, Sn–Cd, and Sn–Zn. Reviewing the ranking, it is apparent that no one attribute (surface tension, viscosity, reaction with substrate, etc.) can be used to explain the spreading variation observed from alloy to alloy. 2. Contact Angle Fig. 53 is a compilation of contact angle measurements of various lead-bearing and lead-free solder alloys measured by Drewin et al. [169], Vianco et al. [170], and Pan et al. [171], Drewin et al. and Vianco et al. determined the contact angles from a wetting balance, whereas the experiments of Pan et al. were unique in that they deposited a liquid drop of the alloy onto a preheated fluxcoated substrate. Generally, the contact angles of the lead-free alloys tend to be in the 30–50j range, with Ag-bearing alloys tending to have slightly higher contact angles. None of the leadfree alloys have contact angles as low as Sn-Pb culectic alloy. 3. Effect of Ternary Elements Many emerging lead-free solders are comprised of 3 or more alloying elements. Loomans et al. [172] evaluated the spreading of Sn–Bi eutectics with the addition of 1% ternary elements (Fig. 51) and found that the contact angle increased with the addition of each ternary element investigated. As seen in Fig. 55, the presence of Zn always increased the contact angle (i.e., decreases wetting). 4. Effect of Silver Additions Sessile drop experiments, using a formic acid–nitrogen gas mixture as a flux, performed by Goslin et al. [173] on Au-coated Ni substrates (Fig. 56), indicate that the addition of Ag in the alloy reduced spreading. Fig. 57 shows the spreading results for the same alloys except that the
SOLDER WETTING AND SPREADING
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FIG. 56 Spreading studies carried out at 250jC of Sn, Sn–0.7Cu, Sn–3.5Ag, and Sn–3.5Ag–0.7Cu solders on 0.05-Am Au over 4.5-Am Ni deposited on a Si wafer. All alloys are given in weight percent. A gaseous flux mixture of formic acid and nitrogen was used. (From Ref. 173.) The initial sphere diameters were 0.889 mm and were deoxidized with the ROSA process. (From Ref. 174.)
FIG. 57 Spreading studies carried out at 250jC of Sn, Sn–0.7Cu, Sn–3.5Ag, and Sn–3.5Ag–0.7Cu solders on thin Au over 0.34-Am Pd/3.3-Am Ni deposited on a Si wafer. (From Ref. 173.) All alloys are given in weight percent. A gaseous flux mixture of formic acid and nitrogen was used. The initial sphere diameters were 0.889 mm and were deoxidized with the ROSA process. (From Ref. 174.)
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substrates have a layer of Pd between the Au and Ni. With the presence of the Pd, the addition of Ag to the liquid alloy did not result in as great a reduction in spreading for reasons that are not fully understood at this time. 5. Effect of Flux With the exception of the gaseous flux experiments shown in Figs. 56 and 57, all the spreading experiments discussed utilized a mildly activated rosin flux. As noted in Sec. 6, there appears to be Sn transport in the liquid rosin flux from the spreading drop to the unwet copper ahead of the contact line, so the impact of flux chemistry on solder spreading is clearly significant. Loomans et al. [172] showed that SnCl2 promotes good spreading of solders on Cu not only because it is a good activator but because it also reacts with Cu to give Sn or Sn–Cu intermetallic compounds on a Cu surface. Vaynman et al. [175] were able to reduce the contact angle of Sn–Zn eutectic alloy (Tm=198.5jC) on Cu at 260jC from 89j to 25j by changing from a mildly activated rosin flux to a flux containing Sn organic compounds. For comparison, pure Sn under these conditions had a 37j contact angle. They indicate that x-ray diffraction experiments showed that these Sn organic compounds decompose and form pure Sn on the Cu surface. Although the effectiveness of these fluxes to improve wetting is clear, they must be carefully evaluated to insure that there are no flux residues left behind, which would be detrimental to the long-term reliability of an electronic assembly. 6. Summary In summary, the spreading of Pb-free solders is generally not as good as the heritage Sn–Pb alloys they will be replacing. The Pb-free solders also require higher process temperature. There are a number of factors influencing the spreading behavior of Pb-free alloys and it is likely that several different substrate/alloy/flux combinations will emerge and that manufacturing inspection criteria for ‘‘acceptable wetting’’ will need to be redefined.
ACKNOWLEDGMENTS T. Singler and S. Meschter would like to express their deep gratitude to Liang Yin of the Materials Processing Laboratory of the Department of Mechanical Engineering at SUNY Binghamton for his expert assistance with figures and other aspects of manuscript preparation.
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12 Lead-Free Finishes for Printed Circuit Boards and Components Rob Schetty Technic Inc., Plainview, New York, U.S.A.
I. INTRODUCTION Tin–lead is used as the primary electronic interconnection material in solder pastes, PCB coatings, and as a finish on the external leads of electronic components such as surface-mount and through-hole devices, or as a solder ball or bump material on advanced semiconductor packages, such as ball grid arrays (BGAs), chip scale packages (CSPs), and flip-chip devices. In order to create a truly environmentally safe Pb-free electronic assembly it is required that Pb-free materials be used throughout the interconnection. As with solder pastes, many options exist for creating a Pb-free circuit board or component finish. To date, most research on Pb-free solder paste materials has identified binary, tertiary, and quaternary alloys of tin with additions of trace metals such as silver, copper, and/or bismuth as the most promising to replace Sn–Pb solder. In the case of solder balls or bumps on advanced packaged components, these are typically formed via a molten extrusion process; therefore any combination of compatible metals can be blended to the desired composition, and as such, this is outside the scope of this chapter. However, in the case of PCBs or ‘‘conventional’’ surface mount or through-hole components, the solder material is often applied via electrodeposition to create a plated deposit or finish. Electrodeposition is a complex electrochemical reaction involving metal ions, electrolyte compounds, and proprietary additives in an aqueous solution. The electrodeposition of more than one metal is difficult, and more than two metals almost impossible in a manufacturing environment. It is not practical for plated finishes on boards and components to match Pb-free solder paste materials. Therefore it is anticipated that Pb-free electronic interconnections that consist of a solder paste material, a board finish, and a component finish will likely not all be the same material, but some combination, i.e., hybrid structure. That is, the board or component finish need not necessarily duplicate the selected solder paste composition; the main requirement is that they be compatible with the Pb-free solder paste material. This chapter will focus on a number of Pb-free board and component finishes such as nickel/palladium and other precious metal-containing coatings, pure tin, and tin alloys. Solderability performance will be demonstrated with both Pb-containing and Pb-free solders, and other important properties will be discussed.
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II. TYPES OF FINISHES AND DEPOSITION METHODS The term ‘‘finish’’ as used in this chapter is defined as a surface coating or treatment that is applied to a substrate or to an underlying layer on a substrate. The function of the finish is to modify, protect, and enhance certain properties of the substrate or underlying layer onto which it is applied. Most finishes for PCBs and components are applied to enhance the solderability of the substrate or underlying layer so that at the board-assembly level, the board or component will solder well and provide a reliable, long-life solder joint. Other functions of finishes include wire bonding, contact switches, press fit connectors, etc. Finishes can be metallic or nonmetallic, organic or inorganic, and fusible or nonfusible in nature. Most finishes for boards and components are metallic. Many common metallic finishes for PCBs and components are applied through a technology called ‘‘plating.’’ Plating processes can be further categorized by the specific deposition method employed: (i) electrolytic plating or electroplating; (ii) electrode-less plating, more commonly known as electroless plating; and (iii) immersion plating also known as displacement plating. These are briefly described below.
A. Electrolytic Plating In electrolytic plating, a substrate is immersed into an aqueous solution containing ions of the metal to be plated (Mn+) and an anode which is a solid form of the metal to be plated (M). In this case the substrate acts as the cathode, and when the anode and cathode are linked through an external power supply and current is applied, electroplating occurs by virtue of the following reactions: Cathodic reaction: Anodic reaction:
Mnþ þ n e ! M M ! Mnþ þ n e
ð1Þ ð2Þ
At the cathode, the metal ions in solution are reduced to their metallic state and metal is electrodeposited onto the substrate; at the anode, solid metal dissolves electrolytically, forming more metal ions that feed the cathodic plating reaction. Electroplating takes place until such time as the current is turned off. The maximum thickness of electroplated deposits is, in theory, only limited by the current utilized to apply the finish, and the length of plating time. However, once the practical thickness limit is exceeded for a specific material, a functional deposit can no longer be obtained. Other than the metallic ions in solution, there normally also are proprietary compounds known as ‘‘additives’’ in solution that highly influence the electrodeposition reaction and the deposit properties. Collectively, this solution is known as the ‘‘electrolyte.’’ Electrolytic plating reactions can be very simple or highly complex, and much of the ‘‘art’’ around electroplating involves the formulation of the specialized proprietary additives that impart specific desired deposit properties. A schematic of a typical electroplating reaction is shown in Fig. 1, which illustrates the interaction of the metal cations (M+), conducting acid ions (A), organic addition agents (O), and electrons () as the metal ions are reduced electrolytically at the cathode surface. Solution pH, operating temperature, applied current, composition and concentration of chemical constituents all play an important role in electroplating.
B. Electroless Plating Electroless and immersion plating are similar in that no external power supply is required to drive the deposition reaction. In electroless plating, also known as autocatalytic plating, the electrons required to force the deposition reaction are supplied by a chemical reducing agent (R) that donates electrons to the catalytic surface of the substrate. As the deposition reaction proceeds, the reducing agent (R) is subsequently oxidized to species (Rox) as illustrated by the reaction below, Mnþ þ R ! M þ Rnþ ox
ð3Þ
LEAD-FREE FINISHES FOR PCBs AND COMPONENTS
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FIG. 1 Schematic illustrating the interaction of various species in a bath during plating.
No power source, electrical connections, or anodes are required for electroless plating, and plating occurs on a continuous basis until the substrate is removed from the plating bath, unless the metal ions or reducing agents are depleted from the solution, and so high thickness deposits are possible. Electroless plating baths are usually complex mixtures of metal ions, reducing agents, stabilizers, chelating agents, conductivity compounds, and proprietary additives. Solution pH, operating temperature, composition and concentration of chemical constituents, etc. all play an important role in electroless plating and careful control of the electroless plating bath is required to ensure consistent, uniform deposition.
C. Immersion Plating Immersion or displacement plating is the deposition of a metallic coating (M) on a metallic substrate (S) from a solution that contains the metal being plated, and the metal on the substrate is displaced by a metal ion from solution that has a lower standard electrode potential than the displaced metal ion. The displaced substrate material enters the solution in ionic form (Sn+) and the metal ion (Mn+) deposits onto the substrate in its place. In immersion plating the electrons required to force the deposition reaction to occur are supplied by the surface of the substrate itself and no chemical reducing agents are required as illustrated in the reaction below, Mnþ þ S ! Snþ þ M
ð4Þ
No power source, electrical connections, or anodes are required for immersion plating although the thickness of the deposited metal in this case is self-limiting because deposition stops when the entire surface of the substrate has been coated; therefore only relatively thin (
D. Other Types of Finishing Application Methods Molten coatings such as hot air solder leveled coatings (HASL) on PCBs are applied via specialized equipment that coats the substrate with molten metal selectively in the areas where the finish is desired. The thickness distribution is not as uniform as with plated finishes. As the molten coating method involves application of a molten metal at very high temperatures, the
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TABLE 1 Summary of the Advantages and Disadvantages of the Various Plating Methods Utilized for Metal Finishes in Electronic Assemblies Finishing method Electrolytic plating Electroless plating Immersion plating Molten coating application Organic coating application
Thickness variation
High thicknesses possible
Difficulty to apply
Cost
M L L H M
Yes Yes No Yes No
L M L M L
M H L/M L L
Key: L=low; M=moderate, H=high.
method has additional drawbacks of safety and health concerns for operators of the equipment, as well as a high thermal loading which the substrate must endure during the coating operation. Organic coatings are often applied via an immersion process. Although in name this process may seem similar to the immersion plating process the fundamental mechanism is quite different in that in place of a metallic layer an organic layer is deposited and no substrate material is displaced during the reaction as occurs during immersion plating. Instead of relying on electron donation from the substrate to drive the deposition reaction, the organic coating immersion process relies more on surface adsorption and chemical agents that are specifically attracted to and/or reacted with the substrate material. A summary of the advantages and disadvantages of the various finishing methods is provided in Table 1.
III. LEAD-FREE PRINTED CIRCUIT BOARD FINISHES Extensive activities are underway in both industry and academia to identify and implement alternatives to Pb for the various aspects of Sn–Pb solder electronic assemblies. In the area of Pbfree solder pastes, a ternary Sn–Ag–Cu alloy has been generally identified as the most promising candidate and so for the solder paste portion of electronics assemblies, the selection of a Pb-free material appears to have a clear direction. For PCB finishes, the choice is not so clear. Board finishes, also referred to as surface finishes or final finishes, can be generally classified into two categories: reflowed or molten coatings, and plated coatings. Plated coatings can further be subcategorized as electrolytically plated (with current) or electroless/immersion plated (without current) as described in the previous section.
FIG. 2 Graphic depicting the percentage of various printed circuit board (PCB) finishes produced in the United States in the year 2002.
LEAD-FREE FINISHES FOR PCBs AND COMPONENTS TABLE 2
435
Summary of Key Criteria for Board Finishes
Board finish criteria . .
. . .
. .
Possess good solderability and wetting characteristics, and be capable of maintaining those characteristics after exposure to a variety of natural and artificial aging environments. Be compatible with the reflow profile and flux types recommended for the selected Pb-free solder paste, and other component and board materials of construction (in general, enabling a reflow profile with a maximum peak reflow temperature of approximately 230–245jC). Be compatible with surface mount technology (SMT) and wire bonding. Be compatible with press fit and high density interconnect (HDI) connectors. Have a robust manufacturability performance, in most cases this means the ability to be applied from a chemistry that is easy to control, does not attack the solder mask, has good stability, and produces a finish that can be verified in production. Resist tarnishing or discoloration during storage and/or exposure to natural and artificial aging/ environments. Be cost-effective.
Board finishes have traditionally consisted of a molten Sn–Pb coating applied via an application method referred to as hot air solder leveling (HASL). End users have been seeking a replacement for HASL for years, due to the inherent aspect of producing a nonuniform film thickness which creates a lack of planarity, which is of increasing importance as component I/O grid dimensions are steadily decreasing. Good planarity is important to assure high yields, and in dealing with high-reliability solder joints with fine-pitch components. The need to eliminate Pb from PCBs has only accelerated the push for HASL replacements. Although HASL is widely sought to be eliminated, it is worthy to note that in 2002 approximately 50% of all PCBs produced in the United States were processed through HASL (Fig. 2).
A. Lead-Free Board Finish Criteria Board finishes must meet the criteria listed in Table 2.
B. Lead-Free Printed Circuit Board Finishes The most common Pb-free PCB finishes under consideration are listed in Table 3. Each surface finish is discussed in detail in the following sections.
TABLE 3 The Most Common Lead (Pb)-Free Printed Circuit Board Finishes Circuit board finishes . . . . . . . .
Pb-free HASL Reflowed tin Electrolytic tin–bismuth Electroless nickel/immersion gold (ENIG) Electroless nickel/electroless palladium/immersion gold (ENEPIG) Organic solderability preservatives (OSPs) Immersion silver Immersion tin
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TABLE 4 Variations Typical of Eutectic Sn–Pb Hot Air Solder Leveled (HASL) Finishes Parameters Poor planarity Solder joint volume variations
Net variability due to HASL
Characteristics Typical range, 10 to 100 A-in. Typical example – 0.050 in. pitch, 0.0260.080 in. pad size – solder volume. Range 104 to 2080 mils3 – theoretical printed volume, 4440 mils3 2.3% to 47%
Source: From Ref. 1.
1. Industry Reference: HASL Eutectic Sn–Pb HASL has the key advantage of excellent solderability because ‘‘nothing solders like solder.’’ In addition, HASL-produced finishes possess an excellent shelf life (at least 1 year), provide a good electrical probe surface, and HASL finishes easily withstand multiple processing steps. Advantages: Notwithstanding its limitations, HASL is a well-understood, mature, low-cost surface finish, and currently >80% of the cards used worldwide have a HASL finish. HASL’s popularity is predicated mostly on two factors: (a) It is much cheaper than a plated finish in most instances, and (b) users do not have to be concerned about wetting (i.e., yields, reliability) because it comelts with the screen printed solder forming an integral mass (i.e., no wetting of an interface is required). This is particularly true if the card or board is used fairly soon after the finish is applied (i.e., Sn still in the 2+ state instead of 4+ state). Disadvantages: The main disadvantage of HASL coatings, notwithstanding the fact that they contain Pb, is the wide thickness variation they typically exhibit, both in terms of pad-to-pad and board-to-board thickness variations. The HASL process is not capable of providing finishes with a planar surface to enable the placement of components during SMT assembly as described in Table 4 and illustrated in Fig. 3. There are other concerns in addition to the effects of solder volume variation, such as oxidation. High Sn content alloys have Sn oxide on the surface. In the case of Sn–Pb, it is Sn oxide as opposed to a Pb oxide that is present on the surface. A fresh HASL alloy coating containing Sn is very wettable as the Sn in the oxide, typically 10–20 A˚ thick, is in the
FIG. 3 Scanning electron microscope (SEM) micrograph depicting a significant variation in solder volume deposited on metal features on a printed wiring board (PWB) by the HASL method.
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TABLE 5 Comparison of Variations Between Finishes Created by Plating (Planar) Compared to HASL (Nonplanar) Device
Pitch (in.)
Pad width (in.)
Solder vol. (mils3)
Paste vol. (mils3)
% Variability finish: paste
104–2080 36–720 25–500 5.7–113
4440 1680 920 303
2.3–47.0 2.1–43.0 2.7–54.0 1.8–37.0
15–22.5
920
0.16–0.24
15–22.5
920
0.16–2.7
f0
920
f0
Nonplanar finish PLCC 0.050 0.026 Lead 0.020 0.012 QFP 0.016 0.010 BGA 0.020 0.012 Planar finish Immersion Ag or Au, 3–4 Ain. thick QFP 0.016 0.010 Flat solderable Sn, 30–35 Ain. thick QFP 0.016 0.010 Organic solderable preservative QFP 0.016 0.010 Source: From Ref. 1.
(2+) state. However, over time due to exposure to air, etc., the Sn2+ is converted to a Sn4+ oxide state that is more difficult to reduce by the flux during soldering, thus making the surface significantly less wettable. The thickness of the Sn oxide is also thicker (50 to >100–300 A˚). There is also a high thermal stress imparted to boards during HASL due to the high temperatures they encounter, and the risk of solder-plugged holes or reduction in hole size that poses potential reliability problems. In terms of manufacturability, HASL can be performed in a vertical or horizontal conveyorized mode, but the HASL process is not ideal because the equipment is difficult to work with, poses safety hazards due to high operating temperatures, and frequent maintenance requirements. However, as the drive to finer pitches continues, HASL coatings will increasingly become a problem due to bridging, and solder volume variations resulting in even larger solder joint solder volume % differences compared to larger size pads. Table 5 indicates that planar finishes achieved through plating result in a much smaller finish variability compared to a nonplanar finish as is created by a HASL deposition. Planar finishes are therefore the choice for tight pitch applications. 2. Lead-Free HASL It is possible to maintain the HASL operation and simply substitute one of the many common Pb-free alloys listed in Table 6 in place of molten Sn–Pb solder in the HASL equipment. The end result is a Pb-free HASL finish that eliminates the Pb problem, but the intrinsic deficiencies
TABLE 6 Several Candidate Lead-Free Alloys for HASL Deposition of Printed Circuit Board Finishes Alloys
MP, jC
93.3 Sn–0.7 Cu 96.5 Sn–3.5 Ag 96.2 Sn–3.2 Ag–0.5 Cu 90 Sn–2.0 Ag–7.5 Bi
227 221 218 186–212
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of the HASL process listed in Table 7 remain unresolved. Based on the potential consequences, it is not likely that Pb-free HASL will be widely adopted. 3. Reflowed Lead-Free Solder or Tin Reflowed lead-free solder or reflowed tin, also referred to as selective reflow or selective solder (or tin) strip, is a process whereby solder or tin is electrolytically plated onto the copper pads and traces on a PCB prior to solder mask application. A solder that does not contain Pb could potentially be plated as an electrolytic Pb-free surface finish. The solder (or tin) must then be selectively stripped to expose those areas of the copper where soldermask will be applied. The coating is then reflowed to produce the final finish. The main advantage of this method compared to HASL is that the coating thickness variation is greatly reduced, as the thickness uniformity is much better with an electroplated deposit compared to a HASL molten solder coating. Plated and reflowed films provide a relatively planar and consistent surface suitable for SMT fine-pitch component attachment. Other advantages of this method include good solderability; long shelf life (at least 1 year); good electrical probe surface; and the reflowed tin or solder coating easily withstands multiple processing steps as the solder-wetting characteristics of tin are excellent. The disadvantages of this method include a limited and decreasing availability of suppliers providing this technology; environmental issues related to tin and tin–lead stripping during the process sequence, an additional high thermal stress condition, and increased risk of via or holes plugged as a result of the tin or tin–lead reflow operation. Also, the registration tolerances for the BGA soldermask is insufficient as the tolerance buildup between the registration of the tin or tin– lead stripping process and the soldermask features can create very narrow soldermask dams with questionable solder mask adhesion around BGA devices. The adhesion of the BGA soldermask dam is a critical feature that prevents solder from being wicked away from the BGA pad and escaping down the adjacent via hole [2]. The additional process steps of this method cause the cost to be higher compared to HASL. 4. Electrolytic Tin–Bismuth (Sn–Bi) Some companies have investigated the use of a eutectic tin–bismuth alloy (58Bi–42Sn) coating deposited electrolytically from a plating bath during the PCB manufacturing operation. This method is similar to the reflowed tin option discussed in the previous section; however, a tin– bismuth alloy is deposited in place of pure tin or tin–lead. A eutectic tin–bismuth finish may be beneficial in cases where low-temperature soldering is required, given eutectic tin–bismuth’s low melting point (138jC). The properties of tin–bismuth finishes are summarized in Table 8. Solder wetting tests indicate that eutectic tin–bismuth coatings reflowed at 170jC provide good wetting characteristics with low wetting angles (<15j), essentially similar to Sn–Pb coatings reflowed at 220jC (Fig. 4). Other than some niche applications where a low melting point is acceptable or even desired, electrolytic tin–bismuth will probably not be widely used owing to potential reliability issues arising out of service ambient temperatures, the presence of Sn–Pb solder, and other factors discussed in Section 4 on Pb-free component finishes.
TABLE 7 Intrinsic Deficiencies of the HASL Process for Board Finishes Issue Higher melting point
Process variations Higher material cost Compatibility
Consequence Stress HASL equipment Stress components Increase dross formation Solder joint volume variation As compared to Sn–Pb Tooling infrastructure Other metallurgical systems (e.g., components)
LEAD-FREE FINISHES FOR PCBs AND COMPONENTS TABLE 8
439
Summary of the Major Aspects of Tin–Bismuth (Sn–Bi) Finishes
Parameters Mechanical properties Plating deposition rate Eutectic (42Sn–58Bi) melting point Melting temperature range Early acceptance Compatibility with Sn–Pb solder
Characteristics Acceptable Acceptable 138jC From pure Sn (232jC) to eutectic composition (138jC) Nikkei Sangyo, Tokyo, Japan, 1998 Forms brittle Bi–Pb IMC. Concerned with hybrid (partially Pb-free) systems
Source: From Ref. 3.
5. Electroless Nickel/Immersion Gold This surface finish is widely used (Fig. 2). The electroless nickel/immersion gold (ENIG) technology involves autocatalytic deposition of a nominal 5-Am coating of nickel–phosphorous alloy (typically 6–10% P) from an electroless nickel process followed by an immersion coating of gold (f0.05 to 0.1 Am Au). The thin gold coating in the ENIG deposit functions simply as a protective layer to prevent oxidation of the underlying nickel, and all subsequent assembly operations (solderability, wire bonding, etc.) take place directly with the nickel surface. Advantages of the ENIG surface finish are summarized in Table 9. Characteristically, ENIG finishes provide an extremely flat, planar surface for attaching SMT components with excellent solderability, a good electrical probe surface, a suitable surface for edge connectors and press fit applications, and a good surface for wire bonding (with aluminum wire only). Handling issues are minimized and the finish easily withstands multiple process steps. The excellent solder wetting performance of ENIG finishes is demonstrated in Fig. 5. This figure shows the wetting force vs. time for an ENIG finish that has been stored for a period ranging from 2 to 18 months at room temperature. Several notable features to this figure are (i) the wetting speed is consistently fast; (ii) high, stable wetting forces are consistently obtained, and (iii) there is minimal degradation in the solderability of the ENIG finish after being stored for 18 months, as evidenced by the very slight decrease in wetting force and speed in the figure. The ENIG process is very complex and involves at least six primary chemical processing steps and greater than 20 overall process steps, each of which requires a very strict level of process control. Both the nickel and the gold plating baths operate at temperatures exceeding 88jC,
FIG. 4 Comparative wetting test results of eutectic Sn–Bi with benchmark eutectic Sn–Pb solder.
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TABLE 9 Some Advantages/Benefits that ENIG Surface Finishes Provide Advantages/benefits . . . . .
Flat, uniform finish Finish wets solder well Relatively good shelf life – Resists tarnishing and discoloration Precious metal electrical contact surface Nickel provides several PTH benefits – Strengthens them – Protects barrels from Cu dissolution during wave soldering
increasing the magnitude of the thermally induced stress due to the coefficient of thermal expansion (CTE) mismatch between the deposited film pad metallization and circuit board material. The higher plating temperature also causes problems for other materials on the circuit board, especially the soldermask. Soldermask lifting was the initial problem encountered by the implementers of the ENIG process, although that has mostly been resolved by improvements in formulations made by soldermask suppliers and improved process control by board fabricators (running processes at the lowest possible temperature, minimizing dwell times, etc.). Other disadvantages of ENIG finishes include the difficulty in measuring the final Aucoating thickness, cost increase relative to HASL, and most importantly, a major reliability issue that is a low-level defect common to ENIG finishes referred to as ‘‘black nickel’’ or ‘‘black pad’’ in the industry. The defect, which exhibits a characteristic interfacial (i.e., flat) fracture (Fig. 6), is believed to be due to corrosion of the underlying nickel layer by the gold plating process under certain conditions. The corrosion causes solder to dissolve gold off a SMT pad and form a weak intermetallic bond to the nickel as depicted in Fig. 7. The weak bond can lead to interfacial fracture of solder joints during storage resulting in components actually falling off the board. It is particularly problematic with large-lead-count ball grid array (BGA) components as shown in Fig. 6. The defect is typically experienced at a low ppm level, although some board types are more susceptible than others. It is believed the problem can be contained through a combination of plating process and board design improvements and process control at the board fabricators. However, the potential reliability risk is a barrier to the wider implementation of ENIG.
FIG. 5 Wetting force for ENIG finishes that have been stored for up to 18 months at room temperature.
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FIG. 6 Planar separation characteristic of ENIG ‘‘black pad’’ problem.
6. Electroless Nickel/Electroless Palladium/Immersion Gold The electroless nickel/electroless palladium/immersion gold (ENEPIG) finish is simply an ENIG finish into which an intermediate layer of palladium (0.1 to 0.5 Am thick) is deposited between the electroless nickel and immersion gold coatings. Palladium is deposited from an autocatalytic plating bath. Palladium is a noble metal applied to protect oxidizable Ni. Palladium (m.p. 1552jC) is not fusible but rather dissolves in the molten solder in a manner similar to gold, and
FIG. 7 Conditions that cause the ‘‘black pad’’ problem sometimes observed to occur with ENIGtype finishes. (From Ref. 4.)
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solder wetting is limited by the need for complete dissolution of Pd into the solder. That is, the thickness of Pd must be sufficient to adequately protect the underlying Ni from oxidation, yet not be so thick as to inhibit complete dissolution during soldering. Therefore a trade-off is required as dissolution of Pd into Pb–Sn solder is four orders of magnitude less than Sn. No more than 0.3Am Pd can be dissolved in a few seconds during soldering. Therefore the coating on Pd-finished components must be kept to less than about 0.4 mm to assure dissolution. The oxidation protection for Ni is questionable if the deposit is porous. Other advantages of an ENEPIG finish include excellent solderability, an extremely planar surface (comparable to ENIG) with ‘‘multifunctional capability’’ to accept SMT assembly, wave solder, wire bonding with gold or aluminum wire, and press-fit connectors. These finishes also provide a good probe and contact surface result in minimal handling issues, and withstand multiple process steps. In terms of reliability, the ENEPIG finish resolves the interfacial fracture issue because the palladium layer acts as a barrier to prevent the immersion gold bath from attacking the plated nickel film. Disadvantages include even more complex chemistry and additional process steps compared to ENIG, which results in a higher cost. The high cost of the finish is driven mainly by the palladium (Pd) content. Palladium prices historically were lower than gold until the mid-to-late 1990s when demand increased due to multiple applications causing the supply to severely tighten. Availability was also significantly affected by the political climate and instability in parts of the world that control the supply of palladium. The end result was a very erratic and upward Pd metal price peaking at over US$1000 per troy oz. in the early 2000s, making its use prohibitive. The price of Pd has reduced to the US$300–$400 per tr. oz. range, but given the uncertainties and instability in the supply situation many are uncomfortable with the selection of this finish. 7. Organic Solderability Preservatives Organic solderability preservatives or OSPs rely on a very thin organic coating directly on top of the bare copper on PCBs. Two types of OSPs are available: a ‘‘thin’’ version (30 to 50 A˚), and a ‘‘thick’’ version (500 to 1500 A˚). The organic coating acts as a relatively short-term protection of the copper surface with an anticorrosion or antitarnish function. The coating then dissolves or evaporates during subsequent assembly operations leaving unoxidized copper as the surface for soldering operations. As the name implies, the only assembly operation an OSP finish addresses is solderability, a function it performs very well, providing good solder wetting characteristics, as shown in Fig. 8, which illustrates the wetting force vs. time curves for an OSP coating aged up to 672 days in a room temperature office environment. This figure demonstrates the good wetting behavior of the OSP finish as evidenced by consistently fast wetting times and high wetting forces
FIG. 8 Wetting force for a copper surface coated with an OSP finish aged up to 672 days at room temperature.
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443
FIG. 9 Degradation of solder wetting of organic solderability preservative (OSP) with repeated temperature/time cycles. (From Ref. 5.)
over the duration of this test. The finish provides a very flat surface for SMT, is very inexpensive, utilizes a simplified chemical processing sequence, and can withstand multiple process steps when used in the ‘‘thick OSP’’ configuration. Thin OSP coatings degrade with increased temperature and time as shown in Fig. 9. The disadvantages include the inability to function as a contact surface. The coating insulates the copper, so all electrical testing must be performed prior to the coating application. The material has a relatively short shelf life (maximum 6 months) and there are also handling concerns as a thin coating is easily damaged. Other disadvantages are a narrow process window for multiple passes, incomplete pad wetting, and an inability to accurately or easily measure the coating thickness. The advantages and disadvantages of OSP coatings are summarized in Table 10. 8. Immersion Silver (Ag) Immersion silver relies on a thin (0.1 to 0.4 Am) coating of silver deposited from an immersion silver process directly onto copper and is one of several immersion finishes under consideration. As described in Section 2, the immersion deposition process occurs as a result of the deposited metal ion having a lower standard electrode potential than the displaced metal ion. Supplemental reducing agents are not required in immersion plating because the base metal itself acts as the reducing agent. That is not the case in electroless plating. Immersion plating occurs when a base metal is immersed into a solution containing metal ions whose standard electrode potential is lower. For example, the standard electrode potential of silver is lower than copper as shown in Table 11 (i.e., silver is a more ‘‘noble’’ metal than copper); therefore silver will displace copper
TABLE 10 Characteristics of Planar Nonmetallic (Organic) Pb-Free Board Finishes Under Consideration Types Thin imidazoles Thick substituted benzimidazoles Thick phenyl imidazoles Prefluxes
Advantages Availability Low cost Large installed base Compatible with Pb-free solders
Disadvantages Relatively short shelf life Not suitable for contacts or wire bonding Difficult to inspect
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TABLE 11 Standard Electrode Potentials of Some Common Elements Element
Standard electrode potential
Gold Platinum Iridium Palladium Silver Mercury
Au +1.4 V Pt Ir Pd Ag +0.80 V E Hg
Ruthenium Copper Bismuth Antimony Tungsten Hydrogen Lead Tin Molybdenum Nickel
D=0.46 V Ru z Cu +0.34 V Bi +0.32 V Sb W H +0.00 V Pb Sn 0.1375 V Mo Ni 0.25 V
j
from the surface of a printed wiring board (PWB) circuit feature when the PWB is immersed into an immersion silver plating solution by the following reaction: Cu þ 2Agþ ! 2Ag þ Cu2þ
ð5Þ
As silver is prone to tarnishing (i.e., oxidation) during storage, the immersion silver process is usually chemically modified to include an antitarnish agent. The characteristics of a typical commercial immersion silver finish are shown in Fig. 10.
FIG. 10 Ref. 6.)
Steps to form and characteristics of a commercial immersion silver board finish. (From
LEAD-FREE FINISHES FOR PCBs AND COMPONENTS
445
FIG. 11 Wetting force for an immersion silver (Ag) board finish subjected to a precondition of 85jC/ 85%RH/24 hr. (From Ref. 7.)
Similar to OSPs, immersion silver coatings act to protect the copper surface from oxidation and therefore provide a solderable coating even after a period in storage. During SMT assembly, silver dissolves very quickly into the molten solder, so wetting characteristics are very good, i.e., wetting is very quick and exhibits high wetting forces with time as indicated in Fig. 11. As the coating is metallic or organometallic, it is more robust than a purely organic OSP coating, and the solderability performance of an immersion silver board finish after being subjected to a variety of aging conditions as measured by the solder float test is demonstrated in Table 12. In terms of manufacturability, the immersion silver process is relatively simple. The coating is very planar and provides a good electrical probe surface capable of withstanding multiple process steps. The coating is also easily detectable and measurable, and it is compatible with all known Pb-free assembly materials. The benefits of immersion silver compared to HASL are provided in Fig. 12. The disadvantage of immersion silver is the film is not as robust as a HASL coating and the thickness is inconsistent due to the self-limiting nature of the immersion process. The surface of an immersion-silver coating can tarnish during storage, even with the best of precautions. As the immersion silver finish is a relatively recent innovation, the long-term reliability and storage issues are not well understood. TABLE 12 Solder Float Test Results for Immersion Silver (Ag) Board Finishes After Exposure to Various Preconditions Condition As is 8-hr bake, 160jC – 8 hr – 8 hr, OSP – 24 hr Temperature/humidity (85/85) – 7 days – 25 days – 25 days, HASL Steam age – 4 hr – 8 hr Source: From Ref. 7.
% Solderability 100 100 65 100 100 100 85 100 100
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FIG. 12 Benefits of immersion silver (Ag) board finish compared to HASL. (From Ref. 6.)
9. Electrolytic Silver An alternate to immersion silver is electrolytically deposited silver. Although electrolytic silver is not commonly applied to PWBs, it is a very common electronic component finish that is particularly suitable for wire bonding applications. A standard procedure used in the industry (in contrast to a Ni/Pd finish) is to directly wire bond to an electrolytically deposited Ag pad and component lead surface as depicted in Fig. 13. Electrolytic silver is not practical for most PWB applications because of the high cost of plating a relatively thick silver deposit, and because of the reliability concerns associated with silver migration. Under certain conditions of temperature, humidity, and electrical bias, silver migrates from one pad to another as shown in Fig. 14. The silver filaments that form as a result of the migration are conductive and can cause electrical failures due to short circuits. 10. Immersion Tin (Sn) Immersion tin is another relatively new board finish, although it has been utilized in the industry in other forms for many years. Immersion tin relies on a relatively thin (0.1 to 0.5 Am) coating of tin deposited from an immersion-tin process directly over copper. The tin protects the copper from oxidation during storage. As tin is not readily deposited onto copper by an immersion process, chemical enhancing agents known as catalysts must be utilized to enhance the tin
FIG. 13 Schematic depicting a wire directly bonded to an electrolytically deposited layer of Ag on a lead frame finger at one end and on a similar deposit on a chip pad at the opposite end of the wire.
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FIG. 14 Schematic depicting the formation of thin Ag filaments, created through Ag migration, causing electrical shorts between adjacent PCB metal surface pads.
deposition characteristics. The compounds used typically are not environmentally friendly, and the process can be very aggressive in attacking soldermask material. Immersion tin provides a flat, consistent surface for SMT, a good surface for electrical probing and press fit connectors, and provides excellent solderability. An aspect of concern in utilizing immersion-tin coatings is that they can transform into a copper–tin intermetallic compound (IMC) over time that results in inhibiting solderability and shortens shelf life (6 months maximum). Tin deposited on copper begins to form copper–tin IMCs immediately after plating, and over time the tin coating is continuously consumed as it is converted to IMCs. The rate at which the conversion occurs depends upon the time and temperature of storage. While tin is readily solderable, copper–tin IMCs are inherently unsolderable; and if too much of the tin deposit is converted to IMC, the solderability of the finish degrades dramatically. Plating chemical suppliers have modified the immersion-tin process to incorporate organic addition agents and grain refiners in an effort to deter copper–tin IMC formation. These measures have succeeded to some extent in extending the shelf life of immersion-tin board finishes. Another issue that can arise with immersion-tin finishes and a potential reliability problem is the growth of tin whiskers. It has been observed that room temperature storage of boards coated with immersion tin can grow long filaments from the surface referred to as whiskers within a few weeks (Fig. 15). Again, plating chemical suppliers have attempted to address this problem through modifications of their plating formulations, and to some extent have succeeded. The subject of tin whiskers is a concern any time a tin or tin-rich alloy coating is utilized. The tin whisker issue is discussed in detail in Chapter 21. 11. Electroplated Tin (Sn) Electroplated Sn is another finish for both boards and components that is rapidly becoming a leading candidate. Electroplated tin can be deposited with a variety of deposit appearances and characteristics as noted in Table 13. Owing to historical considerations and military specifications on maximum permissible carbon content in tin and tin–lead deposits, matte tin or satin tin is generally plated for rigorous solderability applications such as PWBs and electronic components. Because of its higher hardness and lower susceptibility to staining, bright tin is usually selected for connector
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FIG. 15 SEM micrograph that shows a tin whisker growing from the wall of a PCB via hole.
applications where high insertion forces are experienced. Matte or bright tin is commonly used as an etch resist for PWB applications and as in this case the finish is only a temporary coating, the type of finish selected depends primarily on the fabricator’s preference. Much additional information on electroplated tin deposits is provided in Section 4 on component finishes. 12. Summary It is clear that no lead-free board finish is the perfect choice and the selection of a suitable board finish is highly application dependent. A summary of concerns of the various PCB surface finishes discussed in this chapter is listed in Table 14. A summary of the properties, key issues, advantages, and disadvantages of the board finishes discussed in this chapter is presented in Table 15. Typical process sequences are listed in Table 16.
TABLE 13 Characteristics of Various Types of Electroplated Tin (Sn) Finishes for Both Boards and Component Leads Characteristic Carbon content: Grain size: Reflectivity: Ductility: Hardness: Solder wetting speed: Ease of staining:
Matte (or matt) tin
Satin (or satin bright) tin
Bright tin
<0.1% f1–5 Am <0.2 GAM High Low Slow High
0.005–0.2% f0.5–5 Am <0.2–0.7 GAM Intermediate Intermediate Intermediate Intermediate
0.1–>1% <0.8 Am >0.7 GAM Low High Fast Low
LEAD-FREE FINISHES FOR PCBs AND COMPONENTS TABLE 14
449
Summary of the Issues for Several Lead (Pb)-Free Board Finishes
Finish
Concerns
Pb-free HASL finishes
.
Immersion metal finishes (Sn, Ag)
. .
Immersion Ag
. .
Immersion Sn
.
. .
Ni/Au
.
OSP
. .
Electroless Ni/immersion Au
. .
Electroless Pd NET
. . .
Compatibility challenges – Planarity sufficient for fine pitch – High temperature deposition – Alloy compatible with screen/wave solders Compatible with Pb-free alloys considered – Levels (i.e., amount) not critical Compatible with higher soldering temperatures Interest particularly in North America Silver migration (?) Cheaper than Ag – Early concern with whisker formation – Flat solderable Sn (FST) with small Bi concentration (<1%) reported not whisker prone per testing – Approval at Siemens, Alcatel, others Potential for whiskering Sn baths require careful control Package design considerations critical – Avoid ‘‘black pad’’ problem – May be replaced with Ni/Pd/Au flash Degraded solderability, multiple heat cycles No solder paste rework Au can embrittle solder joint – Requires proper PCB design Process not highly controllable Now, very expensive No universal finish anticipated User (at assembly) lowest cost will be key factor – Assumes reliability expectations are satisfied
IV. LEAD-FREE COMPONENT FINISHES Tin–lead has been used as an external lead finish for electronic components since the 1970s when technical and cost limitations of previously utilized gold plating made the continued use of gold prohibitive. Since that time, the finishing of internal leads and pads of devices with silver and external lead finishing with Sn–Pb has become the standard manufacturing method. The primary purpose of the external lead finish is to protect the component during storage and to preserve its solderability so that when attaching the component to the board during assembly is achieved with high yields, and that the solder joints meet reliability expectations. During the assembly operation, Sn–Pb on the component melts and mingles with the molten solder on the circuit board and solder paste to form a reliable solder joint. However, in practice it is not required that the component finish melt during the assembly operation. As long as the solderability of the component is maintained to provide a reliable solder joint, it is not necessary that the component finish must melt to achieve this. In 1989, Texas Instruments developed a multilayer palladium (Pd) finish [8] for components known today as Ni–Pd. The internal leads and pads of the semiconductor device as well as the external leads are coated with a common finish consisting of an initial Ni and then Pd electrodeposits. This method has been further refined to include a very thin gold layer as a final coating to enhance solderability. An additional benefit of this technology was that all Pb was eliminated from the package. Although the component industry has been relatively slow to adopt Ni–Pd finishes on a mass-produced scale, Ni–Pd (Au) is a serious contender to replace Sn–Pb as a Pb-free component finish.
Yes
Yes
OSPs
Electroless Ni/ Immersion Ag
Electroless
Yes
No
Immersion Sn
Pb–Sn HASL
High
Relatively low cost
Relatively low cost
Relatively expensive
High
Low
Cost
Compared to eutectic Sn/Pb. Source: From Ref. 1.
a
Yes
Immersion Ag
Pd
Yes
Finish
Needs OSP coating to preserve solderability Tarnishes in sulfur bearing atmosphere –
Excellent
.
.
Good, wetting slow
Excellent
Good
Solderabilitya
Yes
Yes
–
Yes
Marginal, requires more active flux Yes
Multiple heat cycle solderabilitya
Excellent
–
–
Good
Good
Good
Shelf life
.
. .
No
No
Yes, Al wire Ni under coating required Au wire with Au flash Yes
Yes
No
Wire bondable
Yes
Yes
–
Yes
Yes
Difficult
Electrically testable
Some solder masks are attached Yes
Good
Good
Aggressive chemistry lifts most resists
Good
Solder mask integrity
Comparison of Various Lead-Free Board and Component Finishes Under Consideration to Replace Tin–Lead (Sn–Pb)
Planar finish
TABLE 15
Yes
Yes
Yes
–
–
Difficult
Visual inspection– ability
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Acid clean Rinses Micro-etch Rinses Acid rinse Rinses OSP Blow dry Rinse Dry
OSP Acid clean Rinses Conditioner Rinses Predip Immersion silver Rinses Dry
Immersion silver Acid clean Rinses Micro-etch Rinses Predip Immersion tin Warm rinse Rinses Dry
Immersion tin
Typical Process Sequences for Various Lead-Free Finishes
Source: From Ref. 1.
Acid clean Rinses Micro-etch Rinses Drain Flux Preheat HASL Flux cleaner Hot rinses Rinse Dry
HASL
TABLE 16
Acid clean Rinses Micro-etch Rinses HCl predip Pd catalyst Nickel Rinses Palladium Rinses Dry
Electroless Ni/Pd
Acid clean Rinses Micro-etch Rinses HCl predip Pd catalyst Nickel Rinses Immersion gold Drag out Rinses Dry
Electroless Ni/immersion Ag (ENIG)
Acid clean Rinses Micro-etch Rinses HCl predip Pd catalyst Nickel Rinses Palladium Immersion gold Drag out Rinses Dry
Electroless Ni/Pd+Au flash
LEAD-FREE FINISHES FOR PCBs AND COMPONENTS 451
452 TABLE 17
SCHETTY Summary of the Requirements for Component Finishes
Property
Criteria
Melting point Conductivity Ductility Toxicity World reserves Solderability
Reliability
Manufacturability
Cost effectiveness
Compatible with reflow profile of the selected Pb-free solder paste Possess acceptable conductivity Sufficient to not cause fracturing of the coating during thermal excursions and/or mechanical assembly operations Meet worldwide governmental requirements Sufficient to supply worldwide electronics industry on an ongoing basis Possess good solderability/wetting characteristics and be able to maintain those characteristics after exposure to a variety of natural and artificial aging environments Not cause any unusual or accelerated reliability risks, such as whisker formation or solder joint fracture and, as such, be compatible with both Sn–Pb and Pb-free solder pastes Have a robust manufacturability performance, in most cases this means the ability to be electroplated from common, robust, commercially available plating solutions Be cost-effective relative to Sn–Pb
Lead-free component finishes must meet a variety of criteria that are listed in Table 17. The properties and reserves of the most common Pb-free component finishes are listed in Table 18. The table indicates that the physical and mechanical properties of the reference eutectic Sn–Pb are, for the most part, outstanding. For example, eutectic Sn–Pb exhibits a relatively low melting point that is compatible with common industry reflow profiles, and also with board and component materials of construction. The eutectic alloy has acceptable conductivity, has acceptable elongation, and there are sufficient world reserves. The only major drawback to eutectic Sn–Pb is its toxicity to humans due to its Pb constituent. As many of the desirable physical and mechanical properties of eutectic Sn–Pb are due to the Sn constituent, pure tin would seem to be a logical Pb-free alternative. Tin exhibits good conductivity, superior elongation, low human toxicity, and there are sufficient world reserves of this element. The melting point of pure tin (232jC), although higher than most lead-free solders, does not pose a problem in that the Sn would dissolve into the solder it is in contact with. The major lead-free component finishes are discussed in the following sections.
TABLE 18
Properties and World Reserves of Various Component Lead Finishes
Component finish
Eutectic composition
Melting point
Electrical resistivity (AV cm)
Sn–Pb Sn Sn–Bi Sn–Ag Sn–Cu Sn–Zn Ni–Pd/ Ni–Pd–Au
63Sn/37Pb NA 42Sn/58Bi 96.5Sn/3.5Ag 99.3Sn/0.7Cu 91Sn/9Zn NA
183jC 232jC 138jC 221jC 227jC 199jC >800jC
14.99 11.5 34.48 12.31 11.67 12.0 V12.0
Elongation
Human toxicity
World reserves of alloying element
28–30% >30% 20% 73% >30% 40% <20%
High Low Low Low Low Low Low
High High Relatively low Relatively low High High Very low
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A. Tin–Bismuth (Sn–Bi) Tin–bismuth possesses adequate electrical conductivity and elongation, moderate ductility, and low human toxicity. Bismuth is hampered by a relatively low amount of world reserves, and a very low eutectic-composition melting point. However, the melting point of tin–bismuth can be manipulated to a higher level by adjustment of the bismuth content. In fact, tin–bismuth is the only finish listed that has a melting point at or below the range of eutectic Sn–Pb and for this reason Bi-containing, Pb-free component finishes were the primary focus in the early stages of Pbfree development. However, there are significant reliability and compatibility issues regarding the use of Bi-containing materials with Sn–Pb solder that have emerged which have limited its longterm prospects.
B. Tin–Silver (Sn–Ag), Tin–Copper (Sn–Cu) Sn–Ag and Sn–Cu possess reasonably low melting points, acceptable electrical conductivity, good ductility, low human toxicity, and a moderate-to-large world supply. These three finishes are excellent candidates to replace eutectic Sn–Pb from a physical and mechanical property perspective, but suffer in other areas. 1. Tin–Silver (Sn–Ag) Lead Finish Tin–silver deposits are ductile and exhibit good solderability. However, the cost of Ag is high (>U.S.$8.00/lb). Also, plating variations have a significant impact on the melting point as noted in Table 19. The deposition rate is less than eutectic Sn–Pb, resulting in reduced productivity. Also, the plating solution waste treatment is more complicated. Tin–silver plating baths require strong complexing agents for deposits with low Ag content. These complexing agents complicate the waste management. Another complicating factor is undesirable immersion deposits on the cathode, anode, and equipment. In this system, Ag is much more noble than Sn, so Ag deposition is preferential, which is yet an additional complicating factor. 2. Tin–Copper (Sn–Cu) Lead Finish A notable attribute of the tin–copper system is its low cost (U.S.$2.50/lb). The typical alloys used are Sn–0.7Cu and Sn–0.35Ag–0.75Cu. The deposition current density is typically in the range of 5 to 30 A/dm2. These films exhibit good to excellent solderability characteristics. They have been determined to also exhibit excellent bend and ductility characteristics, i.e., they do not crack over a wide range of deposition and aging conditions. However, their composition and thus melting points are sensitive to process parameters. They also exhibit several plating-related factors such as undesirable immersion deposits on the cathode, anode, and equipment, a more difficult process to control, and more complicated waste treatment. The tin whisker growth concern is greater in the tin–copper system because small amounts of copper increase the propensity for whisker growth, which is a major reliability issue.
C. Nickel–Palladium (Ni–Pd) Nickel–palladium and its derivatives including Ni–Pd–Au are alternative Pb-free finishes that do not rely on melting of the coating during the board assembly operation. Instead, the top precious TABLE 19 Sensitivity of the Melt Temperature of Tin–Silver (Sn–Ag) Solder Alloys to Silver Content Silver content 3.5 5.0 10.0
Melting point, jC 221 250 300
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TABLE 20 Dissolution Rates of Various Metals in Molten Eutectic Sn–Pb Solder Metal Ni Pd Cu Au
Dissolution rate, Am/sec (215jC)
Dissolution rate, Am/sec (250jC)
<0.0005 0.00175 0.08 1.675
0.005 0.07 0.1325 4.175
Source: From Ref. 9.
metal coating(s) dissolve into the molten solder paste during reflow, and soldering is performed to the underlying nickel coating. Therefore the high melting point of Pd (>1500jC) is not an issue in terms of its applicability to being a Pb-free component finish as the dissolution rates of Pd and Au into molten eutectic Sn–Pb solder are the more important parameters as shown in Table 20. This table indicates that thin coatings of Pd and/or Au are fully dissolved during conventional reflow operations. Other physical and mechanical properties of Ni–Pd and Ni–Pd-Au are acceptable electrical conductivity, marginal ductility (potentially impacting its usage on certain component package types), and low human toxicity, but the most significant issue is the availability of Pd, the most important factor affecting its implementation. In summary, none of the Pb-free component finishes listed can clearly be eliminated due to any glaring deficiencies in physical or mechanical properties. The low melting point of Sn–Bi and the questionable availability of Pd are worrisome but not show-stoppers.
D. Pure Tin (Sn) Electroplated pure tin is emerging as one of the leading candidates to replace Sn–Pb as a component finish. As discussed in Section III.B.11, several different tin deposit types are possible, but for semiconductor component plating only the matte and satin tin deposits are receiving the greatest consideration, although others may be acceptable depending on the undercoat and other factors discussed in Chapter 21. In terms of physical and mechanical properties, pure tin finishes exhibit several characteristics. These finishes are nontoxic to humans, exhibit excellent wetting, are relatively easy to electroplate, have a reasonable cost, and possess good mechanical properties. As already stated, the most notable unfavorable aspect is the potential for dendritic whisker growth that can form even after having been in a field environment for several years. Typically, tin whiskers cannot be eliminated from entering the field by a post-manufacture inspection. These very thin filaments act as ‘‘microwires’’ creating a bridge between leads, thereby causing shorts. The mechanism is not fully elucidated; however, alloying is believed to inhibit growth in some cases while hastening growth in others (e.g., Sn–Cu system). Some additional tin whisker phenomenon discussions are in Section VII.A and very detailed in Chapter 21. Although deposition of tin is also possible through immersion and electroless techniques, these deposition methods are not considered here for component finishing due to the relatively high thickness requirements (typically >8 Am). Also, high productivity is required for component finishing which makes immersion and electroless plating methods not feasible for this application.
V. SOLDERABILITY Solderability is perhaps the most important property under consideration for a component finish, and obtaining and maintaining good solder wetting characteristics are the primary objectives for
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TABLE 21 Comparative Solderability Test Results for a Variety of Finishes Subjected to Various Aging Conditions Component finish Sn–Pb 90–10 Sn–Pb 90–10 Sn–Pb 90–10 Sn Sn Sn Sn–Bi 90–10 Sn–Bi 90–10 Sn–Bi 90–10 Sn–Ag 97–3 Sn-Ag 97-3 Sn-Ag 97-3 Sn-Cu 99-1 Sn-Cu 99-1 Sn-Cu 99-1
Aging condition
ZCT (sec)
% Coverage
As plated Steam aged Heat aged As plated Steam aged Heat aged As plated Steam aged Heat aged As plated Steam aged Heat aged As plated Steam aged Heat aged
0.29 0.46 0.32 0.58 0.83 0.68 0.33 0.41 0.37 0.42 0.54 0.53 0.39 0.83 0.79
>95% >95% >95% >95% >95% >95% >95% >95% >95% >95% >95% >95% >95% >95% >95%
any component finish. Many studies [10,11] have shown that fundamental solderability performance of all the finishes mentioned with both a Sn–Pb and a Sn–Ag–Cu solder is acceptable when evaluated by either the ‘‘dip and look’’ or wetting balance methods as shown in Table 21. Solder wetting is discussed in detail in Chapter 11. Previous research [12] has demonstrated to achieve good solder wetting that it is critical to maintain an adequate degree of superheat, defined as the temperature difference above the
FIG. 16 Effect of superheating on the solder wetting characteristics of some lead-free alloys in comparison to the eutectic Sn–Pb benchmark alloy.
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FIG. 17
SCHETTY
The effect of oxygen concentration and superheating on the wetting time of Sn–Zn solder.
melting point of the solder. For example, Hunt and Lea [12] showed that solder wetting characteristics of Sn–Pb, Sn–Ag, Sn–Cu, and Sn–Ag–Cu are almost identical with the same amount of superheating (Fig. 16). In terms of fundamental solderability performance and wetting properties, only Ni–Pd stands out as having a potential problem based on exposure to steam age test conditions, but this may be due to the solderability mechanism (dissolution vs. melting). Tin–zinc (Sn–Zn) suffers from a well-known oxidation problem upon exposure to air (drossing) that requires soldering in an inert atmosphere such as nitrogen. The wetting speed of Sn–Zn as a function of oxygen content is shown in Fig. 17. In general, increasing the superheat of the Sn–Zn solder increases wetting.
VI. MANUFACTURABILITY AND COST EFFECTIVENESS The manufacturability of Sn–Pb component lead finishes is well proven, as it is based on a wellestablished and mature technology. The manufacturability and cost effectiveness of the various types of finishes and coatings utilized for PCBs and components are summarized in Table 22.
A. Pure Tin (Sn) From a component manufacturing perspective, the removal of Pb from a Sn–Pb finish to create a pure Sn finish is virtually a drop-in replacement for Sn–Pb plating. Commercial tin-plating chemistries offer a wide operating window. The cost of pure-tin plating processes is equivalent to or less than commercial tin–lead plating processes.
B. Tin–Bismuth (Sn–Bi) Plating processes for Sn–Bi suffer from several deficiencies including a narrow range of operation, limited throughput due to plating speed limitations, and bismuth immersion on tin anodes that results in the need for additional plating bath and equipment maintenance, and control. As discussed in Sections 2 and 3.2.8, immersion deposits occur when a base metal is immersed into a solution containing a metal of a lower standard electrode potential. As shown in Table 11, Bi has a lower standard electrode potential than Sn; therefore Bi in the Sn–Bi plating solution will immerse on the solid tin anodes present in a production plating cell. This in turn interferes with anodic Sn dissolution and creates maintenance problems. The cost of Sn–Bi plating chemistry is moderately higher than Sn–Pb plating chemistry.
C. Tin–Silver (Sn–Ag) Plating processes for Sn–Ag are virtually nonviable in a manufacturing environment: they have an extremely limited range of operation, exhibit solution and metal instability, have immersion
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TABLE 22 Comparison of the Manufacturability and Cost Effectiveness for Several Board and Component Finishes Difficulty of manufacturability Finish
Board/component manufacturer
Assembly
Relative cost to manufacture
L L H H M L/M
L M/H L L M M/H
L L H H M M
L L M/H M H M L
L L M L/M M H M
L L M M M M H
Board finishes Pb–Sn HASL OSPs ENIG ENEPIG Immersion Ag Immersion Sn Component finishes Sn–Pb Sn Sn–Bi Sn–Cu Sn–Ag Sn–Zn Ni–Pd
Key: L=low; M=moderate, H=high.
problems, and composition control issues. That is, small changes in composition of the alloy have a significant effect on the melting point of the alloy as demonstrated in Fig. 18. It is very difficult to control the composition to achieve the desired alloy. The precious metal content of the process combined with its solution instability and frequent need for bath renewal results in a significantly increased cost compared to tin–lead plating, and one that is difficult to practice.
D. Tin–Copper (Sn–Cu) There are lead finishing problems associated with the Sn–Cu system similar to Sn–Ag: solution instability, composition control issues, and immersion coatings.
E. Tin–Zinc (Sn–Zn) Plating solutions for the Sn–Zn system are relatively uncommon, but appear to offer manufacturers a viable option provided the oxidation and corrosion issues associated with Sn–Zn can be dealt with. The plating solution cost is anticipated to be comparable with Sn–Pb baths, but processing costs are likely higher (e.g., need for inert atmosphere) to suppress the tendency for oxidation.
F. Nickel–Palladium (Ni–Pd) The Ni–Pd finish and its derivatives offer a streamlined manufacturing process, and thus significantly reduce costs in that component manufacturers can eliminate an entire manufacturing process step (plating). All lead finishing utilizing this method is performed by the lead-frame supplier. However, the political instability of those areas that are key producers of Pd makes it a difficult choice for many manufacturers. Because of the uncertainty in Pd supply combined with some reliability-related issues, many in the industry do not consider Ni–Pd and its derivatives a safe, reliable alternative to Sn–Pb finishes, although there are some users that have not experienced these problems.
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FIG. 18 Equilibrium phase diagram for the Sn–Ag system.
VII. RELIABILITY Several potentially significant reliability issues are a concern with some Pb-free component finishes. Eutectic Sn–Pb control has no known reliability issues with regard to its material properties and performance as a finish material. Removal of Pb to create a pure Sn component finish has one significant reliability issue: the formation of tin whiskers.
A. Tin Whisker Phenomenon Tin whiskers are thin single crystal filaments that grow from electroplated tin and tin-rich coatings after plating. The propensity of tin or tin-based coatings to spontaneously form whiskers is well documented and has been known for some time [13,14]. Tin whiskers appear in many different physical shapes and sizes, as shown in Fig. 19. Much has been written on this subject as it is of great concern within the electronics industry as tin whiskers have been known to cause shortcircuit field failures in commercial and military electronic products. Pure tin is not the only candidate to possess a tin whisker risk, and in fact all Sn-rich Sn alloys including Sn–Bi, Sn–Ag, Sn–Cu, and especially Sn–Zn pose reliability risks from the threat of tin whiskers. 1. Formation and Growth Mechanism There are several postulated mechanisms for tin whisker growth discussed in detail in Chapter 21, including recrystallization due to strain aging. The main driving force for tin-whisker formation is believed to be stress. The source of the stress can be either internal (i.e., created within the
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FIG. 19 Series of SEM micrographs that show various size and physical shapes of tin whiskers.
deposited film during the plating operation), or externally induced stress which may occur during assembly or due to the application in the field. Factors affecting internal deposit stress may include grain size and shape, crystal orientation, organic occlusions, inorganic impurities, substrate material properties, and processing steps prior to plating such as pretreatment. Examples of externally induced stress include mechanical stress such as forming or stamping, thermally induced stress, stress induced by IMC formation, etc. It is believed, based on some studies, that compressive stress in the deposit is the main driving force for tin whisker growth, generated either by the properties of the deposit itself or, more significantly, by the formation of IMCs when tin is deposited over copper or copper alloys [15]. The proposed mechanism involves the diffusion of copper into tin as the deposit ages at room temperature and the resulting formation of Cu6Sn5 IMC at the grain boundary locations. As there is an excess of material in a fixed volume, the tin grains are subjected to a compressive stress caused by the IMC surrounding them. As the compressive stress in the tin deposit increases, a ‘‘threshold’’ level of compressive stress is reached, and at this point a tin whisker forms to relieve the stress. Although other mechanisms of tin whisker growth may apply, recent quantitative stress analysis of deposits [16] coupled with focused ion beam (FIB) and scanning electron microscopy (SEM) investigations [17] has demonstrated that this explanation has validity as shown in Figs. 20 and 21. Through the use of the FIB, an analytical tool more commonly associated with front-end semiconductor wafer manufacturing, metallurgical cross sections of very fine features are possible. In these figures, a tin whisker and the tin deposit directly beneath the whisker have been sectioned and examined by SEM. The figures clearly show significant penetration of IMC directly surrounding the base of the tin whisker. These figures lend credence to the concept that the penetration resulted in a compressive stress around the tin grains in question, which subsequently caused a tin whisker to emerge from the deposit directly above the location of the IMC penetration.
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FIG. 20 SEM micrograph showing a sectional tin whisker and the region directly below it prepared using a focused ion beam (FIB). Intermetallic compound (Cu6Sn5) is present near the base of the whisker. The IMC is believed to stress the surrounding Sn grains, which has a role in nucleating tin whiskers.
Annealing and/or reflowing the tin deposit reduces the whisker propensity, through stress relaxation and formation of a regular, dense IMC [18]. Studies have shown that the type of tin– copper IMC formation that occurs at room temperature or at slightly elevated temperatures is uneven and readily penetrates the tin grains. 2. Use of a Nickel Barrier It has been useful to apply a nickel layer between the tin deposit and the substrate to reduce the propensity for tin-whisker growth because it creates a barrier between the substrate and tin deposit. The Ni layer effectively blocks IMC formation between the substrate material and the tin. Many references in the literature confirm the benefits of a nickel barrier coatings in reducing whisker growth [19,20]. In addition, studies have indicated that application of a nickel barrier coating produces a tensile stress in the tin deposit [21]. It is theorized that in the case of tin–nickel IMC formation (Sn4Ni3), tin diffuses into copper, contrary to tin–copper IMC formation where the copper diffuses into tin. As tin diffusion into nickel generates a deficit of material in a fixed volume, the tin deposit experiences a tensile stress. This finding is significant because it demonstrates that it is not necessarily the amount of stress in the deposit that is important for tin-whisker growth, but primarily the type of stress that is present. 3. Stress State Many investigators have confirmed the primary rule of tin whisker growth which is: no compressive stress=no tin whisker growth. Conversely, it has now been demonstrated that a tensile stress in the tin deposit is in fact beneficial for reducing the propensity for tin-whisker formation. Plating process developments are focused on producing tensile stressed tin deposits and some have been commercialized [22]. It is likely that with increased understanding of tin-whisker mechanisms and improvements in plating process technology, pure-tin finishes will be among the best options for producing a reliable, robust, cost-effective, Pb-free component finish.
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FIG. 21 SEM micrograph showing a sectional tin whisker and the region directly below it prepared using a focused ion beam (FIB). The indicated features are similar to those noted in Fig. 20.
B. Issues with Various Lead-Free Finishes Tin–bismuth (Sn–Bi) poses us a potential reliability risk owing to bismuth’s incompatibility with Sn–Pb solder. The presence of Bi in sufficient quantities can cause the formation of a low-meltingpoint Sn–Bi–Pb phase. A 52Bi–30Pb–18Sn ternary alloy forms, which has a melting point of 96jC. The presence of the low-melting phase has severe effects on solder joint reliability, as thermal cycling of through-hole devices can result in a phenomenon known as ‘‘fillet lifting’’ (see Chapter 17 for a detailed discussion). There is a decrease in solder joint strength with increasing Bi content in the alloy, as shown in Fig. 22. For these reasons, Bi-containing Pb-free solders and component finishes are not considered ideal long-term Pb-free solutions. Tin–silver (Sn–Ag) has no major reliability concerns in addition to the tin-whisker issue. Tin–copper (Sn–Cu) is one example where the addition of an alloying agent to tin has been demonstrated to increase the risk of tin-whisker formation. Several studies [23,24] indicate that component finishes of Sn–Cu alloys containing low levels of Cu (<3–5%) significantly increase the propensity toward whisker formation. This represents a case where an assessment must be made of the benefits for utilizing a Sn–Cu finish for a particular application. Among these benefits are that copper additions to tin reduce the tendency for copper thieving (dissolution) from circuit features into the solder. This may be acceptable in a consumer product application, but perhaps not so for a high reliability application. Tin–zinc (Sn–Zn) poses a tin whisker risk and exhibits a propensity to oxidation, resulting in the formation of dross during soldering. It is therefore necessary to perform assembly operations in a nitrogen environment which, although technically feasible, adds to the cost. Inerting is discussed in Chapter 15.
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FIG. 22 The effect of bismuth (Bi) content on the melting point and pull strength of tin–bismuth (Sn– Bi) solder alloys.
Both Ni–Pd and Ni–Pd–Au suffer from two primary reliability issues: low ductility and corrosion on Alloy 42. The relatively low ductility of nickel and palladium coatings often results in a deposit cracking during a component trim and form operation. The cracks can expose underlying copper that can then oxidize, causing a significant loss in solderability performance of a component. The corrosion problem associated with Alloy 42, an alloy consisting of Ni, Fe, and Co, occurs as a result of a galvanic cell set-up due to the strong difference in electrochemical potential between Pd and Fe. The potential drives base material Fe ions to the surface where they are oxidized, thereby degrading the solderability. All component finishes listed are compatible with both Sn–Pb and Pb-free solder and form reliable solder joints with these solder materials, with the exception of Sn–Bi. In summary, Sn-whisker formation remains a concern with all Pb-free finishes except Ni–Pd (Au) as all highly Sn-rich coatings are potentially affected. Tin–bismuth (Sn–Bi) poses some concern due to its incompatibility with Sn–Pb solders if the concentration level is too high. Nickel–palladium (Ni–Pd) and its derivative coatings suffer from cracking and corrosion problems that Sn-based lead finishes are immune to.
VIII. SUMMARY None of the candidate finishes is completely without reliability, manufacturing, or cost concerns, so utilization of a particular finish will be based upon application. For example, from the data presented, Sn–Bi can, for all intents and purposes, be eliminated as a high-volume candidate because of its low supply situation, reliability concerns, incompatibility with Sn–Pb solder, and manufacturability issues. Sn–Ag is likely not a high-volume candidate due to cost and manufacturability issues. Sn–Cu, although mentioned as a potential wave solder candidate, suffers from reliability concerns (increased risk of whisker formation) and manufacturability issues. Sn–Zn has solderability and increased costs concerns. Ni–Pd, which does not have tinwhisker concerns, does have potential corrosion and thus reliability concerns and also costrelated issues, and therefore may not be a viable high-volume contender. One might conclude that pure tin is the leading high-volume candidate to replace Sn–Pb as a Pb-free component finish as it is abundant, cost-effective, and fairly easy to plate. However, the key concern in utilizing pure Sn as a Pb-free component finish is tin-whisker growth, as mentioned previously. However, there are efforts to mitigate and hopefully eliminate tin-whisker formation. The subject of tin-whiskers is discussed in more detail in Chapter 21.
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ACKNOWLEDGMENTS The author wishes to thank Dr. Yun Zhang of Cookson Electronics for useful discussions on tin whisker formation.
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Ormerod, D.H. Getting the Lead Out of the Surface Finish—What are the Options and Challenges ? Proc. Lead-Free Soldering and Interconnection Symposium; Binghamton, N.Y. Section 7, Dec. 1999. Houghton, B. What the EMS Provides Wants in a Board Finish, Proceedings of IPC Annual Meeting Technical Conference; New Orleans, LA, 502-2/3 pp. Schetty, R. Pb-Free Component Finishes, Proceedings of IPC Works ’99; Minneapolis, MN; S-02-3-1– S-02-3-8 pp. Brunno, N. Proc. IPC Printed Circuits Expo; 1999. Goosey, M. Implications of Higher Reflow Temperatures on Boards and Components, Proc. Lead-Free Soldering and Interconnection Symposium, Binghamton, NY Section 6. Furnanz, J., et al. Manufacturing and Reliability Evaluation Of Immersion Silver, Proc. IPC Works ’99; Minneapolis, MN, S-04-5-1–S-04-5-7 pp. Cullen, D. Immersion Silver Performance Results, Proc. IPC Works ’99; Minneapolis, MN, October. 1999; S-04-7-1–S-04-7-16 pp. Abbot, D., et al. Palladium as a Lead Finish for Surface Mount Integrated Circuit Packages. IEEE Trans. Components, Hybrids, Manuf. Technol. Sept. 1991, 14 (3), 567. Abbott, D. Lead-Free Component Lead Finishes, Proc. Lead-Free Soldering and Interconnection Symposium; Binghamton, NY; Section 9, Dec. 1999. Schetty, R. Pb-Free Component Finishes, Proceedings of IPC Works Pb-Free Technical Conference; Minneapolis, MN, Oct. 1999; 48 pp. Schetty, R. Pb-Free Component Finishes, Proceedings of AESF SUR/FIN Technical Conference; Chicago, IL, June 2000; 6–7. Hunt, C.; Lea, D. Solderability of Lead-Free Alloys, Proceedings of APEX Technical Conference; San Diego, CA, Jan. 2000; p-MT2/3-2. Hunsicker, H.Y.; Kenspf, L.W. Growth of Whiskers on Tin-Aluminum Bearings. Quart. Trans. SAE 1947, I, 6. Hawkins, D.T. Metal Whiskers, 1945–1975. Bell Labs internal document, a comprehensive collection of 886 references on metal whiskers. Lee, B.Z.; Lee, D.N. Spontaneous Growth Mechanism of Tin Whiskers. Acta Mater. Oct. 1998, 46 (10), 3701. Xu, C., et al. Understanding Whisker Formation—Driving Force for the Tin Whisker Formation, Proceedings of APEX 2002 Technical Conference; Long Beach, CA, Jan. 2002; 506-2/2-4. Baudry, I.; Kerros, G. Focused Ion Beam in Microelectronic Packaging Applications. Soldertec J. September 2001, 3–4. Zhang, Y., et al. Understanding Whisker Phenomenon, Proceedings of APEX 2002 Technical Conference; Long Beach, CA, Jan. 2002; 506-1/7-9. Zhang, Y., et al. Understanding Whisker Phenomenon, Proceedings of APEX 2002 Technical Conference; Long Beach, CA, Jan. 2002; 506-1/4. Schetty, R. Minimization of Tin Whisker Formation for Lead-Free Electronics Finishing, Proceedings of IPC Works Technical Conference, Miami, FL, Sept. 2002; 5-02-3/3-5. Xu, C., et al. Understanding Whisker Formation—Driving Force for the Tin Whisker Formation. Proceedings of APEX 2002 Technical Conference; Long Beach, CA, Jan. 2002; 506-2/4. Schetty, R. Tin Whisker Growth and the Metallurgical Properties of Electrodeposited Tin, Proceedings from IPC/JEDEC Pb-Free Technical Conference; San Jose, CA, May 2002; pp. 137–145. Moon, K.W., et al. The Formation of Whiskers on Electroplated Tin Containing Copper, Proceedings of 4th Pacific Rim Conference on Advanced Materials and Processing; Honolulu, Hawaii, Dec. 2001; 4 pp. Sriyarunya, A., et al. Lead-Free Plating Qualification, Proceedings of IPC/JEDEC Technical Conference; Taipei, Taiwan, Dec. 2002; 1 pp. Jordan, M. Dr. The Deposition of Tin and Its Alloys; Eugen G. Leuze Publishers: Salgan/Wurtt, Germany, 1995; 33 pp. Cullen, D. Going Beneath the Surface of Surface Finishes. CircuiTree Nov. 2002; Vol. 15, No. 11, 51. Hua, F., et al. Eutectic Sn–Bi as an Alternative Pb-Free Solder, Proceedings from IPC Works Technical Conference; Minneapolis, MN, Oct. 1999; 2 pp. O’Brien, G.; Milad, G. Standard Development Efforts of Electroless Nickel Immersion Gold IPC-1552, Proceedings of IPC Annual Meeting; Orlando, FL, Oct. 2001; S05-2-6.
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13 Formation of Intermetallic Compounds at Pb–Sn/Metal and Lead-Free/Metal Interfaces in Solder Joints Eric J. Cotts and Robert Kinyanjui State University of New York at Binghamton, Binghamton, New York, U.S.A.
Richard Chromik Lehigh University, Bethlehem, Pennsylvania, U.S.A.
Anis Zribi GE Global Research, Niskayuna, New York, U.S.A.
P. Borgesen Universal Instruments Corporation, Cleveland, Ohio, U.S.A.
I. INTRODUCTION Solder joints provide electrical continuity and mechanical stability for interconnects in electronic packages. Intermetallic compounds (IMCs) directly influence solder joint properties. An understanding of the mechanisms of the formation of intermetallic compounds in solder joints is critical to understanding the behavior of interconnections. Intermetallic compound formation can profoundly change the microstructure of solder joints, and therefore their mechanical properties. Factors such as grain size, impurity concentration, secondary-phase precipitates, and dislocation density affect the movement of dislocations, as well as grain growth, in solder joints. These processes determine the mechanical behavior of solder joints, since many deformation processes depend on dislocation growth or on grain boundary sliding. Intermetallic compounds can form in the bulk solder and at the solder/ metallization interfaces of solder joints. Intermetallic compound precipitates in bulk solder can affect dislocation movement and grain growth, and thus mechanical properties. Some IMCs are very brittle, causing a region of weakness, which can result in solder joint failure. Adhesion between IMCs can also be poor, causing solder joint failure. Microstructure affects the mechanical properties of solder joints, and IMCs play an important role in solder joint microstructure [1–3]. Although solder joints are found with various geometries, for the sake of discussion a simple geometry consisting of two essentially planar metallizations joined by solder was selected to illustrate the concept. Whereas the metallizations may be only 10 Am in thickness, solder reactions generally do not consume the metallization material (exceptions include thin, passiva-
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FIG. 1 A sketch (not to scale) of a typical solder joint in microelectronics—two planar terminal metallization pads joined by the solder bulk or matrix, with intermetallic compounds formed at the metallization/solder matrix interfaces. The vertical dimension can vary from approximately 100 Am to 1 mm.
tion layers, such as Au). Thus, in many instances reactions at metallization/solder interfaces can be considered without loss of generality. In Fig. 1 the solder/metallization interfaces are labeled, and the bulk solder is referred to as the solder matrix. The continual reduction in the size of microelectronic components (and so too, their interconnections) along with changes in metallurgies makes the formation of functionally adequate solder joints more challenging, even for the well-studied Pb–Sn solder system. The use of surface finishes such as Au or Pd can result in complex situations. Some metallization deposition methods have changed the course of IMC formation. Examination of these effects provides a good background for the changes brought on by the use of Pb-free solders.
A. Lead–Tin System Interactions between Pb–Sn solder and common metallizations such as Cu or Ni have been well characterized [4–13]. Studies of the growth of IMCs have been conducted for several reflow procedures, annealing schedules, and geometries. Qualitative and quantitative models have been constructed. A good understanding has evolved for Pb–Sn solder/Cu or Ni metallization reactions in bulk geometries. A Pb–Sn solder joint is inherently unstable in that Sn in solder and metallization elements combine to lower their free energy. This is an important factor in the evolution of solder joints; a driving force exists for the formation of Sn-based IMCs. The Cu–Sn, Ni–Sn, Au–Sn, and Pd–Sn phase diagrams [14] presented in Figs. 2–5, respectively, provide important examples of these IMCs and their range of stabilities. On the other hand, Pb is stable with respect to compound formation with Ni or Cu. In considering the formation of IMCs in Pb–Sn solder/metal joints, Pb is generally considered to be inert. Interreactions at Pb–Sn/metallization interfaces generally yield one or more binary Sn–metal (M) intermetallic compound(s), with more complex ternary phases forming under certain circumstances. Common metallizations include Cu and Ni, while Au, and sometimes Pd, is used as a surface finish on Ni. Gold dissolves quickly in the solder matrix during reflow. Sn–M compounds form during reflow and continue to grow during annealing. Intermetallic compounds formed at solder/metallization interfaces are important electrical and mechanical links in solder joints. Intermetallic compounds may also be found in bulk of solder joints and are either an inherent part of the solder, or they are formed during soldering. The formation of IMCs occurs at solder/metal interfaces when molten solder contacts a metallization surface and continues, however slowly, throughout the lifetime of a solder joint (assuming a sufficient supply of metals). The initial formation of one or more IMCs at a solder/
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FIG. 2 Equilibrium phase diagram for the Cu–Sn system. (From Ref. 14.)
metal interface during reflow is generally the most prodigious formation process. Besides the initial growth of an IMC being generally the fastest, temperatures are of course higher during reflow, and the solder is in the liquid state, both of which facilitate the reaction process. For instance, a Cu6Sn5 layer can grow at a Pb–Sn/Cu interface during a reflow of approximately 10 sec at a temperature of 220jC to a thickness of approximately 2 Am [15], whereas annealing for an additional 150 hr at a temperature of 150jC only results in the growth of two more micrometers [9].
FIG. 3 The equilibrium phase diagram for the Ni–Sn system. (From Ref. 14.)
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FIG. 4 The equilibrium phase diagram for the Au–Sn system. (From Ref. 14.)
B. This Chapter The advent of Pb-free solders has had a profound effect on the metallurgy of solder interconnections [16–39]. The Pb in Pb–Sn solders has been replaced with relatively small amounts of other constituents (e.g., Cu or Ag) that form IMCs with Sn. These constituents, although present in small concentrations, diffuse rapidly in Sn and react with termination-pad metallizations. This chapter examines the effect of these changes on the formation and evolution of intermetallic compounds in solder joints. The chapter addresses several Pb-free solder systems among the hundreds proposed for use as solders for electronic packages [40]. Many of these alloys are Sn based. Some of them (for instance Sn–Bi and Sn–In alloys) are currently used in applications, while others have essentially
FIG. 5 The equilibrium phase diagram for the Pd–Sn system. (From Ref. 14.)
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never been applied. The focus is on eutectic and near-eutectic compositions of the Sn–Ag–Cu, Sn–Ag, and Sn–Cu systems. The formation of intermetallic compounds in solder joints during both reflow and subsequent annealing below the solidus temperature is also discussed. The classic Pb–Sn/metallization systems serve as a reference point [4–13]. In this context, the case of thermal cycling of solder joints of Cu/Ni/Au/Pb–Sn and the formation of Au–Ni–Sn intermetallic compounds at metallization interfaces is considered in detail [5,41–62]. The fast diffusion of Au controls the formation of Au–Ni–Sn alloys in this system [54–56]. In fact, some fundamental observations of the diffusion characteristics in Sn provide useful generalizations for all Sn-based solder systems, including Pb-free solders. Many Pb-free solders have near-eutectic compositions of Sn and various elements, often in ternary compositions. Those elements are often in relatively low concentrations, so the reactions between pure Sn and various metallizations are discussed as a basis for comparison. The formation of intermetallic compounds at Pb-free solder/metallization interfaces is discussed, and an attempt is made to understand the basic mechanisms of the growth processes and their relation to the reliability of interconnections.
II. FORMATION AND GROWTH OF INTERMEDIATE PHASES A. Solder Joint Structure The formation of solder interconnections in microelectronic packages involves the melting of solder in contact with a metal surface. The joining of the metals is facilitated by the presence of fluxing agents to reduce oxides on the metal surfaces, and the use of controlled (i.e., inert) atmospheres to prevent their formation during reflow operations. Termination pads are often coated with a surface finish. For instance, Ni is coated with approximately 0.1 Am of Au, or Cu is coated with an organic material referred to as an organic solder preservative (OSP). The intermetallic compounds formed in the solid metal/liquid solder diffusion couple also form in the solid state (i.e., at service temperatures below the solidus temperature) because of growth by solid-state diffusion.
B. Kinetics vs. Energetics Kinetics, rather than energetics, tends to dominate phase selection at interfaces in solder interconnections. This is reflected in the fact that the most Sn-rich alloys generally form first in metal–Sn systems [5,52,53]. Energetics, on the other hand, often favors the formation of other alloys. For instance, in Cu/Sn diffusion couples Cu6Sn5 is observed to form first, while in Pd/Sn diffusion couples PdSn4 is found to grow first [57,63]. The Pd–Sn alloy system contains seven intermediate alloys, which can form at room temperature (phase diagram, Fig. 5). In consideration of the enthalpy of formation [64,65] of these intermediate alloys as a function of Sn content (Fig. 6), energetics is seen to favor the formation of Pd-rich alloys while the most Sn-rich alloy, PdSn4, is the least energetically favored, but it is PdSn4 that forms first. The implication is that understanding the kinetics of formation of intermetallic compounds in solder systems enhances the ability to predict phase formation. 1. Effect of Crystal Structure An examination of solute diffusion coefficients in Sn [56] (Fig. 7) provides additional insight into the growth of Sn-rich alloys in some Sn/metal diffusion couples. It also provides an insight into the diffusion of constituents in some Pb-free solders, such as Sn–Ag–Cu [28,34,36]. Anomalously high rates of metal diffusion are observed at temperatures near the melting point of Sn. Similar averaged rates of interdiffusion are found in many Sn-rich alloys at similar temperatures. Notably, the diffusion of Pd in Sn is almost the same as the rate of interdiffusion in PdSn4, while the rate of interdiffusion in less Sn-rich Pd–Sn and Cu–Sn alloys is lower (Fig. 8). Actually, the structure of the PdSn4 alloy is quite similar to that of pure Sn. Fig. 9 illustrates how the PdSn4 structure, viewed along the [010] crystallographic direction, is nearly as open as the Sn structure
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FIG. 6 The effect of Sn content on the enthalpy of formation of Pd–Sn alloys. The most Sn-rich compound has the smallest enthalpy of formation; nevertheless, PdSn4, although not energetically favored, is observed to form first in Pd/Sn diffusion couples. (From Ref. 64.)
FIG. 7 A plot of solute diffusion coefficients in Sn for a number of constituents found in solder interconnections. The solid lines represent the temperature regions where the measurements were made, while the dashed lines are extrapolations. The point at 303 K for diffusion in Pd is an estimate [37,38]. The anomalously large values found near typical reflow temperatures help to explain some of the phenomena observed in solder/metal diffusion couples. (From Ref. 56.)
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FIG. 8 A plot of the logarithm of the averaged interdiffusion coefficient vs. the inverse temperature for a number of different systems. (From Refs. 37 and 38.)
along the [100] direction. The parallel planes of Sn atoms exhibit a similar degree of separation in both the Sn and PdSn4 structures. When the space between these planes is filled with Pd atoms, as in the PdSn2 structure (Fig. 10), the averaged interdiffusion constants are seen to decrease by several orders of magnitude in Fig. 11. Faster interstitial diffusion of metal atoms in Sn-rich environments explains both the higher values of the averaged interdiffusion coefficient in, and faster growth of, the most Sn-rich phase in the Pd–Sn system. It can also be seen from Fig. 7 that Ag and Cu diffuse rapidly in Sn. While these measurements are for single-crystal Sn at tracer diffusion levels, it is to be expected that these constituents in Sn–Ag–Cu Pb-free solder diffuse very rapidly in the solder matrix. For instance, Cu is observed to have a diffusion coefficient of approximately 3 107 cm2/sec at 150jC in the slow direction in single-crystal Sn [56]. If this number is used for the diffusion coefficient in polycrystalline Sn, then Cu atoms would only require approximately 100 sec to diffuse throughout a 50-Am-diameter solder ball. In fact, as reviewed in detail below, large Cu concentrations in Sn–Ag–Cu (SAC) alloys profoundly affect IMC formation.
FIG. 9 Illustrations of the crystal structures of (a) PdSn4 and (b) Sn. Tin atoms are shown as smaller octahedrons, while palladium atoms are shown as larger dodecahedrons.
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FIG. 10 An illustrated comparison of the structure of (a) PdSn2 and (b) PdSn4. It is evident that while PdSn4 contains Sn/Sn parallel planes (tin atoms are shown as small octahedrons, while palladium atoms are shown as dodecahedrons) as observed in Sn, in the PdSn2 structure the Sn/Sn planes are filled with Pd atoms. The parallel planes of Sn in PdSn4 apparently provide an easy diffusion path for Pd atoms in the growing PdSn4 phase, but in the PdSn2 compound such a diffusion path is not available.
As mentioned above, Sn is the major component of Pb-free solders. In addition, in Pb–Sn solders, Sn is the most active component in the formation of IMCs. Therefore, the formation of IMCs in Pb–Sn solder/metallization diffusion couples is considered first, as a basis for examination of Pb-free solder alloys. This treatment is followed by a discussion of the formation of Au0.5Ni0.5Sn4 compound in Pb–Sn solder joints, because the mechanisms for its formation are similar to the formation of ternary IMCs in some Pb-free solder joints.
FIG. 11 A plot of the logarithm of the averaged interdiffusion coefficient vs. inverse temperature times 1000. The two lines and the open symbols are measurements of the averaged interdiffusion coefficients in either PdSn4 or PdSn2, while the dotted lines are extrapolations. (From Ref. 37.)
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III. EUTECTIC SN–PB SOLDER ON STANDARD PACKAGING METALLIZATIONS A. On Copper Metallization The evolution of the microstructure in Pb–Sn solder joints has been examined thoroughly in the past [4–13]. The growth of intermetallic compounds in the Cu/Pb–Sn system is different above and below the melting temperature of the solder. The rate of formation of IMCs (primarily Cu6Sn5) is more than an order of magnitude greater above the liquidus than in the solid state. The growth kinetics is also different. These differences are thought to stem from the variation in the morphology of the growing phase. Below the solidus, Cu6Sn5 is observed to cover the Cu/Pb–Sn interface in a planar fashion, while above the liquidus temperature the alloy grows in a faceted or scalloped manner, with distinct grain boundaries between the facets. These grain boundaries are thought to directly affect the growth kinetics, providing short circuits for diffusion. 1. Growth Below the Solidus Temperature Several investigators examined the formation of Cu–Sn alloys above the liquidus [15,23,66–68]. For instance, during the reflow of Pb–Sn solder on Cu surfaces, Cu6Sn5 was observed to grow at a relatively prodigious rate at the solder/metal interface. At a temperature of 220jC, the mean radius, r, of Cu6Sn5 grains growing at a Pb–Sn/Ni interface was found to increase as r = (0.8t0.33) Am, where t is time in seconds [15]. That is to say, r was found to be 3 Am after approximately 60 sec. Careful investigation indicates that Cu3Sn forms during reflow as well, between the layer of Cu6Sn5 grains and the Cu, as would be expected. This layer is relatively thin, generally submicron in size, but subsequent heat treatment of solder joints below the solidus eventually leads to more evident growth of the Cu3Sn phase. The models for growth of Cu6Sn5 above the Sn liquidus take the morphology of the growing alloy into consideration. For instance, the model of Schaefer et al. [59] simplifies this geometry into one where all Cu6Sn5 grains are equiaxed, with essentially spherical tops and hexagonal bases of uniform size [Fig. 12(a)]. An actual series of Cu6Sn5 scallops formed at a Cu/Pb–Sn solder interface during reflow is shown in Fig. 12(b). By assuming that diffusion in the boundaries
FIG. 12 (a) A sketch of the geometry of the Cu6Sn5 grains and scallops, assumed by Schaeffer et al.’s model. (From Ref. 59.) (b) An electron micrograph that reveals the formation of Cu6Sn5, scallops at a Pb–Sn/Cu interface upon reflow. This SnPb/Cu solder joint was reflowed at 200jC for 10 min, and then etched. (From Ref. 15.)
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between the grains dominates the growth process, and that there is one dominant diffusing species, Cu, Schaefer et al. developed a theoretical expression for the time dependence of the average layer thickness, x, finding x to be proportional to t0.33. The experimental results of Schaefer et al. showed slower time dependence than t0.33. By assuming that the average grainboundary diffusion distance increases with x2, the model was modified to a t0.25 time dependence in agreement with the experimental results [59]. Modeling efforts by Kim and Tu [15] included consideration of grain coarsening and volume diffusion processes. These investigators included a combination of the interfacial reaction between Cu and Sn(L) and scallop ripening, and found a t0.33 time dependence. They also observed good agreement between their experimental data and model predictions, as shown in Fig. 13 [15]. The time dependence for the growth of Cu6Sn5 between Cu and liquid Pb–Sn (Fig. 13) does not agree with the experimental observation of Schaefer et al., but does agree with their simple model [59]. 2. Growth Below the Solidus Temperature In the solid state, the growth of solder alloys is generally diffusion limited. Choi et al. [9] examined the thickness of Cu6Sn5 and Cu3Sn IMCs during growth at different temperatures in the solid state. They found a diffusion-limited growth regime for the period they investigated; that is, the square of the intermetallic compound thickness, x, was linearly proportional to time, t, x2 = kt. The growth coefficients were found to be similar to previous results [69]. As might be expected, growth rates were found to be distinctly lower in the solid state compared to IMCs growing where liquid solder is in contact with solid Cu. For instance, at a temperature near 150jC, the value of k for the growth of Cu6Sn5 was found to be 5 1014 cm2/sec. The activation energy for this growth process was reported to be 111 kJ/mol. Vianco et al. [70] also examined this system and their work also indicated that the growth of the intermetallic layers was diffusion limited, with a value for k for the combined IMCs of 6 1013 cm2/sec at 170jC.
B. Pb–Sn Solder on Ni Metallizations Most reports consistently show that the reflow and subsequent heat treatment of Pb–Sn solder/Ni joints lead to the formation and growth of Ni3Sn4 [7,8,10,12,71–74]. The rate of growth of Ni3Sn4 in Pb–Sn/Ni systems has been reported to be less than half that observed for Cu6Sn5 in Pb–Sn/Cu
FIG. 13 A plot that displays the mean radius of Cu6Sn5 scallops formed at a Pb–Sn/Cu interface vs. the cube root of annealing time at three different reflow temperatures: 200jC, 220jC, and 240jC. (From Ref. 15.)
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systems [72]. While Cu6Sn5 grows at a faster rate than Ni3Sn4, both of these phases grow the most rapidly in their respective systems. In fact, kinetics rather than energetics dominate phase selection in these solder/metal systems. Several studies addressing the formation of solder alloys in Ni/Pb–Sn diffusion couples have been performed at temperatures above the liquidus [7,8,10,71–74]. Early during the reaction, scallops are found at the Ni interface, with grooves between the scallops that extend to the Ni interface. For instance, in diffusion couples with eutectic Pb–Sn and electroplated Ni/Pd metallization, Ni3Sn4 scallops were observed [7,8] to form on the Ni surface and to coarsen over time. Kinetic data for the radial growth of the scallops and for the increase in the average thickness of the Ni3Sn4 layer were computed. It was determined that the data fit well as an empirical relation between scallop radius, r, and time, r = Bt0.33, with B a proportionality factor dependent on temperature. There are some differences in the morphology of the growing Ni3Sn4 alloy compared to the growth of Cu6Sn5 in the Cu/Sn system. After prolonged growth, the Ni3Sn4/Ni interface is generally found to be essentially smooth. A planar layer of Ni3Sn4 between the Ni3Sn4 scallops and the Ni substrate could slow the growth of the IMC. This is based on the consideration that the most salient conclusion of the theories of growth of Cu6Sn5 at Cu/liquid solder interfaces was that grooves down almost to the Cu metallization (with a thin layer of Cu3Sn separating the Cu6Sn5 scallops and the Cu) result in high growth rates. The presence of a planar layer of Ni3Sn4 apparently affects the growth rate at Ni/IMC interfaces. If additional elements are present in the metallization in significant quantities, such as thick Au overlayers, or P incorporated in the Ni during electroless deposition, IMCs may form in addition to Ni3Sn4. For instance, as discussed in detail in Sec. III.C.4, Au0.5Ni0.5Sn4 forms at the Ni3Sn4/solder interface if annealed below the solidus temperature. The phase Ni3P has been observed to form between electroless Ni and Ni3Sn4 layers [12]. Both of these IMCs (Ni3P and Ni3Sn4) affect solder joint reliability.
C. Gold in Pb–Sn Solder Joints 1. Rapid Dissolution The formation of some phases in solder alloys can be the cause of adverse reliability behaviors in solder joints. Interconnections consisting of Pb–Sn soldered to Au/Ni terminal pads provide an important example of how the fast diffusion of metal atoms in Sn results in the growth of intermediate alloys that dramatically affect interconnection reliability. When eutectic Sn–Pb solder is initially reflowed on an Au/Ni surface, the thin (generally submicron) coating of Au rapidly dissolves into the molten Sn–Pb solder, whereas Ni3Sn4 is formed at the Ni/Sn–Pb solder interface (Fig. 14).
FIG. 14 An electron microscope image of a cross section of a Ni/Pb–Sn solder joint after reflow. The Pb–Sn solder is evident on the bottom section of the figure, while the Ni is the dark section at the top of the figure. A thin interfacial layer of Ni3Sn4 is observed between the solder and the Ni. The Au flash layer on the Ni dissolved into the Pb–Sn solder.
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2. Effect of Gold (Au) Concentration In the case of flip chips reflowed on chip carriers with a relatively thick Au layer, (e.g., some electrolytically deposited layers), the dissolution of Au upon reflow may lead to an average volume concentration of 2% to 3% Au in a solder joint, resulting in a significant reduction in its fatigue resistance. In fact, this has been observed to affect the reliability of flip chip assemblies in spite of underfilling. For example, Au–Sn intermetallics have been shown [41 42] to degrade the thermal fatigue life of Pb–Sn solder joints when present in concentrations of 1.5 to 5 at.%. In these investigations, AuSn4 was observed as a precipitate dispersed throughout the solder. It has been generally asserted that Au concentrations of greater than 1.5 at.% in Pb–Sn solder joints causes a severe degradation in fatigue resistance [43]. 3. Stacked Intermediate Compound Layers The present example concerns a failure mechanism due to a ternary Au solder phase that manifests itself at Au concentrations as low as 0.1 at.%. A small concentration of Au has also been reported to cause premature mechanical failures in ball grid array (BGA) Cu/Ni/Au/Pb–Sn solder joints [43–46]. Gold has a high solubility in molten Pb–Sn solder, so it quickly dissolves into the molten solder during reflow [46]. The final solder joint microstructure and composition depend on the initial thickness of Au, the reflow profile, and subsequent thermal aging. Mei et al. observed that AuSn4 nucleated in Pb–Sn solder after reflow [43]. They noted that upon thermal aging at 150jC, AuSn4 migrated from the bulk solder to the interface adjacent to the preexisting Ni3Sn4 intermetallic layer. These investigators reported that the AuSn4 had a detrimental effect on the bending strength of BGA assemblies and exhibited a considerable reduction in failure resistance. Poor adhesion between the Ni3Sn4 and AuSn4 phases was reported to be responsible for the observed deterioration in mechanical integrity of the solder joints. 4. Effect of Thermal Aging Additional studies [34,75–78] of this phenomenon showed that Au atoms migrated to the Ni3Sn4/ Pb–Sn interface to combine with Ni and Sn, forming a Ni0.5Au0.5Sn4 alloy (Figs. 15, 16). In one study [34,76], printed circuit board substrates consisting of Cu features overplated with Ni/Au metallizations were used, with individual Ni pads (islands) that were approximately 12 Am thick and 0.5 mm in diameter. Eutectic Sn–Pb solder spheres were reflowed on the pads at a maximum temperature of 209jC for 45 sec above the melting point of the eutectic solder (183jC). The samples were then annealed in argon at 150jC for various times (0, 0.5, 1, 4, 9, 40, 150, and 450 hr). Optical and electron microscopy were used to examine cross-sectioned samples in which Cu, Ni, Ni3Sn4, and the Sn-rich and Pb-rich phases were identified in all samples by wavelength dispersive spectrometry (WDS) spectra, with maps and line scans acquired at various locations. a. Growth of Au0.5Ni0.5Sn4 is Au Diffusion Controlled. In general, for these BGA packages, the concentration of Au in the bulk solder after reflow was lower than the solubility limit of Au in molten eutectic Sn–Pb solder (approximately 4 at.%). Therefore, the Au completely dissolved into the molten solder. An examination of two electrolytic solder alloys after reflow using WDS spectra and maps indicated that Au remained well dispersed in a solder ball upon cooling from reflow (Fig. 15) [34]. Thus, the formation of the Au0.5Ni0.5Sn4 alloy occurred by solid-state diffusion during the subsequent annealing at 150jC conducted as part of the study (Fig. 15). During thermal aging at 150jC, the ternary phase, Au0.5Ni0.5Sn4 (Fig. 16), was observed to grow at the solder/Ni3Sn4 interface during annealing at a rate dependent upon the Au concentration in the eutectic Sn–Pb solder after reflow. Fig. 17 provides a comparison of the thickness of the Au0.5Ni0.5Sn4 layer during annealing of Sn–Pb/Au/Ni/Cu solder joints at 150jC together with data by Minor and Morris [77]. It is apparent that the growth rate of Au0.5Ni0.5Sn4 observed in the study by Minor and Morris [77] was approximately two times greater than the growth rate measured by Zribi et al. [34]. This difference is due to the rate-controlling mechanism for the Au0.5Ni0.5Sn4 formation. Because the initial Au concentration in the solder joints investigated by Minor et al. (0.2 at.%) is twice that in the Zribi et al. study, the results are consistent with the hypothesis that the Au0.5Ni0.5Sn4 growth is controlled by Au diffusion.
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FIG. 15 A sketch of the evolution of the microstructure of Cu/Ni/Au/Pb–Sn solder joints, focusing on the formation of Au0.5Ni0.5Sn4 at the Pb–Sn/Ni3Sn4 interface during post reflow annealing. (a) Pb– Sn solder and Cu/Ni/Au metallization before reflow. (b) Solder joint after reflow reflecting dissolution of Au into the solder matrix, including formation of AuSn4 upon cooling, and formation of Ni3Sn4 at the Pb–Sn solder/Ni interface. (c) Solder joint after postreflow annealing in the solid state (e.g., 150jC). Au0.5Ni0.5Sn4 has formed at the Pb–Sn/Ni3Sn4 interface.
b. Mechanism of (Ni,Au)Sn4 Formation. The observation of the growth of Au0.5Ni0.5Sn4 at the Ni/Ni3Sn4 interface is consistent with previous observations of Sn-rich phases growing at solder joint interfaces. Considering the rapid diffusion of Au in Sn and Pb, a ready supply of Au is available at the Ni3Sn4/solder interface. Ni0.5Au0.5Sn4 is the most Sn-rich phase in the Ni–Au–Sn alloy system [47]. Furthermore, the structure of the Au0.5Ni0.5Sn4 alloy was found to be similar to PdSn4 [62]. It is known that Ni atoms substitute for Au atoms in the AuSn4 crystal structure to
FIG. 16 Scanning electron microscopy backscattered electron image showing Au0.5Ni0.5Sn4 and Ni3Sn4 at a Pb–Sn solder/Ni interface. The sample was annealed for 150 hr at a temperature of 150jC. (From Ref. 34.)
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FIG. 17 A plot of the measured thickness of the intermetallic alloy, Au0.5Ni0.5Sn4 at the Pb–Sn solder/Ni interface vs. time. (From Ref. 28.)
produce compounds of composition Au1xNixSn4,, where x < 0.5. The structure of these compounds can be considered isotypical with the pure AuSn4 phase (the PtSn4 structure type), with even a symmetry increase from Aba2 to Ccca observed [62]. This was determined via crystal structure refinement from powder data using the Rietveld method. Two alloys were examined, x = 0.25 and 0.50, yielding Au0.73Ni0.27Sn4 (space group Ccca, a = 6.448, b = 11.606, c = 6.441 A˚), and Au0.51Ni0.49Sn4 (space group Ccca, a = 6.424, b = 11.522, c = 6.384 A˚), respectively [62]. In the Zribi et al. study [34,76] most of the Au atoms diffuse distances of the order of the diameter of the solder ball before they could combine with Ni and Sn to form the intermediate alloy (Fig. 16). Still, the rapid rate of diffusion of Au in Sn (Fig. 7) allows this to occur, as does the relatively high rate of interdiffusion in the growing intermediate alloy. c. Growth of Au0.5Ni0.5 Sn4. The indication that the rate of formation of Au0.5Ni0.5Sn4 depends strongly on the Au concentration indicates that Au diffusion is the controlling mechanism of the growth of this intermetallic compound at micron thicknesses in Pb–Sn/Au/ Ni/Cu joints. This phenomenon also provides some insight into the behavior of Pb-free solder joints, where the constituents added to Sn (such as Cu) rapidly diffuse distances corresponding to the dimensions of a solder ball diameter and determine phase selection and kinetics for the solder intermediate alloy formation at the interface. GROWTH MODEL. A simple model was constructed by Zribi and Cotts [28] to estimate the growth thickness of Au0.5Ni0.5Sn4 for different geometries, Au metallization thicknesses, temperatures, and annealing times. The model assumes that Au is homogeneously distributed within a solder joint (hemisphere) upon reflow, and that all Au atoms that diffuse to the interface are immediately consumed to form Au0.5Ni0.5Sn4 (Fig. 16). In a further simplification, the diffusion constant for Au in Pb–Sn solder is assumed to be the same as the diffusion constant for Au in Sn. They generated the model by using the scaled diffusion Eq. (1) and solved for Au concentration in a two-dimensional, hemispherical domain representing the cross section of a solder sphere utilizing a version of Flex PDE [79]. ðD=L2 Þj2 u ¼ s1 BðuÞ=Bt
ð1Þ
where D is the diffusion coefficient of Au in Sn at the annealing temperature T, L is the diameter of a solder sphere measured upon reflow, s is the diffusion time scale, and u is the scaled concentration of Au, the concentration of Au in solder upon reflow. CALCULATED AND MEASURED GROWTH RESULTS. A plot of the calculated dimensionless thickness (the calculated thickness of the Au0.5Ni0.5Sn4 intermetallic alloy divided by the initial
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FIG. 18 A plot of the calculated dimensionless thickness (the calculated thickness of the Au0.5Ni0.5Sn4 intermetallic alloy divided by the initial Au thickness) vs. dimensionless time (time divided by a characteristic time). A curve (solid line) was fitted to the points calculated with the simple model: [(xAu0.5Ni0.5Sn4 /xAu)fit = 9(1 exp( 17.4t/si))]. (From Ref. 28.)
FIG. 19 A plot of the dimensionless thickness (the thickness of the Au0.5Ni0.5Sn4 intermetallic alloy divided by the initial Au thickness) vs. dimensionless time (time divided by a characteristic time). (From Ref. 28.)
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Au thickness) vs. dimensionless time (time divided by a characteristic time (the diffusion time constant)) is provided in Fig. 18. This plot is based on the model whose detailed basis is given in the Appendix. In Fig. 19 the nondimensional experimentally measured thicknesses of the Au0.5Ni0.5Sn4 alloy are plotted utilizing data from three investigators [32,34,77] along with corresponding simulated data. The simulated data presented in Figs. 18 and 19 are obtained directly from the diffusion calculations with no adjusted parameters. The relatively good agreement between experimental and corresponding simulated data again suggests that Au diffusion is the growth-controlling step in the formation of Au0.5Ni0.5Sn4.
IV. GROWTH OF INTERMEDIATE PHASES IN Pb-FREE SOLDER ALLOYS A. Composition and Multielement Compounds Tin is the main constituent for most Pb-free solders of interest (e.g., eutectic Sn–Cu, Sn–Ag, and Sn–Ag–Cu) as replacements for eutectic Sn–Pb solder. In fact, Sn is found at concentrations greater than 90 at.% in all of these eutectic solders. Relatively small amounts of additional elements such as Cu or Ag are added to Sn to reduce the melting point of the solder alloy and improve its mechanical and wetting properties [16–40]. As some of these elements form IMCs with Sn (e.g., Cu6Sn5 or Ag3Sn), the microstructure of the solder matrix is different from eutectic Sn–Pb. In addition to these alloying metals present as part of a Pb-free solder, others are added during processing such as the partial dissolution of metallizations (Cu, Ni, or Au) during soldering, further increasing the complexity of the system. Furthermore, many of the constituents (e.g., Cu, Au, etc.) found in Pb-free solders, such as the Sn–Ag–Cu system, diffuse at anomalously fast rates in Sn [56], as noted previously (Fig. 7). The availability and mobility of all these constituents considerably increases the likelihood of the growth of IMCs. This includes IMCs that contain three or four elements that may grow in Pb-free solder joints, in a fashion similar to the growth of Au0.5Ni0.5Sn4 in Pb–Sn [34].
B. A Model for Sn/M Systems A significant body of work concerning the formation of intermetallic compounds at Sn/M (M=Ni or Cu) interfaces at temperatures above the melting temperature of Sn has been reported in the literature. Bader et al. [80] found that at temperatures between 513 K (240jC) and 603 K (330jC), Cu6Sn5 and Cu3Sn grew simultaneously, with Cu6Sn5,, the more Sn-rich phase, growing at a much faster rate than Cu3Sn. Intermetallic compound formation in Pb-free systems during reflow was found to be similar to Pb–Sn/M solder interconnections, with Cu6Sn5 growing in a scalloped morphology. The kinetics observed is perhaps best described as the average thickness proportional to the cube root of time. Simultaneous grain-coarsening processes and standard diffusion processes occur through the solid Cu6Sn5. Studies show that Cu6Sn5 forms at Cu/Sn interfaces, with Cu3Sn subsequently growing between the Cu6Sn5 phase and Cu metal. In Ni/Sn diffusion couples, Ni3Sn4 has been observed to grow at the Ni/Sn interface. These phase selections are similar to those observed in Pb–Sn/M diffusion couples. Since Pb-free solders consist primarily of Sn, the behavior of Sn/M diffusion couples provides a basis for understanding intermetallic compound formation in Pb-free solder/M solder joints. In a study of the Cu–Sn system using differential scanning calorimetry (DSC) measurements to study the growth of Cu3Sn from Cu/Cu6Sn5 thin films, it was determined that a diffusionlimited growth regime existed after the initial nucleation of the Cu3Sn phase [63]. In another study [81] that used an electron probe microanalysis on quenched bulk samples after isothermally annealing them in an Ar atmosphere, the growth of Cu6Sn5 and Cu3Sn for temperatures between 170j and 220jC was found to be parabolic, as was determined in a similar study by Mei et al. [82]. Vianco et al. [83] also carried out similar experiments with Cu/Sn and Cu/63Sn–37Pb diffusion couples at temperatures between 30j and 205jC and found that most samples followed parabolic or slightly subparabolic growth laws (time exponent = 0.5 or 0.42, respectively).
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Reactions have also been examined in Ni/Sn diffusion couples. For instance, in Ni/Sn diffusion couples with Sn layers on the order of 3 Am thick, whiskers and scallops were observed to form simultaneously with a planar Ni3Sn4 layer. A Ni3Sn4 layer was observed to form first in a study on Ni/Sn(L) diffusion couples [80]. Further growth was in the form of Ni3Sn2 scallops. Gur and Bamberger [60] concluded that a planar layer of Ni3Sn4 forms by solid-state diffusion between Ni3Sn4 scallops and the Ni substrate, ultimately slowing the growth of the IMC.
C. Formation of Intermetallic Compounds in Pb-Free Solder Systems The formation of IMCs in Pb-free solder systems is in many respects reminiscent of those observed in Pb–Sn, with several intriguing added complications. In Pb-free solders such as Sn– Ag–Cu, the Cu and Ag additives form IMCs with Sn. These elements also diffuse rapidly in Sn, thus a high flux of these constituents is available for otherwise favorable reactions, such as the formation of ternary IMCs at metallization interfaces. The evolution of the microstructure of Pbfree solder joints during reflow, cooling, and subsequent annealing has been shown to be a complex subject. As far as intermetallic compound formation and growth at metallization interfaces are concerned, Sn–Ag–Cu solder alloys were found to behave similar to eutectic Sn–Pb solder on Cu substrates. In contrast, distinct differences were observed on Ni surfaces between the behavior of Sn–Ag–Cu and Sn–Pb solder. 1. Cu–Sn Intermetallic Phases in Sn–Ag–Cu Alloys Reflow of Sn–Ag–Cu solder on Cu substrates yielded results quite similar to Sn on Cu, or Pb–Sn on Cu. Fig. 20 is a scanning electron microscopy (SEM) image of Sn–4.7Ag–1.7Cu (Sn–5.1Ag– 3.1Cu in atomic percent) solder/Cu interface. WDS analysis indicated the growth of Cu6Sn5, similar to Pb–Sn/Cu and Sn/Cu interconnection interfaces. In addition, a layer of Cu3Sn had already formed between the Cu6Sn5 layer and Cu substrate during the reflow process. The average, total layer thickness was measured to be 2 Am. The morphology of the Cu6Sn5/Cu3Sn duo layer is similar to that observed in Pb–Sn/Cu joints [84]. Also visible in the image are distinct dark regions on the order of 2 to 10 Am (e.g., A in Fig. 20) in size, identified by WDS as Cu6Sn5, and lighter regions of similar size (e.g., B in Fig. 20)
FIG. 20 Scanning electron microscope backscattered electron image of a cross-sectioned sample made by reflowing Sn–4.7Ag–1.7Cu (Sn–5.1Ag–3.1Cu in atomic percent) on Cu at 230jC for 60 sec. The black phase at the bottom is the Cu substrate, the dark gray phase at the interface is Cu3Sn, the lighter gray phase on top of it is Cu6Sn5, and the brightest upper part of the picture shows the solder with fine Ag3Sn precipitates in the middle and a coarse precipitate on the left side (B). The picture also displays a coarse Cu6Sn5 precipitate (A) close to the interface on the right side. (From Ref. 29.)
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identified as Ag3Sn. Similar regions were found in the solder before reflow and are associated with the relatively high Cu and Ag content of this particular solder, causing the precipitation of relatively large quantities of intermetallic compounds in accordance with equilibrium requirements. The growth in the solid state of Cu–Sn IMCs at SAC/Cu interfaces has been examined by several researchers. In Fig. 21, measurements from one study of the average thickness of the combined Cu6Sn5 and Cu3Sn phases are plotted as a function of time as solid circles, for annealing at a temperature of 150jC [84]. The data correspond reasonably well to diffusionlimited growth behavior. The rate of growth of these combined phases is of similar magnitude to that previously observed in Cu/Sn and Cu/Pb–Sn diffusion couples [81,84]. 2. Ni–Sn Intermetallic Phases in Sn–Ag–Cu Systems Bulk samples of Sn–4.7Ag–1.7Cu solder reflowed on pure Ni substrates were observed by Zribi et al. [36] to exhibit results distinctly different from Pb–Sn/Ni or Sn/Ni solder joints. Recall that in both Pb–Sn/Ni and Sn/Ni solder joints, Ni3Sn4 was observed to grow first. In contrast, Cu–Ni–Sn compounds are observed to form at Sn–Ag–Cu/Ni interfaces. For instance, Fig. 22 is an SEM image of a Sn–4.7Ag–1.7Cu (Sn–5.1Ag–3.1Cu in atomic percent) solder/Ni interface, where WDS analysis identified the composition of the growing phase as CuxNiySn.45, where the Cu concentration x varied between 44 and 53 at.%, and the corresponding Ni concentration y between 10 and 1 at.%, respectively. These compositions are consistent with the stoichiometry of the compound, (Cu,Ni)6Sn5 [36].
D. Intermediate Phases in the Cu–Ni–Sn Ternary System While both the Cu–Sn and Ni–Sn phase diagrams have been well characterized, less information is available for the ternary phase diagram of the Cu–Ni–Sn system. A section of the Cu– Ni–Sn ternary phase diagram at 235jC (based on experimental data and thermodynamic modeling) provides insight into phase formation in SAC/Ni solder joints [85]. The (Cu,Ni)6Sn5 and (Ni,Cu)3Sn4 compounds are presented as narrow-composition-range compounds in the diagram, which extends the domain of the respective binary Cu6Sn5 and Ni3Sn4 compounds to
FIG. 21 Growth of intermetallic compounds at interfaces of different samples after thermal annealing at 150jC. n The average thickness of the Ni3Sn4 layer at the Sn/Ni interface. . The average thickness of the Cu6Sn5 layer at the Sn–4.7Ag–1.7Cu (Sn–5.1Ag–3.1Cu in atomic percent)/Cu interface. o The average thickness of the (Cu,Ni)6Sn5 at the Sn–3.5Ag–1.0Cu (Sn–3.8Ag–1.85Cu in atomic percent)/Ni interface. (From Ref. 29.)
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FIG. 22 Scanning electron microscope backscattered electron image of a cross-sectioned sample made by reflowing Sn–4.7Ag–1.7Cu (Sn–5.1Ag–3.1Cu in atomic percent) on Ni at 230jC for 60 sec and etched in 20% nitric acid and 80% ethanol by volume. The black phase at the bottom is the Ni substrate, the dark gray phase at the interface is (Cu,Ni)6Sn5, and the lighter gray phase on top of it is Ag3Sn. (From Ref. 29.)
a ternary domain. The Cu–Ni–Sn phase diagram also displays a large two-phase region between (Cu,Ni)6Sn5 and the Cu–Ni solid solution, and a three-phase region between (Cu,Ni)6Sn5, (Ni,Cu)3Sn4, and the Sn–Cu–Ni solid solution. These observations support the idea of a substitutional mechanism where atoms such as (Cu and Ni) and (Ni and Au) can substitute for each other in their binary compounds with Sn. This mechanism was investigated in a study which focused on the Au–Ni–Sn system, where the Au0.5Ni0.5Sn4 intermetallic compound is formed by the substitution of Au for Ni atoms in the AuSn4 lattice [24,28]. Thus, it was concluded [29] that the phase observed to form at SAC/Ni interfaces does indeed correspond to (Cu,Ni)6Sn5. The rate and extent of growth of (CuNi)6Sn5 was determined to depend upon the thickness of the SAC solder. With a relatively large supply of SAC solder, the growth of this compound is prodigious, with a measured layer thickness of approximately 2 Am after a reflow of 60 sec at a temperature of approximately 230jC. The morphology of the layer was found to be somewhat similar to that observed in Pb–Sn/Cu joints, with evidence of scalloping [36]. The effect of a limited supply of SAC solder is discussed in Sec. IV.E. The thickness of the intermetallic layer was monitored over the annealing time at a temperature of 150jC. The average thickness of the (Cu,Ni)6Sn5 phase is plotted (open circles) in Fig. 21, along with data (closed circles) for the thickness of Cu6Sn5 in the Cu/SAC diffusion couple. As can be seen from the figure, the growth rates of the (Cu,Ni)6Sn5 and Cu6Sn5 phases were found to be similar, in this case where a large supply of SAC solder was available. After 20 hr of annealing the average thickness of the (Cu,Ni)6Sn5 layer was 4.5 Am, indicating a growth rate distinctly higher than the growth rate of Ni3Sn4 in Ni/Sn diffusion couples. Data (closed squares) for the growth of Ni3Sn4 as a function of time at a temperature of 150jC in Ni/Sn diffusion couples are provided in Fig. 21 for comparison. The average thickness of the Ni3Sn4 layer was 1.7 Am after annealing for 17 h [36]. This observation is consistent with the concept that kinetics rather than energetics generally dominates phase selection at solder/metal interfaces, i.e., faster growing phases grow first. Similar to the previous observation that Cu6Sn5 grows faster than Ni3Sn4, it is observed that when a supply of Cu is present, (Cu,Ni)6Sn5 grows instead of Ni3Sn4, at a rate similar to Cu6Sn5. That the rate of growth of (Cu,Ni)6Sn5 is similar to Cu6Sn5 is also an indication that the rate of Cu diffusion through the bulk solder to the interface does not appreciably slow the rate of formation of (Cu,Ni)6Sn5.
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E. Intermediate-Phase Studies in 95.9Sn–3.4Ag–0.7Cu/Metal Pad Systems The formation of intermetallic compounds in small solder joints was also examined [36]. The low-magnification electron microscope image of a cross section in Fig. 23 provides a typical geometry of such joints. A rectangular Si die is located at the top of the image. The Sn–Ag–Cu solder ball [Sn–3.5Ag–1.0Cu (Sn–3.8Ag–1.85Cu in atomic percent) in this case] connects the die to the chip carrier consisting of a Cu trace plated with Ni and a thin layer (about 100 nm) of immersion Au. In one study [29] the formation of intermediate alloys in Sn–3.4Ag–0.7Cu/metal systems was investigated for Ni and Cu metallization (with the same die and Ni–V die metallization). In producing these samples, a Cu–Ag–Sn solder paste was printed onto Ni–V die terminal pads and reflowed. The resulting solder bumps were fluxed and reflowed a second time in order to attach them to an OSP-coated Cu metallization or Ni/Au/Cu metallization on a chip carrier. The chips were reflowed under standard industrial conditions. A second reflow was conducted to attach the solder to either a Ni or a Cu metallization. This reflow consisted of peak temperatures between 234j and 250jC, and times above the liquidus temperature ranging between 50 and 80 sec. 1. Reactions with Cu Pads In the case of Cu pads, Cu6Sn5 was observed to form at the Sn–3.4Ag–0.7Cu/Cu interface. Fig. 24 provides a view of the interface formed during reflow conditions of 238jC peak temperature and a time above the liquidus of approximately 70 sec, which reveals growth of a 2-Am-thick layer of Cu6Sn5. The layer morphology follows the interface morphology quite well, although some broad scalloping is observed. The Cu6Sn5 phase is the same as observed at Sn/Cu and Pb–Sn/Cu interfaces. The thickness of the Cu6Sn5 layer was similar in magnitude to previous measurements in Sn/Cu systems, with an indication that the growth is more prolific in these SAC/Cu diffusion couples. The Cu–Sn intermetallic alloy thicknesses measured by other investigators in systems such as Pb–Sn/Cu (reflowed at a higher temperature of 255jC for similar times) are approximately 1 Am in thickness [70,84,86] as opposed to the 2 Am observed in the Zribi et al. study [29].
FIG. 23 Scanning electron microscope backscattered electron image of a cross-sectioned solder joint made by reflowing Sn–3.5Ag–1.0Cu (Sn–3.8Ag–1.85Cu in atomic percent) solder on a Au/Ni-coated Cu substrate. The black phase at the bottom is the Ni-coated Cu substrate after complete dissolution of Au within the solder, the dark gray phase at the interface is (Cu,Ni)6Sn5, and the lighter gray phase on top of it is solder with white needlelike precipitates of Au0.5Ni0.5Sn4 and a few dark gray Cu6Sn5 precipitates scattered within the joint. Also visible at the top of the picture at the interface, a layer of (Ni,Cu)3Sn4 is observed to grow.(From Ref. 29.)
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FIG. 24 Scanning electron microscope backscattered electron image of the interface of a crosssectioned joint made by reflowing Sn–3.5Ag–1.0Cu (Sn–3.8Ag–1.85Cu in atomic percent) solder on a Cu substrate pad. The black phase at the bottom is the Cu substrate, the dark gray phase at the interface is Cu6Sn5 (D), and the lighter gray phase on top of it is solder (E) with a few dark gray Cu6Sn5 precipitates scattered within the joint. (From Ref. 29.)
The thicker layer of Cu6Sn5 may possibly be attributed to the presence of Cu in the Sn–3.4Ag– 0.7Cu solder, which according to Schaefer et al. increases the intermetallic compound growth rate while correspondingly slowing down the dissolution of Cu at the Cu/Sn interface. 2. Reactions with Ni/Au-Plated Pads Distinctly different results are observed to occur in the case of Sn–3.4Ag–0.7Cu solder bumped die on Ni chip-carrier pads [36]. The phase (Cu,Ni)6Sn5 forms at the Sn–3.4Ag–0.7Cu/Ni interface after reflow (Fig. 25 ). The thickness of this ternary intermediate alloy was observed to be approximately 2 Am after reflow. Chemical compositional analysis of the solder matrix after reflow indicated the Cu concentration to be very low. The formation of (Cu,Ni)6Sn5 is much different from observations in Pb–Sn solders, where Ni3Sn4 is formed during reflow. However, after 16 hr of annealing at 150jC, a (Ni,Cu)3Sn4 layer with an average thickness of 0.6 Am formed at the (Cu,Ni)6Sn5/Ni interface (Fig. 26). After 64 hr, this new phase attained a thickness of approximately 0.9 Am. The combined thickness of the two layers, (Ni,Cu)3Sn4 and (Cu,Ni)6Sn5, was measured at various stages during annealing by optical and electron microscopy (compositional line scans across the interface) (Fig. 27). At later times in this small sample, the overall thickness did not increase significantly, but the (Cu,Ni)6Sn5 phase transformed to the (Ni,Cu)3Sn4 phase. In fact, the thickness of (Ni,Cu)3Sn4 at the Ni surface increased with continued annealing at 150jC. Fig. 28 shows the (Ni,Cu)3Sn4 phase at the interface with a Ni– V die pad metallization. After 261 hr of annealing, it is clear that the Cu is concentrated at both terminal-pad metallization interfaces (Figs. 28 and 29). The depletion of Cu from the solder was observed to result in an increased solder melting point and change in mechanical properties [36]. a. Ni vs. Cu Reaction Differences. A clear difference is observable in comparing the growth of intermetallic compounds at the interfaces of Ni and Cu pad metallurgies. Figs. 30 and 31 are scanning electron microscopy images of joints on Cu/OSP and Cu/Ni/Au chip carrier, respectively, achieved during a 238jC peak temperature and 54-sec dwell time condition. The intermetallic compounds have a dark appearance, and are located at the chip-carrier and die-pad
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FIG. 25 Scanning electron microscope backscattered electron image of the interface of a crosssectioned solder joint made by reflowing Sn–3.5Ag–1.0Cu (Sn–3.8Ag–1.85Cu in atomic percent) solder on a Au/Ni substrate. The black phase at the bottom is the Ni-coated Cu substrate after all the Au dissolved into the solder (H) during reflow, the light gray phase at the interface is (Cu,Ni)6Sn5 (F), and the needlelike light gray phase dispersed inside the solder matrix is Ag3Sn (G). (From Ref. 29.)
FIG. 26 Scanning electron microscope backscattered electron image of the interface of a crosssectioned solder joint made by reflowing Sn–3.5Ag–1.0Cu (Sn–3.8Ag–1.85Cu in atomic percent) solder on an Au/Ni substrate. The sample was annealed for 16 hr at 150jC. The black phase at the bottom is the Ni substrate, the light gray phase at the interface is (Ni,Cu)3Sn4, and the darker gray phase is (Cu,Ni)6Sn5 phase; the white matrix on the top is Sn–3.5Ag–1.0Cu (Sn–3.8Ag–1.85Cu in atomic percent) solder. (From Ref. 29.)
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FIG. 27 Average thicknesses of (Cu,Ni)6Sn5 and (Ni,Cu)3Sn4 at the Sn–3.5Ag–1.0Cu (Sn–3.8Ag– 1.85Cu in atomic percent) solder/Ni interface as a function of annealing time at a temperature of 150jC. o The average thickness of (Ni,Cu)3Sn4. n The average thickness of (Cu,Ni)6Sn5. 5 The average combined thickness of (Ni,Cu)3Sn4 and (Cu,Ni)6Sn5 at the Sn–3.5Ag–1.0Cu/Ni interface. For comparison, the measured average thickness of Cu6Sn5 at a Sn–Ag–Cu/Cu interface as a function of annealing time at a temperature of 150jC is also provided, i.e., x the average thickness of Cu6Sn5. (From Ref. 29.)
FIG. 28 Scanning electron microscope backscattered electron image of the interface of a crosssectioned solder joint made by reflowing Sn–3.5Ag–1.0Cu (Sn–3.8Ag–1.85Cu in atomic percent) solder on a Au/Ni substrate. The sample was annealed for 261 hr at 150jC. The phases marked with letters were identified as follows: A (Cu), B (Ni,P), C (Ni,Cu)3Sn4, D (Cu,Ni)6Sn5, E Au0.5Ni0.5Sn4, F (Ni,Cu)3Sn4, and G Sn–Cu–Ag solder depleted in Cu and Ag. (Ref. 29.)
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FIG. 29 Wavelength dispersive spectroscopy (WDS) maps showing the distribution of Cu in a Sn– 3.5Ag–1.85Cu/Au/Ni joint annealed for 261 hr at 150jC. The upper image is a Cu map (white areas) while the bottom picture shows a phase contrast image of the analyzed area. (From Ref. 29.)
interfaces. The solder/Cu interface exhibits a scalloped shape characteristic of Cu6Sn5 growth during reflow. It is evident from these figures that intermetallic compound growth at solder/metal interfaces is more prodigious in the case of Cu metallizations compared to Ni. Fig. 32 provides a side-by-side comparison of two such joints at the same length scale. This observation is consistent with a previous discussion, in which it was surmised that the (Cu,Ni)6Sn5 alloys grow faster than Ni3Sn4, and thus is kinetically selected to grow first at the solder/Ni metallization interfaces. As noted earlier, this growth depletes the solder of Cu, eventually stopping the growth of the (Cu,Ni)6Sn5 intermediate phase. Apparently, in the case of Cu metallizations the growth of
FIG. 30 Scanning electron microscope image of Sn–Ag–Cu solder reflowed for 74 sec on a Cu/OSP substrate. The Sn–Ag–Cu solder was reflowed on a die with a NiV under bump metallization. The bumped die was then reflow attached to a Cu/OSP substrate pad with a time of 74 sec above the liquidus temperature and a peak temperature of 238jC.
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FIG. 31 Scanning electron microscope image of Sn–Ag–Cu solder reflowed for 54 sec on a Ni/Au substrate. The Sn–Ag–Cu solder was reflowed on a die with a NiV under bump metallization. The bumped die was then reflow attached to a Ni/Au substrate pad with a time of 54 sec above the liquidus temperature and a peak temperature of 238jC.
Cu6Sn5 does not deplete the solder of Cu near the interface. In fact, it allows the growth of (Cu,Ni)6Sn5 to continue for longer times at the Ni–V/solder interface as well. As shown in Fig. 33, a 6jC higher peak reflow temperature and 20-sec longer dwell time results in an even greater thickness.
V. SUMMARY Many significant differences exist in the evolution of intermetallic compounds in Pb-free solder joints, such as Sn–Ag–Cu, as compared to Pb–Sn solder joints. Copper and silver, the constituents added to Sn to lower its melting temperature and increase its wettability, form
FIG. 32 Comparison of growth of intermetallic alloys for Sn–Ag–Cu solder (with same die) on different substrates. The Sn–Ag–Cu solder was reflowed on chips with a NiV under bump metallization. Then the bumped chips were reflowed on a substrate with either Ni/Au or Cu/OSP pads or on a substrate (as indicated in the figure) with a time of 54 sec above the liquidus temperature and a peak temperature of 238jC. There is more intermetallic compound growth in the case of the joint with (a) the Cu pad metallization compared to (b) the one with the Ni pad metallization.
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FIG. 33 Comparison of the growth of intermetallic alloys for different reflow times with Sn–Ag–Cu solder. The Sn–Ag–Cu solder was reflowed on chips with NiV under bump metallization. Then the bumped chips were reflowed to substrates with Cu/OSP pads above the liquidus of (a) 545j, and (b) 745j, and a peak temperature of 238jC. An increase in time above the liquidus resulted in an increased intermetallic compound formation.
intermetallic compounds on cooling from the melt (Cu6Sn5 and Ag3Sn). In fact, the morphology and distribution of these intermetallic compounds immediately after reflow affect the mechanical properties of solder joints. Furthermore, the Cu in the Sn–Ag–Cu solder matrix has been shown to react with Ni metallizations. In contrast, Pb does not form intermetallic compounds with Sn, and generally does not react with metallization constituents. As compared to Pb–Sn solder joints, significant differences exist in the growth of intermetallic compounds at Pb-free solder/metallization interfaces during reflow and subsequent solidstate heat treatments. These differences are not huge, generally less than one order of magnitude, but they are distinct. These differences are perhaps best epitomized by the difference in the rates of growth of Ni3Sn4 and Cu6Sn5 at a given temperature, with Cu6Sn5 reported to grow faster than Ni3Sn4. Because phase formation in Sn-based solder joints is dominated by kinetics, rather than energetics, until Cu is depleted from Sn–Ag–Cu solder, Cu allows the growth of (CuNi)6Sn5 at Ni/ Sn–Ag–Cu interfaces. The particularly rapid diffusion of solute metals in Sn and Sn-like structures strongly favors the growth of the most Sn-rich intermetallic compounds. This explains, among other things, the growth of the Au0.5Ni0.5Sn4 phase at the interface of interconnections of eutectic Sn–Pb solder interacting with Ni/Au-coated pads. This may reduce the bonding to the pads, allowing for socalled ‘‘brittle’’ or planar failures, after high-temperature aging. The growth of (Cu,Ni)6Sn5 and (Ni,Cu)3Sn4 layers at terminal-pad surfaces depletes copper from the Sn–Ag–Cu bulk solder between two pads each with a Ni metallization. The resulting solder joint, which is essentially Sn– Ag, exhibits different mechanical properties, and perhaps thermomechanical fatigue resistance than standard Sn–Ag–Cu solder joints. It is clear that careful consideration of all constituents in a solder joint, including metallizations, is required in order to understand the evolution of the microstructure of solder joints, and associated mechanical and reliability issues.
APPENDIX The boundary conditions imposed are a zero flux condition at the outermost surface of the solder and a Dirichlet zero condition at the interface solder/metallization (Au sink). The diffusion coefficient for Au in Sn–Pb was determined by other investigators for several annealing temperatures. Comparison of diffusion coefficients of Au in Sn–Pb to those of Au in single crystal Sn (a
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direction) shows little difference between these quantities in the temperature range 80–160jC. The dependence of DAu in Sn in the c direction on temperature is expressed as, DAu
in Sn
¼ 0:16 expð17:7=1:98 103 TÞ
ð2Þ
where T is the annealing temperature in degrees Kelvin and DAu in Sn is the diffusion coefficient of Au in Sn in units of centimeters squared per second at temperature T [56]. The calculations yield the number of moles of Au, which diffuse across the interface (integrated flux). Using the stoichiometry of the ternary compound, Au0.5Ni0.5Sn4, which forms at the interface, the corresponding number of moles of Au0.5Ni0.5Sn4 was calculated, and finally the thickness of the ternary compound was computed. The calculations assume that the thickness of the ternary compound covers the entire surface area of the solder/metallization interface as it grows. Accordingly, the expression for the thickness of Au0.5Ni0.5Sn4 as a function of the integrated flux is: ð3Þ XðAu0:5 Ni0:5 ÞSn4 ðtÞ ¼ 0:5FðtÞMðAu0:5 Ni0:5 ÞSn4 =qðAu;0:5 Ni0:5 ÞSn4 where XAu0.5Ni0.5Sn4 is the thickness of the ternary Au0.5Ni0.5Sn4 after t hours of annealing at temperature T, F(t) is the integrated diffusion flux of Au atoms across the interface after t hours of annealing, MAu0.5Ni0.5Sn4 is the molar mass of Au0.5Ni0.5Sn4 and qAu0.5Ni0.5Sn4 is the density of the ternary phase. Such behavior is less pronounced in the Ni/Pb–Sn system, where the Ni3Sn4/Ni interface is found to be planar. Both whiskers and spalling are observed at the Ni3Sn4/solder interface, but any grooving apparently does not extend all the way to the Ni3Sn4/Ni interface. Thus, the growth of Ni3Sn4 is significantly slower than Cu6Sn5 in the case of Cu/Pb–Sn interfaces. Reflow studies of Pb–Sn-based systems generally show the formation of Cu6Sn5 at Cu/Pb–Sn interfaces, while the Au on Ni/Au-coated pads dissolve into the solder matrix and Ni3Sn4 is formed at the pad surface.
ACKNOWLEDGMENTS Innumerable comments and contributions from Lawrence Lehman and Anthony Clark are gratefully acknowledged. Some of the research described in this chapter was supported in part by grants from the National Science Foundation (DMR9902783 and DM0218129) and by the Integrated Electronics Engineering Center (IEEC) at the State University of New York at Binghamton. The IEEC is a New York State Center for Advanced Technology and receives funding from the New York State Office of Science, Technology and Academic Research and a consortium of industrial members. This research also utilized the Cornell Center for Materials Research Shared Experimental Facilities, supported through the National Science Foundation Materials Research Science and Engineering Centers Program (DMR-9632275). We gratefully acknowledge TMS (The Minerals, Metals, and Materials Society) for permission to use figures and text from the article ‘‘The growth of intermetallic compounds at Sn-Ag-Cu solder/Cu and Sn-Ag-Cu solder/Ni interfaces and the associated evolution of the solder microstructure’’ from the Journal of Electronic Materials 2001, 30, 1157.
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Frear, D.R.; Burchett, S.N.; Morgan, H.S.; Lau, J.H. The Mechanics of Solder Alloy Interconnects; Van Nostrand Reinhold: New York, 1994. Yost, F.G.; Hosking, F.M.; Frear, D.R. The Mechanics of Solder Alloy Wetting and Spreading; Van Nostrand Reinhold: New York, 1993. Lau, J.H. Flip Chip Technologies; McGraw Hill: New York, 1996. Goyal, D.; Kinzie, P.; Panichas, C.; Chong, K.M.; Villaloboos, O. Failure mechanisms of brittle solder joint fracture in the presence of electroless nickel immersion gold (ENIG) interface. Proceedings Electronic Components and Technology Conference, San Diego, CA, May 2002. Kinyanjui, Robert K.; Zribi, Anis; Cotts, Eric J. Effects of reflow conditions on the formation of Au–
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COTTS ET AL. Ni–Sn compounds at the interface of Au–Pb–Sn and Au–Sn solder joints with Ni substrate. Proceedings Electronic Components and Technology Conference, San Diego, CA, May 2002; 161 pp. Alam, M.O.; Chan, Y.C.; Hung, K.C. Reaction kinetics of Pb–Sn and Sn–Ag solder balls with electroless Ni–P/Cu pad during reflow soldering in microelectronics packaging. Proceedings Electronic Components and Technology Conference, San Diego, CA, May 2002. Ghosh, G. Interfacial microstructure and the kinetics of interfacial reaction in diffusion couples between Sn–Pb solder and Cu/Ni/Pd metallization. Acta. Mater. 2000, 48, 3719. Ghosh, G. Coarsening kinetics of Ni3Sn4 scallops during interfacial reaction between liquid eutectic solders and Cu/Ni/Pd metallization. J. Appl. Phys. 2000, 88, 6887. Choi, S.; Bieler, T.R.; Lucas, J.P.; Subramanian, K.N. Characterization of the growth of intermetallic interfacial layers of Sn–Ag and Sn–Pb eutectic solders and their composite solders on Cu substrate during isothermal long-term aging. J. Electron. Mater. 1999, 28, 1209. Ho, C.E.; Chen, W.T.; Kao, C.R.; Ho, C.E.; Chen, W.T.; Kao, C.R. Interactions between solder and metallization during long-term aging of advanced microelectronic packages. J. Electron. Mater. 2001, 30 (4), 379. Su, P.; Korhonen, T.; Li, C. Intermetallic phase formation and growth kinetics at the interface between molten solder and Ni-containing under bump metallization. Proceedings Electronic Components and Technology Conference, Las Vegas, NV, May 2002; 1712–1718. Jang, J.W.; Kim, P.G.; Tu, K.N.; Frear, D.R.; Thompson, P. Solder reaction-assisted crystallization of electroless Ni–P under bump metallization in low cost flip chip technology. J. Appl. Phys. 1999, 85, 8456. Ghosh, G. Kinetics of interfacial reaction between eutectic Sn–Pb solder and Cu/Ni/Pd metallizations. J. Electron. Mater. 1999, 28, 1238. Massalski, T.B. Binary Alloy Phase Diagrams; 2nd Ed.; ASM International: Materials Park, OH, 1990. Kim, H.K.; Tu, K.N. Kinetic analysis of the soldering reaction between eutectic SnPb alloy and Cu accompanied by ripening. Phys. Rev. B 1996, 53, 16027. Kang, S.K.; Choi, W.K.; Shih, D.Y.; Lauro, P.; Henderson, D.W.; Gosselin, T.; Leonard, D.N. Interfacial reactions, microstructure, and mechanical properties of Pb-free solder joints in PBGA laminates. Proceedings Electronic Components and Technology Conference, San Diego, CA, May 2002. IPC Roadmap: A Guide for Assembly of Lead-Free Electronics, Draft IV. IPC: Northbrook, IL, 2000. Tu, K.N.; Zeng, K. Reliability issues of Pb-free solder joints in electronic packaging technology. Proceedings Electronic Components and Technology Conference, San Diego, CA, May 2002. Kujala, A.; Reinikainen, T.; Ren, W. Transition to Pb-free manufacturing using land grid array packaging technology. Proceedings Electronic Components and Technology Conference, San Diego, CA, May 2002. Balkan, H.; Patterson, D.; Burgess, G.; Carlson, C.; Elenius, P.; Johnson, M.; Rooney, B.; Sanchez, J.; Stepniak, D.; Wood, J. Flip-chip reliability: Comparative characterization of lead free (Sn/Ag/Cu) and 63Sn/Pb eutectic solder. Proceedings Electronic Components and Technology Conference, San Diego, CA, May 2002. Zheng, Y.; Hilman, C.; McCluskey, P. Intermetallic growth on PWB’s soldered with Sn3.8Ag0.7Cu. Proceedings Electronic Components and Technology Conference, San Diego, CA, May 2002. Kang, S.K.; Shih, D.Y.; Fogel, K.; Lauro, P.; Yim, M.J.; Advocate, G.; Griffin, M.; Goldsmith, C.; Henderson, D.W.; Gosselin, T.; King, D.; Konrad, J.; Sarkhel, A.; Puttlitz, K.J. Interfacial reaction studies on lead(Pb)-free solder alloys. Proceedings Electronic Components and Technology Conference, Orlando, FL, May 2001; 448–451. Jang, S.; Wolf, J.; Ehrmann, O.; Gloor, H.; Reichl, H.; Paik, K. Investigation of UBM systems for electroplated Sn/37Pb and Sn/3.5Ag Solder. Proceedings Electronic Components and Technology Conference, Orlando, FL, May 2001; 950–956. Zribi, A.; Zavalij, L.; Borgesen, P.; Primavera, A.; Westby, G.; Cotts, E.J. The kinetics of formation of ternary intermetallic alloys in Pb–Sn and Cu–Ag–Sn Pb-free electronic joints. Proceedings Electronic Components and Technology Conference, Orlando, FL, May 2001. Taguchi, T.; Kato, R.; Akita, S.; Okuno, A.; Suzuki, H.; Okuno, T. Lead free interfacial structures and their relationship to Au plating. Proceedings Electronic Components and Technology Conference, Orlando, FL, May 2001; 687–692. Lin, J.; DeSilva, A.; Frear, D.; Guo, Y.; Jang, J.; Li, L.; Mitchell, D.; Yeung, B.; Zhang, C. Characterization of lead-free solders and under bump metallurgies for flip-chip package. Proceedings Electronic Components and Technology Conference, Orlando, FL, May 2001; 455–462. Zeng, K.; Vuorinen, V.; Kivilahti, J.K. Intermetallic reactions between lead-free Sn–Ag–Cu solder and Ni(P)/Au surface finish on PWBs. Proceedings Electronic Components and Technology Conference, Orlando, FL, May 2001; 693–698. Zribi, A.; Cotts, E.J. Diffusion controlled growth of ternary intermetallic compounds in Pb-based and Pb-free electronic solder joints. Proceedings SMTA International Conference, 2001; 810 pp. Zribi, A.; Clark, A.; Zavalij, L.; Borgesen, P.; Cotts, E.J. The growth of intermetallic compounds at
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Metallurgical and reliability aspects of leadfree mixed technology electronic assembly for mobile communication products. IPC Works, 2000. Zribi, A.; Chromik, R.R.; Presthus, R.; Teed, K.; Zavalij, L.; DeVita, J.; Tova, J.; Cotts, E.J.; Clum, J.; Erich, R.; Primavera, A.; Westby, G.; Coyle, R.J.; Wenger, G.M. Solder metallization interdiffusion in microelectronic interconnects. IEEE CPMT 2000, 23, 383. Chen, S.; Yen, Y. Interfacial reactions in Ag–Sn/Cu Couples. J. Electron. Mater. 1999, 28, 1203. Zribi, Anis; Borgesen, Peter; Zavalij, Lubov; Cotts, Eric J. Growth of Cu–Ni–Sn alloys in Pb free CuSnAg solder/Au–Ni. Metallization Reactions Symposium Y, Proceedings of the Fall Meeting of the Materials Research Society, 1999; Y8.10652. Chromik, R.R.; Cotts, E.J. Thermodynamic and kinetic study of phase transformations in solder/ metal systems. Proc. Mater. Res. Soc. 1997, 69, 445. Chromik, R.R.; Cotts, E.J. A Study of the kinetics and energetics of solid state reactions in Pd/Sn diffusion couples, thermodynamics and kinetics of phase transformations. Proceedings Fall Meeting of the Materials Research Society, Pittsburgh, PA, 1995; 307 pp. Neils, W.K.; Chromik, R.R.; Dreyer, K.F.; Grosman, D.; Cotts, E.J. Calorimetric study of the energetics and kinetics of interdiffusion in Cu/Cu6Sn5 thin film diffusion couples, thermodynamics and kinetics of phase transformations. Fall Meeting of the Materials Research Society, Pittsburgh, PA, 1995; 313 pp. Abtew, M.; Selvaduray, G. Lead-free solders in microelectronics. Mater. Sci. Eng. 2000, 27, 95. Kim, P.G.; Tu, K.N. Fast soldering reactions on Au foils. Mater. Res. Soc. Symp. Proc. 1997, 445, 131–136. Ferguson, M.E.; Fieselman, C.D.; Elkins, M.A. Manufacturing concerns when soldering with Au plated component leads or circuit board pads. IEEE Trans. Compon. Packag. Manuf. Technol. Part C July 1997, 20 (3), 188–193. Mei, Z.; Kaufmann, M.; Eslambolchi, A.; Johnson, P. Brittle interfacial fracture of PBGA packages soldered on electroless nickel/immersion gold. Proceedings 48th Electronic Components and Technology Conference, 1998; 952–961. Darveaux, R.; Banerji, K.; Mawer, A.; Dody, G. Reliability of plastic ball grid array assembly. In Ball Grid Array Technology; Lau, J.H., Ed.; McGraw Hill: New York, 1995; 400–410. Bradley, E.; Banerji, K. Effect of PCB finish on the reliability and wettability of ball grid array packages. Proceedings 45th Electronic Components and Technology Conference, 1995; 1028–1038. Bader, W.G. Dissolution of Au, Ag, Pd, Pt, Cu and Ni in a Molten Sn–Lead Solder. Weld. J. Res. Suppl. 1969, 48 (12), 551s–557s. Anhock, S.; Opperman, H.; Kallmayer, C.; Aschenbrenner, R.; Thomas, L.; Reichl, H. Investigations of Au/Sn alloys on different end-metallizations for high temperature applications. Proceedings IEEE/ CPMT Berlin International Electronics Manufacturing Technology Symposium, 1998; 156–165. Villars, P.; Alan, P.; Okamoto, H. Handbook of Ternary Alloy Phase Diagrams; ASM International: Materials Park, OH, 1995; Vol. 4, 5214–5228. Kulojarvi, K.; Tu, K.N. Effect of dissolution and intermetallic formation on the reliability of FC joints. Microelectron. Int. 1998, 15 (2), 20–24. Tu, K.N. Interdiffusion and reaction in bimetallic Cu–Sn thin films. Acta Metall. Mater. 1973, 21, 3471. Marinkovic, Z.; Simic, V. Comparative analysis of interdiffusion in some thin metal film couples at room temperature. Thin Solid Films 1992, 217, 26. Tu, K.N. Single intermetallic compound formation in Pd–Pb and Pd–Sn thin film couples studied by X-ray diffraction. Mater. Lett. 1982, 1, 6. Tu, K.N.; Rosenberg, R. Room temperature interaction in bimetallic thin film couples. Jpn. J. Appl. Phys. 1974, Suppl. 2 (Pt. 1), 633. Dyson, B.F.; Anthony, T.R.; Turnbull, D. Interstitial diffusion of copper and silver in lead. J. Appl. Phys. 1966, 37, 2370–2374. Dyson, B.F. Diffusion of gold and silver in tin single crystals. J. Appl. Phys. 1966, 37, 2375–2377. Warburton, W.K.; Turnbull, D. Diffusion in Solids: Recent Developments; Nowick, A.S., Burton, J.J., Eds.; Academic Press: New York, 1975; 172–229.
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COTTS ET AL. Chromik, R.R.; Cotts, E.J. A study of the kinetics and energetics of solid state reactions in Pd/Sn diffusion couples. In Thermodynamics and Kinetics of Phase Transformations; Im, J.S., Park, B., Greer, A.L., Stephenson, G.B., Eds.; Proc. Mater. Res. Soc. 1996, 398, 307–312 (Pittsburg, PA). Chada, S.; Laub, W.; Fournelle, R.A.; Shangguan, D.J. Electron. Mater. 1998, 23, 1194. Schaefer, M.; Fournelle, R.A.; Liang, J.J. Theory for intermetallic phase growth between Cu and liquid Sn–Pb solder based on grain boundary diffusion control. J. Electron. Mater. 1998, 27, 1167. Gur, D.; Bamberger, M. Reactive isothermal solidification in the Ni–Sn system. Acta Metall. Mater. 1998, 46 (14), 4917–4923. Kulojarvi, K.; Vuorinen, V.; Kivilahti, J. Effect of dissolution and intermetallic formation on the reliability of FC joints. Microelectron. Int. 1998, 15 (2), 20–24. Zavalij, L.; Zribi, A.; Chromik, R.; Pitely, S.; Zavalij, P.Y.; Cotts, E.J. Metallography and crystal structure of Au1xNixSn4 alloys. J. Alloys Compd. 2002, 334. Dreyer, K.F.; Niels, W.K.; Chromik, R.R.; Grosman, D.; Cotts, E.J. Calorimetric study of the energetics and kinetics of interdiffusion in Cu/Cu6Sn5 thin film diffusion couples. Appl. Phys. Lett. 1995, 67, 2795. Bryant, A.W.; Bugden, W.G.; Prat, J.N. Acta Met. 1970, 18, 101. Guadagno, J.R.; Pool, M.J. J. Phys. Chem. 1968, 72, 253. Zuruzi, A.S.; Chiu, C.-H.; Lahiri, S.K.; Chua, K.M. Kinetics of copper and high Pb/High Sn bilayered Pb–Sn solder interactions. J. Electron. Mater. 1999, 28, 1224. Schaefer, Matt; Laub, Werner; Fournelle, R.A.; Liang, J. Evaluation of intermetallic phase formation and concurrent dissolution of intermetallic during reflow soldering. Design and Reliability of Solders and Solder interconnections, The Minerals, Metals and Materials Society, 1997; 247–257. Liu, A.A.; Kim, H.K.; Tu, K.N.; Totta, P.A. Spalling of Cu6Sn5 spheroids in the soldering reaction of eutectic SnPb on Cr/Cu/Au thin films. J. Appl. Phys. 1996, 80, 2774. Wu, Y.; Sees, J.A.; Pouraghabagher, C.; Foster, L.A.; Marshall, J.L.; Jacobs, E.G.; Pinizzotto, R.F. J. Electron. Mater. 1993, 22, 769. Vianco, P.T.; Hlava, P.F.; Kilgo, A.C. Intermetallic compound layer formation between copper and hot-dipped 100In, 50In–50Sn, 100Sn and 63Sn–37Pb coatings. J. Electron. Mater. 1994, 23, 583. Jang, S.; Wolf, J.; Kwon, W.; Paik, K. UBM (under bump metallization) study for Pb-free electroplating bumping: interface reaction and electromigration. Proceedings Electronic Components and Technology Conference, San Diego, CA, May 2002. Pan, T.; Blair, H.D.; Nicholson, J.M.; Oh, S. Intermetallic compound formation of Sn/Pb, Sn/Ag, and Sn solders on Ni substrate from the molten stage and its growth during aging. EEP Adv. Electron. Packag. 1997, 19 (2), 1347. Kang, S.K.; Rai, R.S.; Purushothaman, S. Interfacial reactions during soldering with lead–tin eutectic and lead (Pb)-free, tin-rich solders. J. Electron. Mater. 1996, 25, 1113. Ho, C.E.; Chen, Y.M.; Kao, C.R. Reaction kinetics of solder-balls with pads in BGA packages during reflow soldering. J. Electron. Mater. 1999, 28, 1231. Zribi, A.; Chromik, R.R.; Presthus, R.; Clum, J.; Zavalij, L.; Cotts, E.J. Effect of Au-intermetallic compounds on mechanical reliability of Sn–Pb/Au–Ni–Cu joints. EEP Adv. Electron. Packag. 1999, 26 (2), 1573. Zribi, A.; Chromik, R.R.; Presthus, R.; Clum, J.; Teed, K.; Zavalij, L.; DeVita, J.; Tova, J.; Cotts, E.J. Solder metallization interdiffusion in microelectronic interconnects. Proceedings Electronic Components and Technology Conference, San Diego, CA, June 1999; 451 pp. Minor, A.M.; Morris, J.W. Jr. Growth of a Au–Ni–Sn intermetallic compound on the solder– substrate interface after aging. Metall. Mater. Trans. 2000, 31A, 798. Ho, C.E.; Zheng, R.; Luo, G.L.; Lin, A.H.; Kao, C.R. Formation and resettlement of (AuxNi1x)Sn4 in solder joints of ball-grid-array packages with the Au/Ni surface finish. J. Electron. Mater. 2000, 29, 1175. FlexPDE version 2.19b, 1996–2000 from PDE solution Inc. URL: http://www.flexpde.com. Bader, S.; Gust, W.; Hieber, H. Rapid formation of intermetallic compounds by interdiffusion in the Cu–Sn and Ni–Sn systems. Acta. Metall. Mater. 1995, 43, 329. Onishi, M.; Fujibuchi, H. Trans. JIM 1975, 16, 539. Mei, Z.; Sunwoo, A.J.; Morris, J.W. Jr. Metall. Trans. A 1992, 23, 857. Vianco, P.T.; Erickson, K.L; Hopkins, P.L. J. Electron. Mater. 1994, 23, 721. Korhonen, T.M.; Su, P.; Hong, S.J.; Korhonen, M.A.; Li, C.-Y. Reactions of lead-free solders with CuNi metallizations. J. Electron. Mater. March 2000, 29 (10), 1194. Dabritz, S.; Bergner, D.; Hoffmann, V. Phase growth between copper and different tin solders. Defect and Diffusion Forum 1997, 143–147, 579–584. Schaefer, M.; Laub, W.; Sabee, J.M.; Fournelle, R.A.; Lee, P.S. A numerical method for predicting intermetallic layer thickness developed during the formation of solder joints. J. Electron. Mater. 1996, 25, 992.
14 Electronics Assembly and the Impact of Lead-Free Materials Anthony A. Primavera Universal Instruments Corporation, Cleveland, Ohio, U.S.A.
I.
INTRODUCTION
While the electronics industry continues to strive towards eliminating lead when assembling electronic devices, it is important to understand the fundamental issues that influence the assembly process, yield and reliability that result. Current standard surface mount devices such as peripheral leaded packages and area array (Ball Grid Array) devices offer robust assembly yields and good long-term solder joint reliability [1–3]. When developing a new assembly process, component technology, or packaging method, it is critical that they are comparable to, or perform better than those that they replace. Not only should a new device/process perform well in assembly, it must demonstrate acceptable package and solder-joint reliability in order to gain acceptance and wide utilization.
A.
Critical Parameters
Typically, current surface mount components (SMC) and area-array assembly processes rely on solder paste deposition through stencil printing, component placement, and mass reflow soldering. In order to ensure high process yields during assembly the process parameters of the various assembly operations must be evaluated. Factors that affect the assembly process yield can be divided into four categories: human factors, equipment and tooling, materials, and process methods. Figure 1 is a so-called fish bone diagram that illustrates the interrelationship among the various factors and their influence on assembly yields. In Insertion Mount Component (IMC) assembly, two general approaches are practiced. The first method is the traditional method, that consists of component insertion, cutting device wires, cinching the lead tail to prevent the part from falling out of the hole, and passing the board through a wave solder operation. The second approach utilizes a mass reflow method, and provides solder by printing or utilizing pre-formed solder arrays. Through-hole components such as headers can alternatively be assembled using the mass reflow approach if the component body base materials can withstand the temperatures experienced in a reflow oven. In a pin-in-paste or alternative mass reflow process, solder paste is printed onto the circuit-board plated through-hole pads corresponding to the pins on the IMC devices. Paste is printed into the plated hole as well to provide sufficient solder to form adequate joints on both sides of the circuit board. After paste application, the IMC components are placed into the plated holes and subjected to reflow temperatures sufficient to melt the solder and form
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FIG. 1 Cause and effect diagram of factors that influence lead-free assembly.
solder joints. This differs from wave soldering in that the IMC component must be capable of withstanding high peak reflow temperatures, since the entire component body is subjected to a thermal excursion while passing through a reflow oven, rather than only the through hole leads which are exposed to the wave. Utilizing a lead (Pb)-free alloy complicates a pin-in-paste assembly since the melting temperature of theses alloys is typically in the range of approximately 220jC to 240jC. This temperature range is significantly higher than eutectic Sn-Pb or neareutectic solders, for example, (60Sn-40Pb, or 62Sn-36Pb-2Ag) whose melting points are approximately 179jC to 185jC.
B.
Solder Joint Perfection
1. Miniaturization With the continual miniaturization of electronic components and overall systems, the interconnection between printed circuit boards (PCB) and components, namely the solder joint, becomes smaller as well. A reduction in the physical size of solder joints places additional demands on solder mechanical properties to ensure adequate robustness. In addition to footprint size reductions, there is an emphasis on an overall reduction in the size of packages that house silicon chips. As surface mount technology (SMT) migrates towards smaller package dimensions, the physical and thermal characteristics of materials used in microelectronic packages becomes increasingly more critical. Significant differences in properties between package layers, or between a chip carrier and die, result in large internal stresses during thermal excursions. When a component is mounted onto a PCB, the solder joints must absorb strains induced by the thermal expansion mismatch between the chip carrier and PCB materials. For traditional SMT components, such as quad flat packages, both the leads and solder joints provide the compliance necessary to compensate for the mismatch in coefficient of thermal expansion (CTE) between the package and PCB. However, in area array devices such as ball grid array (BGA) and chip scale packages (CSP), the joint alone must provide the CTE mismatch compliance [4–6]. 2. Defects As the joint size is reduced, the joint quality becomes increasingly more critical. Physical defects caused by poor solderability, excessive intermetallic formation, and voids negatively impact joint
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robustness and soldering yields. A change to lead (Pb)-free solder can adversely affect one or more of these factors. For example, voids that are cavities and bubbles trapped in molten solder during solidification, typically degrade mechanical, thermal and electrical properties of solder joints [7]. Higher levels of voids have been reported in lead (Pb)-free solder joints compared to their eutectic Sn-Pb counterparts. These observations are likely due to factors associated with solder paste, flux chemistry, and assembly processes.
C.
Lead-Free Alloys
Factors that influence the assembly of components using a lead-free solder are similar to the parameters that influence standard tin-lead (Sn-Pb) solder. Although assembly of SMC and IMC devices differ in the specific steps, equipment, and solder joint shape, the general goal is the same: creation of robust soldered interconnections. The main difference in lead-free soldering is the higher reflow temperatures needed to fully melt the solder alloy. The need for higher process temperatures places greater demands on component and PCB materials.
D.
Fundamental Assembly Issues
In general, the electronic component assembly process and yield are influenced by several main factors including: human factors, machine issues, assembly process, and assembly materials [8– 11], which are discussed in detail in this chapter. While the general concepts hold true for IMC and SMC assembly, they have been shown to apply to area array assembly as well. This chapter describes some fundamental issues associated with the lead (Pb)-free assembly of electronic devices. Specifically, assembly process parameters such as solder paste and wave solder material selection, and circuit board metallurgy, affect the yield when attaching components to organic motherboards. Factors such as the presence of voids, reflow atmosphere, attachment pad metallurgy and assembly parameters have a dramatic affect on the solderability and wetting of lead-free solder alloys. Lead-free assembly procedures are similar to those practiced utilizing eutectic Sn-Pb solder. However, differences in alloy soldering performance, melting point, and physical properties, require that standard assembly procedures be modified. This chapter focuses on the assembly of the three main categories of electronic components: surface mount components (SMC) such as peripheral leaded devices; insertion mount components (IMC) such as through-hole components, and area array components, including ball grid array (BGA) and chip scale packages (CSP).
II.
SOLDER PASTE MATERIALS
The materials used in the surface-mount, area-array assembly process include solder paste, stencils, components, flux, and the PCB. In wave soldering applications, solder paste and paste deposition processes are eliminated, and a cured adhesive is used to retain bottom-side components on a PCB during exposure to a solder wave.
A.
Solder Paste
Solder paste is a homogenous and kinetically-stable mixture of flux that serves as a vehicle, and solder alloy powder. Solder forms the metallic bond between metal terminal pads on a component and mating metal pads on a circuit board. During solder reflow, the flux is thermally activated and wets the metal surfaces. The flux removes the metal oxides formed on the surface of the pads, component leads, and on the solder particles themselves, leaving an oxide-free surface for metallurgical bonding. Once the melting point of the solder alloy is attained, the individual particles in a solder paste coalesce into a uniform liquid mass that reacts with the PCB pad and lead surface forming intermetallic compounds at the interfaces. Solder paste technology encompasses many technologies including; flux chemistry, fluid dynamics of flow, metallurgy of alloying, and rheology of the combined flux, powder and vehicle mixture. In general, lead-free solder pastes
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have print, roll, slump, and aperture release characteristics similar to eutectic Sn-Pb solder paste. However, lead (Pb)-free pastes are darker in color, tend to form taller printed deposits, roll slightly slower, and have dramatically reduced wetting compared to eutectic Sn-Pb solder.
B.
Formulation
Characteristics of the solder paste that are important from a process perspective include; the solder powder particle size, metallurgy, slump, temperature and humidity sensitivity, solids content, type of flux residue, viscosity, and the propensity for solder balling. Viscosity is an important property of a paste related to metal loading. The ratio of metal particles to flux vehicle changes the flow characteristics of the mixture. A higher percentage of powder in the paste increases the viscosity. Lead-free solders, typically have a slightly lower metal loading (88-89%) compared to Sn-Pb (90-91%) to achieve the same viscosity and print characteristics due to the difference in alloy density. No-clean Sn-Pb (63/37) solder pastes with high metal content, (approximately 90 percent by weight), are widely used to attach SMT, CSP, and BGA packages to PCBs during assembly. Lead-free solder pastes are formulated with a lower density than leadbearing alloys due to the difference in mass of equivalent volumes of solder. The solder paste physical properties such as the viscosity are therefore different for eutectic Sn-Pb and lead-free pastes formulated with the same metal loading percentage. For Sn-Pb pastes at a nominal 90% metal loading by weight, the volume of solidified solder is approximately 50% of as-deposited paste.
C.
Powder Particle Size
The size of the particles in a solder paste determines the print characteristics, amongst other things. The particles are produced by a variety of methods, but they are most commonly made by dispersion of a stream of molten solder onto a rotating disk. The particles fall into a tank filled with an inert atmosphere where they solidify and then are collected at the bottom of the chamber. The collected particles are separated by size utilizing in a series of wire-mesh sieves. The mesh size is typically given in wires or holes per square inch. The Joint Industry Standard, J-STD-005, provides for solder paste particle size classification as listed in Table 1. The choice of solderpowder particle size for SMT applications is based on component pitch, part mix and pad arrangement. For example, the paste particle size required for an area array device is smaller compared to a peripheral-leaded device with the same pitch. A 0.5-mm pitch area array device may have 0.25-mm diameter pads which require a 0.25-mm to 0.3-mm stencil aperture to print a Type IV solder paste with an approximately at 60-80% transfer efficiency. Comparatively, a 0.5–mm pitch quad flat pack device would typically have an 0.2 mm to 0.25mm wide pad, but require a 0.15 to 0.2mm wide stencil aperture to print a Type III paste with approximately a 80–90% efficiency.
TABLE 1 Solder Paste Type I II III IV V VI
Solder Paste Classification with Particle Size Requirements Particle Size Range, Content Required: 80% Minimum (microns) 150–75 75–45 45–25 38–20 25–15 15–5
Maximum Size (Microns)
Minimum Particle Size Content Allowed: Less Than 1% (microns)
Minimum Particle Size Content Allowed: Less Than 10% (microns)
160 80 50 40 30 20
150 75 45 38 25 15
20 20 20 20 15 5
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For the assembly of standard BGAs (1.27-mm), the stencil aperture size is typically 0.55 to 0.65-mm in diameter. The solder-powder particle size could range from 200/+325 mesh size (Type 2) to 400/+500 mesh size (Type IV). As the component pitch decreases, the aperture size must decrease correspondingly. For example, to mount a solder ball component with a pitch in the range of 0.8 to 1.0 mm requires a stencil aperture size about 0.4 to 0.5 mm to apply a Type III solder paste. As the pitch is reduced, a reduced particle size paste, for example Type IV, should be used. When assembling 0.5-mm pitch components, the stencil aperture size may be as small as 0.25 to 0.35 mm.
D.
Printing Efficiencies
The aperture area-to-wall area parameter plays a key role in solder-paste print efficiency. The efficiency is defined as the printed volume divided by the aperture volume. A 100% efficiency means that the amount of paste printed equals the aperture volume, while a 50% efficiency means only half of the volume was deposited. In fine-pitch print experiments [12] it has been demonstrated that the aperture opening area-to-wall area ratio is a critical parameter in achieving a high paste transfer efficiency. For circular apertures, the area ratio may exceed 1.5, which leads to a low print transfer efficiency. However, for long rectangular apertures, the area ratio may be 1.0 or less, depending on the stencil thickness, resulting in a much higher transfer efficiency. The print efficiency for circular and rectangular apertures of different thickness is compared in Figure 2 for eutectic Sn-Pb and Sn-Ag-Cu pastes.
E.
Solder Paste Characteristics
A viscosity test is used to help determine the flow characteristics of a solder paste. Solder paste is usually deposited using a ’stencil printing’ approach. Solder pastes are thixotropic fluids which have the characteristic of reducing viscosity with time when subjected to constant shear conditions. In other words, solder pastes are more fluid when dispensed with a squeegee (applied shear stress), but the paste remains thick when no stress is applied. When shear-thinned, solder pastes are capable of flowing into stencil apertures. When a print stroke is complete, the paste viscosity increases allowing the deposit to maintain its printed geometric shape. If a paste is overly viscous, it results in insufficient paste volume resulting in open joints. However, low viscosity results in excessive volumes, slumping and bridging. 1. Viscosity The rheology of a solder paste affects its ability to be dispensed and deposited, and is affected by its flow and elastic properties. Rheology control is a vital pre-production check that assures that the solder paste can be adequately and reproducibly dispensed. In general, the viscosity of a solder paste depends on flux type, powder size and distribution, and the metal content. The kinematic state of a body is known if the position and velocity of all points in the body are known at some time, t. In the case of flow, the kinematic variables are strain and the strain rate. The dynamic state of a body can be determined when the forces acting on the body are known. The forces that act on a body fall into two categories - body forces and surface tractions. Body forces are those that act throughout the surface; but the body is not in physical contact with the source of the force, such as the gravitational force. Surface tractions arise by having direct contact with a boundary of a body. If a force, F, acts on an arbitrary element of surface area, Sa, which is sufficiently small enough so the force is constant over the surface, then the shear stress is defined as the ratio of the force, F, to the area, Sa, Shear Stress ¼ s ¼ F=Sa where: H - Shear Stress in Pascal (Pa) F Force in Newton ðNÞ Sa Surface Area in m2 :
ð1Þ
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FIG. 2 The effect of area ratio on the transfer efficiency of various shaped stencil apertures.
Viscosity is the ratio shear stress to shear rate, Viscosity ¼ A ¼ H =S
ð2Þ
where: H - Shear Stress S Shear Rate: 2. Rheology – Newtonian vs. Non-Newtonian Fluids The flow properties of a fluid vary depending on the method of application and material type. For materials that have Newtonian characteristics, viscosity is independent of shear rates. NonNewtonian solutions, (suspensions), occur when the suspension causes either dilatency or thixotropy. A dilatant suspension is quite fluid until stressed, at which time the suspension becomes resistant to motion. Thixotropy is the opposite, in that the suspension is thick and gelatinous, but when stirred or mixed it flows more readily. While solder pastes typically exhibit similar (but not the same) thixotropic behavior, they only differ in the shear force necessary to provide flow characteristics. The difference among solder paste characteristics is due to the quantity and type of thixotropic agents utilized, which also affects paste rheology.
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For Newtonian fluids such as water, the viscosity A is constant for any practical shear rate S. In other words, viscosity is independent of shear rate. Non-Newtonian Fluids do not have a constant shear-stress to shear-rate ratio, and are grouped into three classes: dilatant, pseudoplastic and plastic. Dilatant fluids increase in viscosity with increasing shear rate, referred to as shear thickening. Pseudo-plastic fluids exhibit the characteristic of decreasing viscosity with increasing shear rate, known as shear thinning. Plastic materials differ from others in that as a shearing force is decreased, there is a threshold at which for all practical purposes, the material stops flowing. This point is called the plastic yield point. Once this point is exceeded, the material may exhibit any of the previously described flow characteristics. Some fluids exhibit a change in viscosity as shearing proceeds at a constant rate. The rheological equation of state includes time as an independent variable. s ¼ fn ðs; tÞ
ð3Þ
3. Thixotropic Fluids For non-Newtonian thixotropic fluids, the changes in viscosity are a result of mechanical interactions of a fluid’s constituent components and not a chemical reaction. For a fixed shear rate, thixotropic fluids decrease in viscosity with time, ultimately achieving a constant value. In a series of tests subjecting a sample to progressively higher shear rates, the result is a family of curves each with successively lower viscosity values. Thus, the decrease in viscosity depends on the time and magnitude of the shear rate. To account for this behavior, an ‘‘internal structure’’ is assumed present that is broken down when subjected to a shearing condition reducing the internal resistance and viscosity. At any given constant shear rate, only a portion of this structure is broken down, finally attaining a corresponding constant viscosity. The shear-thinning behavior of a thixotropic substance is accounted for in the same manner as a pseudo-plastic substance; however, for a thixotropic substance, rebuilding ‘‘the internal’’ structure is not instantaneous. As a result of this, a hysterisis loop can be experimentally observed when the shear rate is ramped up to a maximum shear rate and then reversed back to zero. The area of the thixotropic loop is sometimes used as an indication of the ‘‘degree’’ of thixotropy. The loop area can be interpreted as the energy necessary to break down the thixotropic structure for a particular volume of material. One method of calculating a ‘‘thixotropic index’’, is given as: Ti ¼ log
ðA1 =A2 Þ ðS1 =S2 Þ
ð4Þ
Where A1 and A2 are the viscosity at shear rates S1 and S2, respectively. Solder pastes are thixotropic; the viscosity decreases as the shear stress increases but slowly recovers its original value when the shear is removed. The viscosity of a solder paste depends on the solids content of the flux; on the quantity, size and shape of the solder particles; and on the thickeners added to make the paste thixotropic. Viscosity is a temperature-sensitive property and decreases markedly at higher temperatures. As the metal content decreases, solder pastes become more dependent on the thickening agents for viscosity control, particularly when relatively high viscosity is required. These thickening agents include thixotropic agents, otherwise known as rheological modifiers, which are used to control paste viscosity.
F.
Solder Paste Tests
Solder pastes used for SMT assembly are subjected to a battery of tests which are listed in Table 2 to evaluate screenability, and the ability to maintain feature definition prior to reflow in a furnace [13]. Several tests are specified by the IPC, (for example IPC-SF-818 and IPC-SP-819), while others have been adopted by the electronics assembly industry. 1. Viscosity Test The viscosity of a solder paste can be an indication of the ability of the paste to be printed and transferred properly through apertures of a solder paste stencil. If the viscosity is low, the paste
502 TABLE 2
PRIMAVERA Solder Paste Tests
Test . . . . . . .
Viscosity Solder Balling Slump Wettability Tack Strength Spread Printability
Description Measure of fluidity / flow properties Ability to coalesce into a uniform mass Ability to retain a printed deposit shape Measure of solder coverage on metal surfaces Ability of paste to retain components during assembly Increase in area of print deposit or separation of flux Ability to form well defined printed shapes
tends to not roll properly, stick to the squeegee blade, and the printed deposits do not retain their geometric shapes. Low viscosity pastes often slump excessively, and bleed underneath the stencil and smear onto the surface of the circuit board. However, highly viscous pastes do not roll sufficiently, do not fill the stencil apertures completely, and tend to stick inside the aperture walls rather than release onto the PCB pads. Solder pastes are typically formulated in different viscosities depending on how the paste is to be deposited onto the PCB pads. For stencil printing application, solder paste should have a viscosity in the range of 800,000–1,100,000 centipoise (cps). However, for solder dispensing applications that utilize a dispense pump, the viscosity should be 350,000–500,000 cps, to ensure the material does not clog the pump tip. Two main types of viscosity tests are performed on solder paste. The first method utilizes a T shaped spindle that is spun inside a container of paste in a helical path. The T spindle viscometer is also known as a Brookfield viscometer. The bar is rotated at 5–20 revolutions per minute (RPM) in 5 RPM increments. The viscosity is recorded at each speed for several minutes. The bar moves up and down in the Z axis (perpendicular to the surface of the paste sample jar) as the bar rotates. The helical path ensures the paste is shear thinned excessively by the bar during the viscosity test. The second type of viscometer utilized in solder paste testing is a Malcolm spiral viscometer. The spiral viscometer consists of an inner rod, and an outside grooved shell. Paste is introduced into the viscometer at one end of the spiral shell and is forced up into the space between the inside rod and the outside shell, and exits at the top of the shell. The outside shell rotates and shears the paste against the inside rod. 2. Printability Printability is the relative measure of a paste to be deposited into well formed geometric shapes without slumping, spreading or bridging. Printability includes a variety of paste performance characteristics such as paste roll, aperture filling capability, exhibiting paste curtain (sticking to a squeegee), crisp and sharp feature definition, and transfer efficiency. Other quality-related aspects could include the amount of paste adhering to the stencil wall and number of prints a paste can withstand before the print volume or shape is degraded. In many respects, lead-free pastes behave similar to eutectic Sn-Pb. Figure 3, shows a comparison of eutectic Sn-Pb and Sn-Ag-Cu solder paste print bead color and texture. In addition, the paste roll was found for Sn-Ag-Cu to be visually identical to eutectic Sn-Pb, as shown in Figure 4. The paste curtain resulting from the squeegee lifting away from the stencil following printing of Sn-Ag-Cu and eutectic Sn-Pb pastes is compared in Figure 5, whereas the printed deposits for eutectic Sn-Pb and Sn-Ag-Cu paste exhibit a similar deposition shape and volume as shown in Figure 6. 3. Slump Test Slump is the propensity of the solder paste to spread out after being deposited on PCB pads. Excessive slump can cause bridging of adjacent solder paste deposits. In order to achieve acceptable soldering yields, solder paste slump must be minimized. Slump also depends on the percentage of metal content in a solder paste. Slump tests are performed to determine the ability
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FIG. 3 Solder paste bead coloration of eutectic Sn-Pb and Sn-Ag-Cu pastes.
of a solder paste to maintain its geometric shape both before and during reflow. The necessity for a solder paste to hold its shape increases as the component pitch decreases. When solder paste is subjected to elevated temperatures, the flux spreads rapidly since the viscosity is reduced during heating. Flux spreading must be minimized to prevent contacting solder deposits on adjacent pads. Thixotropic agents added to solder pastes improve the print characteristics, but also help minimize the spread of solder paste deposits during reflow. Typically, the slump tests consist of a stencil with a series of decreasing pitch apertures, and the smallest gap not bridged determines the slump point. Figure 7 illustrates a solder paste slump test stencil and deposit. 4. Spread Tests The spread test provides a quantitative picture of the slump performance of the solder paste by measurement of a printed deposit before and after exposure to simulated factory floor conditions. The spread test measures the change in print deposit area of a circular deposit after a predetermined time period. Typically, a deposit of paste is subjected to aging in an isothermal aging chamber and in a humidity/temperature chamber for up to 8 hours. Typically, the change in printed diameter is measured at 1 hour, 3 hours, 5 hours and 8 hours and compared to the time zero print diameter. 5. Tack Tests Tackiness is the ability of a solder paste to hold surface mount components in place between placement and reflow soldering. The tackiness of a paste is one indicator of whether the paste is still usable. Tack strength provides a measure of a pastes ability of retaining a component in place. Whereas solder paste tack life in an indication of how long a solder paste can hold a
FIG. 4 Solder paste stencil roll of eutectic Sn-Pb and Sn-Ag-Cu pastes.
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PRIMAVERA
FIG. 5 Solder paste separation of eutectic Sn-Pb and Sn-Ag-Cu pastes.
component in place. The tackiness of a solder paste greatly depends upon the choice of solvent since evaporation causes the deposit to dry, and the tack strength and time may be reduced. The size and shape of particles in a solder paste can affect tack since the ratio of surface area to flux increases when the particles sizes decrease. Factors such as viscosity, particle size distribution, metal loading, etc. also affect tack strength but they are interdependent. For example, varying particle size and distribution by adding a significant amount of small ‘‘fines’’ increases the viscosity and in general lowers the tack strength. Tack strength can be measured by several methods including; placing a weight block on printed deposit and then placing the sample in an inclined surface. Other methods include use of a materials test system to measure the load versus displacement curve for a probe placed into and retracted in an axis perpendicular from the surface of a printed PCB. Figure 8 shows a tack test probe for an out of plane retention test. A shear tack test consists of placement of a small block onto a printed PCB and measuring the amount of shear required to push the block from the deposit in an axis parallel to the PCB surface. Tack shear
FIG. 6 Solder paste deposition shape of eutectic Sn_Pb and Sn_Ag_Cu pastes.
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FIG. 7 Solder paste slump test, (a) stencil and (b) depositusing type IV, no-clean, Sn-3.8Ag-0.7Cu solder paste.
FIG. 8 Solder paste tack test probe fixture.
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PRIMAVERA
strength can be related to the size of the placed component since the retention force is equal to the mass of the component times the acceleration imposed on the device. 6. Solderability Solderability is defined as the ability of a surface to be wet by molten solder. In peripheral-leaded mass reflow applications, the ability of the solder to climb and adhere to leads is more important that spreading out on metal terminal pads. In general terms, wettability is a more accurate description of solderability. Solder- wettability is the ability of the molten solder cover all metal surfaces present in the solder joint, namely the component pads or leads, PCB pads, and solder balls or columns on area array devices. The definition of good solderability does not, however, take into account whether alloying of the solder and pad surfaces have been achieved. Solder may flow out onto the pads but not react and bond with the surface. In order to chemically clean metallic surfaces and influence the surface energies of the solder and base metal, the flux must be in intimate contact with both surfaces. A flux must adequately wet the surfaces to be joined by displacing the adsorbed vapor on the metallic surfaces to be soldered [2]. In general, lead-free solders exhibit a much lower degree of wettability compared to eutectic Sn-Pb solder, a trend observed for many component and PCB pad finishes. This is believed due in part to the inability of the flux systems utilized in lead-free solder pastes to properly wet the metal surfaces. Figure 9 shows a comparison of eutectic Sn-Pb wetting on a blanket substrate compared to several leadfree solder alloys. A flux formulation is necessary that takes the metal systems and higher melting point of typical lead-free solder alloys into account. Many fluxes utilized in lead-free solder pastes have been formulated for eutectic Sn-Pb reflow operations. Due to substantially higher reflow temperatures of most lead-free solders, the flux is often lost due to evaporation well below the reflow temperature of lead-free solders resulting in insufficient oxide removal. 7. Solder Ball Test During reflow, the metal particles in a solder paste should coalesce into a single molten solder mass without any extraneous satellites (i.e. small molten solder balls not part of the main mass) remaining on the PCB surface. Solder fines, extremely small solder particles (less than 5 microns), prevent the solder paste from coalescing into a single molten mass. In general, solder fines are highly or completely oxidized which alters the wetting characteristics of a solder and melting point of the solder powder. Consequently, the solder powder melts at a higher temperature or it may not melt at all depending on the level of oxidation. Extraneous solder satellites can cause electrical bridges if they remain adhered to the PCB following reflow. Solder ball exposure tests characterize the ability of a solder paste to coalesce into a single mass. A printed deposit is reflown onto a non-wettable surface such as ceramic and the number of extraneous satellites surrounding the main molten mass are counted. If a paste contains excessive amounts of fines, these fine powder particles may be carried away from the main deposit by the flux and therefore can not coalesce into the molten solder mass. A solder ball test is shown in Figure 10.
FIG. 9 Wetting plot comparing eutectic Sn-Pb with two lead-free solders with several board finishes.
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FIG. 10
III.
507
Solder ball reflow test results for several lead-free solders in comparison to eutectic Sn-Pb.
STANDARD PRINTED CIRCUIT BOARDS
Boards or chip carriers made of organic materials are commonly used in surface mount assembly operations. Board-related parameters that influence the assembly yield due to variations in their dimensional parameters include: fiducial deviation, warpage, mask registration, pad size, and pad location deviation (radial deviation). The trends of reduced size and weight for increased portability coupled with ever increasing functionality fuels the development of new, high-density packages with high-density wiring and high I/O counts that must be escaped from the component to the PCB. This trend is anticipated to continue in order to meet higher levels of integration, performance and miniaturization of electronic components, at an affordable cost. If the pin count requirements, along with package size and cost reductions are to meet consumer product expectations in the future, a drastic reduction in the I/O pitch will be required and technologies to accommodate them. Smaller packages and reduced pitches will result in shorter signal traces and improved performance. Simultaneously, improvements in the PCB are also required to meet demands of reduced-pitch components. A detailed description of the various processes associated with the fabrication of printed wiring boards capable of enhanced routing capabilities to wire high pin count components including direct chip attachment is given in the Appendix in the back of this chapter. This is often referred to as PCB build-up technology or high density interconnect HDI circuitry. This section discusses standard PCB technology and the influence various factors, (Table 3), a printed circuit board has on the overall solder joint formation process. Additionally, the components being placed onto the PCB can change the required technology used to fabricate the PCB and thus influence the solder joint formation quality. The ‘‘components’’ sub-group assembly parameters that can influence solder joint formation and subsequent reliability are shown in Table 4.
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PRIMAVERA
TABLE 3 Circuit Board Features and Factors That Influence Solder Joint Formation Features and Factors . . . . . . . . .
A.
Attachment Pad Metallurgy Circuit Board Thickness Attachment Pad Shape and Size Circuit Board Base Materials Technology to Form Via Structures Circuit Routing Methodology (to Fan-out Inside of Pad Arrays) Board Layer Count Solder Mask Technology (Material, Aperture Formation Methods) Pad Geometry Definition (Feature-Defined or Solder-Mask Defined)
Effect of Process Temperatures for Lead-Free Solder
Typical circuit boards consist of multiple layers of dielectric and conductive materials. The dielectric insulating layers selected greatly influence the overall thermal and mechanical properties of a finished board. Pre-formed sheet material with fiber-reinforced epoxy is generally used for the dielectric layers, however, non-reinforced polyimides are used as well. The specific polymeric resin and reinforcing materials used influences several important aspects of a finished product, namely the coefficient of thermal expansion, glass transition temperature, and mechanical stiffness. The most widely used dielectric material is fire resistant #4 (FR4) glass reinforced epoxy. For FR4 epoxy, the number of functional epoxide groups dictates the softening or glass transition (Tg) temperature. With a single functional epoxy group, FR4 has a Tg of approximately 115 – 117jC. Using di-functional epoxy groups, FR4 has a Tg of approximately 125 – 130jC, while utilizing a tetra-functional epoxy group results in a 170 – 180jC Tg. When the board temperature reaches the Tg, the board transitions from a glass-like material to a flexible or rubbery material. During reflow and solder wave applications, the board may exceed the glass transition temperature for several minutes, causing the board to sag and warp. Potential electrical opens and solder bridges (electrical shorts) may result if the board sag is excessive. Processing at lead-free soldering temperatures (240–260jC), results in a much larger board sag and warpage compared to exposure to eutectic Sn-Pb soldering temperatures (220–235jC). Figure 11 depicts a di-functional epoxy FR4 circuit board exposed to a 250jC peak reflow temperature. Other polymeric dielectric materials utilized in the PCB industry include bisamaleimide-triazine (BT) or
TABLE 4 Component Features and Parameters That Influence Solder Joint Formation Component Features and Parameters . . . . . . . . .
Lead or Ball Configuration Component Construction (Carrier Type) Lead Pitch (Spacing) Solderball or Lead Size Die Size to Package Size Ratio Through-hole Diameter (Related to Component Pin diameter) Component-attachment pad size and definition Base Materials Package Size, and I/O Count.
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FIG. 11 Reflow induced warpage of a di-functional epoxy FR4 circuit board.
cayanate ester resins. These have Tg values in the range of 180–210jC but typically cost much more than FR4. Polyimide materials have a Tg of 210–230jC, which is significantly higher than BT or FR4. A comparison of glass transition temperatures for commonly used dielectric materials are given in Table 5.
B.
Reinforcement Materials
The reinforcing material selection influences overall structural properties of a laminate as well as the CTE. Most reinforced dielectric laminates use either electrical glass (E-glass), structural glass (S-glass) or chemical glass (C-glass) fibers as the reinforcing agent. The fibers are extruded through a die then wound in bundles, and woven into a cloth or mat. A coating (sizing) is often applied to the fibers to prevent breakage and assist in weaving operations. The epoxy resin fills in around the fibers during heating / curing and bonds to the fiber bundles. The dielectric laminate expands and contracts during heating and cooling of the product during assembly and applications in the field. The coefficient of thermal expansion (CTE) is a measure of the expansion in parts per million (PPM) per degree of temperature change. For example copper expands at approximately (15.5–17 PPM) / jC. Many of the dielectric and fiber systems are designed to have an expansion rate approximately equal to copper since copper is the most widely used conductor material in printed circuit boards.
C.
Pad Finishes and Deposition Techniques
To prevent pads from oxidation, a solderable layer or coating is deposited on PCB and component pad surfaces. The commonly used pad coating materials are listed in Table 6. In addition, several lead-free HASL coatings are being developed. These coatings may change the solderability of the pad and, consequently, affect the solder joint’s quality. For properly formed joints, a metallurgical bond must form between the lead-free solder (Sn) and pad surface (Cu or Ni). During reflow, the Sn reacts with Cu or Ni to form an intermetallic compound layer that is
TABLE 5 Average Glass Transition Temperatures (Tg) for Commonly Used Printed Circuit Board (PCB) Dielectric Materials Material FR4-Single Functional Epoxy Group FR4-Di-functional Epoxy Group FR4-Multifunctional Epoxy Groups FR4-Tetrafunctional Epoxy Groups BT-Bisamaleimide-Triazine Polyimide
Glass Transition Temperature, Tg, jC 117 130 155 175 200 230
510 TABLE 6
PRIMAVERA Commonly Utilized Printed Circuit Board (PCB) Pad Finishes
Finish Eutectic Sn-Pb Eutectic Sn-Pb Organic Solderability Preservative (OSP) Nickel/Gold Nickel/Gold Nickel/Palladium Silver-Organic Preservative Tin-Organic Preservative Nickel/Palladium/Gold
Application Methods Electroless/Immersion/Electroless Hot Air Solder Level (HASL)x Plated Spray/Dip Electroless/Immersion Electrolytic Electroless/Immersion Immersion/Codeposition Immersion/Codeposition
brittle but extremely strong. For properly formed metallurgical bonds between Cu or Ni and Sn, the interfacial strength is significantly higher than the plastic flow stress of the solder. Accordingly, the solder will rupture or fatigue due to thermally or mechanically-induced strains. However, many conditions can exist that prevent the proper metallurgical bonding to occur as listed in Table 7. For area array components surface finish solderability problems often leads to poor adhesion of the solder balls to the attachment pads. Poor solderability results in a low ball attachment yield, missing solder bumps, time zero joint failures (including dewetting) or weak interfacial strength. While Cu is commonly used as the primary electrical conductor in organic circuits boards, copper can not be exposed to the ambient because it tarnishes (i.e. becomes oxidized) which will adversely affect solderability [14]. Many surface mount components contain a wirebonded die which requires a metallic pad finish that protects the copper from oxidation and is suitable in thermo-sonic wirebonding. The ideal pad finish has the properties listed in Table 8. While the specific pad finish selected depends on the application conditions, it must exhibit a robust mechanical and thermal fatigue resistance. The selection of a solderable metal finish may however drive the failure mechanism within the solder from bulk fatigue to brittle interfacial failure, as could occur within the nickel–gold system [15]. There are several different ways to deposit a solder wettable finish on copper a chip carrier. For solder leveling, a simple dip, molten stream, or solder wave (solder fountain) can be used. A solder wave or fountain pumps a liquid stream of solder onto the board surface which coats all exposed metal surfaces. Three plating methods are used to deposit Ni, Au, Cu, Pd, Sn, and Ag onto metal surfaces used in the electronics
TABLE 7 Causes of Improper and Uniacceptable Intermetallic Compound Formation During Soldering Causes . . . . . . . .
Improper Amounts of Co-deposition Materials in the Plating Baths Oxidation of the Underlying Pad Surface Porosity in the Outermost Cover Layer Organic Contamination During Plating Soldermask Residue on Pad Surface Improper Fluxing Insufficient Reflow Temperature / Profile Inorganic Contamination
ELECTRONICS ASSEMBLY TABLE 8
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Characteristics of an Ideal Attachment Pad Finish
Characteristic Solderability Oxide Formation Environmental Resistance Thermal Stability Wirebonding Planarity Solder Reactivity Chemical Resistance
Requirements Highly Wettable with Solder Provide protection to the copper against oxidation Possesses a long shelf-life Tolerance of process and field temperatures Good bond formation in applications where needed Provide a flat finish Form a strong intermetallic bond with the solder Not degrade with typical fluxes or cleaning agents
industry, electrolytic deposition, electroless deposition, and immersion deposition. The deposition method affects the resulting physical and chemical properties of the finish deposited. The HASL and plating processes are discussed in the following sections. 1.
Hot Air Solder Leveling (HASL)
a. Method and Characteristics. In PCB applications that do not require chip-on-board (wirebond), tape automated bonding (TAB), a Au finish for connectors or low contact resistant pads, a thin layer of solder is sufficient in retaining the solderability of copper. A HASL pad finish is applied in the following fashion. The PCBs are fluxed and then dipped or immersed in a bath or stream of molten solder. The molten solder wets to any exposed solderable surface which it contacts. As the board exits a HASL chamber, hot air jets blow excess solder from the pads leaving a thin dome of solder. However, while in the molten state, a metallurgical reaction takes place primarily between the Cu base metal and Sn in the solder to form a Sn-Cu intermetallic compound. The air knives limits the amount of solder present on the pads, but this process results in variation, which can range from 30 to 1500 micro inches [14]. b. Intermetallic Compound Formation. The wetting and joining of solder to Cu whether deposited by HASL, plated Sn-Pb, OSP or Sn, results from the reaction of Sn with Cu. When tinlead solder is reacted with copper, two different copper-tin intermetallic compounds can form depending on the energetically favored reaction: Cu6Sn5 (tin rich phase) and Cu3Sn (tin poor phase). Intermetallic Compound (IMC) formation occurs in the liquid state but also exhibits temperature dependant growth in the solid state. When the solder is molten, the IMC formation and growth occurs at the solder side of the IMC, but forming at the base metal side of the IMC when the solder is solidified and there is sufficient temperature for diffusion to proceed [16]. The IMC formation is more rapid in the liquid state compared to the solid state. The rate of formation of Cu6Sn5 and Cu3Sn compounds is affected by the amounts of copper in the tin, as well as the temperature at which the reaction is taking place. In general, the higher the tin percentage (in SnCu systems), the higher the inter-diffusion rate. This implies that for high Sn lead-free solder alloys, the Cu-Sn intermetallic growth rate will be dramatically higher than in eutectic Sn-Pb solder systems. In general, intermetallic compounds are very strong, but brittle. However, extensive testing of solder joints created with Cu pads (Cu-Sn intermetallics) have not resulted in brittle failure of the intermetallic layer. Mixing of Cu and Ni/Au attachment pad finishes, however, can result in the formation of intermetallic structures that are extremely brittle, and have been shown to reduce the mechanical robustness of the solder to attachment pad interfaces. It has been shown that a ternary Cu-Ni-Sn intermetallic region can form at the interface between the eutectic tin/lead solder and a nickel pad finish. The formation of the ternary intermetallic can cause the solder joint to become weak, at the ball to pad, resulting in a non-fatigue failure at the intermetallic layer [15–19] as illustrated in Figure 12.
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PRIMAVERA
FIG. 12 Brittle failure of a BGA solder joint at the Ni pad layer.
2. Electrolytic Plating Deposition by electrolytic plating is an external electrically-driven process. This process is based on the discharge of metal ions from a cathode in a metal salt solution. Metal ions in the solution are reduced to the surface to be plated, which is charged with an electric current. The plated surface acts as the cathode and the bath acts as the anode, acting as a sink for the electrons [20]. When the metal containing salt solution is receives electrons from the current source (the copper pads), the result is the plating of a metal on the copper pads (Figure 13). The reaction that takes place at the sacrificial anode is the conversion of electrically neutral atoms to positively charged ions released to a plating bath; Me ! Mezþ þ ze
ð5Þ
The reverser eaction takes place at the cathode which provides the electrons required by themetalion to convert it to an electrically neutral metal atom; Mezþ þ ze ! Me
ð6Þ
Where, Me is the metal ion/atom species of interest in the plating cell. e represents the electrons z is the number of electron charges exchanged a. Faraday’s Law. Each deposition metal plates at a different current density and thus resulting in local thickness variations. Metal deposition occurs more rapidly in areas that have a higher current. The current density (charge per area) is typically greatest at sharp corners and edges, compared to flat regions. This behavior, for example, results in thick plating at the top of plated through vias. The electrolytic plating follows Faraday’s Law, so plating rate is proportional to current flow and cease when current is removed from the cathode. Therefore, plating thickness is a function of the time in the plating bath. Since deposition thickness is a function of the current density, the current density must be held constant in order to achieve uniform thickness. Maintaining a uniform current density is often difficult due to geometric factors such as plating through vias with a large (thickness / diameter) aspect ratio. Variation in thickness distribution leads to the plating of thicker than required or desired amounts to ensure all plated areas are fully covered. Thickness variation is a key drawback to the electrolytic process.
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FIG. 13 Schematic representation of the electrolytic plating process.
Typically, a plated deposit must be greater than 30 micro inches to ensure total and pinhole-free pad coverage. b. Thick Gold Layers. In PCB fabrication, copper, nickel , and gold are often plated an electrolytic process. For applications that require bonding Au wires to PCB carriers, a relatively thick layer (25-50 micro inches) of Au is plated to ensure the surface can be wirebonded. However, in soldering operations, if Au is plated excessively, and is subsequently dissolved into the bulk solder when molten, it can cause the bulk solder to become embrittled. Bulk Au embrittlement depends on the Au concentration, and the location of the AuSn4 Intermetallic. It has been reported that 2% Au is sufficient to cause bulk solder degradation. However, local Au concentrations at critical pad interfaces can cause layers of brittle materials at much lower Au levels [21]. Similar to the Cu-Ni-Sn system, a ternary Au-Ni-Sn intermetallic can form under certain circumstances which, if located at the solder attachment pad, can reduce the mechanical strength considerably. 3. Electroless Plating Unlike the electrolytic process, the electroless process does utilize an external electric current source to drive the plating reaction. The electrons necessary for the plating process to proceed are provided by through chemical reactions which take place in the plating bath. While both electroless and electrolytic plating require an electric charge/discharge current in the bath, only the electrolytic process utilizes an external source , to satisfy this requirement. In an electroless deposition process, the electrons are provided by a reducing agent. The chemical reactions that take place in the electroless bath are: RAxþ ! RAðxþzÞ þ Ze
ð7Þ
ð8Þ
zþ
Me
þ Ze ! Me
where, RA is a reducing agent, Me is the plated metal,
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PRIMAVERA x is the charge on the reducing agent Z represents the number of electron charges dispersed, e is an electron charge
The reducing agent is chemically reduced yielding ‘‘Z’’ number of electrons. The electrons combine with the metal ions in the bath solution and the electrically neutral metal atom is deposited onto the surface of the substrate. Phosphorous and boron based compounds are often used as the reducing agent in electroless plating baths, which are co-deposited in the plating process. The electroless process is referred to as an autocatalytic deposition process, which implies the deposition continues uninterrupted if reducing agent is present and the sample remains in the bath. However, in practice the electroless process is extremely sensitive process variables including to chemical levels in the bath. Thus it is often difficult to control electroless plating systems. A highly automated monitoring systems is used to track the bath chemical concentrations, pH level, temperature, and rate of reduction. 4. Immersion Plating Immersion metal deposition is a variation of electroless metal deposition. A major difference between immersion plating and electroless plating is that the immersion process is not autocatalytic. Immersion plating is a self-limiting process, and only continues if there are exposed ions on the plated surface left to be exchanged. The process is based on an atomic exchange reaction in which a metal ion taken from the bath. The reaction ceases when there are no exposed base metal ions. Therefore, samples left in the bath for extended periods of time do not increase in plating thickness. This process provides a very thin and uniform layer. In some applications, such as wirebonding, an immersion plated thickness is not sufficient. a. Mechanism. The immersion process is characterized by an exchange of ions between the surface to be plated and the plating solution, where the base metal acts as the reducing agent in this process. Parts to be plated are immersed in a solution of metal salts. A metal ion from the solution partially reduces an atom on the surface of the metal to be plated and simultaneously deposit itself at that surface site [22]. The chemical reactions which occur are: MeA ! Mezþ A þ Ze
ð9Þ
Mezþ B þ Ze ! MeB
ð10Þ
Where, MeA is the original or base metal MeB is the metal to be plated Z is the number of electrons lost/gained e is the electron charge
D.
I/O Pad Design
For area array products utilizing eutectic or near eutectic Sn-Pb alloys, a symmetric design (component pad = PCB pad) balances reliability needs and assembly robustness. While a large pad size is critical to increasing yields, smaller pads lead to higher reliability. Thus, there is an inherent tradeoff between manufacturing yields and reliability. In addition, increasing the pad size can reduce the available space to route conductors between attachment pads on the surface of the PCB. The observed reduction in solder wetting of lead-free alloys on many pad finishes requires pads to be smaller than those for eutectic Sn-Pb soldering. For both lead-free and eutectic Sn-Pb solder area-array components, smaller pads increase standoff and trace routing density on PCBs. However, components with a large amount of ball coplanarity variation will potentially result in an open joint if the pad size is small, and the gap between the component and PCB is large. Therefore, a good starting point would be to have a PCB pad approximately the same size as the component pad to balance standoff height with assembly robustness. Circular pads provide a uniform joint shape, minimize surface energy, and maximize the standoff height for area-array components.
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1. Pad Definition Type In general, the attachment pad solder mask opening on a circuit board is larger than the metallized pad size, which allows the solder to wet the entire pad top and sides. Pad-defined geometry is preferred because it prevents mask residue to be on pads, avoids stress concentration at mask / joint edge, and gives the best registration to vision fiducial features. Both the pad and mask defined configurations are illustrated in Figure 14. In addition, the aperture size control is typically better than mask positional control. Pad-defined geometry provides a mechanically more robust joint due to interlocking of the solder around the top and sides of the attachment pad with an increased attachment surface area. This ultimately lengthens the time to fully propagate a stress induced fatigue crack in the solder joint since there is an increase in the crack path length and the crack is forced to change direction to propagate around the attachment pad (Figure 15). When possible, utilization of a pad-defined geometry is preferred over solder-mask-defined pads since mask residue remaining on the pad surface following solder-mask developing can cause poor solderability. In addition, many cured solder-masks are brittle and often break near the mask edge. Some masks are cured by exposure to UV light, which cures the surface of a mask to a greater extent than the bulk material. Consequently, during etching, undercutting of the top of the mask can occur which along with the mask edge can entrap contaminates. An additional reliability benefit of a pad-defined geometry compared to SMD pads is provided by the mechanical interlocking of the solder around the pad and the absence of a sharp stress concentration caused by the solder-mask edge. 2. Via Designs Via-in-pad designs allow a designer to avoid many routing difficulties utilizing conventional fan out patterns. While the micro-via design adds extra dielectric and Cu layer(s), it actually may reduce layer count depending on space savings of routed area and elimination of some through holes. Fine-line features may require the use of very thin copper foils to allow for feature definition during the etching process. However, with the use of ultra thin dielectrics, there is a question of whether the materials can provide sufficient voltage breakdown resistance and prevent electrical cross talk. Copper foil weight used for fine-pitch applications are typically much lower than standard PCB weights. For area array devices, half ounce and quarter ounce weights are acceptable, while direct chip attach applications may require eighth ounce foil weights. The
FIG. 14 Pad geometry, a) non-solder mask defined and b) solder mask defined.
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PRIMAVERA
FIG. 15 Crack propagation path for non-solder mask defined pad geometry.
use of thin foils although necessary for line and feature definition, are more difficult to process, for example, are easily removed during etching, stripping, deburring, and scrubbing operations. 3. PTH Via Pads Plated through vias should be covered with a solder-mask to prevent solder wicking into the vias. In addition, the covered via prevents the component from soldering to the via pad in the case of component misplacement. Depending on the hole diameter, solder-mask may not completely cover or tent over a hole. In those instances, covering the via annular ring with a mask is sufficient to prevent solder wicking into the PTH. Dry-film solder masks can tent large PTHs while liquid solder masks can typically cover 0.020VV diameter holes or smaller. In addition to PTH routing for standard surface mount devices, tented and plugged vias are required in flip chip applications to prevent void formation in the underfilled assembly as shown in Figure 16. In general, a ‘‘dogbone’’ structure is used to connect area-array PCB pads and PTH via pads. When connecting two adjacent pads (i.e. via-to-via or via-to-SM pad) the copper trace used to connect the pad features must be smaller in width than either of the pads. This reduction is required to prevent lifting of the solder mask from the copper trace which could result in solder wicking beneath the solder-mask as illustrated in Figure 17. In general solder-mask adhesion to a dielectric layer is higher than the adhesion of solder-mask to copper. In wave soldering applications, solder can wick along PTH barrels and lift the solder-mask over the conductor traces
FIG. 16 Flip chip void caused due to a plated via underneath the die.
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FIG. 17 Solder wicking into PTHs from underneath the solder mask.
leading to PTH capture pads. Therefore it is very important to reduce the trace size connecting to PTH capture pads. When assembly is performed using a lead-free solder, the higher process temperatures degrade the mask adhesion more readily compared to reflow using eutectic Sn-Pb. An additional benefit of a reduced trace width is the increased space between Cu features. Pad and routing guidelines for lead-free soldering are provided in Table 9 for area array and leaded components. 4. Via-in-Pad Design Via-in-pad designs are preferred over dogbone designs because they maximize routing density. The increased space between Cu features provides more routing space. Traditional through-hole requires space for a drilled hole on every layer of the PCB since the hole is drilled through the entire laminate structure. However, a blind-via structure requires routing space only on individual layers since the via is fabricated only from layer-to-layer. This provides additional routing channels for conductors on inner layers, and allows the space on the opposite side of a chip carrier to be utilized for additional circuitry. There are several potential drawbacks to via-inpad designs including void formation around the via, and higher cost compared to conventional routing technology. An example of a via-in-pad solder joint with a trapped void, is depicted in TABLE 9 Design Recommendations for Lead-free Printed Circuit Board (PCB) Pads for both Area Array and Peripheral Leaded Components Area Array Components Feature PCB pad size Dog-bone trace
Recommendations
Application
1:1 With Component 20% larger than component 7–8 mils in width 5–7 mils in width 4–5 mils
Eutectic Sn-Pb or lead-free High Lead 10/90, 5/95 Sn-Pb 1.5–1.27 mm Pitch 0.8–1.0 mm Pitch 0.5–0.75 mm pitch
Peripheral Leaded Devices Feature Attachment pad width Attachment pad length Pad Location
Recommendations Maximum of 75% of pitch 130% of lead width 3x foot length 2.5x foot length Center of heel in pad center
Application Eutectic Sn-Pb or lead-free Eutectic Sn-Pb or lead-free Eutectic Sn-Pb Lead -free Eutectic Sn-Pb and lead-free
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FIG. 18 Solder joints for conventional and via-in-pad structures. (a) Solder paste deposit on conventioanl pad, (b) solder joint assembly for conventional pad, (c) solder paste reflown on via-inpad, (d) assembly on a via-in-pad structure.
Figure 18. The void is formed by air entrapped during the print process as occurred in a cross section of dry solder paste (Figure 19). Experimentation has demonstrated a reduction in the occurrence of via-in-pad voids through PCB design or printing process modifications. Several options for void reduction are listed in Table 10. a. Voids. Void reduction in a via-in-pad construction is shown in Figure 20, utilizing a socalled double print process. Double printing is accomplished by printing the paste in one direction on the stencil, and then reversing the print squeegee motion and printing the same board again before lifting the stencil foil from the PCB surface. An example of pre-filling the via with solder from a HASL machine is shown Figure 21. Several other approaches can be utilized to close the via which include plating and filling the vias with epoxy or conductive polymers. Via-inpad voiding occurs at a higher rate utilizing lead-free solders compared to eutectic Sn-Pb soldering due to the observed reduction in wetting. In a eutectic Sn-Pb solder joints, the void may be displaced by the solder as it wets the via, while this does not typically occur with lead-free alloys. Recommendations for via-in-pad designs are given in Table 11 for eutectic Sn-Pb and lead-free solder applications.
FIG. 19 Solder paste deposits in via-in-pad structures.
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Options for the Reduction of Via-in-pad Voids
Operation / Feature
Method
Solder Paste Printing
Increased print pressure and slower print speed Double print stroke Pressurized cartridge Solder filled via (HASL) Plated or filled vias Offset via-in-pad design / offset print
PCB Enhancement
5. Dimensions versus Solder Wetting A key pad design consideration when utilizing lead-free solders is the reduction in solder wetting and spreading compared to eutectic Sn-Pb solder. A comparison of solder spread on copper pads for eutectic Sn-Pb solder and several lead-free solder alloys is shown in Figure 22. This indicates that the entire pad surface may not be covered with solder for lead-free applications. For eutectic Sn-Pb solder, post assembly visual inspection of PCBs typically includes assessing solder pad coverage. A failure is typically indicated if the attachment pad is not fully covered with solder. If the requirement for 100% pad coverage is applied to lead-free soldering, the reduced wettability of many lead-free solders would cause an increase in exposed-pad failure rate. Therefore, the pad size for lead-free soldering should be smaller that a comparative pad that utilizes eutectic Sn-Pb to prevent exposed pads. An example of incomplete pad coverage is depicted in Figure 23, where a through-hole capture pad is not fully covered with solder when the pad is 0.03 inch larger than the PTH but does fully cover a pad 0.02 inch larger than the PTH. For area-array devices utilizing lead-free solder, a one-to-one PCB-to-component pad size is recommended since the area to wet is small compared to the solder volume of the ball and printed paste deposit. For discrete components, the pad size should be reduced in both SMT and wave soldering application to ensure complete pad coverage and adequate fillet formation. Large pads on discrete devices will result in small fillets as shown in Figure 24. For leaded devices, the attachment pad length for lead-free soldering should be shorter than pads for eutectic Sn-Pb to avoid exposed pad area, and to concentrate more solder at the heel fillet. Another area of concern for lead-free soldering of leadframe devices is the reduced solder wetting of the component lead. The solder will climb higher on a lead when using eutectic Sn-Pb solder compared to lead-free solder. The reduced lead
FIG. 20 Reduction in via-in-pad voiding due to double solder printing method. (a) Top view (flat section) of dry paste in a via hole. (b) Vertical cross-sectional view of dry paste on a pad with a via hole. (c) Cross-sectional view of pads with a via after reflow. The voiding is minimal. (Courtesy of Universal Instruments Corporation).
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FIG. 21 Utilizing the hot air solder leveling (HASL) process. (a) A conventional pad coated with SnPb solder. (b) A via-in-pad is filled and coated with sn-Pb solder. (Courtesy of Universal Instruments Corporation).
wetting can result in an increase in soldering defects if the printed solder volume is not properly selected for the lead-free alloy and component lead finish selected. Excessive solder deposits could bridge adjacent leads if solder does not climb sufficiently up the component lead.
IV.
OTHER ASSEMBLY MATERIALS
A.
Fluxes
Since successful solder wetting and attaining yield targets depends upon the flux used in SMT applications, it is important to carefully consider a variety of flux characteristics including; viscosity, quantity and type of post-reflow residue, and solids content. Screening tests, discussed later in this section, are to be performed to identify viable flux candidates, and only those that meet the process requirements should be selected. The use of fluxes that require cleaning postreflow residues were common for SMT assembly. The use of area array components, particularly large ball grid arrays (40-50 mm) has prompted utilizing fluxes which do not require post-reflow residue removal from PCBs. The residue in no-clean flux systems is rendered inactive following
TABLE 11
Recommendations for Via-in-Pad Designs
Feature Pad size Minimum pad size PCB dielectric Via size Via plating Via taper Glass transition temperature Dielectric type
Recommendation
Application
PCB 1:1 with component Via + tolerance (+/ 2 to 3 mils) 1/2 via diameter maximum 5 to 6 mils in diameter Minimum 0.5 mil 1 to 2 mils total 130jC minimum 175jC minimum Reinforced
Eutectic Sn-Pb & lead-free Eutectic Sn-Pb & lead-free Micro via layers When space allows Wall thickness Positive (top > bottom) Eutectic Sn-Pb Lead-free alloys For laser process
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FIG. 22 OSP.
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Solder paste spread test comparison of eutectic Sn-Pb and two lead-free solders on Cu with
exposure to high temperatures during reflow operations. It is difficult to remove residue beneath a BGA component during cleaning. The remaining residue poses a potential reliability problem because salt and metal dendrite bridges may form between conductor pads. In general, no-clean fluxes are not as aggressive as solvent cleanable fluxes. 1. Pb-Sn versus Lead-free Alloys A flux system must be designed to be compatible with a particular solder alloy system. For example, typically the activation and volatilization temperatures for the eutectic Sn-Pb system are lower than lead-free alloys. In lead-free reflow, the soak or stabilization temperature may be in the range of 160 to 170jC compared with 140 to 155jC for eutectic Sn-Pb solder reflow. In addition, the lead-free peak temperature may approach 240 to 250jC compared with 220 to 230jC for eutectic Sn-Pb. At the higher lead-free process temperatures, fluxes vaporize more rapidly and completely compared to standard temperature profiles utilized for eutectic Sn-Pb solder. Often there is insufficient flux left on a board due to volatilization. The volatilization
FIG. 23 Photograph of through-hole incomplete pad wetting and incomplete fillet formation.
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FIG. 24 Lead-free surface mount assembly of a discrete component.
occurs due to fluxes which have not been properly formulated to withstand the higher process temperatures typically required of lead-free solder alloys. Wetting and solderability of lead-free alloys has been observed to be reduced compared to eutectic Sn-Pb solder on both copper and gold pad finishes. A wetting comparison between a lead-free solder alloy and eutectic Sn-Pb is given in Figure 25. The spread pattern for both eutectic Sn-Ag and eutectic Sn-Pb samples consisting of a 0.03 inch diameter solder sphere reflowed to a 0.1 inch diameter pad is shown in Figure 26, (a tacky flux was applied with a brush). 2. Chemical Activity To achieve a sound solder joint, all the products created through environmental attack of the metal surface to be soldered, usually oxides, must be removed to expose the surfaces to be bonded. The chemical activity between a flux and surfaces to be bonded are of two types. In the first type, a flux and impurities react to form a compound which is soluble in the flux or its vehicle. In the second type, the flux reduces the impurities to their original form (i.e., Metal-oxide reduces to atoms of the base metal and oxygen) thereby exposing the metal surface, which is now ready for bonding [23].
FIG. 25 A solder wetting comparison between eutectic Sn-Pb solder and eutectic Sn-Ag reflowed on an electroless Ni/Au (ENIG) surface. (Courtesy of Universal Instruments Corporation).
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FIG. 26 Comparison of the solder wetting between eutectic Sn-Pb and eutectic Sn-Ag using 0.03 inch diameter solder spheres reflowed to 0.1 inch diameter OSP-Cu pads with flux applied. (Courtesy of Universal Instruments Corporation).
3. Thermal Stability Once a flux reacts to remove the surface contamination, the flux must leave a protective coating on the cleaned metallic surface at the soldering temperature. Otherwise, the freshly exposed metallic surfaces easily reoxidize in the atmosphere, and is accelerated by the elevated soldering temperatures. As noted previously, a flux must be capable of withstanding soldering temperatures without evaporating or breaking down. The breakdown of a flux material leaves undesirable deposits which are difficult to displace with molten solder leaving those areas inaccessible for solder wetting. Moreover, these deposits are also difficult to remove with solvents during cleaning. For example, rosin which is used in many fluxes, will char at 285jC. 4. Flux Activation A portion of flux materials consists of active chemicals whose purpose is to remove contamination from the surfaces to be joined. The flux activation requires exposure of the flux to an elevated temperature for an extended dwell time, which typically begins at 125 to 150jC for eutectic Sn-Pb fluxes. It is very important that the flux reaction range is compatible with the solder system of interest. For example, fluxes designed for high lead (5-95 Sn-Pb) typically activate at temperatures greater than 250jC. Once the activation temperature is reached, removal of the oxides begins and wetting can occur. The temperature range over which flux activation occurs is called the activation temperature. For many fluxes, a dwell time at the activation temperature is required to allow sufficient time for oxide removal. While this dwell time is specific for each flux chemistry, it is typically in the range of 2 to 3 minutes. When organic fluxes are heated beyond their activation temperatures, the chemicals within a flux can breakdown and begin to lose activity, and exhibit a reduced ability to react with the surface contamination. Therefore, to assure that contaminants are properly removed from surfaces to be soldered, fluxes should be heated to a temperature in which they are active for a sufficient period before being in contact with the molten solder. The so-called inactivation temperature is the temperature at which the breakdown of a flux is complete, and the flux no longer reacts with the surface contaminants. In no-clean flux systems, once a flux is exposed to the inactivation temperature for a sufficient period of time, then the residues of the flux compounds become chemically inert. 5. Copper Mirror Test The activators typically used in fluxes are corrosive. A flux can corrode the solder joint, copper traces and circuitry both before reflow and post reflow. That is, corrosion can occur during the assembly process subsequent to solder paste deposition, while the work is being processed through the assembly line. In addition, corrosion may result from the activators that remain on the board post reflow. A copper mirror test is used to determine the corrosive effect of the flux on a copper film deposited on a glass slide. The ability to classify flux activity levels helps to determine
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the working life of a paste before reflow must occur. The copper mirror test as outlined in IPCTM-650, TM 2.3.32, requires a droplet of flux to be placed on a glass slide that has 5000 A˚ copper deposited on the surface. A droplet of 25% WW rosin flux is placed on the slide as a control material. Typically, the sample is placed into a temperature / humidity chamber for 8 hours, 1 day, 3 days and 7 days at 30jC / 60% RH. The slide is examined for evidence of copper removal for both the control flux and the flux being tested. 6. SIR Testing The materials used to fabricate circuit boards and component chip carriers have certain electrical properties which includes the resistivity of the surface layers. A test that measures the resistance to current flow between adjacent surface conductors is called a surface insulation resistance (SIR) test. When exposed to moisture, conductive ions present on the surface of the PCB dielectric layer will be dissolved into the surface moisture layer. When a biasing voltage (+/) power is applied to each surface conductor, the mobilized metal or salt ions can link together to form dendrites or conductive bridges between the conductors. IPC-TM-650, TM2.6.3.3, outlines the specific test procedures for performing a SIR test. Typically, a pattern of interdigitated conductor ‘‘combs’’ are utilized in the SIR test. The conductor patterns typically vary in size from 0.4 mm down to 0.05mm, with conductor spacing varying from 0.5mm to 0.05mm, with the fine pitch patterns being utilized for testing high density PCB materials. Standard PCB laminates utilize a 0.4 mm conductor and 0.5 mm space, as outlined in IPC-B-24 and ANSI J STD-004. The bias voltage used in SIR testing is 48+/ V on each conductor. Resistance measurements are made initially, and following 24 hour, 96 hour, and 168 hour exposure to 85jC 85% RH conditions. The 96 and 168 hour resistance measurements are required to exceed 100M V. Fluxes utilized in PCB assembly processes, can decrease surface dielectric resistance of a PCB by supplying additional metal or salt ions on the board surface. The resistive value is a function of the space between conductors, and area common to conductors on other layer of the PCB. Therefore, the SIR values will typically decrease as the spacing between conductors and layer thickness decreases in the PCB. During Flux SIR testing, the test comb pattern is treated with a flux, by a spray or dipping method. The initial resistance is measured between the conductors of the comb(s) at the beginning of an environmental conditioning period and again after exposure to the required test conditions. In general, SIR values will decrease when flux is applied to the comb pattern compared to test resistance level of bare combs. 7. Halide and Fluoride Content Tests Tests for chlorine, bromine, and fluorine content in fluxes are required as per IPC-TM-650, TM 2.3.33 and TM 2.3.35. The presence of these materials cause a reduction in the SIR and can accelerate corrosion of the PCB conductors and assembly solder joints. A test for chlorine and bromine is conducted by placing a droplet of flux on a silver chromate paper, which turns yellow or white if the halides are present. Presence of fluorine is determined by adding a droplet of purple zirconium alizarin to the flux region. A change in color from purple to yellow indicates fluorine is present.
B.
Components
Lead-free versions of components typically utilized for electronic applications include area array, peripheral-leaded devices, and passive (capacitor and resistor) devices. 1. Leads The metallurgy utilized for terminations and protective solderable coating on lead-free leaded devices includes a variety of alloys, as listed in Table 12. Gold and palladium coatings are often used on lead-frame devices because Au and Pd surface layers are used in both soldering and wirebond applications. Since many leadframe devices utilize wirebond technology to interconnect the chip integrated circuit, a coating is required that can accommodate wirebonding. In order to avoid a two-step metallization process, the gold or palladium layer can be used to coat the
ELECTRONICS ASSEMBLY TABLE 12
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Lead-free Pad Termination Finishes
Finish/Process/Material Electroless and electroplated nickel/gold (Ni/Au)
Immersion silver (Ag) Immersion and plated tin (Sn)
Electroless nickel/palladium (Ni/Pd) Nickel-palladium-gold (Ni/Pd/Au) Tin-silver (Sn/Ag) Tin-silver-copper (Sn/Ag/Cu)
Application Surface mount terminations Through-hole pins Area array pads Area array pads Area array pads Surface mount terminations Through-hole pins Surface mount terminations Surface mount terminations Area array pads Area array pads
entire leadframe, including the external solderable lead portions and internal wirebond regions. Other metallizations require a multiple alloy process, consisting of a wirebondable that metal is applied to the internal regions, and a solderable coating applied to the leads. 2. Temperature and Moisture Sensitivity All aspects of a component including the base materials, body type, lead configuration, and solderable surface materials, must be considered when designing and evaluating components for lead-free assembly. Many component part numbers currently designed for eutectic Sn-Pb solder reflow conditions will be phased into lead-free versions. The lead-free versions must be requalified to the higher reflow temperatures required of most lead-free alloys, and acceptable moisture sensitivity level (MSL). The JEDEC and IPC standards for eutectic Sn-Pb processing require components to withstand qualification testing at a peak temperature of 225–230jC. Of particular concern is moisture sensitive components since they rapidly absorb moisture into critical die/substrate and die-to-adhesive interfaces. When exposed to rapid heating conditions as occurs during a component-attachment reflow operation, moisture within a package vaporizes causing a rapid increase in pressure within the package, since the vaporized water (i.e. steam) can not escape the package. If the pressure exceeds the bond strength of the die-to-carrier, adhesiveto-carrier, or die-to-adhesive layers, delamination occurs at those interfaces or cracks created to relieve the vapor pressure build up, as illustrated in Figure 27. Overmolded devices can experience similar pressure-induced failures with the mold material cracking apart during rapid heating. However, typically molded lead frame components are not as moisture sensitive as organic area-array components, since they have fewer interfaces for moisture to invade. BGA and CSP components are available in various package configurations including overmolded, flex carrier, rigid carrier, and several wafer-scale formats. Each component exhibits a moisture sensitivity which is generally related to exposed surface area that can absorb moisture. Several component-related parameters including; component body size, number of chip carrier layers, and material type, have an affect on the moisture absorption and desorption rate. For example, laminate carrier BGAs absorb a larger amount of moisture compared to CSPs with a similar laminate carrier construction. This is due in large part to the greater surface area of BGA components compared to CSPs. Figure 28 compares the moisture uptake curve of a plastic BGA and plastic CSP device, which both have a FR4 laminate substrate and molded body construction. 3. Packaging and Preparation A rigorous component handling strategy must be adopted when using moisture sensitive components. Moisture sensitive packages should be baked prior to being assembled to avoid vapor-pressure induced failures. Packages with large exposed areas of exposed epoxy mold resin,
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FIG. 27 Moisture-induced delamination in components. (a) Illustration depicting delamination between the die attachment material and the chip carrier. (b) Photograph of a delaminated component shown in cross section.
FIG. 28 Moisture up-take curves for several typical BGA and CSP components under stress test conditions (30jC, 60% RH). (Courtesy of Universal Instruments Corporation).
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laminate edges, or polyimide layers, should be baked at 125jC to expel moisture from the package. The actual bake time required depends on the particular device, but as a rule of thumb, plastic BGAs require a 24-hour bake period while 4 hours is sufficient for many CSPs. Other component such as ceramic packages, chip capacitors and resistors, and hermetically-sealed components typically are not baked since their moisture uptake is extremely low. For lead-free assembly, moisture sensitivity tests must be performed at reflow temperatures corresponding to the alloy selected. In general, the peak temperature a component or PCB may experience in reflow is 20–25jC above the melting point of the solder to account for temperature variations across an assembly. Using this rule of thumb, a lead-free moisture sensitivity test is to be performed at reflow temperatures of approximately 250–260jC. However, in an effort to minimize the effects of an increased reflow temperature (on moisture sensitivity, and thermal degradation of materials), peak reflow temperatures of approximately 245jC are utilized in that functionally-acceptable solder joints are created at this lower temperature.
C.
Adhesives
In wave solder applications, bottom-side SM components are held in place by an adhesive deposit to prevent the movement or loss of a component into the molten solder wave. A key requirement for an adhesive is the ability to retain components and maintain their orientation on a PCB when traveling through a solder wave or air knife. Adhesives are deposited on a board by dispensing, pin transfer, printing, or jetting techniques. An adhesive droplet is typically deposited within the component outline utilizing a single or multiple droplet pattern. Once the adhesive is deposited, components are placed onto their corresponding attachment pads, and the component body is in contact with the adhesive. The adhesive is then cured in an ultra-violet or thermal oven to assure the components are retained to the board. Once in the molten solder wave, the solder wets the prefluxed exposed metallized surfaces. If the solder wave temperature of a lead-free alloy exceeds 260jC the adhesive may be charred, or cause adhesive delamination from the board or component. In addition, fluxes must be selected which do not degrade the adhesive material during a wave assembly process.
V.
ASSEMBLY PROCESSES AND TOOLS
Solder joint quality is heavily influenced by the quality achieved at the individual assembly steps. Factors such as reflow methodology, (convection, versus IR), and atmosphere significantly affect solder wetting, joint formation/shape, and the presence of voids. Resulting joint quality is a function of almost all assembly variables but is strongly influenced by the type of paste/flux, attachment pad metallurgy and reflow conditions. Highly irregular shaped joints; excessive voiding and poor solderability may lead to early failures. An insertion-mount assembly process consists of part insertion, cutting and bending of inserted leads, a fluxing operation, and exposure to a molten wave or bath of solder. During lead insertion, the exposed wire or termination lead is placed into and through a plated hole in the circuit board. The termination/lead is typically much longer than the board thickness and must therefore be trimmed to size to allow proper formation of a solder fillet. The component leads are trimmed to a size that will typically allow just enough of the lead to protrude 0.05 to 0.1VV below the bottom of the circuit board. One or several leads on each device are bent to prevent the component from falling out of the circuit board during transportation and assembly. Before soldering, the circuit board is sent through a fluxing machine to ensure the component leads, circuit board pads, and plated through holes are coated with a sufficient layer of flux. Following fluxing, the circuit board is sent through a molten wave of solder. The solder then reacts with all exposed metal surfaces forming a bond between the solder and the metal layers. The typical assembly process for surface-mount, area-array devices consists of solder deposition (Figure 29), component placement (Figure 30), reflow soldering (Figure 31), and transportation, as shown in Figure 32.
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PRIMAVERA
FIG. 29 Solder paste printing. (a) Solder stencil. (b) Solder paste printed onto PCB pads. (c) Stencil printing machine (Courtesy of DEK Printing Machines).
For pin-in-paste, through-hole applications, the assembly process follows the SMC assembly procedure. The process steps and machine configurations for SMC and through-hole assembly operations depend on the component type and their location on a board. There are three standard classifications of PCB [2], Single Side SMC (Type I), Mixed SMC and through-hole (Type II), and double-side SMC (Type III). Each process utilizes a unique set of assembly equipment. Manufacturers generally utilize the equipment shown in Figure 33, for Type I and Type III assembly operations. Process steps are modified depending on the type of products being assembled. The surface-mount, PCB assembly process sequence used for eutectic Sn-Pb solder can also be used for lead-free soldering with some minor process adjustments. The equipment required for surface mount assembly includes; a stencil printer, component placement machine, and reflow oven. The tooling required for each assembly step should be designed achieve desirable process conditions and to facilitate the assembly operation. The methods used for the various processes are described in this section.
FIG. 30 Component placement. a) A BGA component being placed onto its corresponding PCB attachment pads. b) Peripheral-leaded devices (SOICs and QFP) being inspected by an upward looking camera prior to placement. The camera inspects the components for both feature location and lead damage. (Courtesy of Universal Instruments Corporation).
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FIG. 31 Reflow of a printed circuit board (PCB) assembly. (a) Data logger and thermocoupled (T/C) PCB for thermal profile creation. (b) Assembled product exiting a reflow oven on edge rails and a PCB pallet fixture. (Courtesy of Universal Instruments Corporation).
A.
Types and Origins of Solder in Solder Joints
In SMC and area array assembly, paste deposition and/or pre-formed solder spheres are utilized to create a solder interconnection between a component and PCB. Many BGA and CSP components utilize a eutectic or near eutectic Sn-Pb solder alloy. Some BGA components utilize dual metal solder joints, which consist of a high-melting (above 300jC) alloy (10–90, Sn-Pb) solder ball as part of the solder joint to prevent the device from collapsing during solder reflow. The highmelting solder ball is attached to the component with a low-melting solder (i.e. eutectic Sn-Pb). Most industry standard BGA solder balls consist of a low-melting solder (i.e., eutectic Sn-Pb, Sn/ Ag/Cu, Sn/Ag/Bi, etc.), which melt during the reflow process and collapses to an equilibrium state. The final equilibrium joint height depends upon the solder volume, pad dimensions, package weight, and the buoyant force provided by surface tension of the molten solder. A sufficient solder volume is provided by the eutectic solder balls of BGA/CSP components to achieve interconnection, however, a device may not posses the coplanarity which is necessary to ensure that each solder joint properly formed. In SMC assembly, the bulk of the solder comprising a solder joint must be externally supplied since the combined component lead and PCB pad solder volume is not sufficient to form a functionally-adequate interconnection. However, in the case of mono-metal BGA and CSP component, the solder balls are the major source of solder used to create the solder joints between the device and PCB. For example, a 1.27-mm pitch BGA typically utilizes a 0.6 to
FIG. 32 PCB transportation system. Circuit cards being transported between assembly process equipment (pick and place) and a reflow oven. (Courtesy of Universal Instruments Corporation).
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FIG. 33 Representative SMT assembly line. The tools depicted in the photograph are: (a) stencil printer, (b) turret-style placement machine, (c) fine-pitch gantry style placement machine, and (d) reflow furnace. (Courtesy of Universal Instruments Corporation).
0.65-mm diameter solder ball whose volume is 10–20 times larger than the corresponding externally supplied solder paste deposit.
B.
Solder Paste Printing
Solder paste stencil printing is the most common solder deposition method for SMC assembly. In this process, solder paste is deposited onto the PCB attachment pads through corresponding holes in a metal foil, referred to as a stencil. 1. Stencils and Solder Deposits The printed solder-paste volume is an important process variable, with a significant impact on assembly yield. Insufficient solder paste volume may result in electrical opens while excessive solder paste volume increases the chances of bridging resulting in electrical shorts. Printed paste volume is determined by several parameters. The stencil design including aperture condition, shape, size, spacing, and tapered edges, along with stencil thickness, and fiducial deviation has a significant influence on the printed paste volume. a. Stencil Apertures. Depending upon the stencil manufacturing process (laser cut or chemically etched apertures), the difference in the aperture wall roughness might be substantial. In order to achieve optimal solder paste transfer, an aperture designed with tapered edges should be used. Aperture shape and size are typically dependent upon the pad design. For example, leaded devices typically have rectangular pads and stencil apertures, while BGAs may have circular pads and stencil apertures. In assembly of leaded devices, solder paste can bridge between leads or adjacent PCB pads if the solder paste volume is excessive, the paste slumps, or if the paste is displaced by the component lead during placement. In order to ensure good print quality and avoid bridging of leaded components, the stencil aperture is typically reduced to 75–80% of the solder pad width. b. Printed Solder Volume. Over printing (where the aperture size is larger than the pad size) is not unusual when a substantial amount of paste must be deposited on a pad which is typical for BGAs. Overprinting is often required for fine-pitch, area array components such as CSPs to compensate for low-volume transfer efficiencies as is the case for 0.5-mm pitch CSP printing. The diameter of a round aperture shape can be increased in proportion to a corresponding pad size, or asymmetrically to create oblong apertures. When overprinting is practiced, the spacing between adjacent apertures is reduced compared to that between corresponding pads, increasing the chance for solder balling and bridging during reflow. Solder paste volume can also be increased by increasing the stencil thickness. However, as the solder
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paste stencil thickness increases, the solder paste release characteristics degrades, reducing the amount of paste transferred through the aperture. 2. Paste Transfer Ratio Printing circular features, commonly used in area array devices, greatly reduces the amount of paste transferred through an aperture compared to rectangular apertures, which are commonly used for peripheral-leaded components. Aperture size and stencil thickness must be properly adjusted to ensure the highest transfer ratio (paste deposited versus aperture volume). In general, an aperture should be slightly oversized compared to the size of its corresponding attachment pad to increase the solder deposit volume and transfer ratio. However, overprinting may lead to an increase in solderball and satellite formation since a portion of the paste deposit is printed onto the PCB laminate and solder mask surface. Solder does not wet to the dielectric mask and laminate surfaces during reflow. The solder should coalesce into a single mass wetted to the component lead and PCB pad. However, imperfections in the dielectric surface may prevent the paste from coalescing and cause small extraneous solder balls to form referred to as satellite balls. This trend is more prevalent in lead-free solders, since the wetting of these solders to a metallized surface is not as good as eutectic Sn-Pb solder. 3. Lead-free Solder Pastes While the exact printing performance of individual lead-free solder pastes vary, in general, a reduction in paste roll, transfer characteristics, or print quality has not been observed. That is, when comparing the paste roll on a solder paste stencil, there is no noticeable difference in paste bead characteristics except color as noted in Figure 3, which compares the paste roll between eutectic Sn-Pb and Sn-Ag-Cu pastes. In addition, the release quality of lead-free pastes from a stencil has not been noticeably different compared to eutectic Sn-Pb paste. 4. Stencil Printer The process parameters key to the stencil printing process include the squeegee type and hardness, print speed, print pressure, and print gap. An optimal stencil printer setup provides a clean sweep on the stencil surface and a repeatable solder paste deposition process. Shore A scale polyurethane squeegee hardness level between 85 to 95 is appropriate to achieve repeatable solder deposits for lead-free solder pastes. Print parameters such as the print speed, print pressure, and the print gap are adjusted to accommodate the variety of solder paste rheologies available. There are no specific equipment modifications necessary to stencil printer lead-free solder pastes.
C.
Fluxing
Fluxing plays an important roll during PCB assembly since flux is used to prepare and clean metal oxides from the solderable surfaces of an assembly. It also removes oxides from the solder paste particles themselves. Flux is typically dispensed on PCB pads as an ingredient of solder paste. However, some applications require the application of flux itself to PCB sites. In a traditional IMC process, the component leads and PCB board surfaces are exposed to a fluxing operation prior to exposure to a molten solder wave. The specific chemical compatibility between a lead-free flux and PCB or component materials for example solder mask, must be examined for lead-free applications. Fluxes used in lead-free applications should be compatible with the materials used while providing the basic cleaning functions, even though reflow temperatures are higher than eutectic Sn-Pb. That is solder paste suppliers must provide fluxes that take into account the complex chemical interactions between a flux and metal pads and lead surfaces during lead-free process conditions to ensure proper oxide removal is achieved while not degrading the assembly materials. In addition, the physical and chemical characteristics of flux residues from lead-free solder pastes may be significantly different than those created during eutectic Sn-Pb soldering. Since it is possible to attach industry-standard (i.e. eutectic Sn-Pb) CSP/BGAs without solder paste on the PCB, the attachment method often includes a flux deposition. Fluxing BGA and CSP components can be achieved by several methods which include: dipping the component into a flux film deposit, dispensing, spraying, and brushing techniques. To minimize the flux
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residue left on PCBs following a reflow, it is preferred to utilize methods that only dispense flux on the areas required. 1. Flux Dipping Flux dipping commonly used to flux component solder balls, is achieved by applying a tacky flux to a rotating drum or disk as illustrated in Figure 34. The flux depth is controlled with the blade height set a predetermined distance above the drum surface. The component is placed into the flux film and the flux adheres to the tips of the solder bumps immersed into the flux. In the dipping method, the device ball planarity must be considered when specifying the dip depth, which must be at least 1 mil (0.0254mm) greater than the ball coplanarity to ensure each bump is adequately fluxed. 2. Fluxless Methods Fluxless methods rely on oxide removal prior to assembly, typically achieved via a plasma cleaning system. In plasma systems, a plasma gas is made to impinge upon the metal pads to be wet by solder. The plasma radicals bond with the oxygen molecules of the pad surface oxides, which removes them and leaves a clean exposed metal surface. 3. Maintaining Component Position During PCB assembly and transportation, forces imposed on a component can cause the device to move from its original position on a PCB. Solder paste and/or flux is used to retain components in place during the assembly and transportation of the PCBs. The tackiness required of a flux or paste depends on the assembly process utilized. In-line automated assembly requires less retention force than manual batch assembly. Additionally, placement equipment utilizing table movement rather than head movement requires much greater retention forces due to high accelerations imposed on the PCBs and components. The retention force can be calculated by simply multiplying the acceleration imposed on a component by its mass. A tack test can be performed on the solder paste or flux as described in section 2.3.5 of this chapter to determine its retention capability. 4. Adequate Flux Volume When a flux-only method is used for CSP assembly or rework operations, it is critical to ensure that both the bump coplanarity and warpage of the assembly at reflow temperature is fully understood. The combination of variations in solder ball volume, and warpage of both the package and substrate may lead to solder joint electrical opens. That is , if a package has an undersized solder ball at a location within the array where the component experiences significant warpage during a reflow operation, there may not be sufficient solder volume to form a proper
FIG. 34 Rotating drum style thin-film flux application system. (a) Schematic illustrating the key features and concept. (b) Photograph of an actual system. (Courtesy of Universal Instruments Corporation).
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solder joint. The addition of solder paste helps minimize the tendency to create electrical opens since the paste helps bridge the gap between low-volume solder balls and the corresponding PCB attachment pads. In addition, a flux-only process can result in a marginal or cold solder joints if the flux volume is not sufficient. For example, in cases where both oversized and undersized balls exist in the same component solder ball array, the applied flux volume is not sufficient to coat the shortest ball tip and the oxides will not be removed from the ball during reflow. If incomplete fluxing occurs, adequate metallurgical bonding and joint formation may not occur.
D.
Placement Considerations
The strategies used to place components on boards can be divided into several categories: in-line, mass, sequential, and simultaneous placement. In very high volume manufacturing, dedicated sequential or mass placement may be performed. In most cases, flexibility is important to accommodate multiple products and components. SMT and area array assembly typically utilize one of two types of sequential component pick and place equipment. The first is an X,Y gantrystyle machine (Figure 35), and the second is a fixed-head, moving-table placement machine (Figure 36). Overhead equipment offers high flexibility, medium placement speed, high accuracy, and minimal accelerations or movement of the PCB. In contrast, table movement machines (usually equipped with rotary turret heads) offer very high placement speeds, medium accuracy, medium flexibility, and impose high accelerations on the PCB. Table 13, contrasts the two placement approaches. The vision system is an important feature of placement equipment given its impact on assembly. The ability to properly image component features, such as leads and solder bumps, is required to accurately place components onto their corresponding PCB locations. The throughput, accuracy, and repeatability obtained from a component placement machine are a function of its design and intended application. The placement machine is usually the most expensive piece of equipment in an assembly line. The cost is proportional to a machine’s features, accuracy, and repeatability. The required production rate, pitch and size of the components to be placed, and packaging format are some of the factors that must be considered in selecting an adequate component placement machine.
FIG. 35 Overhead gantry-style pick and place machine. (a) Overview indicating that placement machines are capable of not only handling various types of components simultaneously, but also a variety of formats that introduce the components to the tool. (b) Close-up photograph of a gantry-style placement head. (Courtesy of Universal Instruments Corporation).
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FIG. 36 Photograph of a fixed head with rotary motion capability and moving table component placement system. (Courtesy of Universal Instruments Corporation).
1. Accuracy and Repeatability The choice of a placement machine largely depends upon the required placement accuracy which is the deviation in distance between the center of a component lead and center of its corresponding circuit pad. Placement machines have a finite resolution capability, so the target viewed by a machine is not often the actual target. Therefore, the machine’s target is the resolution point nearest to the actual target. When the distribution of actual locations is established, the accuracy is defined as the distance from the distribution modal point to the machine target. Repeatability is the distance from the distribution modal point to the point of maximum deviation. Statistically, repeatability can be expressed as one-half the total range of the distribution. The accuracy of a placement machine is the net effect of software algorithm accuracy, component delivery, head positioning accuracy and repeatability, and vision system capabilities [24]. The types of feeders used and size of a component can also influence placement accuracy. Large feeder site tolerances at a component location can result in a deviation between the component center point and the actual pick-up location. The deviation in the theta axis can be exaggerated due to larger component body sizes. As the component body increases, rotational
TABLE 13
Comparison Between Gantry and Moving Table Placement Machines
Feature
Gantry Movement Characteristic
Table Movement Characteristic
Acceleration of PCB
Low-Only during product transfer
Accuracy Flexibility Quantities of Feeders
Medium-High High Low on base machine, expandable with add-on units All-Tape and reel, tray, stick, bulk Feature identification on device Small-Medium (1 to 1.5 meters)
High-during placement, Low-during product transfer Low-Medium Low-Medium High on base machine, expandable with add-on units Tape and reel
Feeder Types Component Vision Machine Size
Package outline Large (3 to 5 meters)
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changes result in much larger (X-Y) planar deviations compared to smaller parts rotated to the same rotational angle (Figure 37). In contrast, a global change in one of the planar directions, (X or Y) results in the same amount of placement error for large or small components. Of course the accuracy of a measurement method plays an important role in the measurement. Ideally, the accuracy of a measurement method should be an order of magnitude better than the accuracy needed for the measurement. Placement machine accuracy and repeatability for X, Y, and theta axes can be measured using the precision glass slugs and precision plate approach if the accuracy of the glass parts meet the 10X requirement for the machine being measured. Ideally, the tool being used for measurement must have an accuracy at least 10 times greater than the feature size being measured. A statistically valid test strategy can be used to verify the machine’s published specifications. 2. Feature Mis-identification A major placement issue is the ability of the equipment to recognize board and component features and accurately place a device by aligning the device leads, termination pads, or bumps to the attachment pads on a PCB. Another important aspect of vision systems relates to the misidentification of device features. Some components have logos, nomenclature or other features on the array side of a device which may be mis-interpreted as a lead or ball location by a standard forward illuminating camera. Standard forward illuminating cameras utilize a light source, typically LED arrays) that projects light directly perpendicular to the surface of interest. The camera receives the light reflected back from the surface. However, illuminating packages from an angle (typically 45 degrees), is sometimes required to prevent erroneous ‘‘ball finds’’ on CSPs with bottom-side, non-ball features. Components with lead-free alloy terminations or solder balls have surface coloration and reflectivity which is different than the same terminations coated with Sn-Pb. Therefore, light levels will need to be increased for components with lead-free solder bumps compared to light levels utilized for eutectic Sn-Pb solder bumps. 3. BGA Component Placement For ball grid array components, a placement machine does not require a comparable level of accuracy in placement compared with fine-pitch SMT devices. This is partly due to the coarser ball pitch and larger feature size of BGA components compared to peripheral-leaded components. BGA packages can be mechanically centered during a placement operation, unlike fine pitch components that require vision assisted centering. However, very large BGAs (greater than 40 mm), require a higher degree of placement accuracy compared to small BGAs since small errors in theta could result in a misplacement. Similar to flip chips, eutectic Sn-Pb BGA packages exhibit significant self-centering capabilities during solder reflow. In fact, it has been observed
FIG. 37 Representation of rotational error (theta) of large BGA components.
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that some BGAs are able to self center up to a 75% off-pad placement [25,26]. This trend has been shown to be true for BGAs bumped with lead-free solder alloys as well as eutectic Sn-Pb solder. 4. Components With Lead-free Solder The placement of lead-free components may require changes in the vision lighting scheme, since lead-free surfaces tend to be dark and dull compared to Sn-Pb solder balls and coated termination pads. In general, the lead-free alloys have a dull surface finish appearance compared to Sn-Pb (Figure 38). The Sn-Pb solders including eutectic Sn-Pb exhibit a shiny, highly reflective surface. In some cases, however, a lower reflectivity has a positive impact on vision-assisted placement since the amount of high-angle light reflected from ball surfaces is significantly reduced.
E.
Reflow Soldering Temperature Profiles
The primary goal of a reflow system is to achieve a uniform temperature across a PCB assembly. For typical SMT components, the leads or terminations are exposed to the furnace ambient temperature conditions, however, the solder balls of area array components are shielded from the atmosphere or infra-red (IR) lamps. A general rule of thumb for BGA and column grid array devices is to maintain a temperature gradient of 10jC or less across the component solder joint array to prevent component warpage and to ensure all joints reflow properly. Small cards populated with small devices, typical of assemblies utilized in hand-held consumer electronics, can be subject to lower temperatures compared to large, heavy, high-density PCBs used in telecommunication and network routing applications. In addition, high-mass components such as large ceramic devices and connectors exhibit much greater temperature gradients compared to small components such as CSPs, thin plastic packages, or passives. Therefore, assemblies containing a mixture of high and low mass components (i.e. telecommunication products) will be more difficult to achieve a uniform temperature gradient across the board when lead-free solders are used, compared to assemblies containing all low mass components (i.e. portable products). In general, the thermal profile created for the reflow furnace contains several distinct regions; namely the initial ramp, a dwell at elevated temperature, a ramp to the maximum temperature, and a cool down region, as illustrated in Figure 39. The critical reflow profile parameters that must be controlled are the peak reflow temperature, oxygen level, dwell time above liquidus, soak time, ramp rate, cooling rate, conveyor speed, and the temperature difference across an assembly (DT). If the ramp rate is too low, the assembly may not attain the required soak temperature soon
FIG. 38
Lead-free solder joint appearance (dull) compared to eutectic Sn-Pb solder (bright , shiny).
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FIG. 39 Generic stages and features of a reflow profile.
enough. On the other hand, if the rate is too high, the thermal shock may cause some components to fail. Proper soak temperatures and times are required to evaporate solvents and to activate the flux in solder pastes. The soak time has a significant influence on the temperature difference among components mounted on a board. The longer the soak time, the more likely that both small and large components will be at or near the same temperature level. 1. Eutectic Sn-Pb In general, the peak reflow temperature is typically 20jC–30jC greater than the melting point for eutectic Sn-Pb solder [27] to accommodate temperature variation across the PCB and component. For Eutectic Sn-Pb (63/37), the peak reflow temperature is typically in the range of 210 to 225jC. The dwell time or period where the temperature is maintained above the melting point is normally between 45 to 75 seconds to ensure that the solder of the coldest joint in an assembly properly forms a good intermetallic bond with the metallized surfaces. However, excessively high reflow temperatures are to be avoided because they promote the growth of thick intermetallic layers that cause solder joints to be brittle [28]. Long dwell times can result in dewetting and reoxidation of solder joints, while short dwell times can cause non-wetting. 2. Lead-free Alloys The peak temperature for lead-free alloys may approach 240 to 260jC depending on the alloy selected. Table 14 lists the melting and solidus points of several lead-free solder alloys. The peak reflow temperature for lead-free soldering depends on several factors including product size, component mix, alloy selected, and material set including the PCB. For non-eutectic solder alloys, the temperature at which an alloy is completely molten (liquidus temperature) and completely solidifies (solidus temperature) are different temperatures. The range of temperatures between the solidus and liquidus temperature is referred to as the pasty range (slush where both liquid and solid exist). When considering the selection of peak reflow temperature for noneutectic solder alloys, the liquidus temperature should be used as the melting temperature rather than the onset of melting (solidus temperature). Some important considerations for lead-free soldering is the length of time an assembly is at elevated temperatures. a. Reflow Time and Temperature. A traditional reflow profile (ramp–soak-peak) may take 6 to 9 minutes to complete as shown in Figure 40. Due to the high soak and peak temperatures associated with a lead-free reflow, the flux may completely evaporate before all the oxides are removed. Efforts to reduce the profile time by utilizing a straight ramp-to-peak profile should be approached cautiously since the temperature gradient across a board dramatically increases without a dwell period to provide thermal equilibration. For the assembly of small
538 TABLE 14
PRIMAVERA Liquidus and Solidus Points of Some Lead-free Solder Alloys
Alloy Sn-Bi Sn-In Sn-In Bi-In Sn-Zn Sn-Bi-Zn Sn-Bi-In Sn-In-Ag Sn-Ag Sn-Ag Sn-Cu Sn-Ag-Bi Sn-Ag-Bi Sn-Ag-Cu Sn-Ag-Cu-Sb
Composition
Solidus (jC)
Sn-58Bi Sn-%2In Sn-50In Bi-33In Sn-9Zn Sn-8Zn-3Bi Sn-20Bi-10In Sn-20In-2.8Ag Sn-3.5Ag Sn-2Ag Sn-0.7Cu Sn-3.5Ag-3Bi Sn-2Ag-7.5Bi Sn-3.8Ag-0.7Cu Sn-2Ag-0.8Cu-0.5Sb
138 (E) 118 (E) 118 109 (E) 198.5 (E) 189 143 175 221 (E) 221 227 (E) 206 207 217 (E) 216
Liquidus (jC)
125
199 193 186 226 213 212 222
E = Eutectic
cards as utilized for hand-held devices, the temperature spread across a board typically will be small (5 to 10jC), however, large panels used for network or switching applications, the temperature spread may exceed 40jC. Some reflow ovens designed for eutectic Sn-Pb based assembly may require modification to allow densely populated boards to uniformly achieve the higher reflow temperatures required in lead-free soldering. b. Other Considerations. An oven must be stable at these elevated temperatures and capable of high through-put. The added thermal mass of support pallets is another consideration when defining a reflow profile. Pallet materials absorb and retain heat which result in slower thermal ramps and longer cooldown periods. For near or off eutectic lead-free alloys solidification is gradual as cooling commences. A long pasty range can result in improperly formed joints as solidification does not take place uniformly, and could result in segregation of the solder phases into colonies or dendrites. In some cases segregation of the phases can result in slip plane, or paths for easy crack propagation [19]. In addition, a long pasty range can result in hot tearing,
FIG. 40 General four-stage thermal profile for a card/board assembly. The stages are: 1) initial ramp, 2) soak, 3) ramp to peak temperature, and 4) cool down.
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or ripping of the alloy during cooldown [29]. For solders that have a paste range or have more than 2 elemental constituents, the cooling rate may change the metallurgical reactions (formation of intermetallic compounds within the solder joint) that occurs prior to solidification. The cooling rate and alloy percentages dictate which elements alloy (i.e. react) together determines the distribution of elements or phases within a solidified solder joint. The more demanding requirements of lead-free alloys prompts the need for reflow ovens capable of a higher degree of control.
VI.
SOLDER REFLOW METHODS AND CONSIDERATIONS
The heat transfer mechanisms utilized for the mass reflow soldering of electronic assemblies include convection, radiation (infrared sources), and condensation (vapor phase). The most popular solder reflow method is based on forced convection.
A.
Infrared Radiation
IR reflow furnace systems utilize a series of lamps that emit radiation (infrared) onto the component and PCB surfaces. The surface exposed to the radiation absorbs a portion of the energy and reflects the remainder away for the surface. Material composition, surface reflectivity, color, mass, and shape affect the amount of absorbed and reflected radiation. For peripheralleaded devices, the lead and solder paste are directly exposed to the IR source since they reside outside the component body. However, for area-array components, the solder paste and solder balls are underneath the component body and are shadowed or hidden from a direct IR source. For small BGA and CSP components (less than 10-mm body size ) it was determined that infrared reflow systems are capable of achieving temperature gradients of 10jC or less. However, IR reflow of BGAs (>10-mm body size) have much larger temperature gradients across a PCB and attached package due to color differences, surface emmisivity of the devices, and shadow effects. So-called cold solder joints can form if the temperature gradient is larger than 20jC [8]. Preferential heating, shadow effects, and highly reflective surfaces can cause package warpage, bridges, and electrical opens to occur in BGAs. IR reflow concerns for lead-free soldering are similar to eutectic Sn-Pb solder.
B.
Forced Convection Heating
By contrast to IR reflow, forced convection reflow provides a substantially lower temperature gradient across a PCB and component solder joints. In lead-free reflow, several specific concerns should be addressed before selecting a reflow oven or furnace. These concerns are generally related to the higher temperatures required to achieve the suitable soak and peak temperatures for lead-free solders. Convection furnaces typically utilize a heated, perforated metal plate that radiates heat to PCB assemblies in addition to a heated air flow. As the assembly passes through the reflow oven, heated gas impinges on the surfaces of the components and PCB. Some energy is absorbed by radiation from the heated plates within the oven. IR lamps may additionally be present in the furnace to provide supplemental heat to the edges of the board. The atmosphere utilized within the reflow oven is typically either open air or a reduced oxygen (inert gas) media. Nitrogen is the most common inerting gas utilized in reflow ovens. Experimentation has shown that a reduced oxygen environment assists in flux cleaning and maintaining oxide-free metal surfaces on component terminations and PCB attachment pads. The need for a reduced oxygen environment is amplified when using a mildly-active or low-activity flux which is common in applications that do not require the removal of flux residues from assembled PCBs. For lead-free soldering, a reduced oxygen atmosphere (less than 75 ppm O2) usually is sufficient to allow proper solder joint formation and wetting of solder to the metallized PCB attachment pads. The lower the oxygen content in the atmosphere, the better the solder wetting characteristics, and the lower the defect rate. However, the increased cost associated with lower oxygen-containing atmospheres must be balanced against yield and reliability requirements.
540 C.
PRIMAVERA Carriers
During the assembly process, boards or chip carriers must be properly supported to ensure flatness. Typically, under-board supports are provided at each work station, but are not always available in conveyor systems. The weight of a board and its components is often sufficient to cause thin or large boards to sag causing components to shift after placement or during reflow. Consequently, this condition increases the potential for solder joint defects, such as bridging and electrical opens. Carriers should be designed to accommodate large and thin boards to ensure adequate board flatness. The elevated reflow temperatures characteristic of lead-free soldering tends to exaggerate board sagging and warpage so the use of pallets to provide support for PCBs becomes even more important.
D.
Double Side Assembly Issues
When boards are populated with BGA and CSP components utilizing mixed technology, special process concerns arise. High-I/O, area array components correspondingly require an increased number of PCB vias. Since vias have the local affect of removing heat and wicking solder, special precautions must be taken when subjecting a PCB populated with BGAs to a back-side solder wave operation as shown in Figure 41. The wave temperature must be carefully controlled to prevent top-side solder joints from becoming molten (undergoing secondary reflow). Secondary reflow of area array devices can lead to electrical opens if the BGA component warps out of plane placing the solder joints in tension, while, the solder at the PCB pad surface is liquid (Figure 42). This situation is aggravated in the case of lead-free soldering since the solder wave temperature may exceed 260jC. The greater the via count and density, the more heat transfer occurs, increasing the difficulty of maintaining a uniform temperature of a board and its attachments. Taping the bottom side via area with a polyimide film or utilizing a peelable temporary mask minimizes top-side reflow and solder wicking into the vias. Additionally, the top-side via pad ideally should be covered with a solder mask to prevent wicking of solder into the via as illustrated in Figure 17. During exposure to a solder wave, solder can wick under the solder mask into the via due to a large thermal gradient from the via to the attachment pad.
FIG. 41 Typical PCB solder wave machine. (Courtesy of Vitronics-Soltec).
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FIG. 42 Excessive warpage of a BGA component. (Courtesy of Universal Instruments Corporation).
E.
Metallurgical Reactions During Reflow Soldering
Intermetallic compound formation usually accompanies solder reflow operations during the assembly of PCBs. The base metal and materials utilized to enhance solderability dictate the intermetallic compound species that form. The most common PCB pad finishes are listed in Table 6. In Cu-based metal systems, Sn reacts with Cu and the formation of Cu-Sn intermetallics takes place. If the solder contains silver, additional intermetallic formations between the Sn and Ag occur. When soldering to a Ni/Au plated pad, Sn from the bulk solder reacts with Ni to form a Ni-Sn intermetallic compound. The gold on top rapidly dissolves into the solder where it forms AuSn4 which is dispersed throughout the bulk joint upon solidification [18]. Some trace amounts of Au remains dissolved into the solder and dispersed as a Au solute (pure gold). It is important to realize that Au is applied to the Ni layer to retain its solderability since Ni oxidizes rapidly. Gold has several key attributes necessary for this application: it does not oxidize in the ambient, and rapidly dissolves in the molten solder exposing the underlying unoxidized nickel layer for reaction with the solder.
F.
Solder Joint Structure and Morphology
In most solder joints, solder grains will contain Sn and additional phases. Colonies, which appear as dark or light regions on an optical micrograph, are not individual grains, but merely slight orientation variations of the same phase within a larger grain. Grain structure observation requires advanced techniques in sample preparation to delineate these differences [30]. Cooling rate has a dramatic effect on microstructure of solder joints. Rapid cooling provides small equiaxed grains with a uniform dispersion of phases, if several exist. Whereas, dendrite colonies are more prevalent in slowly cooled solder joints. Excessive dendrite growth, or dendrite alignment can allow for rapid crack propagation due to the alignment of soft materials [31]. An alloy consists of a combination of two or more elements with a dominant or base material being a metal and the addition of minor materials which usually is also a metal, but not always. In order to form a good metallurgical interconnection, the solder material must alloy (i.e. chemically bond) with pads or features it contacts by forming an intermetallic compound [32]. The attachment or interconnection of components onto organic PCBs must take place at a temperature that does not destroy boards or components. Therefore, a solder material should have a processing (melting) temperature well below the temperature which can cause a components or PCB to be degraded. However, the melting temperature must be sufficient to accommodate the intended application or specific conditions. 1. Intragranular versus Intergranular Failure Bulk solder fatigue failure takes place due to incremental crack growth during each successive thermal strain cycle. Failure can occur along microstructural grain boundaries (intergranular), or through the grains themselves (transgranular or intragranular). In polycrystalline metals, the fracture path most commonly occurs as a transcrystalline or intragranular failure [19]. Intergranular failure is generally observed when grain boundaries are very soft compared to the
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bulk phase, contain a brittle phase material, or has been weakened by liquid or solid metal embrittlement. Failure along grain boundaries has been observed in various solder alloys including Sn-Pb-Bi [19,30]. Additional problems such as partial melting, interdiffusion, and embrittlement can arise in ternary and higher order alloys. The microstructure of solder is affected by many factors that change the grain size, concentration of Sn and other elements in each grain, as well as intermetallic compound formation due to the solder reactions with metal features it contacts.
VII.
WAVE SOLDERING CONSIDERATIONS
In addition to mass reflow soldering, PCBs are often subjected to a wave soldering operation, in which the entire board surface (one side) is exposed to a molten bath of solder. In through-hole solder applications, PCBs are passed over a molten wave of solder exposing the bottom side of the PCBs which may contain discrete components and through-hole leads to the solder bath. As the boards pass over the wave, solder is attracted to all wettable surfaces including attachment pads, component leads, and vias. Since there is currently no drop-in, lead-free solution for eutectic SnPb, the implementation of a new alloy will affect the wave soldering process. The alloy selection will require compatible process materials including fluxes, board finishes, components, as well equipment. The melting point of most lead-free alloys requires higher process temperatures in order to achieve the same solder joint quality as with eutectic Sn-Pb soldering. While there are many lead-free alloys available, the alloys of interest for wave soldering applications are limited. The most common lead-free alloys being introduced into wave applications are variations of the Sn-Ag-Cu alloy system. For less complex assemblies, board that do not contain through vias, as utilized for single-sided applications, utilize Sn-Cu as a lower cost alternative to Sn-Ag-Cu alloys.
A.
Wave Flux
For adequate soldering to occur, it is required that the metal surfaces to be joined are free from dirt, oxides, and other contaminates. Intermetallic compounds can only form if the molten solder is able to alloy or react with the exposed metal pad and lead surfaces. To remove metal oxides present on PCB pads, component terminations, and solder balls, requires exposure through the action of a fluxing agent. Wave fluxes are required to perform the same function as fluxes used in surface mount applications with the exception of component retention. In wave applications, SMT components are held onto the PCB by mechanical means, or by the use of an adhesive. Therefore, a lower viscosity, less tacky flux can be used in wave applications compared to surface mount applications. The flux activator which is responsible for removing oxides during a soldering operation is embodied in a carrier suspension to retain the activator on a board when contacting the molten solder. In order to prevent solder wave defects, such as solder bridges or icicles caused by oxides, the activator (typically a synthetic resin) enables the flux to remain on the board during exposure to the molten solder. The solvent used in a flux must be capable of dissolving all the activators added to a carrier. The solvent also enhances flux wetting when it is applied to a board. To achieve proper soldering, all the solvent in the flux must be evaporated before the board enters the solder wave to prevent solder spattering. The higher process temperatures associated with lead-free soldering affect the selection of a solder wave flux. Preferred fluxes utilize a reduced volatile organic content (VOC) solvent such as a water based solvent. The water based fluxes are considered environmental friendly, since they do not volatilize as readily as alcohol solvents. In addition, the water based fluxes have a better compatibility with the higher wave temperatures associated with lead-free solders since they do not boil off as quickly as alcohol based fluxes. 1. Flux Application In solder wave applications, there are several ways to apply a flux to a PCB, the method selected depends on the flux system utilized. A foam fluxer (Figure 43) can be used for rosin-based or ‘‘noclean’’ alcohol fluxes that meet the lead-free process temperature requirements. A foam fluxer is
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FIG. 43 Soltec).
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Wave-solder foam fluxer: (a) controller, (b) fluxer, and (c) pump assembly. (Courtesy of
not recommended for VOC-free, water-based fluxes, since the amount of flux applied with this type of applicator can be excessive and difficult to control. One important aspect of flux application is having a stable foam height, which is a function of the porosity of the foam stone (porous block used to control flux bubbling) and the application air pressure. For most solder wave flux applications an atomizing spray nozzle (Figure 44) is preferred since the amount of flux applied to a board can be precisely controlled. In order to achieve satisfactory interaction between the flux and the PCB surface, it is recommended that the droplet size of VOC-free, water-based fluxes be very small. Small droplet size is achieved by increasing the atomization air volume within the nozzle tip. Since the capillarity of water is not as high as alcohol solvents, water-based fluxes must be forced into PCB through-holes by increasing the nozzle pressure. A low spray pressure results in incomplete through-hole penetration and poor soldering. In order achieve adequate solder fillets in through-hole assemblies, the flux must wet and fill the entire PTH barrel.
FIG. 44 Wave-solder atomize flux nozzle (Courtesy of Soltec).
544 B.
PRIMAVERA Preheating
When utilizing lead-free solder alloys in wave solder applications, the preheat system must deliver significantly more thermal energy to a PCB compared to a eutectic Sn-Pb wave. The function of the preheater is to evaporate the solvents in a flux, and help achieve a uniform temperature across a board. In addition, a preheat reduces the thermal shock components experience on a board, due to the rapid rise in temperature when liquid solder contacts the components and board surface. To ensure adequate solvent evaporation, the topside board temperature should reach 110 to 130 jC for water-based solvents and 90 to 110jC for alcohol-based solvents. A board must reach a sufficient preheat temperature in order for lead-free solders to adequately penetrate into PTHs. The higher temperatures associated with lead-free wave solder temperatures increase the temperature gradient imposed on PCB assemblies during a solder reflow operation. However to prevent delamination or cracking of thermally sensitive devices during wave, the maximum temperature gradient should be limited to 2jC/second. Reducing the conveyor speed or increasing the preheating time may be necessary to prevent the creation of temperature gradients in excess of 2jC/second. 1. Preheat Units Wave solder machines can be fitted with a variety of preheat units including calrod elements, IR lamps, and forced convection heaters (Figure 45). Each preheat type has specific characteristics, used for certain applications. When utilizing a VOC-free, water-based flux, the temperature of the assembly should be increased rapidly. A calrod preheating element provides the highest heating rate among preheat systems, thus resulting in a rapid temperature increase in the first preheat region (zone). When utilizing a calrod element, the board temperature can reach 80 to 100jC at the end of the first zone. With the addition of a forced convection unit in the second and third zones, excess water can be sufficiently removed from the board. Convective preheating has the ability of removing solvents trapped beneath components by directing the heated air at a low angle on a PCB. For water-based fluxes, the board temperature must reach least 110jC to promote evaporation of all the solvent. For alcohol-based wave flux, the temperature can be reduced compared to water-based solvents since alcohol evaporates at 80jC (Table 15). Excessive flux removal has been observed when utilizing forced convection units in the first zone of a preheater. Excessive flux removal before the activation temperature is reached may result in insufficient oxide removal. In contrast
FIG. 45 Wave-solder preheater. (Courtesy of Soltec).
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Physical Characteristics of Water and Several Alcohols
Material Water Methanol Ethanol Isopropanol Butyl Alcohol
Boiling Point (jC)
Freezing Point (jC)
Surface Tension at 25jC (dynes/cm)
Vapor Pressure at 20jC (mm Hg)
Specific Heat (cal/gramjC)
100 64.5 78.3 82.3 117.7
0 97.7 114.1 87.8 89
73 22.5 22.1 20.8 24.6
29.2 92 44 33 4.39
1 0.60 0.62 0.65 0.56
to convection or calrods, IR lamps have the advantage of providing a rapid response to changes in temperature settings. IR preheaters are ideally used in wave applications consisting of mixed production requirements and multiple product change over. For a lead-free wave soldering process, a three zone (length about 1800 mm) preheat region is sufficient to heat the boards and remove flux solvents. A typical wave solder preheat configuration for lead-free solders would consist of calrods for the first zone, followed by forced convection in zones two and three.
C.
Lead-free Solder Temperature
In a typical eutectic Sn-Pb wave solder process molten solder temperatures reach 250jC which is 67jC higher than the melting point eutectic Sn-Pb solder. With many lead-free solders the wave solder temperature would approach 300jC if the same 67jC temperature rise was utilized. It is not feasible to process lead-free solders at temperatures that approach 300jC because both PCBs and components are severely damaged at these temperatures in most cases. For example, when utilizing eutectic Sn-Cu (melting point is 227jC), would require a 294jC wave temperature. It has been determined that a 67jC temperature increase above the melting point of lead-free solders is not necessary to achieve adequate soldering during wave applications. The operation temperatures are kept between 260jC (Sn-Ag-Cu) and 265jC (Sn-Cu) which provides functionally acceptable solder joints while minimizing PCB and component damage. Another reason for minimizing the wave temperature is to prevent re-oxidation of the metallized surfaces. Oxide thickness growth rates increase as the temperature increases. A reduced oxygen atmosphere can be used to minimize the re-oxidation of metallized pads. The wetting and hole-fill penetration during wave soldering improves for lead-free solder alloys in a reduced oxygen atmospheres. However, sufficient through-hole penetration is highly dependant on the flux chemistry, application method, and volume. Longer wave contact times may be required to assure through-holes are properly filled. However, an increased thermal exposure may result in damage to the components or boards.
D.
Solder Wave Configuration
1. Wave Former Several types of wave formers (Figure 46) are used in solder wave machines, each having their own specific characteristics. In general, the behavior of lead-free solder alloys to the various wave formers is similar to eutectic Sn-Pb solder. The purpose of a wave former is to produce a solder flow shape that results in both good solder fillets and adequately filled through-hole joints. 2. Double Wave Systems Double-wave systems are designed to solder mixed technology (SMD and through-hole components), consisting of a primary and so-called chip wave. The nozzle of the first wave is directed in the transport direction and produces a turbulent flow front across the board surface.
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PRIMAVERA
FIG. 46 Wave-solder wave former: a) photograph, and b) diagrammatic sketch. (Courtesy of Soltec).
The turbulent flow creates more uniform solder wetting to the surface mount pads. The second wave is a double-sided wave, allowing the molten solder to flow back into the solder bath along both sides of the nozzle. The double-sided wave results in good penetration of the solder into PTHs and results in uniform surface mount fillets for discrete components. Achieving properly formed fillet joints requires sufficient wave contact time (dwell-time), which is defined as the time component terminations and boards are in contact with the molten solder. This time is influenced by the conveyor speed, the distance of the wave to the conveyor chain (immersion depth of the board), the shape of the wave, and the conveyor angle. Compared to eutectic Sn-Pb wave soldering processes, slightly longer contact times are required for lead-free alloys due to reduced wetting compared to eutectic Sn-Pb solder. Although an increased solder temperature improves wetting, a solder temperature tradeoff is required due to material damage which increasingly occurs as the solder temperature increases. Addditionally, as the solder temperature increases, there is an increase in board warpage and dross formation.
VIII. A.
LEAD-FREE WAVE SOLDERING Double-Wave Soldering
In double-wave systems utilizing a lead-free solder, the separation distance between the first and second wave must be minimal to prevent the board temperature from dropping below the solder melting point when passing between the waves. While this phenomena occurs with eutectic Sn-Pb wave soldering, the wetting characteristics are sufficient to result in good through-hole penetration in the second wave. In addition, the temperature of the wave solder is 67jC greater than the melting point of the eutectic Sn-Pb solder, thus reducing the chance of the temperature dropping below the melting point. However, in lead-free solder wave applications, the wave solder temperature is less than 40jC greater than the melting point of the solder. If the board temperature falls below the lead-free solder melting point, through-holes do not fill properly. Making the second wave turbulent (Smart or Wo¨rthmann wave) increases the vertical forces of the solder flow, resulting in an improved through-hole penetration. One limitation of bottom-side
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SMD-component, lead-free wave soldering is that components experience a solder immersion temperature that exceeds 250jC which may result in component damage.
B.
Use of Inert Atmosphere
Utilizing an inerted (nitrogen) atmosphere lowers the surface tension (Table 16) of eutectic Sn-Pb and lead-free solder alloys thus improving the wetting, and reduces oxide and dross formation. Tests have demonstrated [33] that an inert blanket applied in the region of a solder wave improves solderability (Figure 47). A significant advantage of a reduced-oxygen wave utilizing a nitrogen inerting gas is the reduction of dross. In general, lead-free alloys are more expensive than eutectic Sn-Pb solder which increases the interest of using nitrogen in solder waves. However, the decision to utilize nitrogen is based on a variety of factors including nitrogen cost, installation issues, production requirements, recycling costs associated with dross (oxide-rich scrap solder), yield, reliability, and other issues. Experimentation on dross formation in lead-free solder waves shows that nitrogen usage can reduce dross formation significantly. Testing indicates that dross produced by eutectic Sn-Pb solder at 250jC is equivalent in weight to dross produced by a SnCu wave at 270jC, however, the Sn-Cu dross has a lower density, and therefore a slightly higher volume than dross produced by a eutectic Sn-Pb solder wave. Utilization of a small blanket of nitrogen (50 cubic-liters/minute flow rate) reduced the dross formation weight by a factor of 5 for Sn-Cu at 270jC. Sn-Ag-Cu showed a reduction factor of 2 for nitrogen inerting when the wave temperature was 260jC. The tests were conducted using a continuously flowing solder wave [33].
C.
Copper Dissolution
Similar to traditional Sn-Pb wave soldering, metals dissolve relatively quickly during lead-free wave soldering operations. The rate of alloy or metal dissolution of exposed pads on PCBs or component leads depends upon their composition, solder composition, bath temperature, and the flow velocity of the wave solder. The rate of dissolution of a specific metal is lower if this metal is already present in the lead-free solder bath. Of particular concern is the dissolution of copper from circuit boards when exposed to lead-free solder waves. 1. Effect of Cu Concentration in Solder Boards subjected to a Sn-Ag solder wave pass exhibited a significantly higher copper consumption rate than eutectic Sn-Pb solder. It was demonstrated that no copper remained after 6 passes of a PCB laminate coated with 1-ounce copper through a Sn-Ag wave. Figure 48 shows the consumption rate of copper by Sn-Ag-Cu was significantly lower compared to Sn-Ag. Sn-Cu solder yielded the lowest copper dissolution rate of the lead-free alloys tested.
TABLE 16
Surface Tension of Eutectic Sn-Pb versus Several Lead-free Solders
Alloy Sn (Pure) Sn-37Pb Sn-3.5Ag Sn-4Cu-0.5Ag Sn-0.7Cu Sn-58Bi Sn-9Sn
Solidus Temperature, Tsol, (jC) 232 183 221 216 227 138 199
Liquidus Temperature, Tliq, (jC)
Surface Tension (Liquidus Temp + 50(jC) -(mN/mm)Air
Nitrogen
417 431
464 493
491 319 518
461 349 487
222
Intermetallic Phases
Ag3Sn Ag3Sn, Cu6Sn5 Cu6Sn5
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PRIMAVERA
FIG. 47 Illustration of a wave-inert atmosphere blanket.
2. Reactions With Tin Dissolution rates for copper from PCB surfaces into the wave are influenced by several factors including wave temperature, the percentage of Sn in the solder alloy, and the amount of copper already in solution. The copper primarily bonds with Sn to form Cu3Sn or Cu6Sn5 intermetallic compounds. High-Sn alloys dissolve copper more rapidly than low-Sn alloys. 3. Acceptable Copper Concentration The acceptable level of copper allowed in a wave solder is therefore a key parameter. In general, for a eutectic Sn-Pb wave process, a content greater than 0.2% Cu results in increased bridging. Accordingly, the maximum permissible copper contamination in eutectic Sn-Pb wave applications is typically specified as 0.3%. The 0.3% Cu limit is also considered the maximum concentration for Sn-Ag alloys. The high tin content (96.5 %) in Sn-Ag results in a rapid increase in the copper level during production, particularly with boards that have a large quantity of copper pads. 4. Copper Removal Some commercial wave processes utilizing Sn-Ag solder attain the 0.3% copper level after approximately 4 months of production compared to 1–2 years for eutectic Sn-Pb waves. In eutectic Sn-Pb wave soldering, a separation procedure is routinely practiced commercially to remove copper from Sn-Pb solder pots. However, in lead-free soldering, techniques for removing
FIG. 48 Copper dissolution into two lead-free solders compared to eutectic Sn-Pb at 260jC.
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copper from a solder pot on line do not exist, thus requiring that the entire volume of solder in a pot be replaced. For Sn-Ag-Cu, the alloy contains copper which as noted earlier reduces the copper dissolution rate. Results from wave experiments have shown that Sn-Ag-Cu alloys that contain 1% or more copper have reached saturation in the bath so they do not scavenge copper. The copper level has been determined to stabilize at 1% Cu.
D.
Effects of Lead (Pb) and Bismuth (Bi) Contamination
As lead-free solders are transitioned into PCB assembly processes, there will be a period of time wherein components and/or boards with lead-bearing finishes will be mixed with those bearing lead-free solders. Concern arises when lead is introduced into the metallurgical system containing lead-free solder. For example, bismuth-bearing, lead-free alloys exhibit a low-melting ternary eutectic phase of Sn-Bi-Pb (melting point 96jC), the composition of which is 15.5Sn-51.5Bi-33Pb. In addition, lead-free solders contaminated with as small as 0.5% Pb lead will exhibit a 183jC melting point corresponding to eutectic Sn-Pb, as shown in a differential scanning calorimetry (heat of reaction) plot of Figure 49 . Reliability degradation of a multi-phase system (containing liquid and solid regions simultaneously) may manifest as hot tearing of the alloy, impurity transport within the solder joint to the phase boundaries, and creation of slip planes. For example, bismuth congregates at Sn-Pb phase boundaries, rendering them weak areas to initiate and propagate cracks. Lead contaminated Sn-Bi BGA devices demonstrated a reduction in solder fatigue life in accelerated thermal cycle (ATC) testing at –40 to 125jC from over 2000 cycles for eutectic Sn-Pb solder to only 200 for Sn-Bi-Pb. 1. Sources of Pb Contamination Lead (Pb) contamination can be traced to several sources including; paste and sphere manufacturing (lead residue on tooling surfaces), alloy smelting and refining operations (impurities),
FIG. 49 Differential scanning calorimeter plot of a solder containing Pb and Bi. This indicates the presence of a low melting (96jC) ternary eutectic phase (Sn-Bi-Pb). The second peak corresponds to a Sn-Bi phase with a large pasty range (solidus is approximately 128jC and the liquidus is approximately 137jC).
550
PRIMAVERA
and mixing of surface finished and solder materials (i.e. Sn-Pb HASL PCB finish). ‘‘Lead-free’’ alloys typically are not 100 percent lead-free due to imperfections in the refining process. It is not unusual for as much as 0.1% Pb to be present in commercially available lead-free alloys. Lead (Pb) can be accidentally introduced into an assembly process by operator error. For example it is important to maintain strict control on the solder bars which are frequently added during a wave soldering operation to maintain the solder volume. Accidentally adding a 5-Kg SnPb bar into a SnAg3.8Cu0.7 solder wave system with a 760-Kg solderpot capacity resulted in an increased Pb content from 0.1 to 0.3%. Lead is also added into wave solder pots by dissolution from component leads and PCB pad finishes. Many leadframe and passive devices utilize a Sn-Pb (85/15) solder plating as a lead finish. The finish melts when passed through a lead-free solder wave then becomes disperses into the pot. Some impurities are skimmed from the wave during dross removal so it is difficult to assess the concentration of lead or other impurities in a wave pot unless a chemical analysis is conducted.
E.
Iron Contamination
For eutectic Sn-Pb wave applications, the rate of dissolution of iron is very low, which ensures good wear and corrosion resistance of parts within a wave machine. However, with lead-free alloys, the Fe contamination was measured to be as much as 10 times greater than for a eutectic Sn-Pb wave [33]. If however, the wave solder machine is modified with proper wear coatings, the contamination of a solder bath of Sn-Bi-Ag-Sb, utilized in production of electrical light ballast was 0.002% Fe after one year of operation [33].
F.
Solder Defects
1. Fillet Lifting Fillet lifting is a separation of the solder fillet from the copper pad around a PTH during the cooldown stage of soldering as illustrated in Figure 50. The primary reasons for fillet lifting have been determined to be due to the coefficient of thermal expansion mismatch of the alloy composition, copper pad, and board material. Fillet lifting is most prevalent with bismuth-bearing alloys due to a large pasty range. The defect rate increases dramatically a lead-free alloys is contaminated with lead (Pb) to create Sn-Pb-Bi ternary alloy. Fillet lifting has additionally been observed in Sn-Cu, and Sn-Ag wave and pin-in-paste applications. Although fillet lifting is expected to reduced the reliability of PIH solder joints, this is not necessarily the case. In several studies [34] solder joints
FIG. 50 Fillet lifting of Sn-Cu wave solder at the solder/pad interface of a through-hole fillet.
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with lifted fillets did not show a dramatic reduction in fatigue resistance during accelerated thermal cycle testing. Mechanical pull testing of lead-free solder joints showed that fillet lifted joints do not show a dramatic reduction in pull strength. In fact, there is not an apparent reduction in PTH lead pull strength of lead-free solder joints until there is less than 50% of the PTH filled with solder. Due to a lack of standards for electronic assembly utilizing lead-free solders, fillet lifting is accepted for some products and applications. However, long-term effects of fillet lifting on solder joint reliability is unknown, so caution is suggested when implementing lead-free soldering quality standards. 2. Solder Balls In eutectic Sn-Pb wave soldering, formation of solderballs on the surface of a PCB is a lowoccurrence defect. For lead-free wave soldering, however, the number of solderball defects is substantially higher than with eutectic Sn-Pb. The higher operating temperatures required in lead-free soldering softens the solder resist on boards which makes solderballs more prone to stick to the board surface. In addition, the reduced wettability and increased oxide formation found with many lead-free solders increases the chance of solderball formation. 3. Excessive Solder Lead-free solder joints have a surface coloration and texture different from joints formed with SnPb solder. The solder joints of SMD components sometimes exhibit an excess of solder due primarily to a reduced wettability of the solder on component terminations. Physical joint shape may pass solder joint specifications solder excess and irregular joint surfaces should be avoided for cosmetic and quality reasons. In through-hole joints excessive on the top or bottom side is often caused by voids in the solder. These voids form by several means; outgassing of volatiles in the PCB through pin holes in PTHs, poor solder wetting to PTHs or component pins, or from flux or moisture trapped in PTHs. Lead-free soldering shows a higher occurrence of PTH voiding than a eutectic Sn-Pb wave since the process temperatures are higher.
G.
Wave Machine Material Compatibility
When utilizing a lead-free solder in a wave process, the machine and process must be modified to ensure the alloy selected is compatible with the internal parts of a wave machine. Lead-free solders are not ‘‘drop in replacements’’, for eutectic Sn-Pb solder. Issues such as lead contamination, flux chemistry compatibility, dross removal equipment, and dissolution of coatings on the surfaces of a wave machines internal parts into the solder alloy must be considered. 1. Solder Change Over Procedure When Pb residues reach 0.2% in a bath, the solder pot must be removed, cleaned and replenished with new solder. The solder change-out procedure must be followed rigorously to prevent damage or contamination of the solder system. Changing wave machine solder pots is often quite difficult and labor intensive. Draining the solder from a pot may itself be difficult since many solderpots are designed with special chambers to help maintain a stable solder wave. Once empty the solderpot, including the interior parts and surfaces, must be rinsed with tin before it can be refilled with pure tin. The wave machine is operated to flush the system and then redrained to remove traces of impurities. All wear surfaces are inspected for corrosion before the lead-free alloy is added to the pot. An adjustment to the system’s control software is required to prevent damage to the impellers (increase the temperatures at which impellers operate to prevent operation when the solder is not fully melted). Danger to operators cleaning the wave is increased with lead-free solders due to equipment containing solder at significantly higher temperatures. An alternative to wave cleaning is to replace the solderpot with a new pot suitable for lead-free processing. In addition to the solder pot, it is recommended that all bolts and screws used in the solder pot area are replaced with titanium fittings. Titanium has a lower density then the lead-free alloys so fittings will not sink into the solder if they become dislodged during operation, preventing damage to the impellers.
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PRIMAVERA
2. Wear Coatings Due to the high tin content of lead-free alloys, materials such as grade 304 stainless steel (AISI), often used for solderpot parts, can not be used due to iron dissolution causing corrosion damage after several few months in production. The dissolution rate of iron in the lead-free alloy is dependent upon several factors including the pot materials, the lead-free alloy selected, the temperature of the solder wave, and the flow rate of the solder. Wear coatings due to corrosion are therefore applied to stainless steel grade 316 base materials to reduce iron dissolution. Many of the wear coatings are proprietary, consisting of ceramic or high temperature anti-corrosive polymers or metals. Ceramic coatings can be damaged by maintenance operations since the material is typically brittle. Alternatively, replacement of the steel parts with titanium fittings would eliminate the need for a wear coating. For the solderpot itself, steel is preferred, due to steel’s superior thermal conductivity and lower cost compared to titanium, however a heatresistant wear coating is required. Typically, a heat resistant paint or coating is applied to the solder pot to prevent Fe corrosion of the pot.
H.
Rework
As lead-free solders enter main-stream surface mount manufacturing, the assemblies must be reworkable utilizing existing methods and equipment. While many components are reworkable using standard SMT rework equipment, underfilled packages have the same rework limitations as flip-chip dice. The decision to discard or re-use components must be made on a case-by-case basis. The process steps typically consist of component removal, site redressing, addition of solder paste or flux, and component replacement. The rework process must be both repeatable and provide assemblies whose reliability is equivalent to new-build product. The need for solder paste deposition prior to component replacement depends on the package construction (for example, leads or solder balls), composition of the solder balls, and physical dimensions of the component terminations and PCB pads. The thermal profile used for component replacement should be similar the new-build product assembly profile. Both global heating methods used for new-build or localized heating techniques can be utilized for rework. The rework tool nozzle design is another important factor in achieving a uniform heat distribution. Other rework issues that must be considered are; under board heating, excessive heating of adjacent components, and
FIG. 51 Solder mask and pad damage due to degradation during a rework site-dressing operation. Damage is highlighted in white circle areas.
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board warpage. As in other situations associated with lead-free solders the higher temperature is cause for additional concern, especially as it relates to maintaining component and board integrity. An increased occurrence of board solder mask damage and pad peeling has been observed at PCB sites whose pads had been solder dressed at lead-free reflow temperatures (Figure 51).
I.
Underfill
Typically, the assembly of flip chip dice to a chip carrier requires the use of an underfill process to compensate for thermally induced strains caused by the coefficient of thermal expansion mismatch between a die and its chip carrier. The underfill process involves dispensing a highly filled (silica) epoxy resin along the edge of an assembled die, and capillary forces which cause the liquid to flow and fill the gap between the die and chip carrier. The resin adheres to the die, solder joints, and chip carrier when cured. In addition to greatly reducing the stress level on the solder joints, the underfill also provides mechanical protection to a die. Underfilling dice requires an additional step which increases the product fabrication time, and ultimately the cost. For underfilled components or die that are subjected to an additional reflow at lead-free solder temperatures, an increase in underfill delamination form the chip or PCB surface will occur. The elevated temperatures associated with lead-free soldering will degrade the adhesion of underfill epoxies faster than temperatures utilized in processing eutectic Sn-Pb solder. 1. Surface Mount Components Standard surface mount components do not require an underfill, however when assembling some CSPs onto organic PCBs, underfill may be required to increase the thermal and mechanical reliability of the interconnections. Some types of CSPs have a compliant elastomeric layer that decouples the chip-to-carrier body thermal expansion mismatch induced strains. That is the stresses exerted on the solder connections are dissipated by an elastomer that mechanically isolates the silicon die from its flexible polyimide film interposer. Those component designs which do not provide sufficient decoupling between die and carrier require an underfill to satisfy the reliability requirements for some applications. In addition, the components in hand-held consumer products are often underfilled to improve the mechanical robustness of an assemblies ability to withstand drop and shock resistance. Shock and impact requirements for CSPs in portable products may exceed 2,000 G accelerations. 2. Potential Lead-free Solder Impacts In assemblies utilizing lead-free solder, work must be performed to ensure that the flux, underfill, component, and PCB system is compatible. For an underfill to be effective, the underfill must bond to the die and chip carrier surfaces. Current underfill systems are designed to be compatible with flux systems for Sn-Pb solder, which may not be the case with a lead-free solder. An additional concern for underfilled systems is exposure to reflow temperatures. For example, flipchip BGA components may experience several reflow cycles after the underfill step. The higher processing temperatures experienced during lead-free soldering can have detrimental effects such as delamination of the underfill material from the chip carrier or die surface.
J.
Energy Consumption
1. Water versus Alcohol Based Flux Energy consumption and hence cost of operation for lead-free wave soldering is higher than using eutectic Sn-Pb due to higher temperatures required for preheat and the solderpot. Energy usage in preheating depends on the flux utilized. Alcohol-based fluxes evaporate at lower temperatures than water-based fluxes, so the energy consumption VOC-free, water-based fluxes is 20% greater for compared to alcohol-based chemistries. Approximately 40 percent more heat is required to evaporate water-based, VOC-free fluxes compared to alcohol-based fluxes. However, the actual energy consumption is lower than 40 percent since the volume of VOC-free, water-based flux required for lead-free soldering is significantly lower than for alcohol-based soldering.
554
PRIMAVERA
2. Machine Startup During machine startup (warm-up time) more energy is consumed per hour than during wave operation. Typical heat-up time for eutectic tin-lead solder (250jC) is 31⁄2 consuming approximately 34 kWh for a standard commercial unit. In contrast, the maximum wave temperature required for Sn-Cu solder is much higher, approximately 280jC. The heat-up time for Sn-Cu solder is about 51⁄2 hours with an energy consumption of 36 kWh. The power consumption required to maintain the solderpot at temperature was determined to be similar for both alloys despite the temperature difference.
IX.
QUALITY PROCESSING
The importance of human factors is often overlooked, which includes adequate training to avoid costly mistakes. Input from operators has a very significant affect on product quality, yields and reliability. Among the factors with the greatest impact are handling, training, education, setup, and quality control. Specific aspects of joint quality and solder fillet formation that should be considered when implementing a lead-free solder system are the solder color, texture, and wetting angle which are different for lead-free solders compared with eutectic Sn-Pb solder alloys. Assembly utilizing lead-free solders may require changing the solder-joint quality standards since the appearance of lead-free solder joints is different in compared to eutectic Sn-Pb solder joints. Operators not aware of the differences in their appearance would likely reject lead-free solder joints that are functionally acceptable. In general, the lead-free alloys are dark in color with a dull luster compared to eutectic Sn-Pb solder joints which are smooth, bright, and shiny.
A.
Training and Inspection
Operators training, while having a focus on particular equipment should also provide a familiarity with the overall process. This helps instill a sense of ownership and allows them to understand how their actions affect operations farther down the line. Mistakes due to improper training can have serious consequences on product yields or field reliability. Human error can be minimized by a combination of training, proper equipment and tools, and attitude. Often operators assume the end product can be reworked if not assembled properly. Even if true, rework is a costly solution to errors, especially if they were avoidable. 1. Solder Joint Appearance Several aspects of operator training relating to lead-free assembly include the solder joint appearance; sufficiency of wetting; and fillet shape, especially in through-hole joints. Most lead-free solder candidates form solder joints that are dull in appearance and exhibit an irregular surface finish compared with eutectic Sn-Pb solder. The lack of solder-joint luster may cause operators or inspection personnel to mis-identify lead-free solder joints as being of poor quality. A dull appearing lead-free solder joint may well be one capable of providing adequate reliability. Joint shininess or luster is used as a quality criteria during the visual inspection of solder joints. While highly reflective surfaces characteristic of Pb-Sn solder joints, are readily identifiable features for visual inspection, a dull or matte finish typical of lead-free solders provide a much more robust image with automated vision inspection equipment. Highly reflective surfaces are difficult to image with automated inspection equipment, and often require special filters and lighting to achieve a proper feature definition. 2. Fillet Shape and Wetting Angle Another aspect of lead-free soldering related to operator training is in redefining acceptable solder joint fillet shapes and wetting angles. As discussed in section 3.4.5 of this chapter, lead-free solder alloys exhibit a lower degree of wetting to pad finishes used in microelectronic assembly compared to eutectic Sn-Pb solder. The reduced wetting often results in solder fillets with more solder coalesced at the central portion of a joint, and less solder spread on a pad, and lead surfaces.
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Handling
Improper handling, manual or automated, can have a detrimental effect on the integrity of components during assembly. This issue becomes even more important if automatic assembly transportation systems (conveyors) are not implemented. Improper manual handling, especially after component placement, may result in component misalignment causing defects such as opens or bridges during reflow soldering operations. 1. Package Moisture Sensitivity When handling moisture sensitive packages, adequate handling strategies must be implemented to prevent devices from excessive moisture absorption. A condition referred to a popcorning is associated with the rapid expansion of entrapped moisture during exposure to high temperatures. Ideally, components should be capable of surviving several reflow cycles after exposure to the ambient on the factory floor occurs in production during normal scheduled assembly. Diffusion of moisture into overmolded and plastic chip carriers (i.e. PBGAs) typically follows Ficks Law. However, solving a multilayer diffusion problem (diffusion through more than 1 surface layer), as well as the exposed ends of a substrate, requires all the material properties to be known. Prior to assembly, it is usually necessary to know the moisture sensitivity of each package type that will comprise an assembly. Manufacturers provide a JEDEC-based moisture sensitivity level rating for the components they supply. Moisture sensitive components may require a pre-assembly bake out if exposure to moisture exceeds the time recommended by the manufacturer prior to reflow. In general, CSPs almost completely desorb their moisture following a 4-hour bake out at 125jC. However, larger devices and moisture-sensitive plastic molded devices and some BGAs must be baked out at 125jC for 24 hours. During component qualification procedures, components are typically classified by the IPC or JEDEC moisture sensitivity test procedures as found in J-STD020-A, for non-hermetically sealed SMCs. However, the current standards are performed at temperatures far below the peak reflow temperatures for lead-free solders, which would require devices to be re-qualified at 240–260jC temperatures. The JEDEC moisture sensitivity categories and required bake out conditions are illustrated in Table 17.
C.
Setup Checks and Quality Control Monitors
Correct equipment setup is very important to ensure high throughput and yield because it impacts the consistency and accuracy of the results. The setup used at every stage of a PCB assembly process must be performed by certified personnel and validated to be in accordance with the
TABLE 17 20-A
Parameters Associated with IPC/JEDEC Moisture Sensitivity Level Standard J-STDSoak Requirements Floor Life
Level 1 2 2a 3 4 5 5a 6
Standard
Time
Condition
Time (hr)
Condition
Unlimited 1 year 4 weeks 168 hours 72 hours 48 hours 24 hours (TOL)
#30jC/85%RH #30jC/60%RH #30jC/60%RH #30jC/60%RH #30jC/60%RH #30jC/60%RH #30jC/60%RH #30jC/60%RH
168 168 696 192 96 72 48 TOL
85jC/85%RH 85jC/60%RH 30jC/60%RH 30jC/60%RH 30jC/60%RH 30jC/60%RH 30jC/60%RH 30jC/60%RH
TOL = Time on label.
Accelerated Equivalent Time (hr)
Condition
120 40 20 15 10
60jC/60%RH 60jC/60%RH 60jC/60%RH 60jC/60%RH 60jC/60%RH
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PRIMAVERA
engineering specifications. Gage studies should be performed to maintain consistency from lineto-line and operator-to-operator. Simple procedures can be implemented to evaluate the performance of equipment and operators. Stencil printing onto a bare laminate before each shift, placing test components onto double-sided taped boards, and using a data logger with a thermocoupled board (i.e. monitor) to profile reflow ovens on a regular basis are examples of such precautionary measures. More advanced methods could include; assembly of standardized test boards; measurement and analysis of statistical process variables and defect analysis; and characterization of the placement machine utilizing precision chrome/glass components and boards. Mapping the placement machine accuracy versus x-y positional location can be accomplished by utilizing ‘golden standard’ precision components and boards. A calibration component consists of chrome features created by photolithography on a glass or quartz substrate. The components are placed onto glass substrates with similar chrome features created in a regular pattern. The components are placed on the substrate and a measurement is made between the theoretical centroid of a part, and the actual part location as placed on the glass board. The placement machine software can be modified to mathematically correct for placement deviations.
X.
SUMMARY
Lead-free soldering can be achieved with current state-of-the-art assembly equipment, with minor changes to the assembly process. However, use of materials designed for temperatures associated with the reflow of eutectic Sn-Pb, may cause assembly defects. Modifications to the board material, component construction, and flux systems are required in order to withstand the increased process temperatures typical of lead-free solder alloys. Degraded wetting on common board finishes by lead-free alloys in comparison to eutectic Sn-Pb is a characteristic difference. The lack of solder wetting to terminal pads may require modifications to flux systems and pad geometry to avoid exposed pad surfaces and incomplete fillet formation. In addition to material modifications, inspection criteria for solder joint quality must be modified to address the comparatively dull and rough surface of lead-free solder finishes. Joint luster and shine typically used to assess eutectic Sn-Pb solder joints are not sufficient characteristics to determine joint quality for lead-free alloys.
APPENDIX A. PRINTED CIRCUIT BOARDS UTILIZING BUILD-UP TECHNOLOGY Emerging board technologies could have a significant impact on and impacted by the lead-free solder assembly parameters. This appendix discusses the various process associated with PCB build-up technology and discusses the influence and impact lead-free soldering has on this board technology. Build-up circuit boards are fundamentally different from standard PCBs in that interconnection between individual circuit layers is accomplished without the use of a throughhole, but rather relies on an individual layer-to-layer via, as illustrated in Figure 1A.
A.
Overview
In standard PCB fabrication, metallized drilled holes provide an electrical connection between any two layers. However, through vias utilize board real estate on all layers whether an interconnection is required on a particular layer or not. The number of layers not connected by through vias can be significantly reduced through the use of controlled-depth drilled vias and the sequential lamination of pre-drilled core layers (blind internal layer vias). While the use of blind vias (vias that connect individual circuit layers) increases board utilization it may significantly add cost. Additive board layer processes and micro-via formation methods provide alternative solutions to mechanically-drilled holes. Figure 2A, shows an example of inner-layer (buried vias) and outer-layer (blind vias).
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FIG. 1A Cross sectional view indicating blind and buried via structures created by build-up technology on top of a standard ground-rule card/board that serves as the core. Build-up technology can be made to be very dense, thus allows the escape of high I/O-count components (ie. area array), which is not possible with standard ground rules.
Surface Laminar Circuitry (SLC)k developed by IBM is one of the earliest board build-up fabrication methods. This technology provided a solution to the high occurrence of broken drill bits and mis-drilled cores commonly encountered with drilled vias with fine dimensions by using blind and buried via structures. Neither construction method requires through holes, but only vias between layers that require interconnection. There are several categories of via structures being used in the printed circuit board industry which are discussed in the following sections.
B.
Miniaturization Issues
Routing of signal traces becomes much more complex with an increase in I/O count, and reduced lead or bump pitch. With standard circuit board technology, a majority of the signal trace routing is transferred to the other layers by through holes to provide signal escapes. Additionally, increasing lead count adds complexity for existing low cost boards that allow only one or two traces between board features. Packages with higher I/O complexity may require routing schemes resulting in line widths and spaces as small as 2/2 mil. While fine-line technology is possible, the extreme demands placed on the board fabrication process results in lower board yield and thus
FIG. 2A
Various blind and buried via structures.
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PRIMAVERA
FIG. 3A
Examples of dense personalization: (a) 1.5 mil lines and spaces, (b) 2.5 mil lines and spaces.
higher cost. An example of 2-mil lines and spaces are shown in Figure 3A, for the routing of a flip chip device with 4-mil bump pitch. In addition to board fabrication problems, the board assembler may experience reduced yields caused by tighter process windows and smaller tolerances. Subjecting fine-line circuits to lead-free process reflow temperatures may increase the chance of delamination or separation of the copper features (i.e. trace and pads) from the dielectric layer on PCBs. Copper adhesion depends upon the copper plating method, copper thickness, trace width, dielectric type, and temperature. It has been shown [11], that copper adhesion is higher for reinforced epoxy laminates compared to un-reinforced dielectric laminates.
C.
Photolithographically Defined Vias
Photolithography via-formation structures use specially formulated dielectrics that are capable of being photo imaged and developed to create via openings. A photoimageable wet or dry film and electroless copper is used to form the outer blind via structure. They are sequentially built up one or two layers at a time. An additive plating process creates the electrical connections to the attachment pads and into the vias. The sequential build up process begins with a double-sided, copper-clad FR4 laminate. Copper features are created on each side of the laminate by the following steps. First, the laminate is coated with a photoresist, which is then covered with a patterned film, and exposed to ultra-violet light. The regions that are not exposed remain soft and removed by a chemical etchant, exposing the copper areas to be subsequently removed. The exposed copper is then etched, and the remaining solder resist is removed. Once circuitized, a photo-senistive dielectric is applied to the copper circuitry layers/FR4 core. The resist is dried, exposed to UV light through an artwork film and subjected to a chemical developer. The vias are created chemically in the dielectric layer as holes to the underlying copper pads. The dielectric layer is then chemically prepared to accept copper plating. A thin ‘‘seed’’ layer is created utilizing an electroless bath followed by an electrolytic process to deposit copper in the vias and the top surface of the dielectric layer. The circuitry is formed on the top and bottom layers following the same steps used on the copper-clad FR4 layer. The dielectric layer steps are repeated as required to achieve the board routing. A solder mask dielectric layer is typically coated on both sides of the board to protect the outermost circuitry layers [35]. Build-up technology, such as SLCk, has achieved up to three board build up layers per side of laminate core as shown in Figure 4A. One method, the interpenetrating polymer network build-up structure system (or IBSS) technology, developed by Ibiden Corporation, achieves fine lines (2-mil lines and spaces) and photo via holes with 4-mil diameters. One of the important aspects of micro-via formation is the ability to register the via fully within the capture pad. The process tolerances of each formation method requires the via pad to be larger than the via by
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FIG. 4A
559
Example of a photolithographically-formed via structure.
several mils. In general, the photolithographic process produces the smallest via to pad ratio. Vias not fully registered within the top capture pad, and innerlayer stop pad as illustrated in Figure 5A, have shown a reduced reliability in thermal cycle testing. Lead-free soldering could negatively influence PCBs created by photolithographic sequential dielectric materials due to a higher reflow temperatures (delamination of the layers) compared to soldering with eutectic Sn-Pb. In addition, the copper adhesion strength of SLCk-type structures is lower compared to FR4-reinforced dielectrics.
D.
Mass Generation Processes
Mass-generation processes such as chemical etching use wet chemistry and photo resist or plasma etching of copper pre-coated dielectrics. In the chemical etching process, photo mask films are used to etch holes or feature shapes through the copper foil. This defines each feature location on the base structure. Typically, the layers consist of 1-2 mil thick, non-reinforced polyimide film. The circuit layers are processed and via holes are plated. If required, additional dielectric and circuit layers are added to the laminate to provide multilayer, high-density circuit routing. Conductor pattern build-up on the polyimide base laminate structure and the electrical interconnection of vias are formed by additive copper plating techniques. Copper-clad, glass reinforced material or copper clad pre-peg resin is used to laminate the outer circuit layers to the pre-processed core structure. Through holes, if required, are mechanically drilled and plated to form electrical connections to the inner circuit layers. Plasma-etched microvias are formed by printing and etching an image of the vias in the outer layer copper foil, exposing the dielectric between the outer copper foil layer of the board and capture pad on the adjacent inner layer. The boards are then placed in a plasma chamber and processed in a plasma field consisting of an oxidizer and fluorine gas. The plasma chemically decomposes the exposed dielectric layer into volatile species (CO2, H2O), and HF) which are vented from the chamber. Since copper foil acts as a mask for the plasma etching, the underlying pad is the stop point for the chemical reaction.
FIG. 5A
Two examples of misregistration of a via to its stop pad.
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PRIMAVERA
Because of the isotropic nature of the etch reaction, the dielectric layer has an undercut and the formed hole is larger in diameter at the top or center, than at the bottom. This is due to the plasma reactive gas attacking the base polyimide layer in both a vertical and horizontal etching pattern.
E.
Mechanically Drilled Microvias
Mechanical micro-drilling methods of via formation typically use resin-coated copper circuit pairs as a base material. The addition of reinforcing fibers in the laminate causes higher drill breakage compared to non-reinforced materials. Fine mechanically-drilled vias are typically drilled one-up rather than stack drilled to prevent the drill from wandering or breaking. In mechanical drilling, the drill speed required for fine vias (smaller than 0.005’’) is in excess of 100,000 RPM, with 200,000 RPM machines in use today. Mechanical drilling machines typically utilize tooling pins and a registration hole created in the laminate stack. The combined registration tolerances of the pins, drill head, drill size, and drill wandering must be considered when designing the pad location for a given nominal drilled hole diameter. Typically, the pad diameter must be 0.006’’ larger than the drill size to accommodate the combined positional and size tolerances.
F.
Solid Post Construction
In solid post construction, two copper layers are used to laminate an inner layer dielectric with preformed vias. These copper layers can be prefabricated circuits or bare copper sheets on which conductor patterns are formed subsequently by imaging and etching. The advantage of this method of construction is that vias can be stacked on top of each other, further minimizing the area blocked for signal routing. Alternatively, conductive adhesives and highly filled conductive epoxies can be used to create layer-to-layer electrical connections. Vias can be drilled or formed and subsequently filled with a conductive material by screening, stencil printing or other techniques.
G.
Laser Processes
1. Laser Ablation Laser ablation techniques can create both a through (buried) via and blind via geometry. In through-via technology, the laser ablates a thin core material which is then plated and subsequently laminated to outer layers. In blind-via construction, the via is formed from one side of a copper coated laminate, but does not penetrate the bottom or second side copper surface. The via is subsequently plated to connect layer n with layer n-1. In addition, multilayer blind vias can be formed with this technique to connect layer n with layer(s) n-2, or n-3. a. Methods. Two basic approaches to laser drilling have been developed, one utilizes an Ultra Violet Neodymium-Yttrium Aluminum and Garnet (UV Nd: YAG) laser source and the other uses CO2 (carbon dioxide) laser. YAG lasers operate at a wavelength that can cut Cu, epoxy, and electrical and structural glass; while a CO2 laser beam typically is reflected from Cu. In YAG laser cutting, the Cu layer and underlying dielectric and reinforcing layers can be processed simultaneously. However, typically many laser pulses are required to create a single aperture. With CO2 lasers, an aperture is etched or created into the Cu layer and the remaining epoxy and glass are removed by the laser beam pulse. In this operation, the Cu limits the removal of material and the beam diameter is typically larger than the via which allows via formation in a single step rather than multiple steps required in YAG cutting. Utilizing a combination of techniques allows for fast process times. In a combined approach, the YAG laser cuts the Cu layer and CO2 cuts the core material. The choice of dielectric material will depends on the via drilling approach. FR-4 and RCC dielectrics are the most attractive choice for top layer materials when utilizing laser ablation since the resin chemistry is similar to the laminate core. In addition, both materials are Underwriters Laboratories (UL) recognized with well known material properties.
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b. Lead-free Assembly. In lead-free assembly, the top-layer dielectric choice will in part be determined by the alloy selection (melting point). Higher Tg materials can withstand the leadfree reflow temperatures better than the lower Tg materials such as mono-functional or difunctional epoxies and phenolic resins. c. Laser Via Formation Techniques. Through vias are formed by either punching or trepanning. Blind vias are more complicated since the material inside the via must be removed without damage to inner layer copper features. Punching can be used for non-reinforced dielectrics. Laser spiraling is often used for blind vias in FR-4 (reinforced material). Typically a combination of spiraling and trepanning is used to form blind vias in FR-4. d. Laser Punching. In laser punching, the beam is held stationary while a laser punches through the material using multiple pulses at a high repetition rate. The via size depends on the size of the focused laser beam. The process does not mechanically stress the material, so holes can be formed on very fine pitches. Typically, small through-hole vias, less than 2-mils (50-A) in diameter are formed by laser punching. Punching can be used to drill blind vias in non-reinforced dielectrics by adjusting the laser power to a level that ablates the epoxy, but does not damage the underlying copper feature. In general, laser punching is performed on thin (2 to 3-mils) dielectric cores (layer processed with a finished to and bottom side) utilizing a through via as illustrated in Figure 6A. During subsequent lamination of the core to the remaining PCB layers, epoxy resin from the B-stage laminate sheet flows into and fills the punched via. This is fundamentally different from blind vias which are formed after the layer is applied or laminated to the remaining core layers. e. Trepanning. Laser trepanning is cutting in a circular pattern with a small diameter beam (typically less than 0.1-mil). The laser beam requires a high-speed beam positioning system to form an identical circular cut path. The required via dimension is therefore created by placing multiple laser drilled apertures next to each other in an overlapping circular path as illustrated in Figure 7A. The via size and shape affect the trepanning path and cut rate. Vias on a very small pitch and very high aspect ratio often require this technique. Trepanning is often used for small blind vias (2 to 4-mils diameter). f. Laser Spiraling. During spiral cutting, the laser is moved in a circular path of increasing diameter as illustrated in Figure 8A. The path of the spiral is set to remove all material in the via down to the same depth. A UV laser with a high peak power and low average power cuts cleanly through the dielectric material without damaging the inner layer pad. A combination of spiraling and trepanning is used for bigger vias (5 to 8-mil in diameter).
FIG. 6A Lasers are typically used to create holes less than 150 micron (6 mils) in diameter. Lasers can be used to create both (a) blind via structures, and (b) through hole structures.
562
PRIMAVERA
FIG. 7A Computer menu of parameters that control a UV laser with a very small diameter beam (about 0.1 mil). A via is created by overlapping successive laser-drilled apertures to create a circular pattern with the desired diameter.
FIG. 8A Computer menu of the parameters that control a UV laser that is moved in a spiral path of increasing diameter.
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2. Post-laser Processing Issues After laser processing, some issues with downstream processes occur. De-smearing may be required. Sometimes laser drilling leaves resin residue in the cavity which must be removed prior to plating. Some high cross-linked dielectrics are difficult to remove and may pose some additional problems for drilling and de-smear. Process variations may be required to attain acceptable weight loss plating. Conventional electroless techniques are often inadequate to sufficiently plate small hole geometry. The electroless plating solution can not sufficiently deposit material in a blind via due to poor solution flow. Plating solution penetration into blind vias is reduced as the via aspect ratio (diameter to depth) is decreased. Direct metallization technique such as the colloidal graphite technique may be required to effectively plate the blind via structures. Electroplating issues may prevent uniform coverage, due to the evolution of gases, flow/agitation problems, or due to the geometry of the vias. The via shape effects the plating rate and effectiveness. An open via or positive wall angle (larger at the top compared to the bottom) plates more uniformly than a via with straight wall or vias with a negative angle, as illustrated in Figure 9A. 3. Micro Vias Issues The quality and reliability of plated micro-via structures are influenced by many factors, as outlined in Table 1A. In general, via pad size is a more critical parameter than via diameter. Early failures occur if the via is not formed completely within the capture pad, as shown in Figure 10A. A minimal difference in reliability is found when changing the via diameter from 3 to 8 mils as shown in Figure 11A, which compares via diameter with lifetime in an accelerated liquid-to-liquid shock test. The liquid-to-liquid shock test is performed at –55 to 125oC for a duration of 10 minutes at each temperature [36]. While UV-YAG laser processing produces systematically smaller vias than other types, it requires a via pad approximately 5 to 6 mils larger than the via size to compensate for via-to-pad misregistration to ensure the via is formed within the top capture pad and the underlying stop pad. Possible solutions that allow registration of the top layer laser drilled vias to the underlying capture pads are being developed. One method is to align the laser vision system to the underlying layer by a cut-out slot or hole in the top layer. This allows the bottom layer features to be visualized by a camera when viewed from the top, down into the next layer through the clearance hole. Unfortunately, drilled through-holes typically are misregistered by a larger amount since the alignment is based on standard routed slots and tooling pins. This means that the drilled hole
FIG. 9A Via wall angle configurations possible with microvia structures: (a) excessive-positive, (b) positive, (c) straight-wall, and (d) slightly negative.
564 TABLE 1A
PRIMAVERA Recommendations to Enhance Microvia Quality and Reliability
Feature Wall Angle Via Wall Thickness Via Capture Pad Via Capture Pad Via Stop Pad Registration Via Separation Via Diameter Fiber Removal
Recommendation
Application
Positive Taper 0.5 mil Minimum 6 mils Larger than Via Diameter 4 mils Larger than Via Diameter Same Size as Capture Pad Register Within Capture Pad High Strength Dielectric 4 to 6 mils Removal Without Glass Debonding
Laser Drilled All vias Laser Drilled Photodefined All Vias All vias Reinforced Laminate All Methods YAG laser
pattern is registered to a different reference point than micro vias which require larger capture pads for the PTH. An alternative construction consists of eliminating through-hole vias by routing all signals with microvias from the top layer to inner layer buried through-vias. The operating power of a laser effects the quality of the via in several ways, including, the amount of epoxy or glass removed per laser pulse and the damage caused to the dielectric layers due to dissipation of the laser energy. Typical power outputs from CO2 lasers are approximately 1000 watts, compared to 10 watts for a YAG laser. The laser energy transferred to the dielectric layers causes the epoxy and or glass to be vaporized. However, excess energy is absorbed by the dielectric layer and surrounding copper. High power (CO2 laser) ablated vias can fracture and debond the glass from the epoxy matrix in reinforced dielectric layers due to excess heat (laser energy) in the vicinity of a via. During the plating operation, Cu can plate along the de-bonded fiber bundles as shown in Figure 12A. Dendrite growth along the fibers to an adjacent pad, PTH
FIG. 10A Via location in a capture pad. (a) Vias are properly located within their respective capture pads. (b) Via is partially located outside the via pad. (c) Vias are tangent to the edge of their respective capture pads. (d) Via does not touch via pad.
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FIG. 11A Cummulative failures of photodefined microvias ranging in diameter from 3 to 8 mils, under thermal cycle conditions of –55 to 125jC.
or via structure, can cause an electrical short. The dendrite growth is increased by the application of a bias voltage and humid conditions. Microvias have been shown to last approximately 1000–2000 (N50) cycles in –55 to +125C liquid shock. For properly plated vias, first failures occur near 1500 cycles, while in improperly plated vias, first failures have been observed as early as 100 cycles. Via fractures are generally found at the via-to-pad interface, in areas of thin plating, or in fiber-intruded bundles (glass fiber not fully removed ). Positively tapered vias (top larger than bottom) have shown consistently
FIG. 12A Post CO2 laser processed via formation, copper can plate along the remaining glass bundles.
566
PRIMAVERA
FIG. 13A Series of cross sections of increasing magnification depicting the separation of a via from its stop pad due to component warpage following the first-pass reflow assembly.
FIG. 14A Separation of via-stop pad from the laminate due to component warpage and poor adhesion between the copper feature and the dielectric material. (a) No separation between the top pad and the component carrier dielectric material. (b) Separation between the top pad and the component dielectric material. (c) Enlarged view of the separation of the via-stop pad and the dielectric material.
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more uniform plating thickness compared to vias with negatively tapered vias. Separation of the via from the stop pad as shown in Figure 13A, is due to a high out-of-plane ‘‘warpage’’ stress and a weak Cu via/pad interface. Separation of a stop pad from the laminate, as shown in Figure 14A, is due to a high out-of-plane ‘‘warpage’’ stress and a low Cu adhesion strength to the dielectric.
ACKNOWLEDGMENTS The author would like to give special recognition to several groups that assisted in the preparation of this chapter. Universal Instruments has generously funded research in the area of process development for lead-free soldering, which formed the fundamental basis for the work presented in this chapter. The research team at Dover-Soltec is acknowledged for their contributions in the area of lead-free wave soldering. Individual contributions were made by many of the researchers from the Department of Industrial Engineering at Binghamton University. Special thanks are given to Mohammed Yunus at Texas Instruments for his assistance in wetting and solderability experiments for lead-free solder alloys. Additionally, Jaydutt Joshi and Suresh Jayaraman of Conexant Systems, and Ursula Marquez are recognized for their contributions in micro-via technology.
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Lau, J.; Pao, Y. Solder joint reliability of BGA, CSP, flip chip and fine pitch SMT assemblies; McGrawHill: New York, 1997; 47–90. Prasad, R. Surface Mount Technology Principles and Practice; Van Nostrand Reinhold: New York, 1989. Primavera, A.; Huang, Y.; Srihari, K. Some factors that could impact the BGA assembly process. Proceedings - IPC/SMTA BGA National Symposium; 67–76. Lau, J. Ball Grid Array Technology; McGraw-Hill: New York, 1996. Mawer, A.; Cho, D. ‘‘Industry trends in ball grid array development’’, IPC SMTA BGA Symposium Proceedings, 1997. Primavera, A. Influence of PCB parameters on chip scale package assembly and reliability part I, Proceedings SMTA International Sept 12th; San Jose, CA, 1999. Hwang, J. Solder Paste in Electronics Packaging; Van Nostrand Reinhold: New York, 1989. Huang, Y. Yield Estimate For Surface Mount Area Array Devices, Doctoral Dissertation; State University of New York at Binghamton: Binghamton N.Y., 1996. Anderson, L.; Primavera, A. Plastic Ball Grid Array Attachment: Assembly and Reliability Performance, International Journal of Microelectronics May 1997; Number 43, 11–15. Primavera, A.; Sturm, R.; Prasad, S.; Srihari, K. Factors that influence void formation in BGA assemblies. Journal of Surface Mount Technology January 1999, 12 (Issue 1). Primavera, A. Reliability Improvement of Area Array Solder Joints: Changing the Attachment Pad Geometry, Doctoral Dissertation; State University of New York at Binghamton: Binghamton N.Y., 2001. Schake, J. Investigation of Bump Distributions From the Stencil Printing Wafer Bumping Process, Masters Thesis; State University of New York at Binghamton: Binghamton N.Y., 1998. Rajagopalan, S. Solder Paste Testing and Evaluation for the BGA Assembly Process, Masters Thesis Binghamton University; Binghamton, New York, 1996. Cullen, D. Circuit Board Pad Finishes, MacDermaid Corporation, IPC Printed Circuit Exposition; San Jose, California, 1997. Erich, R.; Coyle, R.; Wenger, G.; Primavera, A. Shear testing and failure mode analysis for evaluation of BGA ball attachment. Proceedings of the IEMT, 1999. Ohriner, E. Intermetallic formation in soldered copper-based alloys at 150jC to 250jC. Welding Research Supplement, Supplement to the Welding Journal; 191s–202s. Bradley, E.; Banerji, K. Effect of PCB finish on the reliability and wettability of ball grid array packages. IEEE Transactions CPMT Part B; 1995; 320–330. Bradley, E.; Lall, P.; Banerji, K. Effect of thermal aging on the microstructure and reliability of ball grid array (BGA) solder joints. SMI Proceedings 1996, 1, 95–106. Kalpakjian, S. Manufacturing Process for Engineering Materials; Addison-Wesley Publishing: Massachusetts, 1985; 97–176. Zumdahl, S. Chemistry; Heath and Company: Massachusetts, D.C, 1986. Wild, R. Private Communication Au Embrittlement, 1994.
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PRIMAVERA Riedel, W. Electroless nickel plating. ASM International; Finishing Publications Ltd: 1991. Manko, H. Solders and Soldering; McGraw-Hill: New York, 1992. Glaeser, C. Accuracy Evaluation Methodology For Fine Pitch Surface Mount Placement Equipment. Master Thesis; State University of New York at Binghamton: Binghamton, New York, 1994. Houghten, J. New package takes on QFPs. Advanced Packaging; Winter: 1993; 38–39. Yunus, M. Lead-free Solder Evaluation. Masters Thesis; State University of New York at Binghamton: Binghamton N.Y., 2000. Wu, C. A Knowledge Based Approach To Profile Identification In Surface Mount Infrared Reflow Soldering. Masters Thesis; State University Of New York at Binghamton: Binghamton, New York, 1992. Hill, G. The analysis of manufacturing processes for plastic ball grid arrays (PBGA). Proceedings NEPCON West, 2; Anaheim, California; 1996; 38–39. Callister, W. Materials Science and Engineering; John Wiley and Sons: New York, 1985. Wild, R. An updated approach to the analysis of solder and soldering, Presentation and Proceedings; R. Wild Associates: Vestal, N.Y, 1992. Courtney, T. Mechanical Behavior of Materials; McGraw-Hill: New York, 1990. Klein Wassink, R. Soldering in Electronics, 2nd Ed.; Electrochemical Publications Limited: Ayr, Scotland, 1989. Barbini D. – Dover Soltec. Dusek, M.; Nottay, J.; Hunt, C. Compatibility of lead-free alloys with current PCB materials. Proceedings, International Confeerence on Advanced Packaging Systems, Reno, NV, 2002; 110–115. Coombs, C. Printed Circuits Handbook, 4th Ed., McGraw-Hill: New York, 1995. Joshi, J.; Primavera, A.; Marquez, U.; Srihari, K. Reliability evaluation of high density microvia structures. Proceedings, International Conference on Advanced Packaging Systems, Reno, NV, March 2002; 249–254.
15 Use of Inert Atmospheres in Lead-Free Soldering Martin Theriault Air Liquide Corporation, Houston, Texas, U.S.A.
Jason Uner Air Liquide Corporation, Charlottesville, Illinois, U.S.A.
Armin Rahn Rahn-tec Inc., Sainte He´lene-de-Chester, Quebec, Canada
I. A.
INTRODUCTION Soldering Electronics
As early as a few thousand years ago, metals were joined together by utilizing low-melting alloys. Beginning with the ‘‘electronic age,’’ solder joints served two functions: to conduct electricity, and to create a joint with sufficient mechanical integrity. With the continuous reduction in solder joint dimensions required in microelectronics, the ability to adequately wet the solder surfaces has become increasingly important. Therefore, there is an increased reliance on inerting to assure functionality and sound solder joints.
B.
Oil: The Initial Inerting Method
The addition of oil was the first approach taken to prevent the oxidation of liquid metals in wave soldering systems. Oil also helps to reduce the surface tension of molten solder on printed circuit boards (PCBs) as they exit the wave, which in turn reduces the tendency of adjacent solder joints to bridge. However, using oil is not a clean process and it polymerizes when heated. Oil does meet two key requirements of an effective inerting method: to significantly reduce defects, and to reduce dross formation. However, in the end, the negative aspects of using oil clearly outweigh the benefits, so it has been abandoned.
C.
Inerting Emerges from No-Clean
In the late 1970s and early 1980s, parallel research was carried out in North America and Europe involving the use of a nitrogen atmosphere when soldering. The Montreal Protocol focused world attention on the so-called ‘‘greenhouse effect’’ and on the chemicals that cause global warming. Among them were organic materials routinely used by the electronics industry to remove flux residues. The threat of eliminating the most effective cleaning agents for surface-mount (SM) assemblies caused many companies to search for alternatives.
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Low-solids fluxes (LSFs) and low-residue fluxes (LRFs) were introduced to allow the viability of no-clean processes. In Germany, Hartmann [1] added adipic and formic acids into a nitrogen gas stream with the intent of eliminating the use of liquid flux altogether. Each acid performs a specific function. Adipic acid [HOOC–(CH2)4–COOH, mp=153jC] removes oxides on the base metal. The powder is dissolved with a 1–2% solution in isopropanol alcohol. Formic acid (HCOOH) is introduced over the wave to remove any remaining tin oxide. At temperatures above 150jC, formic acid reacts with oxides as follows: SnO þ 2HCOOH ! ðHCOOÞ2 Sn þ H2 O where (HCOO)2Sn is the appropriate metal formate formed. Above 200jC, the metal formate breaks down: ðHCOOÞ2 Sn ! Sn þ 2CO2 þ H2 A commercial tool that utilized the concept of introducing flux components (i.e., organic acids) together with nitrogen inerting was made available. The concept consisted of passing a nitrogen gas stream through dissolved formic acid. Formic acid was picked up and directed into the nitrogen tunnel. This approach only proved workable whenever all metallic surfaces [including plated through-holes (PTHs)] exhibited excellent solderability and residual oxygen level (ROL) was kept very low. The acid did not reach all the intended surfaces (e.g., inside the holes), but instead attacked parts of the wave soldering machine. Worst of all, the acid reacted with other chemicals to form unwelcome compounds. The system ended up being too problematical and was generally abandoned in favor of using nitrogen in combination with a low-solids flux.
D.
Inerted Reflow Soldering
The idea of inerting was found to be applicable to reflow soldering as well. Within a year of being introduced in commercial wave equipment, inerting was made available in reflow equipment. Infrared (IR)-heated ovens, popular at the time, were used with nitrogen. However, with the advent of forced convection reflow systems, using nitrogen became more of a problem as the consumption number climbed to the 50 N m3/hr and greater range. Higher operational costs associated with running a forced convection inert process became a critical issue for end users. Although assemblers recognize the benefits of inerting during reflow, most assemblers opted to operate under ambient conditions. Many more systems were sold with nitrogen capability than were actually used with nitrogen. Although it was recognized that certain problems were best dealt with by using inerted atmospheres, most were processed using air to prevent the additional cost for nitrogen. As time passed, oven manufacturers redesigned their equipment to reduce nitrogen consumption rates to a range of 20–30 N m3/hr (even lower in Europe) compared to prior convection reflow systems that required 40–60 N m3/hr.
E.
Tinning Components
Wetting the metal finish on components or a lead frame plays an important role during solder joint formation. A method of protecting the base metal (e.g., copper, Alloy 42, Kovar, etc.) from oxidation while also aiding the wetting process is to coat the surface with the proper alloy (i.e., one that melts during solder reflow). One of the oldest coating techniques consists of immersing either the entire component or just its leads into molten solder. This is referred to as ‘‘hot solder dipping.’’ Typically, the areas to be solder-coated have a plated nickel barrier and an underlayer of a leachable species such as silver or palladium–silver. During the ‘‘hot solder dip’’ operation, the component metallization and leads are subjected to conditions similar to a standard wave soldering process: fluxing, perhaps preheating, and then exposure to liquid solder at temperatures
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around 250jC (for eutectic Sn–Pb). An intermetallic compound layer provides the bond between the base metal and the solder coating as is normally the case with most soldering operations. Systems developed for ‘‘tin’’ component lead finishes exhibit some problems. Flagging and icicles (excess solder condition) at the end of leads are particularly difficult to control and very troublesome for automatic and even hand insertion. The use of flux sprayed into the exit of the wave alleviates the problem, but also causes major contamination and maintenance problems. However, the use of nitrogen, instead of flux, results in a more uniform solder coating as icicles draw up on leads under inerted conditions. A number of these tinning systems are commercially available.
II.
WAVE SOLDER DROSS FORMATION
A.
Metal Oxidation
The most obvious advantage of nitrogen inerting is that it prevents contact with reactive species, namely oxygen. Oxygen reacts with metals to form oxides, whose kinetics of formation is dependent upon temperature. Soldering takes place at temperatures above the melting point of the solder and typically above the solder flow point (i.e., the temperature at which a solder easily flows on a heated metal surface). However, oxidation becomes most observable when the liquid solder is pumped and agitated during a reflow soldering operation. Removing oxygen removes the potential for oxidation. All base metals (except some of the noble ones such as gold) are subject to tarnish and oxidation if unprotected through the solder reflow process.
B.
Dross
Tin, which oxidizes more easily than lead, is responsible for creating the larger amount of oxides during soldering operations. Lead oxides are rarely found in these slushy mixtures that cover the surface of the molten solder. Lead does not normally oxidize at temperatures below 600–800jC, but can be made to do so under special conditions. For example, during unprotected solder pumping activity, the shaft of the pump causes friction as it enters the molten solder bath, creating small particles of solder dust. The large surface area of solder dust particles acts as a catalyst, causing even the lead to oxidize. Lead oxide appears as a black powder substance. 1. Toxicity Although most industrial soldering operations are regarded as safe, there are potential concerns. Lead, particularly lead oxides, can cause serious health problems. Because inhaling lead dust is worse than ingesting it, it is prudent to take steps that avoid the creation of lead oxides, and prevent them from entering the breathing space of workers. Accordingly, the use of nitrogen aids in both areas. It is a common practice to use nitrogen inerting in areas where high friction or high turbulence would normally cause the creation of lead oxides if oxygen is not excluded. Covering a bath and inerting the area around the pump and the area where the flow reenters the bath are minimum requirements. Prior to using a nitrogen atmosphere for this purpose, oils and waxes were used, which caused maintenance problems. Oil and waxes needed to be changed frequently, whereas fumes that they generated clogged the exhaust system.
C.
Parameters Affecting Dross Formation
There are several important parameters that affect dross formation during wave soldering operations. 1. Wave Height Increasing the wave height requires an increased flow, rate resulting in an increased surface area exposed for chemical reaction. As a rule-of-thumb, doubling the wave height produces roughly four times as much dross.
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2. Turbulence The surface area of a smooth wave is much smaller than that of a turbulent one, and more surface area equates to more dross formation. Typically, increasing the wave height results in increased turbulence and thus more dross. 3. Nozzle Design Some nozzles are designed to avoid unnecessary turbulence when the molten solder reenters the solder reservoir. Guide plates smoothen the downward fall of the flow and shelter the surface of the solder from direct contact with air. 4. Solder Temperature The oxidation rate of liquid solders is not linear, but increases at an accelerated rate with temperature. The particular oxide(s) that forms also depends upon temperature. 5. Solder Alloy The amount of dross depends on oxidation characteristics and the concentration of constituent metals in the alloy. For example, tin, which is a major constituent of most lead-free solder alloys, undergoes rapid oxidation in air. Therefore, high-tin-content, lead-free alloys will produce high dross levels if measures such as nitrogen inerting are not taken to impede its formation. 6. Frequency of Removal Dross on the surface of a solder pot hinders further dross formation. Hence, the frequent removal of dross is not recommended. It has become customary to remove dross once or twice per shift when soldering under ambient conditions. Removal can substantially increase operational costs through increased solder consumption, and reduce throughput due to production interruptions. 7. Operation Time Significantly more dross is generated by an operational wave compared to when the pumps are switched off. Equipment manufacturers therefore provide proximity switches that turn a wave on only when an assembly is approaching. After a delay due to inactivity, the wave is either switched off or set in a standby mode to maintain a minimum nozzle temperature.
D.
Health Issues
1. Oxidation of Lead The question of lead oxides is a question of health because lead oxides are easily airborne. As inhaling lead is far more critical than ingesting it (although ingesting is also a major health hazard), it is most important to avoid lead oxides from becoming airborne, or to eliminate their formation in the first place. Inerting is one effective measure that suppresses the oxidation of lead. Blood tests conducted on individuals involved in soldering operations involving eutectic Sn–Pb solder do not typically indicate elevated lead levels, but the utilization of lead-free solders eliminates this concern [3]. 2. Accumulation and Direct Contact with Nitrogen Nitrogen, by itself, is not toxic; we inhale a good amount of it with each breath. However, if allowed to accumulate, a reduced oxygen environment can lead to suffocation. Liquid nitrogen emanating from a tank is very cold and can cause frostbite. In addition, cold liquid or gaseous nitrogen is heavier than air, and it tends to accumulate in low-lying areas. Because of strict rules governing the installation of tanks and lines, accidents related to these dangers are quite rare.
INERT ATMOSPHERES IN LEAD-FREE SOLDERING III.
FACTORS TO CONSIDER
A.
Residual Oxygen Level
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The effectiveness of a nitrogen atmosphere largely depends upon the purity of the atmosphere, as indicated by Fig. 1. The major impurity of concern is oxygen. Therefore, nitrogen gas utilized for inerting in reflow or wave soldering applications is rated based on its ROL (i.e., the oxygen content). Oxidation effects are nonlinear, with a significant reduction observed below 50–100 ppm O2. Early investigations [4] determined that wetting, the onset of wetting, and other wetting measures exhibit a similar dependency on the ROL. However, the issue of the requirements for a specific soldering process is still being debated and will intensify more as lead-free transition occurs. A review of the literature indicates clear differences in protective atmosphere requirements for surface-mount reflow situations compared to wave soldering. That is expected, as the circumstances are quite different. During the wave soldering process, the metal features to be soldered are barely protected by LSFs during heatup (just prior to wave soldering) and the solder bath is maintained at a higher temperature than a reflow process actually experiences. During reflow processing, the flux paste protects the base metals and the maximum temperature is at least 25jC lower than wave soldering. In wave soldering, the atmosphere over the solder should be maintained at least below 50 ppm ROL. However, a level below 20 ppm O2 is recommended. The atmosphere in the exit area is of less importance, but excluding oxygen facilitates the containment of nitrogen in areas where inerting is important. In a tunnel system, the ROL should follow the temperature: the higher the temperature is, the lower is the respective oxygen level. It has been determined that oxygen levels of 100–500 ppm in the area before the solder pot and approximately 1000 ppm in the preheating area are satisfactory levels. For boundary systems, where only the solder pot area is protected, actual ROLs are hard to establish. Consequently, the atmosphere and inert gas flow levels are often set based on the manufacturer’s suggestions. Effective and optimized boundary systems, which are typically hoodless, have less than 10 ppm O2 when a board is present over the wave. Inerting the fluxing area is also advantageous, as spraying a high-alcohol-content liquid represents a potential fire hazard. In surface-mount reflow soldering, there is little in the literature to indicate that extremely low ROL values are required. Less than 100 ppm O2 in the peak zone and 500–1000 ppm in the remainder of the system are typical practices.
FIG. 1 Residual oxygen level (ROL) impact on relative wetting time. (After R. Lea, Ref. [4], 1992).
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THERIAULT ET AL. Board Surface Finishes
1. Storage It has always been recognized that PCBs with bare copper pads and traces cannot be stored in an ambient atmosphere for prolonged periods. The exact amount of time is very situation-dependant. Utilizing an inert atmosphere is one method intended to increase the shelf-life of PCBs and components. Additionally, moisture-sensitive parts that have completed bakeout, or those unused components remaining in plastic bags that have been opened are often stored in cabinets purged with nitrogen [less than 5% relative humidity (RH)] to prevent the absorption of moisture. 2. Thick Protective Layers A number of surface finishes have been utilized over the years to protect against oxidation of solderable features. Hot air solder leveling (HASL) and rosin (lacquer) coatings, once popular, are now disappearing due to thick and irregular deposition. With the advent of fine pitch, HAL surface finishes have become a liability. These finishes have been moving more toward thinfilm deposits, which are thin, uniform, and planar. Planarity is an important characteristic for fine-line applications. This realization has directed the search for viable surface finishes that fulfill this condition. 3. Thin Protective Layers Several thin-film finishes have received considerable attention: Ni/Au, Ni/Pd, Ni/Pd/Au, pure Sn, and pure Ag, to name a few. There are also planar, nonmetallic finishes referred to as organic solderability preservatives (OSPs). a. OSPs with Low-Solids Fluxes. OSP is a term for a variety of proprietary surface finishes applied to copper features on laminates intended to be solder-wettable to provide oxidation protection. The treatment ensures good storage properties and provides a planar surface for paste printing and component mounting. OSP finishes are also used in wave soldering applications because they provide an excellent surface for solder wetting, resulting in joints that exhibit high strength. The use of OSPs has resulted in major cost savings compared to other surface finishes in some applications. It should be noted that compounds attached to the bare copper surface are released above 120–140jC for PCBs intended for soldering with eutectic Sn–Pb, and thus the oxidation protection OSPs provide is rapidly lost at elevated temperatures. Therefore, inerting with nitrogen is recommended, particularly in cases where a product experiences multiple heating cycles (such as adhesive cures cycles, multiple passes involving wave and reflow soldering, etc.). Release temperatures are likely to be higher for PCBs with OSPs formulated for use with lead-free solders whose melting temperatures are typically about 40jC higher than eutectic Sn–Pb. OSPs are not new but their use with LSFs was somewhat revolutionary. Besides being a major cost advantage, particularly in high production environments, the surface is planar, the joints are usually stronger than other finishes, and the defect rate compares to prefine-line HASL rates. Nitrogen inerting is utilized in processes beyond 120jC; however, because much assembly is conducted by utilizing nitrogen anyway, this if often not an additional cost.
C.
Low-Solids Fluxes
Fluxes, originally consisting of about 20–40% rosin, have undergone a significant reduction in solids content. Low-solids fluxes, developed to eliminate the need for postsoldering cleaning operations for cost and environmental reasons, are typically formulated with about 2–5% rosin. 1. Reduced Flux Deposit LSFs allow the use of spray fluxers, which are prone to maintenance problems at higher rosin levels. Reducing the rosin content by a factor of five or more and the amount of flux dispersed on a card by a factor of about four (depending on the spray flux application system) has resulted in flux reduction during wave soldering of up to 100 times less than originally utilized. This follows
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directly from the reduction of solids content (i.e., from approximately 40% to less than 2%) and the use of spray fluxers rather than foam fluxers, resulting in a further reduction by a factor of three or four. 2. Surface-Mount Reflow A similar situation exists in surface-mount reflow applications utilizing low-solids pastes. Lowsolids pastes have greatly reduced activator content. It is not surprising that nitrogen inerting has greatly aided the wetting process given the very significant changes in flux systems and activity levels of reduced solids formulations used for reflow and wave soldering.
D.
Impacts and Limitations
Changing an important parameter, such as the interfacing atmosphere from a reactive (oxygen) to a nonreactive (nitrogen) condition, has implications beyond just oxidation. For example, it is necessary to understand the compatibility of various activator systems with nitrogen. Also, an increase in solder pickup, or a higher wave, due to an increase in surface is observed during wave soldering when the atmosphere is changed from oxygen to nitrogen. Many early users that inerted wave soldering equipment found that it was important to redesign the printed wiring board if low defect rates were to be maintained. Certain geometries were not favorable, and minimum distances between pads and components had to be redefined. It was soon learned what the limitations were with the designs at that time because the success with using newly implemented nitrogen inerting systems was very limited. If aggressive fluxes or pastes are used during the assembly process, typically little or no benefit in defect reduction is observed with the use of inerting atmospheres. However, aggressive fluxes require a cleaning step after soldering. Together with the use of no-clean fluxes, especially for fine-line applications, inerting allows the elimination of the cleaning step.
IV.
INERT ATMOSPHERE OPTIONS
A.
Nitrogen (N2)
Nitrogen gas forms about 78% of the Earth’s atmosphere and, in chemical combination, is also prevalent in many other forms of nature. As early as 700 BC, the Chinese realized that air contains an active and an inactive substance. It was not until 1772 that Rutherford discovered nitrogen and Schelle later showed that it was present in the atmosphere. In France, Lavoisier proved the substance to be an element and named it ‘‘azote,’’ from the Greek meaning ‘‘without life.’’ The name ‘‘azote’’ is still used in French today. Chaptal later suggested the name ‘‘nitrogen’’ because it was found to be a constituent of niter, a substance now known as potassium nitrate. Nitrogen, like noble gases Ar, Ne, and He, with its outer electron orbitals filled is also chemically benign. However, nitrogen is significantly more abundant in the atmosphere than noble gases. Noble gases, therefore, are too expensive to be utilized for general applications such as inerting of soldering machines. Nitrogen is thus the gas of choice used to displace oxygen. Because nitrogen is a colorless, odorless, and tasteless gas, one cannot detect its presence in any excess concentration. Its greatest hazard, therefore, is as a simple asphyxiant. Asphyxiation occurs when the percent of oxygen in the atmosphere entering the lungs is too low to maintain essential levels of oxygen in the blood, and subsequently life itself. Nitrogen boils at about 195.8jC and hence is supplied under pressure as liquid nitrogen, which is very cold and can cause severe damage to unprotected skin. 1. Manufacturing and Supply Options Nitrogen is extracted from air, and thus presents a zero-sum result as far as the environment is concerned. That is, the nitrogen extracted from the air is returned to it, and the air is neither depleted nor enriched because of this cyclical process. There are two distinct ways to extract nitrogen from air: cryogenic and noncryogenic production.
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a. Cryogenic Systems. Cryogenic production involves large air separation units. Air is taken to very low temperatures until liquefied, and can then be separated into its various components, where various species are removed in a distillation column. These production units supply bulk nitrogen in liquid form, or gaseous nitrogen via pipeline to large gas consumers. Bulk products delivered to filling centers also allow the packaging of liquid dewars and the conversion from liquid into gas for high-pressure compressed gas cylinders. b. Noncryogenic Systems. Noncryogenic systems, also called on-site systems, involve producing gas directly on a customer’s premises. This is possible because the raw material (air) is present everywhere and is typically accomplished using gas separation technology based on adsorption or permeation. Membrane systems, pressure swing absorption (PSA) units, or the more sophisticated liquid-assist systems enable nitrogen to be produced directly at the customer’s site in compliance with various criteria involving purity, consumption profile, and pressure, and assure a sufficient backup supply. c. Purity. With these different processes, it is possible to provide nitrogen from a purity of 95–99.99999% (0.1 ppm), depending on application requirements. Obviously, different processes and purities result in cost differentials, which are also affected by the amount consumed and the delivery system chosen. d. Mode of Supply. The selection of the most appropriate and cost-effective mode of supply is generally based on technical requirements, economic conditions, and factors such as safety, real estate availability, and local municipal regulations. Process purity, pressure, flow rate, temperature, and state (gas or liquid) all impact the mode of supply required by the process. Economic factors such as market prices and availability of bulk gas, when combined with volume requirements and hours of consumption per month, are contributing factors in the selection process. In general, cylinders and liquid dewars are for small usage. For large volume consumption, cylinders become cumbersome and are not cost-effective. Gas from bulk storage is very flexible and is best when the usage is variable. When the usage is relatively large and constant, on-site production may be the best choice depending on the local pricing of cryogenic or noncryogenic production. Because most PCB assembly processes require a high-purity atmosphere (<1000 ppm), liquid nitrogen or liquid-assist on-site systems are typically recommended for assembly operations [5]. The major modes of supply are briefly discussed in the following sections: 1. Cylinders—Nitrogen-compressed gas cylinders come in various sizes and are made of high-strength steel. Equipped and maintained to ensure total safety, they are generally delivered to customers by a distributor using its own trucks. Cylinders are used for relatively low gas consumption requirements. 2. Portable liquid cylinders or dewars—The liquid cylinder, as a supply mode, bridges the gap between high-pressure cylinders and bulk supply. It combines the cylinder advantage of portability and size, with the bulk advantage of a more efficient package to product weight ratio normal for gases being handled in the liquid phase. The liquid cylinder is a ruggedly constructed, highly sophisticated thermos bottle. This allows the use of nitrogen in liquid (chilled) form, which, if desired, can easily be converted to gaseous form. Liquid cylinders utilized for nitrogen service typically contain 176–240 L of liquid nitrogen (113–155 N m3) and weigh roughly 273 kg when full. This is nearly equivalent to 20 standard-size high-pressure cylinders in terms of contained volume. The delivery pressure may be adjusted within a range up to 12 bar, and a single cylinder has the capacity to maintain a 6-hr continuous flow rate of 10 N m3/hr nitrogen at an ambient temperature of 15jC. A greater gaseous flow may be achieved with an external vaporizer. If a cylinder remains idle for a period of time, normal internal evaporation increases the pressure within the headspace above preset levels. The normal nitrogen evaporation rate of an idle cylinder would be about 2% of full cylinder content per day. One liter of liquid nitrogen is equivalent to 765 L of nitrogen gas. The excess pressure, if not used during the processing, must be evacuated in order to avoid a safety hazard. This is achieved through a pressure relief valve, which is required of these types of systems. If the pressure relief for
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one or more of these systems is conducted in a confined area, this can pose as a potential health and safety concern. 3. Bulk supply—Delivered bulk liquid nitrogen—the traditional supply method of choice for lower-volume and higher-purity requirements—offers excellent versatility. Stationary storage tanks, cold converters, or road tanker trucks are highly insulated containers designed to store or transport gases in liquid form at temperatures ranging from 182jC to 269jC, depending on the gas. Storage tanks and units that convert liquid nitrogen to gaseous nitrogen, sometimes referred to as cold converters, are installed at the customer’s site to provide a reserve gas supply and enable much greater self-sufficiency than is possible with cylinders. The nitrogen can be used in either gaseous or liquid form. 4. On-site PSA—Pressure swing absorption systems have been available commercially for at least 25 years. Recent improvements in the performance of carbon molecular sieves at the heart of PSA units have made the technology more efficient. After going through an air pretreatment unit, air then passes through two sequential operating towers that are packed with carbon molecular sieves. Oxygen is absorbed in the porous sieve material, leaving nitrogen that is delivered at the top of the towers. These on-site systems can achieve purity levels of up to 99.9% N2 (1000 ppm O2), which can be cost-effective relative to liquid nitrogen in some areas of the world. 5. On-site membrane production—Membrane technology is a relatively new process technology. The polymer science that is involved with membrane design is still in a state of evolution. However, the performance of membrane systems is steadily improving and already is generally more cost-competitive than PSA systems. Once again, air is passed through an air pretreatment unit to remove basic particulates and oil, and then injected through a hollow polymeric tube membrane. Oxygen diffuses out of the tube much faster than nitrogen, with the nitrogen emerging axially at the end of the fibers. Hundreds of thousands of these hollow polymeric fibers are packed into a bundle membrane ‘‘module’’ in a tube and shell configuration. The number of modules in a particular system is dependent on nitrogen requirements. These membrane-based systems can achieve purity levels up to 99.9% N2 (1000 ppm O2), making the technology a cost-effective alternative to delivered liquid nitrogen in some regions of the world. 6. On-site, high-purity, liquid-assist systems—Recent improvements and developments in on-site nitrogen generation have led to the introduction of modular and compact high-purity systems. The cost reduction afforded by these systems, without compromising nitrogen purity, is dramatical. Typical cost savings over liquid nitrogen range from 20% to 40%. The liquid-assist system also has the advantages of reduced truck traffic and higher reliability. These systems use a special cryogenic process that utilizes between 1% and 3% of the total nitrogen flow rate requirement to constantly prime the system. The liquid nitrogen is supplied through an integrated storage tank that also ensures an uninterrupted supply. These systems feature load following, an attribute to adjust production to actual requirements, and automatic start-and-stop capabilities. The result is a very consistent and reliable high-quality product with a typical maximum content of 3 ppm O2. 7. Pipeline—Gas pipelines, which link large cryogenic gas plants directly to end users, ensure a continuous and uniform supply of very large quantities of gas. A pipeline supply is usually the option of choice. However, limited pipeline opportunities exist, so that this option is available only in rare cases and in few selected industrial parks around the world.
V.
LEAD-FREE SOLDERS AND NITROGEN INERTING
A.
Activators in Flux
1. Wave Soldering In wave soldering, activator agents within the flux serve to remove oxides on metal surfaces of boards and components, and also help to prevent bridging, flagging, etc. that occur near the exit
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of a wave. Poor wetting, however, also occurs if the activation reaction is premature. It is generally required that printed circuit boards achieve a temperature of about 110jC prior to entering the wave, as measured on the top side of the laminate material. This corresponds to an approximate temperature of 145jC on the bottom side. Thus, the temperature increase from a preheat station to the wave is limited to 100jC or less to assure the integrity of many components. Activators in fluxes are chosen to react at a temperature close to the melting point of the solder to adequately prepare the surface for reflow and not allow time for the surface to again become contaminated through reoxidation, etc. 2. Reflow Soldering In surface-mount reflow soldering, the profile frequently contains a ‘‘plateau’’ at approximately 150–160jC for eutectic Sn–Pb solders to allow for thermal variations on the board to equilibrate. This type of profile alleviates large temperature differences (DT) that result between two components or other attachments in close proximity that vary significantly in their mass. The plateau temperature cannot be too high as it may have a deleterious effect on the activity of the flux, rendering it ineffective during the reflow period. Because the purpose of the plateau is for a solder assembly to achieve thermal equilibration, the assembly must be idle at the plateau temperature for some time (typically a few minutes). If the plateau temperature is too high, too much of the active ingredient of the flux will dissipate, and thus lose its activity and its effectiveness. a. Paste Effects. Coalescence of solder paste particles may be inhibited during surfacemount reflow soldering if a high-temperature plateau causes the activators to disassociate too early. Sufficient flux activity is necessary to eliminate oxide layers on individual solder paste particles. b. Higher Temperatures for Lead-Free Solders. A key difference of lead-free solders is their significantly higher melting temperature (typically about 40jC higher) as well as their higher reflow temperatures compared with eutectic Sn–Pb. Maintaining the approximate 100jdifference between the preheat and the solder wave, as noted earlier, is a standard practice for eutectic Sn–Pb, and therefore requires a substantial increase in preheat temperature for most lead-free alloys. Assuming a solder temperature of 285jC, the bottom temperature of a PCB cannot be much lower than about 185jC. Accounting for differences among laminates, the temperature difference between the top and the bottom of a PCB is about 35–40jC, requiring the top temperature to be adjusted to 140–145jC. The 185jC temperature that the flux will experience represents a challenge because activators utilized for eutectic Sn–Pb solder are not effective at that temperature. New formulations or other solutions are necessary for lead-free alloys to be successfully used in manufacturing environments. c. Temperature Reduction. Early on, it was believed that a peak reflow temperature of 260jC or more may be required for most lead-free solder alloys. There now appears to be a sufficient body of data that indicates that good solder joints can be achieved at a peak temperature of about 235–245jC, which is about 10–20jC higher than that presently used for eutectic Sn–Pb. In order to maintain the same properties, a plateau temperature of approximately 170–180jC is required for most lead-free solders. Until new activators that are compatible with these elevated temperatures are identified or formulated, a dramatical increase in wetting-related defects may occur. Board materials compatible with high lead-free solder reflow temperatures are also necessary because the plateau temperature is above the Tg of FR-4 laminate. Problems associated with board war page and discoloration may be observed if standard FR-4 boards are utilized for lead-free solder applications.
B.
Wetting
Wetting is the interaction that takes place between the liquid solder and the mating solid surface. Wetting is the most important soldering parameter because it is responsible for the integrity of solder joints. Conversely, poor wetting accounts for the vast majority of solder joint defects that occur. Many factors contribute, among them: choice of metals, surface conditions, cleanliness, and the choice of solder, to name a few. Wetting is a surface phenomenon that relies on molecular
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bonding and attraction. There are a number of situations where wetting occurs without a chemical reaction or intermetallic compound formation. However, in soldering, a chemical reaction between the tin in the solder and solder-wettable circuit features normally occurs quite rapidly. 1. Surface Tension Closely related to wetting is the molten solder’s surface tension. In conjunction with wetting force and gravity, it determines the final shape of a solder joint. However, widely different values can be recorded when measuring surface tension due to a fundamental problem when determining the surface tension of solder—at least in air (i.e., in the presence of oxygen). Properly conducted tests substantially overcome these problems under inerted conditions. In air, liquid solder is covered with an oxide layer. Surface layers floating on the surface of molten solder interfere with the surface tension measurement. Systems that are measured or tested in air are not a true liquid solder/air interface, but rather a system consisting of liquid solder/oxides/air interfaces. With nitrogen inerting, the formation of oxide films can be avoided to not only provide enhanced solder wetting characteristics, but also to assure the true liquid solder surface tension properties necessary for several assembly operations. 2. Effects of Temperature Temperature is of vital importance when soldering. Several key characteristics strongly depend on it, including: surface tension, viscosity, and wetting force. What has been observed for leadbearing solders also holds true for lead-free alloys: Wetting performance is better at higher temperatures. 3. Effect of Nitrogen Inerting Not discounting that increasing reflow temperature results in higher integrity solder joints, it has also been reported [6] that at the same temperature, integrity is also enhanced when nitrogen inerting is utilized. These observations have been made over a range of temperatures. A comparison of air vs. nitrogen wetting curves for solders shows nearly parallel lines, which are interpreted as a temperature shift. In other words, depending on the alloy, the same wetting performance may be achieved at a 10–20jC lower temperature when comparing a nitrogen atmosphere with air, as noted in Fig. 2. This temperature reduction provides a significant advantage with regard to components and board integrity, flux activity, and energy consumption.
FIG. 2 Time to 2/3 wetting force vs. atmosphere for various alloys. (After C. Hunt, Ref. [6], 2000).
580 C.
THERIAULT ET AL. Dross
1. Quantity Wave soldering with lead-free solders necessitates two major changes: higher solder pot temperatures, and an increased tin content in the alloy. Both of these changes affect the production of dross in the presence of oxygen. Dross is the silvery sludge that covers the surface of the pot and is formed in wave soldering when the molten wave of solder comes in contact with the oxygen contained in atmospherical air. The pot temperature is anticipated to be approximately 285jC, or an increase of about 35jC over the methods used for eutectic Sn–Pb solder. Using the rule-ofthumb for chemical reactions (i.e., each 10jC increase in temperature results in doubling of the reaction rate) and neglecting the contribution from the increased tin content, the expectation is about an 8–11 times increase in dross compared to the lower Sn–Pb eutectic pot temperatures. This is, of course, a rough estimate. Although some reports suggest that the generation of dross will not be increased, some convincing research indicate five to seven times as much dross when operating in air compared to nitrogen inerting [7]. 2. Dross Composition The composition of the dross typically depends upon the alloying elements present in the solder. For example, dross from a eutectic Sn–Pb bath does not contain lead under normal conditions. Typically, metals that are added to the solder to enhance properties contribute to dross formation if they oxidize at 285jC. The rate of oxidation is dependent upon several factors such as temperature, surface area of the metal, oxygen concentration, concentration of moisture in the air, the type and extent of alloying, and the presence of a protective oxide layer on the molten metal surface.
D.
Cleaning Residues
Residues left after the assembly of a printed circuit board, particularly from flux, have been altered during the heating process, especially when oxygen is present. Printed circuit boards achieve a peak temperature of about 250jC locally and 215–225jC generally throughout the board during reflow soldering. The most commonly encountered residues are those that start as rosin (colophony), a component in many flux materials. Rosin is derived from pine tree extract that is processed to form a mixture of several isomeric acids, primarily: adipic acid, D-primary acid, and L-primary acid. Adipic acid (about 80–90% of the total) melts at 174jC, and at about 300jC, it changes to neoadipic acid whose melting point is slightly lower. When overheated, rosin undergoes several changes: it turns dark (oxidizes), polymerizes, and loses its activity. Other flux ingredients undergo changes as well, such as volatilization reactions with oxygen, and react with other chemicals present on the board. When inerting is utilized, oxidation is excluded from possible reactions. This is important because, in general, it is observed that postsoldering residues are much easier to remove (i.e., clean) if the soldering operation is conducted in an inert atmosphere compared to that in the presence of oxygen. The removal of residues is particularly important in meeting ionic residue and insulation resistance requirements.
E.
Nitrogen Inerting Improves Yields
1. Early Experience Early reports on defect levels due to wave soldering when using nitrogen were inconclusive and contradictory. A better understanding of the factors that are affected when utilizing inerting was necessary. Additionally, in many cases, two changes were implemented simultaneously: the use of an inert atmosphere and an LSF. Accordingly, defects associated with LSFs were much reduced when compared with standard fluxes. That is, the reduction in flux activity, owing to the reduction in flux rosin content, was not a deterrent when used with proper inerting.
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2. Inerting Proves Highly Beneficial It was soon recognized that with a proper PCB layout, defect levels in inerted machines were much easier to control. For example, it is a relatively easy matter to control parameters utilizing inerting systems, which were virtually impossible to control as open systems. Defect reductions of about 50%, which translate to a yield improvement of between 5% and 7%, have typically been observed by Gerhard and Kiecker [8]. However, early on, no impact on defects had been observed. This discrepancy may be explained by statistics that included data on the finest pitch on the board. There seem to be two variables that affect this performance: pitch and activity level of the flux/paste.
VI.
NITROGEN AND LEAD-FREE WAVE SOLDERING
A.
Increased Dross Formation
Based on theoretical considerations, the formation of dross is five to seven times greater for leadfree alloys compared to 60Pb–40Sn or eutectic Sn–Pb alloys because of the increased tin content and soldering temperature [7]. In certain minimum cases, the dross doubles or triples. In addition to better yield and increased reliability, substantial reductions in dross formation to reduce cost are another reason for implementing nitrogen inerting. 1. Cost of Nitrogen Inerting Determining the cost of nitrogen and equipment is a fairly easy process. In addition, the use of nitrogen in wave soldering almost always yields a cost benefit. The easiest and most tangible method to determine the savings realized is to simply keep track of the reduced amount of dross formed and the reduction in flux needed to achieve results similar to soldering in ambient conditions. The cost of nitrogen is almost always less than the amount of material savings. Quality and reliability effects are added bonuses that can make the cost of N2 irrelevant. In the case of lead-free processing, these saving are even greater because the cost of the new solders is much greater and is more difficult to solder.
B.
Flux Reduction
Whenever contemplating the choice of flux, there is a tradeoff between good wetting and the amount of residues left on the assembly after soldering. Studies conducted at AT&T [9] indicated that there are no ‘‘harmless’’ residues, and that all are potentially detrimental to reliability and performance. Their impact must be assessed in each individual case. The studies also showed that the amount of flux deposited is directly proportional to the decline in the surface insulation resistance (SIR) value of the final product. The industry has opted to use flux deposition methods in wave soldering (e.g., spray with ultrasonic, gas pressure, or liquid pressure) that control the amount of flux on a board. The optimum amount of flux required for good solder joints is a tradeoff between the volume and the assurance of acceptable SIR values. 1. An Industry Case Study Deciding which flux to use has a direct impact on solderability as well as the cleanliness of postsolder assembly. In one example, Passman et al. [10] switched to a low-solids flux 1 year before inerting in order to improve their process. They replaced a foam fluxer with a spray version and changed the flux medium from 20% to 2% solids. The benefits they realized were immediate and among them were: increased SIR values, savings in flux/alcohol, reduced handling and storage of alcohol, and reduced volatile organic compound (VOC) emissions. This change did, however, reduce the process window that has subsequently widened with the use of nitrogen. In addition, the nitrogen allowed for milder or less flux usage and less decomposition of the flux itself.
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FIG. 3 Effect of superheating temperature with a nitrogen inert atmosphere on wetting time and force. (After C. Hunt, Ref. [6], 2000).
C.
Wetting of Lead-Free Solders
Research has shown that each lead-free alternative tends to have different wetting properties. Not all formulations follow one particular wetting pattern when it comes to metal content, such as simply tracking the amount of tin to determine wetting characteristics. However, similarities can be seen when superheat (i.e., the number of degree above the melting point for any given solder) is tracked vs. wetting capability, as is indicated in Fig. 3.
FIG. 4 Soldering temperature impact on wetting time for various alloys with and without a nitrogen atmosphere. (After R. Iman, Ref. [13], 1997).
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Effect of Nitrogen on the Wetting Temperature
The wetting performance of several lead-free alloys was evaluated with and without inerting as a function of temperature (Fig. 4). For all alloys tested, including the Sn–Pb control, wetting was enhanced by inerting at all temperatures. The difference in wetting performance in air compared to nitrogen varies among the alloys tested and clearly illustrates that Sn–Pb with and without inerting provides better wetting than any of the lead-free alloys depicted on the graph if reflowed between 220jC and 240jC. Additionally, Fig. 4 provides the reflow temperature reduction for the same wetting performance. Consider, for example, wetting performance represented by nitrogen and air curves for the same solder at corresponding temperatures. The figure indicates that the same degree of wetting can be achieved at a temperature 20–40jC lower by utilizing inerting. Hence, nitrogen inerting may be viewed as a method to lower the temperature during a soldering operation. This aspect of inerting could be very helpful given the temperature sensitivity of components, fluxes, and board materials. The ability to reduce the reflow temperature by 10–15 K or more can make the difference between a quality result and a high-risk process.
VII. A.
NITROGEN IN LEAD-FREE REFLOW SOLDERING Pastes and Reflow Profile
The most common reflow profile allows a board assembly to idle (i.e., plateau) at a temperature approximately 50jC below the melting point of the solder alloy for a sufficient period of time so as to assure that the entire assembly is at the equilibration temperature. This is performed just prior to raising the assembly to the peak reflow temperature. A less commonly used profile eliminates the plateau feature, so that the temperature of an assembly continuously increases to the peak temperature. This approach is typically utilized with small, low-mass assemblies and also on assemblies with reduced reliability requirements. The throughput, of course, is greater using a profile without a plateau. Large, high-mass assemblies or those with components of varying mass typically utilize a profile with a plateau. If either the process or thermal characteristics of a card assembly give rise to significant temperature differences within the assembly during the reflow process, a thermal profile with a plateau is usually better than one without a plateau. The intent is to minimize thermal differences when rapidly ramping to the peak reflow temperature. If, however, the nature of the card assembly (i.e., small, low mass, etc.) is such that only minimal temperature differences will develop during assembly, a thermal profile without a plateau is preferred. 1. Effect of Raised Plateaus on Paste Activation Activators in solder pastes often consist of organic acids that degrade with time and temperature. These acids have been selected to react with oxides of lead-containing solders. They are selected because their activity is near optimum in the vicinity of the melting points of these solders. The effectiveness of activators typically decreases at higher temperatures or over time at elevated temperatures. As noted earlier, lead-free alloys require high reflow temperatures compared to eutectic Sn–Pb—with thermal profile plateaus in the range of 180–190jC, which are too high for fluxes formulated for eutectic Sn–Pb solder. The oxidation of rosin in air and the increased polymerization at elevated temperatures result in residues that are very difficult to clean with standard solvents. Flux vehicles selected for use in lead-free solder pastes are dramatically different from those used in eutectic Sn–Pb solder pastes. It was determined that cleaning products that preformed very well with eutectic Sn–Pb technology did not remove some residues left as a result of the new flux vehicle formulated for a lead-free solder [11]. 2. Effect of Paste Particle Size In assembly applications, the coarsest paste particle size is chosen to accommodate the finest pitch on an assembly. Hence, the finer the pitch is, the finer is the paste particle size required. As the paste particle size decreases, the ratio of exposed surface area to metal volume increases
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dramatically. Consequently, controlling metal oxides, particularly tin oxides, becomes a key concern. a. Activators. The idea of utilizing a paste without an activator seems particularly questionable in fine-pitch applications given the issue of increased surface area. A certain amount of activator appears to be required, even if the base metals are generally clean, in order to remove the oxide layer present on each solder particle in a paste. Without a minimum level of activation, individual particles do not coalesce into a monolithic mass when they become molten. To avoid the necessity of a postsoldering cleaning operation, paste manufacturers have opted to formulate fine-pitch pastes with low levels of activators. However, this limited aggressiveness demands parts and components to be prepared to a condition of ‘‘above average solderability.’’ Inerting has proven to substantially aid this wetting process. The lower the activation of a flux or a paste is, the more beneficial it is to utilize an inert atmosphere. Similarly, the finer the paste particle size is, the more likely inerting will improve the overall soldering results.
B.
Role of Nitrogen
Wetting studies were conducted on copper coupons exposed to varying ROLs. The copper coupons experienced different aging conditions to produce a range of oxide thickness layers. The wetting studies indicated that very solderable surfaces continue to exhibit good wetting over a range of ROLs (i.e., are not highly sensitive to the oxygen level in the ambient air). However, those that do exhibit a sensitivity to the reflow atmosphere (i.e., thicker oxides) show the best wettability at the lowest ROLs. Accordingly, products with variable solderability can be successfully assembled with more or less the same parameters utilizing a nitrogen atmosphere. This can be interpreted as a ‘‘widening of the process window.’’ The process becomes more forgiving under nitrogen than in air. Excellent solderability does not gain much from the presence of a nitrogen inerting atmosphere; it seems, however, that even a minor deficiency in solderability benefits from inerting. This implies that if all the boards and components always exhibit excellent solderability, then nitrogen inerting will not significantly improve soldering parameters. In the more realistic case of varying solderability, however, the set of process parameters is much broader with nitrogen inerting compared to air.
C.
Double-Sided Reflow
The need to provide smaller, lighter-weight products with ever-increasing functionality has led to optimization of several areas. One is to make efficient use of printed circuit board areas by utilizing both sides of boards to mount components. Surface-mount technology (SMT) lends itself particularly well to this approach. There are several ways of accomplishing an effective double-sided reflow process. The two significant parameters are: the number of reflow passes in the furnace (typically, one or two), and the number of solder pastes utilized (again, one or two). In some cases, it is necessary to glue the components onto the bottom of the board to ensure maintaining their position during the first pass. In addition, when two solder pastes are used, the higher-melting-point paste is reflowed first, which avoids remelting when the second pass occurs at a temperature sufficiently above the low-melting-point solder to properly reflow, but below the solidus or melting temperature of the high-melt solder. The main concern in double-sided reflow is component adhesion when the board is inverted. The choice of component location is crucial at the design stage to ensure component adhesion. There is a distinct advantage in conducting the aforementioned process under an inert atmosphere because the wetting force under nitrogen is higher. Thus, a nitrogen atmosphere provides additional assurance that components attached to the bottom of the board will remain in place even when the solder becomes molten during the second pass reflow attaching the top-side components. Overall, a little design work and thoughtful preparation will ensure the proper process flow and choice of materials.
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585
Through-Hole Reflow
Designers are finding it difficult to utilize only surface-mount reflow attachments to meet their requirements. This may be due to several reasons such as a component’s availability in a specific form, the cost of a component, or the reliability when mounted as a surface-mount component. Occasionally, some components are only available in a leaded form that requires PTH processing. In these cases, the option is between ‘‘selective soldering’’ (i.e., machines designed to solder one joint at a time) and PTH reflow. Because the PTH reflow production process is shorter, this is, therefore, the attractive option. The design must be adequate to allow sufficient paste in the board’s through-holes to establish acceptable joints with the component’s leads. The excess paste required for PTH reflow can potentially cause solder bridging beneath a component. However, the use of a nitrogen atmosphere is very helpful in gathering paste particles in through-holes due to the improved wetting it provides. Based on this fact, nitrogen is traditionally used for this application.
E.
High-Temperature Soldering
The automotive electronics industry requires solder joints that can withstand elevated temperatures. The trend is to place electronics outside the firewall, and to mount chip carriers on the engine block, or, as part of brake systems, these applications require that solder joints be capable of operating at temperatures above 140jC. Eutectic Sn–Pb solders cannot meet these conditions because the temperature is too close to the solder melting point (mp=183jC). In these cases, alloys are used whose melting points lie at least in the range of 230–250jC, and in some cases closer to 280 to 290jC. These high-temperature solders are prone to oxidation when processed at elevated temperatures. The use of nitrogen inerting significantly improves the problematical wetting behavior of these alloys. Any additional cost is typically more than justified by the greatly enhanced yield and reliability benefits.
VIII. A.
NITROGEN CONSUMPTION AND COST ISSUES Wave Soldering
Wave soldering equipment have undergone several changes to accommodate changes in board size and mass. Among the changes are a longer and more efficient preheat station. In addition, innovations in the gas delivery system located in the interior of these tools have reduced nitrogen consumption considerably. Typically, today’s nitrogen consumption for commercial wave soldering systems is about 15–25 N m3/hr. Originally, only full- tunnel wave soldering machines were available, which could be operated with or without inerting. A full-tunnel design is one that consists of a completely enclosed area—hence the term tunnel, which provides total inertion from the preheating to cooling sector. Currently, a variety of designs and sizes are available. The fulltunnel design is still being used, but the shorter hoodless systems with inerting placed in more focused areas have become the method of choice. These systems offer several practical advantages including lower gas consumption: typically 10 N m3/hr per wave.
B.
Reflow Soldering
Early convection ovens consumed over 50m3/hr for an ROL of 10–20 ppm. In modern systems, this consumption level has been reduced without impacting the heat transfer performance or ROL. However, as has already been mentioned, the ROL required depends on the inherent wettability of the parts to be assembled. Because the cost of inerting gas increases with purity and the need for higher flow rates to achieve a lower ROL, only a purity level necessary to achieve acceptable wetting should be used. These measures can result in substantial savings. A common recipe is to set the ROL level in the peak zone at 100 ppm, and this can usually be achieved in optimized systems with a flow rate in the range of 20–30 N m3/hr.
586 C.
THERIAULT ET AL. Differences Between Surface Mount and Wave Soldering
The reason for the difference in inerting requirements between surface-mount reflow and wave soldering is predicated on the nature and function of the solder paste that is utilized. The flux in solder paste depositions provides significant protection against oxidation for the surfaces to be soldered. At the same time, the metal powder in pastes is not exposed to oxygen and thus is protected against oxidation as well. Because the solder paste protects the surface to be soldered and metal particles in the paste, the requirements of a protective atmosphere, particularly the inerting gas purity level, are less important in surface-mount reflow soldering than wave soldering even though higher temperatures are experienced.
IX.
EFFECT OF NITROGEN ON RELIABILITY AND YIELD
Typically, joints created under inerted conditions exhibit a higher reliability than those made in oxygen-containing atmospheres. There were early indications that the higher life expectancy is due to a finer crystalline structure, but this result may have been the result of cooling conditions created by the use of nitrogen. Latest studies did not find any direct cause, although crystalline structure, grain size, intermetallics, oxygen, and nitrogen were among several parameters that were investigated [12]. However, it is believed that because surface tension and wetting under nitrogen are enhanced on a variety of surfaces, as is the fillet shape, these factors likely contribute to the observed improvement in yield and reliability. These types of improvements have been reported [13], and it is now widely accepted that the practice of utilizing protective atmospheres such as nitrogen for both surface mount and wave soldering results in solder joints, which exhibit about a 10–15% enhancement in fatigue life when compared to a joint formed in air [7,8]. The main benefits of utilizing nitrogen are cost savings associated with the reduction in dross formation, and a significantly enhanced wettability, which results in both better yield and reliability due to lower defect levels and solder joints that exhibit higher strength.
A.
Wave Soldering
In wave soldering, wetting is definitely improved and all defects related to wetting are seen to decrease under a nitrogen atmosphere. However, these findings depend upon the flux used, and are often overlooked when aggressive fluxes are used and no defect reduction is found. Although solder bridging during wave soldering greatly depends on layout and pitch, narrow spacing that is acceptable under ambient conditions may, in some cases, lead to bridging when using nitrogen. This is the result of the increased wetting force that can actually cause the wetting to be too great. 1. Design and Process Considerations As noted Sec. 8, good wetting can actually create problems. For example, during some initial studies [14], it was observed that inerting a wave soldering process increased the level of bridging boards. As it turns out, it was determined that bridging is strongly dependent on design parameters. However, these early results during industry trials are indicative of the frustration that can accompany the improper introduction of nitrogen technology. Often, it was not recognized that using an inert atmosphere has the potential to impact the entire process. For example, utilizing a nitrogen inerting atmosphere allows the use of less aggressive flux, which in turn reduces the potential for corrosion, or the use of a no-clean flux that eliminates the postreflow cleaning operation. Designers are now aware of some PCB modifications that should be made if utilizing nitrogen inerting, such as adjusting land sizes to prevent tombstoning due to enhanced wetting characteristics, etc. 2. Benefits: Fine-Pitch Capability and Defect Reduction When inerted reflow processes were introduced to attach fine-pitch components (i.e., <0.5 mm) to boards, companies reported substantial improvements in defect rates. One longitudinal study [15] reported a 50% reduction in wetting defects, and bridging also declined. It was demonstrated
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FIG. 5 Residual oxygen level (ROL) impact of debridging. (After Dong, Ref. [16], 1996).
that the ‘‘debridging’’ property was related to the flux and level of inerting. Dong et al. [16] showed that bridges created due to overprinting of solder pastes were opened during reflow soldering with decreased ROLs for pastes that were of low residue. Other solder pastes behaved quite differently, as noted in Fig. 5.
B.
Reflow Soldering
Several long-term studies show a 50% reduction in all categories of defects, which in some cases translated into a 5–7% gain in first-pass yield. Benefits due to nitrogen inerting depend on the activity of the paste, where the milder the flux activity of a paste is, the greater are the benefits that are realized. Fine-pitch boards show a markedly higher improvement in defects than coarse-pitch boards [7,8].
C.
Joint Appearance and Acceptability
Visual defects in solder joints were first defined in the now defunct military standard. The conventional wisdom of the industry was that a strict adherence to visual features generally assumed sound solder joints. It was required that they have a shiny appearance, feathered wetting angles, and a generally concave geometry. Lead-free solder joints typically deviate from this standard. However, it has been determined that although lead-free solder joints are cosmetically less pleasing, they are generally as or more reliable compared to eutectic Sn–Pb solder joints. For example, NASA determined that wave-soldered plated through-hole joints that are not completely filled tend to last longer than those that are completely filled [17]. Although postsoldering inspections are still deemed important, more emphasis has been placed on parts preparation prior to soldering and maintenance of close control of the process. Research has shown that the criteria used for visual inspection, whether by man or machine, were not good predictors of joint reliability [18,19]. Better criteria are necessary to achieve a correlation between inspected solder joint quality and actual field reliability.
X.
EQUIPMENT ISSUES
A.
Implementing Nitrogen in Wave Solder Systems
A full range of wave soldering equipment with a vast array of options and features is available on the market, some of which include inerting capability. The requirements for a wave soldering system, of course, depend upon the intended application.
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Inerting the wave soldering system may be achieved in a number of ways. Systems that only protect the solder pot area with a blanket of nitrogen gas bled over the wave crest (inert boundary) are available. Some existing systems can be retrofitted by (Fig. 6) utilizing nitrogen inerting methods that enable a significant reduction in dross formation and by providing higherquality solder joints while minimizing investment and maintaining low operating costs. These systems are improved versions of shorthood systems. The improvement of the N2 injection system and the removal of the hood or lid have brought several process and cost benefits. Inerting tunnels are available in various lengths and designs. It is easier to properly inert the critical region if the interface with the environmental air is removed sufficiently far away. Properly designed and maintained tunnel systems produce very low dross levels compared to short hoods and inert boundary systems. Capital costs of tunnels are, however, higher than localized inerting systems.
B.
Implementing Nitrogen in Reflow Systems
Many surface-mount reflow areas in ovens (IR or convection) are configured to be compatible with nitrogen inerting (some even for hydrogen use). So, in those cases, it is the assembler’s option whether to utilize a nitrogen atmosphere for a given application. The retrofitting of non-nitrogen capable machines is possible in many cases, but cost tradeoffs must be carefully considered. A number of furnace manufacturers offer units that allow conversion to an inert atmosphere. However, some older systems would require significant rework to make them nitrogen-compatible. Acquiring a new machine may make better economic sense and likely will provide much better performance and control. In cases where furnaces are modified, a careful check should be made of all moving parts, the insulation, and the location of electronics to verify that the higher temperatures demanded by lead-free pastes will not cause undue damage to these machines or pose a potential safety risk.
C.
Use of Nitrogen in Selective Soldering Systems
Selective soldering refers to situations where one or more joints must be soldered after a board has already been assembled (i.e., soldering at specific locations). In most cases, but not necessarily all, the components are leaded and through-hole-attached. A number of systems and technologies have been developed to address selectively attaching components, but the method most often
FIG. 6 Example of wave soldering boundary inerting technology. (Courtesy of Air Liquide, www. airliquide.com).
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589
utilized consists of pumping liquid solders through a small nozzle or presenting solders in some other manner (e.g., scooping, pressing through a variety of special nozzles by hydraulic means, etc.). The solder cooling rate is fairly rapid because the tube diameter is small. Therefore, these systems must operate at elevated temperatures (approximately 280jC). Experience with these systems in eutectic Sn–Pb or Sn–Pb–Ag solder applications has shown an increased rate of dross formation, and problems with tenacious ‘‘skins’’ on the flowing surface caused by the formation of metal oxides. In general, they are operated under nitrogen. Nitrogen consumption will increase with lead-free alloys because the tendency for oxidation is much greater due to their higher process temperatures. It is estimated that about 20% of the board assemblers utilized nitrogen inerting for eutectic Sn–Pb reflow, but that 90% will do so for assemblies utilizing lead-free solder. Retrofitting these robotic tools is generally possible because the area to be covered is rather limited in size and accessibility. Nitrogen consumption is typically low, except in some open systems that employ rotary transportation. 1. Laser Soldering Laser soldering provides an alternative solution to selective joining. The progression of the semiconductor laser has made this method more attractive for soldering. Nevertheless, it only represents a small niche because it requires a direct line of vision and is a rather delicate process. The use of nitrogen is not very common for laser systems because no benefit had been identified.
XI.
SUMMARY
The use of nitrogen in reflow and wave soldering equipment may benefit the first-pass yield and quality (i.e., reliability) of the end product. In the case of wave soldering, other benefits may accrue such as dross reduction, reduced solder pot maintenance, safer operating conditions, and substantial savings due to a lower flux volume requirement. The level of these benefits is even greater for lead-free soldering. In addition, because nitrogen allows for lower reflow temperatures, this is particularly important when using lead-free solders, in producing cleaner boards or easier-to-clean assemblies. A nitrogen inerting process should, however, not be adopted without fully understanding its benefits and limitations. Nitrogen for inerting is an added process cost, but its overall benefits normally outweigh the additional expense for users. The fact that more and more manufacturers are opting for inerted soldering environments demonstrates that in the end, it has a positive effect on the bottom line in a very competitive environment.
XII.
FUTURE TRENDS
Several trends in the industry will have an impact on the future use of nitrogen inert atmospheres despite continuous improvements in flux chemistry. Nitrogen utilization is anticipated to increase in the industry. As a driving force in joining technology, the component industry is steadily advancing toward finer pitches and higher input/output (I/O) counts. Wetting, bridging, and reliability, therefore, will be increasingly challenged. Mass production environments that leave less and less time for maintenance will require more consistent processes. Due to the increased complexity of assemblies and faster working speeds and frequency of active components, cleanliness will soon reemerge as a major issue. Cleaning has become a much more complicated issue due to the consequences of the Montreal Protocol and its successor agreements by the nations of the world to stop using agents that adversely affect the ozone layer in the atmosphere. Therefore, alternative methods must be developed to circumvent subsequent cleaning steps. Finally, the legislative steps taken in Europe requiring the use of lead-free solders in electronic production will have a very significant effect on electronics manufacturers. Nitrogen inerting will play a beneficial role in this conversion.
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ACKNOWLEDGMENTS We would like to express our thanks to a number of individuals who either directly or indirectly contributed to this chapter. Several of our friends and colleagues have given generous advice and counsel, in particular Mr. Philippe Blostein, Mr. Claude Carsac, and Mr. Rolf Diehm, and others too numerous to mention. Armin Rahn’s personal communication with Dr. Rolf Strauss, Dr. Laura Turbini, Dipl.Betr. Wirt. Christiane Furtner, Prof. Wolfgang Scheel, as well as Dipl.-Ing. Gerhard Schaefer and Dipl.-Ing Stefan Klein has been helpful as well. Naturally, without the support of our families, this work would not have been created.
REFERENCES 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19.
Hartmann, H.J. Erfahrung beim Lo¨ten unter Stickstoff. VDI-Ber. 1990, 805. Nowotarski, M.S. Process for Joining/Coating Using an Atmosphere Having a Controlled Oxidation Capability. US Patent 5,071,058, 1991. Biocca, P. Solder Safety and Disposal Management, Proceedings of Nepcon West; Anaheim, CA, February–March, 1994. Lea, C. ‘‘Inert IR Reflow: The significance of oxygen concentration in the atmosphere’’. Circuit World Mag. 1992, 18. Theriault, M.; Blostein, P. ‘‘Reducing the Cost of Inert Soldering’’. Circuit Assem. Mag. July 1998, 46–52. Hunt, C. Solderability of Lead-Free Alloys, Proceedings of the Technical Conference of APEX; Long Beach, CA, 2000. Schlessmann, H. Lead-Free and the Necessary Changes in Soldering Process and Machine Technology, Proceeding of the Technical Conference of APEX; San Diego, CA, 2002. Gerhard, M.; Kiecker, H.-E. Quality Improvement by the Implementation of Reflow Soldering with Nitrogen. Productronica Conference, Munich, Germany, 1996. Guth, L.A. Applicability of Low-Solids Flux. AT&T Bell Laboratories, Engineering Research Center Publication: Princeton, NJ. Passman, R.; Redwitz, K.; Theriault, M.; Wolff, P. Improving the Wave Soldering Process with New Nitrogen Retrofit Systems, Proceedings of Nepcon West; Anaheim, CA, 1999. Bixenman, M. Lead-free solder to impact precision cleaning. Electron. Packag. Prod. Nov. 2000. Reichelt, G. Investigations about the Reliability of Atmospheric and Inert Wave-Soldered 1812Capacitors at Various Footprint—Configurations, Proceedings of Nepcon West; Anaheim, CA, 1994. Iman, R.; Koom, J.F. CCAMTF Evaluations of Conformal Coating and Alternative Surface Finishes, Proceedings of the Technical Conference, Nepcon West; Anaheim, CA, USA, 1997. Scheel, W.; Schu¨tt, J. Lo¨ten unter Stickstoff ja oder nein—ein Applikationsvergleich. Weichlo¨ten in Forschung und Praxis 1996; DVS-Ber. 182. Puschmann, U. Does Nitrogen Eliminate Cleaning? Proceedings of the Technical Program, Nepcon West; Anaheim, CA, 1993. Dong, C.C., et al. Oxygen Concentration in the Soldering Atmosphere—How Low Must We Go? Proceedings of Nepcon West, Anaheim, CA, USA, 1996. Keller, J. PTH solder plugs—necessary?. Assem. Eng. August 1983. Pillar, W.O. SMT Inspection Versus Performance, Proceedings of the Technical Conference, Nepcon West; Anaheim, CA, 1994. Lea, C. Evidence That Visual Inspection Criteria for Solder Joints Are No Indication of Reliability, Proceedings of the Technical Conference, Nepcon West; Anaheim, CA, 1995.
16 Pb-Free Component Conversion and Some Manufacturing Experiences Kathleen A. Stalter IBM Corporation, East Fishkill, New York, U.S.A.
Tom Baggio Panasonic Factory Automation, Elgin, Illinois, U.S.A.
Kenichiro Suetsugu Matsushita Electric Industrial Co., Ltd., Japan
I.
INTRODUCTION
Assembling Pb-free components is similar to standard Pb-bearing components with one major exception: there will be a transition period as the new technology is introduced. Thus, in addition to the new materials and processes, hybrid manufacture (manufacturing both leaded and nonleaded components on the same card) as well as multiple manufacturing lines to handle both leaded and lead-free production must be considered and managed. As is typically the case when introducing a new technology, the database is insufficient and the manufacturing processes have not been standardized, i.e., very little knowledge exists that a practitioner can utilize to bridge to a real production environment, with perhaps the exception of the automotive industry with its need for increased levels of stability that require a higher processing temperature capability as is the case with lead-free solders whose melting points are about 40jC higher than eutectic Sn–Pb. This chapter discusses some options to consider when converting products to Pb-free technology and describes the experiences of several component and hardware manufacturers who have successfully embarked on this journey.
A.
Use of Lead (Pb) in Electronic Devices
Lead has been used in varying amounts electronic assemblies since their inception. Lead is utilized in the body of some electronic components such as capacitors (lead titanate, lead zirconate), in their interconnections that provide both an electrical pathway and method of attachment to a component carrier, and as a protective finish on the printed circuit boards (PCBs) and component leads. It is also found in peripheral hardware such as batteries, monitors, cables, power supplies, motors, etc. In changing over to lead-free technology, there are several other important considerations aside from just the elimination of elemental lead (Pb) from components or an assembly. For example, one has to consider the mechanical implications of the alloy replacement
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system, process deltas, particularly the effect of higher temperatures on components and boards, and moisture sensitivity in causing ‘‘popcorning,’’ delamination, and other defective conditions.
II.
KEY CHALLENGES
A.
Alloy Selection
There are a significant number of alloys that have been chosen as viable candidates for lead-free assembly. It is questionable whether a single lead-free alloy will possess all of the attributes to satisfy a broad range of applications similar to the eutectic benchmark. Factors such as availability, toxicity, melting point, wetting, thermal, and electrical properties must all be considered. These factors are discussed in great detail in Chapters 8, 9, and 11. It is generally accepted that a separate alloy will likely be necessary to accommodate the reflow and wave soldering processes because the significant volume of material required for a wave soldering bath must be changed periodically due to contamination build-up. Alloys with costly elements such as silver would not be a good choice for a wave soldering operation. Clearly, these factors pose therefore additional challenges to assemblers who have OEM customers who may or may not have their own component suppliers, who in turn may use varying alloy finishes, etc. that can result in a partnumber, process variation, and inspection criteria nightmare for the assembler. Selection of an alloy affects many aspects of a product and its manufacturing processes. For example, it affects the integrity of the components, the board, the flux activity, and wetting characteristics to metallized terminations. 1. Lead (Pb) Contamination Common sense dictates that there will be a transition period in which both Pb-bearing and Pb-free components and solder materials may be utilized on the same PCB assembly. In fact, these so-called ‘‘hybrid’’ packages may be present for years to come, requiring special reflow and repair processes. Both forward compatible (leaded components assembled with lead-free processes) and backward compatible (lead-free components assembled with standard leadcontaining processes) will require separate solutions. This is a significant complication. The intermetallic compounds (IMCs) created with lead-free solder are not soluble and precipitate at the grain boundaries of lead containing phases. In addition, the Pb itself does not distribute uniformly throughout the joint but is concentrated or localized at the last point to cool. Pockets may form in the joints and the disturbed grain structure may result in dewetting. [1]. In a study performed at AIM Inc., a significant drop was noted in the cycles to failure with 0.5% and 1% Pb additions.
B.
Flux Selection
Flux selection is a critical variable in optimizing the wetting and mechanical properties of a solder joint, whether used to attach surface mount (SMT) components to a board or other type of carrier, or used as a vehicle in a paste. Flux disrupts and removes existing oxidation and prevents the oxidation of clean surfaces. It is critical that a flux activates at the appropriate temperature for sufficient time to achieve proper wetting. For lead-free solders, the flux must be capable of withstanding temperatures of approximately 250jC to 260jC, depending on the application. The flux itself, of course, must be environmentally friendly, must not significantly increase process costs, must be compatible with the component or board materials, and must not present cleaning challenges that may potentially decrease the reliability of the product.
C.
Board Material and Finish
The majority of organic PCBs utilized in the electronics industry are fabricated from layers of organic resin material that is strengthened with a glass cloth. Typical organic resins utilized are
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epoxies, polyimides, or cyanate esters, the most common being the FR-4 epoxy material with a glass transition temperature in the range of 115jC to 125jC. Printed circuit boards tend to soften and become rubbery above their glass transition temperature, greatly increasing the probability for warpage and delamination. Large boards or those that experience temperatures near the glass transition (Tg) are often supported during reflow to keep the boards flat to prevent warping and creating defects. Depending on the size of the PCB, and the mass and distribution of the components on the PCB, significant thermal gradients can occur which are exacerbated with the increase in soldering temperature required to reflow Pb-free solders. In addition to the concerns associated with the base material of PCBs, most boards have finishes to preserve the solderability (i.e., protect them from corrosion during storage and oxidation during processing) of the metal features to which the components are attached. Some boards have a metallic coating, most commonly a Sn–Pb coating formed by hot-air solder leveling (HASL), while others have an organic solderability preservative (OSP). Wettability varies from coating to coating and from supplier to supplier. The lead-free finishes must be capable of withstanding the increase in process temperature driven by Pb-free solders, while having equivalent shelf-life. Lead-free finishes and solders drive the use of an inert atmosphere to enhance wetting characteristics. Each finish must be evaluated to determine the number of thermal excursions it can successfully experience in the assembly process and still provide acceptable solder wetting. Compatibility qualification and reliability testing of each finish and lead-free solder combination will drive product cost and increase development cycle time. Similar information will be necessary if hybrid combinations are to be utilized in an assembly.
D.
Component Material and Finishes
Many component suppliers are advertising lead-free finishes on terminations. The compatibility of these finishes with both Pb-free and Pb-based solders must be considered as the transition is made to Pb-free processing. Even the body materials of some components such as capacitors have temperature-sensitive properties that may be altered by the higher lead-free processing temperatures. In addition to termination-material or compatibility issues, there are several other component material-related concerns, the most important of which is damage due to moisture uptake when processed at the higher Pb-free assembly temperatures. The most prominent defect is delamination due to warpage or popcorning, a phenomenon whereby the moisture absorbed by a component on the manufacturing floor is converted to steam when exposed to the solder reflowtemperature cycle. Many components are downgraded in moisture-sensitivity-level rating when used with lead-free process conditions.
E.
Synergistic Effect
In the selection of lead-free solder, it is important to also select compatible board materials, board coatings, temperature-resistant components, and flux to optimize both Pb-bearing and Pb-free solder joints. As noted, there will likely be an interim time period where both Pb-containing and Pb-free components will be populated on the same PCB, depending on the cost and availability of Pb-free components.
F.
Process Equipment
The most significant process-equipment-related aspect when transitioning from a Pb-bearing to a Pb-free alloy is an increase in melting temperature of approximately 40jC. 1. Placement Many lead-free alloys under consideration display slower wetting and possess a lower surface tension compared to their leaded counterparts. Thus a more accurate placement capability and process monitoring are required. Less self-centering will occur during the reflow operation.
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2. Reflow Ovens/Furnaces The impact of a higher melting temperature on reflow ovens ranges from very minor to major depending on the age and type of oven utilized. In some cases, ovens must be reconfigured to handle higher zone temperatures. Heating systems that utilize IR as a heat source may not be capable of achieving the tighter process control necessary, achievable with modern convection ovens. Profiles must be developed to minimize thermal gradients between components of varying size and mass. The gradients tend to be exacerbated by the increase in peak temperature required to establish an adequate solder joint. More considerations must be given when mapping components to a board. Smaller components must be placed in locations that avoid the creation of hotspots. Also, component density/spacing must be evaluated in relation to peak temperature and dwell time above the liquidus temperature. Tighter controls will be required to achieve and maintain a process window that minimizes the peak temperature exposure that boards and components experience. Real-time continuous thermal monitoring with feedback control may be required for some applications. 3. Test/Inspection Standards will require revision to accommodate the potential for a variety of leaded and lead-free solder alloys. Acceptable test measurements including inspection criteria must be established including shear and tensile testing, wetting angle measurements, visual criteria defining the acceptable surface appearance of the solidified alloy and retraining will be required. 4. Board Rework and Repair The effect of mixing leaded components with lead-free component options complicates board rework and repair. The issue is not just a tactical one of finished good quality, but a long-term reliability concern. Operator training and board mapping are just a few of the requirements.
G.
Other Factors
There are several factors related to business operations that must be considered when contemplating the conversion to lead-free components and processing. A separation of parts with the same leaded and lead-free configuration must be maintained, bills of materials (BOMs) must be managed, and components and materials distinguished, with each customer and supplier working to a different transition schedule. 1. Inventory Management In addition to qualifying and testing a new set of materials, each supplier and assembly provider will be required to manage and forecast several BOMs for each product and insure that issues of mixing are addressed and well controlled. New marking schemes will be required and labeling and packaging must be readily distinguishable by both the supplier and user. In some cases the inventory management will necessitate separate part numbers (PNs), thus increasing the logistics workload and thus cost. In other cases where suppliers use a change in date code for the change over of a PN to lead free, very strict controls during assembly will be required to avoid confusion between leaded and lead-free versions of the same PN. 2. Supply Chain Readiness and Standardization The ability of the supply chain to manage multiple PNs, BOMs for leaded, lead-free, and mixed configurations must be addressed. Given the fact that there is no standard alloy that will be utilized to replace eutectic Sn–Pb solder, and that the many OEMs and contract manufacturers are working to different schedules, this is a daunting task. It will be necessary to implement quality standards considering the nuances of each alloy. Standards must also be established to classify the specifications and limitations of each component as well as the components’ forward and backward compatibility.
Pb-FREE COMPONENT CONVERSION
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3. Cost Several inherent aspects of lead-free technology give rise to increased costs. Consider, for example, higher peak temperatures that require more energy consumption, thus increasing the production cost. Multiple lines and inventory management require additional resources and capital costs. New materials and requalifications increase the development cost of the product cycle. Inert atmospheres will be necessary for some applications owing to the reduced wetting characteristics of lead-free alloys compared to eutectic Sn–Pb solder resulting in equipment upgrade costs and processing costs. However, some of the more subtle aspects that increase cost must not be overlooked. Higher peak temperatures typically require slower belt speeds that result in increased process times that in turn result in a decreased throughput. Higher temperatures may increase maintenance costs and an increase in forced cooling to meet exit temperature requirements. The use of inert atmospheres requires additional safety requirements both from a tooling perspective as well as procedural. Lead-free conversion schedules may have to be accelerated on the basis of ‘‘green marketing’’ requirements as opposed to those dictated by legislative requirements. Consumers, especially those in certain geographies, are known to consider the environmental aspects of a product when making buying decisions, especially if the quality and performance are compatible. It may be difficult to pass additional costs to the consumers if not the industry practice.
III.
PRACTICAL EXAMPLES OF LEAD-FREE SOLDERING TECHNOLOGY IN MASS PRODUCTION AT PANASONIC (AN IN-DEPTH CASE STUDY)
A.
Introduction
In September of 1998, Panasonic converted the MJ30 portable MiniDisk Player to lead-free soldering [2] (Fig. 1). This was the first electronic product of significant production volumes (>40k/month) to be completely manufactured with lead-free solders. Since then, Panasonic’s conversion to lead-free solders has been rapid (Fig. 2). As of early 2003, over 188 different products have been converted to lead-free solders [3] and by the end of 2003, all the major product groups are anticipated to be lead free worldwide. This section will discuss many of the details and issues involved with converting from conventional soldering to a lead-free-based system. 1. Status of Lead-Free Products Some highlights of Panasonic’s introduction of lead-free solders are given in Table 1. Arriving at this point required the solution to many technological challenges. A detailed understanding of the materials involved, processes, manufacturing implications, and defining adequate product standards were key to the successful implementation of a lead-free program.
B.
Alloy Selection
1. Overview The first step is selecting an appropriate lead-free material. The luxury the electronics industry has had with the ubiquity of eutectic Sn–Pb is not available with lead-free soldering. In the future, lead-free soldering may evolve to one or just a few alloys that will satisfy the common solderingprocess technologies, i.e., wave, reflow, and repair, but, with today’s lead-free alloy choices, a ‘‘one-size-fits-all’’ is not generally available. Therefore Panasonic utilized several lead-free alloys depending on the circumstances. In general, Matsushita/Panasonic has chosen the following solder materials:
For reflow soldering, the predominant alloys used are tin–silver–bismuth–indium (Sn–Ag–Bi–In) and tin–silver–copper (Sn–Ag–Cu). For wave soldering applications, Sn–Ag–Cu and Sn–Cu+Ni. For repair, Sn–Ag–Cu and Sn–Ag wire.
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FIG. 1 Several Panasonic Portable MiniDisk player units that utilized lead-free solder technology. (From Ref. 13.)
Several product groups have worked with the tin–zinc–bismuth (Sn–Zn–Bi) alloys for reflow, but with difficulty as discussed later in this chapter. With a wide range of alloys to choose from, the task of selecting the best alloy was difficult. From Table 2, it is apparent that a single lead-free alloy does not exhibit the best performance in all the categories listed. As an example, among the alloys considered, Sn–8Bi–3Zn has a melting point closest to eutectic Sn–Pb; however, it exhibits poor wettability. Therefore alloy selection is, as often occurs in design issues, a matter of optimizing benefits through tradeoffs. Physical characteristics such as panel size, types of mounted components, electrode finishes, temperature sensitivity of components, and so on all play a role in alloy selection.
FIG. 2 By the end of 2001, Matsushita Electric Industrial (MEI) Company had successfully introduced 151 products utilizing lead-free solder. (From Ref. 14.)
Pb-FREE COMPONENT CONVERSION TABLE 1
597
Status of Lead-Free Products
Date 1998 1999 March 2001 December 2002
Milestone MJ30 MiniDisk (MD) introduced with lead-free solder paste VTR introduced using Sn–0.7Cu wave soldering Five different cell phone models with Sn–Ag–Cu solder paste for a total of over 3 million units produced [3]. Over 8 million VTRs produced Over 180 product categories and 86% of all new semiconductors now using lead-free technology [3]. Approximately 6 million products of various MD players manufactured with lead-free paste
Source: From Ref. 4.
2. Existing Equipment Influence Often, the manufacturing capabilities themselves have a major influence in the process of alloy selection. The conversion of the MD player to a lead-free process focused around two important elements. First, choose a lead-free alloy that could be processed utiliz-ing the existing factory’s assembly equipment. Second, the alloy must meet the MD electrical and mechanical requirements. a. Lack of Close Control for High-Melt Alloy. To meet the first objective, an alloy with a melting point close to eutectic Sn–Pb was desired. At the time of the conversion, the age of the equipment at the MD factory was typically 1 to 6 years. The reflow equipment (Fig. 3) was not obsolete but a concern, as it lacked the latest control capability and was limited in the number of zones available. The existing reflow-oven technology used at the factory was a three-zone convection system. Without an extensive number of zones available in later models, it would have been difficult to introduce an alloy with a considerably higher melting point. Fig. 4 illustrates how the process window is reduced with lead-free solders compared to eutectic Sn–Pb solder. It was felt that solders such as the Sn–Ag–Cu (SAC) alloy, with a melting point of 217jC, would reduce the available process window beyond the oven’s ability to manage or control the soldering process effectively. Therefore the bismuth–indium (Bi–In) system was judged the best choice to replace eutectic Sn–Pb without having to replace the reflow ovens. Altering the existing manufacturing infrastructure would have resulted in a very significant cost impact. b. Lower Melting Point with Bismuth (Bi). Testing was initiated on the Sn–Ag–Bi system to determine the practical limit of the bismuth content. As the bismuth content is increased, the melting point of the solder alloy is lowered; however, the pull strength is also TABLE 2 A Comparison of the Key Characteristics of Three Lead-Free Solder Candidates Considered for Reflow Soldering Applications at Matsushita Attributes Melting point (jC) Wetting Impact resistance Overall result
Sn–3Ag–2.5Bi–2.5In
Sn–3Ag–0.5Cu
Sn–8Bi–3Zn
210 O 85% O 850G D 0 O
218 D 85% O 1100G O O
197 0 O 80% D 800G D D
0 = Excellent, O = acceptable, and D = marginal. O Courtesy of Panasonic.
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FIG. 3 The MD factory in Fukushima, Japan, as it appeared in September of 1998. (From Ref. 13.)
lowered below an acceptable level (Figs. 5 and 6). A test vehicle was developed (Fig. 7) to evaluate the soldering process and the alloy itself. The maximum temperature during the reflow process used for this test vehicle was controlled to 230jC. Thermal cycling studies were carried out at a temperature range of 40jC to +85jC for 30min cycles. Evaluations were performed with pull strength for leaded components and shear strength for chip components. Measurements were performed at time zero and 50 cycle increments up to 500 thermal cycles (Fig. 8). OPTIMUM Bi CONTENT. The 3%-bismuth alloy was determined to have a pull strength equivalent to eutectic Sn–Pb solders (Fig. 8); as were with chip components, fracturing at approximately the same load and exhibiting the same failure mode as eutectic Sn–Pb. However, as the bismuth content is increased, the pull strength is less than eutectic Sn–Pb [5]. Bismuth was observed to precipitate from the solder matrix if the bismuth content exceeds 3%. SEM micrographs (Fig. 6) of the area around the solder/land interface after pull testing measurements were performed (after 500 thermal cycles), showing that elemental bismuth deposits were the reason for the significant reduction in the mechanical strength observed. However, the precipitated bismuth condition decreased as the bismuth concentration was lowered. At bismuth concentrations of 3%, or lower, an IMC of Cu–Sn was present at the land/solder interface, but very little or no elemental bismuth was found to have precipitated from the matrix. The upper Bi concentration was therefore identified as 3%.
FIG. 4 The effect of lead-free solders on the soldering process window. As the melting point increases, the allowable temperature range is dramatically reduced. (Courtesy of Panasonic.)
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FIG. 5 Adding bismuth lowers the melting point but reduces the bonding strength. However, an addition of both indium and bismuth results in lowering the melting point and maintains the bond strength. (From Ref 15.)
INDIUM ADDITION TO LOWER THE MELT TEMPERATURE. The melting point of the 3% bismuth solder was greater than the target of 210jC. Therefore indium was added (Fig. 5) to reduce the melting point while maintaining the desired mechanical strength of the alloy. Testing was continued with the Sn–3.5Ag–2.5Bi–2.5In alloy. After 500 thermal cycles, no significant changes in bonding strength were observed in any components tested. The four different components and electrode finishes tested are noted in Fig. 9. Note that the eutectic Sn–Pb solder with the 0.65-mm-pitch quad flat-pack (QFP) and palladium (Pd)-coated electrode exhibited a significant decrease in pull strength as a result of exposure to thermal cycling, while the 3%bismuth solder alloy did not. Furthermore, no structural changes or cracking was observed with the In-doped Sn–Ag–Bi solder after thermal-cycle testing was complete. Fig. 10 and Table 3 show that the Sn–Ag–Bi–In alloy either outperforms or is equivalent to the benchmark eutectic Sn–Pb solder based on crack length and IMC thickness for several components and component lead finishes. From the mechanical, thermal cycle, and high-temperature storage testing conducted, it was determined that the Sn–Ag–Bi–In alloy was adequate and comparable to eutectic Sn–Pb.
FIG. 6 Scanning electron microscope (SEM) micrographs of Sn–Ag solders with a) 3% Bi and b) 10% Bi at the solder/PCB land interface. As the bismuth content is increased, bismuth separates from the solder matrix resulting in a significantly lower pull strength. (From Ref 16.)
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FIG. 7 The initial test vehicle used for the evaluation of solders in surface mount applications. It is FR-4, 1191620.8 mm. It contains a wide array of component types such as QFPs, at pitches 0.5 and 0.65 mm, 1005, 1608, and 2125 R/C, mini TR/SOT, SOPs, SOJs, crystal/oscillators, Al Caps, connectors, and so on. Electrode finishes used were Sn, Sn–Bi, Pd, Sn–Pb, Au, and Ag. (From Ref 15.)
C.
Flux System Developments
The next critical component for this material was the development of the flux and activator system for the paste. This proved to be a key factor in the success of this project. As the wettability of lead-free alloys is lower than eutectic Sn–Pb, a suitable flux system was critical to the successful introduction of the MD’s conversion to lead-free. In addition to the flux system having the properties to promote wetting, the requirements for screen printing, stencil life, tackiness, and so on were also important when evaluating a solder paste system. Flux technology is discussed in
FIG. 8 Thermal cycle test (40 to 85jC for 30 min) of a 0.5-mm pitch QFP (48 I/O, Sn–Pb finish). At bismuth concentrations of less than 3% the pull strength of the lead-free alloy is at parity with eutectic Sn–Pb solders. (From Ref 15.)
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FIG. 9 Thermal cycle testing (40jC to 85jC, 30-min cycle) with various components and electrode finishes. Comparison of the lead-free alloy Sn–3.5Ag–2.5Bi–2.5In with the benchmark eutectic Sn–Pb solder. (From Ref 17.)
FIG. 10 Photomicrographs of a vertical cross section through a solder joint of a QFP lead after stress testing. The measurement of crack length and the intermetallic compound (IMC) thickness are used to determine rankings in Table 3. (a) QFP lead after thermal aging showing crack in solder joint. (b) Is the land-to-solder interface showing the thickness of the IMC of the solder joint. (Courtesy of Panasonic.)
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TABLE 3 Thermal Cycling and Life Testing Summary. The Lead-Free Alloy’s Performance Often Outperforms or at Least Was at Parity with Eutectic Sn–Pb, the Benchmark QFP Conditions
Solder alloy
Pd
High temperature storage testing (3000 hr) 85jC Sn–Pb B Sn–Ag–Bi–In A 125jC Sn–Pb B Sn–Ag–Bi–In B 150jC Sn–Pb C Sn–Ag–Bi–In B Thermal cycle testing (3000 cycles) 40f80jC Sn–Pb B Sn–Ag–Bi–In B 40f125jC Sn–Pb C Sn–Ag–Bi–In B 40f150jC Sn–Pb B Sn–Ag–Bi–In B
1608C
1608R
Sn–Bi
Sn–Pb
Sn
Sn–Pb
Sn
Sn–Pb
B A B B C C
B A B B C C
B A B A C B
A A B B C C
B A B B C B
C A B B C C
B A C C C C
B A B B C B
B A C C C C
B A C C C B
B B C B C B
C B C B C C
Ranking legend: A = IMC<3 Am, crack<10 Am. B = 3 AmVIMCV10 Am, 10 Am V crack V100 Am. C = IMC>10 Am, crack>100 Am.
detail in Chapter 11. Figs. 11 and 12 show the variation in paste printing and bridging characteristics, respectively, due to differences in flux formulations (Table 4). Flux type 401 shows poor release, but outperforms the others in terms of bridging, but requires the property tradeoffs discussed earlier. 1. Require Increased Flux Activity Fig. 13 shows that reducing tin oxides is more difficult than lead oxides. Because lead-free solders typically contain more than 90% Sn, having sufficient flux activity is an important consideration. In consideration of the fact that lead-free solders do not wet as fast nor as completely as eutectic Sn–Pb solder, it was clear the activity of the flux system must be increased. Slowing down the oven
FIG. 11 Flux evaluation testing of printing transfer rate. Testing conditions were 0.14-mm-thick stencil (ss), aperture for 0.8-mm pitch QFP. See Table 4 for flux compositions. (Courtesy of Panasonic.)
Pb-FREE COMPONENT CONVERSION
FIG. 12
603
Bridging evaluations of several fluxes. Same testing conditions and materials as in Figure 10.
was not an option because this would have resulted in a significantly reduced throughput. As the management mandate for this projects was to utilize the existing assembly equipment with the new lead-free system, the alternatives that were available are listed in Table 5. a. Increased Activator Content. Increasing the activator content is a well-known method of effectively improving the wettability of solders. However, typically the residues that remain behind in a highly activated flux system are usually corrosive and sometimes electrically conductive. Therefore these residues typically cannot remain on a PCB assembly, because of corrosion-related reliability concerns. A cleaning process must be used to remove the residues. However, as the melting point of lead-free alloys is typically higher than eutectic Sn–Pb, the residues are ‘‘baked-on’’ and difficult to remove. b. Self-Neutralizing System. As stated earlier in this chapter and summarized in Table 5, the options were limited for conversion to lead-free solder for the MJ30 MiniDisk Player. The use of available reflow equipment in a no-clean process ruled out the use of an inert atmosphere or a highly active flux. Production demands ruled out slowing the oven conveyor speed. The only viable solution was to develop a flux system that was compatible with manufacturing as it was being practiced, i.e. the same reflow furnaces, standard atmospheres, and a no-clean system. A joint effort between Harima Chemicals and Panasonic resulted in a deactivating flux system that is self-neutralizing after reflow. This satisfies the condition for a no-clean SMT process. Fig. 14 shows that during the preheat and reflow stages of the profile, the flux behaves like a rosinactivated (RA) flux system. However, during cooling, deactivation occurs, which causes the activator to become neutralized to the extent the activity level is reduced to an RMA flux level, which does not require removal (i.e., no-clean process). During reflow, the activator breaks down, forming a halogenated acid. This compound reacts with the oxides of the solder (mainly Sn), to
TABLE 4 The Composition of Several Fluxes Evaluated for Use in the Assembly of the MiniDisk Player (Model MJ30). All Formulations Contained the Same Amount of Activator Material Abietic acid (wt.%) Rosin (wt.%) Solvent (wt.%) Stearic acid (wt.%) Remaining (modifiers) Courtesy of Panasonic.
S0401
S0402
S0403
S0404
16.51 32.8 4 10 balance
18.01 34.8 4 7 balance
20.01 36.3 4 3 balance
21.51 37.8 4 0 Balance
604
STALTER ET AL.
FIG. 13 Reduction of lead (Pb) and tin (Sn) oxides with exposure to rosin at 150jC for 5 min. The Pb oxide reacts much more readily than the Sn oxide. (Courtesy of Harima Chemicals, Inc.)
provide a clean surface for solder wetting. Once the reflow process is complete, and the solder is now cooling to solidification, any remaining activator must be neutralized. This is accomplished by combining the ionically bonded acid with a deactivator to form a covalent bond (C–Cl) compound. Figs. 15 and 16 show that the deactivating flux system developed is effective at the preheat and reflow portions of the profile, but is inactive at post reflow behaving like a typical RMA flux system. Table 6 shows the results of activator concentration and electrical insulation resistance before and after reflow. The flux system has the benefits of an active flux at reflow (0.29% activator), and an RMA flux post reflow with a high insulation resistance (100k V) and low activity (0.05%). With the lower melting point bismuth–indium alloy, and the development of the self-neutralizing flux system, it was then possible to continue utilizing the same reflow furnaces that has been previously utilized to assemble products with eutectic Sn–Pb solder (Fig. 17). In general, other aspects of the assembly operation also required little or no change with the introduction of the lead-free solder. Among these were the stencil printing, assembly/mounting, solder paste handling, and preparation operations. Slight modifications were made to the component layout on the PCB to better distribute the thermal mass, but these changes were minor. The lack of the shiny and bright appearance characteristic of the eutectic Sn–Pb solder joints after reflow resulted in some minor tweaking of the automatic optical inspection (AOI) systems to compensate for the slightly duller appearance, characteristic of lead-free solders.
D.
High-Density Compatibility
The MJ30 and subsequent MiniDisk player models shown in Fig. 1 did not consist of assemblies where any of the mounted components were ultrasmall. However, cell-phone products do consist of chip packages with metric 0603 (English 0201)-type components. It was determined that even with these component types, a very tight spacing could be achieved with lead-free alloys.
TABLE 5 Available Alternatives Considered for Introducing a Lead-Free Solder for the MiniDisk Player (MJ30) Option Use nitrogen environment for reflow soldering Use a highly activated flux system Slow reflow oven line speed Develop flux system to accommodate existing oven technology without sacrificing quality or throughput Courtesy of Panasonic.
Issues Current equipment not capable of nitrogen reflow Would require post-reflow cleaning, currently not available in MD factory Reduction in throughput—not acceptable Preferred solution—but requires flux development
Pb-FREE COMPONENT CONVERSION
605
FIG. 14 During preheat and reflow portions of the profile, the flux system has the activity level of a rosin/resin activated (RA) system. However, once the material starts to solidify and cool, the flux system changes or is neutralized (deactivated) into a rosin mildly activated (RMA) flux system. (Courtesy of Harima Chemicals, Inc.)
As products, particularly consumer hand-held products, such as cell-phones and palmcorders, are constantly migrating to smaller and smaller sizes, the use of smaller components (e.g., 0603) comes into the mix. The issue Panasonic faced was whether lead-free solders could be utilized in tight spacing or high-density applications as in the case in products such as the MiniDisk Player. It was determined that that they could. The following section will discuss the use of Sn–Ag–Cu as a soldering alloy that effectively achieves the rigors of high-density mounting with 0603 components. Fig. 18 shows that the Sn–Ag–Cu alloy’s ability to transfer from the stencil to the PCB’s land area is not as good as eutectic Sn–Pb. Stencil thickness and the area of the aperture opening must be kept to an area aspect ratio of two or less to allow for effective printing transfer with Sn–Ag–Cu solder pastes. As the component spacing becomes narrower, the land and subsequently stencil apertures become smaller, thus increasing the aspect ratio and increasing the difficulty to transfer paste effectively. Fig. 19 shows a set of land and stencil design patterns utilized for evaluation. With 0603 chip mounting and assembly, it is apparent that solder paste printing for small chip components approaches the complexity of printing required for chip-scale packages (CSPs). With stencil openings of 0.3 mm in diameter, the ability to transfer paste from the stencil is more difficult compared to larger chips, if a 1005/0402 chip can be
FIG. 15 Looking at the ability to remove or reduce tin oxides, the ‘‘deactivating’’ system has levels equal to RA systems at ramp-up, preheat/soak, and reflow. Post reflow, the flux system is neutralized to the same levels of activity as an RMA or no-clean flux systems, making this flux an ideal system for lead-free soldering. (Courtesy of Harima Chemicals, Inc.)
606
STALTER ET AL.
FIG. 16 Migration (SIR) testing results of deactivating flux system, showing residues are nonconductive and are suited for a no-clean process. (Courtesy of Harima Chemicals, Inc.)
considered large. Therefore stencil design is an essential factor in high-density 0603 mounting. In addition to having an impact on paste transfer in stencil printing, other attributes such as selfalignment, bridging, and mechanical strength are affected as well. 1. Component Spacing Limits The practical limit of component spacing was determined to be 0.1 mm based on bridging defects (Fig. 20). Comparing the results in Fig. 20, bridges were monitored for 0603 chip mounting with both eutectic Sn–Pb and Sn–Ag–Cu solder pastes. Both solders were observed to achieve the state-of-the-art spacing of 0.1 mm without exhibiting bridging as determined by post-reflow inspections. In addition to printing and bridge comparisons, self-alignment and mechanical strength were also investigated. 2. Self-Alignment As the amount of solder for 0603 chip components is very small, self-alignment and joint strength have a narrow process window. If the amount of solder could be increased, certainly the amount of self-alignment due to the surface tension of the molten solder would be improved. However, an increased solder volume would be a detriment by creating more bridging defects. But as the solder volume decreases, the mechanical joint strength also decreases. While this is true for both solders, Sn–Ag–Cu is affected less than eutectic Sn–Pb with regard to both of these factors. The testing for self-alignment involved purposely mounting a product with a known shift or misregistration in both the x and y directions, then, remeasuring the position post reflow. It was determined that Sn–Ag–Cu alloys outperformed eutectic Sn–Pb with the exception of shifts in the y direction for 0603 resistors (Figs. 21 and 22). Even in that case, the amount of misalignment post reflow was
TABLE 6 Activator Concentrations and Electrical Insulation Resistance Levels of Flux Prior to and after Reflow Property Activator concentration (halogen content) Electrical insulation (resistance) Courtesy Harima Chemicals, Inc.
When
RMA
Deactivation paste
Before reflow After reflow Before reflow After reflow
0.09% 0.05% 100,000 V 100,000 V
0.29% 0.05% 30,000 V 100,000 V
Pb-FREE COMPONENT CONVERSION
607
FIG. 17 Reflow profile of the MJ30 MiniDisk Player. When the MJ30 was converted to lead-free soldering, the profile was identical to that used for eutectic Sn–Pb solder. (From Ref. 18, 2000.)
comparable to eutectic Sn–Pb for misalignments greater than 100 Am. Therefore the process window for self-alignment of components with Sn–Ag–Cu is equivalent to or greater than eutectic Sn–Pb for the same amount of solder printed. As a practical matter, shifts greater than 40–50 Am are avoided with adjacent spacings of 0.1 mm between chips. If chips are mounted with a shift of <50 Am, the likelihood that adjacent components will interfere with each other is high. Therefore with state-of-the-art spacing designs of 0.1 mm, mounting shifts are rarely >40 Am. 3. Mechanical Strength The land pattern and stencil aperture designs were compared using the metric of mechanical strength. The Sn–Ag–Cu solder alloy has been found to yield a higher mechanical strength than that of eutectic Sn–Pb for the same land and stencil design (Figs. 23 and 24). No cracks or changes to the solder joints of 0603 capacitors were observed for either the fillet or the filletless land pattern designs after 1000 thermal cycles (40 to 85jC, 30-min cycle) (Fig. 25). The details of the land and stencil design patterns for fillet (L2-square) and filletless (L3-sqaure) are given in Fig. 19.
FIG. 18 0603/0201 printing testing with Sn–Ag–Cu solder paste. Maximum aspect ratio (or area aspect ratio), as defined above, of 2 is required for proper paste transfer (>50%). Comparing to eutectic Sn–Pb paste, the lead-free alloy shows a slight drop in paste transfer rate. (Courtesy of Panasonic.)
608
STALTER ET AL.
FIG. 19 Land and stencil design patterns used for 0603 chip bridging and mechanical joint strength testing. (Courtesy of Panasonic.)
4. Summary High-density circuit manufacturing was not only demonstrated possible, but shown to have some benefits over conventional eutectic Sn–Pb soldering. To summarize, lead-free soldering with 0603 chips has an improved solder-joint strength, improved self-alignment property, and improved bridging rate (reduced) allowing for tight spacing down to 0.1-mm gaps between components. There is a slight decrease in print transfer with Sn–Ag–Cu compared to eutectic Sn–Pb. As the surface tension of Sn–Ag–Cu is higher than that of eutectic Sn–Pb, the propensity for tombstoning is increased. However, tombstoning can be eliminated by utilizing a filletless land design, and if the misregistration due to both printing and mounting is kept to less than 50 Am.
E.
Larger and More Complex Assemblies
When discussing products such as cell phones and MiniDisk players, the common characterization of these products is that they typically are small and very compact, with a dense placement
FIG. 20 Tight spacing can be achieved with Sn–Ag–Cu. For both eutectic Sn–Pb and Sn–Ag–Cu, 0.1mm spacing is the practical limit for tight spacing of 0603/0201 components based on bridging defects. (Courtesy of Panasonic.)
Pb-FREE COMPONENT CONVERSION
609
FIG. 21 Comparison of Sn–Ag–Cu with eutectic Sn–Pb for the self-alignment of 0603/0201 chip resistors for shifts in the a) x direction and b) y direction. Self-alignment is comparable to Sn–Pb for shifts in the x direction better than for shifts in the y direction. (Courtesy of Panasonic.)
of components. This allows for a uniform arrangement of thermal mass with an achievable maximum temperature gradient of less than 10jC, typically less than 5jC. However, with large, industrial products, this is usually not the case because the PCB thickness is greater, and the thermal mass of the component mix can have a wide range so soldering these products can prove much more difficult. This situation can be further complicated by the fact that the product may include both reflow and wave soldering. 1. Additions to Reduce Melt Temperature An example of a large and complicated PCB assembly is a 861 FA controller card (Fig. 26) that utilizes both reflow and wave soldering for component attachment. The reflow alloy chosen for this product contains 6% indium but maintains the bismuth content at 3%. The increased indium content helps reduce the melting point of the alloy to 206jC. Significant temperature gradients were anticipated during reflow because of the products’ size and complexity. The approach taken to appropriately reduce the thermal gradients was to make improvements to the soldering equipment.
610
STALTER ET AL.
FIG. 22 Comparison of Sn–Ag–Cu with eutectic Sn–Pb for the self-alignment of 0603/0201 capacitors with Sn–Ag–Cu and eutectic Sn–Pb solders. Unlike the resistors, self-aligning properties of the lead-free alloy outperform eutectic in both the x and y directions. (Courtesy of Panasonic.)
2. Land Design Changes As seen in Fig. 27, minor changes were made to the land design to improve the mechanical strength of the QFP solder joints. 3. Reflow Oven Enhancements However, the majority of the effort was focused on improvements to the reflow oven and wave soldering equipment, made in phases. a. Dual Heating System. The first phase was to employ a dual-heating system consisting of both convection and IR heating elements as shown in Fig. 28. The use of an IR-heating source allows devices such as aluminum electrolytic capacitors to reflect the energy from the IR source, thus preventing these components from overheating. In the convection mode, the temperature difference (DT) across the FA controller assembly was in excess of 40jC during reflow. The peak
Pb-FREE COMPONENT CONVERSION
611
FIG. 23 Shear strength testing of 0603/0201 capacitors for various land designs and stencil thickness of a) 0.1 mm and b) 0.12 mm. In general, the Sn–Ag–Cu alloy outperformed the eutectic Sn–Pb alloy. (Courtesy of Panasonic.)
temperature was 253jC and exhibited a DT of 60jC in the preheat stage (Fig. 29). With the IR source enabled, the DT was improved to one-half the convection-only value. In addition, when using IR, the peak temperature of the profile could be reduced to 236jC. These enhancements, however, were not sufficient. Further enhancements were necessary to improve the efficiency of the reflow oven and further reduce the DT. b. Convection Modified Nozzle System. As the IR system could not eliminate the large temperature gradients observed in the preheat sections, this concept was abandoned. To improve the efficiency of the oven’s heat transfer rate, the RSF oven was developed (Fig. 30), which only used convection heating but had a completely redesigned nozzle system, as shown in Fig. 31. This nozzle design improves the efficiency at which hot air is delivered to the surface of a PCB. This allowed the DT across the PCB to be maintained at approximately 5jC for even large boards, such as controller board products. The overall oven temperature was reduced by 50jC due to the nozzle efficiency enhancements, as illustrated in Fig. 32. In addition, Fig. 33 demonstrates that the improved technology of the RSF oven reduced the DT further than the REF-G3 (convection+IR concept). The RSF technology resulted in a reduction in preheat gradient of one-half the G3s condition. Fig. 33 shows the progression from the G3 to the RSF-6 (six-zone) oven. This oven technology allowed lead-free assembly of a wide range of products—everything from small cards for consumer products to mother cards and boards for large, industrial-type products. c. Compact Preheat Section. Fig. 34 shows the implementation of a compact preheat section to a reflow oven that allows difficult-to-reflow products to be introduced without
612
STALTER ET AL.
FIG. 24 Shear strength testing of 0603/0201 resistors evaluating various land design patterns and stencil thickness of a) 0.1 mm and b) 0.12 mm. In general, the Sn–Ag–Cu alloy outperformed the eutectic Sn–Pb alloy. (Courtesy of Panasonic.)
requiring replacement of the reflow oven itself. With this type of in-line preheater, the reflow temperature, peak temperature, and DT can be significantly reduced as seen in Fig. 35. This compact method allows lead-free soldering to be accomplished with older oven technologies.
F.
Wave Soldering
There are several important aspects to successful lead-free wave soldering. These involve understanding how lead-free solders interact with various material finishes, how the machine design impacts the soldering process, how impurities affect soldering quality, and how to control these impurities, to cite a few. A significant amount of study was dedicated to wave soldering with lead-free solders at Panasonic to achieve a manufacturing capability. Some of the major or essential points and results of this work are discussed in this section. 1. Initial Evaluation Study Fig. 36 shows the evaluation board used to study the lead-free wave soldering process, and Table 7 lists the components and their finishes addressed in these studies. A comparative defect summary for several proposed lead-free solders was prepared (Table 8) as a result of the evaluation conducted, as were joint strength measurements (Table 9). Several observations were made based on the studies that are listed in Table 10.
Pb-FREE COMPONENT CONVERSION
613
FIG. 25 Cross sections of 0603 capacitors with fillet and filletless land pattern designs subjected to thermal cycle testing (40jC to 85jC, 30-min cycle). No cracks were noted for either stencil size: fillet L2 (square) and filletless L3 (filled square). (Courtesy of Panasonic.)
a. Joint Strength. With lead-free wave soldering, there is a dependency between the component lead finish and lead-free solder alloy. Figs. 37 and 38 show that a QFP with Sn–Ag– Bi–Cu alloy as having the lowest pull strength, but with jumper wires, Sn–Ag–Bi–Cu alloy has the highest strength. This condition changes over time as the impurity levels increase in the solder bath, so contamination concentration must also be monitored closely. The ability of an alloy to accommodate the presence of impurities to increase the useful life of the bath plays a significant role in alloy selection. Pragmatically, an alloy whose bath life is very short due to an unacceptable impurity level must be eliminated from consideration for use in a high-volume manufacturing environment. Therefore lead-free solder alloys that cannot effectively accommodate contaminants are very impractical for volume production, unless impurity monitoring and control techniques are used to keep impurities to an acceptable level. Impurity monitoring and control are discussed later in this section.
FIG. 26 861 FA controller card, top and bottom side. (From Ref. 19.)
614
STALTER ET AL.
FIG. 27 Land-design improvements made for the FA controller card. To eliminate the crack as noted in the photomicrographs of the cross-sectioned solder joints and improve the mechanical strength, the land length for a QFP component (0.5-mm pitch, 208 I/O) was increased from 2.1 to 3.3 mm. (Courtesy of Panasonic.)
b. Solder Wetting. Achieving adequate wetting of lead-free alloys during wave soldering can be a difficult hurdle to overcome. It is well documented that lead-free alloys do not wet the variety of electrode plating finishes common to microelectronic components as well as eutectic Sn–Pb as shown in Figs. 39 and 40. This is also demonstrated graphically in Fig. 41; a plot of wetting balance tests. In this test, a coupon is held and inserted into a bath of molten solder. The time it takes for the solder to impart a tensile force (or start to wet) on the coupon is referred to as the ‘‘zero force time.’’ As can be seen, the lead-free alloys exhibit a significantly longer wetting time compared to eutectic Sn–Pb. Because of the higher melting points of lead-free alloys, the zero force times show a sharp decrease as the temperature of the solder bath is increased. The eutectic Sn–Pb solder is noted to behave with a flatter curve, partly because of the test temperature range.
FIG. 28 a) REF-G3 model oven used for FA controller card introduction to lead-free solder. b) This oven concept employed a combination of infrared (IR) and convection heating sources. (From Ref. 20.)
Pb-FREE COMPONENT CONVERSION
615
FIG. 29 Comparison of the thermal profile of the FA controller card utilizing convection only a) heating with b) convection+IR. The temperature gradient across the PCB was reduced approximately one-half of the original 40jC. However, a large temperature gradient remained at the preheat section of approximately 30jC. (From Refs. 21 and 22.)
At 240jC, eutectic Sn–Pb is already approximately 40jC above its melting point (m.p.), while Sn– Ag–Cu is only superheated (i.e., temperature above the m.p.), 20jC. Similarly, as the temperature above melting point approaches 40jC, the curve for lead-free alloys also starts to level off. However, operating a wave bath at temperatures greater than 250jC is not practical, so the zero force time is a tradeoff based on a 250jC maximum operating temperature. Figs. 42 and 43 further illustrate this temperature vs. the zero wetting time. As the temperature is increased from 245 to 270jC at a constant conveyor speed in the furnace, the solder coverage is noted to increase considerably. At a constant temperature of 250jC, the solder coverage also increases with a reduction in conveyor speed from 1.0 to 0.75 m/min.
FIG. 30 Conceptual drawing of the RSF-4, four-zone convection reflow oven. The nozzle manifold and scirroco fans improve heat transfer efficiency and reduce the temperature gradients across the PCBs during soldering. (Courtesy of Panasonic.)
616
STALTER ET AL.
FIG. 31 Close-up view of the nozzle design used in the RSF oven. (Courtesy of Panasonic.)
FIG. 32 Comparison between heating and DT of the old heating system and the RSF system. With the new nozzle design matrix, the RSF has an improved heat transfer efficiency. This allowed for a reduction in oven set temperatures from 300 to 250jC, while reducing the overall temperature gradient (DT) of the PCB during reflow. (Courtesy of Panasonic.)
Pb-FREE COMPONENT CONVERSION
617
FIG. 33 Modifications in the nozzle design resulting in further reductions in the temperature gradients achieved on the FA controller card with the RSF oven. Not only was the gradient reduced in the reflow zone from 40 to 10jC, but the gradient was reduced from 50 to 25jC in the preheat/soak portion of the profile. (From Ref. 22.)
2. Fillet Lifting Fillet lifting or lift-off is a significant issue with lead-free solders. The fillet lift-off mechanism is believed to be associated with the formation of low melting point alloys concentrated near the land/solder interface, and also due to solidification stresses as the solder cools. The lift-off mechanism, starting from the solder wetting stage, was analyzed via video on a frame-to-frame basis, some of which are shown in Fig. 44. It was learned that the solder solidifies from the outer edges of the fillet inward, and that the crystals grow toward the top of the fillet. Then, lift-off occurs a few seconds after the fillet surface is completely solidified [6]. The model of the lift-off mechanism shown in Fig. 45 was therefore developed utilizing the videotaped images. According to the model (Fig. 45), the molten solder builds up in phase 2 and begins solidifying from the outside in phase 3, with the crystals growing in the upward direction.
FIG. 34 A vertical oven is used as a preheat section to deliver PCBs to an early model reflow oven consisting of only a few zones. (From Ref. 23.)
618
STALTER ET AL.
FIG. 35 By delivering a PCB from the inline preheater (Fig. 34), the PCB’s soak temperature can be effectively elevated to 170–180jC and the reflow temperature can be reduced to 230jC from 240jC. a) Is the reflow profile without additional preheat oven, and b) is the profile using the preheat oven. (From Ref. 24.)
FIG. 36 Evaluation board used for wave soldering study. (Courtesy of Panasonic.)
Pb-FREE COMPONENT CONVERSION
619
TABLE 7
Component and Electrode Finishes Used for Wave Soldering Test Board
Part type
Chip R/C
QFP
Mini Tr
SSOP/TSOP
Connector
DIP
Jumper wire
Electrode finish
Sn–Pb, SnBi
Sn–Pb, SnBi, Sn, Au, Pd
Sn–Pb, SnBi, Sn–Ag– BiCu
Sn–Pb, SnBi
Sn
Sn–Pb, SnBi, SnAg
Sn–Pb, Sn, SnBi
Courtesy of Panasonic.
In phases 4 and 5, stress accumulates as the solder solidifies further, until peeling starts in phase 6. As the peeled-back area becomes larger in phases 7 and 8, low melting point components run into the crack, ultimately causing the low melting point solder material to accumulate at the interface between the lead and the land [6]. To verify these internal processes, the rate of phase change from liquid to solid was calculated using Sheil’s equation (Fig. 46). The effect that a maximum 1% change in impurity concentration might have on the solder solidification process was investigated. From Fig. 46, the melting point of Sn–0.8Cu–0.1Pb–(0–0.6)Bi solder is reduced by almost 30jC. It is believed that a small percentage of liquid phase solder remains during the final stage of solidification of the solder joint, increasing the time necessary to completely solidify the solder [7]. a. Effect of Lead (Pb) and Copper (Cu) Impurities. Fig. 47 shows that Pb and Cu concentration levels increase the rate of lift-off for a Sn–Cu, lead-free solder bath. In this experiment, Sn–Pb, Sn–Cu, and Sn–Bi lead finished components were soldered using eutectic Sn– 0.7Cu wave solder. As the concentration of Pb exceeds 0.2% [Fig. 47(a)], the lift-off rate was observed to increase sharply. As the concentration of Cu is maintained below 1.0%, the lift-off rate is essentially unaffected [Fig. 47(b)]. This is especially true when soldering lead-free electrode finishes with a Sn–0.7Cu wave solder bath, where the observed lift-off rate was zero at levels of less than 1.0% Cu. In general, Panasonic has found that Cu and Pb concentrations of less than 0.85% and less than 0.2%, respectively, to be the practical limits for impurities in Sn–Cu and Sn–Ag–Cu lead-free wave soldering baths. b. Effect of Board Design. Fig. 48 shows a practical method to reduce fillet lifting, other than controlling impurities. This method consists of reducing the land size on the component or top side of a PCB to reduce fillet lifting. In general, bismuth-bearing alloys show a higher rate of fillet lifting than nonbismuth bearing alloys. However, as stated above, lift-off occurs even with nonbismuth bearing alloys. 3. Wave Soldering Machine Enhancements Panasonic made several enhancements to their wave soldering machine to improve soldering with lead-free alloys. These enhancements pertain to monitoring and controlling impurities and redesign of the wave nozzles. a. Nozzle Modification. The nozzles on the wave solder bath were modified (Fig. 49) to accommodate a higher temperature bath. As the melting point of lead-free solders is higher than eutectic Sn–Pb, the distance between the laminar and turbulent nozzle for eutectic Sn–Pb allows for too much cooling, potentially allowing the solder to start solidifying between the two nozzles. Therefore the distance between the nozzles was reduced from 100 to 50 mm to eliminate this problem. Also, the nozzle hole pattern was changed from a two-hole pattern to a more pronounced three-hole pattern (Figs. 49 and 50) and eventually a four-hole pattern. As discussed earlier, the wetting times for lead-free solders are longer because of the reduced wettability of these solders compared to eutectic Sn–Pb. Therefore it is necessary to increase the PCB’s time over the wave to achieve adequate wetting. Taking these two factors into consideration, time in the solder wave increased from 2 to 3.5 sec. The effects of the nozzle enhancements are shown in Fig. 51. The modified nozzle design using the three-hole design pattern outperformed the standard nozzle design even with an inert atmosphere using a Sn–0.7Cu bath.
60
55
55 >80
Bridge
D
D
D
D
Sn–2.5Ag– 5Bi–0.5Cu
Sn–0.7Cu
Sn–3.5Ag– 0.7Cu Sn–37Pb O
O
O
O
Plating compatibility
O
D 10%
O
D 20%
Void
0 = preferred. D = Marginal, O = acceptable, and O Courtesy of Panasonic.
Solder
Wett (% land coverage)
D
D
D equip dep
O
Icicle
TABLE 8 Summary of the Wave Soldering Evaluation Results
O
O
O
O
Overall bond strength
JW—O QFP—O JW—D QFP—O
JW—O QFP—O
JW—O QFP—D
Fracture mode
O
D
O
0 O
Crack, % elongation
JW—O QFP—O JW—D QFP—O
JW—O QFP—O
JW—O QFP—D
Strength
Bond strength and thermal aging
D 2/9 top side 0 O
X 9/9 both sides D 1/9 top side only
Fillet lifting
0 O
D Cu concentration dross D
D 0.2% Pb
Impurity res.
620 STALTER ET AL.
Pb-FREE COMPONENT CONVERSION
621
TABLE 9 Comparison of the Joint Strength of Several Lead-Free Alloys and the Benchmark Eutectic SnfPb Solder Wave soldering alloy Snf2.5Agf5Bif0.5Cu Snf0.7Cu Snf3.5Agf0.7Cu Snf37Pb
Melting point (jC)
QFP pull strength (kgf)
Jumper wire pull strength (kgf)
Elongation (%)
199f218 227 216f219 183
1.5f3.7 1.8f3.4 2.0f3.8 2.3f3.3
6.1f7.7 4.4f6.9 5.1f7.4 3.8f5.1
23 57 49 59
Courtesy of Panasonic.
b. Monitoring Bath Impurity Levels. As noted earlier, fillet lifting is influenced by impurity levels. Also, impurity levels can have a big influence on the strength of solder joints formed by some lead-free wave solder baths, thus an important consideration. In general, realtime monitoring and impurity control are not necessary with Sn–Pb baths as they can accommodate larger quantities of impurities. However, simple bath maintenance regime can easily be adopted to manage the control of impurities. Panasonic determined the standard practice of controlling a wave solder bath by simply replenishing solder was impractical and costly in the case of lead-free solders. Therefore a real-time monitoring system was developed to measure impurity concentrations in the bath on the production floor. The monitor, developed in cooperation with Malcom Industries, operates on the principle of differential temperature analysis or DTA [8]. Fig. 52 illustrates the system in operation over the range of 0% to 0.3% Pb impurity. c. Real-Time Control of Impurities. Panasonic has also phased in its manufacturing operations a three-zone refining process as a method to control impurity levels in real time. The method uses a technique, very similar to the methods used in IC crystal growing, whereby a controlled cooling and heating rate concentrates the impurities into a low-melting point alloy [9]. The process is based upon controlling the rate at which the solid interface traverses across a billet of solder (Fig. 53). d. Principle of Zone-Refining. As the metal alloy solidifies, the solute or impurities extrude from the crystal and the excess solute disperses into the solvent or liquid tin. Fig. 54 illustrates the diffusion of the liquid phase. Here diffusion is considered only vertical to the solidification interface and can be ignored into the solid area. The amount of solute flowing ahead of the solid interface is given by, D d2 C=dx2 ðcm2 =secÞ
TABLE 10
ð1Þ
Summary of Wave Solder Alloy Evaluations
Lead-free solder attribute Wetting Melting point Fillet lifting Single alloy choice Courtesy of Panasonic.
Summary Reduced for all lead-free materials sampled Significantly higher than that of eutectic Sn–Pb (of those evaluated) Can be an issue with lead-free solders, especially with bismuth containing solders (in general). No single alloy proved best in all categories
622
STALTER ET AL.
FIG. 37 Thermal cycle tests for a 0.8-mm pitch QFP using several lead-free wave solder alloys. Thermal cycling conditions were 40jC to 85jC for 30-min dwell times. Electrode finishes tested were a) Sn–Pb finish, b) Sn–Bi finish, and c) Pd finish. The Sn–Ag–Cu lead-free alloy is generally observed to be the most resilient to electrode finish materials, outperforming even the eutectic Sn–Pb solder in most cases. (From Ref. 24)
where D is the coefficient of diffusion in liquid phase. Using R (cm/sec) as the interface migration speed, the steady state is given as, D d2 C=dx2 þ R dC=dx ¼ 0
ð2Þ
Solving Eqs. (1) and (2) yields, CL ¼ Ca eðRXV=DÞ þ C0
ð3Þ
where Ca is the excessive concentration of liquid phase at the interface, C0 is the initial composition, XV is the distance from the interface, and CL is the concentration at XV. The distribution coefficient (k0) is the ratio of the solid phase concentration (C0) to the liquid phase concentration (CL), k0 ¼ C0 =CL
ð4Þ
As the state of the solid is C0 at some distance from the interface, CL can be stated as CL ¼ C0 þ Ca
ð5Þ
Pb-FREE COMPONENT CONVERSION
623
FIG. 38 Thermal cycle tests for a single-sided jumper wire using several lead-free and eutectic Sn–Pb wave solder alloys. Thermal cycling conditions were 40jC to 85jC for 30-min dwell times. Wire plating tested were a) Sn–Pb, b) Sn–Bi, and c) Sn. With jumper wires, the Sn–Ag–Bi wave solder outperforms the remaining materials over a wide range of finishes. (Courtesy of Panasonic.)
Using Eq. (5), Eq. (4) can be rewritten to be, Ca ¼ C0 =k0 C0
ð6Þ
From Eq. (6), Eq. (3) can be rewritten to provide the concentration profile of the liquid phase in front of the solid interface in steady state (Fig. 55) [9], h i ð7Þ CL ¼ C0 1 þ fð1 k0 Þ=k0 geðRXV=DÞ The concentration profile for the solid phase after the interface in steady state is represented as [10], n h i o k RXV=D Cs ¼ C0 ð1 k0 Þ 1 e0 þ k0 ð8Þ A graphical representation of Eqs. (7) and (8) can be seen in Figs. 56 and 57. As the interface migration speed is reduced, the wider the clean or purified area becomes. The above discussion provides the theoretical basis for zone refining, a method used to remove impurities through controlled solidification and segregation.
624
STALTER ET AL.
FIG. 39 Comparison of the wettability of several lead-free solder baths and the eutectic Sn–Pb benchmark solder for various chip components and finishes. The lead-free alloys each show varying degrees of wettability with the various component electrode finishes, whereas the eutectic Sn–Pb solder completely wet for each test condition. (Courtesy of Panasonic.)
FIG. 40 Comparison of jumper wire wettability for various lead-free alloys and eutectic Sn–Pb as the benchmark. Eutectic Sn–Pb wet 100% of the land (terminal pad) while all the lead-free alloys exhibited a reduced level of coverage. (From Ref. 25.)
Pb-FREE COMPONENT CONVERSION
625
FIG. 41 Wetting balance results for eutectic Sn–Pb and two lead-free alloys. The test consists of monitoring the time required to change the force exhibited on a coupon from compressive (solder is pushing on the coupon) to a tensile force (solder is pulling on the coupon). This change in force direction (or vector) is called the ‘‘zero force time.’’ (From Ref. 26.)
FIG. 42 Wave soldering results for Sn–Ag–Bi–Cu alloy that show the effect of increasing the wave temperature or reducing the conveyor speed to improve wetting. As the wave temperature is increased from 245 to 270jC, the percent coverage increases. In addition, as the wave speed is reduced from 1.0 to 0.75 m/min, the percent coverage is increased while the bath temperature is kept constant at 250jC. (Courtesy of Panasonic.)
626
STALTER ET AL.
FIG. 43 Wave soldering results for Sn–0.7Cu alloy that show the effects of increasing the solder wave temperature or reducing the conveyor speed to improve wetting. As the temperature of the bath is increased or the speed of the PCB is slowed, the percent coverage of the terminal pad was observed to increase. (Courtesy of Panasonic.)
e. Verification of Zone Refining of Lead-Free Solders. Panasonic conducted tests to determine the optimal rate, billet length, and other parameters to utilize the zone refining technique to remove impurities from lead-free solder. Fig. 58 shows the system used to evaluate the Sn–3.0Ag–0.5Cu solder alloy that was initially contaminated with 0.18% Pb. As the solder was processed in the zone refining system (Fig. 58), the Pb impurity was reduced in the solidified solder to a maximum of 0.07% when the migration rate was set to the slowest rate. At faster rates, the impurity levels were higher (from 0.16% to 0.18% at a rate of 1jC/5 min). The results of migration speed and impurity removal efficiency are shown in Fig. 59. Also, as predicted by Eqs. (7) and (8), the concentration levels in the liquid phase increased to a higher level ranging from 0.24% to 0.71% Pb depending on the solidification speed. In addition to varying the migration speed, the desired solder purification level can also be achieved utilizing a multipass method. In Fig. 60, a Sn–3.0Ag–0.5Cu alloy is purified at a high rate of migration (1jC/5 min) but with multiple passes to achieve the same effect as fewer or a
FIG. 44 Frames captured from video observations of Sn–3.5Ag solder of a 14-pin DIP IC during the soldering process. (From Ref. 27.)
Pb-FREE COMPONENT CONVERSION
627
FIG. 45 Illustration of the lift-off phenomena sequence. As the solder solidifies, a low-melting-point alloy forms near the surface of the land (terminal pad) just under the solidified solder. This lowermelting-point material forms a crack near the surface and allows the solidifying solder on the outside to pull up and away from the land. (From Ref. 27.)
FIG. 46 Change in solid phase percentage in solidification of Sn–0.8Cu–0.1Pb–(0–0.6)Bi. The higher the concentration of impurities, the longer the liquid phase or the lower the melting point (calculated with Sheil’s equation). (From Ref. 28.)
628
STALTER ET AL.
FIG. 47 As the impurity level due to a) lead (Pb) and b) copper (Cu) increases, the lift-off rate was observed to increase for the lead-free Sn–0.7Cu solder. (From Ref. 29.)
single pass at slower rates. As the material is repeatedly purified in the zone refining system, the impurity levels continue to drop (Fig. 60). Fig. 61 shows the factory system implemented in production testing. The results of the initial trials show that a 150-kg Sn–3.0Ag–0.5Cu solder bath can be purified from a 0.25% Pb to 0.18% Pb in about 10 days. The cycle rate is approximately 30 kg every 2 days with a bath being turned over every 10 days (five turns). The discharge concentration was 0.8% Pb. With this system, the bath level can be maintained continuously at a level of less than 0.2% Pb [11]. f. Practical Examples of Wave Soldering. With a Sn–0.7Cu wave, a high dross rate and potential tin whisker formation and growth are a concern. Therefore trace amounts of Ni are added to the Sn–0.7Cu eutectic bath to reduce the drossing rate and eliminate the Sn whiskering problem in this bath (Fig. 62). This Sn–Cu-based bath from Nihon Superior, called SN100C, is very stable with makeup solder-type SN100Ce. It is widely used by Panasonic using a bath temperature set at 255jC for products such as video tape recorders (VTR) and DVDs. A Sn–3.0Ag–0.5Cu solder from Senju (M705) is utilized at Panasonic’s TV factory for both wave and selective soldering baths (Figs. 63 and 64). It required approximately 4 months to integrate lead-free soldering and completely phase-out the use of Sn–Pb solders. The wave solder bath is maintained using a simple temperature probe to monitor the solder level. When the bath level drops below the probe height, an automatic wire feeder is energized to feed in the solder wire
FIG. 48 The incidence of fillet lifting can be significantly reduced by reducing the size of the land on the top of the PCB. (Courtesy of Panasonic.)
Pb-FREE COMPONENT CONVERSION
629
FIG. 49 Several changes were made to the wave solder nozzles to improve lead-free soldering. From a), the distance between the turbulent and laminar flow sections was reduced from 100 to 50 mm, and b) the multihole pattern was changed from a two-row design to a three-row design. (Courtesy of Panasonic.)
of a Sn–3Ag+0.008P (Senju M708) solder (Figs. 65 and 66). The typical bath life of the Sn–Ag– Cu bath is about 3 weeks depending on production volume.
G.
Summary and Conclusions
1. Successful Entry to Lead-Free Manufacturing With the introduction of lead-free products such as the MiniDisk players, Panasonic has gained broad experience with lead-free soldering. From this and other products, Panasonic learned it is possible to use lead-free solders in consumer electronics manufacturing without sacrificing quality or production volumes. The quality levels were noted to have improved with the MiniDisk
FIG. 50 Photographs of the wave nozzles. (a) Showing the overall view of the two nozzles and (b) a close-up view of the mountain-like shape of the multihole patterned nozzle. Further enhancements to the nozzle design include a four-hole pattern (not shown). (Courtesy of Panasonic.)
630
STALTER ET AL.
FIG. 51 Series of photographs that show the superior wetting of the new nozzle design compared to the standard nozzle in both air and in an inert atmosphere. Here, a) are photographs of plated through hole without any component lead, and b) a plated through hole with a component lead present. (Courtesy of Panasonic.)
player even as the lead-free system (Sn–Ag–Bi–In) was in its initial stages of manufacturing compared to production with Sn–Pb (Fig. 67). Similar results were obtained during VTR production utilizing Sn–0.7Cu wave solder. Here quality levels saw an increase in defect levels after the introduction of lead-free solder. However, after improvements such as nozzle design enhancements, the defect level was reduced to one-half the eutectic Sn–Pb solder level (Fig. 68). Panasonic has experienced similar results when lead-free solder assembly was phased in for TV production. The defect levels dropped from a historical rate of 3% with eutectic Sn–Pb to a 0.07% level with Sn–3.5Ag–0.5Bi–8In solder paste and Sn–3.0Ag–0.5Cu wave solder. a. Many Challenges. Success was only possible after a significant number of challenges were addressed, some of which persisted into the manufacturing stage. For example, the Panasonic factory at Utsunomiya worked for more than 1 year to utilize Sn–3Bi–8Zn solder paste on various products. This solder alloy has proven difficult to work with because of its
FIG. 52 A real-time monitor based on DTA techniques was developed in conjunction with Malcom Industries to automatically monitor the impurity levels in a lead-free wave soldering bath. a) The monitor indicates the b) initial melting point of the solder bath alloy and c) lower melting point due to lead (Pb) contamination. (Courtesy of Panasonic and Malcom Industries.)
Pb-FREE COMPONENT CONVERSION
631
FIG. 53 As the molten area migrates down the sample, the level of impurities increases in the molten or liquid phase, while the impurity level decreases in the solid phase that had previously been heated. The technique is based on a well-known concept referred to as zone refining. (Courtesy of Panasonic.)
shorter stencil life and intermittent nonwetting defects (voids) to ball grid array (BGA) balls consisting of Sn–Ag–Cu [12]. Therefore the Utsunomiya factory switched over to the bismuth and indium containing solder alloy in early 2003. 2. Monitoring Field Performance Figs. 69, 70, and 71 show that the use of lead-free solder (Sn–Ag–Bi–In) has not resulted in reliability problems. However, some joints have indicated a concern with the potential precipitation of bismuth from the alloy over time. Therefore the bismuth content of the solder used to assemble the MD player will be reduced from 2.5% bismuth to 0.5% bismuth with 6% indium.
FIG. 54 An illustration of the diffusion principle of the solute (impurity) into the solvent (molten tin). The concentrations of the impurities increase at the interface. (Courtesy of Panasonic.)
632
STALTER ET AL.
FIG. 55 The concentration profile as described by Eqs. (3), (4), (5), and (6). Immediately after solidification starts, when the interface is moved slightly, the impurities in the solid phase are decreasing and the impurities are increasing in the liquid phase. (From Ref. 30.)
3. Future Lead-Free Products Further reductions in the melting point are being realized with the Sn3.5Ag8.0In0.5Bi alloy (Fig. 72). This alloy is geared toward desktop and notebook computer assembly applications. It is anticipated that rolling this out to the manufacturing floor will pose some significant challenges. Among these may be modifications to existing wave soldering equipment and new reflow oven designs. Some ‘‘tweaking’’ of AOI equipment may be necessary to compensate for the duller or matte appearance characteristic of these solders. 4. Cost Material cost was another issue of concern. With the introduction of lead-free, economies of scale worked against the MD player product. No other manufacturer was using a lead-free solder in significant volume. When first introduced in 1998, the cost of the lead-free solder paste was about $150/kg. Then in 2000, it dropped to $100/kg. By 2003, the cost of the lead-free solder paste was only marginally higher than eutectic Sn–Pb with the downward trend continuing.
FIG. 56 Result of Eq. (8), the concentration profile of the solid phase of a binary, Sn–0.5% Pb alloy at various solidification migration speeds, R of 1.2, 3.0, and 6.0 mm/min. At the slower rates, the level of impurities (Pb) drops from the solid tin closer to the interface. The distribution coefficient, k0, is 0.074, the coefficient of diffusion, D, is 5105 (cm2/sec). (Courtesy of Panasonic.)
Pb-FREE COMPONENT CONVERSION
633
FIG. 57 Result of Eq. (7), the concentration profile of the liquid phase of a binary, Sn–0.5% Pb alloy at various solidification migration speeds, R of 1.2, 3.0, and 6.0 mm/min. At the slower migration speeds, the impurity levels are concentrating at the solid-to-liquid interface more heavily than at faster migration speeds. (Courtesy of Panasonic.)
IV.
OTHER EXAMPLES OF INDUSTRY PRODUCT CONVERSIONS
A.
Flextronics International Ltd. Lead-Free Assembly
Flextronics International Ltd., with worldwide locations providing electronic manufacturing services, perceived early on the importance of environmentally friendly manufacturing. Flextronics began the journey to lead-free manufacturing in 1997 and as of 2000 had high-volume Pbfree production of 150,000 units per month across several products [33]. As of November 2002, they had shipped several million products with lead-free solder including cell phones, printers, and computer security devices, and have several factories in Asia, the Americas, and Europe using lead-free solder in volume manufacturing [34].
FIG. 58 A laboratory scale system of the zone refining equipment used in the Environmental Production Engineering Lab of Kadoma, Japan, to verify and evaluate the feasibility of the technique. (Courtesy of Panasonic.)
634
STALTER ET AL.
FIG. 59 Testing of the zone refining process by purification of Sn–3.0Ag–0.5Cu solder with an initial state of 0.18% Pb contamination. As the solidification rate is reduced, the concentration of the Pb remaining in the purified solder is reduced more than with higher migration rates. (From Ref. 31.)
1. Considerations Flextronics separated the issues surrounding the conversion to lead free into three categories: impact to the process, impact to equipment, and cost impact. Using a test vehicle which included QFPs with pitches ranging from 0.3 to 0.5 mm, and CSPs with pitches ranging from 0.4 to 0.6 mm, a study was conducted to understand the manufacturing impact of three no-clean, lead-free solders from the Sn–Ag–Cu family compared to a standard no-clean eutectic Sn–Pb solder paste. The evaluation focused on printability, solder paste pot-life, wettability, reflow process window, and inspection [33].
FIG. 60 As the zone refining process is repeated, the impurity levels continue to concentrate into the liquid phase further reducing the contaminate in the solidified material. Here the impurity levels are reduced in a Sn–3.0Ag–0.5Cu alloy from 0.17% Pb to 0.07% Pb in five passes at a rate of 1jC/5 min. With a single pass and at the same rate of 1jC/5 min, the Pb level is only reduced to 0.11% Pb. (Courtesy of Panasonic.)
Pb-FREE COMPONENT CONVERSION
635
FIG. 61 Photograph of the zone refining system utilized in mass production scale-up trials. The Pb concentration level was maintained below the desired impurity levels of 0.2%. (From Ref. 31.)
a. Printability. Variables such as printing pressure, printing speed, and squeegee separation speed were first determined. It was then concluded from previous evaluations [35] that the ratio of stencil thickness to aperture opening, or so-called area ratio, was the critical parameter affecting print quality. Solder paste height measurements were plotted as a function of the area ratio, and comparisons of the lead-free solder alloys to eutectic Sn–Pb revealed that the area ratio of 0.5 must be achieved. It is above this value that the solder paste height was observed to remain consistent, but below a ratio of 0.5 height decreased linearly as a function of decreasing area ratio, independent of alloy (Fig. 73) [33].
FIG. 62 Additions of trace amounts of Ni to the Sn–0.7Cu bath have shown to dramatically improve the wave solder bath by reducing the dross rate, stabilizing the wave shape and height, and eliminating whisker defects. (From Ref. 24.)
636
STALTER ET AL.
FIG. 63 Photograph of the selective soldering machine used at Panasonic’s TV factory in Utsunomiya, Japan. (Courtesy of Panasonic.)
b. PCB Surface Wettability. An experiment was conducted by Yi et al. to evaluate the wetting of several different solder pastes on different surface finishes as compared to a Pbcontaining paste [33]. HASL (Sn–Pb), OSP (Entek), and Ni/Au surface finishes were utilized. A 6mil-thick stencil with 22-mil round openings was utilized. The solder was screened and reflowed and the solder wetting diameter measured and cross sectioned (Fig. 74). It was concluded by the authors that the Ni/Au finish had the best spread and smallest wetting angle, while the Entek OSP
FIG. 64 Photograph of a TV tuner assembly where large subassemblies and odd-shaped connectors are soldered automatically in the selective soldering machine. (Courtesy of Panasonic.)
Pb-FREE COMPONENT CONVERSION
637
FIG. 65 Photograph of Panasonic engineers demonstrating the lead-free wave soldering system at the TV factory in Utsunomiya, Japan. (Courtesy of Panasonic.)
FIG. 66 Photograph of a system that maintains the wave solder bath level by integrating a temperature probe to the wire feeder. As the bath lowers, the temperature of the probe is reduced. When the temperature is lowered to a predetermined level, the wire feeding mechanism is energized to feed makeup wire Sn–Ag+0.008P into the bath to maintain level. (Courtesy of Panasonic.)
638
STALTER ET AL.
FIG. 67 Upon introducing lead-free soldering at the minidisk player factory, an improvement in manufacturing quality was observed immediately as noted by the comparison of a typical month of eutectic Sn–Pb production and the first three months utilizing lead-free soldering. (From Ref. 32.)
FIG. 68 Upon introducing lead-free soldering at the VTR factory, defect levels were significantly higher than eutectic Sn–Pb. However, after instituting several improvements to the wave soldering equipment, the defect rate of lead-free wave soldering was reduced to one-half that of eutectic Sn–Pb. The enhancements are: step 1, raising the preheat temperature from 100 to 125jC; step 2, use of the multihole patterned nozzle design; and step 3, reducing the pitch between nozzles. (Courtesy of Panasonic.)
Pb-FREE COMPONENT CONVERSION
639
FIG. 69 Photograph of a minidisk player assembly that was returned from the field after having experienced approximately 3000 hr of operation. The joints were analyzed to determine the long-term effects on the solder alloy. (Courtesy of Panasonic.)
performed the worst of the three, having the smallest spread area and the largest wetting angle. Among the several Pb-free solder pastes evaluated, none of them individually performed the best across all of the surface finishes (Fig. 75). c. Reflow Process Window. To evaluate the process window during reflow of the Pb-free solder pastes, peak temperatures of 220jC, 235jC, and 245jC were tested. The highest peak temperature resulted in the formation of a dark residue on the joint suggesting charring of the flux in the paste. At 220jC, insufficient wetting was observed. The authors concluded that although a F10jC process window is desirable and suitable for eutectic Sn–Pb solder, a tighter process window is required when forming solder joints with Pb-free solder pastes.
FIG. 70 SEM cross sections of the QFP depicted in Fig. 69. a) Overview of a lead that experienced 3000 hr of operation in the field. b) An enlargement of the area designated as A, showing the lead/ solder interface. c) An enlargement of the area designated as B, showing the solder/land (terminal pad) interface. No problems were noted in relation to the Sn–Ag–Bi–In alloy. (Courtesy of Panasonic.)
640
STALTER ET AL.
FIG. 71 SEM cross sections of the SOP depicted in Fig. 69. a) An overview of a lead that experienced 3000 hr of operation in the field. b) An enlargement of the area designated as A, showing the lead/ solder interface. No problems were observed. c) An enlargement of the area designated as B, showing the solder/land (terminal pad) interface. Although this particular cross section shows no observed issues, it has been noticed that a slight amount of elemental Bi was observed to have precipitated from the Sn–Ag–Bi–In solder alloy in some cases. (Courtesy of Panasonic.)
d. Conclusion. The result of these and several other studies conducted at Flextronics [33,34] resulted in the successful implementation of a lead-free soldering process capable of volume production. Although there is not an extensive database of experience on Pb-free soldering, companies are performing the necessary evaluations, and implementation of Pb-free assembly processes are slowly becoming pervasive in the electronics industry.
B.
Visteon and the Challenge of Lead-Free in Automotive Systems
Implementing lead-free assembly processes in the automotive industry gives rise to unique requirements that must be met for successful product introduction. The most challenging
FIG. 72 Further reductions in melting point coupled with reductions in Bi content are the future trends for lead-free alloys with Panasonic products that use the Sn–Ag–Bi–In system. (Courtesy of Harima Chemicals.)
Pb-FREE COMPONENT CONVERSION
641
FIG. 73 Solder paste height vs. area ratio (AR) for a) Pb-free and Sn–Pb solder alloys. (From Ref. 33.)
application environments necessitate very stringent electronic product demands. For example, many products must be capable of high thermal resistance because of the location of the parts positioning in the engine compartment resulting in thermal-induced strains and material degradation. Depending on season and geography, the electronics in a vehicle may experience very severe temperature fluctuations undergoing approximately a 200jC change in a matter of minutes and exposure to high humidity conditions as well. Also, differences in road conditions give rise to engine vibration conditions in addition to the environmental challenges as noted. Visteon Automotive Systems has performed extensive engineering analysis on Pb-free alloys since the early 1990s. Their objective was to launch the first lead-free soldering process into volume production on a commercial automotive electronics product [36]. 1. Alloy Selections Considerations Given the wide selection of lead-free solder alloys with higher processing temperatures than eutectic Sn–Pb solder, a choice required a solder that had equivalent or better mechanical properties, adequate availability, and one with suitable soldering characteristics. The focus was
642
STALTER ET AL.
FIG. 74 Cross sections depicting wetting angles of Pb–Sn (type A) and lead-free solders (types B–D) as a function of board finish. (From Ref. 33.)
on developing a no-clean process. The tin–silver binary eutectic (96.5Sn/3.5Ag) was chosen based upon metallurgical stability, mechanical properties, and widespread availability in paste, bar, and wire form. 2. Product Selection Several criteria were evaluated in selecting a product for conversion, as illustrated in Table 11. Each criterion was weighted and the best candidate with the simplest design and manufacturing process was chosen (Fig. 76). Table 12 provides the details of the selected product. 3. Process Development Immersion silver plating was chosen as the board surface finish because of the consistency in plating thickness and surface topography. The major unknown that had to be evaluated was the suitability of the surface finish. Because there is a significant schedule delta among component
Pb-FREE COMPONENT CONVERSION
643
FIG. 75 Bar-graph illustrating the wetting diameter of Pb–Sn alloy (type A) and lead-free alloys (types B–D) as a function of board finish. (From Ref. 33.)
manufacturers in their conversion to lead-free surface finishing, mixed component finishes were utilized. The product had to meet the existing reliability standard [36]. In choosing a part with the simplest reflow process, Visteon chose a single-sided assembly requiring only one pass through the reflow furnace. A tin–silver eutectic paste was evaluated with several no-clean flux formulations. A temperature profile similar to the eutectic Sn–Pb soldering profile was utilized consisting of a preheating stage, a temperature soak, and a temperature spike. Solder wetting characteristics, component skewing, extraneous solder balls, component tombstoning, PCB warpage, and PCB delamination were evaluated. First attempts at lead-free soldering revealed an increased occurrence of solder ball formation between the component
TABLE 11 Visteon Automotive Product Selection Criteria for Pb-Free Conversion Candidates Selection criteria . . . . . . . .
Perceived customer interest Low consumer risk product Product engineering office acceptance Long production life Less product design complexity Low manufacturing process complexity Medium-to-high production volume Low line mix
Source: From Ref. 36.
644
STALTER ET AL.
FIG. 76 Photo of Visteon’s lead-free conversion product. a) Photo depicting panel with 56 array of cards. b) Single card fully populated with components. (From Ref. 36.)
terminations, as well as tombstoning of the 0805 capacitors. Solder ball formation was attributed to the print characteristics utilizing a common stencil resulting in more solder volume being deposited with the lead-free solder paste compared to the eutectic Sn–Pb solder paste. It was concluded that the conventional dual-ramp reflow profile was not satisfactory for lead-free processing this product as it increased the incidence of tombstoning. Paste printing parameters, in conjunction with profile modifications, were made to improve solder joint integrity, reduce the occurrence of solder ball formation, and decrease component tombstoning [36]. 4. Testing It was noted that the penetration by the test probe in the bed-of-nails tester resulted in less penetration into the immersion Ag as compared to penetration into the Sn–Pb HASL finish, as shown in Fig. 77(a). A higher spring force and a three-sided chisel probe were chosen to improve
TABLE 12
Visteon Selected Product Attributes
Variable . . . . . . . . . . . .
Product application Printed circuit board material Panel dimension Panel thickness Number of cards per panel Card size Number of copper layers Track width/spacing Surface finish Component count Component types Solder joint count
Source: From Ref. 36.
Product attribute Automotive electronic module FR4 194mm 214mm 0.062 in. 30 cards 30mm 30mm two layers 0.008 in./0.008 in. Sn/Pb HASL 33 SMD per card, single-sided application SOIC, 0805, and 1206 chips, SOD, SOT, crystal 92 per card
Pb-FREE COMPONENT CONVERSION
645
FIG. 77 In-circuit testing on immersion silver pads. a) SEM of a low-force spear head test-probe indentation. b) SEM of a high-force three-sided test-probe indentation. (From Ref. 36.)
on yields and eliminate false rejections. Typical indentation marks with the three-sided probe are shown in Fig. 77(b). 5. Qualification Rigorous testing was performed which included accelerated environmental stress testing at each level of assembly. The testing was designed to simulate 10 years/150,000 miles endurance. [36] 6. Final Steps to Production In addition to passing the electrical, mechanical, and reliability testing, there were other considerations by the Visteon team that had to be addressed prior to launching the product. Close control of production would be required as products in the line switched between the standard lead-containing process and lead-free processing. The hardware and materials would have to be distinguishable to the production operators to insure a mix-up did not occur. To mitigate these risks, Visteon worked with their paste supplier to visually change the packaging of the cartridge with a colored band to represent the lead-free paste. In addition, two identification holes, pictured in Fig. 78, were added to the PCBs, that are automatically detected at each subassembly step by optic sensors. Three check gates were set up within the surface mount assembly line to perform the checking and verification. Operator training was also key to adding precaution to the automatic checks with respect to visual identification, lead-free solder joint criteria, and handling of the materials to prevent contamination [36]. 7. Summary Volume production of the lead-free assembly has been underway since June 1, 2001. Visteon produces about 7000 units a day with lead-free processing. The next level of complexity for future products will incorporate double-sided reflow, selective soldering, and wave soldering process implementation. Visteon received approval from Ford Motor Company to manufacture and supply its Passive Anti-Theft System transceiver module using lead-free solder [37].
646
STALTER ET AL.
FIG. 78 Photo of a printed circuit board (PCB) with lead-free identification holes. (From Ref. 36.)
C.
IBM and the Conversion of High-Complexity SMT Components to Lead-Free Technology
One of the biggest advantages to complex components that are lost with the conversion to leadfree processing is the ease of incorporating a solder hierarchy that is critical to many interconnection solutions. IBM uses a dual melt solder termination system for its ceramic column grid array (CCGA) components. Solder columns are used as the interconnection between the ceramic chip carrier and PCB. They provide a method of accommodating the strain induced due to the mismatch in coefficient of thermal expansion between the carrier and the board. This is an important feature, especially as the ceramic carrier increases in size, thus increasing the distance to neutral point [38, 39]. In addition to providing a method of attaching the component to the board, the columns also provide the electrical pathway between the chip carrier and the PCB. The solder columns fabricated by IBM are one of three configurations: a high lead (90Pb/10Sn) column attached to both the chip carrier and PCB with a low-melt (63Sn/37Pb) solder fillet; a high lead (90Pb/10Sn) column ‘‘cast’’ to the chip carrier by melting the column directly onto the NiAu pad of the ceramic chip carrier; and a column last attach solder process (CLASP) [40]. In the latter case the high melt column is attached last, or post chip join and underfill, to the chip carrier with a 63Sn/37Pb solder doped with palladium such that after reflow the solder mixes and forms a higher melting alloy (Fig. 79). In order to replicate this structure in a lead-free configuration, it would be necessary to find a suitable lead-free alloy in the 300jC range to provide the solder hierarchy necessary to prevent the collapse of the connection during PCB assembly. 1. CCGA Replacement Criteria In addition to replicating the mechanical properties of the column such that the thermal fatigue resistance is equivalent to the existing CCGA versions described above, it is critical that the interconnections have equivalent electrical performance. Manufacturability aspects must also be considered to assure that the columns can withstand the higher temperatures required of lead-free processing. The advantages of the column last configuration were desirable in converting to a lead-free interconnect in that the part could experience first-level assembly of the active and passive components, the bare Ni/Au I/O electrically tested, and then experience a low-temperature reflow to attach the column resulting in a high-melting solder joint. 2. Column Selection A column made out of pure copper was selected to replace the 90Pb–10Sn column primarily because of its high melting temperature, coupled with electrical performance characteristics. The column had to be optimized for both electrical and mechanical properties, in addition to selecting
Pb-FREE COMPONENT CONVERSION
647
FIG. 79 Ceramic column grid array (CCGA) configurations. a) Single melt eutectic Pb–Sn fillet, b) cast column with eutectic Pb–Sn on card pad, c) column last attach solder process (CLASP) with Pddoped solder on chip-carrier pad and eutectic Pb–Sn fillet on card pad.
FIG. 80 Actual loop inductance data vs. predicted results for different Pb-free column geometries. (From Ref. 42.)
648
STALTER ET AL.
TABLE 13 Elastic Limit of 0.36-mm Cu Wires Annealed in N2 for 1 hr at Temperatures Increasing from A to E Anneal temperature Nonannealed A C D E
Elastic limit, MPa 81.3 56.5 54.4 41.4 39.3
Source: From Ref. 41.
a lead-free alloy to attach the column to the chip carrier. Attachment to the PCB would be with the preferred alloy of most industry consortia, SAC, in an effort to support the commonality with second-level assembly suppliers [41]. a. Electrical Optimization. The electrical performance of a column improves with height reduction (lowers loop inductance) and increased column diameter (improves d.c. resistance). However, the taller and thinner the column, the more compliant the structure, and thus the better the thermomechanical fatigue resistance. Several combinations of height and diameter were modeled [42] and compared to the standard 0.5-mm-diameter, 2.2-mm-high 90Pb–10Sn column. Parts were assembled to validate the best candidates from the modeling results and are depicted in Fig. 80. A column length of 1.52 mm was selected to offer the best trade-off between electrical and mechanical performance for the specific application. b. Mechanical Optimization. Taking into account the electrical performance constraints described above, the properties of the Cu column were optimized with respect to thermomechanical behavior. Standard 90Pb–10Sn columns fatigue in the column itself because of the ductility of the material. A copper column, if fabricated by a drawing operation, was significantly more rigid than the Pb–Sn column. A more rigid column may transmit strain to the fillet causing fatigue cracking, and inevitably failure. To optimize the column, annealing was performed to reduce the stiffness. Solder columns exhibit approximately 1% flexural strain, therefore stress at and immediately following yielding was of great interest. Although annealing did not significantly change the ultimate strength of the wire, it did alter the elastic limit (Table 13) [41]. The lifetime of the joints as a function of anneal temperature was predicted and verified by experimental thermal cycle data as shown in Table 14. Cross sections of the copper column at a corner location after annealing and 0jC to 100jC thermal cycle testing are shown in Fig. 81. An annealing temperature was chosen to balance the improved reliability with the potential for handling damage because of the softer columns. Depending on the particular electrical requirements of the application, column dimensions (height, diameter) would be chosen to meet the electrical requirements while maximizing the lifetime.
TABLE 14 Observed Lifetime of Annealed Copper Column Interconnects. All Columns Were 2.2mm in Length and 0.25mm in Diameter Anneal temperature B D F Source: From Ref. 41.
Cycle life 2954 2575 4370
Pb-FREE COMPONENT CONVERSION
649
FIG. 81 Annealed copper column grid arrays (CuCGAs) in a corner location after 4370 cycles at 0 to 100jC. (From Ref. 41.)
3. Fillet Alloy The copper columns were tin-plated to maintain the wettability of the copper by the fillet alloy during both attachment to the chip carrier and board assembly. Having a solder fillet at the chip carrier location that has a slightly higher melting temperature than the card fillet is desirable for card assembly robustness and reworkability. As mentioned earlier, based on the considerations for commonality at card assembly, the SAC alloy was chosen for the card fillet. This dictated the options for a higher melting lead-free alloy required for the copper column-to-component attachment for which a Sn–Ag alloy was chosen [43]. The resulting structure is shown in the cross section in Fig. 82. The figure indicates that the Sn–Ag uniformly wets the tin-coated copper column. Tin-copper intermetallic layers are observed at the interface of the column, and tin–silver precipitates are noted in the solder fillet. 4.
Qualification
a. Moisture Sensitivity Testing. Capless and direct lid attach CuCGA modules were subjected to J-STD-020B [44] moisture sensitivity testing at moisture sensitivity level (MSL) 1 and
FIG. 82 The copper column grid array (CuCGA) structure shown a) optically and b) in cross section as attached to the I/O pad of the chip carrier. (From Ref. 41.)
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TABLE 15 Chip Carrier and Printed Circuit Board Attributes Utilized in Thermal Fatigue Testing of the Copper Column Grid Arrays Ceramic TV Ceramic size Ceramic thickness Encapsulation Column dimensions Column material Column pitch Column array Driclad test card Card dimensions Card cross section Card layout Card surface finish Card pad diameter
White alumina (TV 852) 42.5 42.5mm 2.55 mm, 17 layers Mechanical chip with underfill, direct lid attach 0.25mm diameter, 1.5mm in length Tin-plated copper 1.0 mm 41 41, 1657 total I/O 8640789 229 279 2.36 mm 12S10P five sites OSP 0.70mm design, 0.65mm measurement
Source: From Ref. 41.
qualified for three reflows at 245jC. Underfill integrity was verified by C-mode scanning acoustic microscopy, and electrical testing verified the integrity of the flip chip solder joints that experienced the higher lead-free reflow temperature at the card-level assembly operation. The packages were mounted on cards, subjected to, and passed 2000 deep thermal cycles (DTC) from 55 to 125jC, 96 hr of highly accelerated stress testing (HAST) at 130jC with 85% relative humidity, and 1000 hr of high-temperature storage (HTS) at 150jC. b. Thermal Fatigue. Thermal fatigue testing was performed on special CuCGA daisy chain test vehicles assembled to Driclad PCBs (Table 15). The parts were tested with and without column rework at the chip carrier level, and with and without board rework at the card level. A subset of the parts was subjected to shock and vibration testing. The parts were then thermal cycled from 0jC to 100jC at a frequency of two cycles per hour (Fig. 83). The failure data were fit
FIG. 83 Ceramic chip-carrier and PCB fillet fractures in high-DNP columns after 3480 thermal cycles of 0 to 100jC. a) Low-magnification photo, b) magnified fillet on chip-carrier side, c) magnified fillet on PCB side. (From Ref. 41.)
Pb-FREE COMPONENT CONVERSION
651
TABLE 16 Summary of Copper Column Grid Array Thermal Fatigue Data from Thermal Cycling at 0 to 100jC, 2 cph Cell
Readout
Parts
First fail (cycle)
N50 (cycle)
Sigma
Primea Primea Column rework Card rework
In situb Benchb Bench Bench
30 30 10 10
1410 1660 2700 2360
2200 2410 2760 2770
0.27 0.26 0.15 0.10
a
Half of prime parts preconditioned with impact shock and vibration. Prime parts monitored both in situ and bench. Source: From Ref. 41.
b
to a lognormal distribution to calculate the N50 and sigma. These laboratory fatigue test results are summarized in Table 16 [41]. 5. Summary IBM developed and qualified a lead-free column grid array solution that delivers equivalent electrical performance and a superior lifetime compared to the standard tin–lead technology. The qualification of the lead-free technology supports the manufacturing conditions of 1 column rework with up to two hot oil submersions for column removal. The CuCGA solution can be customized to support various specific application requirements.
D.
Sony Lead-Free Soldering Experience
Green Management 2005 is Sony’s mid-term environmental action program, aimed at specific targets for environmental performance. Under the plan, Sony set restrictions and reduction targets for hazardous materials including lead (Pb) and intends to introduce lead-free solder for use in its main products, and phase-out Pb in most products by March 31, 2005 [45]. Table 17 [46] lists some examples of the progress Sony has made toward that end. Fig. 84 shows a sampling of products with Pb-free printed wiring board assembly introduced by Sony [45]. Sony has been using lead-free solder primarily in consumer products such as televisions, audio products, mobile phones produced in Japan and other locations in Asia since March 31, 2002. By replacing the plating material used for external component contacts, Sony has eliminated 70% of lead from its products [47]. 1. Progress at Sony’s Kohda Division The Kohda Division of Sony that manufactures the Sony Vaio laptop computer as well as camcorders, digital cameras, and the Playstation 2 is one of the most active companies in the movement toward lead-free soldering. These products are assembled on a total of 62 lines in three shifts that run 7 days a week [48]. a. Range of Complexity. From double-sided motherboards to small cards for handheld cameras containing 1500 components, Sony was intent on converting even its most complex designs to lead-free. b. Commencement. Activity started by developing a lead-free solder paste and lead-free reflow profile. The solder selected by Sony is Sn–2.5Ag–0.5Cu–1Bi. Many Japanese OEMs prefer a Bi addition to improve the wetting characteristics of the solder and to slightly lower the melting point. This particular lead-free solder is molten at approximately 222jC. The challenge for Sony was to reach the peak temperature quickly while at the same time maintaining a small temperature delta across the board. Fig. 85 illustrates a typical reflow profile used at Sony for Sn–Pb solder assembly compared to the lead-free solder assembly profile preferred by most manufacturers [48].
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TABLE 17 Categorical List of Products Currently Manufactured at Sony Corporation with LeadFree Solder Assembly Category Car audio Handheld computer except cameras Handheld computer including cameras MD Walkman MD Walkman Digital still camera Digital camcorder Digital camcorder Notebook PC Notebook PC Color television Color television Color television Color television Computer CRT display Color LCD for computer LCD video projector MD system Personal audio system DVD player Video cassette recorder Video cassette recorder AIBO Mobile phone Mobile phone
Lead-free solder
Halogen-free flame retardant
Packaging
XR-CA430X PEG-NR70
PWB-CC PWB-CC
PWB-E PWB-E
NSF NSF
PEG-NR70V
PWB-CC
PWB-E
NSF
MZ-E909 MZ-N1 DSC-P9 DCR-TRV50 DCR-TRV40 PCG-SR9M/K PCG-R505FR/D KV-14DA1 KV-29DS55 KV21DA55 KV-32DX550 CPD-G220 SDM-N51AV VPL-CX4 MDS-JE780 CMT-P555DVD DVP-NS515 SLV-N77 SLV-SE220 ERS-311/312 C413S C1002S
PWB-SC PWB-SC PWB-CC PWB-CC PWB-CC PWB-CC PWB-CC PWB-CC PWB-CC PWB-CC PWB-CC PWB-CC PWB-CC PWB-CC PWB PWB-CC PWB-CC PWB-CC PWB-CC PWB-CC PWB-CC PWB-CC
PWB-E PWB-E PWB-E PWB-E PWB-E PWB-E PWB-E PWB PWB PWB PWB PWB-E PWB-E PWB-E PWB-E PWB-E PWB-E PWB-E PWB-E PWB-E PWB-E PWB-E
NSF NSF NSF NSF NSF NSF NSF NSF RSF NSF RSF NSF NSF NSF NSF NSF NSF NSF NSF NSF NSF NSF
Model
Lead-free solder: PWB-SC—All printed wiring boards and some components; PWB-CC—All printed wiring boards and circuit components; PWB—Main printed wiring board. Halogen-free flame retardants: PWB—Eliminated from printed wiring board; PWB-E—None in printed wiring board or enclosure. Packaging: NSF—No styrene foam; RSF—Recycled styrene foam using limonene. Source: From Ref. 45.
c. Reflow Equipment Issues. The 8-year-old reflow ovens at Sony were not capable of meeting the rigorous demands of the lead-free profile and the environmental requirement of fluxfree emissions. The Kohda facility began a worldwide search to find a supplier to develop such a reflow oven that could meet these demands [48]. The Kohda team evaluated the reflow ovens of numerous manufacturers. The evaluations consisted of furnace loading capability, temperature deltas across assemblies, repeatability, and profile drift. A baseline was established for comparison purposes to determine the potential of each supplier. d. Solution. The criteria employed by the Sony Kohda team are detailed in Table 18. The most important requirement was the ability to maintain a tight process window. In addition, removing flux emissions was a requirement, and the use of filters had been ineffective because the disposal eventually contaminated landfills. Maintenance of these filters also resulted in unaffordable tool down time. Some of the innovations developed by Sony in conjunction with the chosen
Pb-FREE COMPONENT CONVERSION
653
FIG. 84 Representative product examples at Sony Corporation manufactured with lead-free assembly. a) MD walkman, b) color television, c) Playstation 2, d) Network Handicam digital camcorder, e) DVD player, f) mobile phone, g) VAIO-SR notebook personal computer, h) AIBO entertainment robots. (From Ref. 45.)
reflow oven manufacturer were tight gas flow circulation management and a filterless flux removal system with a self-cleaning mode. A high-temperature blower assembly was also developed, as well as a shorter center board support and a reduced length to minimize floor space. The importance of tight gas flow circulation control is that there could exist significant temperature deltas between adjacent furnace heating zones without significant air movement to alter neighboring zone temperatures as occurs in a forced convection oven system. With this, the board could move from a 180jC soak zone to a 290jC ramp zone and then to a 235jC reflow zone. The number of heating zones was increased from the standard three to four zones, to eight or nine shorter zones to improve precise control. Also helping to maintain the tight temperature control was the shorter center board support (CBS) that spanned only the high temperature
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FIG. 85 Reflow soldering profile comparison. a) Typical eutectic Sn–Pb solder profile, b) lead-free solder profile preferred by Japanese manufacturers. (From Ref. 48.)
zones. This is utilized to prevent board warpage but can also block air flow. In reducing the length of the CBS to those zones where PCB warping would occur, there is less obstruction to air flow and less need for special profiling. Fig. 86 illustrates the CBS. Lastly, a condensation/precipitation method was utilized to remove flux from the oven tunnel prior to its cooling, eliminating the need for filtering. The flux is transported to a series of trays where the concentrated flux byproduct runs through a self-clean cycle that operates
TABLE 18 Criteria for Reflow Oven Selection for Lead-Free Solder Assembly Employed at Sony Corporation Criteria . . . . . .
Tight temperature control Very low temperature delta Rapid ramp to meet lead-free profile Flux-free and filter-free operation Minimal maintenance Short machine footprint to conserve floor space
Source: From Ref. 48.
Pb-FREE COMPONENT CONVERSION
655
FIG. 86 Reflow oven with shortened center board support spanning only the high temperature zones. (From Ref. 48.)
automatically during production where the flux is reliquified and captured in collector trays (Fig. 87). The ‘‘self-clean’’ cycle takes 20 min and the collector trays have a capacity to hold the flux that accumulates over approximately 1 year. At that time the trays can be removed and cleaned, resulting in only about 10 min of down time over a 1-year period (Fig. 88) [48]. e. Goal Achieved. As a result of this cooperative effort between the supplier and manufacturer, Sony was able to accomplish its goal of implementing lead-free soldering with flux-free emissions.
E.
Seiko-Epson Lead-Free Soldering for PCBS
Seiko-Epson established a Lead-Free Promotion Committee in June of 1999 to hasten the transition to lead-free equipment. The goal of the committee was to ‘‘gradually reduce the use
FIG. 87 Flux collection system for air reflow including dual internal and external exhausts. (From Ref. 48.)
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FIG. 88 Flux collection trays showing a) flux accumulation after 30 days of processing (56 kg solder paste), b) after 20-min automatic self-cleaning cycle. (From Ref. 48.)
of solder lead in circuit boards and achieve the lead-free goal by the end of the fiscal year 2001’’ [49]. 1. Criteria Seiko-Epson’s criteria for implementation were that the interconnect exhibit characteristics equal or superior to those of the current 63Sn–37Pb alloy utilized. In addition, to utilize to the maximum extent the existing production equipment and technologies already established. Lastly, to develop the lead-free processes in room air conditions. Thermal fatigue performance, soldering performance, and visual inspectability equal to that of eutectic Pb–Sn solder were the front-up approach. It was also a primary consideration that the alloy be nonhazardous and readily available [50]. Seiko-Epson’s approach focused on defining lead-free solutions for the three major soldering processes utilized to assemble electronic units: surface mount reflow soldering, wave soldering, and manual soldering for rework operations. Preliminary investigations narrowed the alloy selection to the following candidates to evaluate: Sn–Ag solder (with Cu, no Bi and with Cu and a small amount of Bi, and with Cu and a larger amount of Bi) as well as Sn–Cu, Sn–Zn, and Sn–Bi solder. Final selections for each soldering method were made mainly on the basis of wetting characteristics and bonding reliability. Based on this experimentation, Seiko-Epson researchers chose the alloys in Fig. 89 for reflow, flow (wave), and rework processing. The optimum production conditions were developed, using Sn–Bi plating for electrical components. By the end of 2000, this process was completed in Japan, and by the end of the following year for the remainder of the world [51]. 2.
Surface Mount Reflow Soldering
a. Wetting. The solder system selected for reflow was Sn–Ag–Cu with a melt temperature of about 220jC using a temperature profile with a peak temperature of 235jC and a dwell time (i.e., time above 220jC) of at least 30 sec in air. Seiko-Epson utilized a test vehicle consisting of a 1.6-mm-thick FR-4 board to which was mounted 208-pin QFP components with a 0.5-mm pitch. Two types of component lead frames were evaluated: Alloy 42 with 90Sn–10Pb plating, and Cu with 98Sn–2Bi plating. The wetting was determined adequate for both the Ob and Pb-free plated leads. b. Solder Joint Characterization. Microstructural analysis confirmed that sound solder joints were achieved. Some Ag3Sn IMC was formed scattered throughout the Sn–Ag–Cu bulk solder. The microstructure did not coarsen when exposed to elevated temperatures. The joint mechanical properties were judged to be very good.
Pb-FREE COMPONENT CONVERSION
657
FIG. 89 Seiko Epson lead-free solder selection for reflow, wave, and manual (repair) soldering. (From Ref. 50.)
Pull strength was evaluated after subjecting parts to thermal cycle conditions consisting of 40jC to 125jC for up to 2000 cycles. It was determined that parts soldered with Sn–Ag–Cu (90Sn–10Pb plated leads) exhibited better pull strength than similar parts reflowed with either 63Sn–37Pb or Sn–Ag–Cu–Bi solders used as a benchmark. Also, it was observed that Sn–Ag–Cu has a much lower tendency to develop cracks during accelerated temperature cycle (ATC) testing than eutectic Sn–Pb as is evident in the cross-section photographs of the solder joints depicted in Fig. 90.
FIG. 90 Cross-sectional photo illustrating leads soldered with eutectic Sn–Pb and Sn–Ag–Cu solder before and after thermal cycle testing (2000 cycles). (From Ref. 50.)
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STALTER ET AL.
c. Which Sn–Ag–Cu Alloy. Seiko-Epson evaluated several Sn–Ag–Cu alloys in comparison to eutectic Sn–Pb as noted in Table 19. All of the compositions evaluated were judged to provide satisfactory wetting using the test vehicle described earlier in this section. In addition, the pull strength of leads bonded with any of the Sn–Ag–Cu compositions evaluated was equivalent or superior to the eutectic Sn–Pb benchmark parts after exposure to ATC testing (i.e., 40jC to 125jC, 2000 cycles). d. Other Factors. The Sn–Ag–Cu alloys are known to exhibit slightly inferior wettability compared to eutectic Sn–Pb. Although a study was conducted to investigate various preheat and peak temperature combinations to determine one that resulted in an optimum front fillet wetting height, all combinations provided reliable solder joints although there was some variation in fillet height. Seiko-Epson also investigated utilizing Sn–Ag–Cu to attach area array packages such as BGAs and CSPs. ATC testing (40jC to 125jC, 30 min/cycle) confirmed that parts attached with Sn–Ag–Cu exhibited more than three times the fatigue life compared to conventional eutectic Sn– Pb solder. e. Conclusion. Based upon all the foregoing, it was concluded that Sn–Ag–Cu alloys were a viable choice over a range of both Cu and Ag composition to assemble Seiko-Epson products. The Sn–Ag–Cu family of alloys was capable of producing adequate solder reflow joints whose properties were equivalent to or better than the benchmark eutectic Sn–Pb solder under a broad variety of processing and lead finish conditions [50]. 3. Wave Soldering The Sn–Cu system was selected for wave soldering, with the eutectic m.p.=227jC, which is about 40jC higher than eutectic Sn–Pb (m.p.=183jC). Although a significant difference in melt temperature exists, Seiko-Epson determined that a wave soldering capability equivalent to eutectic Sn–Pb could be achieved only by raising the bath solder temperature for Sn–Cu by about 10jC, which was typically 240jC to 250jC for eutectic Sn–Pb. To offset the inferior wettability of CuSn relative to eutectic Sn–Pb, Seiko-Epson optimized the post flux by modifying the active agents and increasing the solids content to improve the wettability. Using a solder bath temperature of 250 (F5) jC, a molten solder exposure time of 2 to 5 sec, and the modified post flux, the solder wettability in through holes and component leads was found to be similar to eutectic Sn–Pb [51]. a. Evaluation/Characterization. In evaluating the pull-out strength of pins wave soldered in through holes of a PCB, Sn–Cu soldered pins exhibited a higher pull-out strength initially and after ATC testing (40jC to 125jC) than eutectic Sn–Pb. Large cracks were observed in the eutectic Sn–Pb fillets after ATC testing, but only very slight cracks were observed in the case of the Sn–Cu fillets as shown in Figs. 91 and 92. Pins of large and heavy components or connectors soldered in through holes are a solder creep concern. Creep is a gradual plastic deformation process that takes place over time due to an applied load. As indicated in Fig. 93, both Sn–Ag–Cu and Sn–Cu exhibited vastly superior results in a standard creep test at both 125jC and 150jC compared to eutectic Sn–Pb. Thus both these lead-free solders are adequate for bonding relatively large and heavy components.
TABLE 19
Lead-Free Solders Under Evaluation at Seiko-Epson for Reflow Soldering Alloy composition
Sn–Ag–Cu (type A) Sn–Ag–Cu (type B) 63Sn–37Pb solder Source: From Ref. 50.
Sn
Ag
Cu
Pb
Remaining portion Remaining portion
3 to 3.8 wt.%
0.5 to 1.2 wt.%
0.1 wt.% or less 37 wt.%
Pb-FREE COMPONENT CONVERSION
659
FIG. 91 Cross-sectional photo illustrating posts soldered with eutectic Sn–Pb and Sn–Ag–Cu solder before and after thermal cycle testing (2000 cycles). (From Ref. 50.)
b. Fillet Lifting Phenomena. One of the key concerns with the use of lead-free alloys for wave soldering applications is associated with a phenomenon referred to as ‘‘fillet lifting’’ discussed earlier in studies conducted by Panasonic (Section 4.6.2). It is the partial separation of the soldered area from the land of a PCB through hole immediately after wave soldering. It does occur with lead-free solders, including Sn–Cu as shown in Fig. 94. There is no known solution to prevent the phenomenon [51]. c. Bond Strength. Seiko-Epson conducted testing on double-sided PCBs with components attached using both Cu–Sn and eutectic Sn–Pb wave soldering. Although fillet lifting is certainly an undesirable feature, it is interesting that the pull strength of through-hole joints was at approximately the same strength level for both solders, although fillet lifting was observed in the case of the Sn–Cu joints, but not the eutectic Sn–Pb joints. This was true for joints evaluated both before and after ATC testing (40jC to 125jC, 2000 cycles) [51].
FIG. 92 Cross-sectional photos illustrating enlargements of cracked soldered area after thermal cycle testing (2000 cycles). (From Ref. 50.)
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STALTER ET AL.
FIG. 93 Creep characteristics of eutectic Sn–Pb solder compared to lead-free solder alloys at 150jC. (From Ref. 50.)
d. Electrical Characteristics. Although the bond strength appears adequate even in cases with fillet lifting, it was not immediately obvious that the electrical characteristics of these joints were sufficient and remained so. However, Seiko-Epson, under the same conditions discussed in the previous section, confirmed that the solder joint resistance values remained at about the same value in Sn–Cu joints as the conventional eutectic Sn–Pb joints. e. Conclusions. Based on the testing Seiko-Epson conducted, they adapted Sn–Cu as their lead-free wave solder material for volume manufacturing [51]. 4. Manual (Repair) Soldering Sn–Ag–Cu was selected by Seiko-Epson as the lead-free solder of choice for rework applications, the same as used for surface mount reflow operations. Unlike eutectic Sn–Pb, solder spreading on Cu land areas was found not to vary much, independent of the soldering iron tip temperatures. However, at tip temperatures of 350jC or below, the alloy is difficult to melt. The optimum tip temperature was found to be approximately 365jC to 375jC. At 380jC and above, flux charring and land separation from the PCB is observed [51].
FIG. 94 Fillet lifting on pins post a wave solder operation utilizing Sn–Cu. (From Ref. 50.)
Pb-FREE COMPONENT CONVERSION
661
a. Need for Quick Repairs. Even with a tip temperature at about 370jC, which is desirable from a workability standpoint, repair operations must be carried out quickly to avoid damage to the PCB lands. For example, component and bond strength with joints created using a 370jC tip temperature is optimum with a soldering time of about 3 sec, but decreases rapidly thereafter. The tendency to create thermal-induced damage or peeling of PCB land features follows the same trend. When manual soldering is performed using Sn–Ag–Cu solder at a suitable temperature and soldering duration, the soldering characteristics are very similar to eutectic Sn– Pb as noted in Fig. 95 [51]. b. Effect of Mixed Technologies. A key concern to Seiko-Epson was the effect of a hybrid system, i.e., mixed technologies. That is, what is the impact, if any, on the pull strength where a lead-free solder in a joint becomes mixed with solder containing lead (Pb). An evaluation was conducted addressing the issues from several perspectives. It was determined, as depicted in Fig. 96, that the pull strength of QFP leads remained relatively unaffected when various solders were used to repair a soldered component originally mounted with lead-free solder, Sn–Ag–Cu (either type A or B). The reverse was also true, that the pull strength was relatively unaffected when a lead-free solder was used to repair QFPs originally mounted with eutectic Sn–Pb. It was therefore concluded at Seiko-Epson that no problems would result by utilizing lead-free Sn–Ag–Cu for their solder repair operations independent of whether a SMT component was attached with eutectic Sn–Pb or Sn–Ag–Cu [51]. 5. Lead-Free Status at Seiko-Epson Seiko-Epson has taken action to make in-house processes (including overseas manufacturing affiliates and subcontractors) lead-free, make purchased components lead-free, and implement procedures to obtain approval from customers to switch custom products to lead-free manufacturing. As of January 2002, the solder used in in-house production at Seiko-Epson was 70.8% lead-free [51]. (Not included in that list of products are products that are exempt; products that
FIG. 95 Manual soldering of QFP utilizing Sn–Ag–Cu and eutectic Sn–Pb solder on Sn–10Pb-plated leads. (From Ref. 50.)
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FIG. 96 Bond strength comparison for QFP initially bonded with Sn–Ag–Cu (type A), Sn–Ag–Cu (type B), and eutectic Sn–Pb solder, in the no-repair and repaired condition. (From Ref. 50.)
ceased production before FY2001, and their repair parts; products for which Seiko-Epson has been able to get permission of the customer to switch to lead-free materials.) In April of 2002, Seiko-Epson stated that 98.6% of the solders used in in-house manufacturing processes were lead-free and that 40% of the total number of purchased parts, under this program, were lead-free [50]. a. Source of Supply. As with most major manufacturers, Epson procures the majority of its electronic components from other suppliers, including PCBs. To facilitate the logistics of insuring that its supplier’s parts were lead-free, Seiko-Epson set up a database compiling the leadfree status of over 60,000 parts from over 300 manufacturers, and made it available in both English and Japanese. This database is used worldwide by the Epson Group of companies. [50] b. Custom Products. Seiko-Epson’s business is also greatly composed of made-to-order semiconductors and liquid crystal displays. Permission is therefore required to convert these products to lead-free. Seiko-Epson has approached approximately 6000 of its customers with data and samples, but this process has taken longer than expected. Conversion of these products will take place on a separate schedule in line with the requirements of each customer. [50]
V.
SUMMARY
This chapter offers just a few of the many examples of manufacturers that are well underway in the conversion to lead-free electronics and has highlighted some of the challenges they encountered along the way. There has been substantial progress in both technology and acceptance of the reality of the lead-free movement. It has been over a decade since its inception,
Pb-FREE COMPONENT CONVERSION
663
and manufacturers and their suppliers must be prepared to support customers globally, in response to legislation or ‘‘green marketing’’ influences. The few examples demonstrate, however, that the database surrounding lead-free solders is growing, and that the momentum has shifted from a technology issue to understanding the manufacturing implications that are driven by the conversion to lead-free components and processing. NEMI has demonstrated that manufacturing in most cases can be implemented without major changes to production tools and equipment, and produces reliable solder joints. However, as these examples illustrate, the conversion still requires a significant effort on the part of manufacturers to produce reliable, cost-effective products in high volume. The examples also illustrate that the task is achievable.
ACKNOWLEDGMENTS Authors Tom Baggio and Kenichiro Suetsugu would like to thank the following Panasonic members for their contributions to this work: S. Hibino, A. Furusawa, and T. Ikari of Environmental Production Engineering Laboratory, Kadoma City, Osaka Japan; E. Abe, H. Saitoh, M. Ojima, Y. Hayasa, and Y. Takaku of the AVC TV Products Division, Utsunomiya, Japan; H. Kitahara, S. Kumamoto, and M. Aihara of Harima Chemicals, Inc., Kakogowa, Japan.
REFERENCES 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20.
Seelig, Karl; Suraski, David. A study of lead-contamination in lead-free electronics and its impact on reliability. Proc. SMTA International Chicago, IL; Sept 22–26, 2002. Judd, Mike; Brindley, Keith. Soldering in Electronics Assembly—Second Edition; ButterworthHeinermann: Oxford, 1999. Suetsugu, K. Development of flow and reflow soldering technology for lead-free solder. Proc. of Jisso/Protec Forum; Japan; November 2002; 163 pp. MEI, Environmental Sustainability Report (Covering FY2001), June 2002, 28 pp. Baggio, T. Case studies of lead-free technology implemented in Panasonic electronic products. Proc. Nepcon West, TS-13; March 2000, 5 pp. Suetsugu, K. Advanced applications of lead-free soldering by identifying lift-off mechanism. Proc. 10th Micro Electronics Symposium, Japan; 214 pp. Suetsugu, K. Advanced applications of lead-free soldering by identifying lift-off mechanism. Proc. 10th Micro Electronics Symposium; Japan, 2000; 215 pp. Suetsugu, K. Development of flow and reflow soldering technology for lead-free solder. Proc. of Jisso/Protec Forum; Japan, November 2002; 159 pp. Suetsugu, K. Development of flow and reflow soldering technology for lead-free solder. Proc. of Jisso/Protec Forum, Japan, November 2002; 155 pp. Suetsugu, K. Development of flow and reflow soldering technology for lead-free solder. Proc. of Jisso/Protec Forum, Japan, November 2002; 156 pp. Suetsugu, K. Development of flow and reflow soldering technology for lead-free solder. Proc. of Jisso/Protec Forum, Japan, November 2002; 158 pp. Suetsugu, K. Development of flow and reflow soldering technology for lead-free solder. Proc. of Jisso/Protec Forum, Japan, November 2002; 162 pp. Baggio, T. The Panasonic mini disk player, turning a new leaf in a lead-free market. Proc. IPC Works ’99, October 1999; pS-05-4, 4 pp. MEI, Environmental Sustainability Report (Covering FY 2001), June 2002; 28 pp. Baggio, T. The Panasonic mini disk player, turning a new leaf in a lead-free market. Proc. IPC Works ’99, October 1999; pp. pS-05-4, 4 pp. Baggio, T.; Suetsugu, K. Guidelines for lead-free processing. SMT Magazine, September 1999; 64 pp. Baggio, T.; Suetsugu, K. Guidelines for lead-free processing. SMT Magazine, September 1999; 62 pp. Baggio, T. Case studies of lead-free technology implemented in Panasonic electronic products. Proc. Nepcon West, March 2000; TS-13 8 pp. Baggio, T.; Suetsugu, K.; Okumura, T. Challenges and solutions for lead-free soldering of large PCB assemblies. Proc. IPC Apex, P-MT3-1, March 2000; 2 pp. Baggio, T. Case studies of lead-free technology implemented in Panasonic electronic products. Proc. Nepcon West, TS-13, March 2000; 10 pp.
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Baggio, T. Case studies of lead-free technology implemented in Panasonic electronic products. Proc. Nepcon West, TS-13, March 2000; 11 pp. 22. Baggio, T. Case studies of lead-free technology implemented in Panasonic electronic products. Proc. Nepcon West, TS-13, March 2000; 12 pp. 23. Suetsugu, K. Development of flow and reflow soldering technology for lead-free soldering. Proc. Jisso/Protec Forum, Japan, November 2002; 160 pp. 24. Baggio, T.; Suetsugu, K.; Okumura, T. Challenges and solutions for lead-free soldering of large PCB assemblies. Proc. IPC Apex, P-MT3-1, March 2000; 4–5. 25. Baggio, T. Case studies of lead-free technology implemented in Panasonic electronic products. Proc. Nepcon West, TS-13, March 2000; 14 pp. 26. Baggio, T. Case studies of lead-free technology implemented in Panasonic electronic products. Proc. Nepcon West, TS-13, March 2000; 13 pp. 27. Suetsugu, K. Advanced applications of lead-free solder by identifying lift-off mechanism. Proc. 10th Micro Electronics Symposium, Japan, 2000; 214 pp. 28. Suetsugu, K. Advanced applications of lead-free solder by identifying lift-off mechanism. Proc. 10th Micro Electronics Symposium, Japan, 2000; 215 pp. 29. Suetsugu, K. Advanced applications of lead-free solder by identifying lift-off mechanism. Proc. 10th Micro Electronics Symposium, Japan, 2000; 216 pp. 30. Suetsugu, K. Development of flow and reflow soldering technology for lead-free soldering. Proc. Jisso/Protec Forum, Japan, November 2002; 156 pp. 31. Suetsugu, K. Development of flow and reflow soldering technology for lead-free soldering. Proc. Jisso/Protec Forum, Japan, November 2002; 158 pp. 32. Baggio, T. The Panasonic mini disk player, turning a new leaf in a lead-free market. Proc. IPC Works ’99, October 1999; pS-05-4, 7 pp. 33. Yi, Sammy; Geiger, David; Wang, Mei; Singh, Haprpuneet; Lee, Alan; Wong, Harris A case study of lead-free assembly implementation in EMS environment. Proc. SMTA Lead Free Symposium, Boston, MA, June 2000. 34. Flextronics Press Release, Singapore, Nov. 15, 2002. 35. Wang, M.; Nakajima, K.; Lewis, A.; Kurwa, M.; Bhat, R.; Yi, S. Solder paste printing optimization for CSP. Proc. SMTA International; San Jose, CA, September 1999. 36. Wong, Stephen; Nester, Myron. High Volume Lead Free Production, CMAP Lead Free Workshop, Toronto, Canada, May 22, 2002. 37. Visteon press release, Dearborn, MI: Dec. 18, 2000. 38. Master, Raj, et al. Ceramic column grid array for flip chip applications. Proc. 45th Electrical Components and Technology Conference; IEEE: Las Vegas, NV, 1995; 925–929 pp. 39. Ray, Sudipta, et al. Ceramic column grid array for a high performance workstation application. Proc. 47th Electrical Components and Technology Conference; IEEE: San Jose, CA, 1997; 319–324. 40. Ray, Sudipta, et al. CLASP ceramic column grid array technology for ceramic chip carriers. Proc. Semicon West, San Jose, CA, July 1999. 41. Interrante, Mario, et al. Lead-free package interconnection for ceramic grid arrays. Proc. Semicon West, San Jose, CA, July 2003. 42. O’Connor, Daniel, et al. Electrical modeling and characterization of packaging solutions utilizing lead-free second-level interconnects. Proc. of the 53rd Electrical Components and Technology Conference, New Orleans, LA, May 2003. 43. Interrante, Mario; et al. High Density Column Grid Array Connections and Method Thereof, U.S. Patent 6,429,388, 2002. 44. J-STD-020B, Moisture/Reflow Sensitivity Classification for Non-hermetic Solid State Surface Mount Devices. IPC/JEDEC, July 2002. 45. Sony Corporation, Environmentally Conscious Products and Services, Social and Environmental Report, 2002. 46. Sony Corporation, http://www.sony.net/SonyInfo/Environment/environment/communication/ report/2002/index.html. 47. Sony Corporation. Sony semiconductor’s environmental efforts—towards a circulatory society. Sony CX-News, Feb. 2003; 29. 48. Kikuchi, Atsushi. The Greening of the Reflow Process, Through Partnership, http://www.sehouk. com/Sony_article.doc, 1/2/2002. 49. Seiko Epson Corporation. Epson declares solders 98.6% lead free*. Epson Environmental Newsline, Dec. 2002. 50. Seiko Epson, The Road to Lead-Free Soldering (for PCB mounting), http://www.eea.epson.com/ aboutEEA/PCBMounting.pdf. 51. Press Release, Seiko Epson Announces Lead-Free Status of Products, March 11, 2002.
17 Major International Lead (Pb)-Free Solder Studies Carol A. Handwerker and Frank W. Gayle National Institute of Standards and Technology, Gaithersburg, Maryland, U.S.A.
Erik E. de Kluizenaar Philips CFT, Eindhoven, The Netherlands
Katsuaki Suganuma Osaka University, Osaka, Japan
I. INTRODUCTION Beginning in 1991, the microelectronics community worldwide became increasingly aware of the possibility of being required, by law, by tax, or by market pressure, to replace tin–lead eutectic solders in electronic assemblies. Over the next 10 years that followed, separate groups formed in the United States, Europe, and Japan to examine solder-based alternatives to tin–lead eutectic solder and to understand the implications of such a change before it becomes necessary. Lead-free solder research projects from industrial, academic, and national laboratory groups are described in the Lead Free Soldering report sponsored by the UK Department of Trade and Industry [1]. The time line for comprehensive national or regional studies, shown in Figure 1, illustrates the long-term commitment to develop lead-free solder assemblies. The following studies are featured in this chapter: the National Center for Manufacturing Sciences (NCMS) Lead-Free Solder Project and the NCMS High-Temperature Fatigue-Resistant Solder Project from the United States, the Japan Institute of Electronics Packaging (JIEP) and Japan Electronic Industry Association (JEIDA) projects from Japan, and the IDEALS Lead-Free Solder Project from the European Union (EU). Based on these studies, the microelectronics community gained sufficient experience with the performance of lead-free solders to begin addressing lead-free assembly to assess lead-free issues, including manufacturing yield, process windows for complex boards, and component survivability. Results from these five studies are compared with subsequent data obtained by Motorola and IBM. Progress on more recent national and/or industrial sector groups investigating lead-free solders, such as the National Electronics Manufacturing Initiative (NEMI) Lead-Free Task Force and the High Density Packaging Users Group (HDPUG) is also outlined. Updates and information obtained by these groups can be found at http://www.nemi.org, http://www.leadfree.org, and http://www.lead-free.org. In addition to these studies, which focused on implementation issues, primarily with respect to manufacturing and reliability, other studies yielded materials property data for lead-free solders that give insight into phase transformations, solderability, and thermomechanical fatigue (TMF) resistance. For example, over 20 universities in the United States, Canada, and the
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FIG. 1 Timeline of several lead-free solder studies.
European Union have conducted lead-free solder research programs supported by their national science foundations, companies, and national laboratories. Since 1982, the International Tin Research Institute (ITRI), now known as Soldertec, has performed research on lead-free solders, beginning with plumbing solders. Information on the Soldertec data can be found on at the website http://www.lead-free.org.
II. NATIONAL CENTER FOR MANUFACTURING SCIENCES (NCMS) PROJECT A. Project Organization and Participants From 1992 to 1996, the National Center for Manufacturing Sciences (NCMS), a not-for-profit cooperative research consortium of more than 200 North American manufacturers, national laboratories, and universities, carried out a multiyear effort to develop Pb-free alternatives to Pbbased solders used for electronics assembly [2]. The proposed Reid bill, banning or taxing the use of lead in electronics, sensitized the microelectronics industry to the possible need to remove Pb from solders, and led to the formation of this project. The total cost of the research project was $10.6 million, with approximately $1 million coming from Department of Defense funds and the balance from in-kind contributions. Participating organizations and primary technical contacts are presented in Table 1.
B. Project Objectives The goal of the NCMS project was to determine whether safe, reliable, nontoxic, and costeffective substitutes exist for lead-bearing solders in electronics manufacturing. The scope of the project was based on the following premise: the production of durable, reliable, safe, and affordable electronic products with lead-free solders will require the manufacturer to understand material properties, manufacturing processes and equipment, toxicological effects, alloy cost, long-term availability, and reliability.
C. Down-Selection Process Comprehensive manufacturing assessments and thermal cycling stress tests could only be performed on a limited number of candidate lead-free alloys: seven alloys plus Sn–Pb eutectic control alloy. The Project’s initial list of over 70 candidate alloys was quickly reduced by: (1) eliminating candidates containing toxic elements, (2) eliminating all but one of a family of
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TABLE 1 Participating Organizations and Primary Technical Contacts in the National Center for Manufacturing Sciences Project on Lead-Free Solders Participating organizations AT&T/Lucent Technologies (Lucent) Electronics Manufacturing Productivity Facility (EMPF) Ford Motor Company (Ford) General Motors–Delco Electronics (GM–Delco) General Motors–Hughes Aircraft (GM–Hughes) Hamilton Standard, Division of United Technologies Corporation (Hamilton) National Center for Manufacturing Sciences (NCMS) National Institute of Standards and Technology (NIST) Rensselaer Polytechnic Institute (RPI) Rockwell International Corporation (Rockwell) Sandia National Laboratories (Sandia) Texas Instruments Incorporated (TI)
Primary technical contacts Iris Artaki and Donna Noctor John Greaves Tsung-Yu Pan and Howard Blair Gordon Whitten and Yun Zhu Jerald Rosser Charles Desantis and Willie Desaulnier Duane Napp Carol Handwerker and Leonard Smith Lawrence Felton and Mark Palmer John Mather and Scott Schroeder Paul Vianco and Darrel Frear Joe Felty
candidates having very minor composition differences, (3) eliminating candidates falling outside certain manufacturing, reliability, and economics/availability criteria established by project participants, and (4) applying judgment criteria set forth in a weighted decision matrix for those alloys that passed the first three screenings. The process from the initial listing of alloys through assessing reliability is shown schematically in Figure 2. 1. Toxicology Cadmium is clearly toxic in many forms and is severely restricted in Europe and was, therefore, eliminated as a potential alloying element. The data on all other elements was incomplete, and
FIG. 2 Diagram of the NCMS lead-free solder project alloy down-selection process.
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sometimes contradictory. Given the uncertainty in the toxicology of other possible alloying elements, no other elements were eliminated. The elements remaining for consideration were Sn, Ag, Bi, In, Cu, Sb (as a minor constituent), and Zn. Small additions (<1%) of other common elements were also not believed to pose a risk to environmental or occupational health. 2. Economics and Availability To ensure that an adequate worldwide supply of a potential alloying element exists, and that the cost of an alloy containing a particular element does not exceed $10.00/lb ($22/kg), it was determined that a potential lead-free solder alloy should contain less than 1.5% In or 20% Bi. Although eutectic Sn–58Bi violates this guideline, it was retained as a baseline alloy. The material cost increase alone associated with conversion to one of the remaining lead-free alloys was estimated to be $140–900 million per year, depending on the alloy composition. The cost of Pbfree solder paste not containing In is expected to increase on the order of 5% over eutectic Sn–Pb because the cost of the metal is a small part of the cost of solder paste. On the other hand, the cost of bar stock for wave soldering is expected to be a strong function of composition. 3. Manufacturing- and Reliability-Related Materials Properties a. Critical Criteria. Three different application storage and operating temperature ranges were important to the project participants: telecommunication/consumer electronics: 55 to 100jC; military: 55 to 125jC; and aerospace/automotive: 55 to 180jC. This led to an upper limit of 225jC for the solder liquidus temperature, and a maximum allowable pasty range was set at 30jC, where the pasty range is the difference between the solidus and liquidus temperatures. From these storage and operating temperature ranges and typical assembly process temperatures, material property limits were established for candidate solder alloys. The critical properties for lead-free solders are high electrical and thermal conductivity, good solderability, melting behavior compatible with existing assemblies; and mechanical properties, including thermomechanical fatigue resistance equivalent to or better than eutectic Sn–Pb. Tin-based solders present no electrical or thermal conductivity problems. Solderability is a property that involves not only the solder, but also the flux, the substrate, the pad and lead materials, the reaction time, and the temperature at which soldering is performed. Melting behavior and mechanical properties are much more complicated properties to assess, not specified by a single parameter. Critical pass–fail, down-selection criteria were established based on liquidus temperature, pasty range (the difference between liquidus and solidus temperatures), wettability, and mechanical properties, as shown in Table 2. The pass–fail criteria (right column) were used to reduce the number of candidate alloys, so it was not necessary to consider the area-of-coverage, drossing, elongation, and creep properties in the final quantitative down-selection process. b. Melting Behavior. The melting behavior was the primary solder property used to select solders for the time- and labor-intensive thermomechanical fatigue studies. The three melting characteristics of lead-free solders used to evaluate their suitability as a replacement for lead-free solders are the liquidus temperature, the temperature above which all solder has melted, the solidus temperature, the temperature below which all solder is solid, and the pasty range. For eutectics, the liquidus and the solidus temperatures are the same, and the pasty range is 0jC. The acceptance criteria of a liquidus temperature less than 225jC and the pasty range less than 30jC are illustrated by using the Sn–Ag–Bi phase diagram in Figure 3. The shaded regions indicate where the pasty range is <30jC, which are close to the binary and ternary eutectic compositions. The limit of 225jC for the liquidus temperature further restricts the range of compositions. This implies that down-selected compositions will be close to pure Sn, or to binary, or ternary eutectic compositions. c. Liquidus Temperature Determination. For tin-rich solders, a simple linear equation can be used to estimate the change in liquidus temperature with composition for additions of Ag, Bi, Cu, Ga, In, Pb, Sb, and Zn to Sn. For Ag, Bi, Cu, and Pb, the coefficients were derived from the slopes of the Sn–X (X=Ag, Bi, Cu, Pb) binary phase diagram line depicting liquidus temperature as a function of compositions for the Sn-rich liquidus, for In and Sb from the binary Sn–Y ( Y=In, Sb) peritectics, and for Zn and Ga from the extrapolations of the Sn-rich liquidus for
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Pass/Fail Alloy Down-Selection Criteria
Solder property Liquidus temperature Pasty range
Wettability
Area of coverage Drossing
Thermomechanical fatigue (TMF-1)
Coefficient of thermal expansion (CTE)
Creep Elongation
Definition
Acceptable levels
Temperature at which solder alloy is completely molten. Temperature difference between solidus and liquidus temperatures. Represents the temperature range where the alloy is part solid and part liquid. A wetting balance test assesses the force resulting when a copper wire is immersed in and wetted by a molten solder bath. A large force indicates good wetting, as does a short time to attain a wetting force of zero and a short time to attain a value of two-thirds of the maximum wetting force. Assesses the coverage of the solder on Cu after a typical dip test. Assesses the amount of oxide formed in air on the surface of molten solder after a fixed time at the soldering temperature. Cycles-to-failure for a given percent failed of a test population based on a specific solderjoint and board configuration, as compared to eutectic Sn/Pb. Thermal expansion coefficient of the solder alloy is the fraction change of length per jC temperature change. Value used for comparison was CTE of solder alloy at room temperature. Stress required at room temperature to cause failure in 10,000 min Total percent elongation of material under uniaxial tension at room temperature.
<225jC <30jC
Fmax > 300 AN, t0<0.6 sec, t2/3<1 sec
>85% coverage Qualitative scale
Some percentage, usually >50% <2.9105/jC
>3.4 MPa > >10%
dilute Sn–Zn and Sn–Ga alloys. The change in the liquidius temperature as a function of composition can be estimated as: TL ¼ 232jC 3:1*WAg 1:6*WBi 7:9*WCu 3:5*WGa 1:9*WIn 1:3*WPb þ 2:7*WSb 5:5*WZn
ð1Þ
where the coefficients are in units of jC, and WX is the amount of element X in mass fraction*100. Table 3 lists the composition limits over which this equation applies. Accordingly, the maximum decrease from the melting point of pure Sn with additions of Ag and Cu is 15–16jC, in agreement with the measured ternary eutectic temperature in the Sn–Ag– Cu system of 217jC. From Eq. (1), many alloy compositions with Bi, In, and Zn additions can be identified with liquidus temperatures of 183jC, the eutectic temperature of Sn–Pb eutectic solder, as listed in Table 4. The problem with most of these alloys is that their solidus temperatures are significantly lower than 183jC. For Sn-based solders, the binary eutectics are Sn–58Bi (Tm=139jC), Sn–3.5Ag (Tm=221jC), Sn–0.7Cu (Tm=227jC), Sn–In (Tm=120jC), and Sn– 9Zn (Tm=199jC). For example, when the bismuth concentration is greater than 20% mass fraction, the solidus temperature is approximately 139jC. In addition, alloys with a low pasty
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FIG. 3 Sn–Ag–Bi phase diagram that shows the projection of the liquidus temperature surface. The hatched regions represent compositions with <30jC pasty range.
TABLE 3 Limits of Eq. (1) for Calculation of Liquidus Temperature for Sn-Based Solder Compositions where Compositions are Given in Mass Fraction (100) Tin-based compositions (liquidus calculation, mass fraction 100) Element
Wt.%
Ag Bi Cu Ga In Pb Sb Zn
<3.5 <43 <0.7 <20 <25 <38 <6.7 <6
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TABLE 4 Liquidus Temperature, TL (jC), and Solidus Temperature, TS (jC), as a Function of Composition. The Compositions are in Mass Fraction 100, with the Remainder Sn Elemental compositions, mass fraction % Ag 3.5 3.5 3.5
3.5 3.5 3.5 3.5
Bi 5 20 30 10 9 9
Cu
Ga
In
Temperature (jC) Pb
Sb
Zn
Solidus
Liquidus
6
216 139 139 139 139
216 208 184 184 183 182 183 184 183 183 183 183
0.7 0.7 0.7
0.7 0.7 0.7
10 20
117
5 25
182
14 26 3.5
0.7
6
199
range are preferred. As described in Section II.D.1.a, an alloy with a large pasty range can have defects generated during assembly, particularly, fillet lifting in plated-through-hole joints. d. Nonequilibrium Effects. Furthermore, it should be noted that the pasty ranges based on equilibrium phase diagrams are the minimum pasty ranges that can occur during solidification. In systems that exhibit substantial changes in the solubility of solid Sn during cooling, the amount of liquid present during cooling can be greater than predicted from the equilibrium phase diagram. Systems that exhibit this effect include Sn/Bi, Sn/In, and Sn–Pb. This effect is illustrated in Figure 4 for the Sn/Ag/Bi system with graphs depicting the solid fraction as function of temperature and composition based on the phase diagram ‘‘lever rule’’ and nonequilibrium solidification. For example, considering the composition Sn–3.5Ag–7.5Bi, the last liquid
FIG. 4 The calculated mass fraction that is solid as a function of temperature during cooling from the liquidus temperature. (a) Calculation based on the lever rule. (b) Calculation based on the Scheil assumption of no diffusion in the solid to re-equilibrate the solid composition during cooling. This lack of diffusion in solid leads to a significant fraction of eutectic for low Bi alloys.
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solidifies at 185jC based on the equilibrium phase diagram; however, as a result of segregation during solidification, some liquid is predicted to still be present until the ternary eutectic temperature is attained at 138jC. The amount of nonequilibrium liquid present depends on the cooling conditions and will be between the limits defined by the two curves for Sn–3.5Ag– 7.5Bi in Figure 4a and b. These nonequilibrium effects result in a larger effective pasty range than predicted from equilibrium phase diagrams. For a Sn/Bi solder with 6% Bi, the liquidus temperature is approximately 224jC and the equilibrium pasty range is approximately 26jC; however, the effective pasty range was determined to be on the order of 85jC as measured by differential thermal analysis (DTA) experiments. The maximum acceptable Bi concentration was set at 5%, the composition at which no liquid was detected at 139jC. Likewise with the Sn– 2.8Ag–20In alloy, the equilibrium pasty range is estimated to be approximately 26jC with a liquidus temperature of 183jC and a solidus temperature of 157jC; however, a measurable fraction of ternary eutectic at 117jC has been detected in this alloy by DTA [3]. In the downselection process, the equilibrium pasty range was utilized with the exception of the Sn–2.8Ag– 20In alloy for which the effective pasty range was utilized. e. Drossing. A drossing test was initially included because some Zn-containing alloys showed considerable oxidation during the wetting balance test. These data were excluded from the final decision matrix because: (1) the test was qualitative, (2) the effect of severe drossing could be seen quantitatively as a loss of wettability in the wetting balance test, and (3) severe drossing was only seen for alloys with Zn concentrations greater than 1%. f. Accelerated Thermal Cycle Testing. The mechanical property data was included as part of the quantitative down-selection process based on a thermomechanical fatigue (TMF) test; the test vehicle consisted of a 44I/O leadless ceramic chip carrier (LCCCs-44) with only corner leads soldered to provide conditions for high stress. Test parts were thermally cycled between 55 and +125jC at the rate of 24 cycles per day. The TMF data was expressed as the number of cycles-tofailure for an alloy expressed as a percentage of the cycles-to-failure for eutectic Sn–Pb solder. 4. Down-Selected Alloys for Evaluation The properties of 10 lead-free alloys passing these pass–fail tests were compared with those of eutectic Sn–Pb by using a quantitative decision matrix, which included liquidus temperature, pasty range, wettability, and thermomechanical fatigue resistance. As a result of the downselection process and other deliberations, seven alloys (plus the baseline eutectic Sn–Pb) of the original 79 alloys were identified for full-scale manufacturing and reliability assessments; the alloys compositions and liquidus temperatures are listed in Table 5.
TABLE 5 NCMS Alloys Selected for Manufacturing and Reliability Trials: Compositions, Liquidus Temperatures, and Reasons for Selection Code
Solder compositions
Liquidus temperature (jC)
A1 A4 A6 E4 F2 F17
Sn–37Pb Sn–3.5Ag Sn–58Bi Sn–3Ag–2Bi Sn–2.6Ag–0.8Cu–0.5Sb Sn–4.8Bi–3.4Ag
183 221 139 220 211 210
F21
Sn–20In–2.8Ag 7
187
F27
Sn–3.5Ag–1Zn–0.5Cu
212
Reason for selection Benchmark Benchmark Low melting point alloy Alloy in Sn primary phase field Castink alloy—commercial Sn-rich alloy Sn–Ag–Bi alloy with maximum Bi concentration Commercial alloy with equilibrium liquidus at 183jC; nonequilibrium 117jC ternary eutectic Sn–Ag–Cu alloy with Zn addition
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The Sn–Ag eutectic was included as a baseline alloy similar to eutectic Sn–Pb, but was also a candidate alloy. The Sn–Bi eutectic was included as a baseline alloy and a candidate alloy although it failed the availability pass/fail criterion. Project participants were concerned that all other lead-free candidate alloys had liquidus temperatures in excess of 210jC, too high for some assemblies manufactured at that time. The Sn–Bi eutectic represented a low melting point, In-free alloy. The alloy Sn–3Ag–2Bi is in the Sn primary phase field in the Sn–Ag–Bi phase diagram, while Sn–3.4Ag–4.8Bi is in the Ag3Sn primary phase field, the first phase to form at equilibrium. It was expected that the microstructures and properties of these two alloys would be measurably different from each other. The alloy Sn–2.6Ag–0.8Cu–0.5Sb is a commercial alloy, available in both paste and bar stock, and was used to represent the Sn–Ag–Cu family of alloys, and for comparison with Sn–3.5Ag and Sn–3.5Ag–0.5Cu–1Zn. The alloy Sn–2.8Ag–20In is also a commercial alloy. This alloy failed the pass/fail down-selection criteria for cost, availability, and pasty range (as a result of an experimentally observed large nonequilibrium pasty range). However, it was included for testing because the liquidus temperature is close to eutectic Sn–Pb, and it was necessary to include one alloy that failed the physical properties down-selection criteria in order to test the ability of those criteria to discriminate among solder alloys.
D. Manufacturing Trials Two manufacturing assessments were performed by using the NCMS Soldering Test Vehicle (STV), a printed wiring board (PWB) having both surface mount and through-hole (TH) components. This was a pass–fail assembly test for identifying alloys that were not manufacturable, i.e., could not be assembled with a reasonable yield using normal electronics assembly operations (e.g., stencil printing, solder reflow, wave soldering, etc.). The eutectic Sn–Pb alloy was included as a baseline for comparison in these evaluations as well. 1. Initial Assessment The primary result of the first manufacturing assessment of the seven lead-free alloys was that all solders exhibited acceptable manufacturability, using standard industrial practices and the infrastructure in place for eutectic Sn–Pb. For example, the solder joints of all Pb-free alloys showed adequate surface mount (SM) fillets and bottom side through-hole (TH) fillets but poor top side TH filling. No alloys were eliminated based on manufacturing performance, although the process window for lead-free alloys was found to be narrower compared to eutectic Sn–Pb. For example, careful temperature profiling was necessary to avoid reflow of the top side SM joints during wave soldering. a. Fillet Lifting. Of particular concern was the occurrence of ‘‘fillet lifting,’’ the complete or partial separation of a solder joint fillet from the intermetallic compound on the land side, but remained intact along the barrel. This was considered to be a catastrophic mechanical failure of the fillet by most project participants, although it did not result in immediate electrical failure of joints. This phenomenon was first identified in 1993 by Vincent and coworkers in the Department of Trade and Industry (DTI) sponsored Pb-free solder project, which attributed fillet lifting to the presence of the Sn–Bi–Pb ternary eutectic (98jC) due to Pb contamination of Bicontaining solders from the Sn–Pb HASL board finish [4–7]. This effect is now known to occur without Pb contamination, even in simple alloys such as Sn–3.5Ag. During manufacturing trials of through-hole joints, it was observed that separation frequently occurred along the interface between the Sn/Ag eutectic solder and intermetallic compound layer on the land when an assembly was cooled from the wave soldering temperature to room temperature (Figure 5). The solder appeared to separate cleanly from the intermetallic compound layer extending from the land edge to the knee of the plated barrel, similar to the prior DTI study, with the shape of the solder fracture surface replicating the shape of the intermetallic compound layer. Extensive cross sectioning showed that the separation was characteristic of high-Sn solders. The eutectic Sn–3.5Ag alloy exhibited the lowest level of the down-selected alloys, with 1–2.5% of the lifted TH joints in the final manufacturing trials. In contrast, virtually 100% of the TH joints made with Sn–4.8Bi–3.4Ag exhibited fillet lifting. However, no such cracking was observed in typical
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FIG. 5 Optical micrograph of a vertical cross section of a through-hole solder joint exhibiting fillet lifting between the solder and the intermetallic compound layer on the copper land. Note that the fillet lifting extends from the edge of the land to the knee of the through-hole barrel.
SM joints of high-Sn solders, or in SM or TH joints of eutectic Sn–Pb, or eutectic Sn–58Bi. Several aspects of fillet lifting have been identified. SOURCES OF STRESS. The sources of thermal stresses can be from overall solidification shrinkage, thermal expansion mismatches between the solder, device lead material, the PWB and, possibly, other processes that occur during solidification. The properties that determine how solders respond to these stresses are given in Table 6. The tendency for fillet lifting during cooling increases with increasing board thickness, land size, and CTE mismatch between the PWB. CAUSES OF FILLET LIFTING. Several additional studies were performed to understand the cause of fillet lifting. A full factorial reflow study was performed with Sn–3.4Ag–4.8B, in which reflow and board parameters were varied. The primary result was that all joints exhibited fillet lifting; however, the extent of cracking and the crack opening displacement varied depending on processing conditions. A partial factorial analysis was performed as a function of alloy composition using three board thicknesses, 0.079 cm (0.031 in.), 0.158 cm (0.062 in.), and 0.231 cm (0.091 in.), two land sizes and two component types (CDIP-20 and PDIP-20) to modify the joint stress. The test was full factorial in terms of the test boards and components. A quantitative parameter based on fraction of total cracked joints for a given alloy was utilized. From the results shown in Table 7, it was determined that fillet lifting is predominantly the result of thermally induced stresses arising in the fillet region when the solder is between 90% and 100% solid. The differential shrinkage due to CTE mismatch between the board and the solder generates the stresses; at lower solid fractions, fluid flow occurs relieving the stresses. As the volume fraction of liquid decreases, the stresses are carried by the dendritic matrix and failures occur at the weakest point, location with the highest remaining liquid fraction: the intermetallic compound/solder interface. The same phenomenon has been known to occur in castings and is referred to as ‘‘hot tearing.’’ The tendency for hot tearing increases as the pasty range increases
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TABLE 6 Solder Alloy Properties Affecting Stress Levels in Through-Hole Joints During Cooling from the Wave Soldering Temperature Effect on Stress Levels in Through Hole Solder Joints Cooled from the Processing Temperature
Solder Characteristics Solidification behavior
Mechanical properties Creep properties Fracture toughness Thermal expansion coefficient Microstructural stability
Stresses on the liquid–solid structure are approximately proportional to the difference between the temperature at which the solder first begins to support load during cooling (about 90% solid) and the temperature at which the solder is 100% solid. Solidification shrinkage affects stress levels in joints. Stress/strain (elastic and plastic) behavior of the solder as a function of temperature and thermal history. Creep rate as a function of strain and temperature Interface fracture versus bulk fracture determined by relative toughness of bulk and interface CTE of the solder affects stress level in joints. Coarsening of the solders in TH joints can relieve stresses.
and the temperature difference between 90% and 100% solid increases and is typically worse for alloys with a large nonequilibrium pasty range, such as Sn–Bi. INVESTIGATE CONCEPT. To test the ‘‘hot tearing’’ concept, Sn–3.5Ag, an alloy that showed minimal fillet lifting, was transformed into an alloy showing close to 100% cracked joints with the addition of 2.5% mass fraction Pb. The addition of 2.5%Pb increased the pasty range from 0 to 34jC. These results suggested that Pb contamination from Sn–Pb surface finishes would lead to fillet lifting. Subsequent wave soldering experiments by Multicore, Nortel, and others exhibited
TABLE 7
Tendency for Fillet Lifting as a Function of Composition Defect Fractiona
Alloy Composition (mass fraction %) Sn
Ag
96.5 96.2 91.8 91.5 91.5 95.0 94.0 92.0 90.0 95.0 93.5 92.5 94.0 92.0 94.5 93.5
3.5 2.5 3.4 2.5 0.5
Bi
Cu
Sb
0.5
0.8
4.8
5.0 5.0 5.0 5.0 0.5 1.5 1.0 3.0 0.5 1.5
In
5.0 5.0
1.0 3.0
1.0 3.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0
1.0 1.0
Measured
Calculated
0.03 0.09 0.81 0.18 0.59 0.84 0.83 0.93 0.88 0.04 0.42 0.28 0.40 0.58 0.28 0.13
0.00 0.16 0.90 0.18 0.56 0.85 0.85 0.85 0.85 0.00 0.36 0.27 0.17 0.51 0.26 0.17
a Comparison made between the observed defect fraction and a prediction based on a linear equation for defect fraction as a function of composition.
676 TABLE 8
HANDWERKER ET AL. Printed Wiring Board Surface Finishes Used in Manufacturing Trials
Surface Finishes for Printed Wiring Boards in NCMS Manufacturing Trials Electroless palladium (Pd) (20 Ain.) over copper (Cu) Electroless Pd (20 Ain.) over electroless nickel (Ni) (150 Ain.) Immersion gold (Au) (13 Ain.) over electroless Ni (175 Ain) Immersion Sn (60 Ain.) Imidazole (3–10 nm) HASL Sn–Pb (hot air solder leveled) used only with eutectic Sn–Pb solder as a baseline
fillet lifting in through-hole joints with Sn–Ag, Sn–Cu, or Sn–Ag–Cu solders and Sn–Pb surface finished components and/or boards. In spite of its existence, it is not known if fillet lifting affects TH reliability because the separation does not extend into the barrel, but the mere presence of cracks in as-fabricated TH joints is unacceptable in most applications. 2. Follow-On Assessment The second manufacturing trial was an evaluation of the interaction of the down-selected solders with components and PWBs having Pb-free surface finishes. The manufacturing test vehicle was a two-layer board made from glass-reinforced laminate containing multifunctional epoxy resin with a glass transition temperature (Tg) of about 160jC. The PWB surface finishes utilized in this study are listed in Table 8. The surface mount components used in this phase are listed in Table 9. For each of the PWB finishes listed in Table 8, three PWBs (except for two for Pd over Cu) were assembled with each solder alloy. As Pb-free component finishes were not available, a commercial component–finish–replacement process was used to remove Sn–Pb and replace it with pure Sn. In addition, 132 I/O PQFP and 20 I/O SOIC with Ni/Pd-finished leads were assembled with Sn– 58Bi, Sn–2.6Ag–0.8Cu–0.5Sb, and Sn–3.4Ag–4.8Bi solders. This Ni/Pd process for device leads produced an electroplated 4-Am-thick Pd layer over a 40-Am-thick Ni deposit. a. Wetting and General Integrity. A wetting-Figure-of-merit was developed for solder joint fillets using a relative scale of 1–5, with 5 indicating complete pad coverage and 1 indicating less than 50% coverage, as shown in Figure 6. Assessment of solder joint fillet quality was based on general industry standards of practice, and any instances of inferior joint characteristics were noted. Selected areas were cross sectioned, environmental stress testing was performed, and Jlead pull strength was measured. The pull tests were conducted on joints in the as-soldered condition and following 50 thermal cycles between 55 and +125jC, with 12jC per min ramp rates between the temperature limits and 10-min dwells at each extreme. The purpose of the limited thermal cycling was to determine whether any catastrophic problems were immediately evident in the solder joints, not to determine their long-term reliability.
TABLE 9 Surface Mount Components Used in Study of Printed Wiring Board (PWB) Surface Finishes Components Used in NCMS Manufacturing Trials Bumpered quad flat pack Quad flat pack (QFP) Leadless ceramic chip carrier (LCCC) Plastic leaded chip carrier (PLCC) Small outline integrated circuit (SOIC) QFP PLCC
No. of Leads (Pitch)
Quantity
132. (0.025 in.) 208. (0.5 mm) 44. 44. 20. 256. (0.4 mm) 84.
1 1 1 1 7 1 1
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FIG. 6 Wettability evaluation criteria based on appearance of land and device leads oriented perpendicular to the printed wiring board.
b. Effect of Surface Finish on Wetting. The wetting performance of each alloy was evaluated during SM assembly with pastes containing a conventional no-clean rosin mildly activated (RMA) flux, and is illustrated in Figure 7 as a function of the PWB surface finish. No flux optimization was performed for the Pb-free alloys prior to the assembly trials. The wetting performance of the Pb-free solders was almost as good as the eutectic Sn–Pb control, except when soldering to the imidazole OSP finish. At least one Pb-free alloy matched the wetting performance of the eutectic Sn–Pb control alloy for each metal finish tested, other than the imidazole OSPcoated Cu. Most metallic surface finishes improved the spreading of the Pb-free solders. In the case of the Ni/Au finish, all Pb-free solders exhibited wetting scores of 5, the best performance possible. The fresh immersion Sn finish also enhanced the spreading of the Pb-free solders, most significantly in the case of the Sn–58Bi eutectic. On both the Ni/Pd and Pd-over-Cu finishes, the Sn-rich solders exhibited adequate wetting and spreading (equivalent to Sn or Ni/Au surface finishes), whereas Sn–58Bi and Sn–2.8Ag–20In exhibited considerably reduced spreading. The observed trends are summarized in Table 10.
FIG. 7 The effect of solder finish on an arbitrary wetting index.
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TABLE 10 Wetting Performance as a Function of Solder Composition and PWB Surface Finish Solder Alloy All high-Sn/high-temperature solders Sn–58Bi Sn–20In–2.8Ag
Wetting performance From best Z worst Ni/Au>SncNi/PdcPd>Imidazole Ni/Au>SncNi/Pd>Imidazole>Pd Ni/Au>Sn>Imidazole>Ni/PdcPd
c. Mechanical Pull Testing. Mechanical pull testing of SM device leads was performed for three different components on the manufacturing test vehicle: 20 I/O SOIC, 44 I/O PLCC, and 256 I/O PQFP. Individual device leads were pulled vertically by using a motorized microtensile tester at a crosshead speed of 0.9 cm/min. Approximately 10–15 device leads were pulled from each SOIC and PLCC package, and 100 device leads were pulled from each PQFP package. The maximum load values ranged from 4.9 to 6.9 N for the PQFP device leads, from 10.8 to 17.7 N for the PLCC device leads, and from 7.1 to 14.2 N for the SOIC device leads. The standard deviation for all measurements ranged from F(1.0 to 2.9) N. For both Sn–58Bi and Sn–2.6Ag–0.8Cu–0.5Sb alloys, the contour of the failure path followed that of the device lead. However, the fracture path of the Sn–58Bi joints progressed deeper through the bulk solder; but the fracture of Sn–2.6Ag–0.8Cu–0.5Sb solder joints was localized at the device/solder interface. The same type of device/solder interfacial failure was observed for all the high-Sn solders, consistent with their higher bulk solder strengths reported earlier. The eutectic Sn–37Pb solder exhibited a fracture behavior intermediate to the Sn–58Bi and Sn–2.6Ag–0.8Cu–0.5Sb conditions. For all solders, with the exception of Sn–58Bi and Sn– 2.8Ag–20In, the joints suffered a partial break at the point of maximum load, but remained attached to the pad. The device leads were pulled beyond the maximum load point to achieve complete separation for subsequent examination of the fractured interfaces. In the case of Sn– 58Bi and Sn–2.8Ag–20In, the device leads and associated solder detached completely from the pad at the point of maximum load. Figure 8 shows the maximum load values for SOIC device leads pulled from assemblies made with each Pb-free solder as a function of circuit board surface finish. Considering all board surface finish conditions and accounting for the experimental variability of the data, it was concluded that the performance of all solders is nearly equivalent and, with the exception of Sn58Bi, the differences observed are not statistically significant. Compared with all other downselected solders, the maximum load values with Sn-58Bi are the lowest for imidazole, Ni/Au, Ni/ Pd, and Pd, and second lowest for Sn.
E. Reliability Trials Three separate reliability assessments were performed: (1) thermal cycling of surface mount test vehicles (RTV-SM), (2) thermal cycling of through-hole test vehicles (RTV-TH), and (3) vibration testing of surface mount (RTV-SM) and mixed technology (RTV-TH) test vehicles (high cycle fatigue). The reliability test plan was expanded to include an investigation of the fillet lifting phenomena observed in TH joints after wave soldering. In addition, an assessment was made of company-proprietary models of solder joint reliability available through the Lead-Free Solder Project organizations. A round-robin comparison of these models was performed utilizing the LCCC/FR-4 test geometry and 55jC/+125jC test condition for eutectic Sn–Pb. An energy partitioning (EP) solder joint reliability model devised by a subcontractor, was used to calculate the ranking of three Pb-free solders relative to eutectic Sn–Pb. These reliability modeling studies are described in detail in the NCMS final report and the companion CD-ROM [2]. 1. Surface Mount Thermal Cycle Testing The NCMS surface mount reliability test vehicle (RTV-SM) was designed for in situ electrical monitoring during thermal cycling tests, and the experiment included both electrical testing and
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FIG. 8 The effect of surface finish on the maximum loads measured during pull tests conducted on SOIC device leads soldered with several Pb-free solders and eutectic Sn–Pb.
cross-section analysis of microstructure evolution, crack initiation, and crack propagation during thermal cycling. The RTV-SM was designed for double-sided assembly, with the layout repeated on the second side, resulting in similar components being placed back to back. Double-sided assemblies were used for electrical testing to maximize sample size, while single-sided assemblies were used for cross-sectioning to facilitate sample preparation. All components (Table 11) and boards had lead-free surface finishes. Multilayer FR-4 epoxy glass boards were chosen for the RTV-SM test vehicle to match product requirements. Components (PLCC, BQFP, LCCC, 1206 discrete chip resistors, and 1206 discrete chip capacitors) were distributed across the board so that each component type occupied both edge and central positions, because components placed near board edges often fail earlier than those located more centrally. Components were connected in series to allow electrical continuity testing during thermal cycling by using a half-moon structure provided by AT&T. This allowed isolation of every pair of joints so that defects or failures could be bypass-jumpered to continue the test after some components failed. A total of
TABLE 11
Component Surface Finishes in Surface Mount Solderability Test Vehicle (STV-SM) Lead Count
Pitch/Package Size in mm (mils)
J-leaded PLCC Gull-wing leaded BQFP Castellated I/O LCCC 1206 Discrete chip resistors
84 132 44 —
1206 Discrete chip capacitors
—
1.3 (50) 0.64 (25) 1.3 (50) 3 (length) 1.5 (width) (120 60) 3 1.5 (120 60)
Package Type
Remarks Plastic leaded chip carriers Bumpered quad flat packages Leadless ceramic chip carriers Alumina body Barium titanate body
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10,320 joints were tested per alloy per test condition. The thermal cycling conditions are listed in Table 12. a. Test Results. Solder fatigue failures occurred only for the LCCC and 1206 resistors by the end of the test, after 6773 cycles at the 0jC/100jC condition, and after 5000 cycles at the 55jC/125jC condition. The LCCC was included in the testing to have a component that was certain to fail early in thermal cycling, thereby providing data for the group’s reliability modeling activity. All lead-free alloys performed as well or better than eutectic Sn–Pb for LCCCs for both thermal cycling conditions. No solder fatigue failures occurred for the BQFP, PLCC, or 1206 chip capacitors during these experiments. Alloy performance for the 1206 chip resistors was primarily evaluated through comparisons of total number of failures during the test, cycles to first failure, cycles to 10% failure, and microstructures; with limited use of Weibull statistics. The Weibull plots are shown in Figure 9 and the Weibull values given in Table 13. The data are summarized in the following sections. 0jC TO 100jC THERMAL CYCLE CONDITION. The failure levels ranged from 0% to 11% at the end of 6673 cycles as shown in Figure 9a.
Sn–3.4Ag–4.8Bi was the only alloy, which was failure free for the test duration and, accordingly, was ranked first. Sn–58Bi was the next best performer with less than 1% failures for the test duration. Sn–37Pb, Sn–3.5Ag, and Sn–3Ag–2Bi were grouped together as the next best performers with about 2–5% failures for the test duration. Sn–2.6Ag–0.8Cu–0.5Sb, Sn–2.8Ag–20In, and Sn–3.5Ag–0.5Cu–1Zn were grouped together and ranked the lowest with about 8–11% failures. These alloy rankings were supported by cross-section photomicrographs of chip resistors that have been exposed to approximately 5700 cycles (0–100jC). 55 TO +125jC THERMAL CYCLE CONDITION. The failure levels varied from 4% to 57% at the end of 5000 cycles as shown in Figure 9b.
Sn–58Bi exhibited the best performance with about 4% of components failing by the end of testing. Sn–37Pb and Sn–3.4Ag–4.8Bi are grouped together as the next best performers with about 13% and 16% failures, respectively. The remaining five alloys were tightly grouped, with failure levels ranging from 54% to 57%. Listed by the 10% failure level, Sn–3.5Ag, Sn–2.6Ag–0.8Cu–0.Sb, Sn–2Ag–2Bi, and Sn–3.5Ag–0.5Cu–1Zn essentially performed the same, while Sn– 2.8Ag–20In had a slightly worse fatigue life. This general progression of alloy rankings are supported by the cross-section photomicrographs of chip resistors that have been exposed to approximately 4300 cycles of the 55 to +125jC temperature range. Based on the accelerated thermal cycling test results for the various surface-mounted components in this study, it is clear that the ranking of alloys depends on the thermal stresses
TABLE 12
Thermal Cycling Conditions for the Surface Mount Reliability Test Vehicle (RTV-SM)
Cycling Conditions
Temperature Range (jC)
Ramp Rate (jC/min)
Dwell Time (min)
Approximate Number of Daily Cycles
Profile 1 Profile 2
0 to 100 55 to +125
10 11
5 20
48 20
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FIG. 9 Cumulative failure probability distributions as a function of the number of thermal cycles for 1206 resistors mounted with several Pb-free solder alloys and eutectic Sn–Pb. (a) 0 to 100jC thermal cycling conditions. (b) 55 to 125jC thermal cycling conditions.
682 TABLE 13
HANDWERKER ET AL. Weibull Data for the RTV-SM Components Weibull Parameters 0 to 100jC, 10jC/min ramp rate, 5-min dwells at temperature extremes
55 to +125jC, 11jC/min ramp rate, 20-min dwells at temperature extremes
Solders
c
g
b
c
g
b
Sn–37Pb Sn–3.5Ag Sn–58Bi Sn–3Ag–2Bi Sn–2.6Ag–0.8Cu–0.5Sb Sn–4.8Bi–3.4Ag Sn–20In–2.8Ag Sn–3.5Ag–1Zn–0.5Cu
a
a
a
a
a
a
1900 1187
10,055 5443
2.00 1.64
a
a
a
a
a
a
a
a
a
1232
5017
1.43
a
a
a
1238
4265
1.24
a
a
a
1410 1226 2456 1302 1214
a
5756 5134 9560 5496 5174
1.29 1.40 1.54 0.90 1.56
Insufficient data to compute reliable values for these Weibull parameters.
imposed on the solder by the component and PWB geometry and the thermal cycling environment. The suitability of an alloy for a particular application was determined, therefore, by the failure of the first component on a board. From the data on the 1206 resistors, it appears that high-Sn alloys, with the exception of Sn–3.4Ag–4.8Bi, exhibit poorer performance than eutectic Sn–Pb or eutectic Sn–Bi. For PQFPs, PLCCs, or 1206 capacitors, no meaningful electrical failures were observed for any of the alloys tested, suggesting that all lead-free candidate alloys of this study are acceptable as substitutes for eutectic Sn–Pb under those states of stress exerted during the testing. 2. Through-Hole Thermal Cycle Testing The primary purpose of the RTV-TH test was to determine if the rankings of the various solder alloys under consideration would change as a result of a difference in solder joint configurations and stress loading encountered by TH solder joints. The through-hole reliability test utilized a test vehicle (RTV-TH) and evaluated one low-operating-temperature range solder, Sn–58Bi (A6), one high-operating-temperature range solder, Sn–2.6Ag–0.8Cu–0.5Sb (F2), and included eutectic Sn–Pb solder (A1) for comparison. The RTV selected by the task group incorporated both TH and SM components commonly used in a variety of product applications. Component choice was based on the expected stress/strain response during thermal cycling, in addition to component body material, the lead attachment configuration, and availability in a daisy chain configuration. This test vehicle contained three plated TH solder-joint configurations and material combinations, and two SM components evaluated in the RTV-SM testing, as listed in Table 14. Components were obtained with either a 100% Sn finish, or with a Sn–Pb finish that was stripped and refinished by a commercially available Sn-dipping process. As with RTV-SM parts, the daisy-chained components were electrically monitored through an event detector. Thermalcycle testing was conducted from 55 to +125jC with 16-min transition ramps and 15-min dwell times at temperature extremes (11.25jC/min ramp rate, f24 cycles/day). The testing was conducted for 2000 thermal cycles. A component was considered to have failed when the event detector recorded 15 ‘‘open’’ events. a. Test Results. Solder performance in the RTV-TH varied substantially with component type; the CPGA-84s failed before the CDIP-20s. After 2000 thermal cycles at 55 to +125jC, there were no electrical failures for eutectic Sn–Pb with CDIP-20s; however, Sn–58Bi and Sn– 2.6Ag–0.8Cu–0.5Sb had begun to fail after 1100 and 200 cycles, respectively. Of the 20 CDIP components, 7 components assembled with Sn–58Bi failed by the end of the test (2000 cycles); 18
MAJOR INTERNATIONAL LEAD (PB)-FREE SOLDER STUDIES TABLE 14
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Through-Hole and Surface Mount Components Used for Reliability RTV-TH
Package Type Ceramic pin grid array (CPGA) Ceramic dual in-line package (CDIP) Plastic dual in-line package (PDIP) Plastic J-leaded chip carrier (PLCC)a Castellated leadless ceramic chip carriers (LCCCs)a
Pin Count
Pitch (mils)
84 20 20 44 44
100 100 100 0.05 0.05
a The PLCC-44 and LCCC-44 are SM devices and were used for comparison with the separate RTVSM evaluation.
CDIP components assembled with Sn–2.6Ag–0.8Cu–0.5Sb also failed. Examination of crosssectioned parts suggests that solder joints with both Pb-free alloys were more susceptible to shoulder cracking than eutectic Sn–Pb. Although approximately 25% of Sn–2.6Ag–0.8Cu–0.5Sb as-fabricated joints showed fillet lifting, there was no obvious relationship between fillet lifting and failure. No electrical failures of PDIPs occurred for any alloy at the end of test (i.e., up to 2000 cycles). 3. Vibration Testing Vibration (high-cycle fatigue life) testing was conducted to determine: (1) if there were measurable differences in the performance of the down-selected solder alloys, or (2) if the mode of failure of the Pb-free solders was distinguishably different from eutectic Sn–Pb solder in a vibration environment. Of all components vibration tested on both RTV-SM and STV assemblies, only the LCCC-44 and PLCC-84 parts experienced failures related to solder performance that were analyzed further. The PQFP-208 and PQFP-132 parts exhibited lead fractures for all solders, not just the stronger lead-free solders. The PLCC-44 components did not exhibit enough failures to be meaningfully analyzed. The 1206 discrete devices did not exhibit any failures. On the RTV-SM assembly, component location and position had a strong effect on time-tofirst-failure for PLCC-84 and LCCC-44 devices. While there was a wide range of performance exhibited across the eight solder alloys, a similarly wide variation in performance was observed among the various component sites on the same board. Furthermore, a wide variation in performance was also observed at all locations across the three replicate boards used to test each solder. It was concluded that this position effect, coupled with general data variability, overshadowed the effect attributable to the solder alloy alone, and masked the ability to distinguish one solder alloy from any other. None of the Pb-free alloys exhibited catastrophic failure or distinguishably poorer performance than the other Pb-free alloys or the eutectic Sn–Pb control. Component type determined the failure time and mode. There were no clear differences between solder alloys or PWB surface finishes under the vibration conditions studied. 4. Reliability Assessments The only SM components with obvious fatigue failures after more than 6700 cycles of 0–100jC, or 5000 cycles of 55 to +125jC were LCCCs and 1206 chip resistors. No leaded SM devices exhibited failures. There were no unexpectedly early or catastrophic chip carrier or passive component failures. Those failures that occurred followed the same component order as observed for eutectic Sn–Pb. The ranking of alloys relative to eutectic Sn–Pb varied with thermal cycle and component type. Each solder alloy is able to withstand different amounts, types, and rates of loading, which are dependent upon the different coefficients of thermal expansion (CTE) and mechanical properties of the board, components, and alloys, and upon solder joint configurations. The alloy ranking results, which change with component type, demonstrate the dangers of using a single component, a small subset of typical solder joint configurations, or a set of
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laboratory experiments, such as creep tests, to predict general behavior. One review cited research on Sn–3.5Ag, Sn–0.7Cu, and Sn–4Ag–0.5Cu that noted these alloys exhibit better isothermal creep resistance than eutectic Sn–Pb at 25 and 100jC [8]. However, in the NCMS TMF tests, not all components exhibited this improvement in solder joint fatigue lifetime over eutectic Sn–Pb.
F. Mechanical Properties of Lead (Pb)-Free Solders The NCMS project developed a large data set of the mechanical properties of lead-free solder alloys. For three Pb-free solder alloys and eutectic Sn–Pb, these include creep data, constitutive equations, and microstructural data, as well as detailed descriptions of test methods, sample geometries, and material data for the components and boards used in the experimental testing, as listed in Table 15. Partial datasets for 75 additional solder alloys were generated and are included in the NCMS CDROM [2]. Experimental load–displacement history and creep data were used to estimate the partitioned viscoplastic constitutive properties. Load–displacement loops from double lap-shear tests were used in conjunction with finite element (FE) models to refine the estimates of the effective viscoplastic constitutive properties of the three Pb-free solders and eutectic Sn–Pb. The constitutive equations for the four solders were used as initial estimates when iterating to match experimental and predicted hysteresis loops. That is, experimentally determined double lap-shear specimen load–displacement hysteresis loops were compared with the FE simulations. The constitutive properties were then adjusted iteratively to improve agreement; the equations and properties are presented in Table 16.
G. NCMS Project Conclusions The key conclusions of the NCMS Project were as follows: (1) no drop-in replacement was found for eutectic Sn–Pb solder, and (2) promising alternatives exist but more detailed information was
TABLE 15
Data Obtained in the NCMS Lead-Free Project
Data available from NCMS Project Report and CD-ROM Room temperature properties of lead-free solders Elastic moduli, power law plastic constants; test displacement rate of 0.02 in./min in ambient environment Thermomechanical double-lap shear test data Temperature, load, strain data from double-lap shear specimens simultaneously subjected to in-phase mechanical and thermal cycles: 55 to +125jC (55 to +90jC for Sn–58Bi alloy), 6min ramp time, 3-min dwell time; 2.9104 deformation rate Solder alloy creep data Strain rates at 20, 75, and 125jC and at three stress levels varying from 5 to 75 MPa; creep curves from same tests Damage properties data Experimental fatigue test data for LCCC-44 packages for two temperature cycle histories: 72-min cycle, 55 to +125jC, 11.25jC/min ramp rate, 20-min dwell time, 35jC mean temperature 30-min cycle, 0j to 100jC, 10jC/min ramp rate, 5-min dwell time, 50jC mean temperature Package/board data Package drawings and dimensions for LCCC-44, TSOP-32, PQFP-132, 1206 chip resistors and capacitors Solder joint cross-section photos of 1206 chip components Miscellaneous package materials data, e.g., CTE, elastic stiffness, etc.
MAJOR INTERNATIONAL LEAD (PB)-FREE SOLDER STUDIES TABLE 16
685
Constitutive Equations for Pb–Sn and Lead-Free Solder Alloys Creep Constants
Alloy Sn–40Pb Sn–58Bi Sn–3.5Ag Sn–4.7Ag–1.7Cu Sn–3.4Ag–4.8Bi
E(T ) (MPa, K)
m
E=3.61310474.889T E=3.40510474.552T E=5.783104103.330T E=3.23410474.944T E=3.40010474.778T
0.4 0.4 0.4 0.4 0.4
A 3.99 8.45 3.87 2.72 5.93
108 102 1014 1011 1010
n
Q (kcal K/mol)
CTE (ppm/K)
3.48 3.424 6.05 3.69 3.56
12.001 21.85 14.61 8.6 11.56
25 17 21 21 21
needed before contemplating any significant changes to the present industry practice. Of particular concern were the changes needed in the materials and processing infrastructure. All but one of the solders examined in this study were high Sn alloys with liquidus temperatures above 210jC. The implications of having high-Sn solders with liquidus temperatures approximately 30jC higher than Sn–Pb eutectic go beyond just increasing assembly temperatures. If high-Sn solders are to be used, current board, component, and process materials must be evaluated to determine if they can tolerate exposure to higher temperatures during processing. If these materials are not stable and use of Pb-free solders is desired or required, alternative materials will be needed to allow components and products to survive the manufacturing process.
H. NCMS Project Recommendations Based on the RTV-SM, RTV-TH, and fillet-lifting test results, participants of the NCMS project recommended three alloys: it is expected that the Sn–58Bi eutectic, Sn–3.4Ag–4.8Bi, and Sn– 3.5Ag eutectic solders might perform substantially better than eutectic Sn–Pb in certain applications, as summarized in Table 17. The Sn–58Bi eutectic and Sn–3.5Ag–4.8Bi alloys exhibited fatigue lives comparable to or better than eutectic Sn–Pb in both 0 to 100jC and 55 to +125jC accelerated thermal cycle (ATC) tests. Cross sections of 1206 resistors and capacitors showed that both alloys exhibited only minor cracking in SM joints after 0–100jC thermal cycling, compared with more extensive cracking seen for all other down-selected solder alloys and for eutectic Sn–Pb. For 1206 resistors thermally cycled from 0 to 100jC, alloy Sn–3.5Ag–4.8Bi was the only alloy to have no electrical failures up to 6673 cycles, thereby surpassing the performance of eutectic Sn–Pb by more than 2000 cycles. For 1206 resistors thermally cycled from 55 to +125jC, the number of cycles to first failure for Sn–3.5Ag–4.8Bi was equivalent to eutectic Sn–Pb. The alloy Sn–58Bi exhibited fewer total failures at the end of testing than eutectic Sn–Pb. The Sn–3.5Ag eutectic was selected as a possible replacement alloy for mixed technology (SMT and TH) boards. From the 1206 resistor data, the reliability for Sn–3.5Ag appeared to be equivalent to Sn–37Pb for the 0 to 100jC thermal cycle condition, but exhibited worse reliability than Sn–37Pb for 55 to 125jC.
III. SANDIA NATIONAL LABORATORIES FOLLOW-UP STUDY The alloy, Sn–3.4Ag–4.8Bi, developed and patented by Sandia National Laboratories, was determined in the NCMS Lead-Free Solder Project to exhibit outstanding fatigue properties for surface mount applications under both accelerated thermal cycle test conditions used in the NCMS study. Sandia performed ATC testing of this alloy to 10,000 cycles for 0–100jC with 10jC/min ramp rates and 5-min dwell times [9,10]. There were no electrical failures at end of test (10,000 cycles) for 68 I/O PLCCs, 24I/O SOICs, and 1206 chip capacitors on FR4 boards, no cracks after 5000 cycles, and only minor surface cracks after 10,000 cycles. The Sn–3.4Ag–4.8Bi alloy has demonstrated considerable promise for use in surface mount applications, exhibiting greater fatigue resistance than eutectic Sn–Pb and most other lead-free alloys. It should be
686 TABLE 17
HANDWERKER ET AL. NCMS Project Recommendations
Alloys
Solidus and Liquidus Temperatures
Industry Sectors
Summary of Observations Use: Simple two-component eutectic alloy, but low eutectic temperature restricts maximum use temperature. Surface Mount Technology: Better fatigue life than eutectic tin–lead for both thermal cycle test ranges; less fatigue damage than eutectic tin–lead observed in surface mount cross sections. Through-Hole Technology: Mixed results with fatigue life, for CPGA-84 better than eutectic tin–lead; for CDIP-20 worse than eutectic tin–lead. Surface Mount Technology: Longer fatigue life than eutectic tin–lead at 0 to 100jC; no failures in 1206 resistors up to 6673 cycles; fatigue life equivalent to eutectic tin–lead at 55 to +125jC; less fatigue damage than eutectic tin– lead observed in surface mount cross sections. Through-Hole Technology: Most joints exhibit fillet lifting. Alloy Type: Simple twocomponent eutectic. Surface Mount Technology: Fatigue life equivalent to eutectic tin–lead at 0 to 100jC; worse than eutectic tin–lead at 55 to +125jC. Through-Hole Technology: Less susceptible than other high-tin solders to fillet lifting but results with Sn– 2.6Ag–0.8Cu–0.5Sb indicate through-hole reliability still may be compromised.
Sn–58Bi
139jC (eutectic)
Consumer Electronics, Telecommunications
Sn–3.5Ag–4.8Bi
205–210jC
Consumer Electronics, Telecommunications, Aerospace, Automotive
Sn–3.5Ag
221jC (eutectic)
Consumer Electronics, Telecommunications, Aerospace, Automotive
MAJOR INTERNATIONAL LEAD (PB)-FREE SOLDER STUDIES
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remembered that there are some limitations on its use: in through-hole applications, this alloy exhibits a strong tendency for fillet lifting, and possible contamination of Bi-containing alloys with Pb from surface finishes that may affect the ATC behavior. Additional studies by Sandia have indicated that this alloy may be more susceptible than eutectic Sn–Pb to microstructural damage under thermal shock environments and its high thermomechanical fatigue resistance may lead to damage in the component rather than in the solder. In thermal shock, the amount of damage was least for Sn–3.5Ag, moderate for Sn–58Bi, and greatest for Sn–3.4Ag–4.8Bi [9].
IV. RESEARCH AND DEVELOPMENT IN JAPAN A. Promotion of Lead-Free Soldering In January 1998, the Japan Electronic Industry Association [now called Japan Electronics and Information Technology Industries Association (JEITA)] and Japan Institute of Electronics Packaging (JIEP) released the national roadmap for lead-free soldering in Japan. The purpose was to promote the use of lead-free solders through a small scale, manufacturing-based project in which both processing and reliability information could be accumulated. The roadmap suggested production should begin with Sn–Ag alloys with additions of Cu and/or Bi. These alloys were believed to be the most reliable alloys among the many possible candidates with Sn–Pb surface finished components. The roadmap also suggested that Japanese industry would shift to lead-free surface-finished components when suitable plating technology is developed. 1. First Commercial Products Accordingly, Matsushita Electric Industrial released the first mass-produced product made with Pb-free solder paste, the compact minidisk player shown in Figure 10. They demonstrated their share of the Japanese minidisk player market could be expanded by introducing a ‘‘Green Leaf’’ product, a product assembled with a Sn–Ag–Bi–In solder paste. In October 1999, shortly after the Matsushita product release, NEC introduced its Pb-free notebook computers, soldered with Sn– 8Zn–3Bi solder paste (Figure 11). The rationale for choosing this alloy is that some of the components for the PC require a low soldering temperature. In addition to reflow soldering,
FIG. 10 World’s first mass-produced compact minidisk player soldered with Pb-free solder. Solder utilized is Sn–3Bi–2.7In–2Ag. (Courtesy of Panasonic.)
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FIG. 11 Notebook personal computer soldered with Sn–8Zn–3Bi. (Courtesy of NEC.)
Matsushita Electric Industrial introduced Pb-free wave soldering to mass production of videocassette recorders (VCR) in 1999. The single-sided PWB assembled with Sn–Cu eutectic solder for a VCR is shown in Figure 12. In August 2000, Nissan Motors released a lead-free soldered, keyless entry component produced by wave soldering with a Sn–Ag–Cu alloy. 2. Proliferation of Products Since the start of 2001, an increasing number of products soldered with lead-free solders are reaching the Japanese market, and some of these are summarized in Table 18. Although the assembly of most products includes components with Sn–Pb surface finishes components, leadfree surface-finished components are commercially available to the Japanese microelectronics industry and more limited to other geographic regions.
B. New Energy and Industrial Technology Development Organization (NEDO) Study In 1998–1999, a lead-free soldering Japanese national project was conducted with the support of New Energy and Industrial Technology Development Organization (NEDO), whose organiza-
FIG. 12 Printed circuit board of a videocassette recorder/player whose 0.16-mm-pitch QFP leads are soldered to the board with Sn–Cu solder containing a small amount of Ni. (Courtesy of Panasonic.)
MAJOR INTERNATIONAL LEAD (PB)-FREE SOLDER STUDIES TABLE 18
689
Japanese Products Made with Lead-Free Solder
Company
Date
Products
Panasonic
1998 2000 1999 1999 2000
Compact MD player Compact cassette player VTR VCR, Freezer, Cleaner, Washing machine, Air conditioner, Notebook computer Pager Notebook computer VCR TV, Notebook computer, Desktop computer Notebook computer Keyless entry system
Hitachi
NEC Sony
Toshiba Nissan Motors
2000 1998 1999 2000 2000 2001 2000
Solder Method/Technique Reflow with Sn–Ag–Bi–In Wave with Sn–Cu–Ni Wave with Sn–Ag–Cu
Reflow+Halogen free PWB Reflow with Sn–Ag–Cu Reflow with Sn–8Zn–3Bi Reflow with Sn–2.5Ag–1Bi–0.5Cu Wave/Reflow+halogen free PWB Reflow with Sn–Ag–Cu Wave with Sn–Ag–Cu
tion is shown schematically in Figure 13 [11]. JEIDA and the Japan Welding Engineering Society (JWES) were focused on addressing productivity and reliability issues, and on measuring the basic properties of solders, respectively [12]. The Electronic Industries Association of Japan (EIAJ) joined with JEIDA to evaluate components and their surface finishes. The main purpose of the project was to promote commercial lead-free soldering, with the major companies in JEIDA establishing their own target products and lead-free solder alloy to achieve this goal. 1. JEIDA Reliability Evaluation a. Scope. The lead-free solders evaluated in the JEIDA project are listed in Table 19. These alloys were selected because member companies had already accumulated data on them and selected them as their companies’ choices. Sn–3.5Ag–0.75Cu was selected as a candidate suitable for both reflow and wave soldering processes. Because Sn–Ag–Cu alloys required high processing temperatures, Sn–Ag solders with some Bi were also chosen. The Sn–58Bi eutectic with Ag addition was also considered a potential solder for manufacturing because of its low
FIG. 13 Organization of NEDO Lead-Free project.
690 TABLE 19
HANDWERKER ET AL. Lead-Free Alloys Evaluated in the JEIDA Project First stage
Alloys Sn–Ag Sn–Cu Sn–Ag–Bi
Sn–Bi
Sn–3.5Ag–0.75Cu Sn–0.7Cu–0.3Ag Sn–3Bi–2Ag–0.75Cu Sn–4Bi–2Ag–0.5Cu–0.1Ge Sn–5Bi–3.5Ag–0.7Cu Sn–6Bi–3.5Ag Sn–57Bi–1Ag
Second stage
Reflow, Wave R and W W R R R R R
melting point. Before manufacturing trials, the properties of the solders listed in Table 19 were reviewed based on a preliminary study. The solders of 3–5% Bi were combined into a single alloy because of their complex solidification behavior with Sn–Pb plating on components, and their sensitivity to fillet lifting. For wave soldering, Sn–Ag–Cu was added to the list because of its lower cost. b. Testing. Seven types of PWBs were prepared for reflow soldering, and two types for wave soldering; each corresponds to a particular test category. A typical PWB is shown in Figure 14. The test categories and the types of components used are summarized in Table 20. For the fatigue, creep, and migration tests, in situ monitoring of electrical conductivity was utilized to detect failure. The components utilized in the JEIDA project were plated with Sn–10Pb except for half of the DIPIC parts on the JR-02 board, which were plated with Pd–Ni. The CSP was assembled with Sn–Pb eutectic solder balls. c. Results. The influence of thermal cycles (40 to 125jC) on the lead pull strength of the QFPs soldered with Sn–3.5Ag–0.75Cu, Sn–2Ag–3Bi–0.5Cu, and Sn–37Pb with Sn–Pb plated
FIG. 14 Printed circuit board JR-01 used for thermomechanical fatigue testing utilizing the thermal cycling conditions from 40 to 125jC, with 30-min dwell times at the temperature extremes. Testing also included a shear test for chip components, and a tensile pull test for QFP leads.
MAJOR INTERNATIONAL LEAD (PB)-FREE SOLDER STUDIES TABLE 20
Test Categories with the Types of Components Used
Soldering Method
Board Material
Reflow
FR-4
Wave
FR-4a
Phenolic
a
691
Evaluation Items (Board Design Number) Thermal fatigue test of various components (40 to 125jC, 30-min dwell time) Shear test for chip components, and tensile pull test for QFP leads (JR-01 board) Thermal fatigue test with two layers plating on SOP (40 to 125jC, 30-min dwell time) Tensile pull test of lead wire (JR-02 board) Solderability (wetting, dewetting, solder balls) and migration (JR-03 board) Thermal fatigue test (40 to 125jC, 30-min dwell time) Creep test (JR-04 board) Thermal fatigue test (40 to 125jC, 30-min dwell time) (JR-05 board) Thermal fatigue test (40 to 125jC, 30-min dwell time) Mechanical fatigue test (JR-06 board) Mechanical fatigue test by bending PWD (JR-07 board) Thermal fatigue test (40 to 125jC, 30-min dwell time) Creep test, Fillet lifting (JR-01 board) Thermal fatigue test (40 to 125jC, 30-min dwell time) Creep test, Fillet lifting (JR-02 board)
Components Chip components QFP-100 pins
SOP-42 pins
No QFP-100 pins
BGA CSP-176 balls
Lead-less chip carriers DIPIC Jumper wire
DIPIC Jumper wire
Double-sided.
leads is shown in Figure 15. All joints exhibit a gradual decrease in strength with increased number of thermal cycles. The alloy Sn–3.5Ag–0.75Cu exhibited the highest initial strength and maintained a higher value up to 1000 cycles. The microstructural evolution of the solders is different: Sn–3.5Ag–0.75Cu does not show any significant changes except for small cracks in a solder fillet. In contrast, Sn–37Pb exhibits severe grain coarsening and cracking. Sn–2Ag–3Bi– 0.5Cu frequently shows cracking along the interfaces between the solder and a Cu land or Cu lead. The Weibull plots of the time-to-failure for the CSPs mounted on JR06 PWBs utilizing Sn– 3.5Ag–0.75Cu, Sn–2Ag–3Bi–0.5Cu, and Sn–37Pb solder pastes are shown in Figure 16. The two lead-free solders are equivalent to the Sn–Pb eutectic alloy. d. Summary. The main results from the JEIDA project are summarized as follows: (1) A database of selected lead-free solders has been established. Although each alloy has its own limitation, each can be successfully used for some niche commercial applications. For reflow process: (2) Insulation characteristics such as migration are not problems for lead-free solders. (3) Wetting is not as good as Sn–Pb solder. (4) Bismuth-bearing solders exhibit poor compatibility with Sn–Pb surface finishes on components. The magnitude of the effect depends on the Bi concentration.
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FIG. 15 The effect of thermal cycling (40 to 125jC, with 30-min dwell times at the temperature extremes) on the peel lead strengths of several Pb-free solder alloys used to mount QFPs with Sn–Pb plated leads. The study evaluated two Pb-free solders and eutectic Sn–Pb as a control.
For wave soldering process: (5) Fillet lifting becomes more severe in the presence of Bi. Even without Bi, fillet lifting occurs by the segregation of Pb from the surface finish of components during solidification. (6) Lead-free solders are equivalent to or better than Sn–Pb eutectic solder in creep and thermal fatigue resistance. 2. JWES Method and Materials Evaluations The JWES group evaluated various test methods, and tested a range of solder alloys. Measurements of melting point, tensile strength, wettability, and strength of leaded solder joints and chip joints were performed as part of a Pb-free solder evaluation, including the Sn–Ag–Cu, Sn–Ag–Bi, and Sn–Ag–Bi–In alloy systems. The main results for the alloys are summarized in Table 21.
FIG. 16 Weibull plots of CSPs with Sn–37Pb balls under accelerated thermal cycle test conditions (40 to 125jC, with 30-min dwell times at the temperature extremes), as determined by in situ measurements during the JEIDA project. The study evaluated two Pb-free solders and eutectic Sn–Pb as a control.
MAJOR INTERNATIONAL LEAD (PB)-FREE SOLDER STUDIES
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TABLE 21 Measurements of Melting Point, Tensile Strength, Wettability, and Strength of Lead Joints and Chip Joints were Performed as Part of Pb-Free Solder Evaluation, Including for the Sn–Ag–Cu, Sn–Ag–Bi, and Sn–Ag–Bi–In Alloy Systems Sn–Ag–Cu
Sn–Ag–Bi
Sn–Ag–Bi–In
Pasty range is >1jC in 0.7 f2.0% Cu. Tensile strength is not influenced by Cu addition. Bridging increases as Cu increases. Pasty range is 10jC for 3% Bi and 30jC for 10%Bi. Bi increases strength but decreases elongation. Bi promotes wetting and suppresses bridging. Melting temperature becomes 211jC for 4% In. In additions have little influence on wetting and bridging.
3. JIEP Project a. Scope. JIEP has promoted lead-free soldering since 1994 through the activity of its Lead-Free Working Committee, with membership that has included approximately 50 companies and several universities. The working groups defined several candidate Pb-free alloys for examination. In the first stage, Bi-containing alloys such as Sn–2Ag–22Bi and Alloy-H were evaluated to replace Sn–Pb eutectic alloy without modifying standard processing conditions. Based on the results [13,14], a second stage of round robin testing was defined. Of specific interest, Sn–Zn alloys were examined and a much improved solderability of Sn–Zn paste was demonstrated by using a patented process [14]. This work led NEC to utilize a Sn–Zn alloy in their notebook PC. b. Results. The Low Temperature Soldering Project was initiated by JIEP in August 2000 to explore low soldering temperatures (i.e., below 230jC) with a focus on Sn–Zn and Sn–Bi neareutectic alloys. In the first stage, considerable existing data, such as metallurgical properties, mechanical properties, solderability, reliability, and patents on the Sn–Zn alloy system, were summarized [13,14]. In the second stage, CSPs were selected to examine the solderability and reliability of the latest Sn–8Zn–3Bi solder paste and assembled in air onto FR-4 PWBs. Results indicate that good solderability is seen even in air at 210jC [13,14]. No failures were observed for these CSP solder joints up to 1000 cycles between 40 and 125jC.
C. Other Japanese Projects An IMS project supported by MITI was initiated in July 2000 and led by Hitachi. Many electronics companies, such as Sony, Sharp, Oki, and others, participate in this project along with several Japanese universities. The focus of the project, whose framework is summarized in Table 22, is on the environmental evaluation of electronic packaging technologies. Among the focus areas are life cycle analysis (LCA) evaluation, resource evaluation research, recycling technologies and toxicology of solders, as well as the solderability and reliability of candidate solders, such as Sn–Ag–Cu, Sn–Zn–Bi, and Sn–Cu. This project expanded its membership and research topics to become an international project involving Asian and European companies, national laboratories, and universities. JWES is investigating the standardization of lead-free solder evaluation methods. It is necessary to standardize test methods related to the evaluation of material properties such as melting, solidification, mechanical properties, and wetting properties for comparison of Pb-free alloys. New standard test methods are expected to be established by 2002. JEITA plans to establish comparable standards for the evaluation of components and soldered parts as well.
694 TABLE 22
HANDWERKER ET AL. Framework of the IMS Lead-Free Solder Project Supported by MITI
Membership
Consortium of OEMs and Universities
Period
2000–2003
Work Scope
Contents
WP1 Soldering
Task1 Task2 Task3
WP2 Biological
Task1 Task2 Task1 Task2 Task1 Task2
WP3 Environmental WP4 Recycle/Reuse
TABLE 23
Reflow (temperature uniformity, yield) Narrow pitch Wave (impurity control) Improve plating on components Leaching, Impact on humans Toxicity Resource Life cycle analysis Field research Recycle/reuse technology
Lead-Free Solder Alloys Used in Japanese Market in 2001
Processes
Alloys
Notes
Wave soldering
Sn–Ag family: Sn–3.5Ag, Sn–3Ag–0.5Cu Sn–Cu family: Sn–0.7Cu With/without additions of Ag, Au, Ni, Ge, In, etc.
Reflow soldering
High temperature
Sn–Ag family: Sn–3.5Ag, Sn–3Ag–0.5Cu, Sn–(2–4)Ag–(1–6)Bi With/without In 1–3%
Intermediate temperature
Sn–Zn family: Sn–9Zn, Sn–8Zn–3Bi
Low temperature
Sn–Bi family: Sn–57Bi–(0.5–1)Ag Sn–Ag family: Sn–3Ag–0.5Cu Sn–Cu, Sn–Bi families
Compatibility with Sn–Pb plated components. Fillet-lifting and land-lifting. For one-sided PWBs, Bi can be added though the compatibility with 42 alloy should be noted. Heat resistance of components and PWBs. One needs to control temperature distribution on PWBs. Compatibility of Bi with Sn– Pb plating. Corrosion should be noted, especially for chlorinecontaining environments. Barrier plating such as Au/Ni can improve high temperature stability. Compatibility with Sn–Pb plated components. Compatibility among different solders and fluxes.
Hand and robot soldering
MAJOR INTERNATIONAL LEAD (PB)-FREE SOLDER STUDIES
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TABLE 24 JEITA (the Former JEIDA) Program Roadmap for LeadFree Soldering Activities First adoption of lead-free solders in mass-production Adoption of lead-free components Adoption of lead-free solders in wave soldering Expansion of use of lead-free plated components Expansion of use of lead-free solders in new products General use of lead-free solders in new products Full use of lead-free solders in all new products Lead-containing solder used only exceptionally
Targets 1999 2000 2000 2001 2001 2002 2003 2005
D. Lead (Pb)-Free Solder Roadmap in Japan The major commercially available lead-free solders in the Japanese market are listed in Table 23. The Sn–3Ag–0.5Cu alloy is a very versatile alloy compatible with various soldering processes. It possesses excellent reliability and good solderability, but is prone to fillet lifting with Sn–Pb surface finished components for through-hole circuits. To prevent heat damage of large PWBs or large components on PWBs, the temperature gradients on the PWBs must be reduced by modifying reflow profiles or by utilizing reflow ovens of an advanced design. Solder pastes of Sn–8Zn–3Bi and Sn–9Zn can be adapted to SMT even for air reflow; these alloys are particularly useful when the soldering temperature must be reduced (i.e., 210jC). The reliability of PWBs assembled with these Sn–Zn alloys is excellent. Nevertheless, these alloys can be susceptible to corrosion in some environments, especially in those containing chloride. When Sn–Zn alloy is directly in contact with Cu, the interface degrades severely at 150jC; a barrier coating is therefore required. Eutectic Sn–0.7Cu is particularly useful for wave soldering without modification of processing conditions. The lack of Ag makes this alloy advantageous with respect to cost. Because wetting is not as good as Sn–Pb, the Sn–0.7Cu alloy may be limited to use for single-sided PWBs. Its use may be further limited because of its reduced reliability under severe conditions such as at high temperatures or under high stress. To improve the reliability of Sn–Cu, additions of Ni, Au, and Ag have some effect by refining its microstructure. The JEITA (the former JEIDA) program roadmap for lead-free soldering is given in Table 24. Lead-free reflow soldered products are being introduced earlier than those requiring wave soldering. This is primarily attributable to the problems associated with fillet-lifting and landlifting in wave soldering which are difficult to be overcome until all components are plated with lead-free alloys. The other key point for the promotion of lead-free soldering is the heat-resistance of components and PWBs. They must be improved to be compatible with high-temperature, leadfree solders, such as Sn–Ag–Cu. This is a key issue that prevents the production of lead-free assemblies. Sn–Zn alloy paste can be used for some limited applications, particularly those requiring low processing temperatures. A data and instruction book for Sn–Zn solders will be published by JIEP in 2002.
V. THE IDEALS PROJECT A. Project Organizations and Participants Beginning in May 1996, the European Community funded a major project on ‘‘Improved Design Life and Environmentally Aware Manufacturing of Electronics Assemblies by Lead-Free Soldering (IDEALS)’’ under the BRITE/EURAM program; Project BE-1994 from May 1996 through April 1999. The total effort was approximately 30 man-years. The consortium membership consisted of material suppliers, end users, and a university institute, as listed in Table 25.
696
HANDWERKER ET AL.
TABLE 25
Materials Suppliers, End Users, and University Participants in the IDEALS Consortium
Participating organizations GEC-Marconi Materials Technology, Hirst Division, GB-project coordinator PHILIPS Centre for Manufacturing Technology, NL Siemens AG, Corporate Production & Logistics, DE Witmetaal BV Alpha-Fry Naarden, NL Multicore Solders, GB National Microelectronics Research Centre, University College, Cork, IE Soltec BV, Oosterhout, NL subcontractor FineTech Gesellschaft fuˆr ElektronikTechnologie, Berlin, DE
Primary technical contacts David Jacobson, James H. Vincent, and Martin Harrison Peer Langeveld, Erik de Kluizenaar, and Daniel Schwarzbach Hans-Ju¨rgen Albrecht and Gunnar Petzold Mohammad Biglari and Martin Oud Malcolm Oddy and Roger Billham Hector Steen and Malcolm Warwick Frank Stam, Elaine Davitt, and Liam Kehoe
B. Project Goals and Major Activities The objectives of this project were.:
To develop both reflow and wave soldering processes using lead-free solders, board and component metallizations (i.e., totally lead-free systems) with fluxes that are substantially free of volatile organic compounds (VOCs). To devise repair and rework procedures with novel lead-free, flux-cored wire. To establish the properties of lead-free solders relative to the Sn–Pb eutectic alloy with respect to their mechanical and thermomechanical performance. The project consisted of the major activities listed in Table 26. In the three years of the project, several candidate solders listed in Table 27 and their matched fluxing systems, board finishes, and component metallizations were selected and tested in extensive assembly trials. The entire process technology was expected to meet all European environmental and product recycling legislation at the end of the twentieth century. This specifically applies to metals that replace the lead (Pb) content of solder alloys and all the other materials, products, and waste generated by the manufacturing processes or in any potential recycling routes. Results of the project in terms of the improved solders, fluxes, and processes should be applicable in European industry immediately following the end of the project [15–25]. A key element to this objective is
TABLE 26
Major Activities in the IDEALS Pb-Free Solder Project
Major Activities in the IDEALS Pb-Free Project Development of materials, lead-free alloys, VOC-free fluxes, lead-free and VOC-free pastes, lead-free flux-cored solder wire and lead-free metallizations, and characterization of these materials Process development and verification for wave soldering, reflow soldering, and manual/repair soldering Extended reliability assessments of lead-free soldered joints A limited environmental life cycle impact study of lead-free wave and reflow soldering processes
MAJOR INTERNATIONAL LEAD (PB)-FREE SOLDER STUDIES
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TABLE 27 Lead-Free Solders Selected by the IDEALS LeadFree Consortium Lead-free alloys Sn–3.8Ag–0.7Cu Sn–3.8Ag–0.7Cu–0.25Sb Sn–5Bi–2Sb–1Ag
Solder application Reflow soldering General purpose wave soldering Single-sided wave soldering only
that the soldering processes be developed utilizing current equipment, which is to be modified only if necessary to satisfy the project’s requirements.
C. Background/Initial Considerations Several participants had experience in lead-free soldering research before the start of the project. PHILIPS CFT, together with Witmetaal, had explored the Sn–0.7Cu eutectic alloy for wave soldering and had come to the conclusions that a minimum wave solder bath temperature of 275jC was required for this high-melting alloy and that the fatigue life of Sn–0.7Cu joints was, on average, only 0.6 times that of Sn–40Pb joints. GEC-Marconi and Multicore had participated in ‘‘Alternative Solders for Electronic Assemblies’’; DTI Sponsored Project 1991–1993, which concluded that bismuth-containing alloys were not acceptable because of their propensity for fillet lifting [5]. Later on, during the IDEALS project, it became clear that relatively high reflow temperatures cannot be avoided with bismuth-free lead-free solders. Therefore, some process trials were conducted to determine what reductions in the reflow peak temperature were possible with bismuth-containing solders.
D. Alloys Selected for Investigation Based on the previously collected information, three eutectic solders were chosen for investigation: Sn0.7Cu, Sn3.5Ag, and Sn3.8Ag0.7Cu. Thirteen variations of these alloys were prepared by Multicore and Witmetaal, including the eutectic compositions, off-eutectic compositions, and eutectic compositions doped with minor additions of antimony, bismuth, or nickel. The doping was an attempt to improve properties such as wetting capability, microstructure, and mechanical properties. After initial examination, the project activities focused on a feasibility study involving two alloys, Sn–3.8Ag–0.7Cu and Sn–5Bi–2Sb–1Ag to determine the process windows and make a reliability assessment. This was followed by a process verification study consisting of a large number of parts for statistical significance. Based on the results of the process verification study, a mass-production wave soldering line was installed at PHILIPS in 1998 and a reflow production line at GEC-Marconi in 1999.
E. Property Investigations 1. Solderability The solderability characteristics of the alloys in Table 27 on cleaned copper, immersion silver (Alpha Level, trade mark of Alpha Metals), Sn 0.7Cu, Ni/Au, and Ni/Pd coated coupons were studied and compared with those of Sn–Pb eutectic solder. More consistent and reproducible results were obtained by using a mildly activated rosin flux containing 0.5% chloride than using a pure rosin flux (both flux types conform to standard IEC60068-2-20). With the activated flux, all of the candidate solder alloys exhibited promising results if the solderability test temperatures were equal to or greater than 250jC. The wetting characteristics were similar at the same excess temperature above the liquidus temperature so that the alloy with the lowest melting point (Sn– 3.8Ag–0.7Cu) performed best at the set temperature of 250jC. Wetting times are typically 1F0.2 sec at liquidus temperature +25jC, 0.8F0.1 sec at liquidus temperature +35jC, and 0.6F0.1 sec at liquidus temperature +50jC. Additions of antimony, bismuth, and nickel were determined to
698 TABLE 28
HANDWERKER ET AL. CTE Results Obtained by TMA Analysis of Solder Alloys Temperature Range (jC)
Solder Alloy
50 0 50 50 100 50 100 50 100 30 120
Sn–37Pb
Sn–0.7Cu–0.5Sb Sn–3.5Ag–0.7Cu (96SC) S Sn–3.5Ag–0.7Cu–0.25Sb (SACS) Sn–5Bi–2Sb–1Ag (SBA+)
to to to to to to to to to to to
CTE (ppm/jC)
0 50 150 100 200 100 190 100 190 100 180
21.6 28.1 25.4 17.4 22.1 20.4 22.0 17.4 20.9 21.2 22.9
CTE samples (7 7 7 mm) were machined out of larger ingots. As metals have different mechanical properties in different crystallographic orientations, probably, large parts of the variations are due to the solidification textures of the ingots.
have only a minor effect on solder wetting kinetics. For example, studies of the effect of Sb additions to Sn–3.8Ag–0.7Cu performed at Multicore and Witmetaal using various techniques revealed a slight effect on wetting. However, it was noted that any Sb addition in the range of 0.25–2% Sb produced a significant grain refining effect. A general finding in this study with the lead-free alloys is that solder spreading is slightly less than with Sn–Pb eutectic solders, but was judged to be adequate for all alloys examined. 2. Mechanical and Physical Properties Physical properties of the alloys were measured, mainly at NMRC. Tables 28–31 list selected physical and mechanical properties of eutectic Sn–Pb and lead-free solders, such as coefficient of thermal expansion (CTE), elasticity, yield stress, and plastic behavior. Tables 28–31 illustrate a significant point about lead-free solders as compared with Sn–Pb. Eutectic Sn–Pb is more ductile at low temperatures, while the lead-free solders are much more ductile at temperatures of 100jC and greater. The effect of Bi in hardening the base Sn–3.8Ag–0.7Cu alloy is noted in Table 29. (Data in Tables 30 and 31 should only be used to compare temperature trends; because the specific values obtained are dependent on test conditions, therefore the data reported in the literature may vary.) TABLE 29
Young’s Moduli of the Alloys Selected by the IDEALS Consortium Young’s Modulus, E (GPa)
Solder Alloy Sn–37Pb Sn–0.7Cu–0.5Sb Sn–3.5Ag–0.7Cu Sn–3.5Ag–0.7Cu–0.25Sb Sn–5Bi–2Sb–Ag (96SC)–5Bi
At 25jC
At 50jC
At 100jC
Vickers Hardness (Hv)
32 (2) 45 (3) 46 (3) 44 (2) 56 (3) —
32 (2) 43 (4) 44 (3) 42 (2) 49 (1) —
18 (2) 37 (2) 35 (3) 33 (3) 44 (3) —
16F1 — 17F1 — — 33F2
Data were obtained using the three point bending mode of DMTA on 1-mm-thick slabs of lead-free alloys, together with hardness values recorded for joints.
MAJOR INTERNATIONAL LEAD (PB)-FREE SOLDER STUDIES TABLE 30 Solder Alloy
Yield Stress (N/mm2) for Different Temperatures Sn–37Pb
Sn–3.5Ag
Sn–0.7Cu
Temperature (jC) 23 50 75 100 125 150
699
Sn–0.7Cu– 0.5Sb
Sn–3.8Ag– 0.7Cu
Sn–3.8Ag– 0.7Cu–0.25Sb
Sn–3.8Ag– 0.7Cu–0.5Sb
48.0 34.1 23.5 15.7 11.2 9.8
36.4 26.2 20.4 14.8 12.0 9.8
Yield Stress (N/mm2) 32.5 24.6 18.3 11.8 6.6 3.0
39.9 30.8 22.1 14.8 10.2 8.9
27.5 21.4 15.9 12.6 9.9 8.1
47.6 34.1 26.8 15.6 11.7 8.8
47.1 33.9 23.2 18.4 10.8 8.5
3. Solidification and Aged Structures The solidification structures of all high-Sn lead-free alloys consist of a large fraction of primary tin dendrites with the remaining fraction consisting of eutectic structures filling the spaces between the dendrites (Figure 17). For the alloys examined in this study, this fraction consisted of a fine ternary dispersion of Sn, Ag3Sn and Cu6Sn5. The largest eutectic fraction was obtained with the Sn–3.8Ag–0.7Cu alloy (about 40% volume fraction). It was thought that the large size of the primary tin crystals might reduce the fatigue life of solder joints, therefore several alloying trials were performed for grain refinement. The only alloying element that produced finer grains and did not impair the wettability or the processing characteristics of the lead-free alloys examined was antimony. Antimony did not preferentially oxidize in the wave solder baths to a significant extent. Accordingly, 0.25% mass fraction Sb was added to the Sn–3.8Ag–0.7Cu alloy for wave soldering studies; but Sb additions were not considered for reflow soldering. Thermal aging (125jC, 1000 hr) of Sn–3.8Ag–0.7Cu solder pellets soldered onto copper coupons resulted in coarsening of the interdendritic eutectic fraction and growth of the intermetallic compound copper–tin layer formed on the copper substrate. The intermetallic compound growth rate on the copper substrate was approximately 60% of Sn–40Pb solder on copper and similar to pure tin and Sn–3.5Ag. Preliminary temperature cycling tests did not reveal additional degradation. Based on these findings, it was concluded that unexpected degradation mechanisms and failure modes were highly improbable with Sn–3.8Ag–0.7Cu joints. Therefore, this alloy was chosen for further study as the general-purpose solder candidate. Mainly because of reduced price, i.e., less silver than other alloys, the alloy Sn–5Bi–2Sb-1Ag was developed for wave soldering by Witmetaal. This alloy was also extensively evaluated. In
TABLE 31 Solder Alloy
Plastic Behavior (N/mm2) for Different Temperatures Sn–37Pb
Sn–3.5Ag
Sn–0.7Cu
Temperature (jC) 23 50 75 100 125 150
Sn–0.7Cu– 0.5Sb
Sn–3.8Ag– 0.7Cu
Sn–3.8Ag– 0.7Cu–0.25Sb
Sn–3.8Ag– 0.7Cu–0.5Sb
28.0 25.1 18.3 9.8 6.5 7.0
41.0 20.7 17.1 8.7 7.1 4.9
Plasticity (N/mm2) 50.1 24.6 23.1 1.8 1.1 0.3
33.0 27.7 10.7 9.0 4.9 3.2
14.9 10.5 9.3 8.8 5.4 5.0
35.9 20.1 15.3 4.7 3.7 3.6
38.3 20.4 13.1 8.5 2.5 2.5
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FIG. 17 Optical micrograph showing the microstructure of Sn–3.8Ag–0.7Cu–0.25Sb solder joint, consisting of primary Sn dendrites separated by finely dispersed eutectic phases; estimated volume fraction of eutectic is about 40%.
principle, it exhibits a similar solidification structure, but was observed to produce more porosity than other Pb-free alloys examined, because of its large melting range (about 180–220jC). 4. Development of Soldering Materials Experimental soldering products were developed for these compositions: solder bar for wave soldering, solder pastes for reflow soldering, and flux-cored solder wires for manual and repair soldering. VOC-free solder paste media and wave soldering fluxes were also developed. All of the paste media assessed in the project were established commercial or development products designed for use with tin–lead component and board surface finishes. Each enabled solder joints to be made that in most respects were acceptable according to established inspection criteria. A common finding was that the slightly elevated soldering temperature compared to tin–lead provides sufficient flux activity to overcome the reduced spreading tendency of the lead-free solder alloys. 5. Board and Component Finishes Two mature lead-free board finishes were available during the course of the project, copper with an organic solderability preservative (Cu-OSP), and electroless nickel (with 8% mass fraction phosphorus) with an immersion gold flash (Ni/Au). During the course of the project, immersion silver (Alpha LevelR) also became available. Experiments were performed utilizing hot air solder leveling (HASL) of eutectic tin–copper (Sn–0.7Cu). Board finishes of Cu-OSP, Ni/Au, and immersion Ag were successfully applied. Components with lead-free finishes were not generally available at the time the project was conducted. Ceramic multilayer capacitors (CMCs) and dual in-line IC packages (DIPs) have been available with electroplated pure tin for many years. CMCs are also available with fired AgPd metallization. Some surface mount ICs were supplied with Ni/ Pd. Many lead-free dummy components were developed for this project, those components selected and their Pb-free finishes are listed in Table 32.
F. Wave Soldering Process Studies A wave soldering process study was conducted to establish the processing window for three Pbfree alloys. Realistic wave soldering process trials must be executed on state-of-the-art production equipment. This requires about 800 kg of solder per alloy trial, and changing to another alloy
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TABLE 32 Lead-Free Dummy Components and Their Pb-Free Finishes Selected for the IDEALS Consortium Components CMCs Chip resistors SMD transistors SO package types QFP package types CMCs QFP-100 (0.65 mm pitch) MELF diodes SO package types QFP package types SO package types QFP package types Several through hole mounting type components
Finish Electroplated pure tin
Fired AgPd Plated pure tin Hot-dipped tin Electroplated Sn–3Bi
Electroplated Ni/Pd Conventional Sn–Pb changed to lead-free by a molten solder dip in Sn–0.7Cu. Conventional Sn–Pb because no lead-free alternatives were available.
requires a thorough intermediate rinse of the solder pot with pure tin (also 800 kg). Consequently, only a very limited number of alloys could be investigated in production-based process trials. These alloys were eutectic Sn–0.7Cu, Sn–3.8Ag–0.7Cu–0.25Sb, Sn–5Bi–2Sb–1Ag, and Sn–40Pb for comparison. 1. Test Vehicles For wave soldering trials, a multitude of specially designed test boards as well as production boards were utilized. Only the most important board types are described in this chapter. All of these boards were used for process trials as well as for extended reliability assessments. Dedicated test boards and printed circuit boards used in consumer and lighting electronics manufacturing plants were utilized for the wave soldering experiments. All of these boards accommodated a wide range of surface mount component types together with many different wired components for through-hole mounting. The single-sided test board used for the systematic process parameter investigation and for the large-scale process verification, both with Sn–3.8Ag–0.7Cu–0.25Sb solder, shown in Figure 18a and b. Board characteristics are: size 350250 mm, single-sided FR2 paper-phenolic laminate, Cu-OSP finish, populated with a multitude of surface mounted components on the wave solder side and components for through-hole mounting. In many cases, the components were arranged as closely packed as the design rules allowed (critical with respect to skipped joints and short circuits). The most critical surface mount component was a QFP100 package with a lead pitch of 0.65 mm, positioned under 45j with respect to the transport direction. An almost identical board with plated holes was designed to systematically assess the process parameters. This board was made of FR4 glass-epoxy laminate and had a Cu-OSP finish. A second board for through-hole assembly trials was a production board with six identical circuits, as shown in Figure 19. The board characteristics are: size 350200 mm, double-sided FR4, CuOSP finish, and populated with a multitude of surface mounted components and components for through-hole mounting. A novel aspect of this board was the large thermal demand caused by the large areas of copper on the top side, connected to some of the plated holes. This provided valuable information about thermal design sensitivity.
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FIG. 18 The large single-sided test board utilized for process parameter trials and large-scale verification tests with Sn–3.8Ag–0.7Cu–0.25Sb. (a) Top side. (b) Bottom side.
2. Preliminary Trials Initial trials were performed on a Soltec Galaxy wave soldering machine, using best engineering judgment process parameters; visual inspection and cross sectioning were utilized for evaluation of joint quality. Following the initial trials, a full factorial 33 process parameter variation experiment around the values found in the preliminary experiments was performed on a state-ofthe-art Vitronics-Soltec 6622CC Deltawave soldering machine with a nozzle-spray fluxing unit and a three-stage preheating zone. The preheating temperature, the solder bath temperature, and the contact time with the solder wave were the three parameters varied at three levels. Solder joint quality was evaluated visually, by micro-X-ray inspection, and by joint cross sectioning. Extensive reliability testing was also conducted. 3. Large-Scale Process Trials Thereafter, large-scale process trials were executed with a mix of hole-mounted and surfacemounted components on dedicated test boards, containing many ‘‘difficult’’ components and combinations of component designs, utilizing production boards. Finally, one production line was completely changed over to Sn–5Bi–2Sb–1Ag. Mass production was successfully achieved
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FIG. 19 Double-sided production board with plated through holes used for systematic process parameter trials. (a) Top side. (b) Bottom side.
with a variety of single-sided printed boards with a mixed population of through-hole-mounted and surface-mounted components at PHILIPS Lighting Electronics & Gear since mid-1998. a. Systematic Process Parameter Study. As with any assembly process, wave soldering requires stringent control of the process parameters. Typical values for Sn–40Pb soldering are as follows: a preheating temperature of (115F15)jC, solder bath temperature of 250jC, and a total contact time with the two waves between 2.2 and 3 sec, depending on the type of board (singlesided, double-sided with plated holes, multilayer). Soldering with higher melting temperature lead-free solders requires higher soldering temperatures and perhaps higher preheating temperatures and longer contact times. In preliminary experiments with Sn–0.7Cu (Tm=227jC), it was shown that at 250jC, solder freezes on component leads without really wetting them (Figure 20a). To provide proper wetting, it was determined that Sn–0.7Cu required a solder bath temperature of at least 275jC (Figure 20b), which could cause damage to components and boards and sagging of PWBs.
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FIG. 20 Optical micrograph of a vertical cross section of a through-hole fillet with Sn–0.7Cu joints. (a) When soldered at 250jC, the solder was mainly frozen on the lead without wetting it, which become clearly visible after being subjected to several thermal cycles. (b) When soldered at 275jC the solder wetted the lead well. PARAMETERS FOR Sn–3.8Ag–0.7Cu–0.25Sb. For Sn–3.8Ag–0.7Cu–0.25Sb (Tm=217jC, 10jC lower than Sn–0.7Cu) and with Sn–5Bi–2Sb–1Ag, it is obvious that the minimum required solder bath temperature should be somewhere between 250jC (as used for Sn–40Pb) and 275jC (as required for Sn–0.7Cu). To assess the minimum required process parameters, a full factorial 33 parameter variation experiment was performed with the alloy Sn–3.8Ag–0.7Cu–0.25Sb on a dedicated single-sided test board and on a double-sided board with plated through-holes (see Section V.F.1), using the process parameters noted in Table 33. This trial was performed by using a standard, isopropanol-based, low-residue flux. The visual inspection criteria are similar to but not identical to those for Sn–Pb soldered joints: adequate wetting with sound and smooth solder surfaces is required for Sn–Pb and Pb-free solders; a shiny surface is not required for Pb-free solders. For Sn–Pb eutectic solder, a matte surface can be indicative of poor wetting. For high-Sn alloys, a shiny surface is not possible because of the dendritic structure characteristic of these alloys, and a matte surface is not an indicator of poor wetting. Lead-free joints contain a substantial fraction of primary tin dendrites, which form rounded ends that terminate at the outer surfaces of solder joints. The rounded dendrite ends are responsible for the matte surface appearance as seen in Figure 21. The resulting minimum values required for wave soldering with Sn–3.8Ag–0.7Cu–0.25Sb are presented in Table 34. For wave soldering single-sided boards utilizing Sn–5Bi–2Sb–1Ag, the same values can be applied. PREHEATING. The preheating temperature was determined to have a negligible influence on soldering quality. However, with VOC-free, water-based fluxes, the evaporation of water during the preheating process step requires considerable heat, which puts a very high demand on the soldering equipment. In that case a preheating temperature of 130jC was required to remove
TABLE 33 A Full Factorial 33 Parameter Variation Experiment Performed with the Alloy Sn– 3.8Ag–0.7Cu–0.25Sb on a Dedicated Single-Sided Test Board and on a Double-Sided Board with Plated Through Holes Variables in Full-Factorial Analysis Preheating temperature on soldering side Solder bath temperature Total contact time with the two solder waves
Condition 1
Condition 2
Condition 3
100jC 250jC 2.5 sec
115jC 260jC 3.0 sec
130jC 265jC 3.5 sec
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FIG. 21 Typical appearance of a wave soldered joint (Sn–3.8Ag–0.7Cu–0.25Sb) on a chip resistor at three different magnifications. (a) The joint surface is rough resulting in a matte appearance. (b) Microroughness is typical of high-Sn, dendritic structures. (c) There is surface porosity resulting from solidification, but the porosity does not extend far into the solder joint.
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TABLE 34 Minimum Values Required for Wave Soldering with Sn–3.8Ag– 0.7Cu–0.25Sb and for Wave Soldering of Single-Sided Boards Utilizing Sn–5Bi– 2Sb–1Ag For double-sided boards with plated holes Solder temperature Soldering time Preheating temperature
250.jC 260.jC 265jC z3..5 sec z3..0 sec z2.5 sec z100.jC (130jC for water-based flux)
For single-sided boards with plain holes Solder temperature Soldering time Preheating temperature
250.jC 260jC 265jC z3..0 sec z2.5 sec z2.0 sec z100.jC (130jC for water-based flux)
all the water. If wet printed circuit boards enter a solder wave, the water boils explosively, i.e., like water on a frying pan, and many large solder balls typically form on the top side of the boards. This was remedied in the preheating step: the three preheating zones of the wave soldering machine were optimized by using first an IR unit, followed by two hot-gas blowers with increased air velocity to quickly remove the water vapor. ASSESSMENT OF Sn–5Bi–2Sb–1Ag. With the Sn–5Bi–2Sb–1Ag alloy, a similar parameter study was performed in a manufacturing environment using production boards and dedicated test boards with a component spectrum representative of products in that business. This alloy, with its large melting range, produced extreme solder lifting on boards with plated through-holes. Fillet lifting was not observed with this alloy on single-sided boards. The minimum process parameters required for Sn–3.8Ag–0.7Cu–0.25Sb also apply to Sn–5Bi–2Sb–1Ag. The drossing rates in air and nitrogen with Sn–3.8Ag–0.7Cu–0.25Sb and Sn–5Bi–2Sb–Ag in a state-of-the-art wave soldering machine are similar to those observed with Sn–40Pb, in air and nitrogen. Boards of both process parameter studies were used for extended reliability assessments. b. Large-Scale Verification and Industrialization Study. A large-scale verification was performed with Sn–3.8Ag–0.7Cu–0.25Sb on the same dedicated single-sided test board, designed with many components arranged in critical combinations (Section V.F.1). The component finishes are listed in Table 35. The Vitronics-Soltec 6622CC Deltawave soldering machine was used, equipped with a foam fluxer, air knife, three-zone preheating (IR/hot gas/hot gas), dual wave (chip wave and solder wave) and nitrogen atmosphere (oxygen content less than 100 ppm). The VOC-free foam flux, developed by Alpha-Fry technology in the framework of the project, was applied. The primary process parameters were: (a) preheating to 130jC when entering the first wave; (b) solder bath temperature of 250jC; and (c) contact times with the solder waves of 0.75 and 2.30 sec (total 3.05 sec). Approximately 110 boards with a total of more than 250,000 joints were soldered. The joint defect rate was about 1000 ppm. In principle, this is a high value for wave soldering. However, 60% of this value was ascribed to an intentionally introduced design error, a row of parallel-placed, wired resistors, included to test the sensitivity of the process to form solder bridges. An additional 10% could be attributed to placement and material errors and 30% to the actual soldering process, mainly skipped joints on SOT23 components and bridges between R0805 components positioned in double rows at the trailing end of the board. Within statistical error, these results were the same as obtained earlier with Sn–40Pb. c. Mass Production. After the systematic process parameter study with Sn–5Bi–2Sb–1Ag alloy, followed by a thorough reliability assessment, it was decided to start mass production on single-sided boards (Figure 22) using the assessed minimum process parameters, but without performing a large-scale verification for this alloy. During the first few months, it became clear that these were minimum values indeed. Any deviations from the minimum primary process parameters caused huge quality problems. After having gone through this learning period, the
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TABLE 35 Components and Component Finishes Used in Large-Scale Assembly Verification Performed with Sn–3.8Ag–0.7Cu–0.25Sb on Dedicated SingleSided Test Board Components
Finishes
R1206 R0603 SOD80 Minimelf 0402 SOT23 QFP100 Potter foil capacitor Multilead connector FET transistor Inductor coil C0805
Electroplated pure tin
Hot-dipped Sn–0.7Cu
All other components
SnPbx (5<x<50)
Fired AgPd
process became very stable. The first pass fall off rate was 30 ppm (very good for wave soldering) and no customer complaints due to the change to lead-free soldering were reported. d. Thermal Design Considerations. Wave soldering with Sn–40Pb is performed at 250jC, a temperature difference of approximately 67jC between melting point and soldering temperature. This provides a comfortably large process window, i.e., allowing a sufficient tolerance in thermal board design and process parameter variations. Soldering with Sn–3.8Ag–0.7Cu–0.25Sb at 265jC is typically performed with a temperature difference of only 48jC. Moreover, 265jC is the minimum operating temperature and leaves no tolerance for process variations. Process optimization and control must be very stringent and designs require a minimum amount of connected copper at the top side of double-sided boards with plated through-holes. Thermal
FIG. 22 First mass-produced, lead-free wave soldered product. (a) Top side. (b) Bottom side.
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design rules must be strictly obeyed, otherwise the solder rise in plated through-holes will not take place (Figure 23). e. Multilayer Boards. For multilayer boards, the minimum process conditions must also be defined. Usually, multilayer boards require even more heat. Adhering to thermal design rules is even more important than for double-sided boards. The same arguments hold for Sn–5Bi–2Sb– 1Ag solder. Moreover, there is a large risk of solder bridging if the required minimum process conditions and thermal design rules are violated. But it can be carried out, with the same process yield as Sn–40Pb solder, as demonstrated by a PHILIPS production site, which has performed lead-free mass production very successfully since mid-1998. f. VOC-Free Flux Development. In the project, two VOC-free (water-based) wave soldering fluxes were developed, a foam flux and a spray flux. It was demonstrated that spray application was a viable option for lead-free assembly. A foam application version proved more difficult to develop, but in the end it was shown to be viable as well. Drying the flux was critical, as mentioned above. Foam fluxing applies more liquid to a board than spray fluxing. Therefore, spray fluxing is easier to control because the quantity of water that must be evaporated is significantly less than with foam fluxing. The SIR performance of the flux residues was evaluated by using ANSI-IPC J-STD-004 and Bellcore standard test procedures. The boards passed the JSTD-004 SIR specification, but barely failed the more severe Bellcore specification. This difference using the two tests was a general property of the low-residue, no-clean fluxes for wave soldering available during this project.
G. Reflow Soldering The central issues were to develop pastes for lead-free soldering and to establish the time– temperature process window that would enable the production of joints that pass visual inspection and exhibit metallurgical integrity. Various solder pastes were developed and assessed. Only one simple daisy-chained board was designed and used as the test vehicle (described in Section 7.4.5) for all reflow trials. A systematic process parameter study was performed, but large-scale process verification with the preferred parameter set was not performed. 1. Solder Paste Development Solder pastes must fulfill many requirements, such as rheological properties, soldering capability, corrosion resistance, and reliability. The compositions and recipes are proprietary to the various paste suppliers. Nevertheless, there are some common aspects and characteristics among Pb-free pastes. It was determined that no-clean paste mediums for Sn–Pb alloys were generally adequate for use with Sn–3.8Ag–0.7Cu. However, the limited spread of lead-free solder alloys compared with Sn–Pb alloys requires that the no-clean pastes be optimized. Furthermore, there was the
FIG. 23 Insufficient solder rise of lead-free solder into a plated through-hole because of insufficient temperature at the top side. The design consists of an excess of connected copper on the topside of the board, thus a thermal barrier is required.
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issue of water evaporation in VOC-free media as noted above. The latter can be improved with high-boiling-point solvents (nonvolatile at room temperature). Lead-free solder paste optimization includes several aspects. A high solids content improved the tolerance to the high preheat and reflow temperatures used. The presence of high boiling solvents resulted in increased void formation in joints (Figure 24). Also, the spreading of lead-free solder was observed to be limited, particularly on copper. A significant outcome of the work was the development of several solder pastes that solder well in air. However, soldering in an inert (nitrogen) atmosphere provided more freedom in selecting solder pastes. 2. The Time–Temperature Process Window The printed wiring board utilized for reflow process development contained four daisy-chained QFP-100 (pitch 0.65 mm) IC dummies as the largest component. The other components were all small, i.e., chip resistors and capacitors, sizes 1206, 0805, and tantalum capacitors, size ‘‘C.’’ The initial assembly trials were conducted with a basic IR reflow oven, and a single profile was used in the assembly of the boards to establish and validate the assessment methodology. Some typical values were: preheat temperature of 150jC, reflow peak temperature at the coldest spot of 232jC, and reflow peak temperature on the hottest spot of 253jC. This profile provided adequate solder joints for the reliability assessments. However, the large DT of >20jC between the different component types made it impossible to study the reflow soldering process window in the detail required. It was decided to conduct the process window trials with a forced-gas convection reflow oven because the industry was rapidly adopting this as the oven of choice. The process window is the envelope consisting of both the maximum allowable temperature– time profile [i.e., resulting in no damage to printed circuit boards (PCBs) and components], and the minimum temperature profile required to produce good-quality soldered joints. Temperature profiles for all component solder joints must be within this envelope. The minimum peak temperature typically required for lead-free solders is considerably higher than for Sn–40Pb solder. However, the temperature above which damage occurs to components and PCBs remains the same. Therefore, the process window for lead-free soldering is small compared with Sn–40Pb. a. Parametric Study. In a systematic reflow process parameter study with Sn–3.8Ag– 0.7Cu, the peak temperatures and times above the solder liquidus temperature were varied as presented in Table 36. In all cases, the time from room temperature to reflow peak temperature was 260 sec. The full set of eight reflow profiles was applied on boards with Ni/Au or boards with immersion tin. For each condition, six boards were assembled, inspected, and subjected to reliability testing. Cu-OSP and immersion silver were included in more limited parallel trials.
FIG. 24 Comparison of void content in QFP gull-wing solder joints for 96SC alloy with two solder pastes. [(a) Worst case. (b) Best case]. The voids occurred at the solder pad–older interface. The presence of high boiling solvents was the determining factor in void creation in the IDEALS study.
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TABLE 36 Peak Temperatures and Times Above the Solder Liquidus Temperature Used in a Systematic Reflow Process Parameter Study with Sn–3.8Ag–0.7Cu Bare Board and Small Components
QFP-100 Leads
Low preheating settings: 160C for 100 sec Temperature above liquidus (jC) Time above liquidus (sec)
9 29
13 33
23 48
34 54
2 17
6 22
19 40
27 48
High preheating settings: 175C for 100 sec Temperature above liquidus (jC) Time above liquidus (sec)
9 34
13 38
25 52
34 57
6 28
6 28
19 48
30 53
b. Study Findings. Visual inspection criteria were sometimes compromised. The opinion of some participants was, ‘‘Wetting was limited in some cases and the cosmetic aspects of some joints were less than perfect, but the ultimate test of acceptability, the reliability tests, demonstrated that these joints were reliable in service.’’ This opinion was not universally accepted within the project consortium, mainly because the approach could not guarantee an adequate process yield without proof via a thorough large-scale verification. Nevertheless, based on the cited acceptance criterion, a general soldering result was that Sn–3.8Ag–0.7Cu is acceptable on all board finishes with Sn-based component finishes utilizing a reflow peak temperature of 227jC, and a minimum time above 217jC of 10 sec. However, it is recognized that in practice, this margin between melting point and reflow peak temperature is too small to account for all the tolerances and fluctuations in measurements and process conditions. For a well-controlled process, a minimum of 235jC and dwell time of 30 sec above 217jC are more realistic values. Unfortunately, a large-scale verification with one optimum set of process parameters was not executed for reflow soldering. Nevertheless, one production line was set up for lead-free reflow soldering (still utilizing mostly lead-containing metallizations). Details about the process parameters and first-pass defect rate were not released. Once it was obvious that the reflow peak temperatures were to be about 30jC higher than for Sn–40Pb soldering, it was also realized that the moisture sensitivity level (MSL) of IC packages would become a major issue in lead-free reflow soldering. Since then, history has shown that this is indeed the case. Therefore, a minimum profile study was performed with two bismuthcontaining alloys, Sn–3.8Ag–0.7Cu with 2% and 5% mass fraction of Bi, respectively. The addition of bismuth lowered the required minimum reflow peak temperatures by 4 and 8jC, respectively. However, this temperature reduction was not sufficient to compensate for the negative effects of bismuth additions, such as a large melting range and poorer mechanical and fatigue properties than Sn–3.8Ag–0.7Cu.
H. Solder Joint Rework 1. Test Board The same printed circuit board was utilized for both reflow development and rework/repair soldering trials (see Section 5.7.1 of Chapter 7). The test circuit board contained the following representative range of components: twenty 1206 resistors and 0805 resistors, eight 1206 capacitors and type ‘‘C’’ Ta capacitors, and four QFP100 packages (pitch, 0.65 mm) with internal daisy-chain connections for continuity testing. A populated FR-4 board (dimensions of 114 102 1.6 mm) is shown in Figure 25, with the daisy-chain connections clearly visible for the 0805 resistors located near the four board corners. The components were arranged to form 62 electrical circuits, with each circuit containing four equivalent components connected in series to facilitate the continuity testing of the soldered joints.
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FIG. 25 A populated test board used throughout the IDEALS project for reflow and repair evaluations.
2. Rework Trials Flux-cored wires of Sn–0.7Cu, Sn–3.5Ag, and Sn–3.8Ag–0.7Cu were fabricated by using Sn–Pb production methods. Cored wire down to 0.5 mm in diameter was produced without difficulty. A detailed study was made of available repair equipment (e.g., hot gas, hot bar, soldering iron), and particular attention was paid to the issue of heat transfer methods for unsoldering and remaking joints with higher melting points typical of lead-free solders. The effect of higher temperatures on the immediate area surrounding a joint and on the PCBs was considered. In consideration of the requirements, it was concluded that industry-standard equipment is suitable for the task. The rework trials involved the removal of components from populated test-boards (soldered with Sn–3.8Ag–0.7Cu), followed by reflow or soldering of replacement components in nitrogen without additional solder. This was repeated up to 12 times and the results indicated that the strength and reliability of the joints are similar to original build parts over the range of rework iterations investigated.
I. Reliability Assessment Reliability assessment was a major aspect of the IDEALS project. The primary degradation mechanisms and failure modes are thermomechanical solder fatigue, fatigue by vibrational loading, fracture by mechanical shock and degradation by growth of intermetallic reaction layers at interfaces. The reliability test program consisted of temperature cycle testing, vibration and shock testing, and metallurgical analysis by cross sectioning. Test samples were the boards described in Section 7.4.5 with a wide variety of through-hole-mounted and surface-mounted components. 1. Temperature Cycling Most of the temperature cycling tests were performed according to standard IEC 60068-2-14, referred to as Test Condition A (Na) and Test Condition B (Nb) for twin and single chambers, respectively. Liquid-to-liquid temperature shock and power cycling were performed according to the test conditions in Table 37. a. Conditions. The temperature cycles applied to wave soldered boards were: (Test Condition A) 20jC/+100jC with 20/20 min hold time and (Test Condition B) 20jC/ +125jC with a 2-hr cycle. Power cycling and liquid-to-liquid testing were performed only with the reflow boards. Degradation was characterized by visual inspection, cross sectioning, optical and scanning electron microscopy (SEM), and pull/shear tests.
712 TABLE 37
HANDWERKER ET AL. Test Conditions for Liquid-to-Liquid Temperature Shock and Power Cycling
Test Type
Tmin (jC)
Tmax (jC)
No. of cycles
Single chamber air Single chamber air
20 20
100 125
2000 3500
Twin chamber air
20
100
4000
Twin chamber gas/gas
40
125
3000
Twin bath liquid/liquid
20
125
3000
Power cycling
+25
110
5000
Cycle time 1-hr cycle, f20-min dwells 2-hr cycle, asymptotic heating and cooling curves 1-hr cycle, rapid transfer, 30-min dwell at each extreme 1-hr cycle, rapid transfer, 30-min dwell at each extreme 7-min cycle, rapid transfer, 3-min dwell at each extreme f20-min cycle, asymptotic heating and cooling, 10-min dwell at 110jC
b. Findings. Results of the degradation and fatigue life study of the wave and reflow soldered joints are as follows. Soldered joints of Sn–0.7Cu and Sn–5Bi–2Sb–1Ag deform mainly along the grain boundaries of the primary tin phase and fracture along these grain boundaries (Figure 26). The fatigue life of Sn–0.7Cu in these tests was relatively short, 0.6 of similar Sn–40Pb joints. However, the fatigue life of Sn–5Bi–2Sb–1Ag joints was relatively long, with completely lead-free joints almost twice that of Sn–40Pb. With the solder intentionally contaminated with 0.5 mass% of Pb and with Sn–Pb component finishes, the fatigue life of this alloy became somewhat shorter, but still was about 1.5 times that of Sn–40Pb. The alloys Sn–3.8Ag–0.7Cu and Sn– 3.8Ag–0.7Cu–0.25Sb deform similarly to Sn–40Pb and Sn–36Pb–2Ag soldered joints. These alloys show recrystallization of the primary tin phase and coarsening of the eutectic structure by diffusion and grain growth (Figure 27). With all the various temperature cycling tests conducted, the fatigue life of soldered joints made with these alloys in wave, reflow, and rework/repair soldering was about equal to Sn–40Pb and Sn–36Pb–2Ag joints. The thermomechanical fatigue
FIG. 26 Through-hole joint of Sn–5Bi–2Sb–1Ag solder after thermomechanical fatigue testing. (a) Free surface of a joint showing cracks. (b) Photomicrograph of a vertical cross section of a joint that shows failure occurring along boundaries between Sn grains.
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FIG. 27 Photomicrograph of vertical cross sections of through-hole joints showing plastic deformation damage in Sn–3.8Ag–0.7Cu–0.25Sb solder. (a) Recrystallization in the zone with greatest deformation (recrystallized grains are dark in polarized light image). (b) Fatigue fracture after 2500 thermal cycles.
lifetimes of the various alloys are presented in Table 38, expressed as ratios compared to the life of Sn–40Pb soldered joints. Unfortunately, none of the investigated lead-free alloys exhibited a much longer fatigue life than eutectic tin-lead. The improvement exhibited by one type of solder, Sn–5Bi–2Sb–1Ag, is only marginal. The application of this solder lies mainly in wave soldering of single-sided boards. A general-purpose lead-free solder with improved fatigue life was not found in this study. 2. Vibration and Shock a. Wave Soldered Boards. Resistance to vibration of wave soldered boards was tested according to consumer electronics severity testing (IEC60068-2-6) and bump testing (IEC600682-29) on standard equipment, on as-soldered test boards and after 1200 temperature cycles under Test Condition B. Test conditions are given in Table 39. No major influence of shock and vibration loading on lead-free soldered joints was observed. Only incidental fracture of component leads was observed on large, heavy components, such as on electrolytic capacitors, but no soldered joints were damaged, as was the case for Sn–40Pb solder joints. b. Reflow Soldered Boards. An extended study was performed on reflow soldered boards with solders Sn–40Pb, Sn–36Pb–2Ag (the usual reflow alloy), and Sn–3.8Ag–0.7Cu. Random vibration tests in three directions were performed, with the PCBs clamped in a fixture on only one
TABLE 38 Thermomechanical Fatigue Lifetimes (Relative to Sn– Pb) of the Various Lead-Free Alloys Examined in the IDEALS Consortium Solder Alloy Sn–40Pb and Sn–36Pb–2Ag (baseline) Sn–3.8Ag–0.7Cu–0.25Sb Sn–5Bi–2Sb–Ag Sn–0.7Cu a
Relative to eutectic Sn–Pb.
Fatigue Life Ratioa 1 1 1.5–2.0 0.5–0.7
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TABLE 39
Vibration and Shock Test Conditions
Vibration Bumping/shock
Frequency 10–150 Hz, frequency change 1 octave/min, acceleration/amplitude 2 G/0.15 mm, time: 40 min/direction in 58 min Acceleration 10 G/16 msec, 4 directions, 1000 bumps/direction
side. Initial tests were performed with a frequency range between 100 and 2000 Hz, and amplitudes resulting in forces of 30 G. Tests lasting less than or equal to 8 hr per direction did not result in solder damage of consequence with any of the three alloys assessed by visual inspection and electrical measurements. However, some solder joints of chip resistors mounted to boards which had first undergone 500 temperature-shock cycles between 65 and +125jC with hold times of 10 min, failed in this vibration test. This is not a surprise, because approximately two-thirds of the fatigue life of those joints was consumed by this severe temperature cycling test. The preconditioning test of 65 and +125jC with hold times of 10 min was unrealistically severe. Additional random vibration tests were performed utilizing boards subjected to less severe thermal cycling conditions (40 to +125jC, with 15-min dwell times). Conditions consisted of random vibration directed perpendicular to the boards, at frequencies between 50 and 2000 Hz, 20 G, for a duration of 6 hr. Visual inspection, electrical measurements and shear tests on chip resistors were used to assess the damage. Temperature cycling (40 to +125jC, with hold times of 15 min) caused a slight drop in shear strength, but the random vibration did not add additional damage. Only small, insignificant differences were observed among the three alloys. 3. Humidity Tests Standard moisture tests were executed (40jC/95% RH and 85jC/85%RH). Corrosion effects were determined by visual inspection. No significant corrosion was observed. 4. Intermetallic Compound Growth The intermetallic compound growth rate between lead-free solders and copper was observed to be comparatively small. This was also the case with nickel, indicating that there are no compatibility problems compared to Sn–Pb solders. However, the reaction rate of lead-free solders with fired Ag–Pd and Ag–Pt metallizations (i.e., on ceramic multilayer capacitors and ceramic modules) was observed to be significantly larger with lead-free solders than with Sn–Pb. The different diffusion rates of Sn, Ag, and Pd cause gross, asymmetrical material transport and void formation characteristic of the Kirkendall effect, which results in build-up of stress and fracture of the intermetallic compound layer (Figure 28) and sometimes even of the underlying ceramic. Consequently, this study determined that these silver-based finishes are incompatible with leadfree soldering.
J. Key Findings and Recommendations The IDEALS project has succeeded in identifying suitable lead-free solder alloys and their matched fluxing systems, board finishes, and component metallization, which were tested in extensive assembly trials. The chosen solders were:
Sn–3.8Ag–0.7Cu eutectic alloy for reflow soldering and rework/repair soldering, Sn–3.8Ag–0.7Cu–0.25Sb near-eutectic alloy for general purpose wave soldering, Sn–5Bi–2Sb–1Ag for single-sided wave soldering only.
The alloys Sn–3.8Ag–0.7Cu and Sn–3.8Ag–0.7Cu–0.25Sb melt at or close to 217jC. The alloy Sn–5Bi–2Sb–1Ag has a large melting range of approximately 40jC (between the solidus temperature of 180jC and the liquidus temperature of 220jC). Eutectic Sn–0.7Cu solder performed poorly in early screening trials and was eliminated from further consideration. Complementary lead-free board finishes, including solderability preservative layer (CuOSP), immersion-silver (Alpha levelk) and electroless nickel/immersion gold, were assessed and
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FIG. 28 Photomicrograph depicting microstructural fracture created due to the Kirkendall effect within the lead-free solder and Ag–33Pd metallization layer on a ceramic chip capacitor. Note (1) the thick intermetallic compound layer, (2) the Kirkendall voiding between the metal and ceramic capacitor, and (3) the stress-induced cracking in the intermetallic layer.
observed to be compatible with the Sn–3.8Ag–0.7Cu, Sn–3.8Ag–0.7Cu–0.25Sb, and Sn–5Bi– 2Sb–1Ag alloys. Systematic process trials were undertaken to establish the process parameters for industrial implementation of wave, reflow, and rework/repair soldering. Several designs of circuit board were assembled, including test boards designed specifically for the project and production boards. These boards were subjected to full acceptance tests, including visual and metallographic examination, and an extended reliability test program. The results include the following findings:
A lead-free soldering technology based on Sn–3.8Ag–0.7Cu, Sn–3.8Ag–0.7Cu– 0.25Sb, and Sn–5Bi–2Sb–1Ag alloys is technically and industrially viable. These solders can be produced in the form of pastes for reflow soldering, bar stock for wave soldering, and flux-cored wire for rework/repair, as required. Lead-free wave soldering requires a 10–15jC higher solder bath temperature and longer contact times between boards and solder waves. The effect of fillet lifting with lead-free solder in wave soldered plated holes, is minimized by the use of near-eutectic Sn–3.8Ag–0.7Cu–0.25Sb alloy. Tolerance to lead-containing component terminations has been demonstrated for this alloy. The minimum reflow peak temperature for lead-free reflow soldering with Sn– 3.8Ag–0.7Cu is about 235jC (although soldering is possible even at a temperature as low as 225jC with small boards and with some finish types). Consequently, component survivability at reflow temperatures 30jC higher than eutectic Sn–Pb due to moisture effects has become a major issue with lead-free reflow soldering. The reliability of lead-free assemblies was shown to be functionally equivalent to tin– lead soldered assemblies, in terms of cycles-to-failure in thermomechanical fatigue tests, intermetallic compound growth and resistance to vibration and shock. There was no evidence to suggest that Sn–3.8Ag–0.7Cu will allow substantially increased operating temperatures.
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VOC-free, water-based spray and foam fluxes for wave soldering and VOC-free solder pastes for reflow soldering have been developed. The high latent heat of vaporization of water puts high demands on the preheating section of wave soldering machines. Compatibility of lead-free solders with a wide range of standard lead-containing and lead-free board and component finishes has been demonstrated. Mass-production wave soldering began on one production site in mid-1998 with Sn–5Bi– 2Sb–1Ag solder on single-sided printed boards with a wide variety of surface-mounted and through-hole-mounted components. The wave soldering process is very stable and has a first-pass defect rate of only 30 ppm. Industrial reflow soldering began on another site in early 1999, with no details available about process stability or yield.
VI. NCMS HIGH-TEMPERATURE FATIGUE RESISTANT SOLDER PROJECT A. Project Objectives and Participants In 2001, the National Center for Manufacturing Sciences (NCMS) High Temperature Fatigue Resistant Solder Project completed a 4-year program to identify and evaluate Pb-free, hightemperature, fatigue-resistant solder alternatives to high-lead solder alloys [26,27]. The project was conducted by a consortium of eight corporations, Iowa State University, and NIST, as listed in Table 40. The goal of the project was to determine whether nontoxic, Pb-free, cost-effective substitutes could be found for high-lead and Sn–Ag eutectic solders for use in harsh environments where excellent high-temperature reliability is required. The search for new, higher-temperature, Pb-free solder alloys is being driven by the automotive, telecommunications, and avionics industries. The automobile engine compartment has become considerably more compact, resulting in at least a 20jC increase in the maximum engine compartment temperature. The availability of a new high-temperature solder alloy would allow automobile manufacturers to move electronic devices from the passenger compartment closer to the point of use. In the case of the engine control module, the module could possibly be mounted directly onto the engine. An added benefit is that this configuration will allow the testing of the engine prior to installation into the automobile. In addition, the placement of other engine compartment electronic components, such as alternators, ignition modules, etc., could benefit from higher temperature fatigue resistant solder alloys. The telecommunication industry plans to
TABLE 40
Project Participants in NCMS High-Temperature Fatigue Resistant Solder Project
Participating organizations Allied Signal Amkor Technologies Delphi Delco Electronics Systems Ford Motor Company (Ford) Hereaus Corporation Indium Corporation Johnson Manufacturing Rockwell International Corporation (Rockwell) Iowa State University National Institute of Standards and Technology (NIST) National Center for Manufacturing Sciences (NCMS)
Primary technical contacts Gary Becka Ahmer Syed Jerry Badgett, Gordon Whitten, and Yun Zhu Tsung-Yu Pan and Howard Blair Angela Grusd, Rick Lathrop, Brian Bauer, and Steve Fritzinger Jim Slattery Alan Gickler John Mather and Chris Olson Iver Anderson and Jim Foley Frank Gayle, Leonard Smith, and Maureen Williams Duane Napp, Shirley Phillips, Michael Elta, and Anita Tolen
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locate electronics in outdoor field environments in temperature conditions above the capabilities of eutectic Sn–Pb alloy. The aviation industry is interested in mounting electronic control modules onto jet engines.
B. Alloy Selection The selection of suitable alternatives to high-lead and Sn–Ag eutectic solders required careful evaluation of candidate alloys based on manufacturing and use requirements. An aggressive target of the project was to identify Pb-free solders with lifetimes during cycling from 55 to +160jC equivalent to those of Sn–Pb eutectic solder cycled from 55 to +125jC. From these thermal cycling conditions, typical assembly process temperatures, and the survivability of existing components, down-selection criteria were developed based on material property limits, similar to the methods devised for the earlier NCMS Lead-Free Solder Project. A survey was made of f12,000 metallic binary- and ternary-phase diagrams for binary, ternary, and quasibinary eutectics, and compounds that congruently melt between 183 and 400jC. The goal was to find alloys of the appropriate melting temperatures with minimal freezing ranges. The initial list of several hundred candidate alloys was quickly reduced by eliminating toxic materials As, Cd, Hg, Pb, and Tl and by eliminating any element that would lead to an alloy price of greater than $100 per pound. The list was further reduced by eliminating any element that created oxidation issues, such as Mg and S, and by limiting the mass fractions of Zn to <10% and Li to <1%. After requiring a solidus temperature greater than 208jC (allowing a 160jC operating temperature to be 90% or less of the absolute melting point), and compatibility with low residue/no clean rosin mildly activated (RMA) fluxes of the remaining lead-free solder alloys, 32 Pb-free alloys remained, all of which were Sn-based. Two additional rounds of down-selection were conducted based on further refinements of liquidus temperature, pasty range, interfacial reactions, wettability, and on the results of thermal cycling of leadless ceramic chip carriers on a high-temperature, FR-4 PWB (Tg>170jC). A thermomechanical fatigue screening test for the remaining 13 alloys was performed utilizing 44 I/O and 20 I/O leadless ceramic chip carriers (LCCC) on FR-4 PWB substrates under the thermal cycling test conditions of 55 to + 160jC, with a ramp rate of 10jC/min, temperature dwell of 10 min at each temperature extreme for a total cycle duration of 1 hr. The Weibull results for the various alloys are presented in Figure 29. The seven alloys determined to be the best performers based on mean life are listed in Table 41 The alloy Sn–4.8Bi–3.3Ag
FIG. 29 Weibull parameter data for several Pb-free solder alloys utilized to attach 44 I/O and 20 I/O leadless ceramic chip carriers (LCCC) to FR-4 printed circuit boards and thermally cycled under the thermal cycling test conditions of 55 to +160jC, with a ramp rate of 10jC per min, temperature dwell of 10 min at each temperature extreme for a total cycle duration of 1 hr.
718
HANDWERKER ET AL.
TABLE 41 Alloys Tested for Initial Fatigue Life Screening. Seven Alloys Were Selected for Further Testing Through the Reliability Test Vehicle (RTV) as Indicated Alloy
Composition
Selected for RTV
A1 A10 A11 A14 A15 A21 A32 A62 A55 A66 A86 B23 B36 B63
96.5Sn/3.5Ag 93.6Sn/4.7Ag/1.7Cu 95Sn/4.0Ag/1.0Cu 95.5Sn/4.0Ag/0.5Cu 93.1Sn/4.7Ag/1.7Cu/0.5Co 96.2Sn/2.5Ag/0.8Cu/0.5Sb 91.8Sn/4.6Ag/1.6Cu/1Sb/1Bi 92.4Sn/3.3Ag/1Cu/3.3Bi 91.9Sn/3.3Ag/4.8Bi 95Sn/3.5Ag/1.5In 95Sn/3.5Ag/0.5Cu/1Zn 99.3Sn/0.7Cu 98.3Sn/0.7Cu/1In 63Sn/37Pb
Yes Yes Yes Yes Yes Yes Yes
(A55) was eliminated and replaced with Sn–2.5Ag–0.8Cu––0.5Sb (A21), primarily because of low melting phases and reduced reliability when Bi-containing alloys are contaminated with Pb. The alloy Sn–2.5Ag–0.8Cu–0.5Sb (A21) was also chosen because it is a commercially available alloy, with some history of industrial use.
C. Manufacturability and Reliability Assessment Manufacturability and reliability assessments were performed with a PWB Test Vehicle (RTV) utilizing a variety of surface mount components, as listed in Table 42. The test vehicle is shown in Figure 30. An imidazole-finished copper surface was used on the PWB and the component leads were hot-solder-dipped in the same alloy as the paste used for assembly. Thermal cycling was performed from 55 to 160jC with a ramp rate of 10jC/min and temperature dwell of 10 min at each end of the cycle, for a total cycle duration of 1 hr. For each alloy, approximately 27 boards each containing 28 components were tested.
TABLE 42 Component TSOP PLCC UTQFP QFP QFP PBGA LCCC 0805 CR 1206 CR
Component Set on the PWB Used in the Manufacturing and Reliability Assessment I/O Count
Component type
Number per board
32 68 80 120 160 256 20 — —
Thin small outline package Plastic leaded chip carrier Ultra thin quad flat pack Quad flat pack Quad flat pack Plastic ball grid array Leadless ceramic chip carrier Chip resistor Chip resistor
1 1 1 1 1 1 2 10 10
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FIG. 30 Top view of the printed circuit board reliability test vehicle (RTV) with a variety of surface mount components utilized for manufacturing and reliability assessments in the NCMS HighTemperature, Fatigue-Resistant Solder Project.
1. 1206 Chip resistor Table 43 lists the Weibull parameters for the 1206 resistors. The relative performance of the alloys is shown in Figure 31, normalized with respect to Sn–3.5Ag (A1). Comparing the mean life, all alloys performed better than Sn–3.5Ag (A1) with life improvement in the range of 1.8–3.5x. Also, with the exception of Sn–2.5Ag–0.8Cu–0.5Sb (A21), all alloys performed better than Sn–3.5Ag (A1) based on a first failure criterion. The performance of both Sn–Ag–Cu alloys, Sn–4Ag–0.5Cu (A14), and Sn–4Ag–1Cu (A11), was similarly based on Weibull data. 2. 0805 Chip Resistors Table 44 lists the Weibull parameters for the 0805 chip resistors, and the relative performance comparison based on alloy A1 is shown in Figure 32. Comparing the mean life, it is apparent that all alloys performed better than the industry standard alloy Sn–3.5Ag (A1) for this component. The relative increase in fatigue life for the alloys investigated ranged from 35% for A14 to 135% for A62 compared to A1. It is interesting to note that A14 performed better than A11 with respect to the first failure, but showed a lower value for mean life. This is primarily the result of a very low failure rate, and the extrapolation involved in calculating the mean life. The mean life would likely
TABLE 43
Weibull Analysis Parameters for 1206 Chip Resistors Two-Parameter Weibull
Three-Parameter Weibull
Alloy
Number Tested
Number Failed
First fail
Beta
Eta
Mean
0.10%
Beta
Eta
TruEta
Gamma
0.10%
A1 A11 A14 A21 A32 A62 A66
250 210 270 250 240 260 260
25 20 27 24 22 26 26
412 447 657 403 903 537 526
3.3 1.8 2.2 1.9 3.4 3.0 2.3
2247 7848 7007 6971 5168 4054 6667
2014 6977 6206 6184 4644 3619 5907
270 171 311 192 684 400 334
1.5 0.9 1.1 1.1 2.8 2.7 2.1
3608 24564 15491 14120 5469 4248 7143
3959 24989 16069 14522 5743 4329 7244
351 425 578 402 274 81 101
392 438 613 423 734 411 366
720
HANDWERKER ET AL.
FIG. 31 Fatigue life comparison of several Pb-free alloys utilized to attach 1206 resistors (RTV).
be greater if the test had been extended so that more failures had occurred. The Weibull plots themselves clearly indicate that of all the failures observed, A14 was consistently better than A1 and A11. Finally, based on a first failure criterion, A14 alloy appears to be the most reliable alloy for this component and temperature cycle condition. 3. 80 Lead UTQFP Table 45 lists the Weibull parameters for the 80 lead UTQFP component. Notice that only a few components were tested in some cases. This was a result of large fallout during the board assembly process resulting in misplaced components as well as solder joint bridging. A relative comparison based on alloy A1 is shown in Figure 33. Weibull analysis was not performed for alloy A11 as there were only two failures for this alloy. Comparing the mean life, all alloys performed better than alloy A1 for this component. Although the mean life for A11 was not calculated, it would have exhibited a longer mean life compared to alloy A1 based on the first failure data given in Table 45. The same trend can be observed by using a first failure criterion, except for A14, which had lower first failure life than A1. a. Other Components. Failures during thermal cycling were observed in all alloys for the plastic ball grid array (PBGA) package. However, the data indicated multiple failure modes and early failures not expected from this package, making it difficult to interpret the failure data based on solder performance. Other components on the RTV test vehicle had compliant leads and, as
TABLE 44
Weibull Analysis Parameters for 0805 Chip Resistors Two-Parameter Weibull
Alloy
Number Tested
Number Failed
First Fail
Beta
Eta
Mean
0.10%
A1 A11 A14 A21 A32 A62 A66
270 274 270 270 240 270 250
22 12 9 17 7 8 9
1477 2182 3515 2005 2853 2373 2734
3.9 3.6 9.1 3.8 4.7 3.28 4.7
5220 9653 6750 8468 9167 12491 8979
4725 8698 6395 7653 8387 11201 8215
900 1427 3151 1379 2121 1528 2059
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FIG. 32 Fatigue life comparison of several Pb-free alloys utilized to attach 0805 resistors (RTV).
expected, they had not exhibited any solder joint failures when the thermal cycling was concluded at 5000 cycles.
D. Reliability Evaluation of BGA Packages A study of the seven Pb-free alloys with two types of BGA packages (Table 46) was performed by using more common accelerated test conditions. The packages were assembled using standard processes up to the ball attachment step. All packages were baked at least 4 h at 125jC before ball attachment in order to avoid package-level failures. After baking, the balls were attached by using standard ball attachment equipment and processes, except that a peak reflow temperature of 240jC was used. The packages were mounted on motherboards and tested under two separate test conditions: TC1 (40 to 125jC, 15-min ramps and dwells, 1 cycle/hr), and TC2 (0–100jC, 10min ramps, 5-min dwells, 2 cycles/hr). It should be noted that although a sample size of 30–45 parts is typically used for evaluating second-level reliability, only 15 units were used here because of the comparative nature of this study. Also, because a flux-only process (no additional solder
TABLE 45
Weibull Analysis Parameters for 80 Lead UTQFP Two-Parameter Weibull
Alloy
Number Tested
Number Failed
First fail
Beta
Eta
Mean
0.10%
A1 A11 A14 A21 A32 A62 A66
7 5 21 14 25 18 15
6 2 18 9 9 6 12
2030 2588 1518 2466 2468 3674 2920
5 N/A 3.76 7.1 3.5 6.6 6.5
2993 N/A 3358 3457 6260 5430 4344
2748 N/A 3033 3236 5632 5064 4048
760 N/A 536 1308 852 1910 1504
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HANDWERKER ET AL.
FIG. 33 Fatigue life comparison of several Pb-free solders utilized to attach 80 Lead UTQFP components.
paste) was used for board mounting, some components exhibited very early failures that were not considered for data analysis. 1. Reliability Comparison for fleXBGA Package a. TC1 Condition, 40 to 125jC. The fleXBGA packages were exposed to the TC1 thermal cycle conditions that represents the most severe test combination of the BGA tests considered. A summary of failures observed at the end of 4850 cycles is listed in Table 47, when all units had failed for every alloy system. The table also lists the ranking of all alloys with respect to first failure and mean life criteria. These data show that all alloys performed better than Sn–Pb eutectic solder for this package and test condition with the exception of Sn–3.5Ag alloy (A1). An examination of the raw data and Weibull plot for Sn–3.5Ag indicated dual failure modes, with seven components failing much earlier than the others. Failure analysis of the earliest failures showed no evidence of solder cracking and the exact cause of failure could not be identified. Comparing the mean life of the other Pb-free alloys, the top five alloys (ranked 1 through 5) show at least a 25% improvement in life over Sn–Pb eutectic. Furthermore, these five alloys performed quite similarly, the difference in reliability among these alloys is only 6%. The comparison for first failure also indicates similar behavior for the top five alloys. It is interesting to note that the two Sn–Ag–Cu alloys, A11 and A14, exhibited similar behavior, as shown in the Weibull plot in Figure 34, that compares the two compositions with eutectic Sn–Pb (B63). b. TC2 Condition (0 to 100jC). About 9800 cycles were completed while utilizing this test condition before the test was stopped. While all the packages with Sn–Pb eutectic failed, some of the Pb-free alloys did not show any failures by the end of the test. Table 48 is a summary of the
TABLE 46
Packages Used in BGA Pb-Free Solder Reliability Evaluation
Package Type PBGA FleXBGAk
Size (mm)
I/O
Package Substrate Material
Ball Size (mils)
Ball Pitch (mm)
Die Size (mm)
27 27 12 12
256 144
BT Tape
30 18
1.27 0.8
10 10 6.4 6.4
MAJOR INTERNATIONAL LEAD (PB)-FREE SOLDER STUDIES TABLE 47 +125jC)
723
Comparison of Pb-Free Alloy Reliability for fleXBGA Package (TC1 Cycling, 40 to
Alloy Code
Alloy Composition
# on Test
A1 A11 A14 A21 A32 A62 A66 B63
Sn–3.5Ag Sn–4Ag–1Cu Sn–4Ag–0.5Cu Sn–2.5–Ag–0.8Cu–0.5Sb Sn–4.6–Ag–1.6Cu–1Sb–1Bi Sn–3.4Ag–1Cu–3.3Bi Sn–3.5Ag–1.5In Sn/Pb Control
12 14 14 14 15 14 14 13
# Failed
First Failure (cycle)
Mean Life (cycle)
Rank by First Failure
Rank by Mean Life
12 14 14 14 15 14 14 13
1282 2340 2108 2378 2161 1864 2387 1845
2100 2860 2816 2980 2930 2500 2805 2240
8 3 5 2 4 6 1 7
8 3 4 1 2 6 5 7
failure data. Based on ranking by first failure and mean life criteria, all alloys had a life at least 2 longer than eutectic Sn–Pb in this test, including the Sn–3.5Ag alloy. This is an important result indicating that the acceleration factors for various test conditions are not the same as for eutectic Sn–Pb. For example, for the TC1 test condition, the Pb-free alloys exhibited only a 25% improvement over eutectic Sn–Pb. The acceleration factor for Sn–Pb is about 2 from TC2 to TC1 condition, A11 showed an acceleration factor of 3.3 for the same condition. Because fieldlevel conditions are relatively benign compared to accelerated conditions, the above results suggest that Pb-free alloys do not need to perform as well as the eutectic Sn–Pb under accelerated test conditions to meet the field-level reliability targets. Regarding the two Sn–Ag–Cu alloys, both performed about 2 better than eutectic Sn–Pb. 2. Reliability Comparison for PBGA Package a. TC1 Cycling, 40 to 125jC. The PBGA package was used to evaluate the reliability of all alloys except A1. The test completed 6700 cycles with only a few alloys (A11, A21, A66) showing failures of close to 50% of the PBGAs tested. Table 49 provides a performance comparison that indicates that all alloys performed much better than the eutectic Sn–Pb with more than 30% improvement in solder joint reliability. Of the two Sn–Ag–Cu alloys examined, A14 performed better than A11.
FIG. 34 A two-parameter Weibull plot for two Sn–Ag–Cu alloys, Sn–4Ag–1Cu (A11) and Sn–4Ag– 0.5Cu (A14), and SnPb control (B63) for fleXBGA Package thermally cycled from 40 to +125jC. Note that A11 (Sn–4Ag–1Cu) and A14 (Sn–4Ag–0.5Cu) have similar behavior, and both outperform the eutectic Sn–Pb alloy B63.
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TABLE 48 Comparison of Pb-Free Alloy Reliability for fleXBGA Package (TC2 cycling, 0 to +100jC)
Alloy Code A1 A11 A14 A21 A32 A62 A66 B63
Alloy Composition
# on Test
# Failed
First Failure (cycle)
Sn–3.5Ag Sn–4Ag–1Cu Sn–4Ag–0.5Cu Sn–2.5–Ag–0.8Cu–0.5Sb Sn–4.6–Ag–1.6Cu–1Sb–1Bi Sn–3.4Ag–1Cu–3.3Bi Sn–3.5Ag–1.5In Sn/Pb Control
15 15 15 14 14 15 15 14
6 6 11 6 0 0 13 14
6288 6967 6073 8089 N/A N/A 5630 3418
Mean Life (cycle)
Rank by First Failure
Rank by Mean Life
10300 9456 8861 9238 N/A N/A 6448 4465
5 4 6 3 1 1 7 8
3 4 6 5 1 1 7 8
b. TC2 Cycling, 0 to 100jC. About 10,000 cycles were completed on this test without any alloys exhibiting failures, including eutectic Sn–Pb. The test was stopped at that point. Overall, the BGA study results indicate that the solder joint reliability of all Pb-free alloys tested was better than eutectic Sn–Pb for both test conditions utilized for the BGA components.
E. Conclusions Conclusions of the NCMS High Temperature Fatigue Resistant Solder Project are summarized below. 1. Alloys and Fatigue Performance
A survey of approximately 12,000 binary- and ternary-phase diagrams suggests that the only Pb-free alloys feasible for general microelectronics use are Sn-based alloys. Several lead-free alloy compositions were identified that exhibit harsh-environment fatigue performance which is superior to the industry standard eutectic Sn–Ag alloy. This performance was determined during 55 to 160jC cycling of a wide range of components. All seven lead-free alloys outperformed Sn–Pb eutectic solder lifetimes, in some cases by factors of 2x to 3x, under 0 to +100jC and 40 to +125jC thermal cycling conditions of BGA packages.
TABLE 49
Comparison of Pb-Free Alloy Reliability for PBGA Package (TC1 cycling, 40 to 125jC)
Alloy Code
Alloy Composition
# on Test
A11 A14 A21 A32 A62 A66 B63
Sn–4Ag–1Cu Sn–4Ag–0.5Cu Sn–2.5–Ag–0.8Cu–0.5Sb Sn–4.6–Ag–1.6Cu–1Sb–1Bi Sn–3.4Ag–1Cu–3.3Bi Sn–3.5Ag–1.5In Sn/Pb Control
14 14 14 15 14 14 14
# Failed
First Failure (cycle)
Second Failure (cycle)
Third Failure (cycle)
Mean Life (cycle)
Rank by First Failure
Rank by Mean Life
11 3 6 0 1 9 4
4476 5195 3450 N/A 5875 5102 3395
4686 6054 4621 N/A N/A 5207 3462
5428 N/A 6734 N/A N/A 5784 3710
5428 N/A 6734 N/A N/A 5784 3710
5 3 6 1 2 4 7
6 3 4 1 2 5 7
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Acceleration factors determined for test conditions of 0 to +100jC and 40 to +125jC were observed to be greater for all the Pb-free alloys than for eutectic Snndash;Pb. This important result indicates that Pb-free alloys do not need to perform as well as eutectic Sn–Pb in an accelerated test in order to meet field-level reliability targets for applications below 100jC.
2. Manufacturability
These alloys can be easily manufactured as solder pastes, bar stock, and flux-cored wire. The wetting behavior on copper, based on wetting balance data and contact angle measurements, was fairly comparable for the seven lead-free alloys tested, and were comparable to the performance of eutectic Sn–Pb. Implementation of these Pb-free alloys may require considerable effort in component, substrate, and final product qualification. This may include the elimination of Pb-containing solderable surfaces if there is substantial Bi content in the solders. Major costs may be associated with start-up and qualification costs. Alloy-related costs will probably not be a major factor [typically pennies (U.S.) per PWB]. The use of organic PWB substrates with a Tg greater than 170jC is recommended for assembly, and should provide improved performance during thermal cycling conditions as well. A major constraint on the use of Pb-free solders is component survivability during the assembly process. This is not a problem if Pb-free alloys are used to replace high-Pb alloys, because it is presumed that such components would already be qualified for high reflow temperatures.
3. Recommendations for Alloy Selection The decision to implement a new high-temperature, fatigue-resistant solder alloy should be based on reliability performance, and other factors such as manufacturability, cost, reliability requirements, and environmental factors. For high reliability in harsh environments, the testing results indicate that alternatives exist which are better than eutectic Sn–Ag. These alloys are listed in Table 50 along with comments on possible replacements for Sn–Ag eutectic solder or high-Pb alloys for use in harsh environments.
VII. FOLLOW-ON STUDIES Two major microelectronics associations, National Electronics Manufacturing Initiative (NEMI); http://www.nemi.org/) and HDPUG (High Density Packaging Users Group; http:// www.hdpug.org/), are conducting lead-free solder projects to aid their industrial members in the conversion to lead-free assembly. The NEMI Pb-Free Task Force was formed by manufacturers of aerospace, automotive, and telecom equipment, component suppliers, materials suppliers (vertically integrated) to accomplish the following:
Demonstrate capability to deliver products in volume by 2001 with Pb-free interconnects. Facilitate a common Pb-free solder alloy composition for North American electronics assembly. Work with component and PCB suppliers to develop specifications necessary to meet high-temperature reflow conditions.
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TABLE 50
Promising Lead-Free Alloys for Surface Mount Applications Liquidus and Solidus Temperatures
Alloys Sn–3.4Ag–1Cu–3.3Bi
205–214jC
Sn–4.6Ag–1.6Cu–1Sb–1Bi
214–220jC
Sn–4.0Ag–0.5 Cu
216–219jC
Sn–4.0Ag–1.0 Cu
Sn–3.5Ag–1.5 In
218–223jC
Sn–2.5Ag–0.8 Cu–0.5 Sb
210–216jC
Sn–3.5Ag
221jC (eutectic)
Recommendation/Comments Excellent performance overall at 160, 125, and 100jC. 9jC pasty range may be troublesome in manufacturing process control Complex alloy: Four constituents may mean that care will be required to assure consistent composition control. Excellent performance overall at 160, 125, and 100jC. Complex alloy: Five constituents may mean that care will be required to assure consistent composition control. Alloy may well benefit from reduction in Cu and Ag content, for example, to 3.5–4.0 Ag and 0.5–1.0 Cu. Good performance under most conditions (as good or better than Sn–Ag eutectic). These two alloys performed similarly under most conditions, suggesting relative insensitivity to exact Cu level. Good choice for simple system with good performance. Good performance under most conditions. Indium availability and price volatility may be a problem. Good performance at 125 and 100jC. Good performance at 160jC with low strain; poor performance with 20 LCCCs, and 1206 and 0805 chip resistors. Overall, Sn–3.5Ag was outperformed by other Pb-free alloys tested. Simple system and smallest pasty region; good for manufacturability, especially wave soldering.
Develop criteria that industry can use to evaluate Pb-free processes. Monitor environmental legislation to adjust activities if necessary.
The NEMI Task Force is examining issues of process control, component survivability, wave soldering, rework, supply chain issues, and reliability. The NEMI Task Force project includes thermomechanical fatigue testing from 40 to 125jC for six component types, and from 0 to 100jC for a more limited component set. HDPUG is a group of systems integrators, contract assemblers, device suppliers, and materials suppliers, primarily focused on telecommunications applications. This group is conducting studies of lead-free assembly processes, low-temperature soldering by using a near eutectic Sn–Bi–Ag alloy, and lead-free transition and integration. Results from the NEMI and HDPUG studies are expected to be announced in 2002.
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VIII. NIST DISCLAIMER Commercial equipment and materials are identified in order to adequately specify certain procedures. In no case does such identification imply recommendation or endorsement by the National Institute of Standards and Technology, nor does it imply that the materials or equipment identified are necessarily the best available for the purpose.
REFERENCES 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24.
Lead-Free Soldering-An Analysis of the Current Status of Lead-Free Soldering, Report from the UK Department of Trade and Industry. Copies can be obtained from the ITRI website:
728 25. 26. 27.
HANDWERKER ET AL. Oddy, M.; Biglari, M.H. Lead-free wave soldering with VOC-free fluxes. Part II: Development of spray and foam fluxes. Proc. IPCWorks 2000, Miami, Florida, USA, September 2000. NCMS High Temperature Fatigue Resistant Solder Project Final Report, NCMS, Ann Arbor, MI, 2001. Gayle, F.W.; Becka, G.; Syed, A.; Badgett, I.; Whitten, G.; Pan, T.-Y.; Grusd, A.; Bauer, B.; Lathrop, R.; Slattery, J.; Anderson, I.; Foley, J.; Gickler, A.; Napp, D.; Mather, J.; Olson, C. High temperature lead-free solder for microelectronics. J. Met. 2001, 53 (6), 17–21.
18 Electrically Conductive Adhesives—A Lead-Free Alternative Daoqiang Lu and C. P. Wong Georgia Institute of Technology, Atlanta, Georgia, U.S.A.
I. INTRODUCTION Electrically conductive adhesives (ECAs) are composites of polymeric matrices and electrically conductive fillers. Polymeric matrices have excellent dielectrical properties and thus are electrical insulators. The conductive fillers provide the electrical properties and the polymeric matrices provide the mechanical properties. Therefore, electrical and mechanical properties are provided by different components, which is different from metallic solders that provide both electrical and mechanical properties. ECAs have been with us for some time. Metal-filled thermoset polymers were first patented as electrically conductive adhesives in the 1950s [1–3]. Recently, ECA materials have been identified as one of the major alternatives for lead-containing solders in microelectronics packaging applications. There are two types of conductive adhesives: anisotropically conductive adhesives (ACAs) and isotropically conductive adhesives (ICAs). The utilization of both types of conductive adhesives as lead-free alternatives for flip chip, surface mount technology (SMT), chip scale package (CSP), and ball grid array (BGA) applications is reviewed in this chapter. For the purpose of completeness, the recent research work on nonconductive adhesives (NCAs) for these applications will also be covered in this chapter.
II. DESCRIPTION OF ANISOTROPICALLY CONDUCTIVE ADHESIVES A. Overview Anisotropically conductive adhesives represent the first major division of polymer bonding agents. The anisotropic class of adhesives provides unidirectional electrical conductivity in the vertical or Z-axis. This directional conductivity is achieved by using a relatively low-volume loading of conductive filler (5–20 vol.%) [4–6]. The low-volume loading is insufficient for interparticle contact and prevents conductivity in the x–y plane of the adhesive. The Z-axis adhesive, in film or paste form, is interposed between the surfaces to be connected. Application of heat and pressure to this stackup causes conductive particles to be trapped between opposing conductor surfaces on the two components. Once electrical continuity is achieved, the dielectrical polymer matrix is hardened by chemical reaction (thermosets) or by cooling (thermoplastics). The hardened dielectrical polymer matrix holds the two components together and helps maintain the pressure contact between component surfaces and conductive particles. A series of sketches in Fig. 1 illustrates the attachment steps in achieving ACA joints. Anisotropically conductive
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FIG. 1 A series of schematics illustrating the steps in forming an ACA joint. (a) Component parts: a bumped die and a mating carrier with ACA spread over the surface. (b) The die is mounted with the carrier and held in place when cured. (c) Side view of the completed assembly.
adhesives have been developed for use in electrical interconnection, and various designs, formulations, and processes have been patented in Europe, Japan, and the United States [6].
B. Categories Broadly, ACAs fall into two categories: those that are anisotropically conductive before processing, and those whose anisotropy arises as a result of processing. Their characteristics can be summarized as follows: (a) preprocessing anisotropy results from materials characterized by an ordered system of conductor elements interspersed in an adhesive matrix film. They are always in the form of tape or sheet, and are complicated to manufacture, requiring an adhesive film to be laser-drilled or etched then filled with conducting materials. They provide predictable contacts and are typically applied to a substrate as preforms; and (b) postprocessing anisotropy results from materials that are a homogeneous mix of conductive fillers and adhesive matrices and which have no internal structure or order prior to processing. All adhesive pastes and some tapes fall into this category.
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C. Adhesive Matrix The adhesive matrix is used to form a mechanical bond at an interconnection. Both thermosetting and thermoplastic materials are used. Thermoplastic adhesives are rigid materials at temperatures below the glass transition temperature (Tg) of a polymer. Above the Tg, polymers exhibit flow characteristics. Thus, the Tg must be sufficiently high to avoid polymer flow during the application conditions, but the Tg must be low enough to prevent thermal damage to the associated chip carrier and devices during assembly. The principal advantage of thermoplastic adhesives is the relative ease with which interconnections can be disassembled for repair operations [7,8]. However, thermoplastic ACAs suffer from many disadvantages. One of the most serious issues is that adhesion is not sufficient to hold the conductive particles in position, causing the contact resistance to increase after thermal shocks [7,8]. Moreover, a phenomenon called ‘‘spring back’’ increases the contact resistance while the adhesive layer recovers from the stress caused by pressing of an ACA onto the components during bonding. This phenomenon, a creep characteristic exhibited by thermoplastic elastomers, occurs much after an ACA film has been heated to create the electrical joints. The contact resistance sometimes increases to more than three times the initial resistance during spring back (i.e., unloading) [7]. Thermosetting adhesives, such epoxies and silicones, form a three-dimensional (3-D) crosslinked structure when cured under specific conditions. Cure techniques include heat, UV light, and added catalysts. As a result of the irreversible cure reaction, the initial uncrosslinked material is transformed into a rigid solid. The thermosetting ACAs are stable at high temperatures and, more importantly, provide a low contact resistance. This results from a compressive force that maintains the conductive particles in intimate contact after the cure. That is, the shrinking caused by the cure reaction achieves a low contact resistance with long time stability. The ability to maintain strength at high temperature and robust adhesive bonds are the principal advantages of these materials. However, because the cure reaction is not reversible, rework or repair of interconnections is not an option [7,8]. The choice of adhesive matrix and its formulation is critical to the long-term life properties of a composite. In practice, many options exist for the adhesive matrix. Acrylics can be used in low-temperature applications (under 100jC), whereas epoxies are more robust and can be used at higher temperatures (up to 200jC). Polyimide is used in the harshest environments where the temperature approaches 300jC [6].
D. Conductive Fillers 1. Solid Metal Particles Conductive fillers are used to provide the adhesive with electrical conductivity. The simplest fillers are metal particles such as gold, silver, nickel, indium, copper, chromium, and lead-free solders (SnBi) [6,7,9–11]. The particles are usually spherical and range from 3 to 15 Am in size for ACA applications [12]. Needles or whiskers are also quoted in some patents [6]. 2. Nonmetal Particles with Metal Coating Some ACA systems employ nonconductive particles with a thin metal coat. The core material is either plastic or glass with a metal coating consisting of gold, silver, nickel, aluminum, or chromium. The basic particle shape of these systems is also spherical. Plastic-cored particles deform when compressed between opposing contact surfaces, thus providing a large contact area. Polystyrene (PS) is often selected as the core material because the coefficient of thermal expansion (CTE) of metal-coated PS beads is very close to thermoset adhesives. The combination of epoxy resin and metal-plated PS beads results in a large improvement in thermal stability [7]. In addition, glass can also be selected as the core material. Glass-cored particles coated with metal lead to a controlled bond line thickness because the glass core is not deformable. Because the conductive particle size is known, the conductivity of the joint can be predicted.
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FIG. 2 Schematic depicting the cross section of an interconnection using an MCF-filled ACA.
3. Metal Particles with Insulating Coating To achieve fine-pitch connections, metal spheres or metal-coated plastic spheres coated with insulating resin fillers were developed. The insulating resin layer is only broken under pressure to expose the underlying conductive surfaces, referred to as a microcapsule filler. Higher filler loading can be achieved with MCFs for fine-pitch applications to avoid creating electrical short circuit conditions between printed circuit features [7,12]. A typical cross section of an ACA interconnection with microcapsule filler material is illustrated in Fig. 2.
III. FLIP-CHIP APPLICATIONS USING ANISOTROPICALLY CONDUCTIVE ADHESIVES In traditional flip-chip packages, solder bumps provide electrical connections between a chip and a chip carrier. To achieve high reliability, organic underfill materials are usually required to fill the gap between the chip and the chip carrier. The cured underfill creates a monolithic structure that evenly distributes the stress over all the materials in the gap, not just on the solder connections. In the past several years, much research has been conducted to develop flip-chip packages using ACAs in place of solder bumps. The primary advantages of ACA over lead-bearing solders for flip chips include ACAs’ fine-pitch capability, being lead-free, low processing temperature, absence of flux residue, and generally lower cost. In addition, ACA flip-chip technology does not require an additional underfilling process because the ACA resin acts as an underfill. ACA flip-chip technology has been employed in many applications where flip chips are bonded to rigid chip carriers [13]. This includes bare chip assembly of application-specific integrated circuits (ASICs) in transistor radios, personal digital assistants (PDAs), sensor chips in digital cameras, and memory chips in laptop computers. In all the applications, the common feature is that ACA flip-chip technology is used to assemble bare chips where the pitch is extremely fine, normally less than 120 Am. For those fine applications, it is apparent that the use of ACA flip chips, instead of soldering, is more cost-effective. ACA flip-chip bonding exhibits better reliability on flexible chip carriers because the ability of flex provides compliance to relieve stresses. For example, the internal stress generated during resin curing can be absorbed by the deformation of the chip carrier. ACA joint stress analysis conducted by Wu et al. [14] indicated that the residual stress is larger on rigid substrates than on flexible substrates after bonding.
A. ACA Flip Chip for Bumped Dies 1. Two Filler Systems Kishimoto and Hanamura [15] reported on anisotropic conductive adhesive pastes using two different fillers: Au-coated rubber particles (soft) and nickel particles (hard). The ACAs were used to bond a flip chip with Au-plated bumps to a board with copper metallization. With the application of pressure, the soft particles were brought into contact with surface pads and were deformed, which lowered contact resistance. The hard particles, however, deformed the bumps and pads, thus were also in intimate contact with the surfaces to help reduce contact resistance. The study showed that their choice of both hard and soft fillers in ACA materials had similar
ELECTRICALLY CONDUCTIVE ADHESIVES
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voltage–current behaviors, and both exhibited stable contact resistance values after 1000 cycles of thermal cycling and 1200 hr of 85jC/85% RH aging conditions [15]. 2. Coated Plastic Filler Casio developed an advanced anisotropic conductive adhesive film called the Microconnector (Fig. 3) [16–18]. This adhesive contains conductive particles made by coating plastic spheres with a thin layer of metal, followed by an additional 10-nm-thick layer of insulating polymeric material. The insulating layer consists of a large number of insulating micropowder particles that electrically insulate the outer surface of the spheres. The thin insulation layer is formed by causing insulating micropowder particles to adhere to the surface of the metal layer via electrostatic attraction. The base adhesive resin is thermoplastic or thermoset, producing compressive force when cured. When heat and pressure are applied during bonding, the insulating layer, which is in contact with the bump surface of an integrated circuit (IC), is broken. However, the insulating layer remains intact on conductive particles not crushed by the bonding pads, thereby producing only Z-axis electrical interconnections and preventing lateral short circuit conditions. With an additional insulating layer, a fine pitch and a low contact resistance can be achieved without the risk of lateral short circuiting by increasing the filler percentage (i.e., amount of particles per unit volume base adhesive resin or film). Casio is manufacturing pocket TVs with liquid crystal using this material [18]. 3. Solder Filler Systems Unlike most commercial ACAs, where electrical conductivity is based on the degree of mechanical contact achieved by pressing conductive particles to contact pads on board and chip bumps, solder-filled ACAs establish microscopical metallurgical interconnections. The advantage of these joints is that the metallurgical bonds established prevent electrical discontinuities from occurring should the adhesive polymeric matrix undergo relaxation during the operational lifetime. Therefore, solder-filled ACAs combine the benefits of both soldering and adhesive joining resulting in more reliable ACA joints. Furthermore, better electrical performance is achieved due to lower contact resistance established through the metallurgical bonds [19]. Joints made with SnBi-filled and Bi-filled ACAs experience brittle intermetallic compound formation and have problems with typical conductor and coating materials such as copper, nickel, gold, and palladium [20]. Bi and SnBi are, however, compatible with tin, lead, zinc, and aluminum. Because Zn and Al are easily oxidized, only Sn and Pb are suitable surface finish materials for SnBi-filled and Bi-filled ACA applications. High-quality interconnections were formed by metallurgically bonding SnPb-bumped chips on SnPb-coated substrates utilizing a Bi particle-filled ACA [21]. The joints, once formed at a relatively low temperature, could withstand high temperature. The joint formation process is illustrated in Fig. 4. At the bonding temperature (160jC), as the Bi particles have locally penetrated thin oxide layers on both SnPb surfaces, liquid
FIG. 3 Schematic depicting Casio’s ACF technology—Microconnector.
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FIG. 4 Schematic illustration of the formation of electrical interconnects between a bumped chip and a mating carrier using a Bi-filled ACA. (a) The chip is aligned and placed on a chip carrier. (b) The Bi particle is deformed between a chip bump and a carrier pad when a bonding pressure is applied. (c) The Bi particle dissolves into the liquid lentils upon exposure to heat. (d) Bi diffuses into the Sn–Pb matrix and forms fine solid precipitates.
lentil formation occurs immediately. After the Bi particles have dissolved completely into the liquid lentils between the solid SnPb bumps and the coating, more Sn and Pb will dissolve into the liquid lentils until the liquid has reached its equilibrium composition at the bonding temperature. After solidification, the dissolved Bi will precipitate out as very fine particles from the saturated solution. Because the melting is transient, the remelting of the solid lentils will happen at higher temperatures than the first melting. The remelting point of the solid lentils can be controlled by the concentration of Bi present in the joint. The formed ACA joints exhibited a stable resistance after 2000-hr 85jC/85% RH aging, or after 1000-hr temperature cycle testing (40–125jC). Even though this work is still preliminary, it demonstrates an interesting idea and concept. For leadfree applications, different materials such as pure Sn can be used for chip bumps and surface finishes on substrates [21]. 4. Ni Filler Toshiba Hino Works developed a flip-chip bonding technology using an anisotropic conductive film (ACF) filled with nickel spheres and large-scale integration (LSI) chips with gold ball bumps for mobile communications terminals. Fig. 5 depicts the cross section of flip-chip joints using this ACF system, which generally does not require cleaning or encapsulating processes. A resin sealing process at the sides of the LSI chip was added to improve mechanical strength. An FR-5 glass epoxy chip carrier was utilized to improve heat resistance. The assembled pager sets passed qualification consisting of drop, vibration, bending, torsion, and high-temperature testing. The
FIG. 5 Schematic depicting an ACA flip-chip packaging technology used in pager sets.
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process has been demonstrated to be capable of mass production by utilizing full automation of the flip-chip bonding method capable of producing 30,000 pager modules per month [22].
B. ACA-Bumped Flip Chips on Glass Chip Carriers ACAs are probably the most common approach for flip chips on glass applications. The ACA flip chip on glass technology not only provides assemblies with a higher interconnection density and a thinner and smaller size, but also has fewer processes and lower costs as compared with tapeautomated bonding (TAB) technology. In addition, bonding IC chips directly to the glass of the liquid crystal display (LCD) panel using ACAs is a better choice when the pitch becomes less than 70–100 Am. Small-size and high-resolution LCDs such as viewfinders, videogame equipment displays, or light valves for liquid crystal projectors use flip chips on glass technology for IC connections. 1. Selective Tacky Adhesive Method Sharp developed a flip-chip bonding approach that utilizes ACA technology depicted in Fig. 6 [23,24]. The novel feature of the Sharp technology is the method of attaching electrical conductive particles onto IC termination pads. This ‘‘bumping’’ procedure consists of coating the wafer with a 1–3-Am-thick UV-curable adhesive. Coated wafers are irradiated with UV light in a standard photolithographic process while the Al pads on the IC are optically masked. As a result of this process, the thin adhesive film above the Al pads remains uncured and tacky, whereas the adhesive on other chip areas is cured. Due to the tackiness of the adhesive on the Al pads, conductive particles only easily adhere to these sites. The conductive particles utilized by Sharp are gold-coated polymer spheres. UV-curable adhesive is dispensed on LSI chips before being aligned with a glass carrier. While still applying pressure to maintain contact between the LSI chip and the glass carrier, a light-setting adhesive is irradiated with UV light. Even upon releasing the pressure, chip terminations remain electrically connected to their mating carrier pads. This is due to deformed conductive particles that remain in contact with these termination pads as a result of the compressive force exerted by the cured adhesive. This process has several advantages, among them is that no bump plating is required, and the bonding process can be done by irradiating with UV light at room temperature; thus, other materials are not damaged due to the effects of heat. This packaging concept can potentially achieve a high throughput. 2. The MAPLE Method Seiko Epson Corporation developed a new flip chip on glass technology called the ‘‘MAPLE’’ (Metal–Insulator–Metal Active Panel LSI Mount Engineering) method. The MAPLE method is
FIG. 6 Schematic depicting an ACA flip-chip technology scheme utilized by Sharp. (a) Conductive particles adhere to uncured tacky adhesive on pad areas of a chip. (b) Chip remains in contact with the glass chip carrier because the adhesive exerts a compressive force after it is cured with light (UV).
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used to bond ICs directly to a glass panel substrate using a thermosetting ACF containing uniformly distributed conductive Au particles. Although typical flip chips on glass technologies require several alignment steps, this bonding process is very simple. First, an ACA sheet is placed on a glass panel. After aligning the IC bumps with mating glass panel pads and bonding temporarily, proper IC interconnections are established by permanent bonding at high temperature and pressure. It is necessary for the bonding press tool surface to be flat and parallel to the IC [25]. Comparing MIM panel modules made with TAB, metal–insulator–metal (MIM) panel modules utilizing the MAPLE approach had smaller panel fringe size, thinner panel thickness, fewer assembled sides, fewer processes, and simpler module structure. The panel modules utilizing MAPLE passed all the required reliability tests that are listed in Table 1. The MAPLE approach is being used in the mass production of MIM panel modules.
C. ACA-Bumped Flip Chips for High-Frequency Applications In many low-frequency applications, conductive adhesive joining has proven to be a cost-effective and reliable solution. The high-frequency behavior of ACA interconnections has attracted much attention in the past several years. The high-frequency behavior of ACAs in flip-chip packages has been reported by several investigators. Sihlbom et al. demonstrated that ACA-bonded flip chips can provide performance equivalent to solder flip chips in the frequency range of 45 MHz–2 GHz on FR4 chip carriers and 1–21 GHz on a high-frequency Telfon-based chip carrier (Fig. 7). The different particle sizes and materials in the conductive adhesives gave little difference in the high-frequency behavior of ACA joints [26,27]. Yim et al. developed a microwave frequency model for ACF-based flip-chip joints based on microwave network analysis and S-parameter measurements. By using this model, the highfrequency behavior of ACF flip-chip interconnections with two filler particles, Ni-coated and Aucoated polymer particles, was simulated. It was predicted that Au-coated polymer particle-filled ACF flip-chip interconnections exhibited comparable transfer and loss characteristics to solderbumped flip chips up to about 13 GHz, and thus they can be used for up to 13 GHz, but Ni-filled ACF joints can only be used for up to 8 GHz because the Ni particle has a higher inductance compared to the Au-coated particle. Polymeric resins with low dielectrical constant, and conductive particles with low inductance are desirable for high resonance frequency applications [28].
D. ACA for Unbumped Flip Chips Although ACAs are typically utilized with flip-chip bumped dies, they are also used for unbumped flip chips in some cases. For unbumped flip chips, a pressure-engaged contact must be established by bringing the particles to the aluminum chip pads, rather than to a bump. The pressure must be sufficient to break the oxide on the aluminum pads. A sufficient quantity of particles must be trapped in the contact pad area and remain in place during bonding and curing to achieve a reliable interconnection. In addition to maximizing the number of particles in the contact area, the number of particles located between adjacent pads must be minimized to prevent
TABLE 1 Reliability Tests of MIM Panel Modules Utilizing the MAPLE Approach Test Pressure cooker test (PCT) High-temperature storage Humidity aging Thermal shock Low-temperature storage
Condition 115jC, 1.5 atm, 70% RH, 200 hr 80jC, 1000 hr 60jC, 90% RH, 1000 hr 25jC to 80jC, 500 cycles 40jC to 130jC, 200 cycles 40jC, 1000 hr
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FIG. 7 ACA-bonded flip chips exhibit the same transmission coefficient S21 as solder-bonded flip chips from 1 to 21 GHz.
electrical shorts. An additional factor that must be considered in the case of unbumped flip chips is adhesive flow during bonding and curing. It is essential to control the temperature heating rate to be sufficiently slow when the polymeric resin is curing, so the conductive filler particles can migrate from the chip carrier side to the chip side pad [29]. 1. Gold-Coated Nickel Filler An application utilizing gold-coated nickel particles has been reported to provide reliable connection to unbumped flip chips [30]. Another study showed that ACAs containing larger particles could accommodate planarity issues due to surface roughness and nonflat or nonparallel pads, compared to ACAs containing smaller particles. It was very difficult to obtain 100% consistency in conduction with unbumped flip-chip dice using ACAs with small diameter balls [31]. 2. Ni/Au-Coated Silver Filler A flip-chip technology developed by Toshiba Corporation utilized an ACF to attach bare umbumped chips (with Al pads) onto a polychlorinated biphenyl (PCB) with bumps formed from a silver paste screen printed on the PCB [32]. After curing, Ag bumps were formed (70 Am diameter, 20 Am height), which were subsequently overplated with Ni/Au. It was determined that an ACF with a low CTE (28 ppm/jC), low water absorption rate (1.3%), and utilizing a Auplated plastic ball worked best. It was also found that Ni/Au-plated Ag paste-formed bumps exhibited a lower initial connection resistance and a lower connection resistance increase as compared to Ag paste-formed bumps that were not overplated with Ni/Au. The initial connection resistance for Ni/Au-plated Ag paste bumps and nonplated bumps was 22 and 48 AV, respectively, with a respective increase of 294 and 717 AV after 1000 hr of accelerated thermal cycling (ATC) testing. 3. Conductive Columns Nitto Denko Corporation developed an anisotropic conductive film for fine-pitch flip-chip applications [33]. This ACF: (1) is connectable between bumpless chips and a fine-pitch printed circuit board (PCB); (2) has high electrical conductivity; (3) is repairable (easy to peal off chips from a printed circuit board at elevated temperatures); (4) has high reliability; and (5) can be stored at room temperature. The other notable features are: it is usable at pitches down to 25 Am; the conductive elements are micrometallic columns as opposed to random-shaped particles; this adhesive matrix consists of a thermoplastic polymer resin; and the conductive columns are coated with an insulator and a high-Tg polymer that completely separates the columns from the adhesive (Fig. 8).
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FIG. 8 Illustration of a scheme for fine-pitch, flip-chip interconnection. (a) An anisotropic conductive film filled with micrometallic columns. (b) A typical cross-sectional structure of a chip without bumps and the mating chip carrier. (c) A cross section of an interconnect formed between an unbumped chip and the mating chip carrier. (From Ref. 33.)
It is easy to change the diameter of the conductive columns in order to make the film compatible with a variety of pitches. Sn–Pb or other solder materials are plated on both the top and the bottom of the conductive columns (usually copper). The plated solder on both ends of the conductive columns melts and forms metallurgical connections between the conductive columns and metal pads on a chip and the mating chip carrier, which ensures good connection. Fig. 8a illustrates the cross section of the film structure. A rough surface, a result of plating, has the advantage of providing a good connection with mating terminal pads. A typical terminal pad structure of a chip without bumps is shown in Fig. 8b. To achieve a good connection, the height of the conductive columns must be larger than the thickness of the passivation layer (tp). Because tb (the distance from a Cu pad surface of the chip carrier to the passivation layer surface of the chip) is usually smaller than ta (the distance from the solder mask surface of the chip carrier to the passivation layer surface of the chip), the conductive columns will assume an inclined position during bonding if the thickness of the conductive columns is larger than the ACF thickness (tACF). It is important to adjust the thickness of board or chip carrier pads and ACF thickness to
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achieve good connection and adhesion. Reliability results indicate that the ACF possessing an adhesive matrix with a high Tg (282jC) exhibits high reliability; the contact resistance remained unchanged after 1000 cycles of accelerated thermal cycle testing (25jC to 125jC). Fig. 8c is a photograph of a cross section of a joint formed between an unbumped die and a chip carrier using this ACF flip-chip interconnection method.
E. ACA Flip Chip for CSP and BGA Applications Aiming at the CSP application market, Merix Corporation and Auburn University collaborated to develop anisotropic conductive adhesives called Area Bonding Conductive (ABC) adhesives. ABC adhesives are two-region thermoset adhesives with electrically conductive adhesive pads surrounded by a continuous oxide-filled dielectrical adhesive to form a total area bond. Both regions are solvent-free, B-staged, nontacky epoxies supplied on a Mylar carrier release film. In contrast to conventional ACAs, conductive areas of ABC adhesives are located only at bond pad locations. The assembly process for using ABC adhesives is shown in Fig. 9. The ABC adhesives
FIG. 9 Schematic depicting a flip-chip assembly process utilizing ABC adhesives. (a) A chip is aligned to the ABC preform, which is on a carrier film. (b) The ABC preform is tacked to the die at 100jC and under a pressure of 150 g for 30 sec, and then the carrier film is removed after the chip is cooled down. (c) The chip with the ABC perform is aligned to a mating chip carrier (FR4 board). (d) The chip/ABC perform is attached to the chip carrier at 100jC and under a pressure of 150 g for 30 sec, and then the package is cooled down.
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potentially can provide a reliable, low-cost, low-temperature, low-pressure process for flip-chip and CSP applications [34]. 1. Gold Stud vs. Electroless Ni/Au Bumps As the demand for miniaturization has increased dramatically, concentrated efforts have been made to find cheaper alternatives to established technologies of area array solder bumps. ChipPAC Incorporated demonstrated an alternate process/package concept covering both CSP and PBGA package formats whose construction is illustrated in Fig. 10. The concept package consisted essentially of three parts: ACF, metallic bumps on die bond pads, and an organic chip carrier [35]. Although this packaging solution was not entirely unique, reducing it to a high-volume assembly and packaging process where low cost and high reliability were keys was innovative. This configuration provides an appealing package solution based on several factors. First, the connection can be implemented at a much finer pitch (100 Am) compared to conventional solder bumps, so there is a potential for a die size reduction in flip-chip IC designs that are normally implemented as multirow perimeter arrays using conventional solder bumps. Second, the ACF interconnect approach allows the use of inexpensive bumping technologies, thereby greatly reducing the wafer bumping cost portion of the overall package cost. The combination of cured adhesive interconnection, bumps, and organic substrate provides a reliable, cost-effective flip-chip CSP. It was determined that Au stud bumps were preferable to Ni/Au bumps due to their compliant nature. Because the planarity control of organic chip carriers is difficult, given the nature of the material, it was simpler to change the interconnection method (i.e., using Au stud bumps). However, electroless Ni–Au bumps are still an option if the material properties of the ACF and/or chip carrier are altered to provide compliance. 2. Double-Layered ACF Film Motorola developed a low-cost and low-profile flip chip on flex (FCOF) CSP package using ACFs [36]. The package has the flexibility to utilize the existing wire-bonding pad configuration without adding prohibitive redistribution and wafer solder bumping costs, and eliminates the need for underchip encapsulation. Two types of ACF films were studied: double-layer films with the second layer loaded with Ni–Au-plated polystyrene divinylbenzene (PS-DVB) spheres, and solid Ni particles. The film structure, consisting of a nonfilled and a conducting particles-filled adhesive layers, is illustrated in Fig. 11. The double-layer design reduces the particle density in the x–y spacing of interconnection pads, which serve to enhance the x–y plane insulation characteristics. At the same time, the double-layer film provides more adhesive volume that helps to entrap more particles on the bonding interconnection pads. Both calculated and observed values show that the number of conducting particles trapped is much higher than those in single-layer ACFs. This indicates that even though particle density in a double-layer ACF is low, conducting particles used to effect electrical contact with both interconnection pads are trapped more effectively between interconnection pads in the double-layer ACF. The die has Ni/Au-plated bonding pads and the chip carrier is flexible polyimide, which can provide adequate compensa-
FIG. 10 A schematic depicting the side-view construction of a ChipPAC CSP package utilizing an ACF.
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FIG. 11 A schematic of a double-layer ACF.
tion for planarity differences. Its compliant nature under compressive bonding operation allows the copper traces at the bonding area to deform and compensate for nonplanarity or irregularity that exists. The ACF adhesive system provided the system with stable contact resistance after 500 cycles of liquid-to-liquid temperature shock (LLTS) aging (55jC to 125jC). 3. Ceramic Chip Carriers vs. Organic Chip Carriers A ceramic chip carrier and an organic chip carrier, whose configuration is equivalent to that of microball grid array (ABGA)-style CSP and is broadly representative of BGA and flip-chip devices, were evaluated using ACAs with conducting particles of various sizes [37]. The ceramic chip carrier has AgPd thick film bonding pads and the organic chip carrier is a conventional PCB (1 oz of Cu-clad FR5 laminate) with submicron Au-coated Cu pads. It was determined that uniform conductivity and high yield were more readily achieved with organic chip carriers rather than ceramic chip carriers. This is because bonding pads on the FR5 chip carriers have better coplanarity compared to the thick film ceramic chip carriers. It was demonstrated that optimum process conditions and adhesive material choice were very different for organic and ceramic chip carriers. ACAs with finer particles exhibited worse overall performance on both chip carriers, whereas ACAs with larger and polymer-cored particles exhibited better performance because the deformable polymer-cored particles compensated for the gap variations between the chip bumps and the chip carriers.
F. SMT Applications ACAs have been investigated as replacement for SnPb solders in surface mount attachment for fine-pitch applications. In addition to providing a lead-free attachment solution, cost-effectiveness is an additional key benefit. The key attractive advantage is the cost-effectiveness of using ACA to bond fine-pitch surface mount components. A limitation of ACA adhesives is the need to cure under contact pressure. The concept of using an ACA as a solder replacement on rigid chip carriers utilizing conventional surface mount technology has been demonstrated by Liu et al. [38]. Fine-pitch SM components were bonded to FR4 boards with ACAs using a fine-pitch bonder and then components with larger pitches were bonded with ICAs using standard SM equipment. The study demonstrated that standard surface-mounting tools could be used to assemble conductive adhesives. The connection resistance of solder-plated plastic components (0.65 mm pitch) with ACAs bonded did not change after an ATC test conducted at 40jC to 85jC. However, similar parts failed under conditions of 55jC to 125jC for 1000 cycles [39]. The mechanical stability problem may have been the result of an improper joint geometry (i.e., not optimized for ACA bonding).
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G. Failure Mechanism Because the adhesive matrix is a nonconductive material, interconnection joints rely, to some extent, on pressure to assure contact for conventional ACAs. Adhesive interconnections therefore exhibit different failure mechanisms compared to soldered connections, where the formation of intermetallic compounds and coarsening of grains are associated with the main mechanisms. Basically, there are two main failure mechanisms that can affect the contacts. First is the formation of an insulating film on either the contact areas or conductive particle surfaces. Second is the loss of mechanical contact between the conductive elements due to either a loss of adherence, or relaxation of the compressive force. 1. Oxidation of Nonnoble Metals Electrochemical corrosion of nonnoble metal bumps, pads, and conductive particles results in the formation of insulating metal oxides and a significant increase in contact resistance. Electrochemical corrosion only occurs in the presence of moisture and metals that possess different electrochemical potentials. Humidity generally accelerates oxide formation and also the increase in contact resistance. Reliability test results for FCOF using gold bumps and ACFs filled with Ni particles indicated that the connection resistance increased with time under elevated temperature and humidity storage conditions [40]. In this case, the gold bump acts as a cathode and the Ni particle as an anode. A nickel oxide, which is electrically insulating, eventually forms on the surface of Ni particles. 2. Loss of Compressive Force The compressive forces acting to maintain contact among the conductive components are partly due to curing shrinkage achieved when curing the polymeric matrix of ACAs. Both the cohesive strength of the adhesive matrix and the interfacial adhesion strength between the adhesive matrix and the chip and chip carrier must be sufficient to maintain the compressive force. However, the thermal expansion of adhesives, their swelling due to moisture adsorption, and mechanical stresses due to applied loads tend to diminish this compressive force created as a result of curing. Moreover, water not only diffuses into the adhesive layer but also penetrates to the interface between the adhesive and the chip and chip carrier, causing a reduction in adhesion strength. As a result, the contact resistance increases and can even result in a complete loss of electrical contact [41].
IV. DESCRIPTION OF ISOTROPICALLY CONDUCTIVE ADHESIVES A. Percolation Theory of Conduction Isotropic conductive adhesives, also known as ‘‘polymer solders,’’ are composites of polymer resin and conductive fillers. The conductive fillers provide the composite with electrical conductivity through contact between the conductive particles. With increasing filler concentrations, the electrical properties of an ICA transform it from an insulator to a conductor. Percolation theory has been used to explain the electrical properties of ICA composites. At low filler concentrations, the resistivities of ICAs decrease gradually with increasing filler concentration. However, the resistivity drops dramatically above a critical filler concentration Vc, called the percolation threshold. It is believed that at this concentration, all the conductive particles contact each other and form a three-dimensional network. The resistivity decreases only slightly with further increases in the filler concentrations [42–44]. A schematic explanation of resistivity change of ICAs based on percolation theory is shown in Fig. 12. In order to achieve conductivity, the volume fraction of conductive fillers in an ICA must be equal to, or slightly higher than, the critical volume fraction. Similar to solders, ICAs provide the dual functions of electrical connection and mechanical bond in an interconnection joint. In an ICA joint (Fig. 13), the polymer resin provides mechanical stability and the conductive filler provides electrical conductivity. Filler loading levels that are too high cause the mechanical integrity of adhesive joints to deteriorate. Therefore, the challenge in formulating an ICA is to maximize conductive filler
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FIG. 12 Effect of filler volume fraction on the resistivity of ICA systems.
content to achieve high electrical conductivity without adversely affecting the mechanical properties. In a typical ICA formulation, the volume fraction of the conductive filler is about 25–30% [45,46].
B. Adhesive Matrix Polymer matrices of isotropic conductive adhesives are similar to anisotropically conductive adhesives. An ideal matrix for ICAs should exhibit a long shelf life (good room temperature latency), fast cure, relatively high glass transition temperature (Tg), low moisture pickup, and good adhesion [47]. 1. Matrix Materials Both thermoplastic and thermoset resins can be used for ICA formulations. The main thermoplastic resin used for ICA formulations is polyimide resin. An attractive advantage of thermoplastic ICAs is that they are reworkable (e.g., can easily be repaired). A major drawback of thermoplastic ICAs, however, is the degradation of adhesion at high temperature. Another drawback of polyimide-based ICAs is that they generally contain solvents. During heating, voids are formed when the solvent evaporates. Most of commercial ICAs are based on thermosetting resins. Epoxy resins are most commonly used in thermoset ICA formulations because they possess superior balanced properties. Silicones, cyanate esters, and cyanoacrylates are also employed in ICA formulations [48–52].
FIG. 13 Schematic that illustrates how electrical conduction paths are established by uninterrupted particle-to-particle contact between the component and chip carrier terminal pads in an ICA joint.
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2. Achieving Latency and Rapid Curing Most commercial ICAs must be kept and shipped at a very low temperature, usually 40jC, to prevent the ICAs from curing. Pot life is a very important factor for users of ICAs. In order to achieve desirable latency at room temperature, epoxy hardeners must be carefully selected. In some commercial ICAs, solid curing agents are used, which do not dissolve in the epoxy resin at room temperature. However, these curing agents can dissolve in the epoxy at a higher temperature (curing temperature) and react with the epoxy resin. Another approach to achieve latency is to employ an encapsulated imidazole as a curing agent or catalyst. An imidazole is encapsulated inside a very fine polymer sphere. At room temperature, the polymer sphere does not dissolve or react with the epoxy resin. But at a higher temperature, after the polymer shell is broken, the imidazole is released from the sphere to cure the epoxy or catalyze the cure reaction. Fast cure is another attractive property of a desirable ICA. Shorter cure times increase throughput, resulting in lower processing cost. In epoxy-based ICA formulations, proper hardeners and catalysts such as imidazoles and tertiary amines can be used to achieve rapid cure. 3. Effect of Low Tg Materials Conductive adhesives with low Tg values can lose electrical conductivity during thermal cycling aging [53,54]. Electrical conductivity in metal powder, filled conductive adhesives is achieved through the contact of adjacent metal particles with each other, thus producing a continuous electrical path between a component lead and a metallized pad. When a joint is subjected to thermal cycling conditions, it experiences repeated cyclical shear motion of the lead relative to the chip carrier pad. The amount of shear strain is primarily dependent on the thermal cycling condition and the thermal expansion mismatch between the component and the chip carrier. Neglecting lead deformation and substrate compliance, the majority of the shear strain produced is accommodated by viscoelastic or viscoplastic deformation of the conductive adhesive. When a conductive adhesive deforms to accommodate the shear strain produced, the metal particles move, thus changing the position of contact point(s) between adjacent metal particles. If the organic matrix is too compliant, it will flow to fill the area left behind the moving metal particles. When the direction of the shear strain is reversed during thermal cycling, adjacent metal particles move back to their original contact locations, which now are partially covered with the compliant, dielectrical organic–matrix material. As the number of thermal cycles increases, the contact resistance between adjacent particles increases, thus increasing the interconnection joint resistance [53]. 4. Effect of Moisture Absorption Moisture absorption can influence the reliability of conductive adhesive interconnection joints. Moisture in polymer composites is known to have an adverse effect on both the mechanical and electrical properties of epoxy laminates [54,55]. Studies relating to the reliability and moisture sensitivity of electronic packages indicate similar degrading effects. It was determined that moisture absorption can cause an increase in contact resistance, especially if the metallization on the bond pads and components is not a noble metal [56]. Effects of moisture absorption on conductive adhesive joints are summarized in Table 2. In order to achieve high reliability, conductive adhesives with low moisture absorption are required. High adhesion strength to pad
TABLE 2
Effects of Moisture on ICA Joints
Major effects . . . . .
Degrades bulk mechanical strength Decreases interfacial adhesion strength and causes delamination Promotes the growth of voids present in joints Gives rise to swelling stress in joints Induces the formation of metal oxide layers resulting from corrosion
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and component metallization is a necessary property for conductive adhesives used for interconnections in electronic assemblies. Epoxy-based ICAs tend to have better adhesion strength than polyimide and silicone-based ICAs. However, a silicone matrix tends to have lower moisture absorption than epoxy resins [49].
C. Conductive Fillers Because polymer matrices are dielectrical materials, conductive fillers in ICA formulations provide the material with electrical conductivity. In order to achieve high conductivity, the filler concentration must be at least equal, or higher than, the critical concentration predicted by percolation theory. 1. Pure Silver vs. Ag-Coated Fillers Silver (Ag) is, by far, the most popular conductive filler, although gold (Au), nickel (Ni), copper (Cu), and carbon are also used in ICA formulations. Silver is unique among all of the costeffective metals by nature of its conductive oxide (Ag2O). Oxides of most common metals are good electrical insulators and copper powder, for example, becomes a poor conductor after aging. Nickel-based and copper-based conductive adhesives generally do not have good conductivity stability because they are easily oxidized. Even with antioxidants, copper-based conductive adhesives show an increase in volume resistivity on aging, especially under hightemperature and humidity conditions. Silver-plated copper has been utilized commercially in conductive inks, and should also be appreciable as a filler in adhesives. Although composites filled with pure silver particles often show improved electrical conductivity when exposed to elevated temperature and humidity or thermal cycling, this is not always the case with silver-plated metals, such as copper flake. Presumably, the application of heat and mechanical energy allows the particles to make more intimate contact in the case of pure silver, but silver-plated copper may have coating discontinuities that allow oxidation/corrosion of the underlying copper and thus reduce electrical paths [45]. 2. Particle Shape and Size The most common morphology of conductive fillers used for ICAs is flake because flakes tend to have a large surface area and more contact spots, and thus more electrical paths than spherical fillers. The particle size of ICA fillers generally ranges from 1 to 20 Am. Larger particles tend to provide the material with a higher electrical conductivity and lower viscosity [57]. A new class of silver particles, porous nanosized silver particles, has been introduced in ICA formulations [58,59]. ICAs made with this type of particles exhibited improved mechanical properties, but the electrical conductivity is less than ICAs filled with silver flakes. In addition, short carbon fibers have been used as conductive fillers in conductive adhesive formulations [60,61]. However, carbon-based conductive adhesives show much lower electrical conductivity than silver-filled ones. 3. Silver–Copper Fillers A powder with a specific structure was introduced as a filler for conductive adhesives in 1992 [62]. The powder particle consists of two metallic components: copper and silver. Silver is highly concentrated on the particle surface and the concentration gradually decreases from the surface to the inner of the particle, but always contains a small amount of silver. Conductive adhesive paste filled with this powder exhibits excellent oxidation resistance (i.e., can be exposed to an oxygen content of about 100 ppm in a nitrogen atmosphere without oxidizing). It also exhibits higher solderability than commercially available copper pastes, sufficient adhesion strength even after heating and/or cooling test, and the least migration, almost of the same degree as pure copper paste [62]. 4. Low-Melt Fillers In order to improve electrical and mechanical properties, low-melting-point alloy fillers have been used in ICA formulations. A conductive filler powder is coated with a low-melting-point metal. The conductive powder is selected from the group consisting of Au, Cu, Ag, Al, Pd, and Pt.
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The low-melting-point metal is selected from the group of fusible metals, such as Bi, In, Sn, Sb, and Zn. The filler particles are coated with the low-melting-point metal, which can be fused to achieve metallurgical bonding between adjacent particles and between the particles and the bond pads that are joined using the adhesive material [63,64].
V. FLIP-CHIP APPLICATIONS USING ISOTROPIC CONDUCTIVE ADHESIVES A key factor in achieving a low-cost flip-chip technology is the use of isotropic conductive adhesives. In comparison to classical flip-chip technologies, the use of ICAs for bumping and joining provides numerous advantages (Table 3). Motorola successfully demonstrated an ICA flip-chip bumping process using stencil printing technology both through mathematical modeling and experimentation [65]. Both GaAs and Si flip-chip devices with Au thin film metallization, and alumina and FR4 chip carriers also with Au metallization were used in this study. The electrical performance of chip and chip carrier combinations (i.e., GaAs/Al2O3, GaAs/FR4, and Si/FR4) utilizing conductive adhesive polymer bumps showed no difference from Au and AuSn bumps (all of the flip-chip dies are mounted onto the chip carriers using an ICA). However, more studies are required to address the issues of premature failure observed in HAST and thermal shock tests. The polymer bumping method is a low-cost and efficient process conducted at the wafer level and suitable for large-scale production. Data of joint resistance stability under accelerated aging conditions such as 85jC/85% RH and temperature cycling demonstrate that polymer flip-chip interconnections are capable of long-term stability. The polymer flip-chip assembly is compatible to a large range of rigid carriers and heat-sensitive, flexible chip carriers—a key advantage of polymer flip chip (PFC) over solder flip-chip technology. Currently, PFC is widely used for flipchip bonding on low-cost heat-sensitive chip carriers noted in Table 4 [66].
A. Process Several flip-chip bumping and joining techniques have been reported in the literature. Flip chips using ICAs are often called PFCs. The PFC process is a stencil printing technology in which an ICA is printed through a metal stencil to form polymer bumps on bond pads of IC devices subsequent to the underbump metallization (UBM) deposition on aluminum termination pads. The sequential processes to achieve PFC interconnects are UBM deposition, stencil printing an ICA, bump formation (ICA solidification), flip-chip attachment to achieve electrical connections, and underfill for enhanced mechanical and environmental integrity [65, 67]. 1. Protective Chip Pad Layer As with virtually all flip-chip processes, the Al bond pads must be protected to eliminate the formation of nonconductive aluminum oxide. This insures a low and stable resistance at bond– bond pad interface. The polymer flip-chip process utilizes an electroless plating technique, Ni/Au
TABLE 3
Advantages of Flip-Chip Technologies Utilizing ICAs
Advantages . . . . .
Process simplification and reduction of indexing steps by eliminating activation and purification processes A smaller temperature load on elements and wiring carriers Availability of a large spectrum of material combinations A broad range of applicable adhesive systems allows the selection of processing parameters and joining characteristics Few requirements for UBM because alloy phase formation does not have to be considered
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Low-Cost, Heat-Sensitive Chip Carriers Utilized in Polymer Flip-Chip Applications
Applications of polymer flip-chip bonding . . . . . .
Microcontroller chips on polyethylene terephthalate (PET) substrates Transponder chips on polyvinylechloride (PVC)/Acrylonitrile butadiene styrene (ABS)/PET/ polycarbonate (PC)/polyimide (PI) foils for smart card inlays Circuits on flexible systems (e.g., Dycostrate) Controller and driver circuits on polyester base materials in combination with adhesive-bonded components Circuits on rigid and multilevel substrates such as FR4 boards or BGAs in combination with SMD components Temperature-sensitive sensors and actuators on most diverse carriers and complex microsystems
or Pd, to cover the Al bond pads prior to polymer bumping. The typical metal thickness is 0.5–1.0 Am for Pd and 3.0–5.0 Am for Ni/Au. 2. Print ICA The PFC process combines high precision stencil printing techniques with highly conductive ICAs. These polymers can be thermosets or thermoplastics. First, the polymer bumps are formed by deposition of an ICA through the metal mask directly onto the metallized bond pads on a wafer. Printed conductive adhesive bumps can offer an attractive alternative to the other bumping technologies in terms of cost and manufacturability. The printing process typically involves a screen or stencil with openings through which bumps are deposited. A screen consists of an interwoven wire mesh with an emulsion that covers the wire mesh. The emulsion is photolithographically patterned to match the bump sites. Stencils are made of metal foil. Holes for bump deposition are made by etching, electroforming (plating), or laser drilling. During the printing process, the paste is typically dispensed some distance away from the stencil apertures. A schematic of the printing process is shown in Fig. 14. Typically, the stencil is separated from a substrate by the snapoff distance. The squeegee is lowered, resulting in contact of the stencil to the substrate or wafer surface. As the squeegee moves across the stencil surface, a stable flow pattern develops in the form of a paste roll. The consequent hydrodynamic pressure developed by the squeegee pushes the paste into the patterned stencil openings. The stencil lifts away from the substrate surface with the paste remaining on the substrate. 3. Curing The polymer bumps are then either fully cured or partially cured to the so-called B-stage for thermosetting polymer bumps. For thermoplastic polymer bumps, after stencil printing, the
FIG. 14 Schematic depicting the ICA paste stencil printing process. (From Ref. 65.)
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solvent is removed to form solid bumps. Bump heights are typically 50–75 Am and the process can accommodate pitches down to 5x. Bump densities of up to 80,000 bumps per wafer have been formed with excellent coplanarity. Once the bumped wafers are diced, chips are picked from the wafers, flipped over, and then placed on and bonded to chip carriers. Different process procedures are utilized to bond thermosetting polymer bumps to similar thermoplastic bumps, as noted in Fig. 15. The final
FIG. 15 Schematic illustrating various die attachment assembly processes utilizing ICAs. (a) Chip with cured ICA bumps mated with uncured ICA on carrier pads. (b) Chip with partially cured (Bstaged) ICA bumps mated with bare carrier pads. (c) Chip with thermoplastic ICA bumps mated with bare but preheated carrier pads.
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processing involves a heat cure for thermosetting bumps, whereas thermoplastic bump connections only require a few seconds under heat and pressure to melt the thermoplastic. 4. Underfill An underfill is then injected into the gap between the chip and the chip carrier, and then cured to complete the flip-chip process. The function of the underfill, or encapsulation, as it is sometimes referred to, is to provide mechanical integrity and environmental protection to a flip-chip assembly. Studies have demonstrated that both thermoset and thermoplastic ICAs can offer low initial joint resistances of less than 5 mV and stable joint resistances (Au-to-Au flip-chip bonding) during all the accelerated reliability testing listed in Table 5. The reliability results have indicated that there is no substantial difference in the performance of thermoset and thermoplastic bumps, and that both types of polymers offer reliable flip-chip electrical interconnections [67].
B. Metal-Bumped Flip-Chip Joints ICAs can also be used to form electrical interconnections with chips that have metal bumps. Isotropic conductive adhesive materials utilize much high filler loading than ACAs to provide electrical conduction isotropically (i.e., in all directions) throughout the material. In order for these materials to be used for flip-chip applications, they must be selectively applied to only those areas that are to be electrically interconnected. In addition, the materials are not to spread during placement or curing to avoid creating electrical shorts between circuit features. Screen or stencil printing is most commonly used to precisely deposit the ICA pastes. However, satisfying the scale and accuracy required for flip-chip bonding requires very accurate pattern alignment. To overcome this difficult requirement, Matsushita Electric Industrial Co. Ltd. [68] developed a transfer method. Raised studs or pillars are required on either the die or the chip carrier. Matsushita Electric Industrial Co. Ltd. uses a conventional ball bonder to form Au stud bumps. Bumping is significantly faster than creating complete wire bonds. A ball bumping process eliminates the need for traditional sputtering and plating processes used for standard bump formation. To prevent the bond area from becoming too large, the bumps are formed in a conical shape. The bumps are pressed level by a flat surface, which adjusts both height and planarity. The ICA is selectively transferred on the bump tips by contacting the face of the die to a flat thin film of the ICA, which is produced by screen printing and whose transfer thickness is controlled by changing the printed film thickness. Then the die is picked, aligned, and placed on a chip carrier. The whole assembly is exposed to heat to cure the ICA and form connections between the die and the chip carrier. Finally, an underfill (an insulating adhesive) is dispensed between the die and the chip carrier, and then cured. This method offers the options of oven curing an assembly because bonding pressure is not required. A specially formulated ICA is used to avoid silver migration, containing 20% palladium in a silver palladium alloy. A schematic of the process flow of forming joints with stud-bumped flip chips using ICAs is shown in Fig. 16. 1. Comparison with Soldered Joints Another process for bonding a flip chip with metal bumps consists of screen printing an ICA on a chip carrier, aligning and placing the chip, curing the ICA to form bonds, and underfilling. By
TABLE 5
Accelerated Reliability Testing
Test Temperature cycle Thermal shock Elevated temperature and humidity Pressure cooker
Condition
Time
55jC to 150jC 55jC to 125jC 85jC/85% RH 121jC/15 psi
1000 cycles 500 cycles 1000 hr 168 hr
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FIG. 16 A schematic of the process flow of joints formed with stud-bumped flip chips using ICAs. (a) Tips of the gold stud bumps formed with a wire bond tool are planarized. (b) Planarized bumps are dipped into a thin layer of ICA. (c) The chip is withdrawn, leaving the bumps coated with ICA. (d) The chip is placed on mating pads of a chip carrier with pressure required during curing. (e) An underfill (an insulating adhesive) is dispensed and cured.
using this approach, SINTEF Electronics conducted a comparison study between ICA-bonded and solder-bonded flip chips on FR4 chip carrier with Ni/Au metallization. The number of thermal cycles (55jC to 125jC) to failure for both solder and ICA flip-chip circuits was compared. The study showed that stable contacts could be maintained for at least 1000–2000 cycles for ICA flip-chip joints. This is comparable to the lifetime of solder flip-chip joints. However, the variation among ICA samples was very high and optimization of assembly processes is needed in order to achieve more reproducible joint resistance [69].
C. ICA Process for Unbumped Chips Another polymer flip-chip bumping process is known as micromachined bumping [70,71]. The bumping procedure is illustrated in Fig. 17. Initially, Cr/Au contact metal pads for conductive polymer bumps are deposited on Si wafers, followed by patterning a thick photoresist to create bump holes. A high-aspect ratio and straight sidewall patterns are very important in shaping the conductive polymer bumps. After lithography, thermoplastic conductive polymer materials, usually thermoplastic pastes filled with Ag flakes, are applied by either dispensing or screen printing the pastes into the bump hole patterns. The wafer is heated in a convection oven to remove the solvent. Due to the difference in curing conditions between the thick photoresist and the conductive polymer, the photoresist can be carefully stripped to expose the dried polymer bumps. Finally, the wafer is diced into individual chips.
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FIG. 17 A schematic depicting flip-chip application utilizing chips with micromachined polymer bumps. (a) Process flow for creating micromachined polymer bumps in the wafer state. (b) Die attachment to a chip carrier.
Chips with thermoplastic bumps are placed on chip carriers and preheated to approximately 20jC above the melting point of the polymer, causing the bumps to reflow onto the matching chip carrier pads. Mechanical and electrical bonds are established as the chip carrier cools below the polymer melting temperature. To enhance the mechanical bonding strength, a small amount of pressure can be applied by placing a weight on the chip. This flip-chip bonding technique has high potential to replace conventional solder flip-chip techniques for sensor and actuator systems, optical microelectromechanical systems (MEMS), optoelectonic multichip modules (OE-MCMs), and electronic system applications [71].
VI. APPLICATIONS OF ICAs IN MICROELECTRONICS PACKAGING A. Surface Mount Applications Tin–lead solders (Sn–Pb) are the standard materials used to interconnect electronic components on PCBs. The most common reflow soldering process is SMT, which uses tin/lead solder pastes.
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The pressure to reduce the industrial use of lead is growing, particularly in Europe, because it poses as a hazard to human health [72]. 1. Advantages Thus, the use of tin–lead solder pastes in SMT processes must be reduced or eliminated to satisfy both legislative actions and market-driven pressures as well. Lead-free and environmentally sound interconnect bonding processes are urgently needed. Among the possibilities are ECAs and lead-free solders [73–75]. Compared to soldering technology, ECA technology can offer numerous advantages, such as fewer processing steps, which reduces processing cost; lower processing temperature, which makes the use of heat-sensitive and low-cost chip carriers possible; and fine-pitch capability [74]. 2. Disadvantages However, conductive adhesive technology is still in its infancy, and concerns and limitations do exist. The main limitations of commercial ICAs include lower conductivity than solder materials, an unstable contact resistance with nonnoble metal finished components, and poor impact performance. The electrical conductivity (f104 V1 cm1) of an ICA is lower than that of Sn–Pb solders (f105 V1 cm1). Although generally adequate for most electronics applications, the electrical conductivity of ICAs must be improved. Contact resistance between an ICA and nonnoble metal (such as Sn–Pb, Sn, and Ni) finished components is noted to dramatically increase with time, especially under elevated temperature and humidity aging conditions [76–79]. In addition, printed circuit board assemblies are often subjected to significant mechanical shock during assembly, handling, and throughout their product life. Packages cannot survive without adequate impact resistance. However, most microelectronic commercial ICAs exhibit poor impact performance. Components assembled using ICAs tend to separate from the substrate when the package experiences a sudden shock [78,80]. For conductive adhesive technology to provide an acceptable solution as a solder replacement, new conductive adhesives with the desired overall properties must be developed [78]. There has been considerable effort to improve the properties of ICAs, and to make them more reliable materials. These improvements are described in the following sections. 3. CSP Applications Matsushita Electric Industrial Co. Ltd. developed solderless joining technologies using nickelfilled isotropic conductive adhesives to mount a ceramic chip scale package (CSP-C) onto an FR4 board [81]. Nickel was selected instead of Ag because, unlike Ag, nickel does not migrate. A significant CTE mismatch existed between the CSP-C ceramic chip carrier (CTS=7 ppm) and the FR4 organic chip carrier (CTE=16 ppm). This CTE mismatch resulted in large stress being generated within the solder joints during ATC testing, which resulted in early failure due to solder fatigue. ICAs usually exhibit better thermomechanical properties than solders. In addition, metal migration between joints is a great concern because the joints in a CSP area array package are arranged with a close pitch (i.e., in close proximity). The packaging procedure was as follows: (a) the ICA was screen-printed on the area array lands of the FR4 motherboard; (b) the CSP-C was mounted; and (c) the ICA was cured to form bonds. The Ni-filled conductive adhesive demonstrated a much higher resistance to metal migration compared to Ag-filled IACs, and equivalent to solder joints. In addition, the thermal fatigue life of the Ni-filled ICA joints was five times greater than comparable solder joints.
B. High-Frequency Performance of ICA Joints Only very limited work has been conducted to investigate the high-frequency behaviors of ICA joints. Felba et al. [82] investigated a formulation of isotropically conductive adhesives that performed well as a solder replacement in microwave applications. The study involved various different adhesive base materials and several types of main (silver flakes, nickel, and graphite) and additional (soot and silver semiflake powder) filler materials. In order to assess the usefulness of a given adhesive formulation, an additional gap in the gold strip of a standard microstrip bandpass
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filter was made and bridged by an adhesive bonded silver jumper. Both the quality factor ( Qfactor) and loss factor (L) of the filter with the bonded jumper were measured at a frequency of 3.5 GHz in a preliminary experiment, and at 3.5 and 14 GHz in a final experiment. It was determined that silver flake powders are the best filler materials for ICA for microwave applications because ICAs filled with silver flake powders exhibit the highest Q-factor and lowest loss factor. Also, the addition of soot should be avoided because it decreases the quality factor [82]. A study was conducted at Georgia Institute of Technology on a flip-chip test vehicle mounted on an FR4 chip carrier with gold-plated copper transmission lines [83]. The performance of eutectic Sn–Pb and ICAs was evaluated and compared using this test device. Both ICAs and eutectic Sn–Pb solders were determined to exhibit almost the same behavior at a frequency range of 45 MHz–2 GHz and the measured transmission losses for both materials were minimal. It was also found that the S11 characteristics of both Sn–Pb and ICAs after exposure to 85jC/ 85% RH aging for 150 hr did not vary from the previous signals prior to aging, but the S12 value of the Sn–Pb joints deviated more than that of ICA joints after aging.
C. Fatigue Life of ICA Joints There have been several studies investigating the fatigue life of ICA joints. Aiming to understand the performance of ICA interconnects under fracture and fatigue loading, Constable et al. [84] investigated the performance of ICA interconnects under fracture and fatigue loading by monitoring resistance changes (AV sensitivity) of ICA joints during pull and fatigue testing (cyclical loading up to 1000 cycles). Observation of the fracture surface suggested that the ICA joint life depended upon the adhesive failure of the bond to the metal surface. It was observed that fracture strains for ICAs were in the range of 20–38%, and resistance remained approximately constant in the elastic region, but the resistance started to increase rapidly as soon as the pull force departed from linear elastic behavior. For fatigue tests, linear displacement was ramped up the preprogrammed maximum displacement and ramped back to the starting position. It was observed that the shear strain for ICA joints surviving 1000 cyclical loading was typically 10%, which is about an order of magnitude greater than solders. This suggests that using conductive adhesives may be advantageous for some flip-chip applications. It is believed that because silver filler particles of ICAs cannot accommodate this large strain, the silver filler particles must move relative to one another as the epoxy matrix is strained. The most common pattern of resistance change was only increased to a point corresponding to about a 70% loss in interface contact resistance before sudden failure. This was an indication that the interface crack slightly propagated into the adhesive [84]. In an effort to gain a fundamental understanding of the fatigue degradation of ICAs, Gomatam et al. [85] studied the behavior of ICA joints under temperature and humidity conditions. The fatigue life decreased at elevated temperature and high humidity conditions. It was also observed that the fatigue life of the ICA joints decreased considerably as the temperature cycle frequency was decreased. This effect was attributed to the fact that as the frequency was decreased, the propagating crack was exposed to higher loads for longer periods of time, effectively resulting in high creep loading [85].
VII. IMPROVEMENT OF ELECTRICAL CONDUCTIVITY OF ICAs Electrical conductivity of ICAs is inferior to solders [86]. Even though the conductivity of ICAs is adequate for most applications, a higher electrical conductivity of ICAs is still needed. To develop a novel ICA for modern electronic interconnect applications, a thorough understanding of the materials is required.
A. Eliminate Lubrication Layer An ICA is generally composed of a polymer binder and Ag flake filler materials. A thin layer of organic lubricant is present on the surface of the Ag flakes. This lubricant layer plays an
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important role in the performance of ICAs, including the dispersion of Ag flakes in adhesives and the rheology of adhesive formulations [86–89]. The organic layer consists of an Ag salt formed between the Ag surface and the lubricant, which typically is a fatty acid such as stearic acid [89,90]. This lubricant layer affects the conductivity of an ICA because it is electrically insulating [89,90]. To improve conductivity, the organic lubricant layer must be partially or fully removed through the use of chemical substances that can dissolve the organic lubricant layer [89–91]. However, the viscosity of an ICA paste may increase if the lubricant layer is removed. An ideal chemical substance (or lubricant remover) should be latent (does not remove the lubricant layer) at room temperature, but be active (capable of removing the lubricant layer) at a temperature slightly below the cure temperature of the polymer binder. The lubricant remover can be a solid short-chain acid, a high-boiling-point ether such as diethylene glycol monobutyl ether or diethylene glycol monoethyl ether acetate, and a polyethylene glycol with a low molecular weight [89–91]. These chemical substances can improve the electrical conductivity of ICAs by removing the lubricant layer on the Ag flake surfaces and by providing an intimate flake–flake contact [89,90].
FIG. 18 A schematic of a joint formed using transient liquid-phase sintering conductive adhesives. (a) Initial state after chip attachment and before temperature reaches the melting point of the lowmelting alloy filler. (b) The low-melting alloy fillers start to melt and dissolve the high-melting alloy filler. (c) After the high-melting alloy fillers are completely dissolved, the liquid metal phase solidifies and forms a 3-D network in the joint.
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B. Increase Shrinkage In general, ICA pastes exhibit low electrical conductivity before cure, but the conductivity increases dramatically after they are cured. ICAs achieve electrical conductivity during the cure process, mainly through a more intimate contact between Ag flakes caused by the shrinkage of the polymer binder [92]. Accordingly, ICAs with high cure shrinkage generally exhibit the best conductivity. Therefore, increasing the cure shrinkage of a polymer binder is another method for improving electrical conductivity. For ICAs based on epoxy resins, a small amount of a multifunctional epoxy resin can be added into the formulation to increase cross-linking density and shrinkage, and thus increase conductivity [92].
C. Transient Liquid-Phase Fillers Another approach for improving electrical conductivity is to incorporate transient liquid-phase sintering metallic fillers into ICA formulations. The filler used is a mixture of a high-melting-point metal powder (such as Cu) and a low-melting-point alloy powder (such as Sn–Pb). Upon reaching its melting point, the low-melting-point powder liquefies, dissolving the high-melting-point particles. The liquid exists only for a short period of time and then forms an alloy and solidifies. The electrical conductivity is established through a plurality of metallurgical connections formed in situ from these two powders in a polymer binder. The polymer binder fluxes both the metal powders and the metals to be joined, facilitates the transient liquid bonding of the powders to form a stable metallurgical network for electrical conduction, and also forms an interpenetrating polymer network providing adhesion (Fig. 18). High electrical conductivity can be achieved using this method [92–95]. The ICA joints formed include metallurgical alloying to the junctions as well as within the adhesive itself. This provides a stable electrical connection during elevated temperature and humidity aging. In addition, the ICA joints showed good impact strength due to the metallurgical interconnection between the conductive adhesive and the components. One critical limitation of this technology is that the numbers of combinations of low-melt and highmelt fillers are limited. Only certain combinations of metallic fillers that are mutually soluble exist to form this type of metallurgical interconnections.
VIII. IMPROVEMENT OF CONTACT RESISTANCE STABILITY Contact resistance between an ICA (generally an Ag flake-filled epoxy) and nonnoble metal finished components increases dramatically during elevated temperature and humidity aging, especially at 85jC/85% RH. The National Center of Manufacturing and Science (NCMS) defined the stability criterion for solder replacement conductive adhesives as a contact resistance shift of less than 20% after aging at 85jC/85%RH conditions for 500 hr [77].
A. Causes for Resistance Increase Two main mechanisms, simple oxidation and corrosion of the nonnoble metal surfaces, have been proposed in the literature as the possible causes for the increase in contact resistance of ICA joints during elevated temperature and humidity aging. Simple oxidation of the nonnoble metal surface is claimed as the main reason for the observed increased resistance. Corrosion is claimed as the possible mechanism for resistance increase only by several investigators [75,76,96–98]. One study strongly indicates that galvanic corrosion, rather than simple oxidation, of the nonnoble metal at the interface between an ICA and a nonnoble metal is the main reason for the shift in contact resistance of ICAs (Fig. 19) [99,100]. The nonnoble metal acts as the anode, and is reduced to a metal ion (Mne=Mn+) due to the loss of electrons. The noble metal acts as a cathode, and its reaction generally is 2H2O+O2+4e=4OH. Then Mn+ combines with OH to form a metal hydroxide or a metal oxide. As a result of this electrochemical (corrosion) process,
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FIG. 19 Schematic depicting the effect of galvanic corrosion of a nonnoble metal pad on electrical conduction of a silver-filled ICA. (a) Good electrical conduction before corrosion. (b) Poor electrical conduction due to the formation of a metal hydroxide, or oxide formation as a result of galvanic corrosion.
a layer of metal hydroxide or metal oxide is formed at the interface that is electrically insulating, causing the contact resistance to increase dramatically [99,100].
B. Prevention 1. Reduction of Moisture Absorption Galvanic corrosion requires the presence of moisture. An electrolyte solution must be formed at the interface before galvanic corrosion can occur. Therefore, one way to prevent galvanic corrosion at the interface between an ICA and the nonnoble metal surface is to lower the moisture absorption of the ICA. ICAs that have low moisture absorption generally exhibit more stable contact resistance on nonnoble surfaces compared with those with high moisture absorption [101,102]. Without an electrolyte, galvanic corrosion rate is very low. The electrolyte in this case is mainly from the impurity of the polymer binder (generally epoxy resins). Therefore, ICAs formulated with high-purity resins should perform better. 2. Use of Corrosion Inhibitors Another method of preventing galvanic corrosion is to introduce organic corrosion inhibitors into ICA formulations [100–103]. In general, organic corrosion inhibitors act as a barrier layer between the metal and the environment, forming a film over the metal surfaces [104–107]. Some chelating compounds are especially effective in preventing metal corrosion [106]. Most organic corrosion inhibitors react with the epoxy resin at a specific temperature. Therefore, if an ICA is epoxy-based, the corrosion inhibitors must not react with the epoxy resin during curing, which would cause them to be consumed and lose their effect. Organic corrosion inhibitors are thoroughly discussed in the literature [105,107]. Fig. 20 shows the effect of a chelating corrosion inhibitor on the contact resistance between an ICA and a Sn–Pb surface. It can be seen that this corrosion inhibitor is very effective in stabilizing the contact resistance.
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FIG. 20 Effect of a corrosion inhibitor on contact resistance between an ICA and a Sn–Pb surface with time and aging condition of 85jC/85% RH. (From Ref. 117.)
3. Use of Oxygen Scavengers Because oxygen accelerates galvanic corrosion, oxygen scavengers can be added into ICA formulations to slow down the corrosion rate [104]. When oxygen molecules diffuse through the polymer binder, they react with the oxygen scavenger and are consumed. However, when the oxygen scavenger is completely depleted, then oxygen can again diffuse into the interface and accelerate the corrosion process. Therefore, oxygen scavengers only delay the galvanic corrosion process. Similar to corrosion inhibitors, the oxygen scavengers used must not react with the epoxy resin at its cure temperature. The common oxygen scavengers utilized are listed in Table 6 [104,108–111]. 4. Sharp-Edge Filler Particles Another approach of improving contact resistance stability during aging is to incorporate some electrically conductive particles, which have sharp edges and are referred to as oxide-penetrating fillers, into the ICA formulations. Force must be provided to drive the oxide-penetrating particles through the oxide layer of adjoining particles and metal pads, and keep them in position. This can be accomplished by employing polymer binders that show high shrinkage when cured, as
TABLE 6
Commonly Used Oxygen Scavengers
Material list Hydrazine Carbohydrazide Hydroquinone Oximes Gallic acid Propyl gallate Hydroxylamines and related compounds Dihydroxyacetone 1,2-Dihydro-1,2,4,5-tetrazines Erythorbic acid
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FIG. 21 Schematic depicting an ICA joint containing oxide-penetrating particles and silver filler particles.
discussed in Sec. 7.2 (Fig. 21) [112]. This concept is used in Poly-Solder (a silver-loaded ICA material patented by Poly-Flex Circuits), which has good contact resistance stability with standard surface-mounted devices (SMDs) on both solder-coated and bare circuit boards [112].
IX. IMPROVEMENT OF IMPACT PERFORMANCE The ability to resist performance degradation when subjected to mechanical shock is a critical property that solder replacement ICAs must possess. There are ongoing efforts to develop ICAs that exhibit acceptable impact strength and are capable of passing the standard drop test used to evaluate the impact strength of components attached to a PCB. Among the methods are decreasing the filler loading to improve the impact strength [113], but this then reduces the electrical conductivity of the conductive adhesives. A development study was reported where conductive adhesives were formulated using low modulus resins that absorb the impact energy developed during a drop [114]. In addition, conformal coating of the surface-mounted devices has been used to improve mechanical strength. A study demonstrated that conformal coating improved the impact strength of conductive adhesives joints [115].
FIG. 22 Changes of loss factor (tan d) and the storage modulus with temperature of an ETPU-based conductive adhesive as measured by a dynamic mechanical analyzer (DMA). (From Ref. 117.)
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FIG. 23 The effect of frequency on the loss factor for two ICA materials. (From Ref. 117.)
A. Epoxide-Terminated Polyurethane (ETPU) Systems A class of conductive adhesives based on an ETPU was developed [116,117]. This class of conductive adhesives exhibits properties typical of polyurethane materials, such as high toughness and good adhesion. The modulus and glass transition temperature of an ICA can be adjusted by incorporating epoxy resins such as bisphenol F-based epoxies. Conductive adhesives based on ETPU exhibit a broad loss factor (tan d) peak with temperature and a high tan d value at room temperature. The tan d value of a material is a good indication of the damping property and impact performance of a material. In general, the higher the tan d value is, the better is the damping property (impact strength) of the material. As an example, changes in tan d and storage modulus with temperature of an ETPU-based ICA are shown in Fig. 22. ICAs based on ETPU resins also exhibit a much higher loss factor over a wide frequency range compared to ICAs based on bisphenol F epoxy resins (Fig. 23). This indicates that ICAs based on ETPU resins should exhibit good damping property and improved impact performance in a variety of electronic packages. This class of conductive adhesives has demonstrated superior impact performance and a substantial improvement in contact resistance stability with nonnoble metal surfaces, such as Sn–Pb, Sn, and Cu [116,117].
X. NONCONDUCTIVE ADHESIVES A. Micron Bump Technology Matsushita Electric Industrial Co. Ltd. was the first to use a nonconductive adhesive for flip-chip bonding in 1988, referred to as ‘‘Micron Bump Bonding Assembly Technology’’ [118,119]. Fig. 24 depicts a cross-sectional view of an LSI chip with Au bumps bonded to a chip carrier (with Cr/ Au pads) utilizing this method. The chip bonding accomplished by shrinkage induced in a lightcurable resin (i.e., the chip is held in place by the adhesive force of the resin and the bonding
FIG. 24 A schematic of a cross-sectional view of a flip chip with gold bumps held in place with a nonconductive, UV-curable resin referred to as ‘‘Micron Bump Bonding Technology.’’ (From Ref. 118.)
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connection is made by the internal shrinkage stress exerted by the resin). The technology can support pitches down to the micron range. There are virtually no restrictive factors to limit the pitch because an insulating resin is used for the bonding. Due to its flexible structure, the thermalinduced stresses in the assembly can be relieved to improve the reliability.
B. Applications 1. Print Heads Devices assembled using the method described Sec. 9 passed all the reliability tests noted in Table 7. This technology has been utilized in thermal print heads consisting of 32 driver LSI chips mounted on a ceramic chip carrier and a memory card where LSI chips are attached to an epoxy glass chip carrier. Micron bump bonding technology was also utilized on a light-emitting diode (LED) array module in a printer head. Both 54 LED GaAs chips and 54 LSI driver IC chips (each with gold bumps) were bonded to an SiO2-deposited sodium glass chip carrier, which had 2.5-Am-thick gold pads using a UV curable resin. The assembled devices all passed reliability tests including high temperature storage (125jC, 1000 hr), elevated temperature and humidity storage (85jC/85% RH, 1000 hr), and thermal shock (55jC to 125CjC, 100 cycles) [115]. 2. NCAs vs. ACAs in Flex Circuits The reliabilities of two different interconnection technologies (ACAs and NCAs) mainly to connect driver electronics to liquid crystal displays were compared. The connection was made between flexible kapton circuits and rigid glass chip carriers, and in one case to FR4 carriers. Tests were performed both on test structures and real displays. Anisotropic conductive films are extensively used in producing high-quality LCDs. Anisotropic conductive films contain a small volume fraction of conductive particles to accomplish electrical conductivity between the two connected contact areas. Nonconductive adhesives use the surface roughness on the individual mating contact pads to establish electrical contact. In comparison with conventional ACFs based on thermoset adhesives, the use of NCAs proved to be superior with respect to reliability. This result was verified by thermal cycling (30jC to 90jC) and humidity testing (85jC/85% RH) conducted on test structures and real displays [120]. 3. SMT Applications The use of both nonconductive epoxy adhesives and anisotropic conductive adhesives as a solder replacement for SMT was studied [121]. Quad flat pack components were connected to FR4 substrates and then subjected to temperature cycling. None of the tested adhesives passed the temperature cycling test in accordance with the military standard 883C [121]. Failure analysis indicated that impressions made in the contact area depend on the contact force and surface preparation. At very low contact forces, the presence of insulating oxide layers on the metal surfaces increased the contact resistance dramatically. However, as the contact force was increased, the contact resistance dropped rapidly [122]. 4. Flip-Chip Applications A low-cost flip-chip process using stud bumps with an NCA paste that does not require underfilling of the die was developed [123]. It was found to be particularly suitable for organic
TABLE 7 Reliability Tests for Flip-Chip Devices Assembled Utilizing Micron Bump Technology Test Thermal shock High-temperature storage Elevated temperature and humidity Vibration test
Condition
Time
55jC to 25jC 125jC 85jC/85% RH 10 G
2000 cycles 2000 hr 2000 hr
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chip carriers where CTE mismatches are critical concerns. It is compatible with large-scale production as well as prototyping. The process flow is illustrated in Fig. 25. The Au stud bumping step is preferably done at the wafer level. The gold stud bumps compensate for chip carrier noncoplanarity by deforming the bonding pads. The PCB must be designed to be compatible with the NCA flip-chip process. For example, metallized bias located in the flip-chip area must be blind to prevent any leakage of the NCA paste to the other side of the substrate. Before dispensing the NCA, the PCB must be dried and receive surface treatment to reactivate the surface and increase its surface tension. After dispensing the NCA using a screen-printing or dispensing machine, a die is aligned and its stud bumps are pressed onto mating NCA deposits on the chip carrier, causing the stud bumps to be deformed when contacted by the PCB pads. In the meantime, both sides of the package are heated to provide the thermal energy to cure the NCA. The flip-chip bonder for this application must be capable of applying a wide range of forces and temperatures while keeping the placement accuracy of the die. Equipment that meet the requirements of this process with a throughput of 100 dies per hour are available. Devices assembled using several selected NCAs showed acceptable reliability performance after thermal cycling and humidity aging tests. This technology is utilized in manufacturing at Valtronic SA to assemble subminiaturized electronic devices such as hearing aids and heart defibrillators [123]. 5. 3-D CSP Application Another application is a 3-D CSP multichip module that is based on a thin flexible PCB (Fig. 26). Due to improvements in the PCB manufacturing process, especially with regard to flex-polyimide and its metallization, a high-quality, bondable chip carrier was developed from which a compact electronic module was created with an optimal density within the three spatial dimensions. This packaging concept is used to produce electronic modules for hearing aids [123]. 6. Smart Labels KSW Microtec has developed a high-throughput technology for manufacturing smart labels using an NCA [124]. The aluminum pads commonly used on chips result in unstable ohmic
FIG. 25 Schematic depicting the process flow for a flip-chip technology based on NCAs. (a) The NCA is deposited on the chip carrier sites by screen printing or other suitable methods. (b) Au bumps are aligned with mating pads on the chip carrier (PCB) and place the chip. (c) The chip is held in place by the cured NCA.
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FIG. 26 A schematic depicting the construction of a 3-D multichip module based on CSP using an NCA. (From Ref. 123.)
contacts due to corrosion and oxidation, which result in the formation of an insulating aluminum oxide. A bumping technology based on the electroless deposition of palladium was developed. These Pd bumps have a rough surface covered with many small peaks, which act to break through oxide barriers on the chip carrier pads to provide good contact with underlying carrier pads such as copper. Smart labels have been produced in large scale very successfully for some time using this technology.
XI. FUTURE CHALLENGES A. Anisotropically Conductive Adhesives Significant research has been conducted on ACAs as a potential solder replacement for some electronics packaging applications. However, many aspects of this technology must be better understood before it can be widely used to replace lead-bearing solders. Some critical issues that must be addressed in the future are the following. a. Materials Development. The development of new ACA materials that have good adhesion, high Tg, fast curing, storage stability at ambient, and stable contact resistance after various conditions was frequently encountered in fields such as thermal aging and cycling, thermal shock, high temperature/high humidity/bias, etc. In addition, ACAs with low CTE are required. Commercially available ACAs typically exhibit very high CTEs because of the low filler loading levels utilized. Some preliminary studies have shown that ACAs with a low CTE created by introducing nonconductive silica fillers have a lower shear strain and better contact resistance stability during thermal cycling test [125]. b. High-Frequency Compatibility. The number of high-frequency applications and utilizations is increasing rapidly; thus, it is important to characterize cross-talk between particles, coupling with semiconductor devices, and other fundamental behaviors of ACAs under highfrequency conditions. It is also necessary to maximize the current carrying capability of ACAs at high-frequency range, and after exposure to various environment tests. c. Reliability. It is necessary to understand the effects of the chip carrier material on ACA join reliability. This is a key issue before ACA technology is widely utilized in manufactur-
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ing (i.e., in high-volume and low-cost applications). It is also necessary to establish failure rate prediction models for ACA joints for a wide variety of field conditions. It is essential to gain full understanding of the effects of high current and high power on ACA joints, degradation, and stress relaxation of polymeric matrices; the effects of temperature, humidity, and other environments on matrix materials; and the effects of fillers.
B. Isotropically Conductive Adhesives There have also been a significant number of studies to improve ICA technology. However, several critical issues associated with this technology must also be addressed before they can be used as a replacement for soldering technology. a. Electrical Characteristics. Electrical conductivity must be vastly improved because it is typically one or two orders of magnitudes lower than solders. Silver-filled ICAs achieve their electrical conductivity through a physical contact among the Ag flakes. Due to the high particle– particle contact resistance, ICAs exhibit a high bulk resistivity. Although some preliminary works have been done to improve electrical conductivity by introducing low-melting-point alloys, which form metallurgical interconnections with Ag flakes, additional work is necessary to achieve the desired electrical conductivity. In addition, the behavior of ICA joints under high-current or high-power conditions, and high temperature/humidity/bias is not clear. b. High-Frequency Performance. It has been demonstrated that silver-filled ICAs show similar performance to eutectic SnPb solders at the frequency range of 45 MHz–2 GHz. The highfrequency behavior of ICAs over a wider frequency range needs to be investigated and compared to solders. c. Reliability. Silver-filled ICAs have a potential for silver migration, which cause electrical shorts especially in fine-pitch applications. A palladium-treated silver filler exhibited much improved antimigration characteristics compared to standard silver-filled ICAs. However, the preparation of the Pd-coated silver particles is expensive. Some low-cost approaches must be developed. More comprehensive understanding of the fatigue resistance of ICA joints is required. Activities in this area have been limited and nonconclusive. d. Manufacturability and Yields. Because most commercial ICAs are epoxy-based, they are thermosetting materials and thus not reworkable. ICAs that are reworkable must be developed by using thermoplastic or thermally degradable resins. Due to their high surface tension, SnPb solders have a self-alignment capability during solder reflow operations. However, conventional ICAs cannot self-align. Therefore, components that are bonded using ICAs require a high placement accuracy. Some preliminary research has been conducted to improve the selfalignment capability of ICAs [126,127], but much more work has to be done.
REFERENCES 1. Wolfson, H.; Elliot, G. Electrically Conducting Cements Containing Epoxy Resins and Silver. US Patent, 2,774,747, 1956. 2. Matz, K.R. Electrically Conductive Cement and Brush Shunt Containing the Same. US Patent, 2,849,631, 1958. 3. Beck, D.P. Printed Electrical Resistors. US Patent, 2,866,057, 1958. 4. Gilleo, K. Assembly with conductive adhesives. Solder. Surf. Mt. Technol. February 1995, 19, 12– 17. 5. Hariss, P.G. Conductive adhesives: a critical review of progress to date. Solder. Surf. Mt. Technol. May 1995, 20, 19–21. 6. Ogunjimi, A.O.; Boyle, O.; Whalley, D.C; Williams, D.J. A review of the impact of conductive adhesive technology on interconnection. J. Electron. Manuf. 1992, 2, 109–118. 7. Asai, S.; Saruta, U.; Tobita, M.; Takano, M.; Miyashita, Y. Development of an anisotropic conductive adhesive film (ACAF) from epoxy resins. J. App. Polym. Sci. 1995, 56, 769–777. 8. Chang, D.D.; Crawford, P.A.; Fulton, J.A.; McBride, R.; Schmidt, M.B.; Sinitski, R.E.; Wong, C.P. An overview and evaluation of anisotropically conductive adhesive films for fine pitch elec-
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19 Reliability Aspects of Lead-Free Solders in Electronic Assemblies Puligandla Viswanadham and Steven O. Dunford Nokia Research Center, Irving, Texas, U.S.A.
Jorma Kivilahti Helsinki University of Technology, Helsinki, Finland
I. INTRODUCTION The implementation of lead (Pb)-free technology in microelectronics very much depends on the reliability of interconnections, in addition to other aspects. Thus, the focus of this chapter is on the reliability of lead-free interconnections in electronic assemblies. In the ensuing sections, some reliability fundamentals and reliability requirements are reviewed first. Reliability or long-term product performance under thermal and/or mechanical loading conditions depends on a number of factors. Some of the significant factors include the composition and physical properties of the interconnection alloy, printed wiring board (PWB) surface finish, and component lead termination finish. As the size of package-to-board interconnections becomes ever smaller due to electronic miniaturization and implementation of technologies such as direct chip attachment, additional complexities that affect reliability come into play. Variations introduced in the assembly process can also affect the ultimate product reliability. Reliability-conscious organizations address the issues by utilizing a combination of accelerated testing and modeling methods. Modeling and simulation provide an evaluation of potential reliability and the opportunity to optimize a package design through iterated evaluation of subsequent model validations with input from accelerated test condition findings. Tests are carried out until a sufficient number of failures occur in order to identify different failure mechanisms that may be operating and to obtain statistically significant failure distributions. The test methods selected must mimic actual loads that a product is anticipated to experience in the field, especially in regard to portable consumer products such as cellular phones, personal digital assistants, camcorders, etc. A multitude of thin-walled microvias with a variety of copper thickness, interconnections with extremely small solder volumes, board warpage, and poorly shaped solder joints all become concerns for product reliability. The test methods include cyclical bending, mechanical drop and shock, and vibration caused during product transportation. This chapter provides an overview of these various aspects. In this chapter, the reliability aspects of a number of Pb-free solders are addressed as they pertain to the metallurgical microstructure, influence of minor elements, effects of intermetallics, assembly, and thermal and mechanical reliability. A comparison with traditional tin–lead eutectic solder assemblies is made where appropriate.
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II. GENERAL RELIABILITY CONSIDERATIONS Reliability is a time-oriented concept of quality, where quality is defined as ‘‘meeting requirements.’’ Thus, reliability is the ability of a product to perform the requisite functions, or meet the defined requirements under a set of predetermined conditions over a specified period, which is the design life of a product. This ability is usually expressed as a probability, and therefore reliability is the probability that a given product will perform without failure under a given set of operating conditions for a stated period. For nonrepairable systems (a system composed of many subassemblies and components), the instantaneous failure rate, termed the hazard rate h(t), follows a pattern that changes with time. It is usually represented by a bathtub-shaped failure curve over time, as shown in Fig. 1 [1,1a]. It begins with an initial decreasing hazard rate attributed to premature failure due to defects. This is followed by a useful life period with an almost constant hazard rate due to intrinsic failures and, finally, a wearout period where the hazard rate increases rapidly with time.
A. Statistics 1. Definitions In evaluating the performance of products, several statistical concepts are utilized. Reliability and the occurrence of failures are expressed in terms of probabilities. The reliability function R(t) is the time-dependant reliability, or a survival probability up to a time t. In terms of failures, F(t) is the cumulative probability of failure at time t; these two terms are interrelated. F(t) is a monotonically increasing function of time and, as a probability, takes on values between 0 and 1 over time. Geometrically, F(t) is the area under the probability density function f(t). Thus, F(t) is the probability of failures occurring before or at time t. The probability of failure in the time interval Dt (t1 and t2) is given by: ð t2 fðtÞdt ¼ Fðt2 Þ Fðt1 Þ ð1Þ t1
Alternatively, if t1 is the start time, namely t1=0, and t2 is some time t, then the probability of failure in the time interval 0–t is given by: ð t¼t FðtÞ ¼ fðtÞdt ð2Þ t¼0
It follows then that: fðtÞ ¼
dFðtÞ dt
FIG. 1 The reliability ‘‘bathtub’’ curve.
ð3Þ
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The reliability at time t is R(t); it is the probability of survival and is expressed as: RðtÞ ¼ 1 FðtÞ
ð4Þ
and, fðtÞ ¼
dFðtÞ dRðtÞ ¼ dt dt
ð5Þ
Another useful function that is often used in reliability statistics is the hazard rate h(t); it is used to describe the failure rate of units that are still functional. The hazard rate can be considered as the proportion of units that survived a vanishingly small time interval as good units and failed during a subsequent short period of time. In other words, it is an indication of the instantaneous failure rate. Thus: hðtÞ ¼
fðtÞ fðtÞ ¼ RðtÞ 1 FðtÞ
ð6Þ
It is important to note that hazard rate h(t) indicates the fraction of failures that occur in the infinitesimal time duration where the sample is taken. It does not represent the entire sample population. The cumulative hazard function H(t) is obtained by integrating the hazard rate over the period of interest. Thus: ð t¼t hðtÞdt ð7Þ HðtÞ ¼ t¼0
In addition, it follows from Eqs. (4), (5), and (6): HðtÞ ¼ ln½1 FðtÞ
ð8Þ
The hazard rate concept is very useful in elucidating the typical life pattern associated with electronic components; the bathtub-shaped failure curve over a function of time is a good example. 2. Distributions Several statistical models are employed in modeling time-to-failure, which depends on the failure distribution. The most relevant among these are the exponential, lognormal, and Weibull distributions. The equations representing the three distributions are given in Table 1. Certain distributions may be better suited for specific types of failures. For example, failure data related to chemical process-related failures such as electromigration, corrosion, etc. are typically best fitted to lognormal distributions. Solder joint fatigue failures, on the other hand, are normally best fitted to a Weibull distribution. The three different regions of a bathtub curve can mathe-
TABLE 1
Reliability Distribution Models
Function
Exponential
Weibull
f(t)
1/ket/k
b/k(t/k)b1e(t/k)b
F(t)
1 et/k
1 e(t/k)
R(t)
et/k
e(t/k)
h(t)
1/k
b/k(t/k)b1
H(t)
t/k
(t/k)b
b
b
Lognormal h i p1ffiffiffiffiffi exp 1 2 ðlnt lÞ2 2r r 2pt h h ii 1 p1ffiffi lnt lnl r 2 1 þ erf 2 1 F(t) i pffiffiffiffiffiffi h 1=r 2pt exp ð1=2r2 Þðlnt lÞ2 pffiffiffi 1=2 1 erf 1= 2 ½ðlnt lnlÞ=r n h io ln 1 12 1 þ erf p1ffiffi2 lnt r lnl
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matically be represented by a Weibull distribution by changing the slope parameter b. When the b value is less than unity, the plot represents an early or premature failure. If b equals one, the plot represents the intrinsic failure region; for values greater than one, the distribution represents the wearout failures, as shown in Fig. 2. The failure data of area array solder joints (e.g., flip chips, ceramic ball grid arrays) are often fitted to a lognormal distribution. The choice of the distribution selected may depend on the confidence level chosen for the fit. A lognormal distribution may satisfactorily represent failure data at a lower confidence level in some cases. There are two variations for Weibull distributions: the two-parameter distribution and the three-parameter distribution. The third parameter, called the ‘‘location parameter,’’ represents the minimum time-to-failure. Sometimes the failure data exhibit a slight curvature at a lower failure probability deviating from a two-parameter Weibull distribution. A three-parameter Weibull distribution can be utilized to better fit the data. It is equally important to understand the physics of a failure (e.g., the physical characteristics that affect crack propagation). The variation of joint strength with increasing thermal cycling, the crack growth rate dependence on the area of a crack, the grain size structure, the presence of voids and their location, the nature and extent of intermetallic phases, etc. are all important. The mechanisms for eventual solder joint failures are activated early in the stress cycles, but failures are observed only after a critical stage is reached in the crack propagation that meets the failure criterion. The shape parameter usually captures the variation or spread in the joint quality within the sample population. The so-called characteristic life, namely, time for 63.2% of the population to fail, remains essentially the same in both two-parameter and three-parameter Weibull distributions because it always lies on the straight-line portion of a plot. Although the three-parameter Weibull distributions enable the incorporation of early fatigue failures into the analysis, it is crucial to ensure that the same failure mechanism is operative to cause failures represented later in the distribution. A detailed failure analysis of early failures as well as later failures enables this determination. Otherwise, the distribution may be purely a statistical artifact without a common physics-of-failure basis. Any reliability evaluation and inferences based upon it are incomplete without supporting evidence from failure analysis. Although a three-parameter Weibull distribution may provide a more accurate estimate of the time for early failures, a larger sample size for evaluation may also be required. Hence, an investigator must strike a balance by weighing all the aspects in the choice of a distribution to be used. 3. Acceleration Factor The determination of failure distributions under actual operating environments, although ideal, is impractical and prohibitive due to the long design life and/or market conditions that render the
FIG. 2 Weibull distribution hazard rates for b values, <1, 1, and >1.
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product obsolete before completion of the testing. It is important, however, to conduct extensive testing to ensure product reliability. Therefore, product testing is generally carried out at stress levels much higher than those encountered in service conditions in order to accelerate the process of inducing failures in a short period of time. Accelerated testing is done in such a manner that the failure mechanisms observed in the test samples are the same as that encountered in the field, and that there exists a predictable relation between the applied stress and the life of the product. An acceleration factor (AF) is defined as the ratio of the time-to-failure under service conditions (tf) to the time it takes to fail in the accelerated test environment (tt), and is given by: AF ¼
tf Nf or tt Nt
ð9Þ
where Nf is the number of cycles required for failure in the field, and Nt is the number of cycles required for failure in the test environment. The acceleration factor enables the projection of actual field failures based on accelerated tests. It is important to recognize that the determination of an acceleration factor is a nontrivial task. Yet, it is important to have the capability to project early field failures using acceleration factors.
B. Testing 1. Test vs. Field Failures Unlike early electronics products, modern-day electronic products experience a variety of stresses owing to their versatility, portability, and functionality. Product life cycles tend to be shorter and shorter, and application environments are becoming increasingly diverse. Thermally induced stresses are not the predominant stresses in some cases, especially for consumer products. Resistance to mechanical vibration, drop, shock, etc. will likely play an increasing role in determining product performance. Table 2 depicts various product categories, their typical operating temperature ranges, and anticipated life duration. In addition to environmental conditions, the location of an electronic assembly within a product can influence the stress levels that it experiences, and hence its performance. This is exemplified by automotive applications where the stress level experienced by the electronic assemblies can vary considerably, as listed in Table 3. These parameters are only intended as representative conditions. Actual field conditions can have a profound influence on the choice and selection of accelerated test parameters for product qualification and assurance. Any variance in the failure mechanism between a test and a field condition usually invalidates the life predictions based on the test results. 2. Methods and Specifications Some measure of the reliability must be established in order to correlate the predicted lifetime of a product, the product performance in accelerated testing, and the performance of a product in the actual field environment. This is established through the use of standard tests and specifications.
TABLE 2
The Operating Environment and Service Life of Various Product Categories
Product Auto, under the hood Industrial auto Military avionics Commercial avionics Military, ground/marine Space geo/LEO Telecommunications Computer Consumer/portable
Temperature range (jC)
Service life (years)
65 to 150 55 to 95 55 to 95 55 to 95 55 to 95 40 to 85 40 to 85 +15 to 60 0 to 60
5.–10 10.or more 5.or more 10.or more 5.or more 5.–20 7.–20 5.or more 1.–3
774 TABLE 3
VISWANADHAM ET AL. Operating Stress Levels for Various Automotive Applications
Location Under the hood Above exhaust Intake manifold Firewall Frontal zone Chassis Inside body panel Near exhaust system Inside the automobile Dash board Rear window
Temperature (jC)
Humidity (% RH)
Shock (G)
Vibration
650 125 140 85
80 95 80 85
50 100 1 1
2 kHz 600 Hz 800 Hz
40 to 85 40 to 125
98 98
2 2
2 kHz 2 kHz
40 to 125 40 to 104
98 98
1 1
20 Hz 20 Hz
40 40 40 40
to to to to
Test specifications establish a foundation that allows comparison of different products under the same test conditions to establish some degree of product interchangeability, an expected level of quality, a minimal level of safety, and predicted reliability at an affordable cost. These tests are often used as a benchmark for evaluating new suppliers or modifications in design and materials. Comparisons can also be used to evaluate potential modifications for performance improvements, or for increased product lifetime. Encouraging suppliers across the industry to evaluate their products to a given specification provides the ability to do initial evaluations of materials or product options without incurring the costs of having to test every option independently. Many electronic industry groups have emerged to attempt to provide common ground for these baseline comparisons of materials and products. Table 4 lists many, but not all, of the groups that work together to establish the common infrastructure, test methods, and specifications for evaluating reliability in the electronics industry. Many of the standards are currently being modified to incorporate the requirements for Pb-free solder assembly processing. The standard IPC-SM-785, ‘‘Guidelines for Accelerated Surface Mount Attachment Reliability Testing,’’ is an important standard that provides guidelines for the evaluation and comparison of Pb-free and Sn–Pb solder joint reliability. It also provides a basic understanding of accelerated test issues and enables extrapolation of test results to predict assembly reliability in application-specific use environments. The purpose of accelerated testing is to induce failures similar to those that would occur in the product lifetime, in the shortest period in simulated environments. The use of test standards can reduce the number of tests, and hence the time needed to gain confidence that manufacturing processes and assembly designs will meet the reliability requirements for a specific application. However, analytical prediction is not a guarantee that an assembly or design will meet all the requirements, but it is a statistical technique based on minimal test data that gives a reasonable approximation of the assembly lifetime. Other specifications that are useful in evaluating Pb-free solders are given in Table 5. These standards are updated from time to time and will be modified to include the requirements for Pbfree processing. 3. Major Failure Mechanisms a. Creep. When subjected to a constant load or stress, many materials undergo timedependent plastic deformation called creep. It is a nonrecoverable deformation and proceeds at relatively low strain rates (106 sec1) at temperatures that promote significant diffusion rates. The phenomenon of creep is important for materials and assemblies whose normal operational temperatures are relatively close to their melting points, as is the case with solder alloys and polymeric materials used in electronics. In these applications, solder alloys, for example, undergo creep deformation because thermal activation can keep the materials’ diffusion-controlled
RELIABILITY ASPECTS OF LEAD-FREE SOLDERS TABLE 4
Organizations Establishing Standards for the Reliability of Electronic Assemblies Organization
IPC EIA CEA TIA GEIA JEDEC
ANSI ASTM IEEE SMTA SMEMA IMAPS ISO NIST NEMA NEMI
Information source
Institute for Interconnecting and Packaging Electronic Circuits Electronic Industries Alliance Consumer Electronics Association Telecommunications Industry Association Governmental Electronics and Information Technology Association Solid State Technology Association Previously the Joint Electron Device Engineering Council Semiconductor Engineering Standardization Body of EIA American National Standards Institute American Society for Testing and Materials Institute of Electrical and Electronics Engineers Surface Mount Technology Association Surface Mount Equipment Manufacturers Association International Microelectronics and Packaging Society International Standards Organization National Institute of Standards and Technology National Electrical Manufacturers Associations National Electronics Manufacturing Initiative
JEITA
Formally Electronic Industries Association Japan (EIAJ)
UL
Underwriters Laboratories Inc.
TABLE 5
775
http://www.ipc.org/ http://www.eia.org Each of the listed organizations is a separate organization under the EIA umbrella http://www.jedec.org
http://www.ansi.org/ http://www.astm.org/ http://www.ieee.org/ http://www.smta.org/ http://www.ipc.org/html/ smemastandards.htm http://www.imaps.org/ http://www.iso.org http://www.nist.gov/ http://www.nema.org/ http://www.nemi.org/standards/ comp_sub.html http://www.jeita.org/ Link to standards: http://tsc.jeita. or.jp/GIS-01.htm http://www.ul.org/
Important Industry Standards for Lead-Free Implementation
Industry standard IPC-D-279 IPC-TM-650 J-STD-01 J-STD-02B and -03A J-STD-04 and -06 J-STD-20
Description Design Guidelines for Reliable Surface Mount Technology Printed Board Assemblies Test Methods Manual Electronic Assembly Workmanship Solderability Tests for Component and PWB Solder Paste and Flux Component Moisture Sensitivity Classification
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deformation mechanisms operative above the homologous temperatures (>0.5Tm). The homologous temperature is the ratio of the test temperature to the melting temperature of the material, expressed in Kelvin. It is generally recognized that creep is of engineering importance at homologous temperatures greater than 0.5 because the higher creep rates can result in structural degradation. Creep behavior is described in three stages, as depicted in Fig. 3. During the primary transient stage, creep resistance increases with time by virtue of its own deformation, representing a low-stress and low-temperature condition. Secondary creep occurs above the homologous temperature that correlates with the self-diffusion process [2]. The creep rate attains a steady state due to the equalization of competing strain hardening and recovery processes. Dislocation glide or climb generally is the rate-controlling step during the secondary stage. These processes continue until active changes in the internal structure, particularly void formation, result in rupture, which is characteristic of the final stage referred to as tertiary creep. Creep behavior depends on lattice defects and dislocation structure, and its movement results in plastic deformation, the magnitude of which depends on temperature and stress. Plastic deformation rates from creep curves are related to the stresses based on Dorn’s equation: cp ¼ cp0 sn expðDH=T Þ
ð10Þ
where s is the stress exponent, cp is the kinetic factor, n is a constant, k is the Boltzmann constant, T is the absolute temperature, and DH is the activation enthalpy. The kinetic factor is related to material properties such as shear modulus, diffusion coefficients, lattice constants, etc. [3]. b. Solder Fatigue. Fatigue is the phenomenon of fracture resulting from the application of repetitive stress cycles—a progressive failure as a consequence of cyclical stresses below the material’s ultimate strength. The stress can be of mechanical, thermal, or electrical origin. Fig. 4 shows the most commonly observed failure modes in solder joints that have been tested under thermal cycling conditions. Generally, cracks nucleate at the corner areas of solder joints where stresses are highest and propagate through solder joints often close to intermetallic compound (IMC) layer(s) either on the component or on the board side. The strains are due to global and local mismatches in the coefficient of thermal expansion of the assembly interconnection structure. The low-cycle fatigue can be defined as failure in less than 10,000 cycles. It is the dominant failure mechanism in the case of solder joints because thermal stresses give rise to extensive plastic deformation of solder alloys during each cycle. The thermally induced displacements result in a complex stress and strain distribution in the solder joint and, as mentioned above, the highest shear stresses are located in the proximity of the IMC layers. Thus, fatigue failures depend on the microstructure and solder joint defects generated during soldering operations, the surface metallizations used on component leads and board pads, as well as the nature and thickness of
FIG. 3 The three stages of plastic deformation associated with creep behavior.
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FIG. 4 Cross section depicting the thermal fatigue failure of a Pb-free CSP solder joint that failed in the ATC testing.
intermetallic compounds formed at the interfaces. It is important to note that the microstructure, including intermetallic compound layers, is also affected by the loading of the assemblies in the application environment. Most solder fatigue models correlate the number of thermal cycles to failure with the parameters that quantify the failure mechanism. Because solder fatigue is one of the prominent mechanisms found in product field failures, significant efforts have been made to develop models that characterize creep-induced fatigue. In general, the number of cycles (Nf) to failure of a solder joint in low-cycle fatigue is described by the equation:
1 er b Nf ¼ ð11Þ 2 2ef where er, ef, and b are the plastic strain, fatigue ductility coefficient, and fatigue ductility exponent, respectively. Increased demand for solder joint reliability and the development of new fatigue-resistant solder alloys require a better understanding of the microstructural changes that occur during fatigue cycles. Because the solder materials are used at temperatures well above their homologous temperatures, plastic deformation is strain rate-dependent (as in creep) throughout the strain cycle. The modeling of the deformation behavior of solder joints located between rigid materials becomes especially complicated when the complex structures of intermetallic compounds and the microstructures of solder joints are included.
III. METALLURGICAL AND STRUCTURAL FACTORS It is well known that the microstructure of a solder alloy, like any material, has a very significant effect on its mechanical properties. The higher the application temperature in proportion to a material’s melting point, the more rapid is the microstructural change, and hence the impact on solder joint reliability. Successfully migrating onto and implementing lead-free solders requires better understanding of how these solder alloys interact with the termination and lead materials
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of microelectronic packages. Substrate finishes and their consequential effects on interconnections are also important. In this context, most lead-free compositions are expected to provide some strength advantage, and hence better fatigue resistance properties, over the eutectic tin–lead solder. The Pb-free solders Sn–3.0Ag, Sn–5.0Ag, Sn–0.75Cu, and Sn–4.0Ag have been shown to have better fatigue resistance over tin–lead alloy. The alloys Sn–36In, Sn–58Bi, Sn–50In, Sn– 0.75Cu, and Sn–4.0Ag all appear to have superior fatigue resistance [4].
A. Characteristics As mentioned, most soft solders currently used in electronic assemblies have their homologous temperatures below room temperature. The properties and behavior of the solders cause them to undergo significant changes in plastic deformation when due to temperature-induced stresses or mechanical stresses. Phenomena such as intermetallic compound growth at interfaces, dynamic recrystallization, and grain growth, as well as the creep of solder alloys occur during low-cycle fatigue in a shear mode during thermal cycling or under mechanical loading. Fatigue or creep rupture can occur either in a competitive, alternative, or synergistic manner. Deformation of crystalline metals, under loading, can take place via dislocation glide, climb, grain boundary sliding, grain vacancy movement, or volume diffusion. Fatigue failures in metals generally occur due to localized inhomogeneous plastic deformation. In a high-stress area at low temperatures, plastic deformation kinetics obeys a power law, whereas in a low-stress region at high temperatures, grain boundary sliding could become the rate-limiting step [5]. As emphasized earlier, traditional Sn–Pb alloys undergo gradual microstructural changes during the soldering operation and during long-term use of electronic products. Fig. 5 [6] shows the formation of a continuous Pb-rich layer in a Cu/63Sn–37Pb joint. This layer exists between the bulk solder and the Cu6Sn5 regions after annealing at 170jC for 30 days. The thin, ductile, Pbrich or even pure soft Pb layer is formed when dissolved tin is consumed locally due to Cu6Sn5 formation. These changes alter the mechanical properties of a solder joint. High-tin, lead-free alloys such as eutectic Sn–Ag–Cu provide viable solutions to this problem because tin is not depleted next to the growing intermetallics. 1. Presence of Minor Elements Due to soldering requirements, there is only one element, tin (Sn), that has a suitable melting point (232jC) for use in an interconnection alloy. Hence, most of the lead-free solder alloys are based on tin, with additional elements (Fig. 6) that can be classified either as major or minor
FIG. 5 Optical micrograph of a solder joint region between the 63Sn–37Pb solder and the Cu pad after annealing at 170jC for 30 days. A black Pb-rich layer separates the solder and the Cu6Sn5. (n IEEE 1998, Ref. 6.)
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FIG. 6 The melting range between high-temperature and low-temperature lead-free alloys is about 100jC. (Courtesy of Helsinki University of Technology.)
elements. The elements Ag, Bi, Cu, In, and possibly Zn can be regarded as major elements, which influence the primary properties of solder alloys such as melting point and mechanical properties, whereas Sb, Ge, and possibly some transition metals may be regarded as minor alloying elements. Other elements shown in Fig. 7 are generally used as surface finishes on Cu conductors. Surface finish metallizations either partially or completely dissolve into liquid solders and thereby alter the composition of the solder joints, sometimes significantly, especially when the rate of dissolution is high and the solder volume is small. Metals introduced in small amounts into solder joints from PWB surface finishes or component terminations are considered minor elements. The contribution to the joint may be limited by thin surface finish layers [e.g., 3–5 Ain. of gold (Au) flash], or by the low solubility of the element in the solder (e.g., 120 Ain. of Ni barrier layer). It should be noted, however, that irrespective of their low nominal concentrations, these metals may have high chemical activity or may become enriched in regions close to solder/ conductor interfaces due to their limited diffusion, or, alternatively, in the absence of mixing effects during reflow soldering. The activity of finish metals may become large locally, and also in the case of low-volume solder joints characteristic of high-density area array configurations. 2. Lead as Minor Element In the near-term transition to total lead-free soldering, the electronics industry will be faced with using components with Sn–Pb terminations or finishes until the industry migrates to a Pb-free
FIG. 7 Part of the periodic table showing major and minor solder alloying elements to tin.
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technology. Not all component manufactures may supply packages with Pb-free lead finishes and termination metallurgies in time for Pb-free technology implementation. Thus, the interconnection may contain some amount of lead as a minor element. In addition, because some lead-free alloys melt at temperatures 25–44jC higher than eutectic Sn–Pb, there are concerns regarding the short-term and long-term integrity of components when exposed to higher temperatures characteristic of lead-free processes. With higher reflow temperature, the possibility of dissolving component lead metallizations and even underlying metals into liquid lead-free solders is to be anticipated. a. Effect on Several Lead-Free Binary Solders. In mixed technology applications where the component terminations or the PWB bonding pads have a Pb-containing finish, the use of lead-free solders can have some unexpected interactions. For example, eutectic tin–bismuth solder, which normally melts at 139jC, starts melting at 96jC if contaminated with lead. Similarly, the eutectic Sn–Ag alloy whose normal melting point is 221jC may melt locally at 178jC depending on the Ag and Pb content. This trend is followed by Sn–Cu and Sn–Sb alloys as well, with their melting points reduced from 227jC and 236jC to 181jC and 189jC, respectively. It should be recognized that the extent of melting point lowering depends on the Pb content, the melting point of the ternary eutectic, and the phase equilibria [7]. Tin–bismuth solders form a ternary eutectic with Pb, whose composition is 52Bi–32Pb–16Sn and melts at 96jC. A melting point lowering of 40jC can have a serious impact on reliability in the field, or during accelerated testing in the laboratory. Formation of a low-temperature ternary eutectic at ambient operating temperatures may result in catastrophic failures in the field. b. Effect on Sn–Ag–Cu Solder. It has been reported that low-cycle fatigue testing (ASTM E606) [8] of Sn–4.0Ag–0.5Cu bulk alloy indicates that a 0.5% Pb contamination reduced fatigue life from 13,400 cycles to 6320 cycles, and that a 1% Pb contamination reduced fatigue life to 3252 cycles. Failures due to Pb contamination in Pb-free solder joints were attributed to intergranular separation. A low-melting Sn–Pb–Ag ternary alloy with a melting point of 179jC forms and separates lead-free alloy grains. Thus, the intergranular phase that exhibits pure adhesion was considered the reason for the failures. It was also suggested that the severity of the problem can be minimized by optimizing the reflow profile [9]. Oliver et al. [10] reported the effect of Pb contamination on the fatigue properties of Sn– 3.5Ag–0.7Cu solders under thermal cycling at 15jC to 125jC. They reported a critical problem with 2–6% Pb in the interconnection. At these lower concentrations, the Pb phases are located in the last solidified interdendritic areas of the interconnection. Because the Pb phases are large, less coarsening is necessary for the next stage of degradation to take place. Microcracks passing through Pb phases in the Sn grain boundaries were observed at 500 thermal cycles. On the other hand, at higher lead concentrations, such as 20% Pb, it appears to form a fine, evenly dispersed eutectic between the Sn dendrites. Considerable eutectic coarsening must take place in order for recrystallization and cracking to occur in 20% Pb solders. In practice, Ag–Sn–Cu solders containing 20% Pb can have a better thermal cycling reliability than one containing a lower percentage of Pb. Thus, whereas Pb contamination degrades the reliability of Pb-free Sn–Cu– Ag solders, the effect is more pronounced at lower Pb concentrations. 3. Effect of Other Minor Elements In addition, minor elements such as gold, nickel, palladium, cobalt, tungsten, etc. can be introduced into the solder joints. As a result, solder interconnections will likely be complex multicomponent systems with as many as six or seven elements. The effect of these minor elements on the physical and metallurgical properties of an alloy is still largely unknown. There have been some preliminary studies reported in the literature. Chap. 8 describes their effect when utilized, for example, with the Sn–Ag–Cu system.
B. Intermetallic Compounds In a solder interconnection, the presence of an intermetallic compound layer is testimony that a metallurgical bond has formed. Figs. 8 and 9 show a typical Sn–3.5Ag solder joint on a Cu
RELIABILITY ASPECTS OF LEAD-FREE SOLDERS
781
FIG. 8 Sn–Ag–Cu solder at the Cu/OSP interface after assembly. Ag3Sn forms in the grain boundaries. Hexagonal Cu6Sn5 is seen in the bulk solder. (Courtesy of Nokia Corp.)
substrate and a Ni/Au component termination, respectively, with Cu6Sn5, Ag3Sn, and Ni3Sn intermetallic formations identified. However, the structure and thickness of the IMC layer play a prominent role in the reliability of the interconnection under a variety of mechanical and thermal loading conditions [11]. In a study of hybrid microcircuits, excessive intermetallic compound formation was the result of undue or excessive consumption of thick film metallizations in the solid state, or leaching when the solder is in the molten state, resulting in dewetting. Three alloys, namely, Sn–3.5Ag, Sn–3.33Ag–4.83Bi, and Sn–3.15Ag–5.0Bi–5.0Au, with melting points of 221jC, 212jC, and 195jC, respectively, were investigated. The 76Au–21Pt–3Pd thick film
FIG. 9 Sn–Ag–Cu solder at a solder pad interface after assembly. Ni3Sn4 intermetallic compound forms the Ni/Au component interface. (Courtesy of Nokia Corp.)
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VISWANADHAM ET AL.
metallization was fired at 825jC for 10 min. After the assembly, the solder microstructure changed significantly with aging at 100jC for 2000 hr, notably coarsening Au–Sn intermetallic compounds. Understanding the evolution of structural changes under mechanical or environmental loading conditions is crucial to elucidating the interconnection behavior, as well as to developing a methodology for predicting service reliability. The thickness of the intermetallic layer levels off at higher temperatures (f170jC) once the appropriate element is completely consumed. The above three lead-free alloys investigated all exhibited a higher shear strength compared to Sn–Pb as determined by the ring-and-plug technique. In a ring-and-plug test, a copper ring and a solid cylindrical copper plug specimen are machined from oxygen-free high-conductivity (OFHC) copper. The inner hole diameter of the ring and the diameter of the plug provide a predetermined solder gap dimension of approximately 0.2 mm. The ring and the plug are degreased, rinsed, and etched with 1:1 HCl:H2O for approximately 1 min. Subsequently, the inner surface of the ring and the outer surface of the plug are coated with a dilute rosin mildy activated (RMA) flux. The ring is then placed in a stainless steel fixture. Three copper wires of approximately 0.18 mm diameter are positioned at equal intervals about the ring’s hole to ensure a uniform nominal gap dimensions. The copper plug is located in the ring and a donut-shaped solder preform is slipped down the plug to rest on the top surface of the ring. The entire assembly is placed on a hot plate set between 350jC and 400jC. Once the preform melts, sufficient time is allowed to assure capillary flow of the solder into the gap. The test specimen is then chilled to ambient temperature. The portion of the plug protruding beyond the ring and the bottom surface of the ring are cut with a diamond saw and polished to be parallel. The mechanical strength test is conducted by placing the specimen into a stainless steel holder and by applying force to the plug through a punch attached to the machine crosshead under a constant displacement rate (10 mm/min). A schematic of a ring-and-plug specimen is shown in Fig. 10. The maximum shear stress is then calculated based on the centerline surface of the gap and maximum load applied before failure. Zribi et al. studied the kinetics of formation of intermetallic compounds in Sn–Pb and Sn– 3.8Ag–1.85Cu solder joints formed on electroless nickel/gold and organic solderability preservative (OSP) surfaces. It was reported that the growth rates of (Cu,Ni)6Sn5 and (Au,Ni)Sn4 (alternatively referred to as Au0.1Ni0.1Sn0.8) appear to be greater than Ni3Sn4. The intermetallic compound Cu6Sn5 grows faster than Ni3Sn4. (Cu,Ni)6Sn5 is stable at the reflow temperature and its formation is controlled by the diffusion of copper. Diffusion of Au controls the rate of formation of the metastable phase (Au,Ni)Sn4. These multilayered structures can play a significant role in joint reliability under mechanical loading conditions especially when the interfacial adhesion is poor [12]. The matter of interfacial intermetallic compound formation is discussed in detail in Chap. 13.
C. Effects of Thermal Aging Thermal aging and thermal cycling tend to reduce the mechanical strength of many Sn–Pb solders due to grain growth and coarsening phenomena. In addition, the regions adjacent to the intermetallic bond tend to be tin-depleted, and hence lead-rich in composition, rendering the interconnection weak. On the other hand, Sn-based lead-free solders do not exhibit the typical grain coarsening observed in Sn–Pb solder interconnections. Some Pb-free solder interconnection features associated with thermal aging are discussed in the following sections. 1. Gold Migration Nickel/gold component terminations and solder pad surface finishes are the source for Au in solder joints where Sn–Au intermetallics are formed. The formation of a brittle intermetallic compound (Au,Ni)Sn4 is a characteristic feature of these Pb-free alloys. The boundary between Ni3Sn4 and (Au,Ni)Sn4 is weak, and hence provides a low-energy path for crack propagation and the opportunity for the ductile-to-brittle fracture transition to occur. Subsequent aging indicates transgranular cracks at the (Au,Ni)Sn4 layer [13]. Increasing the solder volume or solder joint size
RELIABILITY ASPECTS OF LEAD-FREE SOLDERS
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FIG. 10 Schematic that depicts the ring-and-plug test.
does not significantly affect the growth of IMC thickness. Hence, IMC layer thickness provides the lower limit for solder joint design for ultrafine pitch and flip-chip applications [14]. The intermetallic compound thickness should be viewed with caution in assessing the reliability of fine-pitch, flip-chip interconnections [15]. Zhang et al. reported the reconfiguration of AuSn4 in the bulk solder to a more thermodynamically stable Cu–Sn–Au phase at interfacial intermetallic compound formations after aging at 150jC. The conversion of Cu6Sn5 to a Cu–Sn–Au phase was followed by the formation of a Cu–Sn–Au–Ni phase with continued aging and the addition of Ni from the underbump metallurgy (UBM). A faster rate of reaction was reported in Sn–Pb solders compared to Sn–Ag–Cu solders with either 0.7 or 1.2 wt.% Au content [16]. 2. Sinkholes Another phenomenon characteristic of some Pb-free solders is the formation of voids during thermal aging. These have been variously described as ‘‘shrinkage voids’’ or ‘‘sinkholes.’’ They are different in appearance from voids formed due to flux entrapment or Kirkendahl voids. Cross sections of solder joints containing these voids showed no fractured surfaces associated with the voids. The surfaces are populated with the smooth, rounded shapes typical of Sn dendrites. It is possible that these features were initiated as cracks and the fracture surface was modified over time. The phenomenon was reported in applications using various combinations of component and PWB surface finishes. This has also been observed under mechanical loading conditions [17]. The dark spots on the exterior surface of the solder joint in Fig. 11a are sinkholes formed during mechanical testing. Similar holes formed due to 40jC to 85jC thermal cycle stress testing. These types of voids were found in Sn–Ag–Cu solder joints after assembly, but they did not extend as deeply into the solder joints and the nodular surface was not well defined. They were present in
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VISWANADHAM ET AL.
FIG. 11 Surface voids or ‘‘sinkholes’’ were identified on Pb-free solder joints after (a) drop testing and (b) after thermal cycling. (Courtesy of Nokia Corp.)
solder joints of Sn–Ag and Sn–Ag–Cu lead-free solders after testing. These voids can progress to significant depths in the solder joints, sometimes as deep as 150 Am, as shown in Fig. 12.
D. Spalling Spalling describes the case where portions of Pb-free solder joints were found to be missing after thermal cycling. Test assemblies with 1.27-mm pitch components were cycled from 40jC to 125jC and cross-sectioned. An example of spalling, shown in Fig. 13, was identified after 6500 thermal cycles from 40jC to 125jC. Although a (Ag,Cu)3Sn plate is located near the fracture, the crack did not propagate along its surface. Spalling may be a problem for applications with long design life requirements. This phenomenon is more common in Sn–Ag–Cu solder joints as compared to Sn–Ag joints [18].
FIG. 12 Cross section shows deep ‘‘sinkholes’’ (arrows) in an SAC on an ENIG solder joint after thermal cycle testing. The solder surface is etched. (Courtesy of Nokia Corp.)
RELIABILITY ASPECTS OF LEAD-FREE SOLDERS
785
FIG. 13 Cross sections indicating spalling of portions of the SAC solder from a BGA solder joint. (a) Variations in color occur at large-angle grain boundaries in the solder joint. (Courtesy of Nokia Corp.)
E. Fracture Characteristics 1. Microcracking Microcracking occurs in small-angle grain boundaries of Pb-free solders, giving a ‘‘shattered’’ appearance, as shown in the thermally cycled, flip-chip joint shown in Fig. 14. The cracks appear at early cycles and are sufficiently small that die penetrant testing can be ineffective in identifying the full extent of cracking [19]. More importantly, only minimal electrical resistance increases are observed to occur. Although the resistance increase is very small, it may be enough to cause an
FIG. 14 Corp.)
Cracking in a SAC flip-chip solder joint after 1000 thermal cyclings. (Courtesy of Nokia
786
VISWANADHAM ET AL.
out-of-tolerance condition in a functional design. It is important to be cognizant of this phenomenon in assessing long-term product reliability. Application-specific testing should be performed to determine whether the changes in resistance would result in degraded performance or a value drift in the application. 2. Crack Propagation Crack propagation in Pb-free solders has been reported to proceed preferentially along largeangle grain boundaries in solder joints in both longitudinal and transverse directions. Predicting the reliability of area array components based on neutral point calculations may be more complicated due to the presence and orientation of these cracks. Current solder fatigue reliability models do not account for preferential crack propagation in large-angle grain boundaries of solder joints, which were identified as early as 2000 thermal cycles [18,19]. Fig. 15 shows electrically functional solder joints with cracks that were observed after 6500 thermal cycles from 40jC to 125jC. In some cases, crack propagation occurs preferentially along the surface of Ag3Sn intermetallic compound plates. It was also reported that cracks progressing along large-angle grain boundaries appear to have been redirected where Ag3Sn plates transcended the large-angle grain boundary [18,19].
F. Voids in Interconnections Due to the Assembly Process Voids in solder joints have been a concern, but to date, no definitive correlations seem to exist between the extent of voiding and long-term reliability. There are conflicting investigations that suggest that some amount of voiding enhances thermal cycle reliability [20]—with some suggesting that voids consisting up to 20–25% of the pad area are acceptable [21], and others suggesting that voiding in general degrades reliability [22]. In practice, the location of the void in the solder joint, the extent of voiding in individual solder joints, and the location of the voided interconnection on the package play an important role in solder joint reliability. It should be a priority to optimize the assembly process to minimize voiding. Voids often occur throughout solder joints but are of most concern when they are found near the IMC layer formed at the solder pad interface, have significant volume in relation to the solder joint volume, when they are located at high-stress locations, or when numerous small voids are present in a plane along the crack propagation path, as depicted in Fig. 16. In each case, voids can
FIG. 15 Longitudinal and transverse cracks in SAC/OSP solder balls. (a) A ball after etch. (b) Before flux removal. (Courtesy of Nokia Corp.)
RELIABILITY ASPECTS OF LEAD-FREE SOLDERS
787
FIG. 16 Voids in Pb-free solder joints with the potential to cause early failures in (a) first level interconnection solder joint after encapsulation. (b) BGA joint fails after thermal cycle testing. (Courtesy of Nokia Corp.)
reduce the time-to-failure under thermal and mechanical loading conditions. Voids aligned along the solder/pad interface either on the package or the board side reduce the effective bonding area, and hence reduce joint strength. Most studies to date address thermal cycle reliability. It is important to recognize that mechanical stresses play a significant role in the reliability of many portable consumer electronic products. More studies are now addressing the effect of voids under mechanical drop and vibration stresses [17]. It was once reported that solder joint integrity was degraded after 2500 thermal cycles with a palladium surface finish on small outline integrated circuit (SOIC) devices utilizing Sn–2.6Ag– 0.8Cu–0.5Sb solders. The reduced fatigue life was originally attributed to extensive voiding observed with a Pd surface finish [23]. This type of voiding was later attributed to the flux used and insufficient temperature exposure during reflow. The voiding was minimized after iterative adjustments to the reflow conditions that increased the peak reflow temperature and time at temperature [24]. Nonoptimized process times and temperatures, the nature of the flux composition and its physicochemical properties, and the pad surface metallurgy contribute to the formation of voids. Void movement within an interconnection depends on the viscosity of the molten solder, the formation of intermetallic compounds in the bulk solder, the void volume, and the associated solid/fluid interfacial energies involved. The increased temperature of Pb-free assembly processes can also influence the extent of voiding due to burnout, which is premature drying of the flux and/or decomposition of the flux. It is difficult to predict the final location of voids within a joint subsequent to assembly. An assembly process optimization should be undertaken, including evaluations of the PWB design to help minimize void formation and to enhance the evolution of voids from solder joints.
IV. RELIABILITY ASPECTS OF SOME LEAD-FREE SOLDERS Lead-free solders available on the market today can be classified into three general categories: binary, ternary, and complex multicomponent systems. These terms are descriptive of the number of elements initially used to create the alloys. Among the binary alloys of Sn–Bi, Sn–Sb, Sn–Zn, Sn–Cu, and Sn–Ag, the Sn–Ag alloys have shown the greatest potential for application in electronic assemblies. Ternary alloys of interest are Sn–Zn–Bi, Sn–Ag–Cu, Sn–Ag–Bi, Sn–Ag–In, Sn–Zn–In, etc., with Sn–Ag–Cu becoming the popular choice for many applications. The leadfree alloys of interest are discussed in detail in Chaps. 8 and 9. In pure form, the alloys are studied to determine the bulk properties and their potential for applications in the electronics industry.
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Determining the bulk properties of various alloys is a starting point, enabling comparison among Pb-free alloys and baseline Sn–Pb solders. In applications, the solder attachment process combines the alloy systems with minor elements from the component termination and from the PWB surface finish to form complex systems. The following sections describe the application of several key alloys and the reliability of the resulting complex systems they form.
A. Sn–Ag Alloy The eutectic Sn–3.5Ag solder alloy has been used for some time in certain electronic applications with significant testing reported in the literature [13,15,25–33]. A thorough thermal fatigue study was conducted on test boards populated with electronic modules, using a thermal cycle range of 40jC to 140jC [26,34]. The results indicate that the eutectic Sn–Ag alloy offers thermal fatigue reliability equivalent to, or even better than, eutectic Sn–Pb alloy. Fig. 17 [13] presents the stress rupture life data of solder joints made with three Pb-free eutectic alloys, compared with the eutectic Sn–Pb alloy. In the temperature range of 25–100jC, eutectic Sn–Ag is clearly superior to the other alloys, including eutectic Sn–Pb [13]. Motorola has carried out accelerated thermal cycling and vibration tests of Sn–Ag and Sn–Pb alloys [25]. It was concluded that the eutectic Sn– Ag alloy provided satisfactory performance and properties. The electrical conductivity, surface tension, thermal conductivity, and coefficient of thermal expansion of Sn–Ag solders were all noted to be comparable to Sn–Pb solders, as shown in Table 6. The most obvious limitation of Sn–3.5Ag solder is its melting temperature (221jC), which is nearly 40jC higher than eutectic Sn– Pb solders, and hence increases demands for heat resistance of components, especially those that are moisture-sensitive or temperature-sensitive. With Sn–Ag-based lead-free alloys, it is not necessary to use the same superheat (40jC) utilized for eutectic or near-eutectic Sn–Pb solder alloys. The viscosities and wettabilities of Sn–Ag-based lead-free solders can be improved by modifying the soldering process. The required superheat (i.e., the extent of heating above the melting point) can also be much less than the 40jC typical of Sn–Pb alloys. Peak reflow temperatures as low as 240jC, or a superheat of 19jC has been used successfully in surface mount assembly operations [35–37].
FIG. 17 The effect of applied stress on the stress rupture life of eutectic Sn–Ag, Sn–Bi, Sn–In, and Sn– Pb solders. Solid symbols are for 25jC. Open symbols are data at the indicated temperatures. (Courtesy of TMS, Ref. 13.)
RELIABILITY ASPECTS OF LEAD-FREE SOLDERS TABLE 6
789
Properties of the Eutectic Sn–Ag Solder Compared with the Eutectic Sn–Pb Solder
Alloy composition 63Sn–37Pb 96.5Sn–3.5Ag
Melting point (jC)
Density (kg/m3)
Coefficient of thermal expansion (ppm/jC)
183 221
8400 7290
21.4/25 22/20
Electrical conductivity (% IACS)
Electrical resistivity (AV cm)
Surface tension (N/m)
Thermal conductivity (W/mK)
11.5 14
14.99 12.31
0.49 0.48
57.9/32.6jC 55.3/23.9jC
In general, tin–silver alloys (e.g., Sn–3.5Ag) exhibit better solder wetting compared to tin– bismuth alloys (Sn–58Bi). Reliability testing Sn–Ag solder assemblies of engine control units in the 40jC to 125jC range for 200 cycles exhibited no degradation failures in spite of utilizing processing temperatures of 240jC [38].
B. Sn–Ag-Based Alloys 1. Sn–Ag–Cu Alloys Sn–Ag–Cu alloys wet and form good-quality solder joints with copper. It is a very promising solder system for replacing the conventional eutectic Sn–Pb solder in avionics and automotive applications where solder joints are subjected to harsh thermal cycle conditions and mechanical vibrations, and are expected to sustain operational temperatures up to 150jC [39–42]. The thermomechanical properties of these Sn–Ag alloys are reported to be better than conventional eutectic Sn–Pb solders, as shown in Table 6 and depicted in Fig. 18 [31]. Various studies conducted on Sn–Ag–Cu solder alloys are listed in Table 7 [31,39–52]. Near-ternary eutectic Sn–Ag–Cu alloys are leading candidates for Pb-free solders. These alloys have three solid phases: h-Sn, Ag3Sn, and Cu6Sn5. Starting from the fully liquid state in solidifying near-eutectic Sn–Ag–Cu alloys, the equilibrium eutectic transformation is kinetically inhibited. The Ag3Sn phase nucleates with minimal undercooling, but the h-Sn phase requires a typical undercooling of 15–30jC for nucleation. Because of this disparity in the required
FIG. 18 Thermomechanical properties of the Sn–3.5Ag–(0–2)Cu solder. (Courtesy of TMS, Ref. 31.)
790 TABLE 7
VISWANADHAM ET AL. Some Sn–Ag–Cu Solder Alloys Studies
Compositions (wt.%) Sn–4.7Ag–1.7Cu
Sn–4Cu–0.5Ag Sn–(3.5–4.7)Ag–(0.9–1.7)Cu Sn–4.7Ag–1.7Cu
Sn–Ag–Cu (composition unknown)
Sn–3.5Ag–0.7Cu
Sn–3.8Ag–0.7Cu
Sn–3.36Ag–0.68Cu 96.3Sn–3.2Ag–0.5Cu Sn–3.62Ag–1.52Cu 95.5Sn–4Ag–0.5Cu 95.5Sn–3.8Ag–0.7Cu 95Sn–4Ag–1Cu 93.6Sn–4.7Ag–1.7Cu Sn–3.5Ag–(0–2)Cu Sn–4Ag–0.5Cu Sn–3.5Ag–0.5Cu Sn–3.8Ag–0.7Cu
Investigations
References
Hardness vs. cooling rate, microstructural stability, wetting behavior (DTA, XRD, WDS) Liquidus T1=222jC; solidus Ts=216jC Microstructures (DTA, XRD, WDS, SEM) Compared with five other promising lead-free solders in microstructure, creep, fracture, and thermomechanical fatigue behavior Compared with eight other promising lead-free solders in wettability, fatigue resistance, and Tm; Sn–Ag–Cu was claimed as the best Reflowing on NiAu-coated FR-4 boards, shear stress in joint, microstructure of joint (SEM) Thermal cycling on NiAu-coated FR-4 PCB with 0402 ceramic chip capacitors; wetting balance tested Eutectic composition predicted thermodynamically Commercial alloy by alpha metals Steady-state creep parameters measured at 20jC, 70jC, and 120jC Wettability compared in air and in nitrogen atmosphere; special flux was needed; dissolution rate of Cu was tested and compared with Sn–Ag and Sn–Pb alloys Crack propagation, ductility, fatigue life, and isothermal fatigue life A literature review written by the National Physical Laboratory and ITRI, UK
40, 41, 43
44 39 42
45
46
47
48 49 50 51
31 52
DTA=differential thermal analysis; WDS=wavelength dispersive spectroscopy.
undercooling for nucleation, large, platelike Ag3Sn structures can grow rapidly within the liquid phase, before the final solidification of solder joints. At lower cooling rates, large Ag3Sn plates can subtend the entire cross section of solder joints and can significantly influence the mechanical deformation behavior of the solder joints under thermomechanical fatigue conditions. It has been demonstrated that Ag3Sn plate formation can be inhibited through rapid cooling [88], an important factor in assuring the reliability of solder joints comprised of these alloys. The main concern with Sn–Ag–Cu alloys is their high melting temperatures (100% liquid at 217jC or above). Moreover, the reliability of the solder joints is not extensively investigated as yet. Minor quaternary additions such as In, Bi, and Ge lower the melting temperature slightly [39,53] (covered in later sections). From a metallurgical point of view, the eutectic Sn–Ag–Cu
RELIABILITY ASPECTS OF LEAD-FREE SOLDERS
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solder alloy is a promising candidate in that the microstructure consists of a fine, equiaxed homogeneous grain structure. Spheroidal Ag3Sn intermetallics are found in small-angle grain boundaries throughout the bulk solder. However, larger deviations from the eutectic composition can bring large primary phases (mainly Ag3Sn and Cu6Sn5) into the microstructure, which can be cooling rate-dependant [54]. The phases can appear as large Ag3Sn plates and Cu6Sn5 rods throughout the bulk solder observed after 6500 cycles from 40jC to 125jC, as shown in Fig. 19 [18]. Sn–3.8Ag–0.7Cu solder was used to demonstrate the applicability of Pb-free solders in consumer products through the production of mobile phone handsets. The reliability of the solder was compared to 63Sn–37Pb solders utilizing thermal cycle testing from 25jC to 125jC through 1000 cycles. Failures were observed only on 0402 ceramic capacitors. In eutectic Sn–Pb solders, the cracks had formed starting at the surface of the solder, whereas in Sn–Ag–Cu, there was no cracking in the solder joints. Thermal strains in the Pb-free solder joints were accommodated by cracking in the components [47,55]. The Sn–Ag–Cu ternary alloy was reported to be a suitable substitute for Sn–Pb solders with a lower super heat than that required for eutectic Sn–Pb solder pastes. 2. Sn–Ag–Bi Alloys Alloying elements that could reduce the melting temperature of eutectic Sn–3.5Ag without degrading its overall characteristics are very desirable alloy additions. The Sn–Ag–Bi ternary system has been extensively investigated because the melting temperature of Sn–58Bi eutectic alloy is too low (139jC) for many applications. The focus has been on the composition range of alloys in the Sn-rich corner of the Sn–Ag–Bi phase diagram with small amounts of Bi. Experiments have indicated that Sn–3.5Ag–Bi alloys with less than 6% of Bi have the melting temperature range of 211–221jC. Alloys with more than 6% of Bi have a second peak in a differential scanning calorimetry (DSC) curve at 136.8jC, indicating that the liquid phase can be stable down to that temperature [50]. Although Bi reduces the melting point of Sn–3.5Ag alloy, some mechanical properties are also affected. The ultimate shear strength (smax) increases linearly
FIG. 19 Ag3Sn plates and Cu6Sn5 rods after an extended etch of a Sn–Ag–Cu solder ball. (Courtesy of Nokia Corp.)
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VISWANADHAM ET AL.
with Bi content up to f6.8 wt.% Bi and then decreases if more Bi is added, as shown in Fig. 20a [54]. This decrease might be caused by the brittle Sn–Bi eutectic clusters [5,56]. Another reason for reduced toughness with higher Bi contents (>6 wt.%) is the discontinuous precipitation structure of Bi at the grain boundaries [5]. The deleterious effects of high Bi content on the plasticity cmax were observed earlier at f4.66 wt.% Bi (Fig. 20b). The isothermal fatigue life of bulk Sn–3.5Ag–(2–10)Bi solder alloys is remarkably reduced with increasing Bi concentration due to a decrease in ductility caused by the coarse, platelike, and irregularly shaped Ag3Sn phase throughout the microstructure [31,32]. However, the reliability of Sn–Ag–Bi bulk solders can be equivalent to eutectic Sn–Pb if 2 wt.% Bi is taken as an upper limit. However, the reliability of Sn–Ag–Bi bulk solders can be maintained as equivalent to eutectic Sn– Pb if 3 wt.% Bi is taken as an upper limit. Nikander [57] reported stress–strain curves of Sn– 3.5Ag–1.5Bi and Sn–3.5Ag–6Bi showing the tensile strength of Sn–3.5Ag–6Bi to be much higher than Sn–3.5Ag–1.5Bi, which is similar to the results reported by Kariya and Otsuka [31,32]. 3. Sn–Ag–In Alloys The compositions of several Sn–Ag–In alloys were investigated, as noted in Table 8, along with their melting ranges [15,31,50,56,58,59]. Because indium is very expensive and scarcely available, it may only be considered for alloys with small additions to Sn–Ag solder alloys. The melting point of Sn–Ag alloys decreases with indium additions. Tensile strength increases but the ductility decreases with increasing indium content, as shown in Fig. 21. Microstructural observations suggest that indium atoms dissolve in the h-Sn solid solution of Ref. 32; thus, the increase in tensile strength accompanying indium additions is most likely the result of solution hardening. The loss of ductility of Sn–3.5Ag–In alloys is ascribed to the irregularly shaped second phase (Ag3Sn) (Fig. 22). The fatigue life of Sn–3.5Ag alloy decreases with increasing indium content (Fig. 1). Eutectic Sn–3.5Ag alloy exhibits a relatively high fatigue resistance, and indium additions of less than 2 wt.% were found to have no practical effect on fatigue life. In one study, Sn–Ag–In alloys were found to be superior to Sn–Pb eutectic even with 5 wt.% In [32]. Although Sn–Ag–In solders exhibit good mechanical properties at ambient temperatures, their application in consumer electronics is limited due to their low eutectic temperature, and the strong segregation of indium as reported by Korhonen and Kivilahti [60]. The system has a eutectic reaction L!Ag2In+g+h at about 113jC. A solder alloy whose composition is within the Ag2In–g–h three-phase triangle at 113jC starts to melt or solidify at this temperature, greatly limiting the upper service temperature of products that utilize these solder alloys. The potential problem of this solder system is that, even if a solder composition is well outside the Ag2In–g–h three-phase triangle, the alloy is not completely solidified above 113jC as confirmed by DSC measurements [60]. This is due to the fact that the diffusion of indium in the solid g-phase during
FIG. 20 Effects of bismuth (Bi) content on the (a) ultimate shear strength (smax) and (b) plasticity (cmax) of Sn–Ag–Bi solder joints with Ag=3.3(F0.1) wt.%. (Courtesy of ASME, Ref. 56.)
RELIABILITY ASPECTS OF LEAD-FREE SOLDERS TABLE 8
793
Melting Temperatures of Several Sn–Ag–In Alloys
Alloy composition
Melting temperature (jC)
Sn–(1–6)Ag–(4–35)Sn Sn–3.5Ag–5In Sn–3.5Ag–(1,3,5)In Sn–3.19–Ag–881In Sn–3.5Ag–(1.5)In
(167.9–179)–(212–214) f210 210–216 205–215 210–217
References 50 58 59 56 31
solidification is very slow, causing indium atoms to be segregated within that phase, leaving a greater amount of the liquid phase along the grain boundaries (i.e., it remains in the liquid state until 113jC and then undergoes solidification). Conversely, when the service temperature reaches 113jC, the liquid phase starts to form at the grain boundaries and renders an interconnection susceptible to hot cracking.
C. Sn–Zn–X Alloys Tin–zinc alloys are generally considered corrosion-prone owing to the oxidation potential of zinc. They have poor wettability and are not well suited for wave soldering due to high dross formation. 1. Sn–Zn–In Alloys The eutectic Sn–9Zn alloy melts at 199jC, but it can, together with near-eutectic alloys, be processed to maintain a stable fine-grained microstructure [36,61]. In contrast, alloys based on the eutectic Sn–Bi (139jC) and Sn–In (120jC) systems are not as stable microstructurally under the same conditions. A partial list of studies conducted on Sn–Zn–In alloys, whose findings are reported in the literature, is listed in Table 9 [15,50,58,62–66]. An addition of 5 wt.% In to Sn–9Zn decreases the melting point down to about 188jC, only 5jC higher than the eutectic Sn–Pb, while significantly improving the wetting characteristics of the eutectic Sn–Zn alloys [15,64]. When using an organically activated (OA) flux, the wetting behavior of this Sn–Zn–In alloy approaches eutectic Sn–Pb. However, OA fluxes require cleaning and are not always practical to use.
FIG. 21 Effect of In on the tensile strength and ductility of the Sn–3.5Ag–In solder at 25jC (e = 5 103). (Courtesy of TMS, Ref. 31.)
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VISWANADHAM ET AL.
FIG. 22 Effects of In content and plastic strain range on the fatigue life of the Sn–3.5Ag–In solder. (Courtesy of TMS, Ref. 31.)
Reflow soldering utilizing Sn–Zn–In alloy pastes on printed circuit boards has been studied using a no-clean, RMA-type flux in both air and N2 atmosphere [40]. After reflowing in air on Auplated Cu pads at 235jC, the solder balls were observed to be shiny and covered the pads well. After reflowing in N2 on pretinned Cu pads at 235jC, a device with pretinned leads was soldered to 1-in. square perimeter arrays of Sn–9Zn–5In solder pastes deposited on a few of these pads. The joints were observed to be well shaped. TABLE 9
Studies of Some Sn–Zn–In Solders
Compositions (wt.%) Sn–9Zn–(5–10)In
Sn–8Zn–5In–(0.1–0.5)Ag
Sn–8Zn–5In Sn–8Zn–5In–0.5Ag Sn8.8Zn–(0–10)In
Sn–9Zn–(2–5)In–(1–9)Bi Sn–6Zn–(2–5)In–(1–9)Bi
Investigations
References
Compressive creep and wetting properties compared with 40Pb–60Sn; oxidation and corrosion problems discussed V0.1 wt.% Ag dramatically improved mechanical properties of Sn–8Zn–5In; microstructures, tensile stress–strain properties, fracture surface in Ag-free and 0.1 wt%. Ag containing alloys were compared Effects of four fluxes on solderability, melting, and wetting behavior were investigated Tm=187jC; Cu was found to be beneficial for microstructural improvement Phase equilibrium calculation shows that a small amount (2 or 5 wt.%) of In is desirable in this alloy; Tm is about 19jC Low Bi content is preferred (1–4 wt.%); A phase transition occurs at around 183jC and may have practical merit; Tm decreases first and then increases with increasing Bi content; microstructures, and mechanical and wetting properties were studied; The 6 wt.% Zn alloy series had the highest reliability
62 63 64 65 58
15 50 66
66
RELIABILITY ASPECTS OF LEAD-FREE SOLDERS
795
a. Microstructure. It should be noted that indium additions result in the formation of a rather undesirable microstructure (i.e., a much coarser and less uniform microstructure containing a platelike phase distributed in a dendritic matrix structure). However, this structure can be modified by small (0.1 wt.%) additions of Ag, as depicted in Fig. 23. The ductility of a Ag-doped Sn–9Zn–5In alloy is significantly improved, as shown in Fig. 24. b. Issues. Some issues with In-containing solders that need to be addressed are listed in Table 10. 2. Sn–Zn–Bi Alloys Tin–zinc alloys have been doped with other elements such as bismuth and indium to improve their mechanical and thermal fatigue characteristics. Tensile deformation properties of bismuth-doped and indium-doped alloys, and estimates of thermal fatigue resistance have been reported. Strain rate sensitivity and microstructures of as-cast samples aged at 120jC for 12 days were studied using cast and machined alloys. Bismuth-doped alloys exhibit their maximum strength at relatively large strains compared to either indium-doped or eutectic Sn–Zn alloys. Bismuth additions have a greater impact on strain rate sensitivity, in comparison to indium additions. A 5% addition of bismuth to a Sn–Zn alloy was found to remarkably increase the tensile strength and to lower the elongation from 40% to 20%, whereas the addition of indium had little or no effect on elongation. Thermal aging has an imperceptible effect on both elongation and tensile strength. Tin–zinc alloy systems were estimated to have better thermal fatigue resistance than Sn– Pb alloys, but were not comparable to Sn–Ag systems. Alloys doped with bismuth or indium display considerable coarsening of the acicular zinc phase [67]. Sn–Zn solders and zinc-bearing alloys have stable surface oxides that are difficult to remove.Alloys containing indium have the disadvantage of high cost, which precludes them from most mass soldering applications. However, Sn–Zn–Bi alloys are good candidates as lead-free solders in mass soldering applications for temperature-sensitive components. These alloys are commercially available and typically have melting points in the range of 190–200jC. Sn–Zn alloys have been used as solders for many years, primarily for soldering aluminum assemblies. The alloy has also found use in diverse applications such as high-performance corrosion-resistant coating for steel and as sprayed coatings for capacitor plates. Their use as interconnection alloys in electronics, however, is a more recent development [68]. a. Solidification Aspects. Most Sn–Zn–Bi solders investigated for electronics are close to the Sn–Zn binary eutectic composition with minor additions of bismuth [44]. The alloy is a
FIG. 23 Fracture surfaces of (a) Sn–8Zn–5In and (b) Sn–8Zn–5In–0.1Ag solder alloys. The Ag-free alloy displays undesirable platelike fracture features, and the Ag-containing alloy displays the more desirable ductile dimples on the fracture surface. (Courtesy of TMS, Ref. 64.)
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VISWANADHAM ET AL.
FIG. 24 Tensile stress–strain curves for Sn–8Zn–5In and Sn–8Zn–5In–0.1Ag Pb-free solders. The curve for the binary Sn–Zn solder alloy is also shown for comparison. (n IEEE 1995, Ref. 58.)
homogeneous liquid at soldering temperatures, with tin-rich and zinc-rich solid solution phases formed upon solidification, often as alternating lamella. Bismuth has appreciable solubility in tin, particularly at elevated temperatures, and may solidify as part of the tin matrix at low concentrations. However, bismuth solubility decreases rapidly as the solidified joints cool down, resulting in the precipitation of discrete Bi-rich particles [69]. The addition of bismuth to tin–zinc seems to improve wetting and corrosion performance, but, unfortunately, it also causes the potential for a problem often referred to as ‘‘hot shortness’’ [70]. Under certain conditions, pockets of Bi-rich liquids that have lower freezing temperatures than the matrix can be formed during solidification (Bi–Sn eutectic=139jC and Sn–Zn eutectic=199jC). These molten pockets remain in the liquid state long after the matrix around them has solidified. The combined effects of stresses due to contraction on cooling and the residual pockets of molten solder can give rise to cracking, or ‘‘hot tears.’’ The defect has been observed on wave-soldered joints with this alloy, but not on surface mount assemblies [70], possibly because the joint volumes are smaller. Reducing the bismuth content reduces the incidence of hot tears. b. Reactivity of Zinc. In most Sn-based solders, it is the tin that is the active element and dominates the interfacial reactions between the solder and adjacent metallized terminal pads. As a result, tin-based solders share many common properties. For example, oxides, which form at the surface of molten Sn-based solders, are almost exclusively those of Sn because they are
TABLE 10
Issues with Indium-Containing Solders
Issues . . . . .
Their wetting behavior in air and inert atmosphere with different fluxes. Mechanism by which Ag beneficially affects their microstructures. Sn–8Zn–5In–0.1Ag alloy requires investigation of its mechanical properties, microstructural evolution, wettability, and melting temperature and is compared with the Sn–Pb eutectic solder. Sn–6Zn–(2–5)In–(1–9)Bi alloys require further investigation to verify the results of the thermodynamic calculations in Ref. 66. The applicability of the Sn–Zn–In alloys to industrial mass production.
RELIABILITY ASPECTS OF LEAD-FREE SOLDERS
797
thermodynamically more stable. However, because zinc is very active, the addition of zinc completely changes the picture. It has been observed that the outermost surface of molten 86Sn– 8.5Zn–5.5Bi solders is not dominated by tin oxide but by zinc oxide. Therefore, flux compatibility and drossing rate should be taken into account when using the Sn–Zn–Bi solder [69]. c. Reactions with Copper. It is generally known that Zn reduces the wettability of Cu by Sn-based solders. In addition to oxidation, zinc prevents tin from reacting with copper, which reduces the mechanical integrity of Zn-containing solder alloys with copper conductors [71,72]. During wetting balance tests of etched copper wires either in air or under a high-purity (H2O+O2<5 ppm) mixture of 20% H2+Ar, zinc in the liquid of a 55Sn–41.5Bi–3.5Zn (at.%) solder completely prevented the solder from wetting the copper wires (even when the ZnO was absent) by preventing Sn from reacting with Cu. Investigations revealed that the g-CuZn phase with approximately 65 at.% Zn was formed at the solder/Cu interface at 250jC. Fig. 25 shows the formation of a thick Cu–Zn binary intermediate phase (g-brass) layer at the 55Sn–41.5Bi–3.5Zn (at.%) solder/Cu joint interface bonded at 200jC. The composition of the layer was analyzed to be 33 at.% Cu and 67 at.% Zn, within the homogeneity range of the g-CuZn phase (i.e., 50–70 at.% Zn). It is clear that the formation of the g-CuZn phase layer interrupts the reaction between Sn and Cu and very effectively degrades the mechanical integrity of the Zn-containing Sn–Bi solder joint with Cu [67]. The formation of Cu–Zn intermetallic compounds in Zn-containing, Sn-based solder/Cu joints has also been reported by others as well [69,73]. Harrison and Vincent observed that the gNi5Zn21 intermetallic compound phase formed at the Sn–Zn–Bi solder/Ni interface, rather than Cu–Sn intermetallic compounds. Suganuma et al. [73] made eutectic Sn–9Zn solder/Cu joints in
FIG. 25 (a) Backscattered electron micrographs (b–d) and EPMA elemental maps (b–d) of a cross section of a 55Sn–41.5Bi–3.5Zn (at.%) solder/Cu interface that was bonded at 200jC for 1000 min. The g-CuZn phase (g-brass) layer is about 20 Am thick (1100). (From Ref. 72.)
798
VISWANADHAM ET AL.
FIG. 26 A partial phase diagram for the Sn–Cu–Zn system. (n IEEE 1995, Ref. 71.)
vacuum at 270jC and 290jC, respectively, using a time range of 5–35 min. Three Cu–Zn intermetallic layers were revealed by transmission electron microscopy (TEM). Two layers were identified by electron diffraction and energy-dispersive x-ray (EDX) analysis as g-CuZn (the thickest) and h-CuZn, respectively. The third layer was too thin to analyze. The thermodynamic analysis of this quaternary system has also been performed by combining the available data on the binary Sn–Bi, Sn–Zn, Cu–Bi, and Bi–Zn systems and experimental information obtained by the diffusion couple technique [71]. As a result of the assessment, the intersection of the Cu–Sn–Bi–Zn system was calculated by keeping the Sn-to-Bi ratio at the fixed value of 1.33 (i.e., corresponding to the eutectic composition of the Sn–Bi system, at 250jC, so that the plane of intersection is joined to the binary Cu–Zn line). With the Zn content used in the study (3.5 at.%), the liquid Sn–Bi–Zn alloy immediately becomes saturated with Cu (point A), causing the g-CuZn phase to form. It can be seen from Fig. 26 that the formation of the Cu6Sn5—instead of g-brass—necessitates that the Zn content is less than about 1 wt.% (point B). When the Zn content is greater than 11 wt.%, the first intermediate phase to form as the product of the solder/Cu reaction is qV-CuZn. According to the phase diagram, the addition of Zn into the Sn–Bi solder prevents the formation of Cu3Sn completely. The formation of the g-phase or the qV-phase—instead of Cu6Sn5—is expected to weaken the interfacial integrity of joints because neither Sn nor Bi takes part in interfacial reactions.
V. HIGHER-ORDER SYSTEMS AND THE INFLUENCE OF MINOR ELEMENT ADDITIONS A. Some Multicomponent Solder Paste Considerations Four-element and five-element alloys in pastes are generally excluded from further consideration due to the following reasons [29]: The variability in composition should be considered. Compositional consistency in powder for solder pastes is a challenge for binary and ternary alloys. The complexity involved in achieving a high level of consistency with four-element and five-element alloys is even greater.
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No five-element or six-element alloy with significant advantages in cost or performance over ternary or quaternary alternatives has yet been introduced to the industry. Generally, five-element or six-element alloy systems are not eutectic, and therefore the liquidus and solidus temperatures can differ significantly. This means that the liquid alloys of these solder systems will solidify over large temperature ranges where liquid is accompanied with one or more solid phases. This can give rise to similar problems as discussed earlier with Sn–Ag–In and Sn–Bi–Zn solder systems. Therefore, usually the binary and ternary eutectic or near-eutectic systems such as Sn–3.5Ag, Sn– 2Ag, Sn–0.7Cu, Sn–4Ag–0.5Cu, etc. are more useful. However, minor additions of some elements to many binary and ternary alloys result in higher-order systems with promising characteristics. Several of these higher-order alloy systems are discussed in the following sections. Furthermore, it is noted that although most solders are binary or ternary alloys, the solder joints produced with these solders are alloyed with PWB and component metal finishes, and therefore constitute multicomponent joints.
B. Sn–Ag–Cu–Sb System CastinR [96.2Sn–(2–2.5) Ag–0.8Cu–(0.5–0.6) Sb; Aim Solder Corporation, Cranston, Rhode Island, USA] is a commercially available lead-free alloy (Fig. 27). The onset temperature (peak in a DSC thermogram; i.e., the temperature at which an alloy has a phase transition) is around 219jC. The alloy has been demonstrated to possess relatively good wetting properties both in laboratory tests and on prototype circuit boards. The wetting contact angle (hc) has been reported to be 44F6j when reflowed at 260jC, which is much greater than the contact angle of 17F6j for eutectic Sn–37Pb alloys at 260jC, with the same RMA flux.
FIG. 27 Differential scanning calorimetry (DSC) thermogram of the CastinR solder alloy with an 8% eutectic Sn–Pb alloy addition utilizing a heating rate of 10jC/min. (n IEEE 1996, Ref. 74.)
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1. Effect of Lead Vianco et al. [74] examined the effect of Pb contamination on the performance of this lead-free solder by addition of 63Sn–37Pb alloys at levels of 0.5–8.0 wt.%. The onset melting temperatures decreased with an increasing Sn–Pb alloy content. A secondary low-temperature peak appeared at 183jC (Fig. 2) in DSC measurements, which is believed to represent a local low-melting-phase transition of the Sn–Pb system. The contact angle depends upon the amount of Sn–Pb alloy addition, as shown in Fig. 28 (also see Sec. III. A-2). 2. Comparison with Other Lead-Free Alloys Test results from several other studies show promising results for some other lead-free alloys. The reliability results comparing various lead-free alloys including Castin are listed in Table 11 [66,75] with the 63Sn–37Pb alloy serving as a baseline. Five lead-free alloys were investigated using an assembly line with normal printing parameters and the required change in the temperature profile to accommodate the higher melting temperatures of lead-free alloys. Test assemblies were thermally cycled from 10jC to 100jC for 510 cycles. The results show reduced fatigue life for the Bi-containing alloy B, and only a slightly reduced fatigue life for those containing In compared to eutectic Sn–Pb solders. The failure of the Castin assembly was not solder-related and the performance of Castin and Sn–Ag was considered equivalent to eutectic Sn–Pb solders. Additional investigations are necessary to determine how surface finishes on boards and component leads affect fatigue life. Some works were carried out, but the solders investigated contained Pb [71]. Because the melting temperatures of most viable Sn–Ag–Cu–Bi alloys are about 20jC higher than eutectic Sn–Pb, they cannot be described as ideal drop-in replacements [44].
C. Sn–Ag–Cu–In–Bi–Sb System Thermodynamic calculations have been performed to design a Sn–Ag-based multicomponent alloy with a low liquidus temperature, narrow melting temperature range, high driving force for the formation of interfacial reaction products with Cu conductors, small surface tension values, and slow coarsening kinetics that does not undergo phase transformations at service temperatures [76]. Bismuth and indium were introduced to decrease the liquidus temperature, and Sb was utilized to slow down the solid-state coarsening kinetics because the diffusivity of Sb in Sn is very low [77]. Although several intermetallic compounds may form at the substrate/solder
FIG. 28 The effect of Sn–Pb contamination on the contact angle of CastinR and Sn–Ag–Bi solders. (n IEEE 1996, Ref. 74.)
RELIABILITY ASPECTS OF LEAD-FREE SOLDERS TABLE 11
801
Cumulative Number of Failures During Accelerated Thermal Cycle Testing Number of cycles
Solder paste alloy (A) Sn–3.5Ag (B) 90Sn–7.5Bi–2Ag–0.5Cu (C) CastinR (D) 80Sn–18In–2.0Ag (E) 77.2Sn–20In–2.8Ag (F) 63Sn–37Pb
4
10
110
Cumulative number 0 0 4 9 1 1 1 1 1 1 0 0
210
of failures 0 0 9 9 1 1 1 1 1 1 0 0
310
410
510
0 11 1 1 2 0
0 11 1 1 2 0
0 11 1 1 2 0
Longest fatigue life = 0; shortest fatigue life=15. Source: Ref. 75.
interface, only those that form first during the soldering process affect the wettability of solder. The intermetallic phase with the highest driving force of formation was calculated to be Cu6Sn5. Besides the effects on the wettability behavior, the thermodynamic calculation indicates that Bi contributes to the improvement of wettability by increasing the driving force to form Cu6Sn5 and by decreasing the surface tension, whereas indium serves to improve wettability by increasing the driving force to form Cu6Sn5. The silver content of the alloy is also a consideration as it affects the cost. An optimum composition of the solder alloy was suggested to be Sn–2.76Ag–0.65Cu– 3.75In–5Bi–3Sb, based on the anticipation of having a high driving force for the formation of Cu6Sn5 and a melting temperature range of 190–208jC. No reliability data have been reported.
D. Sn–Ag–Bi–Cu–Ge System This is a lead-free solder alloy system claimed to be usable with conventional tools and equipment utilized for the eutectic Sn–Pb solder without changing the operational parameters. Table 12 [53] lists the melting temperature ranges of several alloy compositions of this alloy system measured by DSC. A small amount of Ge was claimed to drastically improve the solderability and reliability of Sn–Ag–Bi–Cu alloys, but the mechanism remained largely unexplored. A 0.1 wt.% Ge addition was observed to reduce the dross formation significantly in reflow soldering equipment compared to conventional Pb-containing solders and other Pb-free solders. Because Ge appears to be very effective in suppressing dross formation at the surface of alloys, this effect is thought to be the cause for enhanced wettability of alloys containing small Ge additions. No explanation for suppressed dross formation was given even though Ge is a strongly oxidizing element included in liquid solders.
TABLE 12 Melting Points of Sn–Ag–Bi–Ge Solders in Comparison with Conventional Sn–Pb Eutectic Solders. Composition (wt.%) Sn–2.0Ag–4.0Bi–0.5Cu–0.1Ge Sn–2.0Ag–4.0Bi–0.5Cu Sn–2.0Ag–7.5Bi–0.5Cu–0.1Ge Sn–2.0Ag–7.5Bi–0.5Cu Sn–37Pb Source: Ref. 53.
Solidus (jC)
Liquidus (jC)
198 198 187 187 183
217 217 213 213 183
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The effects of small Ge additions on physical and mechanical properties were also studied. It was concluded that small additions of Ge contribute to enhance both surface and interface characteristics to improve bonding and bulk materials properties. It was reported that Gecontaining solders have similar or better performance and higher reliability than eutectic Sn–Pb solders. Although these results are very promising, this solder family must be appropriately tested and exercised under actual assembly conditions in manufacturing. The interfacial microstructures and joint reliability require further investigation.
VI. EFFECT OF ASSEMBLY RELATED ASPECTS ON RELIABILITY Although fundamental reliability aspects depend on such factors as the type and stability of microstructures of the interconnection systems, the ultimate product reliability depends on several additional factors imposed by various constituent parts of an assembly. These include the chip carrier and its surface finish, component structure, lead materials and finishes, and their combined effects on the bulk solder interconnection. For example, electroless nickel/immersion gold (ENIG) is a popular board finish due to its long shelf life and excellent wetting characteristics with eutectic Sn–Pb solders. However, several solderability and reliability concerns that are primarily due to complex interfacial reaction products that occasionally cause unexpected failures of eutectic Sn–Pb and Pb-free solder joints have surfaced. The major aspects are discussed in the following sections.
A. Effects of High-Temperature Reflow Profiles In addition to the metallurgical aspects discussed above, process parameters can have important effects on reliability as well. Good-quality paste printing, peak reflow temperature, dwell time above the liquidus temperature, cooling rate, and solder atmosphere reactions all affect the microstructure of solder joints and ultimately their reliability. Higher processing temperatures increase the dissolution rates of metal finishes and/or conductor metals (i.e., minor elements) into the solder and can increase the rate of intermetallic compound formation in the bulk solder. This increases the joint stiffness (i.e., reduces the compliance). 1. Assembly Effects The higher Pb-free processing temperatures can affect the assembly yields of particular components due to thermal mass and the size or pitch of a component. The reflow profiles are most often developed to optimize the solder joint formation of the largest components in the assembly without considering the effects on the smaller components. Very small paste deposits appropriate for small passive components such as 0201 or fine-pitch components can dry out before reaching the reflow temperature due to the rapid heat-up rates in Pb-free processing. Noncoalesced solders and tombstoning can be a problem especially when placed on an assembly with larger components having a much higher thermal mass. Thermal management design practices that enhance the removal of heat through attachment of components to ground planes can detrimentally affect solder joint formation by delaying the reflow of the paste and by minimizing the time above the reflow temperature. Poor solder wetting and high void content can result. The PWB design and component mix must be carefully considered to provide an adequate process window when selecting a reflow profile. Numerous studies have demonstrated that modest superheat is sufficient to form acceptable solder joints at temperatures that assure the functional integrity of the great majority of printed circuit boards and components utilized [44,70,75,78,79]. There may be some components, such as tantalum capacitors, that are particularly sensitive to temperatures above 210jC. In these cases, techniques such as selective soldering may be appropriate instead of mass reflow techniques. 2. Alternative Solutions To use temperature-sensitive components with Sn–Ag, Sn–Cu, Sn–Ag–Cu, and other lead-free solders with higher melting points, heating techniques that selectively heat the solder joints and
RELIABILITY ASPECTS OF LEAD-FREE SOLDERS
803
not necessarily the entire component, such as laser or hot bar soldering, can be utilized. In selective soldering processes, a finite number of interconnections are heated locally as opposed to heating the entire assembly for mass reflow. Laser soldering focuses a beam onto the interconnection area, providing bursts of energy sufficient to form the solder joint. Hot bar soldering uses appropriately configured metal bars to heat only the leads, solder, and solder pad interconnection area to achieve the interconnections. These techniques are practiced in the industry but have cost implications due to equipment programming requirements, specialized equipment costs, and slower processing times associated with sequential soldering steps. An alternative solution is to use lower-melting-point lead-free alloys such as 43Sn–57Bi (139jC) or one with indium additions. The 43Sn–57Bi alloy has been successfully used in the past but has relatively poor mechanical properties, particularly at elevated temperatures.
B. Moisture Sensitivity The moisture sensitivity of plastic packages and plastic-encapsulated microcircuits is of great importance to achieving acceptable process yield rates and long-term reliability requirements of Pb-free assemblies. Pb-free reflow profiles are similar in length to profiles used for eutectic solders while driving the maximum PWB and component temperatures 20–40jC higher than eutectic Sn– Pb processing. The standard IPC moisture sensitivity level (MSL) of components can be reduced by as much as two levels due to higher temperatures and rapid heating rates [80]. In other words, components that show a propensity for moisture damage in eutectic Sn–Pb reflow operations have a much higher likelihood of undergoing degradation referred to as popcorning in Pb-free processing. MSL testing should be completed to qualify components for Pb-free processing, and moisture exposure of sensitive components should be tracked closely to minimize the potential for assembly and latent defects due to popcorning (J-Std 020).
C. Printed Wiring Board Surface Finishes Solder spread or ability to wet determines the shape of a fillet in a solder joint. Sattiraju et al. investigated the solderability of immersion tin, ENIG, electroless palladium, and OSP surface finishes with Sn–3.4Ag–4.8Bi, Sn–4.0Ag–0.5Cu, Sn–3.5Ag, and Sn–0.7Cu lead-free interconnection alloys both in air and nitrogen using sequential electrochemical reduction analysis (SERA) and wetting balance techniques. It has been reported that Ni/Au finish performed the best and OSP performed the worst in both nitrogen atmosphere and air environment, suggesting a preference for Ni/Au finish. The Sn–0.7Cu alloy was considered superior, whereas Sn–4.0Ag– 0.5Cu exhibited the worst wettability in air. In nitrogen, Sn–3.4Ag–4.8Bi wet the best, whereas Sn–4.0Ag–0.5Cu and Sn–0.7Cu were reported to be poor. Multiple reflows deteriorated the tin finish more than the other finishes. It was also noted that intermetallic compound layers do not increase significantly in growth from three to five reflow cycles [81]. For example, a 0.76-Am Cu6Sn5 layer grew to 0.91 Am after three reflows and grew to 0.93 Am after five reflows. There was no significant growth of Cu3Sn due to multiple reflows (three to five reflows). 1. Electroless Ni(P) vs. Electrolytic Nickel Kang et al. evaluated Au/Ni(P), Au/Pd/Ni(P), electroplated Ni/Au, and electroplated Cu surfaces with Sn–3.5Ag, Sn–3.8Ag–0.7Cu, and Sn–3.5Ag–3Bi alloys. The surface metallurgies were formed on quartz plates with 30-nm Cr as an adhesion layer. Solder pastes were screened on the various surface metallurgies, reflowed at 250jC at 2, 6, and 20 min, and cooled at 10–20jC sec1. On an electroless Ni(P)/Au surface using Sn–3.5Ag and Sn–3.5Ag–3.0Bi solders, much of the Ni–Sn intermetallics formed were separated from the interface and the morphology was observed to be blocky with only a thin layer of Ni3Sn4 attached to the interface. With Sn–3.8Ag– 0.7Cu, the intermetallics were well attached to the surface with a needlelike morphology that became increasingly planar with time. With a Sn–3.5Ag–3Bi/Au–Ni(P) system, the intermetallic compounds were observed to separate from the interface and no Bi-containing intermetallics were formed [82].
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The results from the electrolytic Ni/Au surface were in contrast to the case of the electroless Ni(P) surface. The intermetallic compounds formed in all three Pb-free solders were thinner and more uniform, well adhered to the surface, and not separated or spalling away. The Ni3Sn4 intermetallic growth rate on electroplated nickel is about two to three times smaller than on electroless NiP. The IMCs grown in Sn–Ag–Cu solders were thicker than the other two solders and appeared to consist of two distinct layers. The top of the IMC layer had a higher copper content and the bottom layer had a higher Ni content. In the case of the Sn–Ag–Cu system, the intermetallic compound that was initially observed to form in the top layer was Cu6Sn5. At the bottom layer, nickel substitutes for copper in the Ni3Sn4 intermetallic compound, forming (Ni,Cu)3Sn4 [82]. 2. Electroless Ni(P)/Immersion Au Zeng et al. [83] also studied the intermetallic compound reactions between Pb-free Sn–Ag–Cu solders and Ni(P)/Au surface finish (ENIG) on printed wiring boards. As the gold dissolves rapidly into the eutectic Sn–Ag–Cu solder, (Cu,Ni)6Sn5 is formed on the Ni/P layer due to copper enrichment from the solder. The formation of (Cu,Ni)6Sn5 at the Ni(P) interface is thermodynamically feasible. Additional Ni atoms diffuse into (CuNi)6Sn5, stabilizing the layer during thermal aging. The fracture is generally located at the interface between (Cu,Ni)6Sn5/Ni3Sn4 and Ni(P)layer. Because the phase relations between Cu6Sn5 and Ni3Sn4 are of great practical interest in many solder/metal finish systems, a very time-consuming thermodynamic and experimental study was conducted on the Cu–Ni–Sn system [84]. Based on preliminary experimental results, the partial metastable phase diagram of the system at 235jC was calculated, as shown in Fig. 29 [85]. It indicates that (Ni,Cu)3Sn4 can be in metastable equilibrium with the (Cu,Ni)6Sn5 phase of different Cu-to-Ni ratios. During long aging (>1000 hr) at 235jC, the metastable (Cu,Ni)6Sn5 phase decomposes into the ternary compound Sn45Cu29Ni26 and the stable IMC (Cu,Ni)6Sn5 [84]. However, in most practical applications, the Ni content of the metastable (Cu,Ni)6Sn5 is far above its equilibrium value, and there are indications that this compound becomes more brittle with an increasing nickel content [86]. Furthermore, a detailed microstructural characterization utilizing TEM was conducted on the relatively complex interfacial reaction layers generated between an ENIG finish and a eutectic Sn–Ag–Cu solder [86]. As shown in Fig. 30, the columnar two-phase (Ni3P+Sn) layer structure is formed between the amorphous Ni(P) and Ni63Sn25P12—the latter being in local metastable equilibrium with the (Cu,Ni)6Sn5 intermetallic layer. There are numerous voids in the vicinity of the ternary Ni63Sn25P12 phase. This ‘‘porous’’ Ni63Sn25P12 phase region is thought to make solder joints susceptible to brittle fracture known as ‘‘black pad.’’
FIG. 29 Metastable equilibria of the Sn–Cu–Ni system at 235jC. (From Ref. 84.)
RELIABILITY ASPECTS OF LEAD-FREE SOLDERS
805
FIG. 30 TEM micrograph showing the reaction layers formed during reflow soldering of an ENIG finished board with a eutectic Sn–3.4Ag–0.8Cu solder at 240jC.
D. Component Termination Finish 1. Lead Finish/Mold Compound Adhesion Component lead finish is another important aspect that must be considered to achieve total leadfree implementation. The matter of component and PWB finish is discussed in detail in Chap. 12. Both Ni/Pd and Ni/Pd/Au are among the major surface finish candidates for lead-free component leads. Important aspects to consider are the adhesion of a lead finish to the molding compound and process compatibility. The typical thicknesses for these finishes are listed in Table 13. Inadequate adhesion can lead to delamination, followed by moisture ingress and possible popcorn effect. 2. Ni/Pd-Based Finishes The finishes listed in Table 13 constitute the finish for lead frame materials such as copper CDA194. It is intended that the palladium and gold layers in the thin film stack are to be completely dissolved into the solder and a metallurgical bond established by forming Ni–Sn intermetallic compounds. It is important to recognize that x-ray fluorescence measurements may not be adequate to accurately measure gold thickness in the 0.003-Am range [87].
TABLE 13
Typical Layer Thickness for Ni–Pd and Ni–Pd–Au Finishes
Finish
Ni (Am)
Pd (Am)
Au (Am)
Ni/Pd Ni/Pd/Au
1 0.5–2.0
0.075–0.25 0.02–0.075
— 0.003–0.010
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VISWANADHAM ET AL.
3. Other Finishes Other possible lead finishes such as pure Sn, Ag, Ag–Bi, Ag–Pd, etc. are available. However, it is important to address such issues as tin whisker formation and silver migration before deciding on a given lead finish composition. Potential reliability-related aspects of finishes must be understood. The mechanisms and kinetics of potential tin-related reliability issues are discussed in detail in Chaps. 21 and 22.
E. Process Atmosphere Reactions The wetting of substrate metal by a solder alloy is strongly affected by the flux composition, partial pressures of oxygen and water in the atmosphere, chemical reactions between the solder and the substrate, dwell time above the melting temperature of the solder, and cooling rate. The primary reactions that take place during soldering are reduction–oxidation (red-ox) reactions between gaseous components, flux components, elements of a solder alloy, and substrate metallizations. There are sufficient active flux components in pastes to effectively reduce the oxidized surfaces of solder particles, components, and board metal finishes (except Au) to achieve adequate wettability so that typically only minor oxide film fragments enter into solder joints. However, this state of affairs can change markedly, as the solder joints become much smaller as occurs in reflow soldering of 0201-type passive components. Moreover, most lead-free solders are somewhat more strongly oxidizing due to the higher chemical activity of tin in these alloys and lead-free finishes such as pure tin. Therefore, the fluxes may need to be more reactive in lead-free solder pastes. However, owing to decreasing volumes of printed solder pastes, the flux solvents evaporate more rapidly during the initial heating phase of reflow soldering operations. The fluxes are therefore less effective in removing oxide skins of metal particles in solder pastes, and this impairs proper fusion of the particles during reflow in air (Sec. VI.A). Therefore, the reflow soldering of small components on high-density PWBs will start gradually to require the employment of inert gases such as nitrogen (discussed in detail in Chap. 15) with low oxygen and moisture contents. Expenses will increase with the level of inerting purity needed to produce consistent solder joints. In such a situation, the small addition of a reducing component such as hydrogen into an inert gas can be a viable option. For example, in the case of Sn–Pb–Ag and most lead-free systems, the most stable oxide is SnO2(s), which can be reduced by nitrogen/hydrogen mixture according to the following reaction: SnO2 ðsÞ þ 2H2 ¼ ½Sn þ 2H2 O
ð12Þ
provided that the pressure ratio pH2O/pH2 at the activity level of the metal [Sn] in the alloy is sufficiently low at the soldering temperature. 1. Effect of Gas Contaminants and Mixtures In principle, a pure reducing gas has an immense reducing power. In practice, however, all gases contain some moisture and other gas components that impact their reducing ability relative to oxide films on the surfaces of solder particles, liquid solders, and solid metal substrates. The limiting conditions for oxide reduction by a gas can be considered using metal oxide equilibria and the corresponding equilibrium composition of the gas mixture. It can be shown that hydrogen or its mixture with some inert gas such as nitrogen (or argon) can reduce an oxide film if the moisture content of the gas is: pffiffiffiffiffiffi Kp ð1 xN2 Þ xH2 O V pffiffiffiffiffiffiffi pffiffiffiffiffiffi aSn þ Kp
ð13Þ
where XN2 is the mole fraction of nitrogen, aSn is the activity of tin in solders, and Kp is the equilibrium constant [71]. The water content of a 20% H2/80% N2 gas mixture must be very low in order to satisfy the thermodynamic conditions necessary for the reduction of oxides to be fulfilled at 250jC without any flux.
RELIABILITY ASPECTS OF LEAD-FREE SOLDERS
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2. Effect of Cooling Rates Dwell time above the melting temperature will increase the dissolution of minor elements into the solder and can increase the intermetallic compound growth rate in the solder joints. Further growth of intermetallic compounds will occur with slow cooling rates. An increase in the growth rate of Ag3Sn plates in Sn–Ag–Cu solders has been reported as significant with cooling rates slower than 3jC sec1 [88]. Cooling rapidly past the solidification temperature minimizes the formation of Ag3Sn plates. At cooling rates slower than 1.0jC sec1, the primary Ag3Sn plates can subtend the entire cross section of a BGA solder joint. Cooling issues are compounded by the thermal capacity of each solder pad. At sufficiently high cooling rates, the time interval during which the Ag3Sn plates can grow in the liquid phase before final solidification is sufficiently reduced to limit plates to a small size. The critical cooling rate for the desired plate size suppression may vary with the size of the solder joint and the nucleation kinetics of the solder mass. Solder joints that are connected to a ground plane can have a much significantly slower cooling rate due to the thermal lag of cooling the ground plane. This results in a disparity in the amount and size of intermetallic compounds formed in adjacent solder joints. Cooling rates should be sufficiently fast to minimize the intermetallic growth rates in spite of the differences in the thermal properties of solder joints across the assembly. More effective cooling also tends to result in a finer solder joint microstructure.
VII. BOARD LEVEL RELIABILITY A. Ceramic BGA (CBGA) Components with Pb-Free Interconnections Farooq et al. conducted a comparative thermal cycle test involving the reliability of ceramic BGA assemblies thermal cycled in the range of 0–100jC on 1.5- and 2.9-mm-thick FR-4 boards evaluating eutectic Sn–Pb, Sn–3.8Ag–0.7Cu, and Sn–3.5Ag–3.0Bi solders. The experimental matrix consisted of CBGAs with standard 10Sn–90Pb, Sn–3.8Ag–0.7Cu, as well as Sn–5Sb solder balls. The card attach solder paste was Sn–3.8Ag–0.7Cu with 63Sn–37Pb solder paste used as a control. Thus, the study consisted of both single-melt and dual-melt BGA joints. The interconnection reliability data were normalized to a standard joint height. The fatigue life of these lead-free solders is reported to be 1.5–1. 6 for Sn–Ag–Cu and 1.9–2.0 times better for Sn–Ag–Bi interconnections compared to eutectic tin–lead for the board thickness evaluated in the test. The thin boards or cards exhibited a 1.7 greater life compared to thick boards, apparently due to their lower stiffness. A thin layer (2 Am) of Ni–Cu–Sn intermetallic compound was observed to adhere to the Ni surface, with Ag3Sn and Cu6Sn5 dispersed throughout the solder matrix. Crack propagation was found to occur within the bulk solder of the joint instead of along the intermetallic compound zone [89]. In another study, Lee et al. [90] investigated the microstructure, joint strength, and failure mechanisms of Sn–3.5Ag and Sn–3.5Ag–0.5Cu vs. 62Sn–36Pb–2Ag ball grid array solder joints on electroless nickel/gold surfaces 6 and 1 Am thick, respectively. In addition, the samples were aged at 150jC for 1000 hr. The key findings were: In the Sn–Pb–Ag system, AuSn4 was found throughout the ball and some AuSn3 was also present. In contrast, Ag3Sn was observed to distribute along the Sn-rich phase boundaries in lead-free systems as fine particles or elongated structures. A thin layer of Ni–Sn intermetallics formed at the interface in the case Sn–Ag and Sn–Pb–Ag solders. On the other hand, Ni–Sn–Cu intermetallics are formed in the case of Sn–Ag–Cu solders. Most of the AuSn4 formed during the initial joint formation in the Sn–Pb–Ag system disappeared from the bulk after aging and tended to resettle at the substrate interface as (Au,Ni)Sn4 pseudoternary compound layer as reported by Zribi et al. [91], Ho et al. [92], and Minor and Morris [93]. The ternary intermetallic constitutes a contiguous layer on top of the Ni3Sn4 layer after 48–96 hr of aging at 150jC. In the Sn–Ag system, the layers adjacent to the pad were found to be Ni3Sn4 and AuSn4; together, they transform to a platelet compound (Au,Ni)Sn4. Thermal aging results in the
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formation of a quaternary intermetallic compound with a nominal atomic composition of 48Cu– 39Sn–10Ni–2Au. The intermetallic compounds AuSn4 and Cu–Sn–Au are both found in the bulk solder, whereas Cu–Au–Sn tends to settle toward the Sn-rich phase boundary and AuSn4 is dispersed throughout the bulk of the joint. Sn–Ag and Sn–Ag–Au joints tend to fail due to plastic deformation within the bulk solder even after 1000 hr of thermal aging at 150jC. In Sn–Pb–Ag systems, the initial failures are ductile fractures, but after aging, they are due to brittle fractures at the interface. Thus, in both lead-free systems, the failure mechanism is attributed to be a purely ductile fracture.
B. Plastic BGA (PBGA), Thin Small Outline Package (TSOP), and Other Components Mounted with Sn–Ag–Cu Solder Woosley et al. investigated the board level reliability of area array packages with pitches in the range of 0.8–1.27 mm, with various ball compositions, a range of substrate thickness (0.26–0.56 mm), leaded packages such as TSOP, and leadless passive components. Liquid-to-liquid thermal cycling (55jC to 125jC) tests were conducted with 388 I/O PBGA assemblies and air-to-air thermal cycling in temperature ranges 0jC to 100jC, 40jC to 125jC, and 50jC to 150jC. In a 40jC to 125jC accelerated thermal cycle (ATC) test of 324 I/O PBGAs, Sn–Pb–Ag solder balls joined with eutectic tin–lead paste and Sn–Ag–Cu paste performed almost identically based on the two-parameter Weibull plot with g values of 4555 and 4575 cycles, and b values of 15.19 and 14.76, respectively. On the other hand, assemblies with Sn–Ag solder balls attached with Sn– Ag–Cu paste performed the best with an g value of 8690 cycles and a b value of 8.1, as shown in Fig. 31 [94]. In a separate comparative study, accelerated thermal cycle tests (40jC to 125jC, 14-min dwell time at the extremities, with a 3-min transition) indicated that Sn–3.8Ag–0.7Cu exhibited equivalent or slightly better reliability compared to Sn–Pb–Ag solder interconnections, as shown in Fig. 32. The components (289 I/O, 0.8-mm pitch, PBGAs) were assembled on FR-4 boards
FIG. 31 Two-parameter Weibull plot of board level thermal cycle test results for a 324 I/O PBGA component. (Courtesy of Motorola Lead-Free Team Ref. 94.)
RELIABILITY ASPECTS OF LEAD-FREE SOLDERS
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FIG. 32 Temperature cycle test results for a 289 I/O PBGA component mounted on a FR-4 RC Cu board with via-in-pad configuration utilizing several solder/pad combinations.
using OSP and Ni/Au surface finishes. Typical failures in Sn–Pb and Sn–Ag–Cu solder joints were at the component/solder interface [95]. Prasad et al. conducted board level reliability studies of lead-free packages with several ball metallurgies assembled utilizing Sn–3.9Ag–0.6Cu and eutectic tin–lead for comparison purposes. The lead-free ball metallurgies included Sn–3.5Ag, Sn–0.7Cu, Sn–4.0Ag–0.5Cu, and Sn–2.5Ag– 1.0Bi–0.5Cu. The results indicated that the assemblies with the Sn–Ag–Cu alloy ball metallurgies outperformed the traditional Sn–Pb solder assemblies by a factor of two. Typical Weibull plots for 208 I/O and 72 I/O (M2CSP), 0.8-mm-pitch, chip-scale packages assembled on 1.5-mm-thick polyclad boards are shown in Figs. 33 and 34 for the two temperature ranges [96]. In the case of 48 I/O TSOP components with Sn–Pb-plated Alloy 42 lead, interconnections with eutectic tin–lead solder seem to outperform those with Sn–Ag–Cu joints in all the temperature ranges investigated, namely, 55jC to 125jC, 40jC to 125jC, and 0 to 100jC, respectively, as shown in Fig. 35 [94]. Comparison of thermal cycle tests performance utilizing various temperature ranges to evaluate 2512 resistors indicates that eutectic Sn–Pb and Sn–Ag–Cu pastes exhibit a similar performance at higher temperature ranges. In the 0–100jC temperature range, lead-free solder interconnections exhibit a slope that is less steep (2.84 vs. 7.1), and a slightly larger g value (3063 vs. 2256), as shown in Fig. 36 [94].
C. Effect of Aging on Several Types of Lead-Free PBGA Joints The effect of alloying metals on the aging behavior is not well understood. In addition, thicker intermetallic compound layers due to higher processing temperatures and attendant fragility of the solder joints are concerns. It has been reported in a thermal aging study conducted at 125jC and 150jC with 388 I/O plastic ball grid array package assemblies that the intermetallic compound layer growth is comparable to that in eutectic Sn–Pb solder joints. The activation energy for several Pb-free solders is given in Table 14. The activation energy is lower when the
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FIG. 33 Weibull plot for a 208 I/O CSP accelerated thermal cycle tested in the temperature range from 40jC to 125jC. (Courtesy of Chip Pac, Alpha Metals, Sanmina, Hewlett Packard, Ref. 96.)
silver content is higher. Sn–Ag and Sn–2.5Ag–1.0Bi–0.5Cu alloys exhibited fracture loads in the range of 600–700 N and those containing Cu, namely, Sn–Ag–Cu and Sn–Cu, exhibited fracture loads in the range of 900–1050 N. The fracture caused pad pullout from the epoxy at the glass/ epoxy interface. The initial IMC thickness in the case of both eutectic Sn–Pb and lead-free interconnections was in the range of 1.6–2.3 Am. Based on limited data, the IMC layer growth rate does not appear to be greater than for eutectic Sn–Pb solder. Due to higher reflow tem-
FIG. 34 Weibull plot for a 72 I/O M2CSP accelerated thermal cycle tested in the temperature range from 0jC to 100jC. (Courtesy of Chip Pac, Alpha Metals, Sanmina, Hewlett Packard, Ref. 96.)
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FIG. 35 Weibull plot for a 48 I/O TSOP with Alloy 42 leadframe material and various solder paste combinations, and thermal cycle temperature ranges. (Courtesy of Motorola Lead-Free Team, Ref. 94.)
FIG. 36 Weibull plot for a 2512-sized 0-V resistor for various solder paste and accelerated thermal cycle test conditions. (Courtesy of Motorola Lead-Free Team, Ref. 94.)
812 TABLE 14
VISWANADHAM ET AL. Activation Energies for Several Solder and Ball Compositions
Solder ball solder
Attachment solder
63Sn–37Pb Sn–2.5Ag–1.0Bi–0.5Cu Sn–4.0Ag–0.5Cu Sn–3.5Ag
63Sn–37Pb Sn–4.0Ag–0.5Cu Sn–4.0Ag–0.5Cu Sn–Ag–Cu
Activation energy (kJ/mol) 45 68 33 31
peratures, the IMC layer at the lead-free solder interface is slightly thinner compared to eutectic Sn–Pb solder. The joint strength is equivalent to Sn–Pb joints as determined by four-point bend tests [97].
D. Effect of Bi and Cu on Quad Flat Pack (QFP) Attached with Eutectic Sn–Ag Karia et al. studied the effect of additional elements such as Bi and Cu on the thermal fatigue life of QFP with Sn–3.5Ag solder joints. The 100-pin quad flat packs consisted of Alloy 42 leads with a Sn–20Pb solder finish. It was determined that the addition of bismuth (in the range of 2–5%) to the Sn–3.5 Ag solder degrades the thermal cycle reliability of the solder joints in the 100jC and 160jC DT range, resulting in a 20% reduction in joint pull strength. Cracks were reported after 200 thermal cycles. Solder joints with Sn–3.5Ag–(0.5–1%)Cu showed an initial higher joint pull strength by 11–22% compared to the eutectic Sn–Pb solder. The Pb phases at the lead/solder interface and bismuth in the Sn–Ag solder may promote crack propagation at the interface and reduce thermal fatigue life. From an isothermal fatigue point of view, an upper limit of 2% bismuth was suggested for Sn–Ag solders to achieve the same fatigue resistance as eutectic tin– lead solders [98].
E. Passives Attached with Pb-Free Solder Vianco and May evaluated large 1825 and 1205, and smaller 0805 chip capacitors in a study using Sn–3.5Ag, 58Bi–42Sn, and Sn–3.3Ag–4.8Bi solders. The component termination configuration was 100% Sn-plated finish over Ni or Cu barrier layers. A 127-Am-thick stencil was used for solder paste printing and test boards were reflowed in a four-zone oven using a peak temperature between 20jC and 30jC above the melting point of the solders. Wetting of the package terminations was reported to be excellent and, overall, the manufacturing feasibility analysis determined that there were no catastrophic assembly problems. A higher propensity for component misregistration was observed with Bi–Sn solders, was attributed to poor self-alignment during reflow, and was consistent with the lower surface tension of the Bi–Sn solders. Increased voiding was observed in solder joints on the larger packages. Mechanical strength of the solder joints was evaluated by applying shear loads on components as fabricated and after thermal cycling (55jC to 100jC, 66-min cycles) and liquid-to-liquid thermal shock (155–100jC, 15-min dwell). The strength values of the solder remained largely unchanged for the larger chips. However, test results for the 0805 chips indicated that the position of the components on the assembly and their proximity to other components can impact solder joint reliability [99].
F. Mixed Composition Systems Dunford et al. investigated the metallurgical and reliability aspects of Pb-free mixed technology electronic assemblies utilizing area array packages, leadless ceramic chip passives, and small outline integrated circuits with conventional Sn–Pb terminations on a thin PWB with Au/Ni surface finish utilizing Sn–Ag–Cu–Sb solder as the interconnection alloy. The Sn–Au and Sn–Ag
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intermetallic compounds were generally well dispersed in the solder joints. Solder joints made with gold-terminated components were observed to have regions of Sn–Cu intermetallic compounds separating the two gold-rich regions, as shown in Fig. 37. A greater concentration was observed to exist on the component side compared to regions on the board side. Detectable amounts of W, Co, Ni, Pt, Pd, and Fe in the bulk solder of these solder joints suggested dissolution and dispersion of the component terminations into the joint due to the higher reflow temperature compared to the Sn–36Pb–2Ag solder. The joints generally exhibit a mottled surface finish and surface voids, which are quite different from those found in conventional eutectic tin– lead solder joints. Thermal cycling and mechanical drop testing indicated that the Sn–36Pb–2Ag control samples experienced failures earlier than the lead-free samples [17].
G. Effects of Process Parameters and Metallurgical Interactions Second-level reliability was evaluated by Bartelo et al. [36] using Sn–Ag–Cu and Sn–Ag–Bi solders. Pad metallurgies employed are generally Ni/Au or Cu with OSP. Ag3Sn and Cu6Sn5 intermetallic compounds seem to interfere with the formation of a smooth shiny surface during the solidification process, resulting in a grainy and matte appearance. Some of the pad metallurgies at each of the joint interfaces (Ni or Cu) dissolved into molten solder and tended to migrate from one interface to the other, forming Cu6Sn5 on board pads metallized with nickel, probably substituted for Cu. In addition, copper from the solder alloy and that due to the dissolution process found their way to the nickel interface. Thus, intermetallic compounds containing Cu, Ni, and Sn can be found on the nickel surface. The Sn–Ag–Bi alloy was determined to be devoid of copper. Copper from the board pads generally finds its way into the bulk solder and forms Cu6Sn5. Reliability studies indicate that the number of cycles to failure decreases with an increase in temperature range and peak temperature, and a decrease in cycle time. Fatigue failure times (N50) in the 0–100jC range for the lead-free solder investigated was determined to be approximately twice that of eutectic tin–lead solder. Significant differences exist in the reliability data obtained in the 0–100 and 40jC to 125jC range. At larger dwell times (240 min/cycle), the lead-free solder joints performed worse than the control eutectic Sn–Pb samples,
FIG. 37 Vertical cross section of an LCCC solder joint showing two distinct zones within the solder joint separated by a Cu/Sn layer (500). (Courtesy of Nokia Corp.)
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only exhibiting 75% of fatigue life of Sn–Pb samples. Some variations in the results of the various studies suggest differences in the module and board characteristics (causing cyclical strains) and stress states to be different. The higher temperature range of 40jC to 125jC, or the increased temperature range of 165jC, can have a dramatic effect on the relative fatigue behavior: a larger strain range and increased fatigue damage, or both. Cross-polarizer optical microscopy revealed thermomechanical stress-induced microstructural changes in the vicinity of fatigue cracks generated during ATC testing in lead-free alloys. These changes are believed to be the result of plastic deformation and were verified by finite element analysis.
VIII. FLIP CHIP-RELATED ISSUES A. Characteristics of Some Lead-Free Solder Bumps There is no readily available drop-in replacement for wafer scale bumping of either the high-Pb or eutectic Sn–Pb solders. As explained before, the process can be further complicated by the metallurgical interactions of the solder alloy with the silicon device UBM, metal finishes on PWBs, and thermal compatibility issues. The possibility of the UBM forming low-melting eutectics or other phase mixtures with the constituents of lead-free alloys cannot be ruled out and must be carefully evaluated. Moreover, many of the metal finishes on PWBs dissolve rapidly into liquid solders and can therefore take part in the reaction between the ‘‘new’’ solder alloy and underbump metallizations, thus complicating the prediction of metallurgical reactions significantly. Several interconnection alloys have been explored recently to find a replacement for the eutectic tin–lead. These include binary alloys Sn–3.5Ag and Sn–5Sb, ternary alloys Sn–20In– 2.8Ag (Ind alloy) and Sn–10In–3.1Ag, and quaternary alloys such as Sn–10In–3.1Ag–1.0Cu, Sn– 20In–2.8Ag–1.0Cu, etc. A replacement for the high-temperature Pb–5Sn alloy is still an open issue. There have been some attempts to find a replacement but with limited success.
B. Effects of Assembly Processes Variables in the assembly process can have a significant effect on the long-term reliability of a Pbfree assembly. Most are associated with high-temperature soldering operations that can detrimentally affect the components. Secondary reflow and moisture sensitivity are initial concerns, along with parameters affecting intermetallic growth rates. Assembly issues are discussed in detail in Chap. 14. 1. Secondary Reflow Most surface assembly practices are likely to be centered around the Sn–Ag–Cu and Sn–Ag–Bi alloys with a melting temperature in the vicinity of 215jC. As a consequence, the melting points of solders internal to the package must be approximately 260jC to prevent the bumps from undergoing secondary reflow during the surface mount assembly process. Secondary reflow of the bump metallurgy can have undesirable consequences such as deformation and extrusion of solders within the underfill (i.e., solder migration), resulting in reduced assembly reliability and even electrical shorts. In these cases, thermal migration of solders from the component’s cold side to the hot side due to solid-state diffusion is not uncommon, and could result in voids or electrical shorts. 2. Other Factors and Issues Flip-chip assemblies using 10 10 and 5 5 mm chips attached to a halogen-free microvia board with Sn–3.5Ag–1.0Cu solder bumps (115 Am in diameter) were reported by Baynham et al. [100]. Nitrogen reflow was demonstrated to provide superior wetting. It was indicated that the solder shapes varied considerably in air reflow attendant with partial or incomplete wetting. Solder shapes, as shown in Fig. 38, can have a significant impact on reliability especially on joints at a large distance from the neutral point (DNP). It was also indicated that flip chips attached with lead-free solder can have a narrower process window compared to those attached with eutectic
RELIABILITY ASPECTS OF LEAD-FREE SOLDERS
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FIG. 38 Vertical cross section of a flip-chip attachment showing partial wetting of the pads. (Courtesy of Auburn University.)
Sn–Pb solders. This was attributed to the higher reflow temperature and the inadequacy of flux activity, joint starvation, pad oxidation, mask height tolerance issues, reflow atmosphere, etc. that can have significant influence on the structure of lead-free solder joints compared to chips joined with eutectic Sn–Pb solder. For example, at higher temperatures, flux may decompose or burn off prematurely. Alternatively, at higher temperatures, wetting quality may be affected [100]. Weise et al. [101] studied microstructure differences between flip-chip solder joints of Sn–Ag–Cu and samples six orders of magnitude bigger than flip-chip joints. The bulk samples exhibited nonuniform phase distribution and a larger grain structure. The flip-chip joints were more uniform with a much smaller grain size than the bulk solder because rapid solidification suppresses grain growth.
C. Effects of UBM and Lead-Free Solder Interactions 1. Sn–Ag and Sn–Ag–X Solders Interactions that a lead-free interconnection alloy may have with underbump metallurgy can have an impact on the integrity of flip-chip solder joints under both thermal and mechanical loading. Puttlitz and Totta [22] investigated the effect of TiW/Cu, Ni, and electroless nickel/gold underbump metallurgies with Sn–3.8Ag, Sn–3.8Ag–0.7Cu, and Sn–2Ag–2Bi solders on the system’s metallurgical characteristics, and on thermal and isothermal mechanical reliability. No large intermetallic compounds were observed to form with Sn–Ag–Bi solders and Ni–P UBM. Copper-containing solders produced an interfacial intermetallic compound containing Ni4Cu7Sn6, whereas those without Cu produced only Ni3Sn4. The presence of Cu generally affects interfacial adhesion. In joints without Cu, the needlelike Ni3Sn4 compound that formed caused a loss of adhesion and spalled into the solder. The adhesion is considered good in the case of Cu-plated compounds due to the formation of Cu3Sn and Cu6Sn5 at the interface. The bulk solder has Ag3Sn and Cu6Sn5 in the Sn–Ag–Cu solder system, but only Ag3Sn in the Sn–3.5Ag solder system. The interfacial intermetallic compounds in the Cu-containing solders are more uniform and stable than those that form with no Cu. In the case of Ni–P/Sn–3.5Ag bumps, the Ni3Sn4 IMC is observed to grow and it is also the region where fractures occurred. The case of Sn– 3.5Ag reflowing twice at 260jC and annealing at 150jC for 1000 hr resulted in a more extensive
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intermetallic compound formation compared to reflowing only once. The IMCs changed from a blocky to a planar morphology, suggesting differences in growth mechanisms between the liquid and the solid states. The solid-state IMC growth is considered to be predominantly an interfacial phenomenon [102]. 2. Sn–Bi and Sn–Pb Solders Jang and Park investigated the effect of a reflow process and UBM systems on the growth of intermetallic compounds for Sn–Bi and Pb–Sn solder bump/UBM interfaces. The UBM systems sputtered were Al/Ti/Cu, Al/Ti/electroless plated Cu, Al/NiV/sputtered Cu, and Al/electroless plated Ni/Au, and the solder bumps were eutectic Sn–Pb and Sn–Bi fabricated by electroplating. The microstructure and composition of IMC phases and their morphology were examined. The IMC compositions that formed were Cu6Sn5, Cu3Sn, Ni3Sn4, or Ni3Sn, depending on the UBM and solder compositions. The effect of IMC growth on bump adhesion strength was also investigated using a ball shear test. The ball shear strength was determined not to depend on processing conditions but on the solder/UBM interfacial adhesion strength in this case [103]. 3. Solid-State Interactions The growth mechanism in the solid state differs from the liquid state; the planar type is perhaps due to interfacial reaction. Lim et al. also investigated the tensile properties of Sn–3.5Ag, Sn– 0.7Cu, Sn–3.8Ag–0.7Cu, and eutectic Sn–Pb solders in the temperature range of 40jC to 180jC. It was reported that Sn–3.8Ag–0.7Cu showed the greatest strength at lower temperatures, but decreased significantly at higher temperatures. The tensile strength of Sn–3.5Ag decreased to the Sn–3.8Ag–0.7Cu level at higher temperatures. In addition, the tensile strength of Sn–0.7Cu is lower than the other two alloys at lower temperatures, but is slightly higher at higher temperatures. Results of tensile tests carried out on flip-chip bumps are reported to be similar to the tape samples. The differences between Sn–3.5Ag and Sn–3.8Ag–0.7Cu are insignificant. 4. Interfacial Failures The alloy Sn–0.7Cu exhibits the best fatigue life with a copper or nickel UBM. A Ni–P UBM with a Sn–3.8Ag–0.7Cu solder exhibited the lowest fatigue life due to interfacial failures also exhibiting similar failures with a Cu UBM. Failures observed for tin–lead solders occurred close to the solder/IMC interface, as is the case for the Sn–3.8Ag–0.7Cu and Sn–3.5Ag solders. In some cases, failures are through the IMCs themselves, or through the solder bulk for Sn–0.7Cu [102].
D. Effect of Creep on Pb-Free Flip-Chip Solder Joints The effect of composition differences on the microstructure of Sn–Ag–Cu solders is due to precipitates dispersed in the h-Sn matrix, which impart a higher creep resistance via precipitation strengthening or precipitation hardening. Steady-state strain rate data indicate that the Sn–Ag– Cu solder has a better high-temperature creep resistance than either Sn–Pb–Ag or Sn–3.5Ag. A large number of small particles offer greater resistance to the movement of dislocations, rather than a small number of large particles. Flip-chip Sn–Ag–Cu solder joints have been shown to exhibit much lower creep rates than bulk specimens. A comparison of creep-related parameters for flip-chip solder joints and bulk specimens is given in Table 15. The coefficient of thermal expansion (CTE) of Sn–Ag–Cu solder is 17.6 ppm/jC in the 20–150jC range, 16.7 in the 20– 100jC range, and 18.8 in the 100–150jC range [101].
TABLE 15 Creep-Related Parameters for Bulk Sn–Ag–Cu Solder and Flip-Chip Solder Joints Parameters Creep exponent Activation energy (kJ/mol)
Bulk solder 10 57.1
Flip chip 18 83.1
RELIABILITY ASPECTS OF LEAD-FREE SOLDERS
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E. Thermal Fatigue Characteristics of Some Lead-Free Solder Bumps ATC tests of flip-chip assemblies using cycles 50jC to 150jC and 40jC to 125jC have been reported in the literature. Flip-chip assemblies with Sn–3.5Ag solder bumps and no underfill materials were determined to be only 30–60% as reliable as corresponding assemblies with eutectic Sn–Pb eutectic solders. Quaternary alloy assemblies with Sn–2.5Ag–0.8Cu–1.0Sb solder bumps were about 80% as reliable as their eutectic Sn–Pb counterparts. Ternary Sn–20In–2.8Ag has been shown to form a low-melting Sn–In eutectic (113jC) that deteriorated the underbump metallurgy. The quaternary alloy Sn–10In–3.1Ag–1.0Cu, on the other hand, exhibited almost 1.5 times better reliability than the eutectic Sn–Pb system with no underfill enhancement. The absence of the low-temperature Sn–In eutectic was attributed to the low indium content of the alloy and the presence of copper. In addition, the soft and ductile nature of indium was suggested to contribute to the reliability [104]. However, DSC studies suggest that the improved reliability is predominantly due to the indium content, rather than the presence of copper. The reduction of indium from 20% to 10% and the addition of 1% copper may have shifted the reaction equilibrium in a manner that reduces the propensity for the formation of low-melting eutectic Sn–In. 1. Lead-Free Flip Chips on Ceramic and Organic Carriers Jung et al. investigated Sn–9.5Bi–0.5Cu (mp 198jC), Sn–3.5/Ag (mp 221jC), Sn–0.7Cu (mp 227jC), and Au–20Sn (mp 280jC) as potential wafer bumping alloys for flip-chip applications. The Au–Sn alloy was used for flip-chip attachment to a ceramic, whereas the other alloys were used with an organic laminate carrier. The underbump metallurgy in each case was Ni/Au, and the substrate surface finish for the organic laminate carrier was Ni/Au, but was a Pd–Ag–Au thick film metallization for the low temperature cofired ceramic (LTCC) carrier. The bump heights were in the range of 85–130 Am in all cases. All the assemblies were fabricated using a no-clean flux, underfilled and cured. Thermal shock was performed by utilizing a 55jC to 125jC range with a 10-min dwell at the extremities. The Sn–Ag assemblies showed failures earlier than 1000 shock cycles and could not be evaluated due to assembly defects of underfill delamination caused by flux contamination. The Au–Sn assemblies on LTCC lasted in excess of 4000 cycles. Preliminary results indicate promise for the use of these alloys for chip-scale packages and flipchip applications [105].
F. Evolution of Microstructures in Highest-Density Assemblies Constant demands for higher functionality and enhanced portability are driving manufacturers to increase the performance and to reduce size of their products. All these must be done without sacrificing reliably or increasing cost while meeting increasing technical challenges (e.g., in paste printing, component alignment, substrate technologies)—in addition to the environmental regulations. More fundamentally, increasing miniaturization will decrease solder joint volumes and reduce the thickness of metallization layers. There is a growing risk that the microstructure of small Sn–Pb solder bumps will result in a significant reduction in reliability in the field. Fig. 39a gives an example of such a decomposition of the originally uniform microstructure during the thermal cycling of flip-chip assembly. Fig. 39b shows crack propagation through the Pb-rich region of an LCC solder joint after 500 cycles from 40jC to 85jC. It is imperative that the effects of dissolution processes, intermetallic formation, and phase transformations be thoroughly understood and controlled, especially when the solder volume decreases to 104–105 mm3 or less. This is due to the fact that the solder joint strain is inversely proportional to the solder joint height. As the solder volume decreases, so does the joint height, resulting in a corresponding increase in solder joint strain. Another important reliability-controlling factor to be taken into account in designing and manufacturing the highest-density electronics in the future is the physical and chemical compatibility of the materials [106,107]. This is becoming increasingly more significant because the number of combinations of lead-free solder alloys, component termination metallizations, and board finishes is increasing—a fact that has been emphasized in this chapter.
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FIG. 39 (a) Flip-chip joint after 2500 thermal cycles from 25jC to 125jC, at 1 hr/cycle. (n IEEE 1998, Ref. 1a) (b) Microstructure of an LCC joint after 500 cycles from 40jC to 85jC, at 32 min/ cycle, showing crack propagation through the Pb-rich region. (Courtesy of Nokia Corp.)
1. An Example: Tin–Bismuth–Copper System When very small solder joint volumes are involved, the major component of the solder alloy (tin) reacts preferentially with the conductor metals (copper or nickel), gradually depleting tin from the alloy and thereby altering the original alloy composition. This occurs in most solder systems because the most commonly used alloying elements (lead, silver, or bismuth) do not react with either copper or nickel, and therefore are not consumed in solder reactions. In considering the Sn– 58Bi/Cu system, two cases can be distinguished: (a) the intermetallic compound reactions during reflow soldering, when the solder is in the liquid state, and (b) the further growth of the intermetallic compounds Cu6Sn5 and Cu3Sn during solid-state aging at ambient or elevated temperatures. a. Liquid State Interactions. During soldering, when the eutectic liquid Sn–Bi solder comes in contact with Cu (along the contact line, CL in Fig. 40), the local equilibrium is quickly
FIG. 40 Isothermal section of the Cu–Sn–Bi system at 235jC. Note the connection line (CL). (Courtesy of Helsinki University of Technology.)
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established between the saturated liquid A and the Cu6Sn5 (D) compound. The dotted line, from A to Cu6Sn5, indicates the local equilibrium. After Sn has diffused through the Cu6Sn5 layer, pure, solid Cu becomes saturated with Sn, resulting in the nucleation and growth of the solid Cu3Sn. These IMC reactions, being well established experimentally, are responsible for chemical bonding of solid solder to copper. What is not so well known is the sequence of events occurring with very small solder volumes, or, alternatively, during a very long time at temperatures where the diffusion of tin is limited [14,91,92]. If the amount of liquid is relatively small, it becomes enriched in bismuth because only tin is consumed in the IMC reaction. Therefore, the local composition of the liquid moves along the Cu6Sn5/liq phase boundary (i.e., liquidus projection) toward the Bi corner of the phase diagram. Accordingly, the diffusion path passes the apex of the three-phase triangle (liq+Cu6Sn5+Cu3Sn) (i.e., point C), and therefore the Cu6Sn5 reaction will stop and the Cu6Sn5 layer starts to disappear from the (liquid) joint structure, mainly by transforming into the Cu3Sn (q) compound [14,91]. With increasing reflow time, the liquid solder will be in equilibrium with pure bismuth so that the diffusion path is through the Bi corner (Fig. 40). According to this local equilibrium condition, a pure bismuth layer is formed between the liquid solder and the Cu3Sn phase. b. Solid-State Interactions. On the other hand, during solid-state aging of a larger joint, tin is consumed near the solder IMC interface because of slow diffusion of tin in the solid solder alloy. A layer rich in bismuth is formed between the Cu6Sn5 layer and the bulk solder. The bismuth layer acts as a diffusion barrier for tin and so retards further growth of the IMCs. The corresponding microstructure is generated when the solid eutectic Sn–Pb solder is in contact with copper at elevated temperatures. In fact, this is what happens during thermal cycling, as shown in the flip-chip solder in Fig. 39a. In this joint, practically pure lead layers are formed during thermal cycling (for 2500 cycles from 25jC to 125jC) between the bulk eutectic Sn–Pb solder bump and Cu UBM layer on the component side, and the Cu pad on the board side. It is interesting to note that the Cu3Sn layer (which only can be in local equilibrium with the Pb-rich phase) is thinner on the bump side where the crack is located. These examples point out the importance of understanding the local equilibrium in the microjoints and associated metallurgies in assessing reliability. This is especially true where solder bump volumes, thin metallizations, or kinetic constraints responsible for the redistribution of the second phase (e.g., Bi or Pb) in the solder/conductor system are involved.
G. Transfusion-Bonded Pb-Free Flip Chips A method of avoiding the decomposition of very small solder joints into brittle microstructures was reported recently by Kivilahti and Kuloja¨rvi [108]. It is essential that this Pb-free lowtemperature interconnection technique not be based on the formation of IMCs, but rather on the formation of high-tin microjoints when chemically coated tin and bismuth layers on Cu conductors are fused together. The silicon devices are bumped with pure tin followed by a thin chemical coating of bismuth, as are the conductor pads on flex or rigid chip carriers. The devices’ bumps are placed on the mating chip carrier pads and are heated to temperatures above 139jC. The fusion is initiated at both Sn–Bi interfaces in contact with each other as the eutectic temperature of the Sn–Bi system is attained. During solidification, tin-rich joints with finely dispersed Bi particles are formed. The transient nature of the fusion means the second macroscopical melting will occur at temperatures that are close to the melting point of pure tin. The mechanical properties such as strength, ductility, etc. of the joints are controlled primarily by the temperature of bonding and the cooling rate. The flip-chip joints with appropriate underfilling have been shown to survive 1000 cycles in thermal shock testing in the range of 40jC to 125jC without failures [109,110].
IX. SUMMARY A number of Pb-free binary, ternary, and quaternary alloys with combinations of potential candidate elements solder alloys have been surveyed and the differences in their mechanical
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properties were discussed. These included those containing copper, tin, silver, bismuth, indium, and germanium. Among the lead-free solders, the tin–copper–silver-based alloys seem to stand out as potential replacements for tin–lead solders, although none of them is a drop-in substitute. The composition of the interconnections formed can be significantly different from the initial alloy due to interaction with the component lead termination metallurgies and the printed wiring board surface finish metallizations. Although the technical literature on traditional tin–lead solders is quite exhaustive because this solder has been utilized in electronic assembly for about five decades, the same is not the case for lead-free solders. Lead-free solder interconnections are much more complex in their structure, and considerable research effort is needed to understand these multicomponent systems. However, the thrust for environmentally safe electronic interconnect materials is gaining ground, and the number of technical contributions has been increasing. Thermal cycling reliability studies with Sn–Ag–Cu-based alloys indicate acceptable reliability for many applications, and in fact suggest a 1.5–2 improvement over eutectic Sn–Pb solders in many cases. However, there are instances where the reliability of Pb-free solder interconnections is equivalent, or slightly lower than, conventional eutectic Sn–Pb solder joints. This is particularly the case with thin small outline packages or packages with stiff leads. Thus, it is important to recognize these variabilities and verify assembly reliability for specific applications. In addition, much of the reliability information pertains to performance under thermal loading conditions, and considerable effort is needed to understand the reliability under mechanical loading conditions such as drop, bend, and torque. The choice of the printed wiring board surface finish has been shown to have significant effects on the joint microstructure in the interfacial regions. The effect of minor elements contamination is an important aspect in the overall second-level assembly reliability. In general, Pb contamination reduces the reliability of solder joints from Pbfree alloys. Lead content in the range of 2–6% has more pronounced effects than at higher concentrations (<20%). Owing to the higher processing temperatures involved, other elements such as Fe, Ni, Pd, Pt, etc. make their way into the solder joints. It is well known that the mechanical properties of many alloys can be modified by the addition of specific minor elements. Although the influence of these elements may be minimal, the physicochemical and metallurgical microstructural aspects are still largely unexplored. Lead-free solders, due to their higher melting point and hence higher assembly reflow temperatures, have an impact on the use of plastic encapsulated microcircuits. The moisture sensitivity levels can degrade by as much as two levels. Development of more robust encapsulating materials, better parts handling, and management during manufacturing operations may be imperative to avoid the degradation of packages including popcorning. The failure mechanisms in the Sn–Ag–Cu-based solder joints have been observed to be considerably different from those encountered in conventional eutectic Sn–Pb solder assemblies, and have been addressed in the chapter. Flip-chip attachment with Pb-free solders is shown to present unique assembly and reliability issues pertaining to the underbump metallurgy. Miniaturization trends in the electronic industry continue with ever-smaller interconnection schemes. The implications of compositional changes have been demonstrated to have associated reliability consequences. In summary, Pb-free solder developments and their implementation in electronics manufacturing are moving forward. The technical literature aimed at understanding Pb-free materials is rapidly increasing. During the implementation phase of Pb-free manufacturing, the industry must address several compatibility issues in the context of the best business practice. Combinations include use of lead-free pastes with Sn–Pb-plated leads or solder balls, or the use of eutectic Sn–Pb pastes with Pb-free termination metallurgies and solder balls. Implementation will likely occur first in the consumer and portable electronics industry where the reliability risk is reduced by the short product design life. Significant knowledge will be gained through the implementation of Pb-free solders in these markets owing to their high-volume manufacturing and distribution infrastructure including warrantee replacement programs. The implementation of lead-free solders is an avenue for a better understanding of these new materials in terms of their metallurgical properties, long-term reliability, and innovations in interconnection materials.
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ACKNOWLEDGMENTS The authors wish to acknowledge valuable help from many of their colleagues and particularly Vesa Vuorinen, Toni Mattila, Kari Kulojarvi, Pekka Rautila, and Weiqun Peng; management support from Pertti Ikalainen and Mark C. Sunderland; and assistance with tables from Pat Liles.
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Whitten, G. Lead free implementation for automotive electronics. Proceedings of the Electronic Component and Technology Conference, Las Vegas, NV, May 2000; 140–149. Melton, C. Nitrogen atmosphere processing in lead free soldering. Proceedings of NEPCON West ’95, Anaheim, CA, February–March 1999; 171–176. Shangguan, D.; Achari, A. Lead-free solder development for automotive electronics packaging applications. Proceedings, Surface Mount International, San Jose, CA, August 1995; 423–428. Lee, N.C. Getting ready for lead free solders. Surf. Mt. Technol. March 1997, 9 (2), 65–69. Plumbridge, W.J. Solder in electronics. J. Mater. Sci. 1996, 31 (10), 2501–2514. Bastecki, C. A Bench Mark Process for Lead Free Assembly of Mixed Technology PCBs. Report from Internet, Alpha Metals, NJ, http://www.alphametals.com/products/lead_free/PDF/leadfree.pdf, 1997. Flanders, D.R.; Jacobs, E.G.; Pinizzotto, R.F. Activation energies of intermetallic growth of Sn–Ag eutectic solder on copper substrates. J. Electron. Mater. 1997, 26 (7), 883–887. Kariya, Y.; Otsuka, M. Mechanical fatigue characteristics of Sn–3.5Ag–X (X=Bi, Cu, Zn, and In) solder alloys. J. Electron. Mater. 1998, 27 (11), 1229–1235. Kariya, Y.; Otsuka, M. Effect of bismuth on the isothermal fatigue properties of Sn–3.5 mass% Ag solder alloy. J. Electron. Mater. 1998, 27 (7), 866–870. Igoshev, V.I. Microstructure changes in Sn–3.5Ag solder alloy during creep. J. Electron. Mater. 1998, 27 (12), 1367–1371. Shimizu, K.; Nakanishi, T.; Karasaw, K.; Hashmoto, K.; Niwa, K. Solder joint reliability of indium– alloy interconnections. J. Electron. Mater. 1995, 24 (1), 39–45. Shina, S.; Belbase, H.; Bresnan, T.; Provencal, P.; Walters, K.; Biocca, P.; Skidmore, T.; Abbott, D.; Pinsky, D. Selecting material and process parameters for lead-free SMT soldering using design of experiments. Proceedings of APEX, San Diego, CA, January 2001; LF1-1. Bartelo, J.; Cain, S.R.; Caletka, D.; Gosselein, T.; Henderson, D.W.; King, D.; Knadle, K.; Thiel, G.; Woychik, C.; Shih, D.Y.; Kang, S.; Puttlitz, K.; Woods, J. Thermomechanical fatigue behavior of selected lead-free solders. Proceedings of APEX, San Diego, CA, January 2001 LF2-2-1–LF2-2-12. Tonapi, S.; Srihari, K.; Borgesen, P. Effects of flux and reflow parameters on lead-free flip chip assembly. Proceedings of APEX, San Diego, CA, January 2001; AT5-2. Melton, C. How good are lead-free solder joints. Surface Mount. Technology 1995, 9 (6), 32–36. Miller, C.M.; Anderson, I.E.; Smith, J.F. A viable tin–lead solder substitute: Sn–Ag–Cu. Journal of Electronic Material 1994, 23 (7), 595–601. Anderson, I.E.; Miller, C.M.; Smith, J.F.; Terpstra, R. Sn–Ag–Cu: A technologically viable Pb-free solder. Seminar Materials, AMES Laboratory, USA; 1994. Anderson, I. Sn–Ag–Cu: A lead free solder for board applications. Proceedings of NEPCON West ’96, February 1996; Vol. 2, 882–887. Frear, D.R. The mechanical behavior of interconnect materials for electronic packaging. J. Met. 1996, 48 (5), 49–53. Anderson, I.E.; Miller, C.M.; Smith, J.F.; Terpstra, R.L. Sn–Ag–Cu: A technologically viable Pb-free solder. Proceedings, Lead-Free Solders—A Mechanics and Material Approach; Northwestern University: USA, July 24–26, 1995. Nimmo, K. Review of current issues in lead-free soldering. Proceedings of Surface Mount International, San Jose, CA, September 1997; 465–467. Hitch, T.T.; Palit, K.; Prabhu, A.N. Critical evaluation of Pb-free solder alloys and performance comparison. Proceedings of the International Conference on Electronic Assembly Material and Process Challenges, Atlanta, GA, May 1996; Vol. 2, 1107/1-15. Kokko, P. Microstructure and Suitability of Sn–Ag–Cu Solder to Reflow Soldering in Normal Conditions. Internal Report. Helsinki University of Technology, 1997. in Finnish. Laine-Ylijoki, T.; Steen, H.; Forsten, A. Development and validation of a lead-free alloy for solder paste applications. IEEE Trans. Compon. Packag. Manuf. Technol., Part C July 1997, 20 (3), 194–198. Lee, B.J.; Lee, H.M. Alloy design of Sn–Ag–In–Bi–Sb solder system using thermodynamic calculations. Proceedings of the Design and Reliability of Solders and Solder Interconnections, Orlando, FL, February 1996; 129–136. Basticki, C. A Benchmark Process for the Lead-Free Assembly of Mixed Technology PCBs. www. alphametals.com. Hua, F.; Glazer, J. Lead-free solders for electronic assembly. Proceedings of the Design and Reliability of Solders and Solder Interconnections, Orlando, FL, February 1997; 65–73. Miric, A.Z. Lead-free alloys. Solder. Surf. Mt. Technol. 1998, 10 (1), 19–25. Richards, B.P. Tomorrow’s Solder Today. www.alphametals.com. Habu, K.; Takeda, N.; Watanabe, H.; Ooki, H.; Obe, J.; Saito, T.; Taniguchi, Y.; Katayama, K. Novel lead free solder alloys for electronic assembly. Proceedings of the 2nd International Symposium, Eco-Efficient Concepts for the Electronics Industry Towards Sustainability, Vienna, Austria, November 1998; 125–128.
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20 The Physics and Materials Science of Electromigration and Thermomigration in Solders James R. Lloyd IBM Corporation, Yorktown Heights, New York, U.S.A.
King-Ning Tu University of California at Los Angeles, Los Angeles, California, U.S.A.
Jasvir Jaspal IBM Microelectronics Division, East Fishkill, New York, U.S.A.
I.
INTRODUCTION
Electromigration (EM) and Thermomigration (TM) or Soret Effect are classes of mass transport resulting from the momentum transfer between conducting electrons and diffusing metal atoms. They occur in any material carrying electrical current (EM) or sustaining a temperature gradient (TM), but in most applications, it is negligible and can be ignored. Occurring when diffusion rates are relatively rapid and in the presence of high direct current densities, electromigration has been identified as a major potential failure mechanism in semiconductor devices. Millions, perhaps billions, of dollars have been expended over the past few decades understanding and controlling this phenomenon. Remarkable progress has been made in the past decade in understanding the physics and materials science of electromigration, and this knowledge has enabled reasonably accurate reliability predictions and significant reliability enhancements through effective design rules governing on-chip metallization. Although there is very little published data concerning solder materials and electromigration, there is every reason to believe that what has been learned with other metal systems can be applied to solder materials as well.
II.
ELECTROMIGRATION
A.
Theory of Electromigration
The first ever observation of electromigration occurred long before it became an engineering problem. Fully a century before it was recognized as a reliability issue, electromigration was observed in a series of experiments that are remarkably relevant even today. In fact, the same reasons that electromigration was observed in these older experiments apply today to solders as well.
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1. Early Studies and Observations a. The First Observations of Electromigration. In the middle of the nineteenth century, electricity was not at all well understood and experimenters were trying just about anything with batteries and dynamos. In 1861, a French scientist, M. Gerardin, was curious about the effects of passing current through a variety of conductive metallic salts and molten metals [1]. Among other things, he wondered what would happen if metals were solidified while connected to a battery. When he performed these experiments, he noticed that the properties of the solidified alloys he investigated were markedly different from those prepared without current flowing. In one case, he found that one end of a sample was brittle while the other was ductile after solidification under bias (Fig. 1). In another, he noticed that one end of a melt would solidify before the other as it was cooled. More interestingly, the effects disappeared when treated metal ingots were remelted without current flowing. When the polarity was switched, the location of the effects was reversed. This ‘‘trick’’ could be performed over and over again. In 1861, there was no real explanation for these effects. Although Michael Faraday’s discovery of electrochemistry a few decades earlier may have suggested an explanation, it would have been incorrect because electrons had not been discovered yet. Without electrons, a proper explanation would have been impossible. Nothing resembling a correct interpretation was forthcoming for more than a half century. b. Inability to Explain with Contemporary Physics. Investigators soon realized that electrochemistry, as understood at the time, could not account for the observed results of these experiments. In most cases, metal atoms were observed to migrate from the cathode to the anode, implying that the metal ions were negatively charged. However, as understood, metal ions were positively, not negatively, charged and should have been attracted to the cathode. Therefore, something else must be responsible for the unusual observed effects. Soon after electrons were discovered, it was recognized that they may be the responsible agents. 2. Basis of Modern Electromigration Theory a. Diffusion. Electromigration is a diffusion-controlled process. Like any diffusion-controlled phenomenon, electromigration-induced mass transport follows the Einstein equation, vD ¼
DF kT
ð1Þ
where vD is the drift velocity (cm/sec), D is the diffusion coefficient (cm2/sec), F is the driving force for diffusion (eV/cm), and kT is the average thermal energy per atom The diffusion coefficient (D) is thermally activated,
DH D ¼ D0 exp ð2Þ kT where D0 is a temperature-independent constant with units of D (cm2/sec) and DH is the activation energy for the active diffusion pathway (eV). Solder materials are low-melting-temperature alloys and because the activation energy for diffusion tracks with the melting point in metals, diffusion in these materials is unusually rapid. Eq. (1) includes not only the diffusion coefficient, but also the driving force. The driving force for mass transport in any system is the chemical potential gradient, composed of many components, all of which are acting either together or in opposition to each other. Electromigration is but one of these components. The interaction of electromigration with the other driving forces is responsible for the varied behavior of metals carrying high direct current densities. This must be fully appreciated to understand not only how solders will act, but how any conductor will act under operational conditions in microelectronic applications. b. Electron Wind, the Electromigration Driving Force. The first reasonable explanation of the electromigration driving force came from Skaupy, who introduced the concept of the ‘‘electron wind.’’ What he proposed, which has been shown to be generally true over the
FIG. 1 M. Gerardin determined in 1861 that if Pb was allowed to freeze while current was being passed through it, one end of the sample would freeze before the other, an effect that could be reversed with a reversal of the polarity.
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LLOYD ET AL.
intervening decades, is that at high current densities, conducting electrons collide with diffusing metal atoms and gently push them in the direction of electron flow [2–4], as depicted in Fig. 2. In deference to the understanding of the day, electromigration was expressed in electrochemical terms as, ~ ~em ¼ Z*eE F
ð3Þ
where Z* is a dimensionless quantity called the effective charge or the effective valence, e is the electronic charge, and E is the electric field (v/cm). As it turns out, Z* is neither a charge nor a valence, but is a measure of the momentum exchange that results from the collisions of the electrons with diffusing atoms [5,6]. As such, it is critically dependent on the electronic structure in the conductor and can be either negative or positive depending on whether the scattering is primarily from n- or p-type charge carriers (Fig. 3). For a conducting metal, the electric field can be expressed as the product of the current density and the electrical resistivity, ~em ¼ Z*eqj F
ð4Þ
where Fem is the the driving force due to electromigration, q is the resistivity, and j is the current density. This equation more accurately represents the physics of the phenomenon than does Eq. (3). It is more appropriate to think of electromigration-induced mass transport as the consequence of high current density rather than resulting directly from the electric field. c. The ‘‘Effective Charge’’ Z*. Z* is an interesting quantity that relates how a diffusing atom interacts with or absorbs the impact of conducting electrons, which is a complex function of the electronic structure, a quantum mechanical effect (Fig. 3). For high conductivity metals, i.e., Al or Cu, the value of Z* is about 1. Experiments have shown that, for solder (Pb and Sn), Z* may be much higher, up to f50. This is undesirable from a reliability perspective. Even with a low Z* value, electromigration in Al and Cu has long been a reliability issue in chip conductor metallization systems, so that if this quantity is significantly larger as it appears to be in solder materials, the effects should be correspondingly more serious. The ‘‘one–two punch’’ of speed (fast diffusion) and power (high Z*) is always a potent combination.
FIG. 2 Schematic layout depicting the effect that conduction electrons have on diffusion. Vacancy defects act as scattering center. When an electron scatters, the change in momentum is partially transferred to the defect creating a biased diffusion referred to as electromigration.
ELECTROMIGRATION AND THERMOMIGRATION
831
FIG. 3 The effective charge, Z*, is determined by the effective mass, m*, of electrons available for interaction which must be within kT of the Fermi energy. The effective mass is proportional to the second derivative in the energy (E)-vs.-momentum (k) relationship, a quantum mechanical effect near E=Ef. Above the inflexion point m* is negative, below it m* is positive.
d. Key Driving Force Contributors. The details of electromigration failure are not so simple, however. One cannot treat electromigration as a lone entity, but must realize that the driving force in Eq. (1) is the complete chemical potential gradient and encompasses contributions from many driving forces. The ones that we are most concerned with are summed as, F¼
X
! Fi
¼ FEM þ FTM þ Fr þ FS
ð5Þ
i
where electromigration (EM) is but one of four major contributors to the driving force. The other three are thermal gradients (TM), stress gradients (r), and chemical potential gradients (S). How they interact and the roles they play in reliability depend on the temperature, geometry, and alloy composition. For instance, for a pure metal (such as pure Cu or Al), usually only electromigration and stress gradients are important. In solders, especially those used in flip-chip solder joint (C4) applications, thermomigration (Soret Effect) where the driving force depends on a temperature gradient can also be important. HYDROSTATIC STRESS. Diffusion occurs through a vacancy mechanism and it can be argued that high vacancy concentrations and vacancy precipitation into voids causes failure. Vacancies, however, cannot be generally supported in metal films above or below the thermal equilibrium concentration provided that sinks and sources are readily available. If the vacancy concentration is above the thermal equilibrium value, they will annihilate at a sink until the equilibrium value is attained. Conversely, if the vacancy concentration is below the thermal equilibrium value, vacancies will be generated at a source until, again, the thermal equilibrium concentration is attained. A common source and sink may be a dislocation, where a climb in one direction will consume vacancies whereas motion in the other will produce vacancies. Dislocations in the lattice or in grain boundaries can be equally active in maintaining the thermal equilibrium vacancy concentration. When vacancies annihilate they generate a tensile stress. Conversely, a vacancy can be formed to relieve compressive stresses. The interaction of vacancy-annihilated-induced stress with electromigration produces the behavior described below. The hydrostatic component of this stress constitutes a chemical potential. Any gradient in this potential provides a driving force for mass transport, Fr ¼ Xjrh
ð6Þ
where X is the activation volume (generally assumed to be the vacancy volume) and rh is the hydrostatic component of the stress.
832
LLOYD ET AL. For pure metals, Eq. (5) must be rewritten as F ¼ Fem þ Fr ¼ Z*eqj X
Br Bx
ð7Þ
if the discussion is limited to mass flow in the x-direction only. STRESS GRADIENT AND EFFECTS. What happens next depends on the boundary conditions and, therefore, on the geometry. If there are perfectly blocking boundaries on each end of a conductor, which means vacancies or atoms cannot diffuse beyond or through the boundary, such as contacts to a semiconductor or to another more refractory, metal where the diffusion coefficient is vanishingly small. The steady-state flux must match the boundary conditions and in this case, by definition, J=0. With a nonvanishing mobility between the blocking boundaries, this can only be achieved if the driving force vanishes. One way this will occur is if a stress gradient is generated in opposition to electromigration. When the two driving forces become equal and opposite a steady state stress gradient is generated (Fig. 4), Br Z*eqj ¼ Bx X
ð8Þ
Eq. (8) can only be satisfied if the stress gradient is maintained. This, in turn, can only be achieved if the material is sufficiently strong to withstand the stresses required to maintain the gradient over the entire length of the conductor. If, on one end, the tensile stress becomes too great, a void or a crack may form, conversely on the other end, if the stress is too great in compression an extrusion will be produced. 3. Blech Length and Blech Product The production of the stress gradients described in the previous section is responsible for one of the most important features of electromigration induced failure, the Blech length effect. Given a maximum stress that can be sustained by the conductor, integration of Eq. (8) produces a product of current density and length that determines whether electromigration damage can occur. If this product is exceeded, damage can result; if it is not exceeded, electromigration damage will not take place. This product was discovered by I.A. Blech in the 1970s and is referred to as the ‘‘Blech Product’’ [7–9], jlB ¼
ðrm r0 ÞX Z*eq
ð9Þ
where r0 is the initial hydrostatic stress in the conductor, rm is the maximum hydrostatic stress that can be accommodated, and lB is the Blech Length (see below). The Blech Length, lB, is the length of a conductor below which electromigration will cease for a given current density, j. Any conductor shorter than a Blech Length will not exhibit electromigration, whereas anything longer will react otherwise. The concepts of the Blech Product and Blech Length are very important in understanding electromigration damage. If all conductors could be designed so that jlB remains below the critical value, electromigration failure could not
FIG. 4 Schematic of the steady-state stress buildup due to electromigration as a function of distance from an absolute flux divergence (blocking boundary).
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833
occur because mass transport comes to a complete halt. For flip-chip solder joint (C-4) applications, this means that if solder joints are sufficiently short or the current is limited below the critical level, long-term reliability issues due to electromigration failure can be eliminated. a. Typical Values. The Blech Product for unconstrained Al alloys is on the order of 2000 A/cm, with some temperature dependence related to the reduction in material strength with increasing temperature. For solder alloys, which are mechanically weaker than Al and also have higher Z* values, jlB may be at least 1 order-of-magnitude smaller. Therefore, for a Blech Product of 100 A/cm, we can substitute for lB, the solder joint height (say f75 Am) into Eq. (9) and calculate a critical current density of f13,000 A/cm2. This could be within the requirements of many applications, thus offering the possibility of designing ‘‘immortal’’ solder joints. Recently, the Blech Product for a high Pb solder was estimated at 110 A/cm [10]. b. Effect of Thermal Stress. As expressed in Eq. (9), the Blech Product is also a function of the initial stress state in a conductor. For on-chip conductors, which are constrained by interlevel dielectric (ILD) layers with a very small coefficient of thermal expansion (CTE or a), stress is generated because of the difference between the operational-use temperature and the temperature at which the dielectric was applied and is given as, rth ¼
E DaDT 1m
ð10Þ
where E is Young’s modulus of elasticity, m is Poisson’s ratio, Da is the difference in CTE of the metal and the confining matrix, and DT is the temperature excursion from a stress-free condition. The temperature where the conductor is stress-free will be a function of the materials and the process used to deposit them. For metals encapsulated in a dielectric that is applied or cured at an elevated temperature where any internal stresses can be relieved, the application or cure temperature is the point where the metal is stress-free. For solder joints, this would be the temperature of application or cure temperature of an underfill. c. Void and Extrusion Failure. The Blech Product can be defined differently for the two distinct failure modes of void or extrusion formation. For the extrusion failure mode, rm is compressive, and for void formation rm is tensile. For Al or Cu chip conductor metallization with oxide ILD, r0 is usually tensile, promoting void formation. For flip-chip solder joints with a filled epoxy underfill, r0 may be compressive, favoring extrusions as a failure mode. With no underfill, r0 may vanish, leaving the preferred failure mode uncertain. It must be pointed out that rm and r0 in Eq. (9) are the hydrostatic components of the stress and even when there is considerable shear stress due to differences in the CTEs of a chip and substrate, the hydrostatic component is often limited. d. Solder Joint Geometry Dependence. Because of the effect of the Blech Product limiting damage, electromigration in solders probably only poses a potential problem for flip-chip solder joints and ball grid array components. In other electrical uses of solder, such as when two wires are soldered together, they are intimately connected with little or no separation. The length of solder acting as a conductor in the direction of current flow is typically short (less than a micrometer), well below the Blech Length. Furthermore, it is not usually the solder itself that carries the current, but the components joined by the solder. Before voids or extrusions could form, the Blech condition would be satisfied and electromigration would come to a halt. In flip chip applications, however, the solder joint has nonzero height and relatively high currents (up to 1 amp) are carried directly by the solder itself. Under these circumstances, electromigration can be a problem.
B.
Fast Diffuser Electromigration
There exists a class of elements known as ‘‘fast diffusers’’ in Pb and Sn that diffuse interstitially. These fast diffusers, which are typically the noble and near-noble elements such as Cu, Ag, Au, and Ni, play an important role in the reliability of solder joints. They are commonly used in integrated circuits (ICs) or printed circuit boards (PCBs) as part of the under bump metallurgy
834
LLOYD ET AL.
(UBM) or as conductors, respectively. In all cases, fast diffusers not only diffuse extremely fast compared to other elements, but also form intermetallic compounds (IMC) with solder constituents. The values for activation energy for diffusion and the effective change (Z*) for some common materials utilized in electronics assemblies are listed in Table 1. 1. Solubility and Fast Diffusion Electromigration of the noble metals (Cu, Ag, Au) and Ni have been studied in Pb, Sn, and Pb–Sn alloys. Curiously, there is a strong inverse correlation between diffusivity and solubility. In both Sn and Pb, the diffusion coefficient is markedly increased as the solubility is reduced. As an example, Sn has substantial solubility in Pb and, although the melting temperature is depressed by its presence, the diffusion coefficient of Sn in Pb is 5 orders of magnitude slower at 100jC than Cu, which has a solubility estimated in the parts per million range. The fastest solid state diffusion known is Ni in Sn, at f104 cm2/sec, where the solubility rate is an almost unmeasurable 10 parts per billion. Extremely low activation energies for diffusion are also recorded. 2. Interstitial Diffusion The reason for the extremely rapid diffusion is that fast diffusers occupy interstitial sites in the host metal lattice. Lead (Pb) has close-packed (face centered cubic) lattice, but Pb is a large atom. Tin (Sn) does not have a close-packed lattice [body centered tetragonal (BCT)]. Both of these structures contain relatively large interstitial sites that can accommodate the much smaller fast diffuser atoms (Fig. 5) without significant strain. Because of this, it has been well established that the noble and near-noble elements diffuse interstitially in Group IV metals. Because interstitial diffusion does not require a vacancy for the diffusing atom to jump into during mass transport, the vacancy formation term is absent in the equation of the diffusion coefficient. Naturally, for interstitial diffusion to occur, the diffusing atoms must fit into the interstices of the host metal lattice, which requires that they be substantially smaller than the host atoms. Not surprisingly, the diffusion coefficient tracks closely with the atomic diameter of the diffusing metals, but the dependence is far from linear. Both Au and Ag (1.442 and 1.445 A, respectively) diffuse fully 10,000–100,000 times slower than Ni (1.246 A) in Sn. Atomic diameter is not the only determining factor, however. With Pb, chemical affinity or valence effects also appear to be important factors. The size effect is more important in Sn than Pb as the host metal. 3. Effect of Second Components Solders are typically eutectic alloys, not pure metals, usually consisting of two phases, such as the commonly used SnPb solder. Some, however, such as Pb–In can be a single-phase solid solution. If there is a second component, its concentration gradient may be considered in the driving force balance. The Z* of solutes is typically different compared to that of the solvents, so that Eq. (5) can be written,
B ln C Br * þX F ¼ Fem þ Fr þ FS ¼ Z solute eqj kT Bx Bx
ð11Þ
where C is the concentration of the solute. In this approximation, the solvent is assumed immobile. Cross terms, such as those reflecting the interaction of the solute concentration with the stress, are ignored for simplicity. Many experiments have been performed confirming Eq. (11), including solder-technology related materials. It is in the nature of the eutectic system, such as in Sn–Pb, however, that the chemical potential can remain constant over a wide composition range below the eutectic temperature. Hence, there is no driving force to homogenize two different Sn–Pb alloys (say 30Sn–70Pb and 70Sn–30Pb) at, say, 100jC. Below the eutectic temperature, both alloys consist of the same primary phases of Pb and Sn, the only difference is in the distribution of the amount of the phases. Upon annealing, no interdiffusion occurs, because the concentration of each species is the same in all phases, and perfectly stable thermodynamically. The only changes that would occur are ripening of the phases where the grains of each phase grow at the expense of smaller ones.
ELECTROMIGRATION AND THERMOMIGRATION
835
TABLE 1 Literature Values for the Activation Energy, ( DH ), and the Effective Charge, (Z*), for Some Solder and Other Materials Utilized in Microelectronics Assemblies Metal/System
DH for Diffusion
Z*
Impurities in Pb
na
Bi/Hg
na
Au in Pb Cu Au In
DH=14 Kcal/mol DH=49.5 Kcal/mol DH=35 Kcal/mol DH=19 Kcal/mol
Z*Au negative 13.5 to 15.5 at high temperature 5 to 9 at high temperature 9
Pb Sn Au and Ag in Pb Cu in Pb
f50 180 to 47 f2 (Au) f+1 (Ag) +1.1
Ni in Pb
f5
Cu in Pb Pb Ni in Sn
0.6 eV 0.56 eV ? 0.19 eV N
Ni in Pb/Sn Ni in Pb/In Ni in Pb
Ag in Pb/In
Au and Ag in Sn In and Sn
14.4–9 kcal/mol
[4,19]
Bulk Marker Motion
[6,20]
[1]
[3]
[21] Q*=+2.1 Kcal/mol In Sn/In alloy Varies strongly with solute concentration
[22] [23,24] [25] [26] [27]
Q*=0.2 eV Threshold of 4500 A/cm2 Temperature-dependent Z*
[28] [29] [30]
5 to 50
Strongly temperature and concentration dependent. Strongly affected by trace In additions Activation energy reduced with In additions, Z* temperature-dependent
[31]
<1 (Ag)
7 to 50
0.37 eV, 1.4 eV
[1]
+1 positive 36 to 67
0.5 eV Sn 1.9 eV In
0.8 eV
Ref
Pb became brittle at the anode and malleable at the cathode when solidified in a field An amalgam of Bi and Hg separated at the cathode Au redistributed towards the anode in solid Pb Bulk Marker Motion
2 (Ag) 9 (Au)
Sn in Pb/Sn and pure Sn
Sn/Pb Solder balls Eutectic Sn/Pb
Remarks
[32]
[33] Thin film, MTF saturates above f0.5 Am. High In values attributed to anomalous Z* behavior Pure Sn in Sn had a low z* increasing to a maximum at the eutectic composition Redistribution and failure with n=1.82 at Solder balls, high n (4.9–13) suggests length effect DH a strong function of j
[34]
[11]
[12] [14]
836
LLOYD ET AL.
FIG. 5 Interstitial (small black) Ni atoms in a Pb (large white) lattice (110 plane represented). Interstitial atoms diffuse easily and do not require the creation of vacancies to move.
a. Solute Fast Diffusion. Fast diffusers in Pb and Sn diffuse interstitially. There are several fast diffusers in Pb, among them Au, Ni, Cu, and a few others not as interesting to solder technology. Fast diffusion of the noble metals (Cu, Ag, Au) has also been observed in Sn. The effects of stress are usually ignored in these experiments because it is generally assumed that solvent diffusion is slow. Stress generation must be accompanied by significant mass transport, thus requiring sufficiently rapid diffusion. In reality, however, the application conditions ensure that solvent diffusion is nonnegligible. In addition, for two-phase alloys, consideration must be given to the fact that the diffusion coefficient and solubility may differ for each phase. This may produce complexities that at this time can only be resolved by experiment. Because fast-diffuser metals diffuse interstitially, the diffusion coefficient is very high and activation energy quite low, implying appreciable diffusion rates even at quite low temperatures. On the other hand, the solubility is rather low, which somewhat limits mass transport. There is, however, the added complexity that intermetallic compounds tend to form with fast-diffuser elements in Pb and Sn. It is, therefore, likely that electromigration-induced metallurgical changes could impact the reliability of a solder joint. For example, the appearance of a Au3Sn layer due to electromigration at an interface may produce cracking that could prove disastrous.
C.
Electromigration Failure in Lead (Pb)-Based Solders
1. Lead (Pb) Content Dependence Although there has been significantly more research carried out on Pb-based solders than Pb-free solders, the literature is scanty compared with other conductors such as Cu, Al, and their alloys. Lead-based solders are two-phase alloys (Fig. 6), usually combined with Sn, but sometimes alloyed with other metals depending on the specific application. In many applications, such as in microelectronics, where low melting points are desired, eutectic (63% Sn/Pb) or near-eutectic solders are used, but high-Pb (>90%Pb) solders are typically used for flip-chip solder bumps owing to their resistance to electromigration. 2. Classification Electromigration failure in Pb-alloy solders can be classified in two ways: (1) the mass transport of Pb or one of the major alloying elements in a solder alloy, such as Sn in a traditional eutectic
ELECTROMIGRATION AND THERMOMIGRATION
837
FIG. 6 Lead–tin phase diagram.
Pb–Sn alloy; (2) the electromigration of minor constituents such as ‘‘fast diffusers,’’ e.g., Cu or Ni. Both of these can be important. In the first case, electromigration of a major constituent can lead to voids or extrusions that can increase electrical resistance and produce open or short circuits [11–14]. When fast diffusing species are incorporated in the under bump metallurgy (UBM), fast diffusion can lead to the dissolution of the UBM materials, and the formation of interfacial intermetallic compounds layers that can lead to interfacial fracture, and ultimately, circuit failure [15]. Both of these failure modes have been observed. 3. Electromigration Failure in Flip Chip Solder Joints As discussed, flip-chip solder joints (Fig. 7) can be susceptible to electromigration failure because the relatively high diffusion coefficient of solder alloys enables significant diffusion at relatively
FIG. 7 Schematic depicting a typical flip-chip solder joint.
838
LLOYD ET AL.
low temperatures. In addition, the dimensions of the joints are large enough that Blech Length effects cannot preclude damage. With this in mind, it is perhaps surprising that solder bumps have proven to be so remarkably reliable. The reason for this has been attributed to the work done characterizing solder electromigration and applying this knowledge to design rules. a. Difficulties in Electromigration Testing of Solder Joints. The intrinsic low resistance of a solder joint makes testing a challenge. Examining the nature of the fracture and other characteristics of solder joints of chips removed by a tensile pull method provides important clues as to the cause of failure, as shown in Fig. 8. Failure analysis has shown that failure usually occurs from the growth of a very shallow lenticular void at the interface of the solder with the adjacent metal. The initial electrical resistance of a typical solder joint is about 10 mV. With a stress current on the order of 500 mA, the voltage drop across a joint is about 5 mV. Owing to the geometry of joining an interconnect line to a much larger solder bump, a very large change in the current density (by a factor of f50) due to current crowding occurs at the contact interface [16,17]. A void initiates at the corner where the solder bump and interconnect line intersect and propagates across the interface. A 1% change in resistance (corresponding to a change of only about 50 AV) requires that a void must span f99% of its cross-sectional area. This places great demands on the instrumentation for detection. In addition to void formation at the cathode, a very large redistribution of the components has been observed following electromigration stressing at the anode in eutectic Sn–Pb solder bumps. At 150jC, electromigration has led to a pile-up of Pb at the anode, indicating that Pb is the dominant diffusing species. The diffusion of Pb appears uphill, yet the concentration gradient of Pb exerts no driving force to the diffusion. This is because there is no chemical potential gradient as a function of composition in the alloy when the current is flowing. When eutectic Sn– Pb solder was tested at room temperature, Sn was found to be the dominant diffusing species and piles-up at the anode. Again, a large concentration redistribution occurred [18]. b. Characterization of Failure Modes. Electromigration failures in solder joints are usually multimodal in nature, with early fails associated with higher initial electrical resistances. These have commonly been attributed to pre-existing voids that formed during the chip-joining process. If pre-existing voids intersect the terminal via, the current density in the remaining solder is higher and local Joule heating can be significant. In a typical test of 0.005-in.-diameter 5Sn– 95Pb solder joints at a current of 1 A and 160jC temperature, using parts containing solder voids intentionally induced by process variations, an early failure distribution was observed with a large standard deviation (t50=146 hr, r=1.45). This compares to a more well-behaved and tighter failure distribution with failure times more than 1 order-of-magnitude later for standard (nonintentionally voided) samples where commonly r=f0.7. c. Solder Joint Failure Kinetics. For high lead solder (95Pb–5Sn), the activation energy for failure was found to be in the range of 0.6–0.8 eV, and the current density exponent was 1.8. It must be stressed that these data were obtained in a single-phase regime, so that although the results were reasonably self-consistent, it is questionable that extrapolations using these parameters can be made at room temperature with confidence (see Section 2E 3b Temperature Limitations Due to the Phase Diagram). Eutectic solder tests revealed very inconsistent results. The measured activation energy at one current density (2.25 104 A/cm2) was 0.37 eV and at a slightly higher current density (2.75 104 A/cm2), the activation energy was measured at 1.4 eV. The temperature range was between 100 and 140jC. In addition, the current exponent at 125jC varied considerably at different temperatures, ranging from f5 at 100jC to over 10 at 125jC. The best that can be said is that we do not know how to accelerate failures in eutectic solder balls based on these studies. More work needs to be carried out in this area. 4. Electromigration of Fast Diffusers In Lead Alloys Because of the commercial importance of Pb-based solders, diffusion of impurities in these alloys was been thoroughly investigated. It has also been a subject of scientific curiosity dating back more than a century, when the rapid diffusion of Au in Pb was discovered. The mechanism for fast
FIG. 8 Scanning electron micrographs (SEM) of the fracture surface of solder joints. (a) A void extends most of the way across the joint and exhibits a smooth interface typical of voids. (b) A joint that, when pulled, separated at the UBM showing the intermetallic compound formed between the Pb–Sn solder joint and the UBM. Such separations are due to poor adhesion usually caused by contamination. Bond pulls and observing the fracture surface is a convenient way to gain insight to the cause of failure of flip-chip solder joints. (Courtesy of IBM Corp.)
ELECTROMIGRATION AND THERMOMIGRATION 839
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LLOYD ET AL.
diffusion has been established by a variety of techniques to be primarily interstitial, although in some cases a combination of interstitial and substitutional diffusion has been required to account for the observations. It has also been observed that in binary systems the presence of a third element can significantly affect diffusion. In addition, if the concentration of a fast diffuser exceeds a threshold value, the diffusion kinetics change markedly. Generally, these effects occur without any appreciable effect on the diffusion of the host. Electromigration of the fast diffusers exhibit interesting and varied effects. The measured Z* of the impurities is often found to be strongly dependent, not only on temperature but on composition, varying with increased solute content or the presence of a second component (such as Sn in Pb–Sn alloys). In some cases, neither temperature nor composition was found to have an effect on electromigration behavior, while in others the temperature effect is sufficient to reverse the sign of Z* changing the direction of atomic flow of the solute from the anode to the cathode. a. Gold (Au) Behavior PURE LEAD (Pb). Gold (Au) diffusion and electromigration in pure Pb differs somewhat from Pb alloys. In pure Pb, Au movement is toward the anode, implying that momentum transfer of electrons colliding with interstitial Au atoms pushes them in the direction of electron flow. This is somewhat surprising because Pb has a small positive Hall Coefficient, which suggests that the major charge carriers are holes, not electrons. The direction of momentum exchange will depend on the sign of the mass of the charge carriers that are available to interact with the diffusing metal atoms. In metals, the charge carrier in a ‘‘hole’’ conductor can alternatively, and in this case more appropriately, be considered as an electron with negative mass rather than a positive charge. As only electrons near the Fermi Surface can interact, this implies that there are more holes than electrons near the Fermi surface, where in momentum space they can interact with the Au atoms. Because holes impart momentum in the opposite direction as electrons, the expectation is that ZAu* would be positive. It has been argued, however, that the absolute value (independent of sign) of the effective mass of electrons near the Fermi Surface is much lighter than those located deeper. The Hall coefficient measures the population of electrons as a function of the sign of the charge carriers, independent of mass, whereas the electromigration Z* depends on the product of the population and the effective mass. Therefore, the results need not necessarily agree. It is believed that electromigration behavior depends on subtleties of the electronic structure that are not apparent in a simple determination of the Hall coefficient. There is a slight temperature effect, with ZAu* becoming less negative as the temperature is raised. LEAD ALLOYS. The mobility of Au is significantly reduced in Pb–Sn alloys as compared to pure Pb, as a result of the trapping of Au atoms by Sn. A binding energy of Au to Sn of f0.2 eV was measured. Little or no effect was observed on ZAu* with Sn additions. ZAu* in Pb–Sn alloys was always found to be on the order of –1, with drift being toward the anode. Experiments with Pb–In showed similar results, but the binding energy appeared somewhat higher (f0.5 eV) and again with little or no effect on ZAu*.
b. Silver (Ag) Behavior. Silver behaves quite differently than Au, despite its chemical and electronic similarity. Gold is pushed toward the anode by the conduction electrons, whereas Ag in dilute solution is pushed toward the cathode. This is true in Pb and dilute Pb–Sn alloys, but as the Sn concentration is increased beyond 12%, the direction of migration reverses toward the anode. The absolute value of ZAg* is always observed to be on the order of 1 or less, either positive or negative. In Pb–In alloys, ZAg* was observed to decrease with the addition of In, but a reversal was not observed. Also, in contrast to Au, the mobility of Ag increased with the addition of Sn as well as In. The increased diffusivity of Ag with the addition of In is remarkable, being over 60 times greater at 200jC for a 30% In alloy compared to pure Pb. The activation energy for diffusion also decreased from 0.63 to 0.38 eV as the In content was increased from 0% to 45%. c. Copper (Cu) Behavior. Copper (the third member of the noble family) behavior in Pb was found to be different from both Au and Ag. Like Ag, ZCu* was positive, toward the cathode, (f+1), but unlike either Au or Ag, there was no measurable temperature effect. Copper exhibits
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the fastest diffusion rate among the noble metals in Pb, and also the lowest solubility (only a few ppm at test temperatures). In both Pb–Sn and Pb–In, ZCu* remains essentially unchanged with increases in the alloying element. The mobility of Cu decreases sharply with increasing Sn or In concentration. A binding energy of Cu with Sn is estimated at 0.3 eV, which is greater than Au. The behavior with In was curious, decreasing initially, but increasing at In concentrations above 7%. d. Nickel (Ni) Behavior PURE LEAD (Pb). Nickel, in pure Pb, was observed to migrate toward the anode, but ZNi* values were substantially higher than any of the noble metals. In addition, there was a marked increase in ZNi* at low temperatures with increasing Ni from 0.1 to 3 ppm. Pb–Sn AND Pb–IN ALLOYS. Similar to its behavior in pure Pb, Ni electromigration in Pb alloys was anode-directed. Correspondingly, ZNi* was found to be much higher at lower temperatures than at high temperatures, with the absolute values at least 1 order-of-magnitude larger for the noble metals. The behavior of Ni with additions of Sn or In to the Pb matrix was observed to be very different. Sn additions reduced ZNi*, whereas In additions increased ZNi*. In Pb–In and Pb–Sn alloys, In and Sn were observed to considerably decrease the diffusivity of Ni. The addition of 3% In reduced the diffusion coefficient by a factor of 3 near the melting temperature, but near room temperature DNi was reduced by about a factor of 500. This implies an estimated binding energy of Ni with In of approximately 1.1 eV. The behavior was similar in Pb–Sn alloys; DNi was reduced and activation energy increased with increasing Sn content. The Ni-to-Sn binding energy was estimated at 1.25 eV. It has been suggested that failure in eutectic Sn–Pb alloys is attributable to Ni electromigration and electromigration-induced dissolution of intermetallic compounds at interfaces. e. Summary of Fast Diffusers in Pb and Pb Alloys. Noble metals exhibit rather weak electromigration characteristics (Z*f1) in Pb alloys and can be directed either toward the anode or the cathode. Nickel (Ni), a transition metal, appears to be more susceptible to electromigration than the noble metals, exhibiting a higher value of Z*. In all cases, the diffusion rates are exceedingly fast—several orders of magnitude greater than the host metal—but the solubilities are all quite small. Additionally, all of the fast diffusers form intermetallic compounds with Pb or Sn, and the possibility of electromigration-induced interfacial problems cannot be discounted. The low solubility is more than compensated by the very high diffusion rates in defining the mass flux of the mobile components in solder interconnections.
D.
Electromigration in Tin (Sn)-Based Lead-Free Alloys
1. Comparison to Lead (Pb) Although electromigration data related to Pb-free solders is sparse in the published literature, it is well known that Sn acts very much like Pb as a host for fast diffusers. The same metals that diffuse rapidly in Pb alloys also diffuse rapidly in Sn, and exhibit many of the same types of behavior. The differences are important, and they reside in the details. One important difference is that unlike Pb, Sn does not possess a cubic crystal structure so the important material properties are anisotropic. Metallic Sn is body centered tetragonal (BCT), whereas Pb is face centered cubic (FCC). For example, in Pb the diffusion coefficient is independent of the orientation, but in Sn there are marked diffusion rate differences parallel and perpendicular to the basal plane. This is true for self-diffusion as well, but nowhere is it more evident than in fast diffuser behavior where the ratio of the diffusion coefficient typically varies by a factor of 30–40 at 200jC. 2. Electromigration Testing of Sn-Based Solder Joints Tin-based eutectic solders such as eutectic Sn–Cu, Sn–Ag, and Sn–Ag–Cu solders consist of Sn and intermetallic compounds. For example, in the eutectic Sn–Cu solder, Sn is in equilibrium with Cu6Sn5 below the eutectic temperature. In other words, there is no chemical potential difference between them. When eutectic Sn–Cu solder is in contact with Cu as part of a chip’s
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under bump metallurgy (UBM), a very large amount of Cu can be dissolved into the solder, driven to anode under electromigration conditions, and form Cu6Sn5 near the anode. Effectively there is no solubility limit of Cu in the solder. Yet, it is the same eutectic effect as discussed for the eutectic Sn–Pb solder that allows the dissolution of UBM to occur in electromigration. The same is true for the dissolution of a Ni layer in a UBM by Pb-free solders [15]. 3. Electromigration of Fast Diffusers in Sn and Sn-Based Alloys a. Silver (Ag) and Gold (Au) Behavior. Because of the effects of the anisotropic structure, electromigration studies for fast diffusers in Sn have been performed with single crystals. Silver electromigration parallel to the basal plane was observed to exhibit a ZAg* of about –2 independent of temperature. Gold exhibited a ZAu* of approximately 9, and is also insensitive to temperature. However, ZAu* perpendicular to the basal plane was observed to be about half this value. b. Nickel (Ni). The most interesting fast diffuser in tin is nickel. Perpendicular to the basal plane, Ni diffusion in Sn was found to be fast but with an activation energy of 0.5 eV, it is not much different than the other fast diffusers. However, parallel to the basal plane, Ni diffuses extraordinarily fast, with extremely low activation energy of less than 0.2 eV. In fact, the solid state diffusion of Ni in Sn at 100jC is actually faster than diffusion of the noble metals in liquid Sn at more than 232jC. The anisotropy in the diffusion coefficient, D, stated as a ratio of diffusion parallel and perpendicular to the basal plane, is more than 100,000 at 120jC, the greatest directional difference known. Nickel electromigration in Sn, similar to the case in Pb, is unusually high. ZNi* perpendicular to the basal plane was –36 at 203jC, rising to –67 at 166jC. These are not only very high Z* values, but the temperature dependence is remarkable. The fast diffusion of Ni in Sn and the unusually high value for ZNi* could conceivably be responsible for reliability problems. c. Reliability Implications of Fast Diffusers. As solder ball connections become smaller and they are required to carry higher current densities, the reliability implications of fast diffuser electromigration leading to a supersaturation of a mobile solute and subsequent intermetallic compound formation at flux divergence interfaces cannot be ruled out. The presence of a brittle, highly stressed, highly electrically resistive intermetallic compound layer where it is not planned may be deleterious to performance. In one case where Sn was sandwiched between Cu terminals, CuSn intermetallic compounds (IMCs) were observed to grow asymmetrically with the application of DC. Copper rapidly diffused through the Sn in the direction of electron flow. The growth of the downstream IMC layer varied as t1/2, suggesting that the rate-limiting process was the diffusion of Cu through the concurrently growing upstream IMC layer. The diffusion of Cu through the Sn was so rapid that it could almost be considered instantaneous. Such behavior must be considered in evaluating Sn solder terminated by Cu conductors [18].
E.
Electromigration Testing
1. Accelerated Testing To evaluate the reliability of any system, testing must be performed to produce results in a relatively short time but which must be quantitatively related to performance under operational conditions. To achieve this, test structures are subjected to conditions more severe than those expected under field conditions. In the case of electromigration, this means that testing must be performed at higher temperatures and current densities than anticipated in real applications. This is called accelerated testing. a. Limits to Accelerated Testing. For accelerated testing to be effective, the results must be related to field conditions by failure models developed from a detailed understanding of the physical processes. There are limitations as to the degree of acceleration that can be attained in a test. It is essential that the same physical processes and mechanisms operate at both the accelerated and operational use conditions. If the test stress conditions are too severe, introducing
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a change in the physical failure mechanisms from the operational use condition, the results cannot be used for evaluations. This is referred to as overstressing. There are limitations on both temperature and current density that must be recognized. 2. Overstressing Electromigration testing can be compromised by both overstressing and poor test structure design. To obtain test results in experimentally convenient time frames, accelerated testing must be performed. In these tests, stress conditions are chosen to be more severe than field conditions, and the test results are extrapolated (‘‘decelerated’’) to represent the expected performance in operation. Overstressing occurs when the test conditions are such that the results cannot be decelerated. This occurs if the choice of conditions excites failure modes that will not occur under normal operation. 3. Temperature Effects a. Temperature Limitations Due to Diffusion. The most common source of overstressing is the use of excessive temperature. Because diffusion is thermally activated, high temperatures produce a rapid rate of degradation. There is, therefore, a strong incentive to raise temperature in order to obtain results in a shorter time. In most materials, the major diffusion pathway is temperature-dependent. Because microstructural features (grain boundaries, lattice, or other interfaces) determine diffusion, the major diffusion pathway can be different at higher temperatures than at lower temperatures. For bulk metallic specimens, the critical temperature above which the major diffusion pathway changes, is generally about half the melting temperature on an absolute scale. For example, for Sn (Tmp=232jC=505 K), half the melting point is below room temperature. Therefore the crossover temperature where the major diffusion pathway changes from grain boundary to lattice diffusion is not an issue with Sn. The same diffusion mechanisms operate at both the testing and the operational conditions. b. Temperature Limitations Due to the Phase Diagram. For other lead-free alloys, however, the phase diagram must be carefully studied. The equilibrium phase distribution and the composition of the constituent phases must be similar at both the test and use conditions. The effect is apparent in the Pb–Sn system shown in Fig. 1. HIGH Pb CONTENT ALLOY EXAMPLE. Consider a 95 Pb–5Sn alloy. Above f100jC, the tinrich h phase disappears, thus, any results obtained at a temperature above 100jC are essentially invalid for extrapolation to lower temperatures. Note also that even at 50jC, the amount of a phase is significantly different than at lower temperatures. If microstructure is important, the results will vary considerably. This makes accelerated testing of high-Pb alloys problematic for this alloy. For use at room temperature, the maximum testing temperature is around 80jC. For use at conditions approaching 100jC, it can be argued that accelerated testing cannot be reliably performed. For use above 100jC, however, testing can be performed up to nearly 300jC. EXAMPLE: EUTECTIC ALLOY EXAMPLE. For eutectic compositions and above (to f95% Sn), however, there is little difference in the equilibrium microstructure compared to field conditions even above 150jC. The maximum test temperature based on the phase diagram could approach the eutectic temperature. c. Current Density Limitations. Along with temperature, the current density must also be limited for valid electromigration testing. There are two major reasons to limit current density, Joule heating and the Blech Length effect. JOULE HEATING AND TEMPERATURE GRADIENTS. Attendant with high current density is Joule heating. The problems associated with Joule heating in electromigration testing are that the temperature must be maintained below a level where invalid mass transport mechanisms operate, such as lattice transport, which is not significant at low operational temperatures. More importantly, Joule heating can cause temperature gradients. As diffusion is thermally activated, a temperature gradient can cause a flux divergence. The geometry of solder connections generally makes this an unimportant effect. A temperature gradient, however, can
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produce a driving force similar to electromigration called thermomigration or the Soret effect (see Section III of this chapter.) The driving force for diffusion in the Soret effect is the temperature gradient itself and in solders this is more important than with most other materials. Temperature differentials over the dimensions of a solder joint of only a few degrees can produce thermomigration. Therefore, the current density should be limited to assure that Joule heating is very small, less than a few degrees. BLECH LENGTH EFFECTS. This is a subtle effect that is perhaps more important than has been previously considered. When a metal is subjected to direct current with blocking boundary conditions, a stress gradient is produced that provides a mass transport driving force which opposes the electromigration flow reflected in Eq. (9). If operational currents are sufficiently low, a stress gradient will be generated that can stop electromigration flow and preclude failure due to electromigration. In an effort to shorten the times to failure during testing, it is tempting to increase the current density. However, care must be taken not to increase the current density so much that the Blech threshold is exceeded, because then the projection to the field condition cannot be made. The test will be invalid and the results unduly pessimistic (see Section II.A.3).
III.
THERMOMIGRATION
A.
Theory of Thermomigration
Thermomigration, also known as the Soret or Ludwig–Soret Effect, is mass transport in response to a driving force resulting from a temperature gradient. It is one of the driving forces noted in Eq. (5), usually represented as, Q* jT ð12Þ T where Q* is the ‘‘heat of transport’’ and T is temperature. The physical basis behind thermomigration is not well established. The most accepted theory is closely related to electromigration in that the force acting on the diffusing atoms is the momentum exchange from the collisions of diffusing atoms and conduction electrons. In this case when there is no current flowing, the force in the direction of the temperature gradient results from the fact that the energy and, therefore the momentum, of the electrons at higher temperatures is greater than at lower temperatures. The gradient in the momentum exchange produces a driving force for mass transport. Based on this argument, Q* for metals with high electromigration Z* values should also correspondingly be high. Here again, the sign of Q* can be positive or negative depending on the effective mass of the charge carriers. In most solids, Q* is rather small, and thermomigration is generally a negligible effect. In some liquids it can be significant, but because convection usually precludes the observation, it is rarely observed on earth. As such, investigation of the Soret effect has been a popular topic of study in space where gravity does not have a role and there is no convection. In solder metals (Pb, Sn, In) that are especially susceptible to electromigration, thermomigration is a real concern as well. Therefore, it must be carefully considered when investigating the reliability of solders. FTM ¼
1. Threshold Effects To evaluate the effect of temperature gradients on the failure of solder joints, one must keep in mind that the governing physics is described by Eq. (5). All driving forces are always acting. Therefore, the Soret effect is difficult to separate from other effects such as electromigration and/ or stress migration. In addition, the presence of the other driving forces can produce various effects, such as the appearance of threshold effects. For instance, in one experiment, when the temperature difference across Pb–In solder balls was varied, failure did not occur unless the temperature difference exceeded 8.5jC. If the temperature difference was less than this, the joint essentially remained unaffected.
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The reason for this is most probably the presence of competing driving forces during the experiment similar to an electromigration test, as material diffuses in response to the driving forces, a stress gradient develops opposing the mass flow, provided there are sufficient fluxdivergent forces. For example, the force generated in the presence of a temperature and stress gradient is, F ¼ Q*
d ln T dr X dx dx
ð13Þ
As both components of the driving force in Eq. (13) depend on gradients, the threshold temperature difference for thermomigration is
DT X ¼ exp ðr1 r2 Þ 1 ð14Þ T Q* where r1 and r2 are the maximum hydrostatic stresses that the material can sustain at each end of the thermal conductor. Note that r2 will, in general, be of opposite sign to r1, and that the quantity in the exponent is defined to always be positive. Eq. (14) suggests that the threshold temperature difference is a function of temperature, being larger at lower temperatures. It also suggests that encapsulation of the solder joint in a rigid material would increase the threshold by increasing the allowed values of the maximum stress before failure. If the threshold is exceeded, the net mass flow would be expressed by including Eq. (13) into the Einstein equation (1) modified for mass flux, J¼
DFC DC d ln T dr X ¼ Q* kT kT dx dx
ð15Þ
Also, thermomigration may be rapid if the threshold is exceeded, because the second term in Eq. (15) is limited by the stress at the boundaries. If the surface is free, as occurs when a void forms, the hydrostatic stress vanishes and with it the restraint on thermomigration is significantly reduced or eliminated altogether, depending on the state of the opposite boundary. Needless to say, the situation can become complicated and confusing, and results obtained from experiments where the boundary conditions differ significantly from those under operational conditions must be carefully considered. 2. Thermomigration of Solutes a. Interstitial Solutes. Consider the case of an interstitial solute diffusing rapidly in an immobile matrix. Representative of this situation is a fast diffuser (such as Cu that has been investigated) in Pb. The relevant driving forces can be extracted from Eq. (5). For an immobile matrix and an interstitial solute, the stress gradient term can be neglected so the driving force is, F ¼ Q*
d ln T d ln C kT dx dx
ð16Þ
which predicts there should be a solute concentration profile that is directly proportional to the temperature profile at steady state. Using this concept, the Q* for Cu in Pb was estimated to be f0.2 eV. The consequences of this can be important in practical applications. Paradoxically, many of the fast diffusers have very small solubilities in the host metal, and are therefore commonly used as underlay materials and even diffusion barriers. If a temperature gradient is established, the solute will be subject to a driving force for diffusion that may over time transfer significant amounts of barrier material across the temperature gradient. Threshold effects could also be present with boundary conditions determined by the equilibrium concentration of solute in the host metal in contact with the solute containing species at each side of the temperature gradient. Note the equilibrium concentration at the
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boundaries may be a strong function of temperature. If the threshold is exceeded, the solute mass transport is expressed as, J¼
DFC DC d ln T d ln C CQ dT dC kT ¼ Q* ¼D kT kT dx dx k2T dx dx
ð17Þ
In many cases, the diffusion coefficient for interstitial solutes is very rapid. Even if the solubility is very low, the extremely high diffusivity results in substantial mass transport. A case in point is Ni in Sn, which may have important engineering consequences because Ni is often used as a barrier metal. The diffusivity of Ni in Sn is the fastest solid diffusion known, even faster than diffusion in the liquid at the melting temperature. The solubility is almost vanishingly small, but the speed with which it moves through Sn suggests it is an important consideration in real systems. b. Substitutional Solutes. Thermomigration of interstitial solutes represents a much simpler process than for substitutional solutes. The major simplifying assumption of no stress gradients being induced, in general cannot be made for substitutional solutes. In addition, the approximation of a stationary host is not valid. Substitutional solutes diffuse via a vacancy mechanism just like the host. Therefore, if the solute is exhibiting significant mobility, so is the host metal. The driving force on the diffusing atom in the presence of stress effects becomes F ¼ Q*
d ln T d ln C dr kT X dx dx dx
ð18Þ
The addition of the stress gradient term in the driving force significantly complicates the analysis. If electromigration is included, the problem becomes effectively intractable theoretically and can only be studied experimentally.
FIG. 9 Solder joint resistance over time for several thermal gradients created by varying test chip power dissipation and substrate temperature. (Courtesy of IBM Corp.)
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FIG. 10 The resistance change of Pb–In flip chip solder joints over time for a chip dissipating 3 W of power and at 150jC. (Courtesy of IBM Corp.)
FIG. 11 Resistance change in Pb–45In flip chip solder joints at a constant average temperature of 120jC and constant power of 2.3 W for several varying current levels that show the effect of current flow on electromigration. Note that with no current flowing, there is still a finite lifetime.
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3. Thermomigration in Pb–In Alloy Solder Joints The Pb–In alloy system has received some attention with respect to thermomigration. At one time, Pb–In alloys showed some promise as a substitute for Pb–Sn alloys in flip-chip solder bump applications, because of favorable mechanical and fatigue properties. The reason this alloy system was not adopted for high-performance applications was the discovery its very poor resistance to thermomigration damage. A review of this work is instructive for future studies in Pb-free solder. a. Experimental Procedure. To produce a temperature gradient across the solder joints, heat was generated in a specially designed ‘‘thermal’’ chip consisting of an array of resistors that maintained the temperature of the chip to be above the substrate by a fixed amount that depends on the power dissipated in the resistor network. Therefore, the average temperature could be varied by the temperature of the oven, and the peak temperature and the temperature gradient could be varied by the power dissipated by the test. The temperature of the test chip was determined by a 4-point resistance measurement of a calibrated resistor. A similar resistor was incorporated into a matching test substrate. A 50Pb–50In solder was investigated. The solder bump connection tested was 125 Am wide and 75 Am tall. The temperature gradient established was over the 75-Am dimension. The average substrate temperature was 100, 150, and 175jC, and by dissipating 2.3, 3.8, and 6 W, temperature gradients of 10, 12, and 16jC, respectively were realized. The effect of the thermal gradients on the average resistance change of flip-chip solder joints is shown in Fig. 9. b. Experimental Results. The resistance change (DR) of the solder joints was found to follow the empirical relation (Fig. 10) pffiffi DR ¼ R0 exp a t
ð19Þ
FIG. 12 Thermomigration induced resistance increase for Pb–In and Pb–Sn alloy flip chip solder joints. Pb–In is clearly inferior to Pb–Sn under similar conditions. (Courtesy of IBM Corp.)
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with R0=0.12 mV and a=0.02 (hr)0.5 for 3 W and 150jC average temperature. An isothermal control experiment was performed with no change in resistance observed. Subsequent failure analysis showed that solder joints that did not carry current were damaged as well as those carrying current, although those carrying direct current were somewhat more damaged, depending on the direction of current flow. This suggests that although electromigration played a role, it was not necessary for damage to occur, as noted in Fig. 11. Mass transport was in the direction from the hot to the cold side of the solder joints. The damage was observed to consist of shallow lenticular voids at the interface between the solder joint and the adjacent conducting metallurgy. Resistance increases were only measurable when the voids very nearly spanned the width of the terminal via connecting the solder joint to the underlying metallurgy. The failure times were fit to the empirical relationship;
DH ð20Þ tf ¼ Pn exp kþT where P is the power dissipated in the chip resistors and T is the average temperature across the solder joint. Failure was defined as an increase of resistance of 5 mV. The activation energy, DH, was found to be 0.5 eV and n was determined to have a value of about 2. c. Implications. Although Pb–In alloys were found to be superior to Pb–Sn alloys in terms of resistance to thermal cycling and mechanical fatigue, the susceptibility to thermomigration was significantly worse than Pb–Sn. For example, under equal stress conditions, a 45In–55Pb exhibited an average 5 mV resistance increase in f100 hr, whereas the worst observed resistance increase of 24 samples had not reached the failure criterion in over 3000 hr, as shown in Fig. 12. This increased sensitivity to failure made it inadvisable to implement this solder bump composition for high-performance applications, where significant heat is typically generated in the chip. d. Reversal of Thermal Gradient. In another experiment, the temperature gradient was reversed by turning off the power to the test chip and heating the substrate with a laser such that the temperature difference was identical to when the thermal chip was powered. The resistance of the solder joint was measured throughout the experiment. The resistance increase that was experienced when the thermal chip was hottest was seen to recover in comparable times when the substrate was hottest. This was conclusive evidence of the effect of thermomigration in solder joint reliability.
ACKNOWLEDGMENTS One of the authors (J.R.L.) would like to acknowledge the help and contributions of D. Gupta, K. Puttlitz, and R. Rosenberg of IBM Corporation, and to M. Sullivan and L. Kisselgof, formerly of IBM.
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Gerardin, M. De l’action de la pile sur les sels de potasse st de soude st sur les alliages soumis a` la fusion inge´e. Comptes Rendes 1861, 53, 727–730. Skaupy, F. Elektrizita¨tsleitung und Konstitution flu¨ssiger Metalle und Legeirungen. Physik. Zeitschr. 1920, 21, 597–601. Seith, W.; Etzold, H. U¨ber die Beweglichkeit von Gold in Festem Blei. Zeitschr. Elektrochem. 1934, 40, 829–832. Wever, H. U¨berfu¨hrungsversuche an Festem Kupfer. Zeitschr. Elektrochem. 1956, 60, 1170–1175. Fiks, V.B. On the mechanism of the mobility of ions in metals. Sov. Phys. Solid State 1959, 1, 14–28. Huntington, H.B.; Grone, A.R. Current-induced marker motion in gold wires. J. Phys. Chem. Solids 1961, 20, 76–87. Blech, I.A.; Kinsbron, E. Electromigration in thin gold films on molybdenum surfaces. Thin Solid Films 1975, 25, 327–334.
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Blech, I.A. Electromigration in thin aluminum films on titanium nitride. J. Appl. Phys. 1976, 47, 1203– 1208. 9. Blech, I.A.; Herring, C. Stress generation by electromigration. Appl. Phys. Lett. 1976, 29, 131–133. 10. Ding, M.; Matsuhashi, H.; Ho, P.S.; Marathe, A.; Master, R.; Pham, V. Wheatstone Bridge method for electromigration study of solder balls. Proc. 41st Ann Int’l. Reliab. Phys. Symp.; Dallas, TX, 30 Mar–4 Apr, 2003; 442–446. 11. Liu, C.T.; Chen, C.; Tu, K.N. Electromigration in Sn–Pb solder strips as a function of alloy composition. J. Appl. Phys. 2000, 88, 5703–5709. 12. Brandendburg, S.; Yeh, S. Proceedings of the Surface Mount International Conference and Exposition; San Jose, CA, 1998; 337–344. 13. Lee, T.Y.; Tu, K.N.; Kuo, S.M.; Frear, D.R. Electromigration of eutectic SnPb solder interconnects for flip chip technology. J. Appl. Phys. 2000, 89, 3189–3194. 14. Huynh, Q.T.; Liu, C.Y.; Chen, Chih; Tu, K.N. Electromigration in eutectic SnPb solder lines. J. Appl. Phys. 2000, 89, 4332–4335. 15. Lee, T.Y.; Tu, K.N.; Frear, D.R. Electromigration of eutectic SnPb and SnAg3.8Cu0.7 flip chip solder bumps and under-bump metallization. J. Appl. Phys. 2001, 90, 4502–4508. 16. Yeh, E.C.C.; Choi, W.J.; Tu, K.N. Current-crowding-induced electromigration failure in flip chip solder joints. Appl. Phys. Lett. 2002, 80, 580–582. 17. Jang, S.Y.; Wolf, J.; Kwon, W.S.; Paik, K.W. UBM (under bump metallization) study for pb-free electroplating bumping: interface reaction and electromigration. Proceedings of 52nd Electronic Components & Technology Conference, San Diego, CA, 2002, 1213–1230. 18. Gu Xu, M. Sc. thesis, UCLA, 2001. 19. Grone, A.R. Current-induced marker motion in copper. J. Phys. Chem. Solids 1961, 20, 88–93. 20. Gilder, H.M.; Lazarus, D. Effect of high electronic current density on the motion of Au195 and Sb125 in gold. Phys. Rev. 1966, 145, 507–518. 21. Lodding, A. Current induced motion of lattice effects in indium metal. J. Phys. Chem. Solids 1965, 26, 143–151. 22. Thernqvist, P.; Lodding, A. Self-transport in polycrystalline Zn and Pb. Z. Naturforsch. 1966, 21a, 1310–1311. 23. Ohring, M.; Sun, P.H. Void marker motion during electromigration in Sn–In thin films. Thin Solid Films 1971, 8, 455–464. 24. Tai, K.L.; Sun, P.H.; Ohring, M. Lateral self-diffusion and electromigration in thin metal films. Thin Solid Films 1975, 25, 343–352. 25. Hsieh, M.Y.; Huntington, H.B; Jeffery, R.N. Cryst. Lattice Defects 1977, 7, 9. 26. Hsieh, M.Y.; Huntington, H.B. Electromigration of copper in lead. J. Phys. Chem. Solids 1978, 39, 867–871. 27. Golopenta, D.A.; Huntington, H.B. A study of electromigration of nickel in lead. J. Phys. Chem. Solids 1978, 39, 975–984. 28. Stracke, E.; Herzig, Ch. Phys. Status Solidi, A Appl. Res. 1978, 47, 513. 29. DiGiacomo, G. Electromigration depletions in Pb–Sn films. Proc. 17th Ann Int’l Reliab. Phys. Symp.; San Francisco, CA, April 24–26, 1979; 72–76. 30. Yeh, D.C.; Huntington, H.B. Extreme fast-diffusion system: nickel in single-crystal tin. Phys. Rev. Lett. 1984, 53, 1469–1472. 31. Mei, S.; Shi, J.; Huntington, H.B. Diffusion and electromigration in lead alloys. I. Nickel as a mobile element. J. Appl. Phys. 1987, 62, 444–450. 32. Shi, J.; Mei, S.; Huntington, H.B. Diffusion and electromigration in lead alloys. II. Ag, Au, and Cu in lead–indium. J. Appl. Phys. 1987, 62, 451–455. 33. Shi, J.; Huntington, H.B. Electromigration of gold and silver in single crystal tin. J. Phys. Chem. Solids 1987, 48, 693–696. 34. Gilde, R.; van Daal, H.J.; Brongersma, H.H Electromigration and coagulation in thin films of pure indium and pure tin. Phys. Status Solidi A, Appl. Res. 1988, 105, 493–499.
21 The Structure and Kinetics of Tin-Whisker Formation and Growth on High Tin Content Finishes W. J. Choi Intel Corporation, Pheonix, Arizona, U.S.A.
George Galyon IBM Corporation, Poughkeepsie, New York, U.S.A.
King-Ning Tu University of California at Los Angeles, Los Angeles, California, U.S.A.
T. Y. Lee Hanbat National University, Taejon, South Korea
I.
INTRODUCTION
Metallic whiskers are single crystal eruptions from a metal surface, typically 1–5 Am in diameter and 1–500 Am in length Fig. 1. Whiskers can be straight, kinked, and even curved [1]. Almost always, the whiskers erupt (grow) from metallic films that are electroplated on a substrate material. Metallic-film deposits also demonstrate other types of eruptions that are quite different in appearance from whiskers. These eruptions are referred to as flowers, mounds, extrusions, volcanoes, etc. and have not been as interesting as the considerably longer whisker eruptions (Figs. 2–4). Most, if not all, nonnoble metals grow whiskers under the correct conditions, but the lower-melting-point metals of tin (Sn), zinc (Zn), and cadmium (Cd), along with silver (Ag) in the presence of hydrogen sulfide (H2S) grow whiskers under ambient, or near-ambient conditions. This is a source of concern because of their widespread utilization in electronic hardware applications where whisker growth has caused significant reliability problems. The greatest interest has been focused on Sn, because Sn platings are widely used in electrical hardware on closely spaced lead frames and circuit-board features, where whiskers can readily short one lead or feature to another. Zinc is also of interest because electroplated Zn is a common surface finish on sheet steel used for the underside of raised-floor panels in computer rooms. Cadmium was of interest during, and shortly after, World War II when it was the metal plating of choice for electrical hardware. During the 1950s, Cd was quickly replaced by Sn and lead (Pb)–tin (Sn) alloy
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FIG. 1 A scanning electron microscope (SEM) image of a bright-tin whisker. (Courtesy of G. Galyon and L. Palmer, IBM Corporation.)
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FIG. 2 SEM of a bright-tin surface extrusion or flower. (Courtesy of G. Galyon and L. Palmer, IBM Corporation.)
platings. Silver is used in some electronic applications because of its combined properties of low contact resistance and good solderability. But by far, the greatest number of technical publications have dealt with the problems associated with whisker formation in Sn and Sn alloys.
A.
Background
There has recently been a renewed interest in Sn whiskers because of the worldwide conversion to Pb-free solders and finishes in electronic manufacturing. Finishes are applied to printed circuit boards (PCBs) and to the lead frames used to connect device packages to printed circuit boards. Lead frames are typically made of a copper (Cu) or iron–nickel (FeNi) alloy plated with a Sn–Pb alloy. Fig. 5 is a schematic diagram of a lead frame cross section bonded to a chip-carrier package. The surface finish of the lead-frame leg is designed to provide surface passivation and enhanced solderability. Typical Pb-free surface finishes are eutectic Sn–Cu or pure Sn. Tin(Sn) whiskers readily grow on high-Sn content finishes under certain conditions.
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FIG. 3 SEM micrograph of a bright-tin surface mound structure. (Courtesy of G. Galyon and L. Palmer, IBM Corporation.)
B.
Whisker Description
Whiskers can be of sufficient length (>125 Am) to cause an electrical short between two legs of a lead frame, as shown in Fig. 6(a). An enlarged scanning electronic microscope (SEM) image of a long whisker on a Sn–Cu finish is shown in Fig. 6(b). The whisker in Fig. 6(b) is about 3 Am in diameter and more than 200 Am in length. It has a straight, fluted surface similar to the grooved columns in some classical buildings. The root of the whisker is shown in the SEM image of Fig. 6(c). The top surface (i.e., the tip of the whisker) of this particular whisker is rough and similar in appearance to the surface of the finish. Many whiskers are kinked at sharp angles, as shown in Fig. 6(d). Short (f10 Am) whiskers on pure Sn finishes are shown in Fig. 7(a) and (b). The surfaces of the whiskers in Fig. 7(b) and (b) are faceted but not fluted, and their diameter is similar to
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FIG. 4 SEM micrograph of a bright-tin surface nodule or bud. (Courtesy of G. Galyon and L. Palmer, IBM Corporation.)
the grain size (3–5 Am) of the Sn matrix. The top surface of these short whiskers is flat. Clearly, the morphology of the whiskers grown on Sn–Cu and pure Sn Figs. 6 and 7, respectively) is different.
C.
Overview of Tin Whisker Studies
Any risk-assessment decision on electroplated Sn usage is hampered by the lack of scientific consensus on the growth mechanism involved in whisker formation. Experimental results are notoriously unpredictable and nonrepeatable. Whiskers may appear within days after electrodeposition or they may not appear for years. This delay in appearance, or incubation period, makes the study of whisker growth a frustrating laboratory endeavor. It has also been
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FIG. 5 Schematic diagram of the cross section of a lead frame on an electronic component mounted on a board. (From Ref. 47.)
frustratingly difficult to examine the physical structure of as-deposited electroplated films because of their small thickness and relative softness. As a result, there have been few published attempts to examine the metallurgical aspects (microstructure) of electroplated-Sn films. Experimental investigations are further hampered by the lack of a standard acceleration test that can be utilized to certify a plating process as whisker-free. Perhaps, the greatest variable is the electroplating process itself. Seemingly similar processes can produce sequential runs of electroplated films with
FIG. 6 SEM images of Sn whiskers grown on eutectic Sn–Cu finish on a lead frame. (a) A whisker creates an electrical short between two lead frame legs. (b) A fluted whisker on the Sn–Cu finish surface. (c) An enlarged image of the root of a whisker. (d) A few of the whiskers are bent at sharp angles. (From Ref. 42.)
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FIG. 7 SEM images of short whiskers on a pure Sn finish. The surface of the whisker is not fluted and the whisker diameter is similar to the Sn matrix grain size. (From Ref. 42)
measurably different whisker formation and growth characteristics. Nonetheless, various researchers have periodically brought new analysis tools to bear on the problem of whisker formation and growth and added new data, and occasionally new insights. Based on what is currently known, the principal facts that most Sn whisker theorists would probably agree on are listed in Table 1.
II.
TIN PLATING TYPES
There are several types of electroplated Sn, and each type exhibits different whisker behavior. The technical literature often does not define the type of Sn plating being discussed, but it is an important fact to know. Independent of the type of electrodeposited Sn, the substrate material on which the Sn is deposited has a significant effect on the formation and growth of whiskers. Much of the early work between 1950 and 1975 was on matte Sn deposited on steel, with or without an underlay material. Tin on steel tends to grow numerous whiskers of relatively long (>100 Am) lengths. Over time, Sn-whisker research extended to substrate materials of Cu and Cu alloys. In general, Sn plated onto Cu substrates has been observed to grow more whiskers than a comparable Sn film deposited on a steel substrate. Tin deposited on some Cu alloys, such as brass (CuZn), have been observed to grow even more numerous whiskers than Sn deposited on relatively pure Cu. However, substrate material affects whisker formation only in degree, not in any absolute manner. Much the same thing can be said about electrodeposition-process variables. Process variations affect whisker formation and growth in degree but cannot preclude whisker formation and growth. A brief description of the various types of Sn plate is presented in the following sections.
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TABLE 1
Summary of Whisker Attributes with a High Degree of Consensus
Assertion Statement Whiskers grow by atoms being added to the base of the whisker, not the tip. Whiskers are single crystals with growth directions parallel to dislocation glide vectors
Whisker growth is caused by the relief of internal compressive stresses.
Whisker growth rates are too fast to be explained by theories relying on bulk diffusion of Sn atoms in a Sn matrix. The two most prevalent theoretical approaches used by whisker modelers are dislocation theory and recyrstallization. A third approach involving a defective oxide concept has been postulated relatively recently.
A.
Commentary and Reference Asserted by Koonce and Arnold in 1953 [24] and never refuted Statistically true, but exceptions were noted by Ellis et al. [37] based on studies of kinks in whiskers at Bell Labs during the 1950s. The exceptions noted are critical to the critique of dislocation-based whisker growth theories A generally accepted statement. Early dislocation theories presumed that negative surface tension due to oxidation was the driving force. The clamp-pressure experiment of Fisher et al. [27] established the concept of compressive stress gradients as the driving force behind whisker growth. A generally accepted statement. All modern theories of whisker growth presume that the atoms migrate to the root of the whisker via grain boundaries or dislocation networks. Dislocation theories were first proposed in 1953 by Eshelby [26] and Frank [25]. Recrystallization was first proposed by Ellis et. al. in 1958 [37]. The cracked oxide concept was proposed by K.N. Tu in 1994 [54].
Matte Tin
A Sn plate whose appearance is relatively dull is referred to as matte Sn. A dull appearance is the result of a rough surface texture due to the relatively large (typically 5 Am or greater) grain structure of matte Sn in comparison to fine-grained (typically 1 Am or less) bright Sn. Matte Sn was the only type of Sn plating up through the mid-1960s, and all the published literature up to about 1968 was in reference to matte Sn even if it was not specifically stated to be the case. Modern matte Sn tends to have large, polygonal grains that extend through most, if not all, of the plating thickness. These large polygonal grain structures are achieved by additions of specific (and often proprietary) organic substances to the plating bath. Residual stress levels in asdeposited matte Sn depend on a number of factors, but are generally considered to be less than the residual-stress levels of comparable bright Sn films. Matte Sn does grow whiskers, but the whisker densities and lengths are generally somewhat less than those observed for comparable bright Sn finishes.
B.
Bright Tin
A Sn plating that appears relatively bright because of the high degree of reflection (low scattering) of light from the surface of the plating is referred to as bright Sn. The surface texture of bright Sn is smooth as a result of a relatively small (typically less than 1 Am) grain size. Bright Sn was developed in the mid-1960s for a number of reasons unrelated to whisker growth. The key to making bright Sn is the addition of certain organic additives to the plating bath. Residual stress levels in bright Sn are generally higher compared to matte Sn, and whisker growth is more prolific in bright Sn than matte Sn. Satin-bright Sn is a term describing an intermediate degree of
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brightness between a matte and bright Sn and the internal stress levels in satin bright tins are intended to be as close to zero as possible.
C.
Fused Tin
A fused-Sn plating is one that has been reflowed (melted and resolidified) subsequent to electroplating. Typically, an electroplated part is dipped into a hot-oil bath and held at a temperature above the melting point of Sn. The objective of the fusing operation is to allow the Sn to slowly solidify and, thereby, remove any internal stresses that may have resulted from the electrodeposition process. Fused Sn is reputed to not grow whiskers unless the surface of the tin is scratched, compressively stressed, or plastically deformed [2].
D.
Immersion Tin
Immersion Sn is an electroless-plating process. It is a slow process compared to electroplated Sn and is not used to plate lead frames. It is believed that immersion Sn has never been the focus of a published Sn whisker study, probably because there have never been any reported incidents of Sn-whisker growth on immersion Sn finishes [3–5]. Immersion Sn is used when it is necessary to obtain good edge coverage for purposes of corrosion protection as electroplated films do not provide good edge coverage. Copper heat sinks are occasionally immersion-Sn plated, as are printed-circuit boards (PCBs). Immersion-Sn coatings are considered to be a low-stress plating in comparison to electroplated Sn. Unlike electroplating, where the current and potential is supplied by an external source and the plating follows Faraday’s Law, electroless (or immersion) plating amounts to an exchange of one ion in the plating bath for one atom on the surface of the material being plated. This is a self-limiting process in that, when all the surface atoms have been exchanged, an equilibrium is established with the plating bath and the reaction ceases. It must also be noted that immersion Sn films can be made extremely thin (<1 Am) in comparison to electroplated films (typically >>1 Am), and this may have been a key factor in the reputed inability of immersion Sn films to form whisker structures. These very thin immersion-tin films may be completely consumed by the formation of intermetallics at the substrate/film interface. As a result, there may be little or no unconsumed Sn available for whisker formation. However, the absence of whisker formation on immersion-tin films is contradicted by the reported observations by one of the authors who found 10-Am whiskers forming within 30 days of depositing a 0.6-Am-thick immersion-tin layer [6]. It is thought to be unlikely that such a thin film has the capacity to grow whiskers to lengths over 50 Am. Such short whiskers are probably not a problem in most electrical component applications, but the assertion that immersion tin is fundamentally not capable of growing whiskers is in error. Expert advice is recommended for all immersion Sn film applications.
E.
Tin with an Underlay
Underlays are electroplates of another metal deposited before (underneath) a Sn film. The most common underplate is nickel (Ni), but some studies have been carried out with other underplate materials. An underplate has many purposes, one of which is to retard, and hopefully eliminate, whisker formation and growth [7]. Nickel appears to change the state of stress within a Sn film on a Cu substrate from a compressive to a tensile state, and it forms a different intermetallic compound (Ni3Sn) with the Sn plate [8]. Nickel also acts as a diffusion barrier between a Cu substrate and a Sn plating. A typical Ni-underlay thickness ranges between 1 and 2.5 Am, although there has been some work carried out with thinner films. Nickel diffuses into a Sn plating at a slower rate than does the Sn into Ni. This is in contrast to the very rapid diffusion of Cu into Sn compared to the diffusion rate of Sn into Cu. Thus, it is logical to presume that the addition of Cu to a Sn plated film will cause a compressive stress state, whereas the diffusion of Sn into Ni will result in a Sn film that is tensile.
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An alloy is a material consisting of two more elements, the majority constituent being a metal. Some electroplated-Sn alloys have been shown to retard whisker formation, such as Sn–Pb [9], and some have been shown to accelerate whisker formation, most notably Cu, Fe, and Zn [10].
III.
TIN WHISKER RELIABILITY PROBLEMS
Whisker reliability problems were first noted on cadmium (Cd)-plated filters during World War II [11]. In 1948, the Bell Telephone System experienced whisker problems on cadmium-plated filters and initiated a program investigating metallic-whisker growth that was first reported in the technical literature in 1951 [12]. By 1956, Bell Laboratories had developed and published whisker mitigation strategies [1,2,9]. Nevertheless, Sn-whisker problems continued to proliferate and be reported in the technical literature for the next 45+ years. It is perplexing that a problem defined by the middle 1950s continues to be a serious problem into the 21st century, although the problem of whiskers has not been ignored in the intervening years. Review papers have periodically revisited the topic of whisker formation and new data has been presented in an attempt to define the fundamental mechanisms of whisker growth. Nonetheless, new hardware designs continue to ignore the whisker knowledge base and incorporate electroplatings prone to whisker formation and growth. As discussed in the following sections, the end results of these unfortunate design practices can be catastrophic.
A.
Field Problems
In 1975, the European Space Agency noted its experiences with Sn-whisker problems and strongly recommended that surfaces that may support stress-induced whisker growth, such as tin, cadmium, and zinc, be excluded from spacecraft design [13]. The agency also noted that ‘‘an alternative finish not been seen to support whisker growth is 60/40 tin–lead.’’ These recommendations were probably the first ever publicly made stating that whisker-forming metals (Sn, Cd, Zn) should be excluded from mission-critical applications such as spacecraft hardware. It is not known whether the European Space Agency followed its own recommendations, but it is a fact that Sn-whisker problems continued to plague some military and commercial spacecraft hardware over the following quarter century. In 1993, the U.S. Air Force published some of their Sn-whisker experiences, along with a detailed description of a disposition process for Sn-plated parts [14]. The NASA Goddard Space Flight Center has also listed a number of Sn-whisker related incidents (Table 2).
B.
Some Industry Practices Used to Cope with Tin Whiskers 1. Vacuum Clean—Northern Electric Corporation described their experiences with Sncoated wiring on filter assemblies and Sn-plated steel frames in a series of papers published between 1968 and 1975 [15–18]. As an interim solution, Northern Electric developed a vacuum tool to remove whiskers from Sn-plated steel frames while still in field service and found that whiskers did not regrow on the vacuumed parts. General Electric has reported Sn-whisker problems with wire-wrapped relay contacts [19] (Fig. 8a and b). GE used a vacuuming technique to deal with the affected hardware in a manner similar to that pioneered by Northern Electric. 2. Heat treatment/fusing—To provide a solution to the problem of whisker formation at the assembly stage, Northern Electric developed a thermal treatment based on heattreatment concepts, initially proposed by Glazunova and Kudryavtsev [10], as well as a fusing operation based on a recommendation initially proposed by S.M. Arnold [2]. However, in the mid 1960s Northern Electric was developing bright-Sn processes as a replacement for matte Sn, and they found that bright-Sn deposits cracked and spalled when heat-treated [18].
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Some Whisker-related Reliability Incidents
Problem Description Heart Pacemaker-Class 1 Product Recall—due to tin whisker problems F-15 Radar: electrical short inside hybrid package due to tin whiskers. U.S. Missile Program—tin whiskers on relays Phoenix Air-to-Air Missile: electrical short circuits due to tin whiskers. Galaxy IV/Galaxy VII: loss of satellite ops. Nuclear Utilities: relay electrical shorts due to tin whiskers. Patriot Missile II: whiskers from tin-plated terminals.
Reference Ref: http//www.fda.gov/gra/inspect_ref/itg/itg42.html Ref: B. Nordwall, Aviation Week and Space Technology, June 20, 1986, pp. 65–70. Ref: J. Richardson and B. Lasley, Proc. 1992 Govt. Microcircit Apps. Conf., Vol. XVIII, pp. 119–122, Nov. 10–12, 1992. Ref: L. Corbid, Proc. 3rd Inter. SAMPE Electronics Conf., pp. 773–779, June 20–22, 1989. Ref.: http://www.sat-index.com/failures/ Ref: http://www.nrc.gov/reading-rm/doc-collections/events: status/part21/1999/1999352.html Ref: http://www.anoplate.com/news/pastings/fall2000/tin.htm
3. Lead (Pb) additions—Because of cracking and spalling problems when annealing bright tin, Northern Electric adopted the practice of adding lead (Pb) to mitigate whisker formation. The addition of Pb to a Sn plating in the amount of 1–10% by weight became the most common whisker-mitigation practice largely as a result of the work by Bell Laboratories and Northern Electric. There are no known instances of Sn-whisker incidents in actual field service for tin–lead (Sn–Pb) platings, which have been the predominant lead-frame finish since the 1950s. Laboratory experiments with Sn–Pb films have only been able to grow whiskers when the films are put under clamping pressure or when they are subjected to stress testing (e.g., temperature cycling). 4. Nickel underlay—A major electronics manufacturer has reported over 20 years of success with bright Sn on a Ni underlay over Cu substrates [20]. Occasional manufacturing lapses that resulted in inadvertently omitting the Ni underlay resulted in whisker growth in the field requiring service action. Nickel (Ni) underlays are the predominant whisker mitigation practice for separable connectors where wear resistance is an important design consideration, and should be considered as a prime method for whisker mitigation of tin films for applications other than connectors. It seems that a Ni underlay results in a Sn film with a built in tensile stress that remains stable over time [21]. The great majority of theoretical models for whisker formation presume that a
FIG. 8 (a and b) Tin whiskers on relay pins. The spacing between the pins is about 50 mils. (From Ref. 19.)
862 TABLE 3 Ref. 7)
CHOI ET AL. Tin Whisker Mitigation Recommendations from the International Tin Research Institute (From
Sn-Whisker Mitigation Recommendation Sn on brass should have a Ni underlay, but Sn on steel may be better without an underlay Bright tin directly on brass must not be used. All bright tin coating should be accompanied by every possible safeguard where whisker growth could be damaging Coating thicknesses of tin electrodeposits, not flowmelted, should be at least 8 Am thick. Heat treat tin coatings after plating at 180–200jC for 1 hr. Care is needed in applying heat treatment to bright-tin coatings. If heat treating interferes with subsequent soldering, a protective nitrogen atmosphere should be considered. A copper undercoat may help to obtain better results from heat treatment. Storage conditions and, when possible, service environments should be controlled to avoid corrosion of the base metal since this may introduce harmful stresses to the coating. A hot dipped (or flow melted) tin coating is at far less risk than an unheat-treated, electrodeposited coating Tin–lead deposits, at least 8 Am thick, matte or bright, are probably safe and suitable for most purposes where whisker growth is a potential hazard. The use of a nickel or copper undercoat on brass is a useful additional precaution. Heat treatment is not necessary and can lead to undesired fusion of the tin–lead coating if not well controlled. A lead (Pb) content of 1% has been claimed as effective, but it seems better to select a tin–lead process giving a larger lead (Pb) content. All tin and tin–lead coatings may develop whiskers rapidly where they are subjected to local pressures. When the diminished solderability and ductility of tin–nickel alloy (with 65% tin) are not a bar to use, this coating will provide immunity from whisker growth. Although organic coatings of the thickness commonly used for protection cannot be relied upon to prevent emergence of whiskers, the use of thick layers of resin or the introduction of a solid insulating barrier between points in danger is effective. If, in spite of all precautions, whisker growth occurs, it may be possible to rehabilitate equipment by the physical removal of whiskers. . .a useful means of removal is a small head attached to a vacuum system.
Commentary The Zn in brass is blocked by the Ni and cannot diffuse into the Sn film. Bright tin films have relatively high internal stresses and very small grain sizes. They are very prone to whisker growth.
Bright tins are very difficult to heat treat. Northern Electric tried to heat treat bright tin films and abandoned the practice.
Testing at elevated humidity levels has consistently been shown to accelerate the formation of whiskers. Fused tin is essentially flow melted tin.
Tin–lead films have been the standard (most common) tin-based plating for over 40 years and have never been shown to have any whisker growth under ambient usage conditions. High clamp-stresses on parts like bolted connectors can result in whisker growth in tin–lead films.
This recommendation refers to bolted connectors.
Tin–nickel alloys are not in common usage.
Such practices are often used to mitigate the risk of using inventory, which has been compromised because of whisker formation by a bad choice of plating.
This idea was initially proposed by M. Rozen of Northern Electric in the 1960s, and it has been periodically used since then to recover a contaminated inventory of parts.
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compressive-stress state in the film is a necessary prerequisite for whisker formation and growth. While it is true that laboratory stress testing has produced whisker formation on Sn films over a Ni underlay, there are no known instances of whisker formation on Sn over Ni underlay in typical field-service environments. 5. Pure tin finishes—User communities are well advised to exercise caution when designing electrical hardware utilizing any electroplated material capable of growing whiskers. The European Union’s Reduction of Hazardous Substances (RoHS) legislation requires that Pb be eliminated in most electronic-hardware applications by July 1, 2006. Many component providers will attempt to meet the European Union regulations by simply modifying their Sn–Pb platings to pure Sn. Tin can, and has, been successfully used. For example, all surface-mount, multilayer ceramic capacitors (MLCCs) have used a pure Sn end-cap metallurgy since 1992 with no known field-service whisker problems (as of 2002). However, the MLCC process utilizes a barrel-plated Sn with a Ni underlay on a Ag-frit substrate, and almost all of the Sn on MLCC end-caps is reflowed during the subsequent board assembly operation. While no field-service whiskering has been reported on MLCCs, there has been some laboratory work performed where whiskers were grown on MLCC end-cap metallurgy by subjecting the device to temperature cycling between 40 and + 60jC [22]. Whiskers were observed to grow from the Sn surfaces at about 100 cycles. It appears that the success of the commercial application of lead-free MLCCs was attributable, in part, to the fact that normal commercial applications do not subject the part to temperature cycling as described above, and also because most of the end-cap metallurgy is reflowed during the solder attach process. However, aircraft applications are another matter, as temperatures are constantly cycled between 40 and +60jC. For aircraft applications, it is advisable to use MLCC end-cap metallurgies other than Sn. The user should clearly understand the data behind the claims of ‘‘whisker-free’’ platings before implementing Sn-electroplated parts. The user should understand that the decision to use any Sn-electroplated film is not risk-free, despite claims to the contrary.
C.
Recommendations
The Tin Research Institute in England, now known as the International Tin Research Institute (ITRI) [7] detailed 20 years of Sn-whisker observations based on work carried out in cooperation with Bell Laboratories. Recommendations, listed in Table 3, were made which summarized the best thinking at that time, and these recommendations can still be regarded as relevant to the careful user.
IV.
WHISKER FORMATION AND GROWTH THEORIES BASED ON DISLOCATIONS
Dislocations are line defects in three-dimensional crystalline solids consisting of extra (or missing) atoms arranged in line in an otherwise ideal crystalline-lattice structure. These line defects are the means by which all metals are plastically deformed, and they also play a role in many solid-state phenomena, such as diffusion and electrical resistivity. Dislocations were the basis of the first theories proposed for the growth mechanism of Sn whiskers. The first whisker formation and growth dislocation theory was published in 1952 [23]. Peach proposed that whiskers grew by Sn atoms migrating through a screw dislocation located at the center of a whisker and depositing themselves at the tip of the whisker. This particular theory was quickly invalidated by subsequent experimental data.
A.
Whisker Growth from Whisker Base
The first experimental data of relevance was the seminal observation by Koonce and Arnold (K–A) in 1953 that whiskers grew from Sn atoms continually added to the base, and not the tip,
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of a whisker [24]. This observation effectively negated the idea of a whisker with a centrally located screw dislocation acting as the conduit for diffusing Sn atoms to the tip of a whisker, as proposed by Peach.
B.
Early Dislocation Theories
Dislocation theorists quickly began to construct theories that were consistent with the Koonce– Arnold observations. These theories were based on the generation of dislocations and their subsequent movements. Frank [25] and Eshelby [26] independently proposed diffusion-limited dislocation mechanisms where the driving force for dislocation generation and motion were stress fields created by surface oxidation. For a dislocation to move it is necessary to have a stress field, either externally applied or internally created. To create a whisker, it is necessary for a dislocation to move to a surface and deposit its extra plane of atoms on that surface. Furthermore, any theory proposing that whiskers grow by the movement of dislocations that fails to reconcile the Koonce–Arnold observation would be invalid. The K–A observation has never been contradicted or questioned since it was first introduced in 1953. Eshelby’s model postulated an internal source of simple prismatic dislocations that expanded by climb to the boundaries of a whisker-forming grain and then moved by glide to the surface of the grain. Frank’s model involved a rotating edge dislocation pinned to a centrally located edge dislocation. Both Frank and Eshelby felt that bulk diffusion of Sn would support the observed growth rates for spontaneously grown whiskers, and they both claimed their models were consistent with the Koonce–Arnold observation.
C.
Effect of Externally Applied Forces on Whisker Growth Rates
An important contribution to the Sn-whisker knowledge base was a study conducted by Fisher et al., where they observed that a Sn-plated steel specimen held within a metallurgical clamp grew a prolific number of whiskers over a period of only a few days. In a more controlled experiment, Fisher et al. made the first whisker growth-rate measurements under conditions of an externally applied stress [27] (Figs. 9 and 10). At an applied compressive stress of 8000 psi, some whiskers were observed to grow at rates of 10,000 A˚/sec. Spontaneously grown whiskers (grown without any externally applied stress) grew at rates closer to a fraction of 1 A˚/sec. This data demonstrated
FIG. 9 A growth plot for three different tin whiskers (A, B, and C) that were grown on tin-plated steel with a clamp pressure of 8000 psi. (From Ref. 27.)
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FIG. 10 A growth-rate plot for tin whiskers grown on tin-plated steel with a clamp pressure of 8000 psi. The three plots (1, 18, and 100) represent the number of individual whiskers that correspond to the three plot lines. (From Ref. 27.)
that whisker growth was directly tied to the magnitude of compressive-stress gradients in an electroplated-Sn film. Fisher et al. explained the sudden stoppage of whisker growth (i.e., cessation) as the result of impurity atoms plugging the dislocations and inhibiting fast diffusion of tin atoms through the dislocation networks. Although Fisher’s results have not been specifically reproduced, the general relationship between compressive-stress gradients and whiskergrowth rates has been verified by other experimenters. Clamp-pressure experiments were conducted on tin-plated steel at pressures of 150 kg/cm2 that resulted in whisker-growth rates of 2.3 A˚/sec [28] (compared to the 10,000 A˚/sec reported by Fisher et al.). Additional clamppressure experiments were conducted on Sn-plated steel reported where the highest whiskergrowth rate achieved at clamp pressures of 8000 psi was 593 A˚/sec [29]. In this later study, it was observed that whisker-growth rates decreased over time, which was in contrast to the linear growth rates reported by Fisher et al. This later study showed that whisker growth ceased with time, as was also observed by Fisher et al. This study also commented about clamp-pressure experiments on hot-dipped Sn and 50Sn–50Pb platings on both steel and Cu substrates. While whisker densities were observed to decrease with the addition of Pb, considerable whisker growth occurred at high clamp pressures (several thousand psi) for the 50Sn–50Pb plating. It was also observed that a hot-dip Sn coating on Cu produced considerably fewer (about half) whiskers compared to the same hot-dip coating on steel substrates when subjected to high-clamping pressures.
D.
Dislocation Theories: Post Early Clamp-Pressure Results
The first whisker dislocation theory subsequent to the clamp-pressure results of Fisher et al. proposed that internal stress in the whisker-growing medium is relieved by whisker growth when that stress could not be relieved by other processes [30]. Whisker growth stopped when the internal stresses were relieved. This model proposed that a concentration of vacancies at the root of the whisker was maintained at a constant level by absorption of vacancies at edge dislocations situated at the end of a stress gradient. Using these assumptions, it was demonstrated that a linear relation should exist between growth rate and applied pressure, as reported by Fisher et al.
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However, predicted growth rates were still at least 1 order-of-magnitude smaller than those reported by Fisher et al. In addition, the pinning of dislocations by impurity atoms over time suggested that growth rates should tail off gradually and not abruptly as observed by Fisher et al. Some clamp-pressure experiments [29] were, in fact, reported that did show a gradual tailing off of whisker growth rates over time [27]. Another dislocation model proposed that helical dislocations in the whisker grain move to the surface by climb [31]. No experimental evidence for the existence of helical dislocations in Sn films was offered. It was stated that the helical dislocation model was consistent with the Koonce– Arnold observation, but there was no discussion of the helical-dislocation model in reference to the clamp-pressure experimentation of Fisher et al. [27].
E.
Dislocation Glide Theory
J. Franks [32] recognized that rationalizing the Fisher et al. observations appeared to be ‘‘difficult,’’ so he proposed a dislocation–glide model where the frequency of dislocation generation was dependent on diffusion processes. He proposed that whisker-generating dislocations, called Eshelby sources, are initially pinned due to lattice faults, and thereafter act as dislocation sources under the influence of either an applied or internal-stress field [33]. Once pinned, these dislocations expand so as to lie in glide planes, and then glide to the surface, piling up as they reach the surface. Eventually these piled-up dislocations break through the surface and grow a whisker. According to this theory, the material for whisker growth is supplied by a ratecontrolling diffusion mechanism. This model accounted for the observation that whisker growth suddenly stops at some fixed end point, regardless of the growth rate or applied pressure, by surmising that the dislocation sources eventually become fixed or plugged. That is, the dislocations become incapable of generating new dislocations because of faults introduced into the ‘‘region by the constant addition of material to the region at the base of the whisker, eventually locking the whisker-generating dislocations.’’ Franks’ theory attributed the stress fields to either internal or external forces, and not oxidation effects as was the case with the earlier Eshelby expanding-loop theory [26].
F.
Two-Stage Dislocation Models—Climb and Glide
U. Lindborg claimed that prior dislocation theories based on lattice diffusion achieved agreement with experimentally observed Sn-whisker growth rates because the estimates for Sn diffusion coefficients were in error on the high side by about 106 [34]. Lindborg proposed a two-stage dislocation model for the growth of whiskers in Zn, Cd, and Sn where the first stage was a dislocation loop-expansion stage, based on dislocation climb and vacancy diffusion, similar to the prior theories of Eshelby [26] and Franks [32,33]. The concepts of grain-boundary and dislocation-pipe diffusion were used to account for the whisker growth rates reported in the prior literature. A second stage was also postulated wherein dislocations, after they are created by the source and expand by climb, glide toward the surface where they deposit a layer of Sn atoms. Resistance to gliding dislocations was attributed to a network of forest dislocations within the grains. Either stage could be the rate-determining factor in the whisker-growth rate. It was speculated that the very high, stress-accelerated growth of whiskers was an example of the first stage (diffusion-limited growth) determining the growth rate. The clamp-pressure results of Fisher et al. [27] were thought to be a manifestation of the first stage in this model, where diffusion limits the growth rate. 1. Change in the State-of-Stress Lee and Lee proposed a model where prismatic dislocation loops in the whisker grain expand by climb up to the grain boundaries, and then glide toward the surface driven by a stress gradient. Whisker kinking (a change in growth direction) was attributed to prismatic dislocation loops expanding on new slip planes, and the internal stress gradients were attributed to Cu6Sn5 precipitation in grain boundaries. Lee and Lee reported the first direct measurements of residual stresses in Sn electroplate through the use of a cantilever-beam method. One side of a cantilever
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beam was plated, thereby causing the beam to deflect as a result of the stresses in the film. The deflection can be correlated to the average residual stress in the film. It was observed that immediately after plating the stress in the films was tensile. However, within days, the tensile stress changed to become compressive. This change in the state-of-stress was attributed to the formation of Cu6Sn5 at the Sn/Cu boundary and at the grain boundaries. 2. Crystallographic Orientation Lee and Lee [35] also determined the preferred-orientation indices of the deposited films by using X-ray diffractometry. Their Sn was plated on phosphor-bronze substrates from an acid-stannous bath maintained at room temperature. It was not stated whether the Sn was matte or bright, but the polygonized nature of the grain structure suggests that brighteners were not added to the plating solution. The average grain size of the electrodeposits was 1 Am, which is a relatively small grain size for matte-Sn plating. Unlike some previously published data, the grain size was observed to decrease with increasing electrodeposition-current densities [36]. The crystallographic orientation of individual whisker grains was determined by comparing the angle of whisker growth to the preferred orientation of the film, and found that whisker grains were different in orientation compared to the predominant texture of the as-plated films. It was conjectured that the differently oriented whisker-forming grain may have been the result of a recrystallization event, and that the different orientation of the whisker grain resulted in a weaker TABLE 4
A Summary of Whisker Growth According to Lee and Lee [35] with Commentary
Assertions Compressive stresses in the film are built up over time due to the diffusion of copper atoms from the substrate into the tin film, and the subsequent formation of the intermetallic Cu6Sn5. The as-deposited stress state for the tin film was net tensile (+11 MPa) and changed to a compressive stress (8 MPa) after a few days. Subsequent to whisker formation and about 50 days later, the stress level decreased (5 MPa). Tin whiskers grow from grains whose orientation is different from the major orientation of the tin film. . .the tin surface oxide film can be sheared along the boundaries of the grain. To release the compressive stress in the film, tin whiskers grow from the grain whose surface oxide is sheared. The whisker growth is controlled by the expansion of the prismatic dislocation loop on the slip plane by climb. . ., i.e., the operation of a Bardeen–Herring dislocation source. The dislocation loop expansion is restricted by the grain boundary. The loop then glides along its Burgers vector direction. As a result, the tin whisker grows by one atomic step. The continuous operation of the Bardeen–Herring dislocation source gives rise to whisker growth until the stress is relieved.
Commentary These data were the first direct measurements of tin film internal stresses, and the cantilever beam method was utilized.
The different orientation of the tin whisker grain had been seen by others prior to Lee and Lee’s work. It is a generally accepted fact that the whisker grain is different in orientation than the surrounding regions. It is generally accepted that tin whiskers are one type of stress relief mechanism. This proposal is an expansion of the original concept proposed by J.D. Eshelby in 1953 and expanded upon by others. It is not generally accepted as a proven concept mainly because there is no direct experimental evidence to support it.
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(i.e., thinner and/or cracked) oxide layer. A thinner oxide could facilitate gliding dislocations to break through the surface layer and cause the formation and growth of a whisker. Lee and Lee’s proposals integrated a number of prior concepts into a general concept of whisker formation and growth. It is, however, important to note they did not discuss their dislocation model with respect to the Koonce–Arnold observation. The major conclusions based on the work of Lee and Lee are summarized in Table 4.
G.
Critique of Tin Whisker Formation and Growth Based on Dislocation Theory
Ellis et al. stated in 1958 that some whisker-growth directions in kinked crystals were not dislocation glide directions, and that an alternative (nondislocation) mechanism would be required to rationalize these observations [37]. All dislocation–glide theories require that whisker-growth directions be a dislocation glide plane. Ellis, et al., pointed out that while most whisker-growth directions are parallel to dislocation glide planes, not all are. Ellis’ point was acknowledged at the time by Frank, one of the earliest advocates of a dislocation-based, whisker-growth theory. No one has ever refuted Ellis’ observations, even as they have been largely ignored. The importance of dislocation networks and grain boundaries as fast-diffusion paths for Sn atoms to reach the base of the growing whisker was acknowledged by Ellis. However, the major thesis of Ellis’ work was the proposal that recrystallization was a key step in whisker formation and growth. Ellis had no direct proof of recrystallization, but inferred from various data the reasonableness of such a proposal. Tin atoms would move out of the grain boundaries and into the recrystallized grains, thereby growing the volume of the recrystallized grain.
V.
ANALYTICAL TOOLS THAT PROVIDE FUNDAMENTAL UNDERSTANDING
Bell Laboratories was the first to use the electron microscope to investigate whisker growth problems in the early 1950s [38]. The scanning electron microscope (SEM) was introduced with the first micrographs in 1972 [17]. Auger analysis was initially utilized to investigate whiskers in the 1980s [39]. X-ray diffractometry has been used to identify chemical compositions and film stresses since at least 1996 [40]. Focused ion beam (FIB) microscopy was initially used to study Sn whiskers in 2001 [41], and microfocus X-ray diffractometry in 2002 [42].
A.
Need to Understand Structural Details
By the end of the twentieth century, it was clear that theories of whisker formation and growth had not been substantiated by sufficient experimental evidence and, therefore, were little more than informed speculation. A very comprehensive survey concluded that none of the then existing whisker-growth theories were supported by adequate experimental verification, and that it was critical to understand the crystalline microstructure of Sn-electroplated films and whiskers [43]. However, Sn-film microstructural analysis was extremely difficult to do because of the physical nature of Sn. Tin is a very soft material that is extremely difficult to polish and etch in the classical metallurgical manner. Furthermore, tin tends to readily recrystallize as a result of mechanical deformation from laboratory polishing operations, which means that the microstructure eventually observed after polishing and etching is not the actual microstructure. It was clear that new analytical tools were required to advance the fundamental understanding of whisker formation and growth. In particular, it was necessary to develop a means for examining the detailed microstructure of Sn whiskers and the surrounding region; and to gain an understanding of stress in the whisker region in detail, rather than just on average. Detailed stress measurements were made possible by the development of microfocus X-ray diffractometry that focused X-ray beams to a 1-Am2 spot size (previously only possible down to about 500 Am square). Microfocus X-ray provided a means to attempt the measurement of relative stress levels for 1-Am square regions around a whisker. Furthermore, the development of focused ion beam
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(FIB) microscopy provided a means of conducting in situ micromilling on Sn films without the necessity of mechanically abrading the Sn. FIB microscopy utilizes a rastered stream of accelerated gallium (Ga) ions to mill the surface of a target film and, at the same time, generate a stream of secondary electrons from the milled surface that can be collected to generate a visual picture of the structure. Some FIB microscopes incorporate a scanning electron microscope capability integrated into the basic FIB tool, the so-called dual-beam FIB. Microbeam X-ray and FIB diagnostic tools have been the primary means by which new insights into the fundamental mechanisms of whisker formation and growth have been determined.
B.
Microbeam X-Ray Diffractometry (Synchrotron Radiation)
1. Advantages and Method The microdiffraction apparatus at the Advanced Light Source in Lawrence Berkeley National Laboratory was used by Choi et al. [42], to study the stress around Sn whiskers grown on a eutectic Sn–Cu plated finish deposited on a Cu lead frame. An X-ray microdiffraction end-station was utilized which was capable of delivering a white X-ray beam (6–15 keV) focused to 1 Am via a pair of elliptically bent Kirkpatrick–Baez mirrors. The size of the beam (f1 Am) was smaller than the grain size (3–5 Am) of the deposited film, so that a single-grain white beam Laue pattern could be obtained for individual grains. The Laue patterns were collected with a large area (9 9 cm2) charge-coupled device (CCD) detector with an exposure time of 1 sec at each step scan, from which the orientation matrix and a deviatoric strain tensor for each illuminated grain were derived. Because of the low absorption of X-rays, several grains were illuminated at the same time through the thickness of the finish, but the grain of interest (the one closest to the surface) was discriminated from the rest by the intensity of its reflections. An area of about 100 100 Am was scanned by using 1.5-Am beam squares. The strain (and equivalent stress) in the Sn–Cu matrix grains was determined by using the lattice parameters of the whisker as a stress-free internal calibration reference. Fig. 11 is a low-magnification SEM micrograph depicting an area where a whisker and its surrounding region was scanned. A microbeam diffraction pattern of the whisker is shown in Fig. 12. The axis along the length of the Sn whisker was determined to be (001). Pole figures of (100), (110), (321), and (211) orientations are shown in Fig. 13(a)–(d), respectively. A high concentration of (321) at the center of the pole can be seen in Fig. 13(c), thus the surface of the finish had a (321) texture. 2. Deviatoric Stress State The above microdiffraction study showed that for 1.5-Am square areas immediately around a whisker the stress was not biaxially uniform; rather the stresses were highly inhomogeneous with grain-to-grain variations. The film stress was biaxial only in average. Fig. 14 shows a plot of rVzz, which is the deviatoric component of the stress along the surface normal, that was measured from deviations in crystal Laue pattern and which did not include any volume expansion corrections. Because r Vxx+r Vyy+r Vzz=0 (by definition), r Vzz is a measure of the in-plane stress. A positive value of r Vzz (=r Vxx+r Vyy) indicates an overall tensile stress, whereas a negative value indicates an overall compressive stress. However, the measured strains of less than 0.01% were only slightly larger than the strain detecting sensitivity of the white-beam Laue technique (the strain sensitivity of the technique is 0.005%). The key conclusion from the above study is that the compressive stresses in the finish were very low (less than 10 MPa) and no long-range macrostress gradients could be determined around the root of the whisker to indicate that whisker growth had relieved most of the local compressive stress in the surrounding grains. However, when Choi et al. assumed that the whisker was stress-free the microdiffraction data could be interpreted to mean that the surface layers of the Sn–Cu finish around the base of the whisker were compressively stressed (the calculated values of the stress mapping of the region in and around the whisker are shown in Table 5). The compressive stress values were quite low, on the order of several MPa (or several hundred psi), and there was a slight (i.e., short range) stress gradient from the whisker root to the immediately surrounding regions. This implied that the stress level just below the whisker was slightly less compressive than the surrounding area, which
FIG. 11 Low-magnification SEM image of the surface of a lead frame coated with a Sn–Cu finish that exhibited several Sn whiskers. The one selected for a microbeam diffraction analysis is circled. (From Ref. 42.)
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FIG. 12 Microbeam diffraction pattern of the whisker circled in Fig. 11. (From Ref. 42.)
is to be expected because the stress very near to the whisker is presumed to be relieved by whisker formation and growth. In Table 5, the arrows indicate the stress gradients. Some examples of adjacent blocks in Table 5 having the same stress level value are indicated by circled sets, which means that they belong to the same grain. The microdiffraction technique also provided the grain orientation distribution surrounding the root of a whisker, as shown in Fig. 15. Of particular interest is the grain underneath a whisker. 3. Grain Orientation Under a Whisker Choi et al. [42] intuitively felt that the microstructure of the whisker grain should be different from the surrounding grains. From the pole figures in Fig. 13, they determined that the surface layer of the Sn–Cu solder finish had a (321) texture, and from Fig. 15 they determined that the grain just below the whisker exhibited a (210) orientation. This (210) grain was, therefore, considered to be a discontinuity in the predominantly (321) microstructure. Choi et al. conjectured that this (210) structural discontinuity could be a location where the surface oxide could easily be broken by a whisker growth. 4. Summary From the studies conducted by Choi et al. [42] on Sn–Cu films, it was determined that the internal stresses, on a scale of 1.5-Am squares, were highly inhomogeneous with significant grain-to-grain
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FIG. 13 Several pole figures of grains in the Cu–Sn finish. (a) Pole of (100), (b) (110), (c) (321), (d) (211) orientations. A high concentration of (321) grains is noted at the center of the pole in (c). (From Ref. 42.)
variability. On average, the stresses around whiskers were compressive and generally smaller in magnitude at regions immediately adjacent to the whisker. a. Internal Stress Variation in Sn-Electroplated Films. Choi et al. established that internal stress variation in Sn–Cu electroplates were highly variable from grain to grain. However, vertical stress gradients were not addressed in this work. The Sn/substrate interface is a region of great metallurgical interest. Tin forms an intermetallic compound (IMC) with most substrate materials almost immediately after the electroplating process has been completed, and for Cu substrates the IMC is usually Cu6Sn5. It is well known, and generally accepted, that Cu6Sn5 creates a compressive stress state at the Sn/Cu interface. Therefore, the presumption is that there is a vertical compressive stress gradient in the Sn-plate films with the highest compressive stress located at the Sn/Cu boundary where the Cu6Sn5 IMC is located. This vertical compressive stress gradient would be further enhanced by the diffusion of Cu (and other impurity atoms) from the substrate into the Sn film. The stress state at the surface of the film will be less
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FIG. 14 Deviatoric stress in the Z-direction for the area around the whisker root, with the contribution of the whisker deleted. (From Ref. 42.)
TABLE 5 Stresses and In-Plane Stress Gradient Map of the Region Surrounding a Tin Whisker Root (From Ref. 42)
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FIG. 15 Distribution of grain orientation around the root of a whisker determined by X-ray microdiffraction. (From Ref. 42.)
compressive than the film at the substrate interface. It is even possible, perhaps even likely, that the stress state of the film at the surface will be zero or even tensile. W. Stevens reported synchrotron X-ray diffractometry results on matte-Sn platings indicating that compressive stresses at the Sn/Cu substrate interface approach 40 MPa [44]. If confirmed, this would be the highest magnitude internal stress ever reported for a Sn film and it would add some weight to the speculation that there are positive (i.e., compressive to tensile) vertical stress gradients in Sn-electroplated films of relatively high magnitude. This X-ray result has to be considered very preliminary, but it is consistent with observations on cantilever beams that have been plated on one side and then etched [45]. Shortly after the cantilever beam was plated with a tin film a compressive stress was generated that deflected the beam. The tin film was then etched to remove the tin film but not the IMC that had formed between the tin film and the Cu substrate. It was observed that the deflection was relatively unchanged by the etching operation. The conclusion from this experiment was that compressive stresses in a Sn film were largely a result of IMC formation at the tin/substrate interface. It has also been theorized that Sn films over a Cu substrate have compressive stress gradients resulting from fast diffusing Cu atoms migrating into the grain-boundary network of the Sn film and forming precipitates of Cu6Sn5 IMCs, and that these compressive stress gradients were the principal driving force for whisker formation and growth [46].
C.
Focused Ion Beam (FIB) Microscopy
FIB studies were conducted that identified some important microstructural characteristics of Sn whiskers relative to their immediate surroundings [47]. FIB specimens were characterized by
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using a selective area electron diffraction pattern, and the corresponding transmission electrons microscopic images of the whisker cross-section normal to its growth direction are shown in Fig. 16(a) and (b), respectively. The diffraction patterns were indexed to be a single crystal in the h001i orientation. 1. Focused Ion Beam Images of Sn Whiskers and Eutectic Sn–Cu Finishes Fig. 17 depicts a focused ion beam (FIB) image of a surface area on the surface of a Sn–Cu finish with two rectangular etched holes and a thin bridge of Sn–Cu left standing between the two holes. This bridge was subsequently removed intact and prepared for transmission electron microscopy (TEM). Utilizing a set of FIB trenches in this manner is a typical method of preparing a sample from a specific location for cross-sectional TEM study. Several Sn whiskers can be observed surrounding the two holes. Actually, there was a whisker located between the two holes before the FIB etching. This thin sample prepared by FIB enabled an image of cross-sections parallel to the whisker growth direction to be studied. Similarly, cross-sectional images of the grains immediately surrounding and below the root of a whisker could also be examined. Fig. 18(a) and (b) shows corresponding FIB and TEM images of a thin slice similar to the one in Fig. 17 In the cross-sectional FIB image of Fig. 18(a), a crack is apparent in the upper left part of the image. The same crack can also be found in the upper left part of the corresponding cross-sectional TEM image in Fig. 18(b). The top layer above the crack is a deposited protective layer needed to prevent etching the thin slice by the focused ion beam during sample preparation. The image of a whisker, which is below the top protective layer, is indicated by an arrow in Fig. 18(b). Although the whisker was a single crystal, it nevertheless contained observable defects. Most likely, these defects were introduced when etching the sample with the high-energy ion beam. a. Cu6Sn5 Precipitates in Grain Boundaries of Eutectic Sn–Cu. Sheng et al. [47], noted that there were many small precipitates of Cu6Sn5 in the Sn grain boundaries (Fig. 18a). They appeared as bright particles and their composition was confirmed by energy dispersive analysis to be Cu6Sn5. The presence of these Cu6Sn5 precipitates provided an explanation for the origin of the compressive stresses thought to be the driving force for whisker growth, and an explanation for why eutectic Sn–Cu finishes form more whiskers than pure Sn finishes. It was also reported [47] that most of the grain boundary Cu6Sn5 particles precipitated during the electroplating of the eutectic Sn–Cu alloy. Sheng et al. stated that if the eutectic Sn– Cu film was reflowed (i.e., melted), most of the Cu in solution during the liquid state would precipitate out as grain boundary Cu6Sn5 IMC particles during solidification. During solidification, the Sn becomes supersaturated with Cu atoms, which then precipitate out of solution. As the grain size of the resolidified Sn–Cu film was only a few microns, it took less than a second for Cu in the interior of a grain to diffuse to the surrounding grain boundaries to form an intermetallic (IMC) Cu6Sn5 precipitate. The interstitial diffusivity of Cu in solid Sn is extremely fast; more rapid than 108 cm2/sec at room temperature. The above solidification scenario is also true for electroplating. Supersaturated Cu atoms remaining in solution within the Sn film after plating quickly diffuse to the grain boundaries during storage at room temperature. Whether the diffusion of these remaining supersaturated Cu atoms to a grain boundary to form Cu6Sn5 would induce a compressive stress, or not, is controversial. The stress caused by a Cu6Sn5 precipitate in Sn films depends on whether the Cu comes from the Cu substrate or from Cu atoms in the grains that originated from the plating deposition process. Cu atoms from the substrate add volume to the film and result in a compressive stress, whereas Cu atoms coming out of solution and precipitating as Cu6Sn5 in the grain boundaries result in a tensile stress because of the difference between the partial molar volumes of 6 Cu and 5 Sn atoms in solution and in the Cu6Sn5 precipitate. Sheng et al. [47] and Choi et al. [42] believe that the IMC Cu6Sn5 phase is the reason why the addition of Cu to a Sn-electroplated film builds up a compressive stress that enhances whisker growth. However, even for the case of pure Sn deposited over a Cu substrate there is significant diffusion of Cu from the Cu substrate through the Sn film which will grow grain boundary precipitates resulting in the build up of a compressive stress in the Sn film.
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FIG. 16 Cross-sectional transmission electron microscopic images of a tin whisker. (a) A selected area diffraction pattern of a whisker in the 001 growth direction. (b) Cross-sectional images near a whisker bend thought to be images of screw dislocations. (From Ref. 47.)
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FIG. 17 Preparation of a thin slice sample utilizing a focused ion beam (FIB) for a transmission electron microscope (TEM) study. Two rectangular holes were etched on the surface of a eutectic Sn– Cu finish with a thin slice left standing between the two holes. The thin slice was used to perform the TEM analysis. (From Ref. 47.)
The morphology of the Cu6Sn5 particles shown in Fig. 18(a) and (b) suggested that the stress generated by their growth was not uniform. The Cu6Sn5 was distributed through the microstructure as discrete particles, and not as a thin layer, or wedge, in the grain boundaries. This observation was the basis for reasoning that there was a stress concentration gradient around each individual Cu6Sn5 particle. Furthermore, during room temperature aging, the Cu6Sn5 particles in the grain boundaries were observed to ripen (enlarge). In a closed system, with no additional (outside) availability of Cu atoms there can be no volume ripening. However, in the case of a Sn–Cu or pure Sn plated lead-frame the system is open, and Cu atoms from the leadframe substrate readily diffuse into the Sn–Cu finish to form increasing amounts of Cu6Sn5 over time. This continual ripening or growth in the volume of Cu6Sn5 within a Sn–Cu or pure Sn film produces a compressive stress. The existence of many Cu6Sn5 particles in the Sn–Cu finish was thought to be the main reason why eutectic Sn–Cu films had more whisker growth than was observed on pure tin finishes. b. Cu6Sn5 Precipitates in Grain Boundaries of Pure Sn. An FIB image of the cross section of a pure-Sn finish is shown in Fig. 19. While the Sn grains are clearly shown, relatively few grain-
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FIG. 18 (a) A thin slice of eutectic Sn–Cu finish prepared by FIB thinning. The whisker is indicated by an arrow. Many grain boundary precipitates can be observed that have been identified to be Cu6Sn5 by elemental analysis. (b) A corresponding TEM image. The whisker is indicated by an arrow. Although the whisker is a single crystal of Sn, it nevertheless contains numerous defects, most of which are dislocations. (From Ref. 47.)
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FIG. 19 An FIB image of a cross-sectional area of pure Sn finish prepared by FIB thinning. (From Ref. 47.)
boundary Cu6Sn5 precipitates are observed in comparison to those seen in Sn–Cu films (Fig. 18a), which is reflective of the major difference between the two finishes.
D.
Additional Features and Characteristics of Sn Whiskers Provided by Analytical Tool
1. IMC Particle Near Whisker Root One of the first published [41] FIB cross sections of a pure-Sn whisker (Fig. 20) clearly shows a floating particle, presumably Cu6Sn5, at the root of a whisker. There have been other published FIB x-sections of tin whiskers for matte, satin-bright, and bright Sn, in which the presence of an IMC particle was clearly evident directly at the root of the matte Sn and satin-bright whisker grains [48] (Fig. 21). 2. No IMC Particle Near Whisker Root However, in the above study [48], there was no indication of an IMC particle at the root of brightSn whiskers. This was thought to be attributable to the fact that bright-Sn whiskers originate
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FIG. 20 The first published FIB cross-sectional micrograph of a tin whisker grown on a copper substrate showing an intermetallic SnCu particle at the root of the whisker. (From Ref. 41.)
from a surface nodule rather than a surface grain. For bright-Sn films, a nodule appears to be a precursor state for the formation of whiskers. During bright-Sn aging experiments, nodules are observed before whiskers appear. 3. Effect of an Underlay Internal stress measurements using X-ray diffraction (XRD) and cantilever-beam techniques invariably show that, over time, internal compressive stresses are built into Sn films (matte, satin bright, or bright) deposited directly onto Cu or Cu-alloy substrates. These compressive stresses are usually attributed to buildup of the intermetallic compound Cu6Sn5 at grain boundaries and the film/substrate interface. Tin (matte, satin bright, or bright) deposited over a Ni underlay [48] exhibits a built-in tensile stress immediately after deposition that remains tensile after aging up to (at the time of this writing) 6 months. A study conducted by Vo used lead-frame Alloy 42 (Fe–Ni) substrates and deposited 10 Am of matte Sn over a 1-Am underlay of Ni [49]. The test samples were temperature cycled between 55 and +85jC for several hundred cycles and then examined using FIB. Some relatively short whisker growths were found on these samples. Fig. 22 is an FIB xsectional micrograph showing a well-defined matte-Sn columnar-grain structure with Cu6Sn5 precipitates on the vertically oriented grain boundaries and NiSn intermetallic at the boundary between the Sn film and Ni underlay. The whisker appears to be growing out of a surface grain and there is no evidence of precipitates in the boundary of the whisker grain. To date, there have been no reported instances of whiskers growing under ambient conditions for Sn films with a Ni underlay. To grow whiskers on Sn films with Ni underlay, it has been necessary to impose a stress test of some sort (e.g., temperature cycling, clamping pressure, or elevated temperature/ humidity). These facts are the basis for the pervasively high degree of confidence in Ni underlays as a whisker mitigation strategy.
VI.
WHISKER FORMATION AND GROWTH THEORY BASED ON RECRYSTALLIZATION
Material scientists recognize recrystallization as a phenomenon where a crystalline solid transforms its internal structure from one with high internal stresses and relatively small grains to a structure with low internal stresses and relatively large grains. The recrystallization transformation reduces the total grain-boundary area and defect density (e.g., dislocations, stacking faults, point defects) per unit volume. However, normal recrystallization does not involve net mass transport of atoms from one region to another. Early on, whisker growth was considered to be a stress-relieving process and a particular type of grain growth, so it was natural that some connection between whisker growth and recrystallization processes would be considered. There
FIG. 21 An FIB cross-sectional micrograph of a whisker grown on satin-tin deposited on a copper substrate showing (a) overview of an intermetallic SnCu particle at the root of the whisker. (From Ref. 48.)
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FIG. 22 (a) SEM micrograph of a tin whisker before FIB cross-sectioning. (b) FIB cross-sectional micrograph of a whisker grown by thermally cycling a 10-Am-thick matte-tin film over a 1-Am-thick nickel underlay on a copper substrate. The whisker was determined to be pure tin and appeared to form from the surface grain. Intermetallics were observed to form at the grain boundaries. (From Ref. 49.)
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FIG. 23 A schematic diagram of a recrystallized grain structure showing grains that are about the same size and uniform in shape. (From Ref. 50.)
were several studies that inferred the possibility of recrystallization based on experimental data, but none had direct metallographic evidence of recrystallization [10,37]. Kakeshita et al. surmised that ‘‘whiskers are considered to grow on recrystallized grains’’ and showed schematics of recrystallizing grains forming within a region of smaller, highly stressed grains [50] (Figs. 23 and 24). However, Kakeshita also had no experimental evidence to demonstrate the existence of recrystallized grains. Additional indirect evidence for recrystallization was reported in Ref. [35], where it was determined that the orientation of the whisker grain was different from the predominant grain orientation (or texture) as determined by powder X-ray diffraction analysis. It was speculated that the whisker-growing grain was different because it had recrystallized from a parent-crystalline matrix and, in so doing, had grown a whisker structure. Any whisker formation theory must rationalize the observed whisker data, particularly the kinetics of whisker growth and the cessation (sudden stoppage) of whisker growth. A theoretical hypothesis must be consistent with the direct and visually evident observations provided by microstructural analysis. That is, any whisker recrystallization hypothesis must demonstrate that
FIG. 24 A schematic diagram of a secondary recrystallization grain structure in which one grain has grown at the expense of its immediate neighbors. (From Ref. 50.)
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the microstructures of whisker structures are consistent with the expected morphology of recrystallized grain structures.
A.
Recrystallization and Tin-Whisker Growth Kinetics
Growth-rate data for Sn whiskers have been limited because of the difficulty of making such measurements. Tin-whisker formation and growth are well described as erratic. The delay time (incubation period) for whisker formation can be hours or years, and seemingly identical platings can give significantly different whisker densities and growth rate results. However, some whisker growth rate data is available, and there is also data on the speed with which grain boundaries move during recrystallization. These data will be examined in the following sections.
B.
Growth Kinetics of Spontaneously Grown Whiskers
Whisker growth rates for spontaneously grown whiskers are much lower than those measured in clamp-pressure experiments. The rates cited for all reported spontaneous, whisker growth-rate data are less than 1.5 A˚/sec. Table 6, which is a summary of the reported data, indicates that the observed growth rates range from 0.01 to 1.50 A˚/sec, with most of the reported data being between 0.01 and 0.10 A˚/sec. Growth rates for spontaneously grown Sn whiskers are relatively slow metallurgical reactions. For example, the growth rate of whiskers grown from the vapor phase has been reported to be 10,000–100,000 A˚/sec [51]. The rate of grain-boundary migration during recrystallization can be as high as 105 A˚/sec [52], and single crystals of materials such as germanium have been grown at rates of 2 104 A˚/sec [53]. A number of models, based on a variety of concepts, have been developed that readily rationalize observed whisker growth rates on the basis of grain boundary self-diffusion of Sn. These models make reasonable assumptions for the grain boundary self-diffusion coefficients of Sn because there are no direct measurements available. Generally, researchers assumed an activation energy for grain-boundary (or dislocation) diffusion to be some fraction of the well known activation energy for bulk lattice diffusion.
C.
Whisker Growth Rates and Cessation
1. Differences Among Whisker Growth Models All modern whisker models presume that the Sn atoms necessary to sustain whisker growth move to the vicinity of a whisker via grain boundaries or dislocation networks. Differences between the various models come after the Sn atoms arrive at the boundary of the whisker itself. Dislocation theorists presume that Sn atoms arrive at the whisker via grain-boundary diffusion, and then migrate into the whisker and supply dislocation-source mechanisms that continually generate dislocations, which then climb or glide into the whisker structure. The cracked oxide theory discussed in Section VII [53], presumes that local stress relief is achieved at defective (cracked) oxide locations that allow Sn atoms, that have migrated there through long-range diffusion, to
TABLE 6
Spontaneous Tin Whisker Growth Rates on Various Substrate Materials
Plating Type Sn Sn Sn Sn Sn Sn Sn
on on on on on on on
brass copper zinc copper-clad steel quartz steel Fe on brass
Whisker Growth Rates (A˚/sec)
Reference
0.100–1.500 0.080–0.840 0.240 0.008–0.012 0.010–0.340 0.032–0.075 0.002–0.008
Glazunova and Kudryavtsev [10] Glazunova and Kudryavtsev [10] Glazunova and Kudryavtsev [10] Zakraysek Ellis et al. [37] Ellis et al. [37] Ellis et al. [37]
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build up a whisker structure. Similarly, the recrystallization theory also recognizes that Sn atoms must be delivered to the recrystallized region via long-range, grain-boundary diffusion, and that Sn atoms must then migrate from the grain boundaries into the recrystallized grains (or whisker) whose growing volume then causes the oxide layer to crack. A detailed model of the migration from a grain-boundary network into a whisker-nodule structure has been described [37]. Because whisker growth is a relatively slow metallurgical process, it is not difficult for any model to rationalize observed growth rates. It has been necessary to recognize that the self-diffusion of Sn atoms in the Sn matrix is not quite fast enough to rationalize model growth-rate projections with the observed data and, therefore, it is necessary to include the grain-boundary (or dislocation network) self-diffusion of Sn into any proposed model. A difficulty for all whisker models is the linear growth rate as a function of applied external pressure, and the sudden halt in growth (cessation) that have been reported [27,28] by some investigators. It seems more reasonable to many that whisker growth rates should continually decrease over time as the driving force internal stresses are gradually relieved. In point of fact, there have been some data reported [29] of whisker growth rates that did continually decrease over time. These seemingly contradictory results may simply reflect the complex and time varying stress states in electroplated Sn, but they do complicate modeling. Stress measurements in plated films are the focus of much experimental work, and the interpretation of stress measurement data has been the subject of considerable controversy. 2. Effect of Intermetallic Compounds on Stress State The generally accepted rationale for the varying state-of-stress in Sn electroplates involves the formation of intermetallic compounds (IMCs) within the Sn matrix and at the Sn/substrate interface. The metallic elements of Cu, Fe, Ni, and Bi form IMCs in combination with Sn. Typical commercial Sn-plating solutions contain small amounts (30–100 ppm) of Cu, Fe, Ni, and Bi in solution, and the substrate material itself can contaminate the plating bath and, therefore, the asplated structure. These IMC-forming elements readily come out of solution and create discrete IMCs that tend to locate at the grain boundaries of the as-plated structure. The state of stress caused by elements (such as Cu) coming out of solution and precipitating out in grain boundaries as an intermetallic compound is a matter of some controversy. The molar volume of the Cu intermetallic Cu6Sn5 is less than the molar volume of the equivalent number of Cu and Sn atoms in solution; therefore, the induced stress state from this particular IMC formation process should be tensile. However, if the Cu diffuses up from the substrate into the tin film and then forms an IMC at the grain boundary, or anywhere else in the film, the resultant stress will be compressive. Experimentally, it is not possible to determine where the Cu atoms of an IMC particle in a Sn film grain boundary originally came from so the experimental observation of IMCs in the plating cannot be unequivocally interpreted as an indicator of a compressive stress. Lee and Lee [35] reported time-zero internal stresses, as determined by a cantilever-beam technique, that were initially tensile, and then became increasingly compressive over time. Another study [55] reported that bright-tin cantilever beam specimens were initially compressively stressed, and then relaxed to a less-compressive level over time. In yet another study [48], it was observed that the average residual stress for Sn on Cu substrates was compressive, but for Sn with a Ni underlay over a Cu substrate the average residual stress was tensile. The consensus opinion on stresses in electroplated films is that Sn on Cu substrates forms an intermetallic compound at the interface over time, and that the intermetallic Cu6Sn5 is itself in a compressive stress state relative to the underlying Cu substrate. For the case of Sn over Ni, the intermetallic compound that forms over time is in a tensile stress state relative to the underlying Cu substrate. The state of stress in the Sn film is a much more controversial subject. It is generally recognized that the time zero (right after deposition) state of stress in a Sn film can vary from tensile to compressive depending on the plating process conditions, impurity concentrations, and the type and amount of additives in the plating solution. The Sn-film stress state over time is the real controversy. XRD work tends to indicate that the surface layers of the Sn film (i.e., the top 1–2 Am) develop very low stress states (3–10 MPa) that can be either tensile or compressive. However, the data is argumentative for several reasons. Stress states of 3–10 MPa are extremely low and right at the edge of the detection
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capability of XRD equipment. In other words, the measured strains are right at the background noise level of the equipment detection capability. Second, interpreting X-ray diffraction patterns requires certain assumptions about the nature of the stress field, which may not be true. X-ray data interpretation requires an assumption that the stress fields be biaxial (i.e., uniform in at least two perpendicular directions). On a large enough scale (>100-Am square), it is probably a good approximation that the stress fields are biaxial. But when trying to discriminate stress gradients on a very small scale (<10-Am square), it is highly questionable that the stresses are biaxial. 3. Slow Growth Rates of Tin Whiskers Because whisker growth rates are relatively slow metallurgical processes, it is not difficult for modeling approaches to develop a theory that predicts observed growth rates. The relatively fast diffusion rates in dislocations or dislocation networks (e.g., grain boundaries), are more than adequate to provide the required delivery rate of Sn atoms necessary to sustain whisker growth. The transfer rate of Sn atoms from grain-boundary networks into a grain is well known from internal friction studies [56] and is more than adequate to sustain the observed whisker growth rates. Even the relatively high whisker-growth rates reported in clamp-pressure experiments are not considered to be very fast metallurgical processes, and are readily rationalized by a diffusionbased theoretical approach. 4. Validation Required While it is necessary for a theory to account for the observed whisker growth rates, doing so is not proof that a particular theoretical atomistic mechanism is valid. Direct evidence is necessary to validate a proposed theory. Some whisker-growth theories have proposed that dislocations (for dislocation growth theories) or grain boundary networks (for both dislocation and recrystallization theories) become plugged up over time due to diffusion of miscellaneous impurities to those sites [33], thereby restricting or stopping the diffusion of Sn atoms through the dislocations or dislocation networks. Alternatively, some proposals suggest that whisker growth stops when the stresses that drive growth processes have been relieved to the point where the growth processes are deactivated [29]. It would not be unreasonable to presume that both suggestions play a role in the cessation of whisker growth.
D.
FIB Microstructural Analyses of Sn Surface Mounds and Nodules
Most of the earliest published FIB cross-section micrographs of bright-tin, mound-nodule whisker structures [41,47–49] show that whisker and nodule growth is associated with grain structures that are different from the microstructures of the immediately surrounding regions. Fig. 3 shows a 45j view of a surface mound with a crack clearly evident at the upper-left perimeter of the mound. Fig. 25 is a cross-sectional FIB micrograph of the surface-mound in Fig. 3 and it shows a large CuxSny particle (probably Cu6Sn5) at the apex of the mound structure. The plating structure is clearly disturbed immediately around the CuxSny particle, but there is no evidence of any recrystallization in this micrograph. Fig. 26 shows a surface-eruption feature sometimes called a ‘‘bud’’ and Fig. 27 shows the cross-sectional FIB analysis of this ‘‘bud’’ feature with a clearly evident recrystallized structure.
E.
FIB Microstructural Analysis of Whisker Structures
A sequence of FIB cross sections of a bright-Sn whisker-nodule structure is shown in Figs. 28–34. The sequence starts at a slight distance away from the whisker-nodule structure and then incrementally closes to the whisker-module structure to allow an understanding of various features and their location associated with the formation. Fig. 28 is an FIB cross-section taken outside of the whisker-nodule root. A root is the point of origin for the whisker. Figs. 29–34 show FIB cross sections taken progressively closer to the root of the whisker. These micrographs clearly show that the nodule structure is a mass of individual Sn grains that are larger (1–5 Am) than the as-plated grain structure (0.1–0.5 Am). The nodule grains appear to have nucleated from within the as-plated structure, most probably at the clearly evident CuxSny particulates scattered
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FIG. 25 An FIB cross-sectional micrograph of the bright-tin surface mound shown in Fig. 3. Note the large SnCu intermetallic particle at the apex of the mound and the distorted plated structure in the mound microstructure. (Courtesy of G. Galyon and L. Palmer, IBM Corporation.)
in-and-around the nodule mass. These large CuxSny particulates are not evident in the surrounding region. The particular whisker shown in Figs. 28–34 has grown from what appears to be a singular point (i.e., root) in the nodule mass where several grains meet. As the cross sections progress into the root of the nodule-whisker structure, the nodule grains appear to penetrate down into the plating very near to the Sn/Cu interface layer where the Cu6Sn5 IMC layer is located. 1. Key Features Observed in FIB Cross Sections of Bright Sn Films Some of the FIB cross-section micrographs created as part of the Galyon and Palmer study appear to show voids at the Sn–Cu interface. Any theory of whisker-formation and growth must explain the mass transport (i.e., where the Sn comes from) that forms the whisker-nodule structure. The micrographs in Figs. 28–34 do not show any obviously missing Sn in the immediate vicinity of the whisker nodule, so it was reasoned that the Sn comes from a remote region, most likely the Sn–Cu interface layer where voids were evident.
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FIG. 26 A 45j FIB micrograph of a bright-tin surface nodule. (Courtesy of G. Galyon and L. Palmer, IBM Corporation.)
FIG. 27 An FIB cross-sectional micrograph of the bright-tin surface nodule shown in Fig. 26. Note the recrystallized grain structure in the nodule and the numerous SnCu intermetallic particles at the base of the nodule. (Courtesy of G. Galyon and L. Palmer, IBM Corporation.)
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FIG. 28 An FIB cross-sectional micrograph of a bright-tin nodule whisker structure taken just outside of the junction between the nodule-whisker structure and the tin film. The substrate is copper. (Courtesy of G. Galyon and L. Palmer, IBM Corporation.)
FIG. 29 An FIB cross-sectional micrograph of the bright-tin nodule whisker structure shown in Fig. 28 taken somewhat closer to the center of the nodule whisker structure. (Courtesy of G. Galyon and L. Palmer, IBM Corporation).
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FIG. 30 An FIB cross-sectional micrograph of the bright-tin nodule-whisker structure shown in Fig. 29 taken closer to the center of the nodule-whisker structure. In this micrograph, there is a large SnCu intermetallic particle at the base of the nodule. (Courtesy of G. Galyon and L. Palmer, IBM Corporation.)
FIG. 31 A higher-magnification FIB micrograph of the same cross-section shown in Fig. 30. (Courtesy of G. Galyon and L. Palmer, IBM Corporation.)
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FIG. 32 An FIB cross-sectional micrograph of the nodule-whisker structure shown in Figs. 28–31 taken closer to the root of the whisker. Note the penetration of the recrystallized grain structure into the film and the distorted plated structure immediately beneath the nodule structure. (Courtesy of G. Galyon and L. Palmer, IBM Corporation.)
FIG. 33 An FIB cross-sectional micrograph of the nodule-whisker structure shown in Figs. 28–31 taken at the root of the whisker. Note the prominent grain boundary at the root of the whisker that extends down to the as-plated structure. (Courtesy of G. Galyon and L. Palmer, IBM Corporation.)
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FIG. 34 An FIB cross-sectional micrograph of the nodule-whisker structure shown in Figs. 28–33 taken on the far side of the whisker root. (Courtesy of G. Galyon and L. Palmer, IBM Corporation.)
a. Features Visible in FIB Cross Sections Before the Root. In Fig. 28, the FIB trench is outside of the whisker-nodule root. The as-plated structure is columnar in appearance with a disturbed region in the vicinity of two IMC particles immediately beneath the whisker root. The Sn/Cu boundary layer IMC is evident along with two relatively small voids at the Sn/Cu interface. A large CuxSny particle is evident immediately beneath the whisker-nodule root. In the vicinity of the CuxSny particle the vertically oriented as-plated structure was distorted causing the columnar structure to be oriented in a near horizontal direction. The nodule appears to make contact with the plated structure at this point, and there are two voids at the nearby Sn/Cu interface. The whisker itself begins to be evident in Fig. 29. In Fig. 30, the greater part of the nodule is continuous with the as-plated structure. In Figs. 28 and 29, the FIB cross sections show the nodule structure growing over the as-plated structure after erupting through the surface layer. This indicates that these FIB cross sections are within the root of the nodule. The nodule grain structure is clearly evident and extends well down into the asplated microstructure, and it also extends upward beyond the surface of the as-plated structure. Two relatively large CuxSny particles are evident in these micrographs, and the whisker root appears as a point that is in direct contact with a single, vertically oriented grain boundary. A voided area is located at the Sn/Cu interface at the lower right-hand portion of the FIB trench. Fig. 31 shows nodule grains penetrating almost the entire thickness of the as-plated structure, and the whisker root is in direct contact with a grain boundary. In this cross-section there is only one small CuxSny particle in the nodule structure, and that particle is located above the as-plated surface to the left of center. A voided area is evident at the Sn/Cu interface at the lower right-hand side of the FIB trench. 2. Key Features Observed in FIB Cross Sections of Whiskers on Matte-Tin All the FIB cross-sections shown in Figs. 28–34 are bright-Sn nodule-whisker microstructures which are clearly different in appearance from the as-plated microstructure of the immediately surrounding regions. These bright-Sn whiskers grew out of polycrystalline nodule structures that
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nucleated from of the as-plated microstructure. Matte-Sn whiskers appear to grow as a single grain (Fig. 35) that nucleated from within the Sn film
F.
Recrystallization—A Key Feature
Based on the observations described in the preceding section, it appears that bright Sn-whisker growth is fundamentally associated with the metallurgical process called recrystallization. The series of FIB micrographs shown in Figs. 28–34 appear to unequivocally show that, for bright Sn films, recrystallization is a fundamental part of whisker formation and growth. The situation is somewhat more ambivalent for the matte-Sn whiskers. Clearly, the matte-Sn whisker grain appeared different from its surroundings, but it also may have been formed as a result of a solidstate recrystallization process, or during the plating process itself. Therefore, recrystallization cannot be ruled out for matte-Sn whiskers, but it is not clearly evident to be the case from the above FIB micrographs. Fig. 36 is an FIB micrograph of a bright-Sn whisker cross section taken in a dual- beam (SEM/FIB) microscope. The plated structure in the SEM mode is made less evident than in the FIB mode, i.e., the grain structure is washed out. Nevertheless, voids in the plating are clearly evident, as is a lining structure beneath the raised-surface layer and alongside the left-hand side of the whisker filament. An energy-dispersive analysis determined that this lining structure was an intermetallic CuxSny (probably Cu6Sn5). Fig. 37 is a higher-magnification view of the cross section shown in Fig. 36 with the CuxSny lining labeled. This CuxSny lining structure was not seen outside the immediate vicinity of the nodule. It appears that the recrystallizing grains rejected Cu, or precipitated particles of CuSnx, which then formed a film of CuxSny at the surface of the recrystallized region. This CuxSny surface film was then ruptured by the growing whisker-nodule structure. 1. The Integrated Recrystallization Theory Galyon and Palmer [57] detailed a whisker formation and growth theory that integrated various factors such as internal stresses, stress distributions, plating textures, and FIB microstructural analyses with data generated by themselves and others. The key features of the Integrated Recrystallization Theory (IRT) are listed in Table 7.
FIG. 35 An FIB cross-sectional micrograph of a matte-tin whisker structure on a copper substrate. (From Ref. 49.)
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FIG. 36 SEM cross-sectional micrograph of a bright-tin nodule-whisker structure. Note the voids at the interface between the tin film and the copper substrate. (Courtesy of G. Galyon and L. Palmer, IBM Corporation.)
FIG. 37 A higher-magnification SEM micrograph of Fig. 36, the SnCu intermetallic film on the underside of the nodule structure is indicated. (Courtesy of G. Galyon and L. Palmer, IBM Corporation.)
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TABLE 7 Whisker Growth Based on the Integrated Recrystallization Theory (From Ref. 57) with Commentary Key Features Whiskers do not grow from as-plated film structures. They grow from a recrystallized structure that forms locally within the asplated structure. The recrystallized structure is a metallurgical ‘‘event’’ that effects a reduction in the stateof-stress in a localized region of the Sn plating. The recrystallized-grain structure may or may not grow in volume. Growth depends on the relative state-of-stress in the immediate surrounding regions. It is necessary that a positive stress gradient exist between the surrounding region and the recrystallized region. For the recrystallized grain to grow, it is necessary for the stress in the immediate surrounding regions to be more negative than the recrystallized grain structure. The recrystallized structure may or may not form a whisker. A growing nodule may consist of several grains that form what is often called a ‘‘flower’’ or ‘‘bud’’ type of surface eruption. A whisker can nucleate if there is a favorable junction point between two, or more, recrystallized grains. For matte and satin-bright tin films, it appears that the recrystallization event causes a single grain to nucleate. For these single grain recrystallization events, it appears that growth of the recrystallized grain occurs via a filamentary whisker, and not by a flower or bud surface eruption. The growing nodule-whisker structure cracks through the surface oxide layer. It is not necessary for the surface-oxide layer to be weaker at the eruption points. It is merely necessary for the surface oxide to be thin enough so as to permit the pressure exerted by the growing whisker-nodule structure to crack through. Atoms migrate to the whisker-nodule structure from surrounding regions that are more highly compressively stressed. The higher the stress gradient, the higher the whisker growth rate becomes.
Commentary Basis for this statement are the FIB micrographs of bright-tin whisker-nodule cross sections (Figs. 30–36) FIB micrographs indicate that the recrystallized grains may nucleate at CuSn intermetallic particles dispersed throughout the as-plated structure in the immediate vicinity of the nodule structure. Recrystallization can occur in a film that is in a tensile state-of-stress to locally relieve stresses if the surrounding regions are in a lower tensile stress state or if the surrounding regions are in a compressive stress state. It is the stress gradient that matters. No mass transport occurs without a positive stress gradient. The recrystallized-grain structure itself may in compressive, zero, or a tensile-stress state.
Thermodynamically, the growing multigrain nodule will tend to grow a single-crystal filament because it is energetically favorable to do so; most probably due to the elimination of high-energy grain boundaries.
This statement is in contrast to the cracked oxide theory, which surmises that oxides must be locally weak for a whisker to form.
All modern whisker growth theories make similar statements, but do not emphasize a positive stress gradient concept.
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TABLE 7
Continued
Key Features Atoms migrate to the whisker-nodule structure through the grain-boundary network leading to the nodule root. The recrystallized grain structure appears to reject a layer of CuSn precipitates to the surface. When does the recrystallization event occur? The data to date do not allow this question to be answered.
Commentary Most modern whisker growth theories make similar statements. Grain boundary or dislocation diffusion rates are fast compared to bulk diffusion. It is not clear whether this CuSn surface layer is always part of the whisker growth process, or whether it is only there when the conditions are right. It is possible that the recrystallization event occurs at the time of plating or at some later time.
The Galyon and Palmer proposals are an affirmation of the recrystallization concept initially proposed by Ellis et al. [37]. Their basic recrystallization hypothesis is summarized as follows; ‘‘a whisker represents a special recrystallization event that is accompanied by mass transport into the recrystallized region. The nucleating point of a whisker is small and forms by a heterogeneous recrystallization event within the film. The atoms building the whisker are derived by mass transport from the surrounding regions, most probably via grain boundaries. A whisker is the subsequent growth of the recrystallized region out of the free surface, due to the continuing addition of atoms to the base. The driving force for the mass transport of atoms into the recrystallized region is a positive stress gradient (i.e., from negative to positive). The recrystallization event is necessary to develop the necessary positive stress gradient which is the driving force for the growth of nodule-whisker structure.’’
VII. A.
WHISKER FORMATION AND GROWTH BASED ON CRACKED OXIDE THEORY Conditions of Tin Whisker Growth—Cracked Oxide Theory (COT)
There are many intriguing issues concerning whisker growth such as, why do Sn films grow whiskers spontaneously at room temperature, whereas Au films do not? There are also the issues of driving force, kinetics, and specific atomistic mechanism/s associated with whisker growth. The cracked oxide theory (COT), as initially proposed by K.N. Tu [54], addresses these necessary conditions somewhat differently than the above described recrystallization concept. As previously stated, there are three necessary conditions for spontaneous Sn-whisker growth. The first condition is adequate mass transport kinetics at room temperature. This is easily satisfied in the case of Sn because Sn has a low melting point and, therefore, grain boundary diffusion in Sn at room temperature is adequate to sustain the observed whisker growth rates (typically 0.01–0.10 Am/sec). The second condition is a driving force. The COT theory defines the driving forces as a combination of chemical affinities and mechanical stresses that combine in a way to cause a compressive stress state. The third condition in the COT theory is a surface oxide layer that is locally weak or defective in some way. The following sections discuss the individual aspects of the COT theory (compressive stress, surface oxide, microstructure, composition, and morphology).
B.
Compressive Stress as the Driving Force for Tin Whisker Growth
The growth of a whisker relieves a compressive stress in the matrix on which they grow. Whiskers are known to grow from the bottom, not from the top. This is deduced from the fact that the
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morphology of the tip does not change during the growth. Also, for a kinked whisker, that part of the whisker below the kink grows longer. Whisker growth, therefore, results from a region that is in compression causing a localized area on the surface to push upward (i.e., from a protrusion). 1. Chemical Reaction Induced Force The origin of the compressive stress can be mechanical, thermal, chemical, or any combination thereof. Chemical forces are a result of a reaction between Sn and Cu at room temperature to form an intermetallic (IMC) compound Cu6Sn5. The diffusion of Cu from the substrate into the Sn film generates a compressive stress in the Sn. Details of the IMC formation and stress generation are discussed in Sections 1 and 2. A compressive stress in Sn can, at room temperatures, be relaxed by atomic rearrangement via grain boundary diffusion. Relaxation occurs by the removal of atom layers normal to the stress. The Sn atoms diffuse along grain boundaries to the whisker root forcing the whisker grain upward, i.e., causing a whisker to be pushed out from the surface by adding to its growth from the bottom. Hence, whisker growth is driven by a compressive stress and, as noted earlier, is a stress-relief phenomenon. Because the reaction of Sn and Cu can occur at room temperature, the reaction continues for as long as free Sn and Cu atoms are available. The continuing growth of the Cu6Sn5 IMC maintains a compressive stress that keeps whiskers growing. The balance between stress relaxation and the stresses generated by the continuing generation of Cu6Sn5 IMC maintains a near linear whisker growth rate. The film stress due to the chemical force can be expressed by Eq. (1), where V is the specific volume of the Sn layer, B is the bulk modulus of elasticity for the film, and X is the partial molar volume of a single Cu atom in the Cu6Sn5 intermetallic compound, X ð1Þ V The negative sign indicates that the stress resulting from the chemical force is compressive. If n Cu atoms diffuse into the volume segment V, the stress will increase accordingly by replacing X with nX in the above equation. To release the stress, Sn atoms must diffuse out of the volume V and diffuse to the whisker base. The subsequent whisker growth will correspond to the continuing diffusion process initiated by the stress buildup per Eq. (1). r ¼ B
2. Dominance of the Reaction-Induced Force Sometimes it is puzzling to note that Sn whiskers seem to grow on Sn films under a tensile force [47]. For example, Sn plated on a Cu lead frame typically exhibits a tensile stress state immediately after plating, yet whiskers subsequently grow on these finishes. It has also been observed that a fused Sn plating (i.e., a reflowed electroplated Sn film) on a Cu lead frame also grew Sn whiskers. The fused Sn film is initially in a tensile stress state. The tension condition results from the fact that Sn has a higher thermal expansion coefficient than Cu, thus the Sn layer should be under tension after a reflow cycle. When a lead frame (or any substrate) is bent, one side is in tension and the other is in compression. Whiskers have been observed on both the tensile and compressive sides of bent samples. These observations at first appear to be inconsistent with the aforementioned COT condition for whisker growth relative to compressive stresses. However, thermally or mechanically induced stresses, whether in tension or compression, are finite and can be quickly relaxed by atomic diffusion at room temperature in Sn-based solders. The continuing chemical reaction between the substrate material (e.g., Cu) and the Sn film develops and maintains the compressive stress condition necessary to grow whiskers. These observations demonstrate that the chemical force ultimately is dominant as regards the creation of internal stresses. Accordingly, when considering the driving force of spontaneous whisker growth on Sn, or any plated finish on Cu, a key aspect of the cracked oxide theory is that a compressive stress is necessary for tin whisker formation and growth, and that these compressive stresses result mainly from a chemical reaction between the reactive species of the substrate (e.g., Cu) and the plated film (e.g., Sn). a. Room Temperature Reaction Between Tin and Copper. The room temperature reaction between Sn and Cu was studied [46] by depositing Sn and Sn over Cu films onto a quartz substrate using e-beam evaporation and resistance heating techniques. Both films (Sn on quartz and Sn over Cu) were deposited on quartz disks 1 in. in diameter and 1/16 in. in thickness. The thicknesses of
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CHOI ET AL.
the Cu and Sn layers varied from 0.2 to 0.6 Am and from 0.4 to 2.5 Am, respectively. The samples were maintained at room temperature up to 1 year. Whiskers were observed on the surface of the Sn over Cu on quartz, but no whiskers were observed for the Sn on quartz. As these samples were deposited and kept at room temperature, there were no thermally induced stresses. Also, because the quartz was very thick, there were no mechanically induced stresses due to bending. All the internal stresses were the result of chemical interactions between the Cu and the Sn. X-ray diffraction analysis was carried out for the Sn/Cu/quartz samples (Fig. 38) and peaks for Cu, Sn, and Cu6Sn5 were found. The same was found for similar samples annealed at 60jC. At annealing temperatures of 80jC, X-ray spectra showed the presence of both Cu6Sn5 and Cu3Sn. No intermetallic compounds of any kind were detected on any of the Sn-on-quartz samples, annealed or not. It was noted that the Cu6Sn5 growth rate, as measured by X-ray intensity changes over time, did not fit the parabolic law of diffusion-controlled growth. No morphology of the Cu6Sn5 was studied by cross-sectional microscopy. During the growth of Cu6Sn5 the dominant (i.e., faster) diffusing species was determined to be Cu by using an ultra thin film of tungsten as a marker. The density of whiskers was determined to be about 103–104 whiskers/cm2, with a spacing of about several hundred microns. The average growth rate of whiskers was about 0.2108 cm/sec. Using the glancing incidence X-ray diffraction method, the Sn layer was found to be under compression. 3. Role of Surface Oxide on Sn and Sn Alloy Film Surfaces In the cracked oxide theory, a compressive stress is a necessary, but insufficient, condition for whisker growth. The presence of an oxide on the Sn surface is also necessary. An analogy with experiments on Aluminum (Al) was made to substantiate the critical aspect of a surface oxide on whisker formation. In an ultrahigh vacuum, no nodules were found to grow on Al surfaces under compression [58]. Nodules grew on Al only if the surface was oxidized, probably because a free surface without an oxide is a good source and sink for vacancies. An oxide-free surface on a deposited film allows stresses to be uniformly relieved on the basis of the Nabarro–Herring creep model. In the Nabarro–Herring creep model, relaxation occurs in each individual grain, so stress relaxation is uniform over the entire surface. If stress relaxation is uniform across an entire film surface, no localized growth of nodules or whiskers can occur. Whisker growth is considered to be a localized stress-relief phenomenon. To establish and maintain localized growth, the surface cannot be oxide-free. The oxide layer must be a protective oxide and effectively block all the vacancy sources and sinks on the surface. Hence, only those metals that grow a protective oxide,
FIG. 38 X-ray diffraction spectra of a bimetallic Sn/Cu thin film maintained at room temperature for 1 year. The diffraction peaks of Cu, Sn, and Cu6Sn5 are identified. (From Ref. 40.)
STRUCTURE AND KINETICS OF TIN-WHISKER
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such as Al and Sn, are known to have nodule or whisker growth. Noble metals, such as Au, do not oxidize and do not grow nodules or whiskers. a. Requires Weak Spots. On the other hand, the cracked oxide theory also holds that a very thick surface oxide can physically block the growth of nodules or whiskers because a very thick oxide cannot be penetrated. Thus, a second necessary COT condition for whisker growth is that a protective surface oxide must be sufficiently thin at certain locations on the surface to create weak spots that can be broken by an erupting whisker. b. Role of Oxide-Free Regions. Any oxide-free surface is an effective source and sink of vacancies and, under compression, the surface of every oxide-free grain can provide the vacancies needed to relax the local stress state. Fig. 39(a) is a schematic diagram depicting the flux of atom movement (arrows in each grain) of a polycrystalline thin film under compression. The stress is relieved via lattice diffusion via the Nabarro–Herring creep model. Alternatively, the movement of atoms can be achieved by grain boundary diffusion on the basis of the Coble creep model. With either the Nabarro–Herring or Coble creep models, relaxation is homogeneous with no localized growth of nodules or whiskers. As previously shown, polycrystalline aluminum (Al) thin films deposited and compressively stressed in an ultrahigh vacuum do not form nodules. Yet, when the same Al films are exposed to ambient and stressed again, nodules form [59]. c. Presence of Surface Oxide on Sn Films. In an ambient environment, Sn forms an oxide that is known to be very stable and protective, which means a low-energy interface exists between the oxide and metal. This also implies that the interface is not a good source and sink of vacancies because when films with such oxides are compressively stressed, the Nabarro–Herring model of defect formation does not operate effectively. In other words, for Sn films with a surface oxide, the
FIG. 39 A schematic diagram of the cross section of a polycrystalline Al thin film under compression. (a) The arrows indicate the flow of atoms to relieve the stress on the basis of the Nabarro–Herring or Coble creep models in the case where there is no surface oxide. (b) If a surface oxide exists, stress relief is only possible if it can be broken locally and penetrated. (Courtesy of UCLA.)
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CHOI ET AL.
surface is not an adequate source of vacancies for stress relief. To provide stress relief locally, the surface oxide must be broken through as depicted in Fig. 39(b). Sheng et al. [47] used a focused ion beam (FIB) to sputter the surface oxide on a Sn–Cu film and expose the underlying microstructure. Fig. 40(a) shows an FIB image of a eutectic Sn–Cu film with several whiskers evident. Most of the whiskers are straight, but some of them are bent at sharp angles. In Fig. 40(b), the oxide on a rectangular area was sputtered away to expose the microstructure beneath the oxide. The thickness of the oxide was not measured. The sputtered area appears darker than the surrounding unsputtered area because the contrast in an FIB image depends on the degree of ion channeling. The image appears dark when there is a high degree of channeling and bright when there are more backscattered ions. Surface oxide and IMC particles generate more backscattered ions in the FIB image. Many bright images of Cu6Sn5 particles are observed in the sputtered area of Fig. 40(b). d. Many Cu6Sn5 Particles in Sn–Cu Grain Boundaries (COT). In Fig. 40(c), a highermagnification image of the sputtered area is shown, in which the microstructure of Sn grains and Cu6Sn5 grain boundary precipitates are clear. Because of the channeling effect, some Sn grains
FIG. 40 FIB images of whiskers on a eutectic Sn–Cu surface. (a) FIB image of a set of long whiskers on the Sn–Cu surface. (b) FIB image of the same area shown in (a) with a rectangular area sputter cleaned of surface oxide. The sputtered area appears darker than the surrounding area. Many bright particles of Cu6Sn5 can be seen on the surface of the sputtered area. (c) An enlarged FIB image of the microstructure in the sputtered area. The grain structure in the Sn matrix is clear, and the Cu6Sn5 particles are noted to be located in the Sn grain boundaries. (From Ref. 47.)
STRUCTURE AND KINETICS OF TIN-WHISKER
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appear darker than the others. The Cu6Sn5 particles distributed along grain boundaries are brighter than the Sn grains due to channeling. In Fig. 40(c), it is evident that the diameter of the whisker (approximately a few microns) is comparable to the grain size of the Sn–Cu finish. Based on Fig. 40(a) and (b), Sheng et al. [47] concluded that there was a surface oxide on the Sn–Cu finish and that Cu6Sn5 precipitates reached the interface between the Sn–Cu finish and the surface oxide. e. Few Cu6Sn5 Particles in Sn Grain Boundaries (COT). In Fig. 41(a) and (b), FIB images of a pure Sn surface are shown before and after sputtering away the surface oxide on the Sn surface. Several short Sn whiskers can be seen on the surface. After the surface oxide was removed (Fig. 4b), the Sn microstructure was revealed. The film grain size was about the same as the diameter of the short whiskers, indicating that the growth of these whiskers occurred by pushing up an existing Sn grain from the film. However, compared to the sputtered eutectic Sn– Cu surface shown in Fig. 40(c), many fewer Cu6Sn5 IMC particles are noted in the case of whisker growth on pure Sn.
C.
Role of Surface Oxide on Tin Whiskers
According to the COT hypothesis, an oxide on a whisker serves two very important purposes. The first is that an oxide surface layer limits lateral growth so that a whisker has a constant crosssection during growth. The second is that the oxide reduces the surface energy of a whisker and defines the whisker diameter. As a general statement, the overall driving force for whisker growth is a net reduction of strain energy. The whisker itself is generally considered to be strain-free, but whisker growth does result in an increase in total surface area. The balance between reduction in strain energy and increased surface energy defines the overall size of a whisker. The surface oxide on a Sn film cannot completely cover the surface. If the oxide did cover the surface of the whisker grain, a whisker could not grow, because there would not be a place for vacancies to form. Fig. 42(a) depicts a thick surface oxide on a Sn surface that blocks the growth of whiskers even when the Sn is under compression. For a compressive stress in the film to be released, the oxide at certain localized areas of the Sn surface must be capable of being broken. Stress relief takes place at these breakable locations, and whisker growth occurs as the result of stress relief. The surface of whiskers should be oxidized. To sustain growth, the whisker base must remain oxide-free, as illustrated in Fig. 42(b), so that vacancies can be continuously supplied to the grains thereby sustaining the long-range diffusion of Sn atoms to the whisker site. Many whiskers are bent or kinked. The cracked oxide theory (COT) rationalizes whisker bends as a process for healing one side of the crack at the base of a whisker. A stress gradient may be radially unsymmetrical around the base of a whisker resulting in a much smaller supply of vacancies at those points and whose stress gradients are correspondingly smaller as well. Whisker growth will be slower at those points with lower vacancy concentrations. COT assumes that when whisker growth is sufficiently slow, an oxide crack may have time to heal. Whisker growth will stop on the healed side, causing the whisker to bend as the opposite side continues to grow. 1. The Structural Difference Hypothesis Whisker growth occurs at certain spots on a Sn surface. Proponents of the COT hypothesis [54] wanted to understand why these whisker spots were unique, and specifically why the surface oxide at particular whisker locations was breakable. They felt that the Sn microstructure at these spots should be different from the surrounding regions. Specifically, they believed that a structural discontinuity should exist at these whisker spots which allowed the surface oxide to be easily broken. They further reasoned that Sn films with a preferred-orientation texture have a few surface grains with orientations different from the predominant texture orientation, and these different surface grains represented a discontinuity in the uniformity of the oxide layer. They reasoned that these surface grains, under compressive stress, could become a whisker grain because the acting stress would push Sn atoms through the surface oxide along the grain boundaries between the discontinuity grain and its surroundings.
902 D.
CHOI ET AL. A Kinetic Model of Tin Whisker Growth
By ignoring the specifics of the atomistic mechanism (dislocation, recrystallization, cracked oxide, etc.), Choi et al. constructed a generalized mathematical model that related the dynamics of whisker growth to a stress factor (the driving force) and diffusion constants that are determining factors in the kinetics of whisker growth. Assuming a whisker diameter of 2a and a whisker-to-whisker separation of 2b, the steadystate growth in a diffusional field can be described by a two-dimensional continuity equation in cylindrical coordinates as represented in Fig. 43. Stress can be regarded as an energy density that obeys the continuity equation,
j2 r ¼
B2 r 1 Br ¼0 þ Br2 r Br
ð2Þ
The boundary conditions are r=r0 at r=b, and r=0 at r=a.
FIG. 41 FIB images of whiskers on a Sn surface. (a) FIB images of short whiskers on pure Sn surface. (b) FIB image of the same area shown in (a) after sputtering the surface oxide away. The Sn grain structure is exposed, and it can be seen that very few Cu6Sn5 particles are on the sputtered surface compared to the Sn–Cu surfaces of Fig. 40(c). (From Ref. 47.)
STRUCTURE AND KINETICS OF TIN-WHISKER
903
FIG. 42 A schematic diagram of the cross section of bimetallic Cu/Sn thin films forming the compound Cu6Sn5. (a) The surface of the Sn layer is oxidized. (b) A break in the tin oxide allows a Sn whisker to protrude. The whisker is oxidized except at the base where the oxide is broken. A flux of Sn is indicated by arrows in the Sn film. (From Ref. 54.)
FIG. 43 A schematic diagram illustrating the growth of whiskers of diameter 2a and a separation of 2b on a planar surface. Typically, a = 3 Am, b = 0.1 mm, r0X = 0.01 eV (at r0 = 0.7109 dyne/cm2), kT = 0.025 eV at room temperature, s = 0.3 nm, and D = 108 cm2/sec, where D is the self-grain boundary diffusivity of Sn at room temperature. (From Ref. 54.)
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CHOI ET AL.
The solution to Eq. (2) is r=Br0 ln(r/a), where B=[ln(BA)]1, where r0 is the average stress in the Sn film. Knowing the stress distribution, the driving force can be evaluated as follows. BrX ð3Þ Br where X is the atomic volume. The flux necessary to grow a whisker is calculated at r=a, using the following equation, Xr ¼
J¼C
D Br0 D Xr ¼ kT kT a2
ð4Þ
For a pure metal, C=1/X. The volume of material transported to the root of a whisker in a period of time (dt) is calculated as, JAdtX ¼ pa2 dh
ð5Þ
In Eq. (5), A=2pas and is defined as the peripheral area of the growth step at the root, s is the step height, and dh is the incremental increase in whisker height over the time interval dt. Therefore, the growth rate of a whisker can be expressed as, dh 2 r0 XsD ¼ dt lnðb=aÞ kT a2
ð6Þ
Using Eq. (6) (above), whisker growth rates can be determined for typical parameter values based on the model of Fig. 43. For example, dh 2 2 0:01 eV 3 108 cm 108 cm2 =sec ¼ ¼ 4 2 dt lnðb=aÞ lnð3 10 cm=1 10 cmÞ 0:025 eV ð3 104 cmÞ2 ¼ 7:6 10
10
ð7Þ
cm=sec
A whisker growth rate of 7.61010 cm/sec, which correlates to a whisker length of 0.24 mm after 1 year, agrees well with experimental observations. It should be noted that in the above calculation, the stress gradient is quite small because of the large value of b. a. Whisker Growth with Few Grain Boundaries. The Choi et al. [42] study assumed grain boundary diffusion. In their microstructural analysis, they observed relatively few grain boundaries connecting the whisker base to the underlying Sn microstructure. Hence, in taking the total atomic flux that supplies the growth of a whisker to be JAdtX, where A=2pas, they assumed that the flux goes to the entire periphery of a whisker 2pa, but only for a step height of s for its growth.
VIII.
MASS TRANSPORT OF TIN
For as-plated structures, the volume of Sn whisker-nodule structures is considerable in relation to the volume of each individual grain. Therefore, it is not a matter of a single grain being converted to a whisker-nodule structure because there is no sufficient volume of material in single grains to account for the material that comprises a whisker. It is essential that Sn atoms migrate to the whisker-nodule structure from regions adjacent to, or remote from, the whisker-nodule structure itself. That is to say that there must be a net mass transport of atoms to the whisker grain. This basic tenet has been recognized by all published whisker research for over 50 years. However, experimental evidence substantiating the net mass transport of Sn atoms has been minimal until recently.
A.
Radioactive Tracer Studies
Radioactive-tracer experiments were conducted to determine the origin of whisker atoms [60]. Evaporation deposition was used to prepare Sn film samples. A layer of radioactive Sn was deposited locally on a substrate, and a covering layer of inactive Sn was then deposited over the
STRUCTURE AND KINETICS OF TIN-WHISKER
905
FIG. 44 A schematic diagram of a tin-whisker experiment, in which radioactive tin was used to show that the whisker material came from tin that was originally located at the tin/film substrate interface. (From Ref. 60.)
entire substrate, including the previously deposited active layer. Fig. 44 is a schematic representation of the experimental setup. The whiskers immediately over the radioactive sublayer were found to contain radioactive Sn, whereas the whiskers immediately over the inactive Sn were not radioactive. The same results were obtained when the layers were deposited in the opposite sequence. These results demonstrated that material transport normal to the substrate must have taken place during whisker formation, while no large-scale diffusion parallel to the substrate had occurred.
B.
Voids
To further substantiate the source of Sn atoms for whisker formation, it is necessary to demonstrate that voids, which can be considered a grouping of vacancies, are at locations where the Sn-whisker atoms originated. It has been reported [61] that remote surface-grain subsidence in regions immediately adjacent to whiskers was observed, as illustrated in the SEM micrographs of Figs. 45 and 46. The study also noted that grain boundaries between the subsided-grain and the whisker appeared to be depleted of material. These particular results were obtained on matte Sn and indicated that for these samples the whisker grew by adding Sn atoms that came from adjacent and remote grains via grain boundaries. Galyon and Palmer [57] did not observe any evidence of remote surface-grain subsidence in their analysis of bright-Sn whiskers, nor is there any awareness of other investigations having observed remote-grain subsidence. Galyon and Palmer did observe voiding at the Sn/Cu
FIG. 45 SEM micrograph of a whisker grown on matte tin deposited over copper showing remote subsidence. The arrows indicate the subsided grains. (From Ref. 61.)
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FIG. 46 SEM micrograph of a whisker grown on matte tin deposited over copper showing a subsided grain next to the whisker and depleted grain boundaries (white arrows) leading to the subsided grain. The dark arrows show normal grain boundaries. (From Ref. 61.)
substrate interface (Figs. 28–34), which could infer that these are the voided areas from which the whisker Sn atoms originated. To further investigate these Sn/Cu interface voids a three-dimensional FIB-trench analysis (Fig. 47) was performed on the growth mound shown in Fig. 26. Small voids were found underneath and around the periphery of the nodule structure within a radius of about 15–20 Am. The total volume of the voids was more than sufficient to account for the material contained in the growth-nodule. These results indicate that bright-Sn whisker-nodule
FIG. 47 A 45j FIB micrograph of the tin nodule shown in Fig. 46, which has been milled out on three sides by an FIB beam to show the microstructure of the tin film in regions around the nodule structure. Note the voiding evident at the film/substrate interface. (Courtesy of G. Galyon and L. Palmer, IBM Corporation.)
STRUCTURE AND KINETICS OF TIN-WHISKER
907
atoms probably came from highly stressed regions located at or very near to the Cu/Sn substrate interface, and from within 2–30 Am radius of the whisker-nodule structure. Voids were also observed at the Cu/Sn interface region in plan view FIB cross sections, where the milling was parallel to the film plane. The voiding observed in the Galyon and Palmer study would be consistent with the observations made in the aforementioned radioactive Sn experiments [60].
IX.
SUMMARY OF TIN-WHISKER MITIGATION PRACTICES
The user community should exercise great care in using any high-concentration (>95%) Sn electroplating. The application conditions must be understood as regards to temperature, humidity, expected length of service, critical spacings between adjacent circuit features under electrical bias, and the required reliability performance. The use of high-Sn content platings will require a trade off between cost and reliability. It is true that Sn platings have been used in many applications with great success, and with no evident whisker problems. But it is also true that there have been some significant and costly failures involving high-Sn content platings that grew whiskers and caused shorts in electrical circuitry. Users should seek expert advice before utilizing high-Sn content platings in critical applications. A list of mitigation practices, with no guarantees, is presented below: 1. Use alternative platings such as nickel (Ni)–palladium (Pd)–gold (Au)—Lead-frame finishes of Ni–Pd–Au have been successfully utilized in large quantities since 1992. This plating will not pass the relatively severe mixed-flowing corrosive gas tests required for some applications, but users must determine if this is a reasonable or necessary requirement because many commercial applications (e.g., business office environments) do not require meeting the harsh conditions imposed by a mixed-flowing gas test. The Au surface finish may be eliminated if long-term storage in uncontrolled environments is not an issue although it is often advisable to retain the Au layer because it promotes solder wettability. The solderability of Ni–Pd–Au with Pb-free tin–silver–copper (SAC) solders seems not to be an issue. 2. Fused Sn—Fused Sn lead-frame finishes were used for many years without any reported whisker problems. However, fused Sn will grow whiskers if scratched. 3. Tin over a Ni underlay (for Cu and Cu alloy substrates only—i.e, Sn/Ni/Cu)— Bright Sn over a Ni underlay on Cu substrates has been used for many years by a major electronics manufacturer without any reported whiskering problems. However, experiments have demonstrated that whiskers can be grown on Sn/Ni/Cu when subjected to accelerated thermal cycling, or when stored at 60jC/95% RH [49]. These whiskers are generally shorter (<100 Am, usually less than 10 Am) than the spacing between the finest-pitch lead frames (f125 Am). Barrel-plated Sn–Ni films have been used since 1992 on multilayer ceramic capacitors (MLCCs) without any reported field problems. However, laboratory studies on barrel-plated Sn/Ni/Ag MLCC end terminations have shown that thermal cycling can result in whiskers over 100 Am in length. 4. Annealed tin electroplate—Annealing heat treatments have been found to only be useful on matte-Sn platings. Bright-Sn platings tend to blister when annealed. Annealing is often an impractical solution but should be considered for matte-Sn plated structures where annealing at 150–200jC for an hour or more is practical. 5. Matte tin without an underlay—Some manufacturers claim that matte Sn without an underlay will provide whisker-free results. A National Electrical Manufacturer’s Initiative (NEMI) study has demonstrated whisker growth in matte Sn under conditions of accelerated thermal cycling or prolonged storage at 60jC. These whiskers were typically less than 100 Am in length. Use of matte-Sn platings should be carried out only with expert advice and great care. Matte-Sn finishes are not recommended for longterm, high-reliability, mission-critical applications.
908
CHOI ET AL. 6. Satin-bright tin without an underlay—Satin-bright Sn without an underlay should be considered riskier than matte Sn, but somewhat less risky than bright Sn. There are documented reports of satin-bright tin platings growing long (>100 Am) whiskers in less than 3 months. Use of satin-bright Sn platings should only be carried out done(with expert advice and great care. 7. Bright tin—Bright Sn without an underlay is prone to growing long (100–300 Am) whiskers in normal (i.e., ambient) service conditions, and is not recommended for any application sensitive to whisker growth. Bright Sn over a Ni underlay has been used successfully by a major electronics manufacturer as a bus-bar and heat-sink finish without any known evidence of whisker growth. 8. Immersion tin—Immersion Sn is a relatively unstudied entity. Data from a major electronics manufacturing firm on the use of immersion Sn platings is encouraging. There were no reported Sn whisker problems in field service where the environments were relatively controlled (e.g., a typical office or computer room). Some published reports have indicated that immersion Sn films on printed circuit boards have grown whiskers inside the barrels of the plated through holes, but not on the surface film. It has very recently been reported that 0.6-Am-thick immersion-Sn films on copperfoil substrates have grown whiskers 10–15 Am in length within 60 days [62]. Use of immersion-Sn films should only be carried out with expert advice and great care.
X.
ACCELERATED TESTING
A.
Accelerated Test Considerations
There is no industry standard acceleration test to characterize the whisker-formation capability of a given film. Accelerated tests are typically performed at elevated temperatures to increase the reaction kinetics. For Sn films, it is necessary to keep the temperature below about 80jC to avoid the creation of intermetallics compounds (Cu3Sn) not seen at lower temperatures. At these lower temperatures whisker growth rates are still quite slow. At temperatures above 80jC, diffusion is much faster but the microstructure is not equivalent to the room temperature microstructure as a result of the formation of the Cu3Sn intermetallic compound. In addition, at higher temperatures the stresses are relieved quicker due to creep mechanisms, which decreases the driving force necessary for whisker formation. Hence, there exists a tradeoff between driving force and kinetics in standard temperature-based acceleration testing.
B.
Electromigration as a Whisker Formation Acceleration Test
The use of electromigration for conducting an accelerated test of Sn whisker growth has been suggested [42] by utilizing the classic Blech electromigration test [58] with Al films on a titanium nitride (TiN) base. In this test, Al atoms are current driven from the cathode to anode, which results in a compressive stress at the anode accompanied by nodule growth. The reader is directed to Chapter 20 of this book for a detailed discussion of electromigration. The potential advantage of electromigration as a means to determine sensitivity for Sn-whisker growth is that the driving force (current density) and the kinetic parameter (test temperatures) can be controlled independently. 1. Test and Model for Whisker Formation and Growth Fig. 48(a)–(d) shows the growth of a Sn whisker at the anode of a pure Sn Blech test sample under electromigration conditions. Measuring the growth rate and diameter of a whisker over time provides the volume change per unit time, V ¼ JAdtX;
ð8Þ
STRUCTURE AND KINETICS OF TIN-WHISKER
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FIG. 48 Growth of a Sn whisker at the anode of a test sample of pure Sn under electromigration at 150jC and 105 A/cm2 for: (a) 20 hr, (b) 40 hr, (c) 60 hr, (d) 80 hr. (Courtesy of W. Choi, UCLA.)
where J is the electromigration flux, A is the cross section of the whisker, dt is unit time, and X is the atomic volume. The stress driving the growth of a whisker can then be determined from Eq. (6). Knowing J, Z* can thus be determined because J¼C
D kT
drX þ Z*ejq dx
ð9Þ
where C=1/X in pure Sn, D is diffusivity, kT is thermal energy, r is the stress at the anode, dr/dx is the stress gradient along the short strip of Sn of length of dx, Z* is the effective charge number of the diffusing Sn atoms in electromigration, e is the electron charge, j is the current density, r is the resistivity of Sn at the test temperature, and it is assumed that the stress at the cathode is zero. The stress, r, can be determined from Eq. (5), and the value of Z* can be determined from Eq. (9) because all other parameters are known. It is difficult to measure the size and volume of an irregularly shaped nodule emerging from the surface of a deposited film. According to Choi et al. [42], regularly shaped nodules of constant cross section can be obtained from the Blech test by depositing a thin coating of quartz over the entire Sn strip and then etching holes of given diameter at the anode, as depicted in Fig. 49(a) and (b). An applied current then causes whiskers to be pushed out from the holes etched at the anode end of the film. Using this technique, the growth rate of a whisker can be measured as a function of current density, temperature, time, and distance from the anode. The authors [42] also noted that it was possible to replace the Sn strip with eutectic Sn–Cu, or any other composition strip, for a comparison of whisker formation characteristics. However, this electromigration test may not be meaningful until it can be confirmed that a whisker
910
CHOI ET AL.
FIG. 49 (a) A schematic diagram of the cross section of a Sn strip deposited on a TiN baseline, coated with a sputtered quartz film and with holes etched at the anode. (b) Under electromigration conditions, Sn whiskers push out of the holes. (From Ref. 42.)
driven by electromigration has the same basic atomistic growth mechanism as a spontaneously grown whisker.
XI.
SUMMARY AND FUTURE OUTLOOK
A.
Dislocation-Based Theories
As yet, there is no consensus within the scientific community on a model for whisker formation and growth. Dislocation theories should probably be regarded as nonessential, as was admitted by F.C. Frank, one of the original proponents of dislocation-based whisker growth [36]. The main objection to a dislocation-based whisker theory is that not all of the whisker growth directions are parallel to glide planes.
B.
Recrystallization and Cracked Oxide Theories
The recrystallization and cracked-oxide concepts are not necessarily contradictory. Recrystallization postulates a localized recrystallization event that causes the Sn oxide layer to crack from pressure exerted by the growing whisker nodule. The cracked oxide theory (COT) states that a locally weak oxide layer allows a whisker nodule to form and grow, thereby relieving the local stresses. However, the COT concept require the metal to be an oxide former. Oxide-free metal surfaces, such as gold, act as sinks for interstitial Sn atoms and lattice vacancies, and all internal stresses would tend to be uniformly relieved across the entire surface layer. Local relief mechanisms, such as whisker-nodule formation, are not be necessary. Recrystallization and cracked-oxide concepts both recognize that heavily oxidized surfaces act to prevent whiskernodule growth because of the strength of the oxide layer. One of the authors (G. Galyon) favors the recrystallization concept because experimental data shows that grains from which the whiskers grow always appear ‘‘different’’ than as-plated microstructures, and in some cases (bright Sn) the whiskers grow from grain structures that exhibit the classical appearance of recrystallized structures. There is, as yet, no direct experimental evidence for the existence of weak-oxide layers prior to whisker formation and growth. Most theoretical proposals for whisker formation recognize compressive stresses as the driving force behind whisker growth. The
STRUCTURE AND KINETICS OF TIN-WHISKER
911
Galyon–Palmer Integrated Recrystallization Theory is somewhat different because it recognizes a positive stress gradient, rather than a compressive stress, as the driving force. The stresses in a film could be entirely tensile, but if a localized positive stress gradient exists across a microstructurally recognizable boundary separating a surface grain from the surrounding region, whiskers or nodules can grow.
C.
Observations Differ Depending on Type of Tin Deposit
It seems clear from focused ion beam (FIB) microstructural analysis, energy-dispersive analysis, and cantilever-beam stress data that integration of multiple concepts is necessary to explain the various phenomena observed in whisker formation and growth. Recrystallization appears to play a role in bright-Sn whisker formation [57], whereas in matte Sn it remains to be seen if whiskers growth involves a recrystallization event. Matte-Sn microstructures often show large variations in as-plated morphologies, and some matte-Sn microstructures are quite similar to columnar bright-Sn microstructures; while other matte-Sn structures have been observed to consist of large, well-polygonized structures. Some preliminary data appears to indicate that even well-polygonized structures can grow whiskers under certain test conditions (e.g., temperature cycling or storage at 60jC/95% RH). An FIB cross section of a Sn whisker grown from well-polygonized matte-Sn under accelerated thermal cycle testing (45 to +65jC) is shown in Fig. 35. The appearance of the grain from which the whisker has grown is different than the grains of the immediately surrounding region. However, it is not clear whether the different appearing grain formed as a result of recrystallization subsequent to plating or formed during the plating process. Additional investigation should be directed at these large-grained, matte-Sn plated structures. It is not unreasonable that these different appearing matte-Sn grains from which the whiskers grew were caused by a localized recrystallization event, either during or after plating. This could occur in a manner similar to the formation of the nodule-whisker structures observed in bright-Sn films. Analyses of fused and immersion-Sn microstructures should be a subject of future research. Data on fused Sn indicates it is necessary to cold work the as-plated structure before whiskers will grow. A microstructural assessment of fused and immersion-Sn structures would be helpful in clarifying the modeling issues.
ACKNOWLEDGMENTS The authors Choi, Lee, and Tu would like to thank the Semiconductor Research Corporation contract #NJ-853 (Dr. Harold Hosack), and National Semiconductor Corporation (Dr. Luu Nguyen) for the financial support for the research described in this chapter. The authors would also like to thank George T.T. Sheng and C.F. Hu at Macronix International Company, Hsinchu, Taiwan, for some of the focus ion beam images of Sn whiskers. They would also like to thank N. Tamura at Advanced Light Source, Lawrence Berkeley National Laboratory for X-ray microdiffraction study of Sn whiskers. George Galyon would like to acknowledge the advice and counsel of a number of people in constructing portions of this chapter. To Dr. Karl Puttlitz of IBM for his leadership in lead elimination within IBM, and his encouragement of Sn-whisker research as an active member of NEMI (National Electrical Manufacturer’s Initiative Consortia). To Ron Gedney for his leadership as the NEMI coordinator of three Sn-whisker committees, one on modeling, one on User concerns, and one on the development of accelerated testing for Sn-whisker formation and growth. To my NEMI colleagues on the Whisker Modeling and USER GROUP Committees; Irina Boguslavsky, Peter Bush at SUNY, S. Lal at FCI, Chen Xu at Cookson Electronics, Maureen Williams at NIST, Valeska Schroeder at HP, Joe Smetana at Alcatel, Jack McCullen at Intel, Nick Vo at Motorola, Ben Huang at Indium Corp., Jim Martin and Neil Brown at Shipley, B. Radharkrishnan at Oak Ridge National Laboratories, Don Abbott and Doug Romm at TI, Ben Huang at Indium Corp., Rick Coyle at Lucent Corp., Dave Love at Sun Microsystems, Rick Charboneau at Storage Tek, Lynda Anderson at IBM, and Rich Parker at
912
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Delphi Electronics. . .thanks for the many stimulating discussions and insights. To Larry Palmer, my colleague at IBM Server Group, whose skill and initiatives produced many of the FIB microstructural cross section so useful in advancing the knowledge base on Sn-whisker formation and growth.
REFERENCES 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33.
Arnold, S.M. The growth and properties of metal whiskers. Proc. Am. Electroplaters Soc. 1956, 43, 26–31. Arnold, S.M. The growth of metal whiskers on electrical components. Proc. Elec. Components Conference; 1959; 75–82. Hedlund, L. Private communication: IBM Materials and Process Engineering Dept., eServer Group, Rochester, MN. Gutierrez, S. Private communication, IBM ECAT line, Austin, TX. Ranadive, N. Private communication, IBM LPAT line, Poughkeepsie, NY. Galyon, G.T. Private communication, IBM Corp., Systems Development Group, Poughkeepsie, NY. Britton, S.C. Spontaneous growth of whiskers on tin coatings: 20 years of observation. Trans. Inst. Met. Finish. April 1974, 52, 95–102. Lee, B.Z.; Lee, D.N. Spontaneous growth mechanism of tin whiskers. Acta Metall. 1998, 46 (10), 3701–3714. Arnold, S.M. Repressing the growth of tin whiskers. Plat. Mag. Jan. 1966, 53 (1), 96–99. Glazunova, V.K.; Kudryavtsev, N.T. An investigation of the conditions of spontaneous growth of filiform crystals on electrolytic coatings. (Translated from) Z. Prikl. Khim. March 1963, 36, 543– 550. Cobb, H.L. Cadmium whisker. Mon. Rev. Am. Electroplaters Soc., Jan. 1946, 33 (94), 28–30. Compton, K.G.; Mendizza, A.; Arnold, S.M. Filamentary growths on metal surfaces—‘whiskers’. Corrosion 1951, 7, 327–334. Dunn, B.D. Whisker formation in electronic materials. Circuit World July 1976, 2 (4), 32–40. McDowell, M.E. Tin Whiskers: A Case Study. Aerospace App. Conf., 1993; 207–215. Rozen, M. Practical whisker growth control methods. Plat. Mag., November 1968, 55 (11), 1155– 1168. M.Rozen, M. Effects of temperature on bright acid tin-plated deposits. Plating, October 1970, 57 (10), 1019–1024. Jafri, A. Fighting whisker growth in the communication industry. Plating, April 1973, 60 (4), 358– 359. Sabbagh, N.A.J.; McQueen, E.H.J. Tin whiskers: causes and remedies. Met. Finish., March 1975; 27–31. G.E. Web site: http://www.geindustrial.com/pm/support/dls/dlssb01.pdf. Galyon, G.T. Private communication, IBM Corp., Systems Development Group, Poughkeepsie, NY. Xu, C.; Fan, C.; Zhang, Y.J. Whisker prevention. Proceedings of the 2003 APEC Conf., April 2003; 1–8. Brusse, J. Tin whisker observations on pure tin-plated ceramic chip capacitors. AESF/SurFin Conf., June 2002; 45–60. Peach, M.O. Mechanism of growth of whiskers on cadmium. J. Appl. Phys. 1952, 23, 1401. Koonce, S.E.; Arnold, S.M. Growth of metal whiskers. J. Appl. Phys. 1953, 24, 134–135. letters to the editor. Frank, F.C. On tin whiskers. Philos. Mag. August 1953, 54, 854. Eshelby, J.D. A tentative theory of metallic whisker growth. Phys. Rev. 1953, 91, 774–775. letters to the editor. Fisher, R.M.; Darken, L.S.; Carroll, K.G. Accelerated growth of tin whiskers. Acta Metall. May 1954, 2, 368–373. Glazunova, V.K. A study of the influence of certain factors on the growth of filamentary tin crystals. (Translated from) Kristallografiya Sept.–Oct. 1962, 7 (5), 761–768. Pitt, C.H.; Henning, R.G. Pressure-induced growth of metal whiskers. J. Appl. Phys. 1964, 35, 459– 460. communications. Hasiguti, R.R. A tentative explanation of the accelerated growth of tin whiskers. Acta Metall. 1955, 3, 200–201. letters to the editor. Amelinckx, S.; Bontinck, W.; Dekeyser, W.; Seitz, F. On the formation and properties of helical dislocations. Philos. Mag., Ser. March 1957, 8, 2 (15), 353–377. Franks, J. Metal whiskers. Nature May 1956, 7, 984. letter-to-the-editors. Franks, J. Growth of whiskers in the solid phase. Acta Metall. Feb. 1958, 6, 103–109.
STRUCTURE AND KINETICS OF TIN-WHISKER 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62.
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Lindborg, U. A model for the spontaneous growth of Zn, cadmium, and tin whiskers. Acta Metall. 1976, 24, 181–186. Lee, B.Z.; Lee, D.N. Spontaneous growth mechanism of tin whiskers. Acta Metall. 1998, 46 (10), 3701–3714. Selcuker, A.; Johnson, M. Microstructural characterization of electrodeposited tin layer in relation to whisker growth. Capacitor and Resistor Technology Symposium Proceedings, Oct. 1990; 19–22. Ellis, W.C.; Gibbons, D.F.; Treuting, R.G. Growth of Metal Whiskers from the Solid. Growth and Perfection of Crystals; John Wiley & Sons: New York, NY, 1958; 102–120. Koonce, S.E.; Arnold, S.M. Growth of metal whiskers. J. Appl. Phys. 1953, 24, 365. letters to the editor. Fujiwara, K.; Kawanaka, R. Observations of the tin whisker by micro-Auger electron spectroscopy. J. Appl. Phys. Dec. 1980, 51 (12), 6231–6233. Tu, K.N. Cu/Sn interfacial reactions: thin-film versus bulk case. Mater. Chem. Phys. 1996, 46, 217– 223. Baudry, I.; Kerros, G. Focused ion beam in microelectronics packaging applications—lead-free plating analysis. Solder. Assem. Technol., Issue 3, 2001. www.lead-free.org. Choi, W.J.; Lee, T.Y.; Tu, K.N.; Tamura, N.; Celestre, R.S.; MacDowell, A.; Bong, Y.; Nguyen, L.; Shen, G.T.T. Structure and kinetics of tin whisker growth on Pb-free solder finish. IEEE—Proc. of 52nd Elec. Components and Technology Conf., San Diego, CA, May 2002; 628–633. Gorbunova, K.M.; Glazunova, V.K. Present state of the problem of spontaneous growth of whisker crystals on electrolytic coatings. (Translated from) Zas. Met. May–June 1984, 20 (3), 342–358. Stevens, W. Private Communication, Brookhaven National Laboratory: Internal Report to NEMI Modeling Committee, 2002. Boguslavsky, Irina. Private Communication, NEMI Modeling Committee, 2002. Tu, K.N. Interdiffusion and reaction in bimetallic Cu–Sn thin films. Acta Metall. April 1973, 21 (4), 347–354. Sheng, G.T.T.; Hu, C.F.; Choi, W.J.; Tu, K.N.; Bong, Y.Y.; Nguyen, L. Tin whiskers studied by focused ion beam imaging and transmission electron microscopy. J. Appl. Phys. July 2002, 92 (1), 64– 69. Xu, C.; Zhang, Y.; Fan, C.; Abys, J.; Hopkins, L.; Stevie, F. Understanding whisker phenomenon— driving forces for the whisker formation. IPC APEX, S-06-2-1–S06-2-6. Vo, V. NEMI Workshop—Fall 2002; IPC/APEX workshop—Nov. 2002. Kakeshita, T.; Shimizu, K.; Kawanaka, R.; Hasegawa, T. Grain size effect on electroplated tin coatings on whisker growth. J. Mater. Sci. 1982, 17, 2560–2566. Sears, G.W. A mechanism of whisker growth. Acta Metall. July 1955, 3, 367–369. McLean, D. Grain Boundaries in Metals. Clarendon Press: Milltown, NJ, 1957. Chaps. 8 and 9. Bennet, D.C.; Sawyer, B. Single crystals of exceptional perfection and uniformity by zone refining. Bell Syst. Tech. J. 1956, 35 (3), 637. Tu, K.N. Irreversible processes of spontaneous whisker growth in bimetallic Cu–Sn thin-film reactions. Phys. Rev. B, January 1994; 2030–2034. Williams, M. Private Communication, NEMI Modeling Committee, December 2002. Ke, T. Experimental evidence of the viscous behavior of grain boundaries in metals. Phys. Rev. 71, 533. Galyon, G.; Palmer, L. Integrated Recrystallization Theory for Whisker Formation. NEMI Workshop, TMS, March 2002. Blech, I.A.; Petroff, P.M.; Tai, K.L.; Kumar, V. Whisker growth in Al thin-films. J. Cryst. Growth Feb. 1976, 32 (2), 161–169. Chang, C.Y.; Vook, R.W. The effect of surface aluminum oxide films on thermally induced hillock formation. Thin Solid Films May 1993, 32 (2), 205–209. Kehrer, H.P.; Kadereit, H.G. Tracer experiments on the growth of tin whiskers. Appl. Phys. Lett. June 1970, 16 (11), 411–412. Boguslavsky, I.; Bush, P. Analysis Report for NEMI; May 16, 2002. Galyon, G. Private communication, IBM eSystems Group.
22 Degradation Phenomena Michael J. Sullivan Lloyd Technology Associates, Inc., Katonah, New York, U.S.A.
Stephen J. Kilpatrick U.S. Army Research Laboratory, Adelphi, Maryland, U.S.A.
I. A.
INTRODUCTION General
The move to lead-free technology is ironically juxtaposed against the unparalleled virtues of lead (Pb)-based solders. Tin–lead solder is virtually an ideal material in nearly every regard. As will be discussed in this chapter, the features of that binary phase diagram, the mechanical properties of that alloy, and its thermomechanical fatigue behavior in service are extremely well suited to its utilization in microelectronic packages, providing a family of solders with a range of melting temperatures for a variety of applications. Lead-free systems, on the other hand, offer fewer options.
B.
Temperature Hierarchy
The challenge of identifying a replacement for lead-bearing solders requires satisfying the desirable attributes listed in Table 1 [1]. A key feature of the Pb–Sn solder system is that it provides a family of solders that melt over a range of temperatures which is very useful during assembly operations. For example, eutectic Sn–Pb (63–37) melts at 183jC, and a whole range of hypoeutectic (low Sn) alloys has been utilized for a variety of applications, up to the 97Pb–3Sn alloy (MP=325jC) utilized by IBM for flip chip solder bumps. A high melting point alloy (i.e., high Pb content) is utilized for chip solder bumps because they are attached early in the process. A lower melting point solder (i.e., lower Pb content) is utilized to attach ball grid array (BGA) components to cards, which occurs later in the process. In other words, the highest melting temperature solder is reflowed first and it does not remelt during a subsequent reflow operation, often referred to as a solder hierarchy. Use of a solder hierarchy can be beneficial in other ways also, such as cases where an underfill is used with a flip chip die to avoid the solid-to-liquid volume expansion or concomitant hydrostatic pressure that would result if the solder melted. Ideally, in migrating to a Pb-free system, it would also be desirable that it, too, can provide a series of alloys that melt over a broad range of temperatures to preserve the assembly benefits provided by a solder hierarchy.
915
916
SULLIVAN AND KILPATRICK
TABLE 1
Requirements for Suitable Alternative Pb-Free Alloys
Requirements Low cost Relatively nonhazardous No potential environmental problems; ranking in decreasing order of safety: Bi > Zn>In>Sn>Cu>Sb>Ag>Pb Capable of forming reliable joints Compatible with relatively low-temperature processing Corrosion-resistant Compatible with copper substrates, immersion gold-over-nickel, and a variety of nonlead substrates, as well as leaded substrates Available in bar, wire, and paste forms Available in sufficient quantities Low melting temperatures (<240jC) Good electrical conductivity Good thermal conductivity Easy reparability Adequate strength properties Source: Ref. 1.
C.
Major Studies Suggest Tin-Based Solder
Many investigations have been made in the past decade to determine the possible replacement candidates for leaded solder [1–24]. Several of these studies were very encompassing, starting with a lengthy list of possible candidates and down-selecting to a list of just a few promising ones based on considerable research and testing [2,3,7,8,10–12]. One such study, undertaken by The National Center for Manufacturing Sciences (NCMS) from 1992 to 1997 [2,3], started with over 70 different alloys and down-selected to 7, listed in Table 2. This and other lead-free alloy selection studies are discussed in detail in Chap. 10. One thing is clear on the basis of the various studies conducted: there is no lead-free solder drop-in replacement. However, it is quite remarkable that all the viable candidates are Sn-based alloys. The most emphasis has clearly been placed on ternary Sn–Ag–Cu, with some minor compositional variations, and may include a small amount of Sb. The National Electronics Manufacturing Initiative (NEMI) in North America recommended that the industry standardize on Sn3.9Ag0.6Cu in 2000 as a replacement for reflow applications [7]. The Interconnection Technology Research Institute (ITRI), a U.K.based consortium, through the SOLDERTEC project, has recommended Sn(3.4–4.1)Ag(0.45–
TABLE 2 List of Down-Selected Pb-Free Alloys from the NCMS Project Solder compositions Sn–3.5Ag Sn–58Bi Sn–3Ag–2Bi Sn–2.6Ag–0.8Cu–0.5Sb Sn–3.4Ag–4.8Bi Sn–2.8Ag–20In Sn–3.5Ag–0.5Cu–1Zn Source: Ref. 3.
Liquidus temperatures (jC) 221 139 220 211 210 187 221
DEGRADATION PHENOMENA
917
0.9)Cu as a general replacement for SnPb [10,11]. Some have also considered alloys with significant indium content, but they are rather expensive, and one that was offered commercially for a time was eventually abandoned due to severe shape changes during thermal cycling. None of the lead-free candidates, including the Sn–Ag–Cu system, provides a solder hierarchy. Most leadfree replacement solders which have been considered have melting temperatures which fall in the range of 210–232jC, thus 30–50jC above the Sn–Pb eutectic, and well below those of the high-Pb solders. The Au–Sn eutectic, with a melting temperature of 278jC, has also been suggested, although its high strength, low ductility, and high Au content (80%) make it problematic. This chapter discusses the properties of Sn and Sn-based alloys, and the various degradation phenomena that can occur in these materials, while making comparisons to Pb and Pb–Sn solders. The effect that certain anomalous Sn properties has on the performance of solder applications in microelectronic components will be discussed as well. For example, these discussions will address the effect of tin’s anomalous degradation behavior and associated reaction kinetics on fatigue resistance during thermal cycling, and other reliability issues discussed in other chapters of this book, but without these additional complicating factors.
II.
ANOMALOUS BEHAVIOR OF TIN
A.
Materials Classifications
The anomalous behavior of tin results from the two crystal structures in which it can exist in the solid state. One of these structures is a metal and the other is a semiconductor, and it is therefore necessary to give a brief description of these basic material classifications and the type of atomic bonding that gives rise to these different structures. There are three major classes of solids: metals, semiconductors, and insulators [25]. Approximately three-quarters of all naturally occurring elements are metals. Those materials which are neither metals nor nonmetals but that share the characteristics of both include gallium, tin, antimony, and polonium. Examples of elements and compounds for these classes of materials are given in Table 3. These classes of solids result from their characteristic atomic bonding. 1. Insulators Insulators form when electrons transferred from one atomic species to another result in the donor species having an electrical charge that is opposite the acceptor species, thus they are attracted to each other [26]. The electrons are bound to both the acceptor and donor species (i.e., ions), so there are no free electrons for current flow; hence the material is an insulator (Fig. 1). These materials are characterized by a negative temperature coefficient of resistivity (TCR) which means that the resistance decreases as the temperature is increased. As the temperature is increased, the carrier mobility, ions for the case of insulators, increases to decrease resistivity. The number of mobile electrons does not increase because the band gap between the valence band and the conduction band is often too great to overcome by thermal energy alone [27]. 2. Semiconductors Semiconductors are formed when electrons are shared between atomic species forming covalent bonds between them. The temperature coefficient of resistivity is negative for semiconductors
TABLE 3 Examples
Classification of Materials with
Classes of materials Metals Semiconductors Insulators
Examples Al, Cu, Fe, Sn Si, Ge, GaSb, Sn NaCl, MgO, LiF
918
SULLIVAN AND KILPATRICK
FIG. 1 Schematic depiction of ionic bonding in insulators.
because the number of carriers can be increased by thermal energy since the band gap is relatively small. The crystal structure of semiconductors is entirely controlled by the nature of the bonding. Semiconductor elements usually have a valence of four, and in the solid state, each atom is surrounded by just the four other atoms with which it shares electrons. As was the case with insulators, the bonding is directional and close-packed structures are precluded. The nearest neighbor atoms are arranged in tetrahedra (Fig. 2) which results in a diamond cubic crystal structure [28]. 3. Metals Metals are formed when the bonding electrons are shared by all of the atoms in the crystal. In these structures, the conduction band is partially filled and there are empty energy states available for electron movement throughout the crystal [29]. Metals exhibit a positive temperature coefficient of resistivity so an increase in temperature does not increase the number of carriers, but does decrease carrier mobility due to increased vibration and scattering by the lattice atoms (i.e., electrical resistivity increases with temperature). The metallic bond is relatively nondirectional and close-packed structures often result. In the classification of solid types given above, tin is included in both the metallic and semiconductor classes. This is the basis for tin’s anomalous behavior because the transformation, which occurs at 13.2jC (55.6jF), is not merely between crystal structures within a class, but between classes of solid types [30].
B.
Allotropic Changes Within a Metallic System
An allotropic transformation results in a change in the crystal structure of a solid material. Allotropic transformations between crystal structures in the metallic class are often not detrimental and are, in fact, used to great advantage [31]. Steel, which is an alloy of iron with a small amount of carbon, is a familiar example. At low temperature, steel has a body-centered cubic crystal structure. As the temperature is increased, the structure changes to face-centered cubic
DEGRADATION PHENOMENA
919
FIG. 2 Depiction of covalent tetrahedral bonds in semiconductors including silicon and gray tin.
(FCC), and if the material is cooled slowly, the metal transforms back to body-centered cubic. If, however, the steel is rapidly cooled (quenched), the material transforms to the body-centered tetragonal crystal structure. This structure, termed martensite, is very strong and hard, and, at low temperature, it is metastable with respect to the equilibrium body-centered cubic structure. The transformation rate from the metastable body-centered tetragonal structure to the stable body-centered cubic crystal structure is very slow at room temperature and poses no problems in use. All of these structures exhibit metallic bonding with positive temperature coefficients of resistivity.
C.
Tin Allotropic Change Between Materials Classifications
The allotropic transformations that occur in tin are different from those described above for steels. In tin, the transformation involves a change in crystal structure and a change form a metal into a semiconductor. This change in solid classification involves a change from metallic bonding with a relatively close-packed structure to covalent bonding with directional nonclose-packed structure. Accordingly, tin undergoes a substantial volume change (21%, Table 4) as the transformation occurs which causes the metal to experience internal stresses which are sufficient to cause fracturing and ultimately the complete loss of integrity forming a powder [32]. Tin pest is therefore the loss of the metal’s integrity due to the transformation between the allotropic phases.
D.
Comparison of Solder Systems
The discussion in the previous section makes it clear that there are significant differences between lead-free, tin-based solder systems and other solders successfully used in the past. The anomalous crystal structure and allotropic transformations in tin-based alloys can affect the material properties that control the ultimate performance and reliability of these solders in microelectronic assemblies. Table 5 provides a comparison of several solder systems including highlead and eutectic tin–lead alloys, white and gray tin, a lead–indium solder, gold–tin eutectic, and a fictitious ideal alloy. 1. Ideal Solder Alloy Characteristics An ideal solder alloy would have a melting temperature dictated by the package materials that is resistant to the process flow, thermal degradation, and possesses a melting point hierarchy capability. An ideal solder would also have a face-centered cubic crystal structure (Fig. 3) which
920 TABLE 4
SULLIVAN AND KILPATRICK Properties of Tin
Parameter Atomic number Atomic mass Atomic radius (CN 12) Valences Ionic radii, Sn+2, Sn+4 Melting temperature Boiling temperature Vapor pressure at 727jC Heat of fusion Heat of vaporization Specific heat at 20jC Normal entropy at 25jC Thermal conductivity at 20jC Surface tension at MP Viscosity at MP Expansion on melting Resistivity (h tin) at 20jC Resistivity (a tin) at 0jC Photoelectric work function Single electrode potential a to h transformation temperature Crystal structure h tin Crystal structure a tin Lattice constants h tin Lattice constant a tin Density h tin Density a tin Volume change (%), h to a tin CTE, h tin, a-axis CTE, h tin, c-axis Tensile strength (h tin) Elongation to fail (h tin) Young’s modulus (h tin) Poisson’s ratio (h tin) Twinning plane (h tin)
Value 50 118.69 1.58 101 nm 2 and 4 0.93101, 0.71 101 nm 231.88jC 2625jC 7.4 106 mm Hg 7.08 kJ/g atom 296.4 kJ/g atom 222 J/kg K 57.5 J/kmol 65 W/m K 544 mN/m 1.85 mNs/m2 2.3% 12.6 AV cm 300 AV cm 4.64 eV 0.52 V 13.2jC (55.8jF) BCT (A5 lattice type) Diamond cubic (A4 lattice) a = 58.3102, c = 31.8102 nm a = 64.9102 nm 7.30 gm/cm3 5.75 gm/cm3 21% 30.5 106 in./in./jC 15.45 106 in./in./jC 2600 psi 90% 6.0106 psi 0.33 (301)
has an atom at each corner of the cube and an atom in the center of each face. This structure contains the greatest number of dislocation slip systems, thus provides the greatest opportunity to undergo plastic deformation to relieve stress [33]. Dislocations glide most easily on closest packed crystal lattice planes and in closest packed directions within these planes [34]. A close-packed plane is one with the highest density of atoms per unit area, and a close-packed direction is one that has the highest atom count per unit length. Atoms in these special close-packed planes and directions are in intimate contact (Figs. 3b and 4). Note that A, B, and C are equivalent crystallographic directions. The face-centered cubic crystal structure has the greatest number of slip systems of the common metal crystal structures because it has the closest packed planes and directions. As the solder is being strained during temperature excursions in product applications, the major deformation mode in the solder is grain boundary sliding (Fig. 5a) [35]. As the sliding occurs, obstacles are encountered such as intermetallic particles located on the grain boundaries, which increase the resistance to sliding (Fig. 5b). Grain boundary triple points, points at which
DEGRADATION PHENOMENA TABLE 5
921
Properties of Various Solder Alloys Solder
Property Melting temp. (jC) Crystal structure Pest reaction Anisotropy of properties Resistivity at RT (AV cm) Interface reactions Strength (UTS) (psi) Ductility % (elongation) T/C Life (cycles) E/M Life (ideal=1.0) T/M Life (ideal=1.0) Whiskers
Ideal solder
Pb–Sn 3–97
Sn–Pb 63–37
h-Sn white
a-Sn gray
Pb–In 50–50
Au–Sn 20–80
—
325
183
232
232
227
278
FCC no no
FCC no no
FCC BCT no no
BCT yes yes
Dia. Cubic yes no
FCC FCT no yes
Orth. Hex no no
—
19.5
14.5
12.6
300
—
—
ok f1,000
ok 3,400
ok 3,600
ok 3,800
ok —
ok 1,000
excessive 42,000
f100
60
60
50
—
100
10
—
1,500
1,000
500
—
5,000
<500
1.0
f0.9
f0.5
f0.5
—
f0.1
—
1.0
f0.9
f0.5
f0.5
—
f0.1
—
no
no
no
yes
yes
no
no
FIG. 3 Schematic representation depicting the face-centered cubic (FCC) crystal structure. a) Atom locations depicted on three of the six faces of the cube in the FCC structure. b) The diagonal planes possess the closest atomic packing in the FCC structure and lines forming the diagonal planes are the directions with the closest atomic packing.
922
SULLIVAN AND KILPATRICK
FIG. 4 Schematic representation depicting closest packed planes and directions in the FCC structure. The closest packed plane is the same shown in Fig. 1(b) in Chap. 21. The equivalent directions A, B, and C are the dotted lines forming the diagonal plane.
FIG. 5 Depiction of grain boundary sliding due to shear forces applied at high temperature. (a) Unimpeded sliding of two different grains relative to each other along their grain boundary with no obstacles. (b) Sliding at grain boundary triple point showing location of lattice deformation. (c) Grains undergo lattice deformation due to the presence of an intermetallic particle on the grain boundary during grain boundary sliding. The obstacle increases the resistance to sliding, thus plastic deformation.
DEGRADATION PHENOMENA
923
several grain boundaries intersect, within the system also cause local distortions (Fig. 5c) [36]. However, deformation of the metal lattice due to dislocation glide adjacent to an obstacle allows the sliding to proceed without crack formation and results in a long thermal cycle fatigue lifetime. An ideal solder would not be subject to allotropic pest reactions, exhibit anisotropy, nor exhibit high electrical resistivity. Another important trait of an ideal alloy would be controlled reactions with the chip and chip carrier metallizations. Multiple solder reflows should not result in problems such as Kirkendall voids (see Sec. VI.G.3), high stress, or impurity snowplowing [37]. Impurity snowplowing occurs during reaction when the reaction product rejects small amounts of impurity present in the reactants. The rejected material accumulates at the reaction interface and can weaken the interfacial strength. The strength of an ideal solder should be sufficiently low to not transmit high stress to a chip and chip carrier and exhibit good ductility to accommodate the required plastic strain without degradation. In the absence of an underfill material, the solder must absorb the plastic strain that results from a mismatch in coefficients of thermal expansion (CTE) between package materials [38]. A weak, ductile solder is best suited to the role of absorbing stress through plastic deformation without cracking. These properties provide the best resistance to thermomechanical fatigue, thus superior reliability. An ideal solder should also exhibit good electromigration and thermomigration resistance. Other potential problems such as whisker growth would not occur in an ideal solder system. 2. High Lead Solders A comparison of the ideal solder with 97Pb–3Sn solder utilized as a solder bump material for flip chips indicates that this high-lead solder is close to ideal. There are no difficulties with tin pest, allotropic transformations, anisotropy, interface reactions, or whisker growth. The thermomechanical fatigue lifetime is acceptable, but could be improved if the strength was lower and the ductility was higher. The electromigration and thermomigration behavior is good partially as a result of the high melting temperature of the alloy; that is, atomic mobility is usually correlated with melting temperature—the higher the melting temperature of a solder, the lower its atomic mobility. Low atomic mobility helps to prevent void formation and terminal failure caused by electromigration and thermomigration [39].
FIG. 6 Schematic depiction of the body-centered tetragonal crystal structure.
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3. Eutectic Sn–Pb Solder The eutectic Sn–Pb alloy exhibits a much reduced electromigration and thermomigration resistance compared to high-lead solders. This reduced resistance is mostly due to the significantly lower melting temperature of the eutectic solder which, in turn, results in a greater atomic mobility at the same service temperature. 4. White Tin The properties of white tin given in Table 5 indicate that this allotropic form of tin is an excellent example of a nonideal solder material. The body-centered tetragonal crystal structure (Fig. 6) results in the anisotropy of properties that can lead to failure modes such as thermal ratcheting (see Sec. III.C). White tin is susceptible to the catastrophic pest reaction and is known to grow whiskers that are a potential reliability concern. The strength of tin is greater than high-lead solders, which is surprising in light of the significantly greater melting temperature of high lead solders. This seeming contradiction is due to the body-centered tetragonal crystal structure of white tin which has no closest packed planes or directions, making dislocation glide difficult. Accordingly, Sn and Sn-based solders cannot easily absorb stress through plastic strain without cracking, and the thermomechanical fatigue lifetime suffers as a result. The atomic mobility is relatively high in white tin, so electromigration and thermomigration lifetimes are low compared to high lead solder (see Sec. VII.A).
FIG. 7 Depiction showing the principle features of the diamond cubic crystal structure with each atom surrounded by four equidistant nearest neighbors which lie at the corners of a tetrahedron. For clarity, the figure does not show all of the atoms in the unit cell.
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5. Gray Tin Only a few properties of gray tin are given in Table 5 because there are virtually no applications for this material. As discussed above, this form of tin is a semiconductor with a diamond cubic crystal structure (Fig. 7), which results in high strength and low ductility, thus yields a very low thermomechanical fatigue resistance. The electrical resistivity of gray tin is 25 times greater than white tin. This increase in resistivity alone can cause circuit failures, so for this and the other reasons cited, the occurrence of the tin pest reaction (i.e., formation of gray tin) must be avoided. 6. 50Pb–50In Solder The 50Pb–50In alloy is included in Table 5 to illustrate a few important points. This alloy is a mixture of phases consisting of face-centered cubic and face-centered tetragonal (FCT) crystal structures. During thermal cycling, the alloy exhibits thermal ratcheting due to anisotropy associated with the face-centered tetragonal phase. The strength of the alloy is very low and exhibits excellent ductility resulting in exceptionally good thermal cycling lifetimes. However, this solder has very poor thermomigration and electromigration resistance due to the high atomic mobility that results from the relatively low melting temperature. Note that this alloy has approximately the same melting temperature as lead-free, tin-based alloys which indicates that the tin-based alloys may be susceptible to the same failure modes [40]. 7. 80Au–20Sn Hard Solder The 80Au–20Sn eutectic alloy (discussed in detail in Sec. VII.E.4) is included here as an example of strong solders with limited ductility that typically do not perform well in accelerated thermal cycle (ATC) tests in the absence of an underfill. This solder exhibits the same properties that are desirable in underfill materials: high strength, elastic deformation, and no stress relaxation [41]. This solder can assist the underfill with its role of stretching the chip during thermal cycling thus decreasing the strain imposed on the flip chip solder joints (C4 terminal). This material may be useful for flip chip solder joint applications that include underfill if the reactions of the gold with the chip and chip carrier metals can be controlled.
III.
ANISOTROPY OF PROPERTIES
A.
Physical Properties
The coefficient of thermal expansion, CTE, data in Table 4 reveal that the properties of h tin (white tin) are anisotropic. This means that the properties differ in various crystallographic directions. This is not the case for a tin (gray tin) which has a diamond cubic crystal structure that exhibits uniform properties in all crystallographic directions. The body-centered tetragonal, white tin crystal structure is elongated along the a-axis compared to the c-axis. The difference in bond length accounts for much of the observed anisotropy. The CTE along the loosely bound aaxis is twice that of the more tightly bound c-axis. The room temperature a-axis compressibility is 67.19106 mm2/kg which is more than the c-axis compressibility of 60.22106 mm2/kg. Other white tin properties also exhibit anisotropic characteristics. At room temperature, the electrical resistivity along the a-axis is 14.30 AV cm with a temperature coefficient of resistivity of 0.00447 AV cm/jC. Along the c-axis, the resistivity is 9.90 AV cm and the temperature coefficient of electrical resistivity is 0.00469 AV cm/jC. For polycrystalline material, the room temperature electrical resistivity of white tin is 11.0 AV cm.
B.
Elasticity-Based Mechanical Properties
During use in a microelectronic assembly, tin-based solders will be subjected to stress conditions resulting in both elastic and plastic stress and strain. For most use conditions, the elastic strain will be transformed to plastic strain due to stress relaxation, recovery, and recrystallization which occurs at temperatures above one-half of the absolute melting temperature. For an isotropic material, the only constants needed to describe the elastic stress–strain behavior are E, the
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modulus of elasticity, G, the shear modulus, and m, Poisson’s ratio. These elastic constants are related by the relation: G ¼ E=2ð1 þ mÞ
ð1Þ
In order to describe the behavior of an anisotropic material, Hook’s law can be written in completely general terms [42]. This requires that six strain components and 36 elastic coefficients be known in order to calculate the stress. Symmetry considerations are such that even for the least symmetrical crystal structure, triclinic, the number of independent elastic constants required is reduced to 21. For metals, whose crystal systems all exhibit relatively high degrees of symmetry, the number of constants is further reduced to 12. Anisotropic materials such as magnesium, zinc, and tin require at least five elastic constants. Materials with cubic crystal structures require three independent elastic constants, while a truly isotropic material requires only two elastic constants.
C.
Plasticity and Thermal Ratcheting It will be noted that tin exhibits anisotropy of thermal expansion properties in different crystallographic directions, and this may lead to steps appearing in a free surface at the boundaries between large grains in samples subjected to severe thermal cycles [43]. (Barry and Thwaites)
Distortions can occur in an anisotropic material during thermal cycling. An interesting example of this phenomenon was observed with uranium fuel rods in nuclear reactors [44]. During temperature cycling between 50jC and 550jC, uranium rods increased in length and exhibited surface distortions due to internal stresses generated by anisotropy. After 500 thermal cycles, the length of 1-in.-long rods increased by approximately 20% with a concomitant decrease in diameter. The crystal structure of uranium is orthorhombic which exhibits a unit cell with all angles equal to 90j and three sides of unequal length. This structure accounts for the observed anisotropy of properties and the thermal ratcheting behavior. Thermal ratcheting is the accumulation of plastic strain due to the mismatch of properties of differently oriented adjacent crystals during thermal cycling. As noted, tin’s body-centered tetragonal (BCT) crystal structure exhibits anisotropic properties and is susceptible to degradation phenomena. The degradation mechanism occurs in the absence of an externally applied load and no temperature gradients during thermal cycling. 1. Requirements There are three requirements in order for thermal ratcheting to occur. The thermal expansion of the material must exhibit directional anisotropy so that adjacent grains in a polycrystalline material expand and contract nonuniformly in different directions. Thermal stresses are produced by a nonuniform expansion and contraction condition. The strength of the crystal must also exhibit directionality so that plastic flow readily occurs in some directions, while other directions resist the plastic flow and only deform elastically. This means that the critical resolved shear stress for the onset of dislocation glide is different for the various crystallographic planes. The critical resolved shear stress is the component of the applied stress acting on the close-packed slip plane in the close-packed slip direction in that plane. The third criterion is that at or above a critical temperature, the strength of the interface (grain boundary) between adjacent crystals decreases, so that the interface is no longer capable of restraining the relative movement between crystals. 2. Mechanism The thermal ratchet phenomenon can be explained with the use of an idealized system shown in Fig. 8 [45]. Crystal A is a cylinder with an axial hole through the center that contains crystal B. Both crystals are made of the same material, but the crystallographic orientations differ. Crystal B is oriented so that plastic flow occurs easily in the axial (vertical) direction, and crystal A is oriented such that plastic flow is easy in the horizontal direction. The directions of high coefficient of thermal expansion for the two crystals are the same as easy plastic flow as indicated in the
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FIG. 8 Schematic representation depicting the elongation of crystal B relative to crystal A during thermal ratcheting.
figure. Fig. 9 is a graphic representation depicting the effect of temperature on the strength of an interface between the two crystals. The interfacial strength decreases rapidly as the critical temperature, Tc, is approached. The thermal ratchet mechanism is depicted graphically in Fig. 10. For example, the initial condition for the stresses and strains in crystal B is at point 0 in Fig. 10 and the temperature is assumed to be Tc. As the temperature is decreased, crystal B contracts significantly more than crystal A, causing a tensile stress in crystal B. The stresses and strains are elastic until the yield stress is attained at point 1 in Fig. 10 when plastic flow commences. The path 0–1–5 is followed as the temperature is reduced from Tc to To (point 5). As the temperature is increased, the stresses are reduced corresponding to the path 5–6–7–4 as the temperature approaches Tc. If no interfacial deformation takes place, the next thermal cycle will result in the stresses and strains following path 4–3–2–5–6–7–4, which results in equal amounts of tensile and compressive deformation and no net dimensional change after the first cycle. This, however, is not the case because the interfacial strength drops to zero at Tc, so crystal A no longer imposes any restraint on crystal B. At this point, the stress–strain condition of crystal B changes from point 4 to point 3, and crystal B elongates compared to crystal A in the manner shown in Fig. 8b. This occurs because the tensile plastic flow from point 1 to point 5 is greater than the compressive
FIG. 9 Graphical depiction of the effect of temperature on the strength of grain boundary and grain lattice materials. (a) Strength decreases rapidly as the critical temperature (Tc) is approached for an ideal grain boundary. (b) Strength decreases gradually as Tc is approached for actual grain boundaries and decreases less so for the lattice material.
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FIG. 10 Graphic illustration of the deformation sequence during thermal cycling to cause the thermal ratcheting mechanism.
plastic flow from point 7 to point 4. During the next thermal cycle, the starting condition is point 3 (not point 0), so that the path 3–2–5–8–etc. is followed. Each additional thermal cycle results in the imposition of more plastic strain (point 2 to point 5) of crystal B relative to crystal A. These changes in the crystal size result in discontinuities between adjacent grains, the surface becomes textured, and holes can appear. 3. Actual Systems The ideal variation of interfacial strength with temperature shown in Fig. 9a is not representative of the behavior of real grain boundaries which actually change with temperature as revealed in Fig. 9b [46]. The real boundary strength decreases slowly with temperature, and the boundaries become weaker than the lattice at approximately 50% of the absolute melting temperature. In the case of the ideal model, all the elastic strain energy stored in crystal B is completely converted into plastic strain due to boundary deformation at the critical temperature, Tc. In reality, the strain is partitioned between the boundary and lattice. Above Tc, most of the deformation is due to grain boundary sliding, and below Tc, most of the deformation is due to dislocation glide on lattice planes. Prevention of this mechanism is difficult for the case of tin-rich solder joints in microelectronic assemblies. 4. Minimize Effects The effects of this anisotropic behavior can be minimized by maintaining a small uniform grain size in the solder and by minimizing the maximum temperature and dwell times. The grain size in solder joints usually varies across a joint. Near interfaces, the grain size is small due to the presence of heterogeneous nucleation sites, but increases away from interfaces. Because solders are utilized at temperatures at or above 50% of the absolute melting point, mechanisms such as recrystallization and grain growth occur during use which changes the initial grain structure. Reducing the maximum operating temperature and dwell times is typically not an option because they are usually fixed by the application conditions. The use of an underfill for flip chip or ball grid
DEGRADATION PHENOMENA
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array solder joints could prevent surface roughening due to thermal ratcheting by providing physical restraint.
IV.
TIN PEST
A.
History I will turn my hand upon thee, and purely purge thy dross, and take away thy tin. Isaiah 1:25
Tin has been known since antiquity. Along with copper, it is the main element in bronze alloys and it produces alloys with superior mechanical properties and castability as compared to pure copper. Bronze artifacts have been found in Egypt, Mesopotamia, and Ur that date from 3000 BC or possibly earlier. One of the anomalous properties of tin known as ‘‘tin pest’’ was noted by Aristotle. He commented on the change that occurs in tin when it is subjected to extremes of temperature [47]. More recently, in 1851, Erdman noticed structural changes in tin organ pipes which he attributed to the effects of vibration and not the cool temperatures encountered in poorly heated churches and cathedrals of the time. During the Russian winter of 1867, the temperature dropped as low as 38jC and Fritzsche [48] reported that blocks of tin disintegrated into granular crystalline pieces and coarse powder. In 1899, Gowland [49] observed the pest reaction in an alloy of 94.35Sn–5.06Pb–0.59O and traces of iron and copper. In 1911–1912, Scott led an expedition to the South Pole which established depots with supplies for the return trip. Petroleum and kerosene to be used for stoves were held in metal containers fabricated with pure tin or tin-rich solder. The containers were placed on top of the food and other supplies so that they could be opened first as each depot was reached. The explorers found the containers failed at each depot and the food was saturated with kerosene. The explorers died of hunger and exposure [50] because the tin pest reaction transformed the solder to powder when exposed to the extreme Antarctic cold.
B.
Occurrence/Description
1. Varying Opinions There are differing opinions concerning the occurrence of tin pest as revealed by the following quotations. Fears of the failure of fabricated products made of block tin or high-tin alloys at low temperatures, or of the disintegration of tin in storage, are largely unfounded, because of the inhibiting effect of the common impurities and the difficulty in initiating the transition. Authenticated instances of the transformation taking place under natural conditions are rare [51]. . . . the transformation of h-tin (white tin) into a-tin (gray tin) occurring in Sn–0.5Cu, aged at 255jK for 1.5 and 1.8 years. . . .This result indicates that tin pest could lead to total disintegration of real joints [52]. Tin is one of the few metals which have sufficient dignity to be subject to a disease. Many workers have observed that ordinary tin changes into a gray powder when exposed to extremes of cold. Medallions, coins and antiques in museums acquire a surface crust of powdery gray tin which gradually grows, seemingly self-catalyzed, until complete disintegration results. This is the tin pest or disease of the museums. . . .When tin or a tin alloy is affected by tin pest, gray colored spots appear and the metal becomes brittle. Expansion occurs so that the product occupies a greater volume then the unaffected tin. The expansion produces pustule-like nodular excrescences at the affected points. Transformation extends radially outward from spots until the whole mass is infected. The metal then rapidly breaks down to a brittle powder. The disease is infectious and can be propagated by inoculation. Transformation can be begun by contact between a grain of powder and a
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SULLIVAN AND KILPATRICK piece of sound metal. The metal becomes sick in an analogous manner to that of the human organism when attacked by pathogenic bacteria. Once infected, the whole mass is in danger [53].
2. Cause: Allotropic Transformation Of historic interest is the question of the existence of a high-temperature form of tin with a transformation temperature at 161jC. This form of tin was said to have a rhombic crystal structure and called gamma or brittle tin. It has been demonstrated that this form of tin does not exist. It has been established that tin exists as the two polymorphic forms, gray tin (alpha) with a diamond cubic crystal structure up to 13.2jC, which transforms to white tin (beta) with a bodycentered tetragonal crystal structure up to the melting temperature (232jC). Tin pest is caused by the allotropic transformation from metallic, body-centered tetragonal white tin to semiconducting diamond cubic gray tin which occurs as the temperature is decreased below 13.2jC (55.6jF). The high-temperature stable white tin has a density of 7.30 g/cm3, while the low-temperature stable gray tin is less dense (5.75 g/cm3). As the reaction occurs during cooling, the density changes by 21% and this large volume change causes the brittle gray tin to fracture and, in some cases, the material is reduced to powder. a. Stress-Assisted. Fig. 11 illustrates the cracking phenomena in a 99.5Sn–0.5Cu alloy aged at 18jC for 1.5 and 1.8 years [52]. As noted previously, this alloy is a prime candidate under consideration by the microelectronics packaging industry as a substitute for leadcontaining solders. The figure reveals that the reaction is stress-initiated at the sample surface and then proceeds to the interior. The grips of the tensile specimens were machined leaving residual stresses at the surface of these locations. The transformation of high-density white tin to low-density gray tin results in a volume expansion, and tensile stresses assist in the nucleation of the low-temperature phase. Solder joints are often subjected to shear stress during use in microelectronic assemblies. Fig. 12 demonstrates that shear stresses are always accompanied by tensile and compressive stresses. A stress element in flip chip C4 or BGA-type solder joints and the Mohr’s circle (Fig. 12b and c) representation demonstrates that the magnitude of the tensile and compressive stresses are equal to the magnitude of the shear stresses [54,55]. The maximum tensile and compressive stresses are orientated at 45j to the direction of the maximum shear stress, and the direction of the stress changes by 180j as the temperature is cycled. b. Effects of Elemental Additions. Various alloying additions can accelerate or reduce the onset of the tin pest reaction. Inoculation, or physical contact with gray tin, can greatly increase
FIG. 11 Photographs of 99.5Sn–0.5Cu test parts aged at 18jC for 1.5 and 1.8 years. a) Surface condition of several test parts. b) Cross section of a test part located near the tensile machine grips. (From Ref. 52.)
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931
FIG. 12 Graphical representation of the state of stress of an element in the interior of an area array solder joint (e.g., flip chip and ball grid array). (a) Element in the joint interior. (b) Tensile, compressive, and shear stresses acting on the element. (c) Magnitude and direction of the stresses are depicted on Mohr’s circle.
the onset of the tin pest reaction in white tin. The reaction is also accelerated due to the presence of certain alloying additions like germanium, zinc, aluminum, manganese, cobalt, magnesium, and tellurium. These elements are seldom present in commercial grades of tin. Several elements are known to retard the tin pest reaction, such as additions of 0.05% bismuth and 0.10% antimony which are particularly potent in this regard. Other elemental additions such as lead, gold, silver, and nickel also retard the tin pest reaction, but are not as effective as bismuth and antimony.
C.
Nucleation Effects and Growth Kinetics
The tin pest reaction is an example of a solid-state reaction in which no change in composition is involved. The reaction only results in a change of the tin crystal structure. The lack of an orientation relationship between the unreacted white tin and transformed gray tin precludes formation by a martensitic-like mechanism [56]. Also, the relatively slow reaction rates indicate that the tin pest reaction is nucleation- and growth-controlled. The complex crystal structures involved also tend to negate a martensitic-type reaction because dislocation motion is the basic mechanism involved. These arguments are valid for transformation in both directions, i.e., whiteto-gray tin during cooling and gray-to-white tin on heating. 1. Nuclei Formation and Stability A graphical illustration of the relationship between the surface and volume energies characteristic of nuclei as they form and grow is given in Fig. 13 [57,58]. The functional relationship is that the
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FIG. 13 Graphical depiction of how both the surface and volume energies of a nucleated phase vary with size (nucleus radius). A nucleus becomes increasingly more stable with growth beyond a critical size, rc, because its total energy (surface plus volume energies) continuously decreases beyond rc.
volume free energy decreases as the radius of a nucleus is cubed and the surface energy increases as the radius is squared. Thermodynamically, a nucleus is unstable when it initially begins to grow in size (i.e., increase in radius) after formation because it is increasing in energy. However, the existence and further growth of a nucleus is favorable at a size beyond which additional growth results in a reduction in energy. The size of the nucleus where there is no further increase in energy is referred to as the critical radius, rc, with a corresponding critical energy, Ec. For a nucleus to form and grow, it must first overcome the critical energy barrier to attain the critical radius. The large strain energy due to the volume change that occurs during the tin pest reaction further increases both the critical radius and critical energy barrier which results in a drastic decrease in the nucleation rate because the nucleation rate varies exponentially with energy. Conversely, heterogeneous nucleation that takes advantage of a preexistent surface results in a decreased surface energy term, serves to reduce the energy required to form stable nuclei, so that the nucleation rate increases. Consequently, the primary nucleation sites for the tin pest reaction are at the surface of the white tin phase (Fig. 11). Tensile stresses also assist in overcoming the nucleation barrier. Some elemental additions such as bismuth and antimony retard nucleation because they go into solid solution resulting in long-range stresses that increase the nucleation barrier. 2. Tin Pest Nucleation Rate The nucleation rate, I, with units of nuclei/cm3 sec, can be described by the following relation: I ¼ mA*N5=3 exp ðQ þ W *Þ=kT ð2Þ where m=jump frequency (1/sec); A*=critical nucleus area (cm2); N=atoms/area in matrix (atoms/cm2 ); Q=jump activation energy (eV); kT=average thermal energy (eV); and W*=VGv+cA+EV (eV). The terms involved in W* are VGv, the free energy of reaction which is the driving force, Ac, the surface energy, and EV, the strain energy. The terms V and A are the volume and surface area of the nuclei, respectively. For most reactions, the strain energy term is small compared to the free energy term. Due to the large volume change that occurs during the tin pest reaction, the strain energy term dominates. At 0jC, the free energy change is 0.5 kcal/g atom and the strain energy is 5.0 kcal/g atom. The calculation of nucleation rates using Eq. (2) is complex and details can be found in Ref. 59.
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3. Tin Pest Reaction Kinetics The reaction kinetics for the white tin to gray tin reaction can be described using the well-known Avrami relation below: f ¼ 1 expðKtn Þ
ð3Þ 3
where f=volume fraction transformed (%); K=rate constant (temperature-dependent) (sec ); t=time (sec); and n=time exponent (temperature-independent). For the tin pest reaction, the time exponent, n, is 3 [60]. Using the data in Ref. 52, it is approximated that a 40% volume fraction transforms after 1.5 years at 18jC, which yields a calculated value of K=5.71024 sec3 when substituted into Eq. (2). It was also noted in Ref. 52 that tin pest was ‘‘evident’’ after 0.58 years. This results in approximately 2% of the volume transformed based on the previously calculated value of K. These time–temperature transformation reaction kinetics yield the classic S-shaped curves when the volume fraction transformed is plotted against the log of time. On that basis, it would require approximately 8.4105 min to transform 50% of a 99.5Sn–0.5Cu alloy. Other measurements of reaction kinetics in ‘‘pure’’ tin [56] are given in Table 6 which indicates that the time to transform a 50% volume fraction at 15jC is 72 min. This difference, a factor of 10,000, is due to several parameters: alloy additions, surface condition, residual stress, and prior thermal history. This very large difference in reaction rate illustrates the difficulty encountered when a tin-based solder is evaluated for use in microelectronic assemblies. Fig. 14 depicts the effect of temperature on the growth rate of the white-to-gray tin transformation. The maximum growth rate occurs at 40jC and decreases by a factor of 10 as the temperature approaches 0jC [56]. The transformation of white-to-gray tin is one in which nuclei form when the transformation initially commences, but then proceeds into three-dimensional growth with no new nuclei formed. The number of nuclei that form at any temperature can be determined from the Avrami relation [Eq. (3)] and Eq. (4). The temperature-dependent rate constant, K, can be written as [61–63]: ð4Þ
K ¼ acG3 3
where a=shape factor=p/3; c=nuclei density (nuclei/cm ); and G=growth rate (cm/sec). 4.
Flip Chip Joint (C4) Transformations
a. White-to-Gray Tin. At 40jC, the growth rate from Fig. 14 is 2.55105 cm/sec and the time to 50% volume transformed is 900 sec (Table 6). Substitution of these data into Eq. (4) yields a nuclei density of 5.7104 nuclei/cm3. The solder volume of a typical flip chip C4 terminal is 1.0106 cm3 and therefore multiplying the nuclei density times the C4 volume, approximately 5.7% of the terminals will contain nuclei. Because flip chips typically have hundreds and, in many cases, thousands of solder bump C4 terminals, it appears likely that every chip would have solder joints with tin pest nuclei. At the maximum growth rate (40jC), the reaction will consume an entire joint in approximately 8.4 min, while at 0jC, the transformation would require 84 min.
TABLE 6 Reaction Kinetics for Two Levels of Transformation (5% and 50% Volume Fraction) from White Tin to Gray Tin Temperature(jC) 48 40 35 28 21 15
Time to transform 5% volume (min)
Time to transform 50% volume (min)
9 7.5 10 14 23 38
16 15 18 28 43 72
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FIG. 14 Graph depicting the effect of temperature on the growth rate of the white-to-gray tin transformation. The rate is a maximum at approximately 40jC.
b. Gray-to-White Tin. The transformation of gray-to-white tin occurs as the temperature is increased above the transformation temperature of 13.2jC (55.6jF) and is nucleationcontrolled. A number of nuclei form at the onset of the transformation and grow a small amount until the volume change induces the formation of more nuclei. Table 7 lists the reaction kinetics as a function of temperature, and Fig. 15 depicts the gray-to-white tin transformation rate as a function of temperature, which is approximately 100 times more rapid than the reverse transformation (i.e., white-to-gray tin). Therefore at 38jC, the transformation of a gray tin C4 terminal to white tin would occur in 3.2 sec (Fig. 16).
D.
Structure-Limited Deformation
As discussed, the properties of metallic, body-centered tetragonal white tin are far from ideal for applications in microelectronic assemblies. Tin and tin-based solders exhibit property variations along the crystallographic directions (i.e., anisotropy) which leads to significant shape changes due to thermal ratcheting (see Sec. III.C). White tin is relatively strong (3800 psi UTS) with limited ductility (50% elongation) and exhibits inferior thermomechanical fatigue resistance compared to other high-lead solders (Table 5). In addition to a severe loss in mechanical integrity, the transformation of white tin into a brittle semiconductor (gray tin) is accompanied by a very significant increase in electrical resistivity, which must be avoided as well. As noted, the white-togray tin transformation results in a 21% volume increase which cannot be accommodated by the gray tin diamond cubic crystal structure which provides few opportunities for plastic deforma-
TABLE 7 Reaction Kinetics for Two Levels of Transformation (5% and 50% Volume) from Gray Tin to White Tin Temperature (jC) +35 +32.5 +30 +27.5 +25
Time to transform %5 volume (min)
Time to transform 50% volume (min)
— 0.5 4 25 130
1 3.5 15 65 250
DEGRADATION PHENOMENA
935
FIG. 15 Graph depicting the effect of temperature on the gray-to-white tin growth rate.
tion (i.e., slip via dislocation glide). The gray tin fractures and, in some cases, is reduced to a powder.
E.
Other Factors
Solder joints are subjected to a variety of conditions that have detrimental effects; among them are temperature cycling, high current density, temperature gradients, corrosion, etc. [64]. Some of these conditions can have a significant adverse effect on the tin pest reaction. During the tin pest
FIG. 16 Schematic representation depicting the effects of time and temperature on the transformation of tin between its white and gray structures.
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reaction, gray tin is nucleated at the surface of white tin and grows into the interior of a solder joint as the temperature is decreased. Transformation of an entire solder joint will not occur if the time at the low-temperature portion of a thermal cycle is insufficient. Because the gray-to-white tin transformation is relatively quick, any gray tin that formed during cooling would be transformed back to white tin accompanied by a large volume decrease that could cause more cracking. It has been shown that this reaction can be incomplete, leaving small regions of untransformed gray tin in a white tin matrix. These regions act as nucleation sites for the growth of gray tin during the next depression below the transformation temperature. However, in these cases, the transformation rate is greatly increased because no nucleation time is required.
F.
Preventative Methods
There are a number of methods available to avoid the tin pest reaction, although some are not practical. Clearly, the tin pest reaction will not occur if the temperature is not reduced below the transformation temperature. Unfortunately, the transformation temperature is not so low that it can be avoided either during product use or shipping; therefore temperature control is not an acceptable solution. The imposition of a compressive stress is known to inhibit the transformation. This may be useful in some applications, for example, the underfill used in conjunction with flip chip solder joints (C4) exerts a compressive stress on the joints as the volume increases during the tin pest reaction. The effect of the compressive stress may be sufficient to eliminate or retard the tin pest transformation. Unfortunately, this mechanism would not apply to solder joints not utilizing an underfill material such as ball grid array (BGA) and other surface-mounted components [65]. An uncomplicated and efficient method of combating the tin pest reaction is through the addition of suitable alloying elements such as bismuth or antimony. Table 8 lists the tin pest transformation rates for two types of pure tin due to alloy additions of bismuth, antimony, lead, and cadmium [53]. The pure white tin was inoculated with particles of gray tin before the samples were aged at 10jC. The data indicate that the transformation rate was reduced to zero through the addition of either 0.5% antimony or bismuth. However, it has been determined that antimony and bismuth only exert a retarding effect on the tin pest reaction if they are in solid solution with the white tin. Even if these elements are added to provide protection against the tin pest reaction, the added elements could be depleted from the solder. For instance, a depletion could result due to reactions between the solder and chip or chip carrier terminal metallization. This effect has been observed with gold depletion from lead–tin solder alloys. Electromigration can also preferentially deplete antimony or bismuth from a white tin matrix, leaving the solder vulnerable to the tin pest reaction.
TABLE 8 The Effects of Alloy Additions on the Tin Pest (White-to-Gray Tin) Reaction Rates for Two Tin Materials Solder compositiona A or B plus addition
Tin pest reaction rate at 10jC, White-to-gray tin (mm/10 hr)
A +1% lead (Pb) +0.1% bismuth (Bi) +0.5% bismuth (Bi) +0.1% antimony (Sb) +0.5% antimony (Sb) B +2.0% cadmium (Cd) a
A—Kahlbum tin; B—Banka Tin.
0.0205 0.0075 0.002 0.0000 0.001 0.0000 0.0125 0.0095
DEGRADATION PHENOMENA V.
SOFT ERRORS
A.
What are Soft Errors?
937
It has been known for more than 20 years [66] that extraneous energetic particles (i.e., radiation) can cause random storage errors in memory devices, particularly dynamic random access memory (DRAM). These errors are referred to as ‘‘soft errors’’ (or, alternatively, upset events) because the data stored at any moment in a particular storage element are corrupted without harming the device itself. This is to be distinguished from a ‘‘hard error’’ induced by faulty device operation, where the data are lost and the storage location is rendered unusable. Today, DRAMs are generally considered to be relatively immune to soft errors, partly due to their relatively small area for capturing charge. Static random access memories (SRAMs), on the other hand, are quite sensitive, and all the more so for the leading-edge technologies [67,68]. This is true for two fundamental reasons: (1) shrinking geometries and increasing transistor densities increase the probability of a hit and (2) lower operating voltages require a lower total charge to change the state of a node [69]. The effect on other circuit types such as logic and application-specific integrated circuits (ASICs) is relatively small, but increasing in more recent products [68,70,71]. Certainly, embedded memory in logic products increases the risk of soft error rate (SER) failures. One unit of measure of soft-error-induced damage is the failure-in-time (FIT), defined as 1 fail per billion (109) device hours. To put this in perspective, consider that 1 fail per month out of 1000 parts or devices is equivalent to 1370 FITs (1 FIT=1 fail per 1.37106 device months; so 1 fail per 1000 device months=1370 FITs). As an example of the impact of soft errors on current technologies, the soft error rate for SRAMs can be in tens of kilo-FITs. This clearly drives the need to understand this subject and devise effective ways to shield devices from energetic particles. There have been many studies of SER sources and methods to predict and mitigate their effects, some of which are discussed in this section. Several references are available in the literature for a more thorough treatment of the subject [68,70,72–82].
B.
Source of Energetic Particles (Radiation)
There are multiple sources for the radiation that causes soft errors. They fit within the broad categories of cosmic rays, B10 (boron) neutron capture, alpha (a) particles from materials in microelectronic packages, and electrical noise or electromagnetic interference (EMI) [67]. The last category will not be considered further. 1. Cosmic Rays and Secondary Particles Cosmic ‘‘rays’’ are actually fast-moving particles traveling through space which constantly bombard the earth from all directions. They consist largely of protons with energies in the range of billions of electron volts. (An electron volt, abbreviated eV, is defined as the amount of energy required to move one electron through a potential difference of 1 V. Gas molecules moving in the air around us at room temperature, for instance, have an average energy of only 0.025 eV.) As these particles interact with the earth’s upper atmosphere, they create showers consisting of many types of secondary particles and also photons. Fig. 17 [83] provides information about these various types of particles. The neutron is the species with generally the highest flux at the earth’s surface (sea level). Neutrons, along with protons, also have the largest effect when they penetrate the surface of silicon. The neutron flux at sea level with energies above 10 MeV has been measured as approximately 20,000 n/khr cm2 [67] and increases exponentially with altitude. Although neutrons are uncharged, they undergo inelastic collisions in solids. In the case of the silicon lattice, they can cause recoil events that generate ionizing particles, which in turn result in charge collection at sensitive nodes, causing soft errors [74,78]. It is believed that neutrons produced by cosmic rays cause a significant fraction of the observed soft errors [72]. An estimate of the relative importance of the various sources of soft errors for SRAM devices from one study [68] is shown in Fig. 18. IBM data suggest a considerably larger contribution from cosmic rays and alpha particles [84]. Scientists [67] are aware that low energy (<100 MeV) cosmic particles of many types also
938
SULLIVAN AND KILPATRICK
FIG. 17 Cascade of secondary cosmic ray particles in the earth’s atmosphere. (From Ref. 83.)
FIG. 18 A pie-shaped chart that depicts the relative contributions of radiation types to SER in SRAM chips. (From Ref. 68.)
DEGRADATION PHENOMENA
939
contribute to SER, although less is understood of their interactions with integrated circuit (IC) packages. In summary, cosmic rays are unavoidable, so methods to effectively deal with the potential for the soft errors they generate must be appropriately addressed. Among these methods are circuit designs to create redundant circuits, error correction circuits to distinguish real signals from soft errors, use of high-capacitance nodes, use of high drive currents to minimize SER sensitivity, etc. There has also been considerable effort on the part of chip makers like IBM [73,75] to predict the sensitivity of circuit designs to soft errors due to cosmic rays. 2. B10 Neutron Capture The subject of B10 neutron capture is related to the discussion of cosmic rays above. B10 is an isotope of boron having a total of 10 protons and neutrons in its nucleus. Each element has its own unique number of protons, but occurs in nature with differing numbers of neutrons, each one being termed a different isotope of the parent element. Boron exists in nature as either B10 or B11. B10 is an unusual atom in the presence of thermal neutrons (i.e., neutrons which have essentially come to equilibrium with their surroundings, having about 0.025 eV of energy at room temperature). First, it has an extremely high capture cross section for thermal neutrons (i.e., has a high likelihood of absorbing neutrons) compared to most other isotopes, by about 3 to 7 orders of magnitude. B11, for instance, has roughly a million times smaller capture cross section for thermal neutrons than B10. Furthermore, B10 fissions (or splits) after capturing a neutron, rather than emitting a gamma ray (a high energy photon) as is typical of other isotopes, including B11. The fission reaction produces a 0.8-MeV Li7 (lithium) nucleus, a 1.5-MeV alpha particle, and a gamma photon. This sequence is shown schematically in Fig. 19. Because gamma photons do not cause soft error events, it is clearly the B10 isotope which is of concern. As noted earlier, cosmic rays produce a secondary shower of neutrons which strike the earth’s surface with a wide range of energies. A neutron of any energy can cause a spontaneous fission event in B10, but because the likelihood of capturing a neutron decreases rapidly with increasing neutron energy, only thermal neutrons are important here. Therefore thermal neutrons generated by the incident cosmic ray flux interact with boron in IC packages to create Li7 recoil nuclei and alpha particles, both of which can cause soft errors [68]. Boron is typically present in IC packages both as a p-type dopant in silicon chips and as part of the boro-phosphoro-silicate glass (BPSG) dielectric utilized to separate metal wiring levels in back-end-of-line (BEOL) processing of devices. Because BPSG typically contains 2–8 wt.% boron, and boron doping levels in silicon are orders of magnitude smaller, BPSG is the boroncontaining material which can lead to significant SER in IC packages. Considering the range of the Li7 recoil nuclei and alpha particles is less than 3 Am, and the energies which are necessary for these particles to create upset events, it has been estimated [68] that the BPSG must be within approximately 0.5 Am of an active device area within a chip. Clearly, only the BPSG in close proximity to the silicon is problematic. Recent measurements [68] on SRAM devices built in two
FIG. 19 A schematic representation of neutron capture by B10, and its subsequent fission, forming a lithium ion, an alpha particle, and a high-energy photon.
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CMOS technologies demonstrated that devices containing BPSG exhibited SER nearly an order of magnitude greater than devices without BPSG. Consequently, some chip manufacturers have eliminated BPSG from at least the first layer of BEOL dielectric. Alternatively, BPSG could, in principle, be formulated using only B11. Also, package designs can take advantage of the spongelike attraction of B10 for neutrons and add boron-rich shielding materials to IC packages to ‘‘soak up’’ thermal neutrons before they reach the active device regions. 3. Alpha Particles Another major source of soft errors is alpha particles emitted from materials in microelectronic packages. This topic is particularly germane to the subject of lead-free processing. Research at IBM has shown that the effects due to alpha particles and cosmic rays can clearly be distinguished [72]. An alpha particle consists of two neutrons and two protons, identical to the nucleus of a helium atom, He4 (Fig. 20). They are emitted during the decay of certain radioactive isotopes, several of which exist as impurities in materials used to manufacture microelectronic packages (notably isotopes of uranium and thorium). Both U238 (uranium) and Th232 (thorium) are the parents (i.e., initial atomic species) of two decay chains or radioactive series in nature, shown in Figs. 21 and 22 [85], respectively. Table 9 lists all the naturally occurring alpha emitters, some of which are not part of decay chains. Chip manufacturers often classify alpha particle sources as intrinsic or extrinsic. a. Intrinsic Sources. Intrinsic sources exist within the processed silicon itself, but generally are of little importance. They result from process-related factors such as residuals left behind from phosphoric acid etching. Phosphoric acid is commonly used for patterning silicon nitride insulator films during wafer fabrication; and it is generally of relatively low purity, containing low levels of radioactive isotopes. Other intrinsic sources include trace impurities in thin-film oxides and nitrides, extraneous impurities added to the silicon during implant operations, and impurities within a silicon wafer itself [67]. b. Extrinsic Sources. Extrinsic sources are normally distinct from the silicon chip but within the IC package. Most alpha particle sources fall into this category. The most common sources of alpha particles in microelectronic packages are listed in Table 10. Estimates of the individual contributions of some of these alpha-emitting sources are given in Table 11. It is now believed that virtually all materials used for IC packages contribute to soft error fails [68], and establishing routine monitoring procedures for incoming materials and manufacturing processes will be a necessary approach given the ever-increasing sensitivity of devices to SER due to reduced dimensions which increases proximity. c. Mechanism. Alpha particles from radioactive decay generally exhibit energies in the range of 4 to 10 MeV and can travel on the order of 25 Am within an IC package. As they travel through active device areas, they ionize the silicon along their trajectories, leaving behind approximately 1019–1021 electron-hole pairs/cm3 per radiation event. The electrons and holes are rapidly separated by the device electric field, with carriers being collected at the nearest node,
FIG. 20 An alpha particle consists of 2 protons and 2 neutrons.
DEGRADATION PHENOMENA
941
FIG. 21 The uranium series of radioactive elements. The half-lives are abbreviated as As = microseconds, s = seconds, m = minutes, h = hours, d = days, and y = years. (From Ref. 85.)
as schematically shown in Fig. 23a and b. If the collected charge exceeds the node threshold (i.e., the minimum charge needed to turn the nearest transistor on or off ), a soft error occurs. d. Avoidance. One method for reducing the effect of extrinsic alpha particles is to build circuits with the silicon-on-insulator (SOI) technology introduced by IBM in 1998 [69,86]. As shown in Fig. 23c, the buried oxide layer below the active devices significantly reduces the collection of charge during a radiation event. Another method to reduce the effect of extrinsic alpha particles is to place a shielding material on the die surface such as a thick layer of polyimide (f20 Am) which has been found effective in stopping practically all alpha particles [67,84]. Even the BEOL metal wiring levels are an important mitigating factor in the effect of incoming alphas. For a typical BEOL thickness (i.e., of the stack of metal wiring layers on top of the silicon chip) of 8.5 Am, an alpha particle emitted at the silicon surface, where the active devices are located, causes as much damage as 5 to 10 alpha particles emitted at the top of the BEOL levels [84]. Consequently, even low levels of intrinsic alpha emissions can pose as a credible SER threat. e. Relative Specific Activity. The relative specific activity of a particular isotope must be considered to account for its effect on SER. An isotope’s activity is defined as the rate at which a collection of atoms decays to form a new atomic species, referred to as the daughter product, and is inversely proportional to its half-life. An isotope’s half-life, as the name suggests, is the time required for half of a collection of atoms of a particular species to decay to its daughter species. From Figs. 21 and 22 and Table 9, it can be seen that the half-lives, and thus the specific activities, of various alpha emitters differ by roughly 21 orders of magnitude, from hundreds of microseconds to billions of years. Consider the extremes in the case of alpha particle emitters
942
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FIG. 22 The thorium series of radioactive elements. The half-lives are abbreviated as As = microseconds, s = seconds, m = minutes, h = hours, d = days, and y = years. (From Ref. 85.)
TABLE 9 Isotope
All Naturally Occurring Alpha Particle Emitting Isotopes Natural abundance (at.%)
Half-life t1/2 (years)
11 24 8 15 11 14 0.2 0.06 0.2 2 0.01 100 0.7 99
>5 1016 2 1015 >1 1017 1 1011 8 1015 >1 1016 1 1014 >1 1018 2 1016 2 1015 6 1011 1.4 1010 7.0 108 4.5 109
Ce143 Nd144 Nd147 Sm147 Sm148 Sm149 Gd152 Dy156 Hf174 Os186 Pt190 Th232 U235 U238 Source: Ref. 67.
Relative specific activity 2 108 8 107 7109 0.01 8 108 8 108 2 107 4 1012 3 108 5 108 1 106 0.34 0.005 1.0
DEGRADATION PHENOMENA TABLE 10 Packages
943
The Most Common Sources of Alpha Particles in Microelectronic
Sources Pb–Sn solder Alumina substrates BEOL metallizations Fillers in plastics, encapsulants, underfills, mold compounds, and solder masks Flux Lead frame alloys Gold used for wirebonding and lid plating Particulates from plastic ball grid array (PBGA) trimming/handling operations Source: Ref. 67.
from lead-containing solders: U238 (uranium, 4.5 109 years) and Po210 (polonium, 138 days), corresponding to a Po210 specific activity about 1.2 1010 greater compared to U238. This implies that 1.2 ppm of U238 in the solder has the same SER effect as 1010 ppm of Po210. The startling reality is that just a few Po210 atoms located on the die active surface pose as an unacceptable SER risk [84,87].
C.
Elimination of Alpha Emitters from Lead Solders
Soft errors in microelectronic packages are a difficult, troublesome problem to address. Eliminating them is virtually impossible. Soft error rate effects can be reduced in a number of ways, including the use of shielding, software correction methods (although this reduces performance), alpha particle-tolerant structures (e.g., SOI), and utilization of low-alpha-emitting materials. Let us now focus on the reduction of alpha particle-induced SER from traditional leadbased solders.
TABLE 11 Alpha Radiation Activity of Some Common Materials Utilized in Microelectronic Packages Material Processed wafers Cu metal (thick) Al metal (thick) Mold compound Underfill Pb solders ‘‘Hot’’ Pb LC II Pb (HEM) LC I Pb (HEM) Alloy 42 (Hitachi) Au-plated alloy 42 (HEM) ELJ125/Au-plated alloy 42 (HEM) Sn (HEM) AlSiC (Lanxide) LC6 Al (HEM) Source: Refs. 68 and 69.
Alpha radiation flux (a/khr cm2) 0.9 1.9 1.4 24 to <2 2 to 0.9 7200 to <2 >5000 50 to 3 1000 to 130 8 4 <1 >1000 to <1 215 8
DEGRADATION PHENOMENA
945
1. Low-Alpha Solder Lead-based solders typically are alloys of lead and tin with weight percentages of lead running from the 37% Pb eutectic composition up to high-lead solders for wafer bumping, such as the 97% alloy used by IBM for many years in their flip chip (C4) process [88]. Solder utilized for microelectronic packaging comes in several forms: solder metal (e.g., bars, spheres, preforms, wire, evaporation pellets, and electroplating anodes), solder paste, and plating solutions. In the smelting of Pb ore (principally galena), trace amounts of U and Th in the matrix rock [69,89], or Rn (radon) in the coke used as a reducing agent or in the ambient air [90], become impurities in the refined Pb. Hence Pb solder materials without special processing can be relatively radioactive, with activities as high as 5000 a/khr cm2 or above [67,69]. But chemical purification by standard methods can reduce impurity levels to the parts per million range or below, as desired. This material is available from a number of suppliers for the microelectronics industry at a variety of alpha emission levels, albeit at an increased cost to the purchaser, and is termed ‘‘low-alpha lead.’’ The practice of flip chip manufacturers is to use low-alpha lead in the range of 50 down to 10 a/khr cm2. This specification will inevitably be reduced to even lower levels of activity for future IC products. Table 12 notes a scheme used to classify the activity of low-alpha solders [91], referred to in this section. 2. Role of Po210 The decay sequence of greatest importance in the U238 decay chain (Fig. 21) is from Pb210 to Pb206: Pb210 ðh ; 22 yearsÞ ! Bi210 ðh ; 5:0 daysÞ ! Po210 ða; 138 daysÞ ! Pb206
ð5Þ
The alpha particle emitted in the decay of Po210 has an energy of 5.407 MeV [85]. Note the fact that a radioactive isotope of Pb (i.e., Pb210) exists in the middle of this decay chain and, more importantly, that it is naturally occurring in most Pb ores. A chemical purification step only removes nonlead impurities, including Po210, but not Pb210. Upon purification, the Pb210 continues to decay to its daughter products down the chain. The quantities of daughter products and the alpha particles emitted from Po210 over time can be calculated, as shown in Fig. 24. After sufficient time has elapsed, the relative quantities of all members of the chain reach a new point of equilibrium, termed secular equilibrium. This point is attained in 820 days (27 months) for Po210 as is tabulated in Table 13 [92]. The values in this table were calculated using half-lives of 8140, 5.012, and 138.38 days, respectively. To get the activity of Po210 at equilibrium, one divides the measured value by the fraction in the table corresponding to the number of days after removal that the measurement was made. Note that operations such as the evaporation or electroplating of solder material upset the secular equilibrium. Measurements of Pb solders to assess their level of activity should be extrapolated to the secular equilibrium using the method described in Table 13 or made after secular equilibrium has been attained. This, of course, assumes that the activity is only due to Po210. Measurements must be made to verify this assumption. Suppliers often choose to obtain their refined Pb from carefully selected ores low in Pb210 rather than achieve it through additional purification steps. Lead mines around the world vary widely in their concentration of Pb210 [93], with activities as low as 10 a/khr cm2 in isolated cases [87]. When very low alpha emission levels are required, so-called ‘‘old’’ Pb is often utilized. Because Pb210 has only a 22 year half-life, some manmade Pb items made many years ago, such as cannonballs, plumbing, and ballast from century-old ships, can be recovered and reused. It is also possible, but quite costly, to remove the Pb210 by an isotope separation technique. Lawrence Livermore National Laboratory developed a laser isotope purification process, with particular
FIG. 23 Schematic depicting the sequence of events in which alpha particles cause soft errors in memory devices. (a) A device node prior to an event. (b) Silicon is ionized along an alpha particle trajectory creating electron-hole pairs. (c) Presence of an oxide layer below the active device significantly reduces the collection of charge. (From Ref. 67.)
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SULLIVAN AND KILPATRICK
TABLE 12 List of Various Grades of Low-Alpha Radiation Emitting Solder Materials and Their Activity Levels Grade LC0 (normal) LC2 LC2.5 LC3 LC3.5 and below
Specification (a/khr cm2) (500 to 5000, typical) <50 <20 <5 <2
Source Worldwide Selected mines Selected mines ‘‘Old’’ lead Pb-free solders or isotope separation
(Projected) Year needed N/A 1999 2002 2004 2008
Source: J. Griffith, IBM Corp.
effort recently to deploy a production-type tool capable of producing large quantities of ultrapure Pb at or below 1 a/khr cm2 for chip interconnections [87]. Russian scientists developed a similar process [94], which has been used to produce a 2 a/khr cm2 solder available through a U.S. vendor in limited quantities. 3. Flip Chip Solder Joints The issue of alpha particles released from solders has received significantly more attention in recent years corresponding to the move to flip chip packaging, where solder bumps are placed in arrays across the active chip area instead of the chip periphery. Logic chips with thousands of bumps per die are becoming commonplace. One possible option to reduce the incidence of soft errors is to define exclusion zones around particularly sensitive nodes, eliminating solder bumps directly above those locations. The tradeoff of SER improvements must be weighed against undesirable increases in chip size. Finally, to make matters worse, processing steps after the solder bumps are placed on a chip, such as rinsing, ashing, fluxing, and under-bump-metallurgy (UBM) etching, can produce solder residues on the chip surface. Care should be exercised to ensure that very thin layers of alpha-emitting material are not spread over large interbump regions.
FIG. 24 Plot depicting the concentrations of Po210 and Bi210 formed from Pb210 decay over time in freshly refined lead, and the associated alpha radiation flux. (From Ref. [69].)
DEGRADATION PHENOMENA TABLE 13 Days 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
947
Approach to Secular Equilibrium for Po210
Fraction
Days
Fraction
Days
Fraction
Days
Fraction
Days
Fraction
0.0003 0.0013 0.0029 0.0049 0.0074 0.0102 0.0133 0.0167 0.0203 0.0241 0.0281 0.0322 0.0364 0.0408 0.0452 0.0497 0.0543 0.0589 0.0635 0.0682 0.0729 0.0776 0.0823 0.0871 0.0918 0.0965 0.1013 0.1060 0.1107 0.1154 0.1201 0.1248 0.1295 0.1341 0.1388 0.1434 0.1480 0.1525 0.1571 0.1616 0.1662 0.1707 0.1751 0.1796
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
0.1840 0.1884 0.1928 0.1972 0.2016 0.2059 0.2102 0.2145 0.2187 0.2230 0.2272 0.2314 0.2356 0.2398 0.2439 0.2480 0.2521 0.2562 0.2602 0.2643 0.2683 0.2723 0.2763 0.2802 0.2841 0.2881 0.2919 0.2958 0.2997 0.3035 0.3073 0.3111 0.3149 0.3186 0.3224 0.3261 0.3298 0.3335 0.3371 0.3408 0.3444 0.3480 0.3516 0.3552
89 90 91 92 93 94 95 96 97 98 99 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164
0.3587 0.3622 0.3658 0.3693 0.3727 0.3762 0.3796 0.3831 0.3865 0.3899 0.3932 0.3966 0.4032 0.4098 0.4164 0.4228 0.4292 0.4355 0.4418 0.4480 0.4541 0.4602 0.4662 0.4721 0.4780 0.4838 0.4896 0.4953 0.5009 0.5065 0.5121 0.5175 0.5229 0.5283 0.5336 0.5389 0.5441 0.5492 0.5543 0.5593 0.5643 0.5692 0.5741 0.5790
166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 204 208 212 216 220 224 228 232 236 240 244 248 252 256 260 264 268 272 276 280 284 288 292 296 300 308
0.5837 0.5885 0.5932 0.5978 0.6024 0.6069 0.6114 0.6159 0.6203 0.6246 0.6289 0.6332 0.6374 0.6416 0.6457 0.6498 0.6539 0.6579 0.6657 0.6735 0.6810 0.6884 0.6957 0.7028 0.7097 0.7165 0.7232 0.7297 0.7361 0.7424 0.7485 0.7545 0.7604 0.7661 0.7717 0.7772 0.7826 0.7879 0.7931 0.7981 0.8031 0.8079 0.8126 0.8218
316 324 332 340 348 356 364 372 380 388 396 404 412 420 428 436 444 452 460 468 476 484 492 500 516 532 548 564 580 596 612 628 644 660 676 692 708 724 740 756 772 788 804 820
0.8306 0.8390 0.8471 0.8548 0.8622 0.8692 0.8760 0.8825 0.8886 0.8945 0.9002 0.9056 0.9108 0.9157 0.9204 0.9249 0.9292 0.9333 0.9372 0.9409 0.9445 0.9479 0.9511 0.9542 0.9599 0.9650 0.9697 0.9739 0.9776 0.9810 0.9840 0.9866 0.9890 0.9910 0.9928 0.9944 0.9957 0.9968 0.9977 0.9985 0.9991 0.9995 0.9998 1.0000
The chart shows the buildup of Po210 from pure Pb210 following the sequence in Eq. (5), as a function of days after Po210 removal. Source: Ref. 92.
948 D.
SULLIVAN AND KILPATRICK Lead-Free Solders can be a Concern
Based on the discussions in prior sections, the soft error concern associated with traditional leadbased solders is quite clear, but what is less clear is why lead-free solders can potentially pose a SER concern. Because the overriding SER concern with lead-based solders is alpha particle emission by Pb210, then it may be reasoned that solders which do not contain Pb do not emit alpha particles. Understandably, there are many in the industry making that assumption. Although lead-free solders may be the best path to very low alpha particle-emitting solders for SER-sensitive products, they can also be sources of radioactivity unless proper processing steps are taken. 1. Impurities in Tin Lead-free solders generally contain mostly tin, with other metals such as silver, copper, antimony, bismuth, or zinc in small amounts of up to a few percent. It has been determined at IBM and elsewhere that Sn and Sn-rich solder materials (such as 99.99% Sn pellet anodes, immersion-Sn plating baths, Sn–Cu bars, and Sn–Ag–Cu pastes) can be quite radioactive, in the range of 200 to 5000 a/khr cm2, and whose activity has been found can vary considerably from lot to lot [95]. Recall that 5000 a/khr cm2 is near the upper limit of activity encountered for normal Pb solder materials, as defined in Table 11. These measured levels of activity were at first both surprising and confounding because no Sn isotopes are alpha particle emitters (Table 14). Therefore Sn cannot be responsible for the measured high activity levels. Alpha energy spectrometer measurements have only indicated a 5.407-MeV peak for Po210 alpha particle emission from these materials [95]. In the case of an immersion-Sn bath, for instance, the initial activity was measured at 700 a/khr cm2, as noted in Table 15. Then the Po210 level was reduced to just a few a per kilohour square centimeter by an extended interval of plating, and the bath was allowed to sit for several weeks before another sample was plated. That final sample measured above 100 a/khr cm2, indicating the presence of parent Pb210 in the bath producing Po210. Furthermore, secular equilibrium calculations showed that there was sufficient Pb210 present to account for all the bath activity. This indicates the contamination was not just Po210 from a processing step, but Pb contamination in the Sn starting material. This conclusion has also been arrived at by others [94,96] based on a variety of commercially available, Sn-based, Pb-free solder materials. This results from the fact that ordinary Sn contains trace amounts of Pb that cause unacceptable levels of alpha radiation. 2. Effect of ‘‘Young’’ Lead There is, however, a disproportionately high level of alpha particle emissions given the measured trace amounts of Pb present. That is, analysis conducted at IBM has shown that the typical Pb contamination level is only in the parts per million to tens of parts per million of Pb range [97]. If the isotopic distribution for that quantity of Pb was the same as normally found in Pb mines, there would be no serious SER issue with Sn. However, the Pb impurity in Sn materials is vastly enriched in Pb210. In other words, the Pb impurity is younger, or farther up the decay chain, with fewer stable Pb isotopes.
E.
Elimination from Lead-Free Solders
Chip and microelectronic package manufacturers intending to implement Pb-free solders assumed it would also serve as a simple fix to the SER problem. Vendors of Sn-rich materials were surprised when confronted with the alpha particle emission issue. 1. Made-to-Order Solder The general approach taken by material vendors is to match the Sn source to a particular product. In some cases, this means offering both a standard and a low-alpha product, and in other cases, it means acquiring multiple Sn sources and offering ‘‘made-to-order’’ solder materials. Tin sources are available for LC2-quality materials without the need for further processing. In some cases, vendors opt to specify Sn purity to customers rather than the activity level, but this can be risky because purity does not necessarily guarantee a minimum allowable activity level. When further
DEGRADATION PHENOMENA TABLE 14 Isotope Sn108 Sn109m Sn109 Sn110 Sn111 Sn112 Sn113m Sn113 Sn114 Sn115 Sn116 Sn117m Sn117 Sn118 Sn119m Sn119 Sn120 Sn121m Sn121 Sn122 Sn123m Sn123 Sn124 Sn125m Sn125 Sn126 Sn127m Sn127 Sn128 Sn129m Sn129 Sn130 Sn131 Sn132
949
Listing of Tin Isotopes Natural abundance (at.%)
Half-life
Decay mode
9 min 1.5 min 18.1 min 4.0 hr 35 min
EC h+, IT h+, EC EC h+, EC
20 min 115 days
IT, EC EC
14.0 days
IT
f250 days
IT
76 years 27 hr
h h
40 min 129 days
h h
9.7 min 9.6 days f105 year 4 min 2.1 hr 59 min 2 min 9 min 2.6 min 1.3 min 2.2 min
h h h h h h h h h h h
0.96
0.66 0.35 14.30 7.61 24.03 8.58 32.85
4.72
5.94
The various decay modes are abbreviated as h+ for positron emission, h for negative beta emission, EC for orbital electron capture, and IT for isomeric transition from upper to lower isomeric state. Source: Ref. 85.
refinement of Sn is required to meet industry demands for low-alpha solder, it is generally a matter of chemically removing Pb impurities, which is much less difficult than removing specific isotopes of a given species. 2. Low-Activity Level Solders At the LC3 level and below, it may be necessary to specify high-purity metals, perhaps in the five 9’s range, for alloying components such as Ag and Cu, to remove traces of alpha-emitting impurities. There are two additional issues to achieve very low alpha emission levels. First, the detection of low-alpha emission levels is very difficult [87,98,99], with equipment limits at approximately 2–4 a/khr cm2 [71]. Second, the measurement of low impurity levels in Sn can
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SULLIVAN AND KILPATRICK
TABLE 15
Measurement Sequence of Radioactivity in Immersion Tin Bath
Action Initial measurement Long period of immersion Sn plating Bath idle for 38 days Final measurement
Activity (a/khr cm2)
Comments
700 30–40
Alpha radiation from Po210 Po210 selectively removed from bath
— 117
Pb210 generates more Po210 Secular equilibrium projected to be 450–700, depending on how much new Pb210 was also generated
Source: B. Bonitz and T. Zabel, IBM Corp.
be problematic. Glow discharge mass spectrometry (GDMS) for instance, which is generally an excellent technique for impurity concentrations in the parts per billion (ppb) range, is difficult for Sn because Sn–Sn pairs (dimers) can form in the discharge which coincidentally overlap the masses of U and Th isotopes and mask their detection [96]. This can, for instance, result in a sensitivity for U and Th which is 50–100 times worse than that for Ag and Cu within Sn.
VI.
INTERFACES IN SOLDER JOINTS
A.
General Description
An interface is a surface that forms a common boundary between two bodies or phases. A number of different types of interfaces are discussed in this section. Some interfaces form as the result of a solder reaction with chip or chip carrier terminal metallizations. These interfaces separate layers of intermetallic compounds and form boundaries between solder and the unreacted terminal metal. Other interfaces exist between metal and insulation layers. A number of critical interfaces form between an underfill and chip, substrate and solder. The solder contains a number of interfaces including grain boundaries, phase boundaries, and boundaries between intermetallic particles and the solder. Fig. 25 illustrates interfaces that exist in a terminal made with Pb–Sn solder, Ti–Cu–Au under bump metallurgy (UBM) mounted on a chip carrier with Ni–Au metallization and reflowed in a hydrogen environment. These interfaces must perform a number of critical roles in the formation of solder joints. The interface supports large structure and composition differences between phases and also contains and controls electrochemical barriers [100].
B.
Structural and Mechanical Characteristics
The atomic structure of an interface can vary depending on the materials being joined. Some interfaces are epitaxial, i.e., maintain a specific orientation relationship between phases. Some interfaces maintain coherency such that the lattice planes are continuous through the interface extending from one phase to the next. Grain boundaries are special interfaces that consist of orientation differences with no change in composition. In general, the interfacial energy is minimized by satisfying all bonds, maintaining a unique nearest neighbor distance, minimizing bond angle distortion, and by minimizing the interfacial thickness. Lattice imaging of interfaces between phases reveals that the interfacial thickness is on the order of a few atomic distances [101]. The interface can be visualized as a thin region of distorted, noncrystalline material that deforms in a perfectly elastic manner at low temperature. This type of general interface will be subject to brittle fracture because there are no mechanisms available for plastic flow to blunt the crack tip as occurs in metals. The stress–strain behavior of a general interface is compared with several common materials utilized in microelectronic packaging in Fig. 26. The elastic characteristic implies that the bonds between atoms on either side of an interface elongate elastically as a
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FIG. 25 Schematic that depicts an example of the numerous interfaces observed in flip chip (C-4) solder joint structures.
stress is applied until the maximum interfacial strength is exceeded, resulting in a brittle fracture. However, at elevated temperature, grain boundaries can slide and provide metals with a deformation mode when heated above approximately one-half of the absolute melting temperature. Note that one-half of the absolute melting temperature for lead is 27jC and for tin it is 21jC. The stress–strain behavior of lead and tin solders (Fig. 26) results from a combination of grain boundary sliding and dislocation movement required to accommodate sliding at obstacles such as triple points and intermetallic particles located on the grain boundaries. Fig. 26 also indicates that intermetallic compounds are brittle and very strong compared to solder. Stresses transmitted to intermetallic compounds via the solder are therefore elastic [102]. In a properly made solder joint, the solder should always be the weakest link, deforming to relieve stresses so they are not transmitted beyond the terminal pads on either side of the joint. Additionally, this is the preferred failure mode because solder fails due to the accumulation of plastic strain damage and the failure behavior can be modeled and predicted. That is, the interfaces in a proper solder joint fail when the interfacial strength is degraded due to any number of mechanisms such as a phase change, impurities, void accumulation, etc. If the interfacial strength is reduced below the applied stress, the interface fails. This type of failure mode is more difficult to model and predict compared to the accumulation of plastic strain damage in the bulk solder.
C.
Effect of Phase System on Mechanical Properties
1. No Mutual Solubility or Intermetallic Compound Formation System The mechanical properties of interfaces can be predicted based on the form of the binary equilibrium phase diagram [103]. Weak interfaces result in phase systems which do not form compounds or exhibit solubility. This behavior results because the unlike atomic species repel each other, typical of a system like Cr–Cu (Fig. 27). The binary phase diagram shows these species do not exhibit solubility or compound formation, and that the metals do not mix in the liquid state for most compositions. Interfacial adhesion can be improved in these systems by the addition of a ‘‘glue layer’’ which reacts with both metals. For the Cr–Cu system, the glue layer can be oxygen or another metal such as aluminum. Alternatively, the adhesion can also be achieved
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FIG. 26 Plot depicting the relative mechanical properties of various materials and structures found in microelectronic packages.
FIG. 27 Illustration of the main features of the chromium–copper binary equilibrium phase diagram. This system exhibits no mutual solubility or compound formation, resulting in weak interfacial strength. (From Ref. 105.)
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by forming a mechanically interlocked, rough interface created through codeposition techniques. This technique has been used with great success for over 30 years at IBM as part of their chip terminal UBM (stacked thin film) structure capable of withstanding in excess of 100 reflows. The advantage of this type of interface is that no reaction occurs during high-temperature process steps, and so no degradation in strength results. It should be noted that the structure of the socalled phased region which consists of codeposited species is critical. 2. Some Mutual Solubility, No Intermetallic Compound Formation System A system such as Ni–Cu (Fig. 28) that exhibits mutual solubility but no compound formation typically yields good adhesion [104]. The Ni atoms are accommodated on the Cu lattice, and Cu atoms are accommodated on the Ni lattice without restriction allowing a continuous series of solid solutions for all compositions involving both species. The reactive nature of this type of system can, however, cause problems during high-temperature process steps during which diffusion occurs resulting in complete mixing of the Cu and Ni layers which leads to large increases in electrical resistance. 3. Systems with Intermetallic Compound Formation A binary phase system that forms an intermetallic compound normally provides good adhesion because of the mutual attraction between atoms of different species. Examples of this type of system include Ti–Cu, Ni–Sn, and Sn–Cu (Fig. 29) [105]. Intermetallic compound formation occurs during high-temperature process steps, and the consequences are usually undesirable, resulting in increased stress levels, impurity snowplowing, Kirkendall voids, and an increase in electrical resistance. These reactions must be controlled either by limiting the amount of reactants available or by controlling the time and temperature of the reaction.
D.
Reaction at Flip Chip Under-Bump-Metallurgy Interfaces
1. Reactive vs. Nonreactive Under-Bump-Metallurgy Structures As noted in the previous section, reactive interfaces are usually required in order to achieve acceptable strength in a solder joint. These interfaces not only exist between the solder and the
FIG. 28 Illustration of the main features of the copper–nickel binary equilibrium phase diagram. This system exhibits complete solubility in all proportions, thus forms strong interfaces. (From Ref. 105.)
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FIG. 29 Illustration of the main features of the copper–tin binary equilibrium phase diagram. This system exhibits compound formation, thus forms strong interfaces. (From Ref. 105.)
chip and substrate metallizations, but within the chip and substrate terminal metallization. The notable exception to this generalization is the Cr–Cu UBM system that relies on mechanical interlocking to achieve adhesion rather than chemical bonding [106]. The Ti–Cu–Au UBM system shown in Fig. 25 is an example of a reactive system [107]. Both sputtered and evaporated Ti contain approximately 2% to 5% oxygen that is partitioned between oxygen in solid solution with Ti as well and as titanium oxide at surfaces and grain boundaries. Copper forms a weak bond with the surface oxide; but strong interfacial adhesion requires a reaction between the Ti and Cu, which can only occur if the intervening oxide is not present. The Ti–O binary phase diagram [108] shows that approximately 3% oxygen forms solid solution with Ti at 300jC. At this temperature, the Ti and Cu react to simultaneously form the three layers of intermetallic compound: TiCu, TiCu2, and TiCu3. Au from the top UBM layer diffuses through the Cu layer to form TiAu4 at the expense of the Ti–Cu compounds because TiAu4 has a lower free energy of formation compared to the Ti–Cu intermetallic compounds. If the structure is heated above approximately 300jC in hydrogen or forming gas, the Ti also reacts to form TiH2 which prevents the formation of the Ti– Cu compounds also due to free energy considerations. When Ti reacts to form the hydride (TiH2), there is an attendant 30% increase in thickness due to an allotropic transformation from a FCC to FCT crystal structure at approximately 50jC, which also results in a significant volume change [109]. The Ti-based UBM system is extremely reactive and can be difficult to control and its behavior is much different from the nonreactive Cr–Cu system. The difficulties of forming an adequate Cr–Cu phased region are tolerated in order to achieve good adhesion, but with no complicated reactions. 2. Complex Stacked Under-Bump-Metallurgy Structures As UBM structures become more complex, other reactions can occur. A Cr–Cu–Ni–Au structure has been used to reduce the intermetallic compound thickness during reflow (Fig. 30). This occurs because Sn reacts more slowly with Ni than Cu. Upon heating the structure, there is a counterdiffusion of Cu and Au through the Ni layer to form Au–Cu solid solution on both sides of the Ni. The diffusion in the Au and Cu layers is due to both bulk and grain boundary diffusion.
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FIG. 30 Depiction of interdiffusion in the copper–nickel–gold system showing grain boundary and lattice diffusion in low melting point copper and gold with only grain boundary diffusion in high melting point nickel.
Because Ni has a much higher melting temperature than either Cu or Au (Ni: 1455jC, Au: 1064jC, Cu: 1084jC), diffusion in the Ni layer is primarily in the grain boundaries. After the reaction, a Cu-oxide layer usually exists on top of the Au–Cu layer, and the underlying Cu layer exhibits a high electrical resistance due to the Au interdiffusion. The Ni layer contains a small amount of Cu and Au at grain boundaries.
E.
Liquid Solder Reaction with Flip Chip Terminal Pads
When the liquid Pb–Sn solder reacts with the terminal metallization, several reactions occur. At 360jC, liquid lead can dissolve 40% of its own weight in Au; and at 260jC, liquid Sn can dissolve about 25%. Consequently, any Au on the UBM or chip carrier terminal pad surface will dissolve in the liquid Pb or Sn where it is very mobile. The Au is transported throughout the solder and, on cooling, becomes part of the intermetallic compounds at the terminal interfaces and within the bulk solder. The presence of these intermetallics can cause problems as noted below. High-lead solders such as 97Pb–3Sn react with Cu to form Cu3Sn at approximately 360jC [110]. During this reaction, the Cu and Cu3Sn remain solid and only the solder is liquid. Upon cooling, some Cu3Sn reacts with Sn in the solder resulting in a solid-state peritectic decomposition reaction to form a layer of Cu6Sn5 which dissolves in the liquid solder and reprecipitates during each subsequent reflow. Eutectic 63Sn–37Pb solder reacts with Cu to form the same two intermetallic compounds. Eutectic Sn–Pb and 97Pb–3Sn solders react with Ni and generally form two intermetallic compound layers: Ni3Sn4 and Ni3Sn2. As illustrated in Fig. 25, the sequence of intermetallic compound (IMC) layers is that the most Sn-rich compound is in contact with the solder. The Sn concentration decreases in each subsequent IMC layer from the solder. The reaction of high-Sn solders with Cu and Ni terminal metallization results in the same IMC structures except that the most Sn-rich compound predominates the reaction with Cu and produces primarily Cu6Sn5 with little or no Cu3Sn, while the reaction with Ni produces Ni3Sn4.
956 F.
SULLIVAN AND KILPATRICK Flip Chip Pull (Tensile) Test and Interpretation
One of the simplest and most useful tests performed on reflow-attached flip chips to determine the adequacy of the solder joints (i.e., C4) is a tensile pull test (Fig. 31). This is done by adhesively attaching a metal stud to the back of a joined chip and pulling the joints in tension at a slow strain rate (approximately 1.0103 sec1). The pull force is measured during the test using an appropriate load cell. The pull strength is a useful parameter, but the failure mode is a very important indicator of joint quality. Planar failure at the solder joint interfaces is indicative of a weak and unacceptable interface condition. 1. Pb–Sn Solder Joints Fig. 21 is a plot that depicts the relative strengths of several features of a solder joint. In a properly fabricated joint, the intermetallic compounds are very strong and deform elastically, but should never fracture. In a tensile test, a properly formed high Pb/Sn solder joint always fails within the bulk solder which implies that the strengths of the interfaces depicted in Fig. 25 are greater than the strength of the solder. Note that the stress–strain behavior of only one interface is shown in Fig. 26. Although each interface shown in Fig. 25 exhibits a different stress–strain behavior, each must possess a tensile strength greater than the solder. If an interface in the structure is weaker than the solder, it will result in a brittle, planar failure in a tensile pull test. A change in fracture mode from plastic solder fracture to brittle elastic interface fracture is usually an indication that a terminal is defective. Lead-rich solders are usually weaker and more ductile than tin-based solders (Fig. 26).
FIG. 31 Schematic representation depicting the pull test used to determine interfacial integrity in flip chip solder joints. (a) Pull test configuration and conditions. (b) Ductile solder fracture indicating good interfacial strength. (c) Brittle or planar interfacial fracture indicative of unacceptable interfacial strength.
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2. Pb-Free Solder Joints Some modifications of the standard tensile pull test may be required for lead-free solders with high-Sn contents which are typically stronger than high Pb–Sn solders causing failures in the chip insulator or chip carrier. This can confuse data interpretation but is not necessarily a concern if the pull strength is adequate, and no joint interfaces fail.
G.
Examples of Degraded Interfaces
1. Impurities The strength of an interface can be degraded in a number of ways. Key among them is the presence of impurities at an interface [111]. For example, in the Ti–Cu UBM system, the reaction to form intermetallic compounds snowplows the oxygen present in the as-deposited Ti. The oxygen accumulates at the reaction interface causing it to become severely weakened. Degradation of an interface in a reactive system (e.g., Ti–Cu) where the initial interface between Ti and Cu is replaced by four interfaces, Ti–TiCu–TiCu2–TiCu3–Cu, any of which could be weaker than the original interface, can be complex. In many UBM thin-film stacks, the reactive layers are made relatively thick (2 to 5 Am) in order to prevent the reaction front from reaching an interface to cause weakening. This approach works but at the expense of an increased stress-thickness product which can cause a normally good interface to fail when the force becomes too great. Note that the force exerted by a film is equal to the stress in the film (usually thermal stress) times the film thickness [112]. As indicated above, good interfacial adhesion can be achieved in binary systems that are reactive, but the consequences of reaction are usually undesirable. Impurity snowplowing is one effect that can occur. It should be noted that the greater the amount of reaction, i.e., thickness of reaction product, the greater the amount of impurity that accumulates at an interface to cause weakness. 2. Accumulation of Nonwettable Material Another example involves joining to plated electroless Ni metallization. If plated from a hydrophosphate bath, the deposit typically contains from 3% to 10% P, and during reaction accumulates a weak layer of Ni3P near the interface during a reaction with the molten solder. If the accumulation is sufficient, it results in a planar separation at the solder/Ni deposit interface because the Ni3P is not wet by solder. Note that this reaction occurs during the liquid solder reflow operations and in the solid state during high-temperature storage. During the reaction, the Ni–Sn intermetallic compound grows thicker and P is rejected at the reaction front where Ni3P forms [113]. Fig. 32 shows an example of interfacial weakening in which the strength is degraded but there is no change in the slope, i.e., elastic modulus, of the curve. It is also possible for the modulus to decrease until the interface is weaker than the solder. This can be due to impurities or can result as the materials at the interface change due to reaction. In the example discussed above, the strong Ni-to-Ni3Sn4 interface is replaced by a weaker Ni-to-Ni3P interface. 3. Kirkendall Void Formation Another reaction that can lead to interfacial weakening is Kirkendall void formation [114]. In a reactive system like Cu–Sn, the reactants are initially separated by an interface which is on the order of a few atomic distances (Fig. 33). When the reaction is initiated, the reactants become separated by a layer of reaction product. Further reaction requires that the reactants diffuse through the reaction product, Cu3Sn in this example. The initial reaction kinetics are interfacecontrolled and the growth of the layer is linear with time (Fig. 34) [115]. The interface reaction is one in which a Cu atom, as an example, jumps from the Cu to the Cu3Sn crystal lattice structure. When the reaction product reaches a critical crossover thickness, on the order of 100 nm, the kinetics become diffusion-controlled and growth proceeds as time to the one-half power. The crossover thickness is equal to the parabolic rate constant divided by the linear rate constant. In this example, further growth of Cu3Sn proceeds as the Cu diffuses through the Cu3Sn to react with Sn at the Cu3Sn–solder interface. At the same time, Sn counterdiffuses (i.e., diffuses in the opposite direction) through the Cu3Sn to react with Cu at the Cu–Cu3Sn interface. The rates at
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FIG. 32 Plot that depicts the relative mechanical properties of several materials and structures found in solder joints (solid lines). Also noted are the effects of various conditions on those materials and structures (dotted lines).
FIG. 33 Schematic representation depicting the formation of Kirkendall voids during the reaction of copper with tin to form intermetallic compounds. The imbalance in the diffusion fluxes between copper and tin atoms results in the generation of atomic vacancies that condense to form voids.
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FIG. 34 Graphic representation of the change in reaction kinetics with reaction product thickness. Below the cross over thickness, xc, the thickness of the reaction product is proportional to the reaction time t and above xc, the thickness is proportional to t1/2.
which Cu and Sn diffuse through Cu3Sn are not equal. For this system, Cu diffuses more quickly than Sn and the result is that atomic-sized vacancies are generated in the Cu to preserve the mass balance. As the reaction proceeds, the vacancy concentration increases until supersaturation occurs resulting in the nucleation and growth of voids. The reaction front typically grows well beyond the voids so they become imbedded in the reaction product. As was the case for impurity snowplowing, the greater the amount of reaction product, the greater the void volume. Fig. 35 depicts Kirkendall voids that formed in the Ni–Sn system with a high-Sn, lead-free solder. The unreacted Ni is void-free, while there are numerous voids in the Ni3Sn4 reaction product. These voids usually form close to a reaction interface, reducing the interfacial area but not necessarily the interfacial strength. Fig. 32 shows the effect of the voids on the properties of intermetallic compounds. The cross-sectional area of the intermetallics is reduced and the presence of voids results in a stress concentration at void surfaces [116]. For a spherical void, the stress concentration factor is typically three times the nominal stress.
FIG. 35 Schematic depiction of Kirkendall voids in Ni3Sn4 at the Ni interface, but the unreacted Ni is void-free. The voids and reaction product were formed when Ni reacted with a high-tin, lead-free solder.
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4. Spallation Another reaction mechanism which can cause interfacial weakening is the spalling of a reaction product to expose underlying interfaces to molten solder. Spalling is the flaking and cracking of particles from a reaction product surface into molten solder (Fig. 36). When a high-lead solder is in contact with Cu metallization during a reflow operation, some of the Cu dissolves into the molten solder to satisfy the solubility requirements. The dissolved Cu comes primarily from the Cu grain boundaries and results in spalling the grains. This effect can be significantly reduced or eliminated by presaturating the high-lead solder with Cu. In most cases, a small amount of spalling is not harmful. However, spalling reactions can occur which completely remove the reaction product and expose weak interfaces. The addition of a small amount of Pd to a high lead–Cu system has a very significant effect on the spalling behavior. The Pd reacts to form a ternary intermetallic compound that is a 1:1 mixture of PdSn4 and Cu3Sn. It also forms a ternary eutectic (99.4Sn, 0.1Pd, and 0.5Cu, MP=217jC) that causes all of the ternary intermetallic compound to spall into the molten solder. If Cu is deposited directly on a Cr layer, the spalling creates a situation in which the Cr is directly exposed to molten solder resulting in dewetting. The interfacial strength is greatly reduced and a brittle, planar failure occurs at the solder–Cr interface. The Cr–Cu phasing used as part of IBM’s flip chip (UBM) terminal structure is designed to survive this type of gross spalling by providing mechanical interlocking at the interface. 5. High Strain Rate Effects Fig. 32 depicts the relative strengths of intermetallic compounds, the solder–intermetallic interface, and the solder. As noted earlier, in a typical flip chip solder joint, the solder is the weakest link and therefore the portion of the terminal structure that fails due to plastic deformation in a pull test or during thermal cycling. The intermetallic compounds and the interface can, however, be weakened as discussed above so that failure shifts to these locations rather than within the solder. The figure also shows that the strength of solder can be increased through plastic deformation at high strain rates [117]. The strength of the interface and intermetallic compound strengths are not affected by strain rate increases because these structures deform elastically. If high strain rates are used in a pull test, the solder strength can be increased above the product application conditions. This can induce artificial failure modes which a product will not experience. The use of low strain rate results in a more meaningful pull test.
FIG. 36 Schematic representation depicting intermetallic spalling into solder in a typical flip chip (C-4) terminal.
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RELIABILITY CONSIDERATIONS
Solder joints must be capable of meeting stringent reliability requirements discussed in detail in Chaps. 19 (Reliability), 20 (Thermomigration/Electromigration), and 21 (Tin Whiskers). Some of these issues are discussed briefly in this section for convenience of providing an overview.
A.
Multiple Reliability Requirements
1. Solder Reaction-Related Factors Solder joints in microelectronic assemblies, and especially flip chip solder joints (C4 terminals), must meet a host of reliability requirements simultaneously (see Table 5). Initial reactions of the liquid solder with the various chip and chip carrier metallizations must result in generally defectfree interface structures that provide adequate adhesion. This alone is a stringent requirement because this is a special case of liquid metal in contact with a thin-film metal, a situation that often leads to embrittlement. The type and amount of reaction products must be controlled to achieve adequate adhesion, and the chip UBM metal must act as a diffusion barrier to prevent a liquid solder reaction with the chip metallization [118]. Multichip modules such as microprocessor modules that consist of multiple logic and memory chips and capacitors sometimes must be reworked to meet yield or reliability objectives. Rework subjects solder joints to multiple reflows which results in additional reaction and increases the potential for those problems discussed in the previous section. Solder reactions involving chip and chip carrier terminal pad metal continue to occur in the solid state during high-temperature storage tests (typically 150jC) and during applications in the field at temperatures as high as 125jC that can lead to terminal failure. 2. Creep and Fatigue Resistance During product test and some field conditions, the solder is subjected to temperature extremes of 55jC to 150jC or higher. These temperature cycles result in the imposition of large cyclic stresses and strains that cause the solder to fail due to complex interactions of creep and fatigue fracture mechanisms. If a chip underfill is employed, the critical interfaces between the underfill and chip and chip carrier are subjected to high alternating stress that can cause fracture, especially in the presence of impurities and contamination. 3. Thermomigration Based on experience with solder alloys with different relative melting temperatures, it can be inferred that thermomigration may be a serious concern for tin-based solders because low melting temperature usually correlates with high atomic mobility. High-lead solder alloys, such as 3Sn– 97Pb (MP=325jC), are fairly resistant to thermomigration failure at microelectronic application conditions. There have been reports of thermomigration damage in eutectic Sn–Pb (MP=183jC) and 50Pb–50In (MP=220jC). C4 terminals made with 50Pb–50In failed due to the growth of solder voids located within the chip via hole which grew due to atomic diffusion in the direction of the temperature gradient from the chip to chip carrier. Pure tin melts at 232jC and some alloys under consideration have even lower melting temperatures; the Sn–Cu–Ag eutectic melts at 217jC. If atomic mobility is related to melting temperature, then (in the absence of data) high-tin alloys are anticipated to behave like 50%Pb–50%In alloy relative to this failure mode. The atomic flux equation describing thermomigration [119]: J ¼ CðD=kTÞðQ*=T dT=dxÞ ðatoms=cm2 secÞ
ð6Þ
where C=concentration of diffusing species (atoms/cm3); D=diffusity=D0 exp[DH/kT] (cm2/ sec); DH=activation energy (eV); dT/dx=temperature gradient (jC/cm); kT=thermal energy (eV); and Q*=heat of transport (eV). In this relation, the heat of transport is the critical quantity. Very little data are available in the literature; work needs to be done on tin-based alloys.
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4. Electromigration Electromigration has been discussed in detail in a previous chapter in this handbook. The following is a calculation that shows the relative electromigration resistance of high-lead and high-tin solder alloys. This is the basis for the lifetime comparison shown in Table 5. The atomic flux equation for electromigration is based on the Einstein relation for diffusion with a driving force [120], J ¼ DFC=kT
ð7Þ
where J=mass flux (atoms/cm2/sec); D=diffusivity (cm2/sec); F=driving force (eV/cm); C=concentration of diffusing species (atoms/cm3); and kT=thermal energy (eV). For electromigration, the driving force is: F ¼ z*eqj ðeV=cmÞ
ð8Þ
where z*=effective charge or valence (no units); e=electronic charge (e); q=electrical resistivity [V cm=(V cm)/amp]; and j=current density (amp/cm2). The electromigration lifetime is proportional to 1/J and the relative lifetimes of tin and leadbased solders are calculated by determining JSn/JPb, the ratio of the mass flux in the tin-based alloys to lead-based alloys. According to Black’s Law [121], lifetime varies as J2 due to voidnucleation-dominated failure. The J1 behavior relates to failure due to the growth of existing voids or for fast void nucleation compared to growth. The lifetime ratio is determined by substituting the value of F from Eq. (8) into Eq. (7). The diffusivity in Eq. (7) is given by D ¼ DoB expðDHB =kTÞ ðcm2 =secÞ where DoB=bulk diffusion pre-exponent (cm2/sec) and DH=bulk diffusion activation energy (eV). In utilizing this approach, it is assumed that failure occurs by bulk diffusion, and that both the tin- and lead-based solders have approximately the same grain size, meaning that CSn=CPb. It also assumes that the current densities are equal in both the high-tin and high-lead solders. Substitution of the parameters listed in Table 16 into the flux relations provides a flux ratio JSn/ JPb=2.0. This states that the electromigration lifetime of tin-based solders will be about one-half of high-lead solders.
B.
Relaxation and Recrystallization
During product use, solder joints in microelectronic assemblies are subjected to temperature excursions corresponding to power on and off cycles. Strains are generated within solder joints due to the mismatch in the coefficient of thermal expansion (CTE) of components and materials comprising a microelectronic package and differential heating and cooling rates. In a properly manufactured solder joint, the intermetallic compounds and interfaces are strained elastically (Fig. 26) and should not fail. Solder is intended to be the weakest link in the structure. The solder strain is primarily plastic with any elastic strain component quickly converted to additional plastic strain through relaxation processes. In the absence of an underfill (discussed in the next
TABLE 16
Electromigration Parameters for Tin and Lead
Parameter z* q (AV cm) DoB (cm2/sec) DHB (eV)
Sn solder
Pb solder
18 11.0 9.0 1.1
47 20.65 0.9 1.1
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section), the failure of flip chip solder joints is primarily due to the accumulation of plastic strain damage. Relaxation and recrystallization effects can occur in metals at temperatures exceeding 50% of the absolute melting temperature [122]. It should be noted that room temperature is 50% of the absolute melting point of lead and 60% of the absolute melting point of tin. Therefore these phenomena have a profound effect on the fracture behavior of both lead- and tinbased solders. 1. Grain Boundary Sliding and Dislocation Glide At elevated temperatures, the primary deformation mode in metals is grain boundary sliding (Fig. 5), while at less than 50% of the absolute melting temperature, the major deformation mode is due to dislocation glide. Both deformation modes operate simultaneously in solders because dislocation glide is required to assist grain boundary sliding to overcome obstacles such as grain boundary triple points and intermetallic particles on grain boundaries. This dynamic behavior is difficult to model. The solder undergoes plastic deformation due to stresses generated as temperature is increased. Grain boundary sliding occurs with cracks being initiated and growing at the grain boundaries with an attendant increase in surface (crack) area and energy. During the temperature dwell period, the elastic strain in the solder relaxes resulting in the generation of additional crack surface area and energy. As this occurs, the dislocation and point defect density and energy increase near grain-boundary sliding obstacles. 2. Recrystallization After some number of cycles, sufficient stored energy exists to induce recrystallization [123]. Because recrystallization occurs at crack initiation and growth locations, cracks can become embedded in grain interiors and do not propagate as the new grains nucleate and grow (Fig. 37). The crack area and energy associated with these trapped intragranular cracks do not contribute to solder joint failure because a continuous crack across the joint is required to cause electrical and mechanical failure. During cooling, the solder joint is strained in the opposite direction
FIG. 37 Effects of grain boundary geometry and obstacles on sliding behavior during hightemperature deformation. (a) Cracking at grain boundary triple points and intermetallic particles. (b) Recrystallization and isolation of grain boundary cracks.
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causing additional plastic strain at grain boundaries with concomitant cracking, followed by another period of stress relaxation and yet additional cracking. 3. Modeling Failure Rate Note that stress relaxation occurs twice during each thermal cycle, while recrystallization (which requires a minimum critical energy) may only occur after a number of cycles. This process is difficult to model because of the discontinuities introduced with crack growth and because not all cracks that are initiated contribute to the final failure. A failure rate prediction model should, however, reflect the aspects noted in Table 17.
C.
Plastic Strain Accommodation
It is important to note that a major role of solder in area array solder joints at the chip and package level is to accommodate plastic strain without cracking; that is, the solder is a plastic strain absorber. This implies that weak solders are potentially good candidates for this application. It has been demonstrated that solders with low shear strengths exhibit the greatest thermal cycling lifetimes [124], and this explains the lower thermal mechanical fatigue resistance of tin-based solders compared to lead-based solders (Table 5). 1. Crystal Structure Although tin melts at a lower temperature than lead, it exhibits greater strength due to its nonclose-packed crystal structure as compared to lead which is face-centered cubic (a closest packed system). Therefore tin is less capable of accommodating plastic strain during straining without cracking. Tin is also subject to additional strain due to CTE anisotropy effects which can increase the plastic strain per cycle due to thermal ratcheting discussed in Sec. III.C. An additional complication is added due to the allotropic crystal structure change from white-togray tin causing a complete discontinuity in deformation and cracking behavior which makes it extremely difficult to formulate an acceleration model. The usual failure criterion for a solder joint is a specified resistance increase due to crack growth across a joint. Because of the high resistivity of gray tin, the resistance increase criterion can occur with no cracking if the temperature is decreased below 13.2jC (55.6jF). 2. High Pb–Sn Solder High-lead solders usually fail due to intergranular cracking during thermal cycling [125]. The fracture surface exhibits long grain boundary sliding striations orientated parallel to the strain direction. Fatigue striations, which are perpendicular to the strain direction because they mark the location of the crack front after each strain cycle, are sometimes superimposed on the grain boundary sliding striations (Fig. 38) [126]. Fractographs of cycled high-lead solder joints also show cracking at grain boundary triple points and at intermetallic compound particles on grain boundaries. The fractographs typically exhibit subsurface cracks at these locations and a main crack which nucleates and grows from the geometrically induced stress concentrations at the solder joint edge. Fatigue cracks always nucleate at a free surface, while subsurface crack nucleation is classic creep behavior. The coexistence of two simultaneous failure mechanisms
TABLE 17
Effect of Cycling Parameters on Lifetime
Parameter
Effect on lifetime
Reason
Increasing plastic strain Increasing temperature
Decrease Decrease
Increasing cycling frequency
Increase
Crack growth rate increases Plastic strain and stress relaxation rate increase Insufficient time for stress relaxation to increase plastic strain
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FIG. 38 Features observed on fracture surfaces of solder joints due to thermal cycle induced crack growth. Grain boundary sliding striations form parallel to the strain direction. Fatigue striations form perpendicular to the strain direction.
contributes to the difficulty of formulating a failure model. The fracture behavior of eutectic Pb– Sn solder is different from high-lead solders due to microstructural differences. High-lead solder is primarily composed of lead grains and some eutectic material consisting of alternating lamella or plates of tin-rich then lead-rich phase which nucleate and grow from the lead grain boundaries by a process of discontinuous precipitation. 3. Eutectic Sn–Pb Solder The entire structure is composed of alternating Sn-rich and Pb-rich plates for the eutectic Sn–Pb solder. Each grain can contain a number of colonies of lamella oriented in different directions due to the number of equivalent crystallographic planes in FCC lead. This complex structure contains grain boundaries between grains, lamella colony boundaries within grains, and phase boundaries between lamella within colonies [127]. During cycling, the strain becomes concentrated along certain low strength, or low area, planes in a solder joint. Additional strain energy causes the lamella to coarsen at these locations, and the crack propagates in these coarsened areas. The lamella coarsens to reduce the surface area and energy. The solder is weaker at locations where the lamella is coarse because there are fewer lamellas at the grain boundaries to impede sliding and deformation which leads to failure. 4. Lead-Free Solders Because tin-based solders are used at higher absolute temperatures than the lead-based solders, it might be expected that the grain boundaries would be the weakest part of the structure and that failure would be intergranular. Figs. 39 and 40 are photographs depicting microsections of eutectic Sn–Ag–Cu solder subjected to thermal cycling conditions. Grain boundaries with triple points and intermetallic particles are visible in the photographs. Fig. 39 exhibits a crack propagating along a grain boundary which likely would result in intergranular failure, whereas the crack in Fig. 40 is propagating into the interior of a grain to cause transgranular cracking. How to integrate these two fracture modes in an already complex situation to define a failure prediction model is a difficult task.
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FIG. 39 Scanning electron microscope (SEM) photograph depicting intergranular cracking in eutectic Sn–Ag–Cu solder alloy subjected to thermal cycling. (Courtesy of IBM.)
D.
Failure Prediction Models
Several acceleration models that can be applied under a variety of situations are listed in Table 18. 1. Coffin–Manson Model Among the best known is the Coffin–Manson model [Eq. (9)] which states that the product of the number of cycles to failure and the plastic strain squared is a constant. The model only addresses plastic strain. According to the model, a metal, intermetallic compound, or interface which is
FIG. 40 Scanning electron microscope (SEM) photograph depicting intergranular and transgranular cracking in eutectic Sn–Ag–Cu alloy subjected to thermal cycling. (Courtesy of IBM.)
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subjected to cyclic elastic strain will not fail. The constant, K, is a material parameter which varies for different solders. This model does not account for the effects of time and temperature which are important considerations for materials stressed at temperatures above 50% of the absolute melting point. However, the relationship was modified to account for the effects [Eq. (10)] [128]. The frequency and temperature terms were taken from the early literature and do not necessarily apply to microelectronic applications. a. Temperature Term. The temperature term was determined using lead cable sheathing alloys in the form of 17-in.-long samples stressed isothermally in a rotating beam configuration at a rate of over 2 million cycles per day. An entire flip chip solder joint (C4 terminal) is smaller than the grain size in these samples, and a typical electronic product (e.g., desktop computer) only experiences a few cycles per day. The maximum temperature term in the model indicates that the lifetime should decrease by a factor of 1.8 as the maximum cycling temperature is increased from 85jC to 150jC. It has been determined for 95Pb–5Sn solder that there is virtually no reduction in resistance to thermomechanical fatigue over this temperature range because a phase transformation takes place at about 85jC for this composition. Below 85jC, the alloy consists of two phases: a lead-rich structure with a small amount of tin-rich lamella which nucleates heterogeneously at the lead grain boundaries. Above 85jC, all of the tin is in solid solution with the lead and there are no lamellas. This change in structure is critical to the cyclic lifetime of the alloy because grain boundary sliding is the principal deformation mode accompanied by an intergranular cracking fracture mode. The presence of the tin-rich lamella inhibits grain boundary sliding and thus promotes cracking. If an accelerated thermal cycle (ATC) test is
TABLE 18
Various Models Utilized to Predict the Thermal Cycle Lifetime of Solder Joints
Model Coffin–Manson relation
Modified Coffin–Manson relation
Approximation for Pb-based solder Approximation for Sn-based solder ‘‘Green’’ cycle modification to Miner’s law
Approximation for an underfill Underfill fracture mechanics-based model Underfill environmentally assisted model
Relationship/parameters
Equation
NðcÞ ¼ K where N=number cycles to fail; c=plastic strain; and K=constant N ¼ Cð f Þ1=3 ðcÞ2 ðTmax functionÞ where f=cycling frequency; Tmax=max cycle temperature; and C=constant N ¼ 2000ðcÞ2 where c=plastic strain in % N ¼ 700ðcÞ2 where c=plastic strain in % K ¼ Nm ðcm Þ2 þ Ng ðcg Þ2 where Nm=number of main cycles; cm=main cycle plastic strain; Ng=number of green cycles; and cg=green cycle plastic strain N ¼ B½2000ðcÞ2 where B=underfill improvement factor N ¼ DðDKÞm where DK=range of stress intensity and D=constant N ¼ E Pr expðDH=kTÞ where P=pressure; DH=activation energy; E=constant; r=pressure exponent; and kT=thermal energy
9
2
10
11 12 13
14 15
16
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conducted utilizing a temperature cycle range from 25jC to 85jC, the lamellas are always present. If, however, a range from 25jC to 150jC is utilized, the tin-rich lamellas are not present for about one-half of the temperature cycle and the lifetime increases due to the relative ease of grain boundary sliding to accommodate the strain without cracking. The transformation temperature for the transition from a two-phase to single-phase alloy is a function of composition and decreases to about 50jC for 97Pb–3Sn solder. This is believed to be a key factor for the enhanced thermomechanical fatigue life exhibited by a 97Pb–3Sn alloy compound to a 95Pb–5Sn alloy. b. Frequency Term. The lifetime of area array solder joints decreases as cycling frequency to the one-third power [Eq. (10)]. This term accounts for the decrease in lifetime that occurs due to stress relaxation which converts elastic strain to plastic strain. The driving force for relaxation is the residual stress within the solder which decreases to low values in approximately 15 min at room temperature. In practice, it is assumed that the lifetime decreases according to the one-third power relationship down to 6 cycles per day for Pb–Sn solders and then becomes constant because the driving force disappears. This relation may be accurate for frequencies greater than 3 cycles per hour, but does not apply to lower frequencies that are of interest for microelectronic applications. During accelerated testing, the thermal inertia of the samples often limits the maximum cycling frequency to about 3 cycles per hour. It has been demonstrated [129] that the lifetime of area array solder joints decreases linearly with thermal cycle frequency from 3 to 1.5 cycles per hour and then becomes constant at lower frequencies. The decrease in cyclic lifetime calculated as the frequency is reduced from 3 cycles per hour to 1 cycle per day is coincidentally the same for both frequency models (Path A–C and A–B–C in Fig. 41). The use of the correct model, however, has important implications. A linear relation implies that the same cycling time is required to reach failure at 1.5 cycles per hour (36 cycles per day) as is required at 3 cycles per hour (72 cycles per day) because the lifetime is reduced by one-half at the lower frequency. This is advantageous because it is easier to operate a temperature cycling chamber at a lower cycling frequency and because lifetime is not a function of frequency below 1.5 cycles per hour and this effect can be eliminated from the model. It should be noted that Eq. (10) is usually used to determine the ratio of the lifetimes at accelerated testing conditions to the lifetime at product application conditions. This means that the constant, C, in the equation is not determined, as discussed later. c. Effect of Tin-Based Solders. The discussion above is in relation to high-lead solders. A material change to high-tin solder requires changes to the model. Complications arise due to the anisotropic properties of tin which result in the generation of internal stresses and strains not
FIG. 41 Graphical representation depicting the variation of thermal cycling lifetime (N) with cycling frequency. Above 72 cycles per day (cpd), the lifetime varies as f 1/3. Between 72 and 36 cpd, the lifetime varies as f 1. Below 36 cpd, the lifetime is not effected by cycling frequency.
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caused by CTE mismatches in a package. The model would become even more complex if the allotropic transformation from white-to-gray tin occurred during cycling. Some or all of the tin in a joint can transform during every thermal cycle resulting in a 21% volume change, which can lead to catastrophic failure. This reaction must be eliminated (e.g., by Bi additions or other means) because it introduces high reliability risk and it is very difficult to model this situation. Tin-based solders exhibit the same general response to temperature and frequency as the high-lead solders. Increasing the maximum cycling temperature results in a decreased lifetime because the strain is greater due to increased stress relaxation. Increased cycling frequency results in an increased cyclic lifetime because there is less time for stress relaxation and concomitant increase in plastic strain. However, the model parameters must be appropriately adjusted to account for tin’s material characteristics. Eq. (12) (Table 18) shows an approximation of the modified Coffin–Manson relation. The approximation can be made because the temperature and frequency terms in Eq. (10) are cancelled when the ratio between laboratory test and product application conditions is determined. During accelerated testing, several parameters are typically increased relative to actual application conditions; among them are the temperature change, maximum cycling temperature, and cycling frequency. Increasing temperature tends to decreased lifetime and increasing frequency tends to increased lifetime. The result is that the plastic strain is the most important factor in determining lifetime. 2. Other Models The model described by Eq. (11) is a conservative estimate of lifetime for many lead-based solders stressed under a variety of conditions. An approximate model for tin-based solders [Eq. (12)] assumes that lifetime varies with plastic strain squared and reflects the lower cyclic lifetime of tin solders compared to lead solders [130]. To conserve energy, many electrical components power down to a standby state when not in use which is sometimes referred to as ‘‘sleep mode.’’ For computers, it means that these additional ‘‘green’’ cycles must be superimposed on the main temperature cycle caused by machine on/off conditions. As an example, the main temperature cycle is typically in the range 25jC to 100jC with an on–off frequency of 1 cycle per day. Green cycles only occur during the high-temperature portion of a main cycle and could result in a temperature decrease of, say, 30jC which could occur every 15 min. Eq. (13) is a form of Miner’s law that can be used to model this complicated cycling schedule. Note that the constant, K, in Eq. (13) is the same as in Eq. (9).
E.
Effects of Underfill
1. Properties and Role Underfill material is typically an epoxy filled with silica particles [131]. The role of the silica particles is to increase the modulus of elasticity of the composite material (Fig. 26). The coefficient of thermal expansion (CTE) of underfills is adjusted to equal the solder. For high-lead solder, the CTE is approximately 29.3 ppm/jC and 23.0 ppm/jC for polycrystalline white tin. An underfill is dispensed adjacent to a mounted flip chip where it then fills the space between the chip and chip carriers by capillary action and is then cured. The purpose of the underfill is to mechanically couple a chip and chip carrier to eliminate relative movement between them that causes shear strains in the flip chip solder joints (C4 terminals). Because silicon chips exhibit the lowest CTE in a package (approximately 3.0 ppm/jC), an underfill must stretch a chip so the expansion is the same as the chip carrier. Some organic chip carrier materials, such as FR-4, have CTE values in the range of 14–21 ppm/jC which results in high strain in the chip solder joints. The CTE and modulus of elasticity of underfills are typically maximized so that a high stress can be exerted on the chip. Underfills are formulated so their CTEs do not exceed the solder CTE because the solder is subjected to tensile stresses which cause failure by cavity formation. Underfill epoxies are highly cross-linked after curing so there is no stress relaxation in an underfill, which is a critical factor. Stress relaxation in an underfill would result in both an increased strain in an underfill and flip chip solder joint. It should be pointed out, however, that an underfill can only exert force on a
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chip and chip carrier if there is adequate adhesion of the underfill to the chip, chip carrier, and C4 terminals. The surfaces must be clean before underfill is dispensed. 2. Failure Mode The failure mechanisms which occur due to thermal cycling differ for underfilled parts compared to those with no underfill. In the absence of an underfill, area array solder joints fail due to solder fracture during thermal cycling. With an underfill, solder fracture is suppressed and other parts of the structure fail. These failure modes include chip fracture and delamination of the underfill from a chip, chip carrier, and solder joints. When the underfill adhesion fails, the solder joints locally are subjected to very high strain levels and quickly fracture. 3. Failure Prediction Model Any failure model for area array solder joints including C4 terminals with underfill should be based on underfill interfacial integrity and not solder fracture. Note also that all stresses and strains in an underfill and at the interfaces are elastic and that no stress relaxation occurs. The modified Coffin–Manson relation applies only to the accumulation of plastic strain damage and therefore does not apply to underfill fails. Also, note that the absence of stress relaxation in underfill materials implies that there is no need for a frequency term in a failure model because lifetime is not a function of time. The form of the underfill model is not well understood. The model given by Eq. (14) (Table 18) is occasionally employed, although the form is clearly incorrect expressed as the Coffin–Manson lifetime times an underfill improvement factor. This improvement factor, B, can be as high as 500 [132] for identical parts cycled to failure compared to parts without underfill. Lifetime predictions made using this model will almost certainly be incorrect because this relation does not reflect the actual failure mechanism which is elastic, impurity-assisted interfacial fracture. The model given by Eq. (15) is based on fracture mechanics and expresses the cyclic lifetime as a function of the range of the stress intensity factor raised to some power. This model should be better suited for an underfill interfacial, decohesion fracture mechanism. The stress intensity factor includes the interfacial stress and length of cracks or defects and is applicable to elastic stress conditions. A model has also been generated [Eq. (16)] that is useful for situations where the crack growth is assisted by impurities and humidity. 4. Alloys with Underfill-like Properties The 80Au–20Sn eutectic (Table 5) is an attractive lead-free alloy because the melting point (278jC) is between those of the high-lead solders and eutectic Sn–Pb to provide a melting temperature hierarchy during assembly. The mechanical properties of the Au–Sn eutectic solder (Table 5, Fig. 26) differ significantly from other lead-free alloys; for example, Au–Sn eutectic exhibits a much greater strength and lower ductility. The properties of this alloy are similar to intermetallic compounds because it is a mixture of two intermetallic compounds. The equilibrium binary phase diagram indicates that up to 109jC, the structure is composed of a mixture of 64 wt.% Au5Sn and 36 wt.% AuSn. The Au5Sn phase has an orthorhombic crystal structure and melts at 490jC, whereas AuSn exists as a hexagonal crystal structure and melts at 420jC. Room temperature is only about 40% of the absolute melting temperature of these compounds, so it is not surprising that the alloy exhibits limited ductility. As a general rule, intermetallic compounds are ductile above approximately 60% of their absolute melting temperatures [133]. In the absence of underfill, this alloy does not perform well as a flip chip solder joint because it does not have the capacity to absorb plastic strain without cracking. In this regard, 80Au–20Sn alloy acts like an underfill because it deforms elastically, exerting a stress on the chip and chip carrier. The total area of all flip chip solder joints combined is usually only a few percent of the total chip area. The Au–Sn alloy is unable to stretch a chip to match the chip carrier expansion during heating causing the alloy to fracture because it must absorb the expansion mismatch. However, in the presence of an underfill, the Au–Sn eutectic alloy helps to stretch the chip because, as pointed out, it behaves much like an underfill. Also, like an underfill, the eutectic Au–Sn does not relax during temperature dwell periods so strain is not transferred to the solder. Table 19 lists the creep strain rate for several solders at 100jC and 1450 psi. The stress relaxation in eutectic Au–Sn is noted to be 9 orders of magnitude less compared to other lead-bearing and lead-free alloys. The high
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reactivity of Au with many chip and chip carrier metallizations, including Cu and Ni, could limit the use of eutectic Au–Sn. Au can substitute for Cu or Ni to form a number of ternary intermetallic compounds, e.g., Cu5AuSn5, Cu2Au2Sn, and others. These compounds form during solder reflow operations and during solid-state, high-temperature storage conditions. As various compound layers grow thicker, the stress-thickness product, or force, increases at their interface which can cause fracture to occur [134].
F.
Testing
The testing that must be performed in order to assure the reliability of solder joints in a microelectronic assembly is extensive because of the large number of possible failure mechanisms that must be addressed. Most tests are the same for both lead-containing and lead-free solders. Among the tests conducted most frequently and relied upon most heavily are high-temperature storage, temperature and humidity, temperature and humidity with bias, mechanical shock and vibration, and hostile environment exposure. This section discusses those tests specific to high-tin solders. 1. Pull Test The pull test was discussed previously as critical to understanding the interfacial strength and the failure mode of flip chip solder joints. As noted, pull testing typical lead-based terminals results in ductile solder fractures. Pull testing tin-based solder joints is more complicated because tin exhibits greater strength and lower ductility than lead (Fig. 26). A correctly manufactured tinbased solder joint can fail at locations other than the bulk solder, e.g., at an interface, or in the metallization and insulation on a chip and chip carrier if the pull test parameters utilized are the same as for lead-based joints. a. Strain Rate Modification. The pull test can be modified for tin solders by decreasing the strain rate. The ultimate tensile strength of solders is lower at lower strain rates. As noted earlier, interfaces and intermetallic compounds in a solder joint deform elastically so are not affected by changes in strain rate. Although tin-based solder joints can be made to repeatably fail in the solder at low strain rates, the rate is too slow (1.0 104 in./in./sec) for practical purposes requiring many hours to complete a single test. b. Increased Temperature Option. Another option is to increase the joint solder temperature which weakens the solder and shortens the test time. However, a temperature increase can also affect interfacial and intermetallic compound strength. In order to prevent the introduction of new failure modes, only modest temperature increases should be employed. 2. Effects of Anisotropy on Thermal Cycle Testing Unlike lead, tin exhibits anisotropy, e.g., coefficient of thermal expansion that varies by a factor of 2 in different crystallographic directions. As discussed in Sec. III.C, this condition can lead to large internal stresses and thermal ratcheting in tin alloys that does not occur in lead-based solders. These effects are anticipated during normal thermal and power cycling tests with no
TABLE 19
Parameters and Creep Strain Rate for Several Solder Alloys at 100jC and 1450 psi
Solder alloy 5Sn–95Pb 63Sn–37Pb 96.5Sn–3.5Ag 97Sn–3Cu 20Sn–80Au a
Frequency constant C
Activation energy DH (eV)
Stress exponent n
Relaxation (creep) strain ratea dc/dt (sec1)
1.94 0.21 2 104 9 104 2 105
1.03 0.49 0.70 0.51 0.82
11.03 5.29 8.67 7.00 2.55
2.0 103 7.2 103 3.1 105 9.7 104 5.2 1014
dg/dt = Cexp(DH/kT)H n
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modifications of the test parameters required. Note, however, that the tin anisotropy has an effect on solder joint lifetime and the acceleration model. a. Tin Pest Transformation. The allotropic tin pest transformation that can occur in tin and tin-based alloys at temperatures below 13.2jC (55.6jF) is very difficult to characterize because it is nucleation-controlled and affected by many factors such as stress, small impurity additions, surface conditions, and temperature. During temperature or power cycling, it may not be apparent from a visual examination that tin pest is occurring because other mechanisms can cause cracking during thermal cycling. The presence of cracks is not an unambiguous indication of the pest reaction. Quite obvious is a severe case in which the complete solder joint is reduced to powder. A more direct way to determine the presence of tin pest is to monitor the electrical resistance because the resistivity of gray tin is about 25 times greater than white tin (Table 4). At a
FIG. 42 Graphical depiction of the variation of strain with time for different parts of a microelectronic package. (a) Strain changes during power cycling in which the chip is the source of heat. (b) Strain variation during temperature cycling in which a thermal cycling chamber or ambient is the source of the heat.
DEGRADATION PHENOMENA
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constant temperature, increased electrical resistance can only be due to cracks created due to the tin pest reaction and/or the increased resistivity of the gray tin. 3. Power Cycling Test Temperature cycling, in which parts are placed in a chamber that is cycled between two temperatures, is a basic and important test routinely performed on microelectronic assemblies. The test, however, can only approximate the thermal–mechanical behavior of a product because the chamber, not the chip, is the source of the heat. The test cycling frequency is limited by the thermal inertia of the test parts and capability of the thermal cycle chamber. Under application conditions, chips are the source of heat so are typically the hottest part of a package, but their heating and cooling rates are faster than other parts of a package. This can lead to subtle strain effects during each power cycle. Power cycling can duplicate these effects in a manner that closely approximates the application conditions (Fig. 42) [135]. This figure shows the variation of strain in the C4/underfill and the substrate/lid of a package as a function of time during power cycling and temperature cycling. The difference in behavior is due to the different heat sources and temperature gradients resulting from the power cycling and thermal cycling tests. Power cycling requires a test chip with heating capability and temperature-sensing devices joined to a product chip carrier or assembly. Typically, high current is supplied to resisters embedded in a test chip causing the test package to mimic the operation of a product chip. During testing, the test chips heat and cool before the other parts of a package, creating product-like temperature gradients across the package. Accordingly, choosing the proper test conditions of temperature, current, and cycling frequency results in product-like behavior resulting in simpler acceleration models because many variables are eliminated. Power cycling also makes it relatively easy to superimpose green cycles on the high-temperature portion of main cycles. Cycle frequency can be greater with power cycling as compared to thermal cycling because each package is heated and cooled individually. This can be an important consideration in packages with underfill because they are not sensitive to cycling frequency.
VIII. A.
SUMMARY Crystal Structure and Anisotropy Effects
The drive to reduce or eliminate lead from microelectronic assemblies has led the industry to use tin and tin-based solders which exhibit anomalous characteristics and behavior. Tin-based solders exhibit this behavior because it exists in two forms with a transformation temperature of 13.2jC (55.6jF). Above this temperature, it exists as white tin, a metal with a body-centered tetragonal crystal structure whose properties vary along different crystallographic directions (i.e., exhibits anisotropy). It exists as gray tin below the transformation temperature and is a semiconductor with a diamond cubic crystal structure. The transformation of white tin-to-gray tin at 13.2jC is called tin pest and results in a 21% volume change that can cause the material to disintegrate into powder. The transformation is nucleation- and growth-controlled and can be eliminated with small additions of bismuth or antimony. The coefficient of thermal expansion is among the anisotropic properties exhibited by the body-centered tetragonal crystal structure of white tin. During thermal cycling, thermal ratcheting can occur due to this condition that can cause significant distortion in solder joints.
B.
Soft Errors from Lead-Free Solders
Lead-free solders can contain sufficient quantities of lead to cause soft errors. Purification of leadfree solders should not be as difficult as lead-containing solders because isotope separation is not required. However, even minute quantities of lead adjacent to active chip areas can cause problems due to the dramatic enrichment of Pb210 in certain ores.
974 C.
SULLIVAN AND KILPATRICK Degraded Interfaces
All solder joints contain numerous interfaces between terminal metallization, intermetallic compounds, and solder. Properly manufactured high Pb–Sn flip chip solder joints should always fail in the solder in both pull and during accelerated thermal cycle tests. However, whether the joints consist of lead-bearing or lead-free solder reactions at interfaces can cause effects such as impurity snowplowing, Kirkendall voids, and excessive intermetallic compound growth resulting in increased stress levels which can lead to premature failure at terminal pads.
D.
Task of Lead-Free Solder Candidates
Microelectronic solder joints are subjected to a number of failure mechanisms such as thermal cycle cracking, electromigration, thermomigration, corrosion, etc. Any new solder alloy must satisfy all of these requirements simultaneously. Power cycle testing stresses an assembly in a manner that closely replicates actual application use conditions.
REFERENCES 1. Kester Solder Lead Free Update, Kester Division of Litton Systems, Inc., web site: http://www.kester.com/leadfree/leadfree_update.htm. 2. National Center for Manufacturing Sciences Lead-Free Solder Project, Special Supplement to Surface Mount Technology, June 2000. NCMS Report 0401RE96, Lead-Free Solder Project, National Center for Manufacturing Sciences, Ann Arbor, MI, August 1997. CD-ROM, June 1998. 3. Handwerker, C.A.; Noctor, D.; Whitten, G. Current assessment of the reliability of lead-free solders. Proc. of SMTA Symposium on Lead Free Interconnect Technology; Boston, MA, June 2000; 98–103. 4. Kang, S.K.; Sarkhel, A.K. Lead (Pb)-Free Solders for Electronic Packaging. J. Electron. Mater. 1994, 23 (8), 701–707. 5. Kang, S.K.; Horkans, J.; Andricacos, P.; Carruthers, R.; Cotte, J., et al. Pb-free solder alloys for flip chip applications. Proc. 49th Electronic Comp. and Technol. Conf.; San Diego, CA, June 1999; 283– 288. 6. Seelig, K.; Suraski, D. The status of lead-free solder alloys. 50th Electronic Comp. and Technol. Conf.; Las Vegas, NV, June 2000; 1405–1049. 7. NEMI Press Release, NEMI Group Recommends Tin/Silver/Copper Alloy as Industry Standard for Lead-Free Solder Reflow in Board Assemblies, Jan. 24, 2000, web site:
DEGRADATION PHENOMENA 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61.
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Sattiraju, S.V.; Dang, B.; Johnson, R.W.; Li, Y.; Smith, S.; Bozack, M.J. Wetting characteristics of Pb-free solder pastes and Pb-free PWB finishes. Proc. 51st Electronic Comp. and Technol. Conf.; Orlando, FL, June 2001; 1338–1344. IPC roadmap: A guide for assembly of lead-free electronics. Draft IV, IPC Association; June 2000; web site:
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62.
Cahn, R.W. Recovery and recrystallization. In Physical Metallurgy; Cahn, R.W., Ed.; NorthHolland Pub.: Amsterdam, 1970; 19 pp. Avrami, M. Kinetics of phase change. I. J. Chem. Phys. 1939, 7, 1103–1112. Jeannotte, D.A.; Goldmann, L.S.; Howard, R.W. Package reliability. In Microelectronics Packaging Handbook; Tummala, R.R. Rymaszwski, E.J., Eds.; Van Nostrand Reinhold: New York, 1989; Chapter 5. Miller, H.S. Flip chip packaging. Chip Scale Rev. July 2001, 5, 32–41. May, T.C.; Woods, M.H. Alpha-particle-induced soft errors in dynamic memories. IEEE Trans. Electron Devices 1979, ED-26 (1), 2–9. Baumann, R. Silicon amnesia: a tutorial on radiation induced soft errors. 39th Annual Intl. Reliability Physics Symp.; Orlando, FL, April 2001. Baumann, R.C.; Smith, E.B. Neutron-induced boron fission as a major source of soft errors in deep submicron SRAM devices. Proc. 38th Annual Intl. Reliability Physics Symp.; San Jose, CA, April 2000; 152–157. Weiser, M.W. Alpha particle issues in microelectronics. TMS Annual Meeting; New Orleans, LA, February 2001. Dai, C.; Hakim, N.; Hareland, S.; Maiz, J.; Lee, S.-W. Alpha-SER modeling and simulation for sub0.25Am CMOS technology. 1999 Symp. on VLSI, Technol. Digest of Tech. Papers; Taipei, Taiwan, 1999; 81–82. Low Alpha Particle Alloys, Kulicke & Soffa, Flip Chip Division, website:
63. 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. 80. 81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93.
DEGRADATION PHENOMENA 94. 95. 96. 97. 98. 99. 100. 101. 102. 103. 104. 105. 106. 107. 108. 109. 110. 111. 112. 113. 114. 115. 116. 117. 118. 119. 120. 121. 122. 123. 124. 125. 126. 127. 128.
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Rinne, G. Nuclear Particles and the Green Movement: Low Alpha and Lead-Free Solders, Unitive, Inc., website:
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Howard, R.T. Optimization of indium–lead alloys for controlled collapse chip connection applications. IBM J. Res. Develop. May 1982, 26 (3), 372–389. 130. Manson, S.S. Thermal Stress and Low-Cycle Fatigue; McGraw-Hill: New York, 1966; 257 pp. 131. Nakano, F.; Soga, T.; Amagi, S. Resin-insertion effect on thermal cycle resistivity of flip chip mounted LSI devices. Proc. Intl. Soc. Hybrid Microelectronics (ISHM); 1987; 536–541. 132. Doi, K.; Hirano, N.; Okada, T.; Hiruta, Y.; Sudo, T.; Mukia, M. Prediction of thermal fatigue life for encapsulated flip chip interconnection. Int. J. Microcircuits Electron. Packag. 1996, 19 (3), 231–236. 133. Lawley, A. Mechanical properties—Plastic behavior. In Intermetallic Compounds; Westbrook, J.H., Ed.; R.E. Krieger: Huntington, NY, 1977; Chapter 24. 134. Mei, Z.; Callery, P.; Fisher, D.; Hua, F.; Glazer, J. Interfacial fracture mechanism of BGA packages on electroless Ni/Au. Adv. Electr. Packaging 1997, 2, 1543–1550. 135. Reiley, T.C.; Shih, D.-Y. Package-to-board interconnections. In Microelectronics Packaging Handbook; Tummala, R.R., Rymaszewski, E.J., Eds.; Van Nostrand: New York, 1989; 805–814. Chapter 11.
INDEX
[Adhesives, electrically conductive] reliability, 762–763 solid metal particles, 731 anisotropically conductive adhesives flip chip for bumped dies coated plastic filler, 733 nickel filler, 734–735 solder filler systems, 733–734 two filler systems, 732–733 anisotropically conductive adhesives flip chip for CSP, BGA applications, doublelayered ACF film, 740 anisotropically conductive adhesives for unbumped flip chips conductive columns, 737–739 gold-coated nickel filler, 737 nickel/gold-coated silver filler, 737 anisotropically conductive adhesivesbumped flip chips glass chip carriers, 735–736 high-frequency applications, 736 MAPLE method, 735–735 selective tacky adhesive method, 735 electrical conductivity, isotropically conductive adhesives, 753–755 contact resistance stability, 755–758 corrosion inhibitors, 756–757 increase shrinkage, 755 lubrication layer, 753–754 moisture absorption, 756 oxygen scavengers, 757 prevention, 756–758
AAS. See Atomic Absorption Spectroscopy Abortion, spontaneous, effect of lead, 51 Accelerated thermal cycle, 549, 685, 737, 808, 915, 967 Accumulation, nonwettable material, degradation, 957 ACGIH. See American Conference of Governmental Industrial Hygienists Acid number, 389 Acid-base reactions, 404–405 Acidity, 399–401 Activators, 379 Active species, 379 ADEME, 132 Adhesives, electrically conductive, 729–768 ACA flip chip for CSP, BGA applications ceramic chip carriers vs. organic chip carriers, 741 gold stud vs. electroless nickel/gold bumps, 741 anisotropically conductive adhesives, 762–763 adhesive matrix, 731 categories, 730 conductive fillers, 731–732 description of, 729–732 high-frequency compatibility, 762 materials development, 762 metal particles with insulating coating, 732 nonmetal particles with metal coating, 731–732
979
980 [Adhesives, electrically conductive] resistance increase, 755–756 sharp-edge filler particles, 757–758 transient liquid-phase fillers, 755 failure mechanism loss of compressive force, 742 oxidation of nonnoble metals, 742 flip-chip applications, 732–742 anisotropically conductive adhesives flip chip for bumped dies, 732–735 anisotropically conductive adhesives flip chip for CSP, BGA applications, 739–741 anisotropically conductive adhesives for unbumped flip chips, 736–739 failure mechanism, 742 SMT applications, 741 using isotropic conductive adhesives, 746–751 future challenges, 762–763 impact performance, 758–759 epoxide-terminated polyurethane systems, 759 isotropically conductive adhesives, 763 adhesive matrix, 743–745 conductive fillers, 745–746 description, 742–746 electrical characteristics, 763 high-frequency performance, 763 latency, rapid curing, 744 low Tg materials, effect of, 744 low-melt fillers, 745–746 manufacturability, yields, 763 matrix materials, 743 moisture absorption, effect of, 744–745 particle shape, size, 745 percolation theory of conduction, 742–743 pure silver vs. silver-coated fillers, 745 reliability, 763 silver-copper fillers, 745 microelectronics packaging, 751–753 advantages, 752 CSP applications, 752 disadvantages, 752 fatigue life of isotropically conductive adhesives joints, 753 high-frequency performance of isotropically conductive adhesives joints, 752–753 surface mount applications, 751–752 nonconductive adhesives, 759–762 3-D CSP application, 761 applications, 760–762 flip-chip applications, 760–761
INDEX [Adhesives, electrically conductive] micron bump technology, 759–760 NCAs vs. anisotropically conductive adhesives in flex circuits, 760 print heads, 760 smart labels, 761–762 SMT applications, 760 using isotropic conductive adhesives advantages, 746 comparison with soldered joints, 749–750 curing, 747–749 isotropically conductive adhesives process for unbumped chips, 750–751 metal-bumped flip-chip joints, 749–750 print isotropically conductive adhesives, 747 process, 746–749 protective chip pad layer, 746–747 underfill, 749 Adhesives alternative, conductive, 24–26 advantages, 25 categories, 24–25 disadvantages, 26 Adsorption, effects of, 334–335 Aerospace industry, lead-free solders utilization in, 27 Aging, tin-silver solders, 243–233 high temperature stability, 244 interface intermetallic compounds, 244 temperature effect, 243 Alcohol amines, 399 Allotropic changes, within metallic system, 918–919 Allotropic modification, solders, 213 Allotropic transformation, tin pest, 930–931 Alloy selection, lead-free component conversion, 592 Alloys. See also under specific alloys viscosity of, 359–360 Alloys with underfill-like properties, degradation, 970–971 Alpha emitters, lead solders, 943–947 Alpha particles, soft errors, degradation, 940–943 American Conference of Governmental Industrial Hygienists, 72 Amines, 396–398 Amino acids, 398–399 Ammunition, lead usage, 2 Anisotropic conductive film, 734 Anisotropically conductive adhesives, 729, 762–763 adhesive matrix, 731 categories, 730
INDEX [Anisotropically conductive adhesives] conductive fillers, 731–732 metal particles with insulating coating, 732 nonmetal particles with metal coating, 731–732 solid metal particles, 731 description of, 729–732 flip-chip applications, 732–742 anisotropically conductive adhesives flip chip for bumped dies, 732–735 anisotropically conductive adhesives flip chip for CSP, BGA applications, 739–741 anisotropically conductive adhesives for unbumped flip chips, 736–739 ceramic chip carriers vs. organic chip carriers, 741 coated plastic filler, 733 conductive columns, 737–739 double-layered ACF film, 740 failure mechanism, 742 glass chip carriers, 735–736 gold stud vs. electroless nickel/gold bumps, 741 gold-coated nickel filler, 737 high-frequency applications, 736 loss of compressive force, 742 MAPLE method, 735–735 nickel filler, 734–735 nickel/gold-coated silver filler, 737 oxidation of nonnoble metals, 742 selective tacky adhesive method, 735 SMT applications, 741 solder filler systems, 733–734 two filler systems, 732–733 high-frequency compatibility, 762 materials development, 762 reliability, 762–763 Anisotropy, 925–929 degradation phenomena, 925–929, 973 elasticity-based mechanical properties, 925–926 physical properties, 925 plasticity, 926–929 effects on thermal cycle testing, 971–973 elasticity-based mechanical properties, 925–926 physical properties, 925 plasticity, thermal ratcheting, 926–929 Antimony in electronic assemblies, 97 health issues, 71 indium, 72
981 [Antimony] ingestion, 71 regulation, 72 toxicity in humans, 72 occupational exposure to, 3 regulation of, 57 world reserves of, 13 Application-specific integrated circuits, 937 Area bonding conductive, 739 Asia Pacific, initiatives in, 7–8 Assembly related aspects on reliability, effect of, 802–807 Association of Connecting Electronics Industries, standards, 6 ATC. See Accelerated thermal cycle Atmospheres, inert, 569–590. See also Inert atmospheres Atomic Absorption Spectroscopy, 76 Atomic level, solders, 212 Automatic optical inspection, 604 Automotive industry, lead-free solders utilization in, 27 Back-end-of-line, 939 Ball grid array, 431, 440, 476, 496, 497, 729, 915, 936 BGA. See Ball grid array Billets, lead usage, 2 Bismuth in electronic assemblies, 97–98 health issues, 69–70 human exposure, 69 regulation, 70 occupational exposure to, 3 regulation of, 57 world reserves of, 13 Bismuth-tin solders, 282–288 applications, 285–287 assembly, 285–287 other attachments, 287 as-cast microstructure, 282–283 fatigue, 284–285 interfacial compound formation, 283 mechanical properties, 283–284 utilization, 287–288 wetting characteristics, 283 Blood effect of lead on, 51 lead effects on, 52 Board level reliability, 807–814 aging, effect on several types of lead-free PBGA joints, 809–812 CBGA components with lead-free interconnetions, 807–808
982 [Board level reliability] effect of bismuth, copper on quad flat pack, 812 metallurgical interactions, 813–814 mixed composition systems, 812–813 passives attached with lead-free solder, 812 PBGA, mounted with tin-silver-copper solder, 808–809 process parameters, 813–814 Board material, lead-free component conversion, 592–593 Board surface finishes, inert atmosphere, 573–574 Body centered tetragonal, 834, 841 Bond number, 347–348 Bone, effect of lead on, 51 Bone integrity, 53 Boro-phosphoro-silicate glass, 939 Bottom residue, municipal solid waste combustors, 105 Brain cellular morphology, effect of lead, 51 Brain edema, effect of lead, 51 BRITE/EURAM, 695 Build-up technology, printed circuit boards utilizing, 556–567 laser processes, 560–567 mass generation processes, 559–560 mechanically drilled microvias, 560 miniaturization issues, 557–558 overview, 556–557 photolithographically defined vias, 558–559 solid post construction, 560 Cable covering, lead usage, 2 Cadmium contamination in crops, 58 health issues, 73 Calcium use, cardiac, effect of lead, 51 Carbon fiber reinforcements, 311 Carboxylic acid fluxes, 390–396 Cardiovascular system, 52–53 calcium use, effect of lead, 51 effect of lead on, 51 electrical function, effect of lead, 51 sodium metabolism, effect of lead, 51 Casting metals, lead usage, 2 Cathode ray tube, 65, 84, 108, 115, 140 Cation exchange capacity, 59, 62 CDC. See Center for Disease Control Center for Disease Control, 67, 104 Central nervous system, effect of lead, 51–52 Central processing unit, 107 Ceramic chip scale package, 752 Ceramic dual in-line package, 683
INDEX Ceramic multilayer capacitors, 700 Ceramic pin grid array, 683 Ceramic products, oxides used for, lead usage, 2 Ceramic substrate materials, lead-tin soldering, 195–196 Charge-coupled device, 869 Chemical glass, 509 Chemically heterogeneous surface, contact angle for, 372 Chemicals, oxides used for, lead usage, 2 Chip scale package, 294, 431, 496, 497, 605, 729 Chlorofluorocarbon, 6 Circuit boards, printed, 507–520 lead-free finishes, 431–464 electroless plating, 432–433 electrolytic plating, 432 immersion plating, 433 issues with, 461–462 lead-free board finish criteria, 435 lead-free component finishes, 449–454 lead-free component finishes tin, pure, 454 lead-free printed circuit board finishes, 434–449 manufacturability, 456–458 nickel-palladium, 453–454, 457–458 printed circuit board finishes, 435–449 reliability, 458–462 solderability, 454–456 tin, pure, 456 tin whisker phenomenon, 458–461 tin-bismuth, 453, 456 tin-copper, 457 tin-silver, 456–457 tin-copper, 453 tin-zinc, 457 types of finishes, 432–434 pad design, 514–520 pad finishes, 509–514 process temperatures, effect of, 508–509 reinforcement materials, 509 utilizing build-up technology, 556–567 Coefficient of thermal expansion, 214, 233, 240, 241, 303, 310, 440, 496, 509, 683, 698, 731, 923, 962, 969 Coffin-Manson model degradation, 966–969 degradation phenomena, 966–969 lead-tin soldering, 202–203 Cognitive intelligence, effect of lead, 51 Collection schemes, burden, 106–107 Collection/take back programs, 106–109
INDEX Committee on Toxicology, Ectoxicology and Environment, 125 Component material, lead-free component conversion, 593 Component spacing limits, 606 Component termination finish, 805–806 lead finish/mold compound adhesion, 805 nickel/palladium-based finishes, 805 other finishes, 806 Comprehensive surface mount reliability, 203 Computational modeling, lead-tin soldering, 203–205 constitutive models, 203–204 damage models, 204–205 Conductive adhesives alternative, 24–26 advantages, 25 categories, 24–25 disadvantages, 26 Conductive anodic filament failure, 102 Constitutive models, lead-tin soldering, 203–204 Contact angle, 422 Contaminated water, 3, 59–63 Controlled atmospheres, lead-tin soldering, 192 Cooperative Administrated by Science and Technical Research, 161 Copper concentration in solder, effect of, 547–548 contamination in crops, 58 dissolution, tin-silver solders, effect of, 242 dust, occupational exposure to, 3 in electronic assemblies, 96–97 fume, occupational exposure to, 3 health issues, 70 direct contact, 70 ingestion, 70 inhalation, 70 interfaces, 418–419 mirror test, 523–524 with organic solderability preservative, 700 regulation of, 57 world reserves of, 13 Copper-nickel-tin ternary system, intermediate phases, 483 Copper-tin intermetallic phases in tin-silvercopper alloys, 481–482 Corrosion resistance, lead-tin soldering, 205–206 Cosmic rays, soft errors, degradation, 937–939 COST. See Cooperative Administrated by Science and Technical Research
983 Cost, element replacements for lead, electronic assemblies, 14 Counter ions in organic vs. inorganic fluxes, 382 Cracked oxide theory, 896, 901, 910 Creep, 214–219 degradation, 961 diffusional creep mechanism, 216–217 dislocation-related creep, 217 mechanism, 324–325 mechanisms, 215–217 resistance enhanced, 320–321 factors, 321–323 stages of, 214–215 tin creep, 218 tin-silver eutectic alloy, 218–219 tin-zinc eutectic alloy, 218–219 Critical resolved shear stress, 212 Crops, metal contamination in, 58 CRT. See Cathode ray tube Crystal structure degradation, 964, 973 effect of, 469–472 Crystallographic orientation, 867 CSP. See Chip scale package CSTEE. See Committee on Toxicology, Ectoxicology and Environment CTE. See Coefficient of thermal expansion Cycles-to-failure, solders, determination of, 231–233 Damage models, lead-tin soldering, 204–205 Danish order to phase out lead, 125–126 Decomposition reactions, 405–407 Degradation phenomena, 915–978 alpha emitters, lead solders, 943–947 anisotropy, 925–929, 973 elasticity-based mechanical properties, 925–926 physical properties, 925 plasticity, 926–929 thermal ratcheting, 926–929 Coffin-Manson model, 966–969 crystal structure, 973 degraded interfaces, 974 failure prediction models, 966–969 interfaces description, 950 examples of degraded interfaces, 957–960 flip chip pull test, 956–957 Kirkendall void formation, 957–959 liquid solder reaction, flip chip terminal pads, 955
984 [Degradation phenomena] mechanical characteristics, 950–951 phase system, effect on mechanical properties, 951–953 reaction at flip chip under-bumpmetallurgy interfaces, 953–955 structural, 950–951 interfaces in solder joints, 950–960 lead-free solders, 948 multiple reliability requirements, 961–962 plastic strain accommodation, 964–966 radiation, source of, 937–943 recrystallization, 962–964 relaxation, 962–964 reliability, 961–973 soft errors, 937–950, 973 defined, 937 temperature hierarchy, 915 testing, 971–973 tin, 929–936 allotropic change between materials classifications, 919 allotropic changes within metallic system, 918–919 behavior of, 917–925 comparison of solder systems, 919–925 growth kinetics, 931–934 history, 929 materials classifications, 917–918 nucleation effects, 931–934 occurrence-description, 929–931 other factors, 935–936 preventative methods, 936 tin-based solder, 915–917 underfill, effects of, 969–971 ‘‘young’’ lead, effect of, 948 Denmark electronic waste management, 131–132 order to phase out lead, 125–126 Density, solder wetting, 352–354 DEP. See Department of Environmental Protection Department of Environmental Protection, 140 Department of Natural Resources, 141 Department of Trade and Industry, 6, 304 Destruction removal efficiency, 105 Deviatoric stress state, 869–871 Die size, tin-silver solders, 240 Differential scanning calorimetry, 246, 480, 791, 799 Differential thermal analysis, 672 Diffusional creep mechanism, 216–217 Diffusive spreading coefficient, 366 Diffusivity, solder wetting, 360–361
INDEX Direct chip attach, 194 Dislocation glide, 963 Dislocation-related creep, 217 Dispersoids high-temperature lead-free solders with, 301–330 bulk solder without reinforcements, 313 composite solders, 305–306 dispersoids, effects on microstructural stability, 309 fracture characteristics, 326 further investigations, 313 harsh service conditions, 302–303 high-temperature applications, 301–302 interfacial intermetallic compound layers, 311–313 lead-free composite solders studies, 313–327 lead/tin system studies, 307–313 mechanically added reinforcements, 316–320 melting point, 304–305 microstructural/property requirements, 303 overview, lead-free solder alternatives, 304–305 process challenges, 301 process compatibility, 303 reinforcement addition methods, 306 reinforcement requirements, 305–306 reinforcement types, 306 reinforcements on mechanical properties, effects of, 320–323 requirements, 302–303 solderability, 325–326 solders with reinforcements, in situ method, 313–316 stress relaxation, 323–325 thermal expansion, low coefficient of, effects of, 310–311 ultrafine oxide dispersions, effects of, 309–310 use of dispersoids, 302 weakly bonded reinforcements, 326–327 presence of, 303 Distance from neutral point, 814 Distilled water toxicity test methods, 77–78 DNR. See Department of Natural Resources Double wave systems, 545–546 Drinking water contaminated, 3 heavy metals in, 57–58 worldwide regulation, 57 DSC. See Differential scanning calorimetry
INDEX DTI. See Department of Trade and Industry Dual in-line IC packages, 700 Dynamic mechanical analyzer, 758 Dynamic random access memory, 937 Eco-auditing, management system, 121 Eco-labels, 151–155 benefits, 152–154 types of labels, 152–153 Eco-marketing Europe, 161–162 consortia, 161 corporate policies, 161 products, 161–162 Japan, 155–160 consortia, 156 corporate policies, 156 products, 156–158 North America, 162–164 consortia, 163 corporate policies, 162–163 products, 163–164 Edema, brain, effect of lead, 51 EIAJ. See Electronic Industries Association of Japan Electrical conductivity, isotropically conductive adhesives, 753–755 contact resistance stability, 755–758 corrosion inhibitors, 756–757 increase shrinkage, 755 lubrication layer, 753–754 moisture absorption, 756 oxygen scavengers, 757 prevention, 756–758 resistance increase, 755–756 sharp-edge filler particles, 757–758 transient liquid-phase fillers, 755 Electrical current, 827 Electrical function, cardiac, effect of lead, 51 Electrical glass, 509 Electrically conductive adhesives, 729–768 anisotropically conductive adhesives, 762–763 adhesive matrix, 731 categories, 730 conductive fillers, 731–732 description of, 729–732 high-frequency compatibility, 762 materials development, 762 metal particles with insulating coating, 732 nonmetal particles with metal coating, 731–732 reliability, 762–763
985 [Electrically conductive adhesives] solid metal particles, 731 electrical conductivity, isotropically conductive adhesives, 753–755 contact resistance stability, 755–758 corrosion inhibitors, 756–757 increase shrinkage, 755 lubrication layer, 753–754 moisture absorption, 756 oxygen scavengers, 757 prevention, 756–758 resistance increase, 755–756 sharp-edge filler particles, 757–758 transient liquid-phase fillers, 755 flip-chip applications, 732–742 advantages, 746 anisotropically conductive adhesives flip chip for bumped dies, 732–735 anisotropically conductive adhesives flip chip for CSP, BGA applications, 739–741 anisotropically conductive adhesives for unbumped flip chips, 736–739 ceramic chip carriers vs. organic chip carriers, 741 coated plastic filler, 733 comparison with soldered joints, 749–750 conductive columns, 737–739 curing, 747–749 double-layered ACF film, 740 failure mechanism, 742 loss of compressive force, 742 oxidation of nonnoble metals, 742 glass chip carriers, 735–736 MAPLE method, 735–735 selective tacky adhesive method, 735 gold stud vs. electroless nickel/gold bumps, 741 gold-coated nickel filler, 737 high-frequency applications, 736 isotropically conductive adhesives process for unbumped chips, 750–751 metal-bumped flip-chip joints, 749–750 nickel filler, 734–735 nickel/gold-coated silver filler, 737 print isotropically conductive adhesives, 747 process, 746–749 protective chip pad layer, 746–747 SMT applications, 741 solder filler systems, 733–734 two filler systems, 732–733 underfill, 749
986 [Electrically conductive adhesives] using isotropic conductive adhesives, 746–751 future challenges, 762–763 impact performance, 758–759 epoxide-terminated polyurethane systems, 759 isotropically conductive adhesives, 763 adhesive matrix, 743–745 conductive fillers, 745–746 description, 742–746 electrical characteristics, 763 high-frequency performance, 763 latency, rapid curing, 744 low Tg materials, effect of, 744 low-melt fillers, 745–746 manufacturability, yields, 763 matrix materials, 743 moisture absorption, effect of, 744–745 particle shape, size, 745 percolation theory of conduction, 742–743 pure silver vs. silver-coated fillers, 745 reliability, 763 silver-copper fillers, 745 microelectronics packaging, 751–753 advantages, 752 CSP applications, 752 disadvantages, 752 fatigue life of isotropically conductive adhesives joints, 753 high-frequency performance of isotropically conductive adhesives joints, 752–753 surface mount applications, 751–752 nonconductive adhesives, 759–762 3-D CSP application, 761 applications, 760–762 flip-chip applications, 760–761 micron bump technology, 759–760 NCAs vs. anisotropically conductive adhesives in flex circuits, 760 print heads, 760 smart labels, 761–762 SMT applications, 760 Electroless nickel covered with immersion gold, 99 Electroless nickel/electroless palladium/ immersion gold, 435, 441–442 Electroless nickel/immersion gold, 435, 439–441, 802 Electroless plating, 513–514 Electrolytic plating, 512–513 Electrolytic silver, 446
INDEX Electrolytic tin-bismuth, 438–439 Electromagnetic interference, 937 Electromigration, 827–844 basis of modern theory, 828–832 degradation, 962 early studies, 828 failure in flip chip solder joints, 837–838 failure in lead-based solders, 836–841 classification, 836–837 lead content dependence, 836 fast diffuser electromigration, 833–836 fast diffusion, 834 interstitial diffusion, 834 second components, effect of, 834–835 solubility, 834 fast diffusers in lead alloys, 838–841 testing, 842–844 accelerated testing, 842–843 overstressing, 843 temperature effects, 843–844 theory of, 827–833 tin-based lead-free alloys, 841–842 comparison to lead, 841 fast diffusers in tin, tin-based alloys, 842 testing, 841–842 Electronic assemblies acceleration factor, 772–773 characteristics, 778–780 effect, 780 lead, as minor element, 770–780 presence, 778–779 distributions, 771–772 element replacements for lead, cost, 14 intermetallic compounds, 780–782 metallurgical, structural factors, 777–787 reliability, 769–826 solders utilized for, 11 statistics, 770–773 testing, 772–777 major failure mechanisms, 774–777 methods, specifications, 773–774 specifications, 773–774 test vs. field failures, 773 Electronic Industries Association of Japan, 689 Electronic materials toxicology of, 63–74 Electronic waste management Europe, 125–137 Austria, 130, 131 Belgium, 130–131 Denmark, 131–132 Finland, 131, 132 France, 131, 132
INDEX [Electronic waste management] Germany, 131, 132 Italy, 131, 133 Netherlands, 131, 133–135 Norway, 131, 135 Spain, 131, 135 Sweden, 131, 135–136 Switzerland, 131, 136–137 United Kingdom, 131, 137 landfills, 85 Electronics, 495–568 adhesives, 527 assembly processes, tools, 527–539 fluxing, 531–533 placement, 533–536 reflow soldering temperature profiles, 536–539 solder joints, 529–530 solder paste printing, 530–531 build-up technology, printed circuit boards utilizing, 556–567 laser processes, 560–567 mass generation processes, 559–560 mechanically drilled microvias, 560 miniaturization issues, 557–558 overview, 556–557 photolithographically defined vias, 558–559 solid post construction, 560 components, 524–527 fluxes, 520–524 fundamental assembly issues, 497 lead use in, 115–116. See also Lead lead-free solder in. See also Lead bismuth-tin solders, 282–288 circuit boards, lead-free finishes, 431–464 corporate policy, 149–166 degradation phenomena, 915–978 electrically conductive adhesives, 729–768 electromigration, 827–850 electronic assembly, lead-free materials in, 495–568 environmental impact, 49–82, 83–114 health issues, 49–82 high-temperature lead-free solders, with dispersoids, 301–330 inert atmospheres, in lead-free soldering, 569–590 intermetallic compounds, at metal interfaces in solder joints, 465–494 international lead-free solder studies, 665–728 lead-free component conversion, 591–664
987 [Electronics] lead-free finishes, printed circuit boards, 431–464 marketing trends, 149–166 mechanical properties, 211–238 metallurgical properties, 167–210 overview, 769–826 product trends, 149–166 regional perspectives, environmental stewardship with, 115–149 solder wetting, spreading, 331–430 thermomigration in solders, 827–850 tin-antimony solders, 288–290 tin-copper solders, 290–292 tin-indium solders, 294–296 tin-silver solders, 239–280 tin-whisker formation, structure, kinetics of, 851–914 tin-zinc solders, 292–294 utilization of, 1–48 lead-free wave soldering, 546–554 bismuth contamination, effects of, 549–550 copper dissolution, 547–549 double-wave soldering, 546–547 energy consumption, 553–554 iron contamination, 550 lead contamination, effects of, 549–550 rework, 552–553 solder defects, 550–551 underfill, 553 use of inert atmosphere, 547 wave machine material compatibility, 551–552 quality processing, 554–556 handling, 555 setup checks, 555–556 training, 554 replacing lead-bearing solders in, 85–88 solder joint perfection, 496–497 solder paste materials, 497–507 formulation, 498 powder particle size, 498–499 printing efficiencies, 499 solder paste, 497–498 solder paste characteristics, 499–501 solder paste tests, 501–507 solder reflow methods, 539–542 carriers, 540 double side assembly issues, 540–541 forced convection heating, 539 infrared radiation, 539 metallurgical reactions, 541 solder joint structure, 541–542
988 [Electronics] standard printed circuit boards, 507–520 deposition techniques, 509–514 I/O pad design, 514–520 pad finishes, 509–514 process temperatures, effect of, 508–509 reinforcement materials, 509 wave soldering considerations, 542–546 lead-free solder temperature, 545 preheating, 544–545 solder wave configuration, 545–546 wave flux, 542–543 Electronics Manufacturing Productivity Facility, 667 Electroplated tin, 447–448 Element replacements for lead, electronic assemblies, cost, 14 Elimination of lead from human body, 53–55 liver, 55 renal system, 54 respiratory tract, 54 Emergency Plan and Community Right to Know Act of 1986, 138 EMPF. See Electronics Manufacturing Productivity Facility Encephalopathy, effect of lead, 51 End of life disposal, 102–105 landfills, 103–105 construction of sites, 103 geo-movement, toxic materials, 104–105 leaching, 103–106 municipal solid waste combustors, 105 bottom residue, 105 stack emissions, 105 End-of-life recovery, 106–109 collection schemes, burden, 106–107 collection/take back programs, 106–109 environmental benefits, 109 materials recovery, 108–109 scrap composition, 107–108 transportation considerations, 107 Energy consumption, impact on environment, 102 Energy partitioning, 678 Energy-dispersive x-ray, 798 Environmental impact, lead, 83–114 electronics, replacing lead-bearing solders in, 85–88 end of life disposal, 102–105 bottom residue, 105 construction of sites, 103 geo-movement, toxic materials, 104–105 landfills, 103–105 leaching, 103–106
INDEX [Environmental impact, lead] municipal solid waste combustors, 105 stack emissions, 105 end-of-life recovery, 106–109 collection schemes, burden, 106–107 collection/take back programs, 106–109 environmental benefits, 109 materials recovery, 108–109 scrap composition, 107–108 transportation considerations, 107 energy consumption impact, 102 environmental approach, 88–90 responses to environmental problems, 89–90 industrial ecology assessment, 108–111 industrial ecology assessment, 111 product manufacture, 100–110 product use, 110–111 refurbish, recycle, disposal, 111 resource extraction, 109 transportation, 110 landfills, electronic waste, 85 lead utilization, 84 metallic elements in electronic assemblies, 94–101 antimony, 97 bismuth, 97–98 copper, 96–97 gold, 98–99 indium, 98 lead, 95–96 nickel, 99 platinum group metals, 99–100 silver, 100 tin, 95 zinc, 100–101 obsolete electronics, 84–85 product manufacture, 101–102 rate of growth, 85 recycling, waste streams prior to, 85 regional perspectives, 115–149 resource extraction, 90–101 abundance, 92 energy consideration, 92–93 hydrometallurgy, 93 ores, 91–92 pyrometallurgical roasting of ore, 92 reduction, 93 waste products, 93–94 temperatures during assembly, increase in, 102 United States, consumption of lead in, 84 Environmental management system, 5, 118, 144
INDEX Environmental Protection Agency, 83, 115, 136, 150 Environmental standard ISO 14001, attributes, features of, 5 Environmentally preferable purchasing, 118, 150. See also Eco-labels EPA. See Environmental Protection Agency EPCRA. See Emergency Plan and Community Right to Know Act of 1986 Epoxide-terminated polyurethane systems, impact performance, 759 Ethylenediaminetetraacetic acid, 286, 401 Ethylenedinitrilotetraacetic acid, 55 Europe eco-marketing in, 161–162 consortia, 161 corporate policies, 161 products, 161–162 electronic waste management, 132, 137 initiatives in, 6–7 European Community, 161 European Union, 2, 72, 115, 121–126, 665 banned substances, 122 end-of-life vehicles directive, 124 exemptions, 124 exemptions, 122–123 hazardous substances restriction in electronic products, 121–122 materials restrictions, 121 member states’ initiatives, 124–126 Danish order to phase out lead, 125–126 Swedish environmental quality objectives, 126 regulation by, 64 timeline, penalties, 123–124 waste from electronic equipment, 121–122 Eutectic systems, 382–383 Eutectic tin-lead, 537 Eutectic tin-lead solder, degradation, 924, 965 Excessive solder, 551 Exposure routes, heavy metals, 55–59 air, 55–56 body destinations, 56 ingestion, 56–58 Extended producer responsibility, 118 Extruded products, lead usage, 2 Failure prediction model, degradation, 966–970 Failure-in-time, 937 Fast diffuser electromigration, 833–836 interstitial diffusion, 834 second components, effect of, 834–835 solubility, 834 Fast diffusers in lead alloys, 838–841
989 Fatigue isothermal, solders, 222–233 lead-tin soldering, microstructural effects, 200–202 thermomechanical, solders, 233–236 Fatigue crack nucleation, 223–225 Fatigue failure studies, lead-tin soldering, 202–203 Coffin-Manson model, 202 frequency-modified, Coffin-Manson equation, 202 plane strain levels, Coffin-Manson, 202–203 strain energy approach, 203 Fatigue resistance, degradation, 961 FDA. See Food and Drug Administration Feature mis-identification, 535 Fetal development, effect of lead, 51 FIB. See Focused ion beam Fillet lifting, 550–551 Fine oxide particles, effects on microstructure, 310 Finite element, 684 Finland, electronic waste management, 132 Flextronics International, Ltd. lead-free assembly, 633–640 Flip chip issues, 814–819 assembly processes, effects of, 814 ceramic, organic carriers, lead-free flip chips on, 817 creep, effect on lead-free flip-chip solder joints, 816 highest-density assemblies, evolution of microstructures in, 817–819 lead-free solder bumps, characteristics of, 814 secondary reflow, 814 thermal fatigue characteristics, lead-free solder bumps, 817 tin-bismuth-copper system, 818–819 transfusion-bonded lead-free flip chips, 819 UBM, lead-free solder interactions effects of, 815–816 interfacial failures, 816 solid-state interactions, 816 tin-bismuth, 816 tin-lead solder, 816 tin-silver, 815–816 tin-silver-X solders, 815–816 Flip chip on board, 194 Flip chip on flex, 740 Flip chip pull test degradation, 956–957 degradation phenomena, 956–957 lead-free solder joints, 957 lead-tin solder joints, 956
990 Flip chip under-bump-metallurgy interfaces, degradation, 953–955 Flip-chip applications, 732–742 anisotropically conductive adhesives flip chip for bumped dies, 732–735 coated plastic filler, 733 nickel filler, 734–735 solder filler systems, 733–734 two filler systems, 732–733 anisotropically conductive adhesives flip chip for CSP, BGA applications, 739–741 ceramic chip carriers vs. organic chip carriers, 741 double-layered ACF film, 740 gold stud vs. electroless nickel/gold bumps, 741 anisotropically conductive adhesives for unbumped flip chips, 736–739 conductive columns, 737–739 gold-coated nickel filler, 737 nickel/gold-coated silver filler, 737 anisotropically conductive adhesivesbumped flip chips glass chip carriers, 735–736 high-frequency applications, 736 MAPLE method, 735–735 selective tacky adhesive method, 735 ceramic chip carriers vs. organic chip carriers, 741 failure mechanism, 742 loss of compressive force, 742 oxidation of nonnoble metals, 742 isotropic conductive adhesives, 746–751 advantages, 746 comparison with soldered joints, 749–750 curing, 747–749 isotropically conductive adhesives process for unbumped chips, 750–751 metal-bumped flip-chip joints, 749–750 print isotropically conductive adhesives, 747 process, 746–749 protective chip pad layer, 746–747 underfill, 749 nonconductive adhesives, 760–761 SMT applications, 741 using isotropic conductive adhesives, 746–751 advantages, 746 comparison with soldered joints, 749–750 curing, 747–749 isotropically conductive adhesives process for unbumped chips, 750–751
INDEX [Flip-chip applications] metal-bumped flip-chip joints, 749–750 print isotropically conductive adhesives, 747 process, 746–749 protective chip pad layer, 746–747 underfill, 749 Flow stress solders, 214 strain rate on, effect of, 222 Fluoride content tests, 524 Flux activation, 523, 602–604 Flux apllication, 542–543 Flux dipping, 532 Flux selection, lead-free component conversion, 592 Flux technology, lead-tin soldering, 191–192 controlled atmospheres, 192 flux categories, 191–192 function of flux, 191 Flux volume, 532–533 Fluxing, 531–533 Fluxless soldering, 414–415 Focused ion beam, 459, 868–869, 875, 900, 911 tin whiskers, eutectic tin-copper finishes, 875–879 Food, lead in, 58. See also under Health issues Food and Drug Administration, 55 Ford, lead-free solders utilization in, 27 Fracture characteristics, 784–786 crack propagation, 784–786 microcracking, 784 France, electronic waste management, 132 Fujitsu, eco-marketing, 157 Fundamental assembly issues, 497 Furnace heating, lead-tin soldering, 193 Gallium, occupational exposure to, 3 Gaseous contaminant absorption, effect of, 335–336 GECI. See Global Environmental Coordination Initiative Geo-movement, toxic materials, 104–105 Germany, electronic waste management, 132 Gestation period, implantation influences, effect of lead, 51 Glass, oxides used for, lead usage, 2 Global Environmental Coordination Initiative, 164 Global vs. local equilibrium, 347 Glow discharge mass spectrometry, 950 Gold concentration, effect of, 475–476 in electronic assemblies, 98–99
INDEX [Gold] migration, 783 world reserves of, 13 Gold-coated copper, tin reaction with, 365 Gout, effect of lead, 51 GPN. See Green Purchasing Network Grain boundary sliding, 963 Grain orientation under whisker, 871 Gray tin, degradation, 925 Green marketing, 155 Green purchasing, 118, 144 Green Purchasing Network, 151 Growth below solidus temperature, 473–474 Halogen-free organic fluxes, 390–401 Hand soldering, lead-tin soldering, 194 HASL. See Hot air solder leveling Hazardous substance, definition of, 64 HDPUG. See High Density Packaging Users Group Health issues antimony use, 71 indium, 72 ingestion, 71 regulation, 72 toxicity in humans, 72 bismuth use, 69–70 human exposure, 69 regulation, 70 cadmium use, 73 copper use, 70 direct contact, 70 ingestion, 70 inhalation, 70 lead use, 49–82 air, 55–56 blood, lead effects on, 52 body destinations, 56 bone integrity, 53 cardiovascular system, 52–53 central nervous system, 51–52 contaminated water, 59–63 crops, metal contamination in, 58 distilled water methods, 77–78 distilled water with salts methods, 78 drinking water, 57–58 electronic materials, toxicology of, 63–74 elimination from human body, 53–55 European Union, regulation by, 64 exposure routes, 55–59 extraction solution, 76–77 hazardous substance, definition of, 64 heavy metals, target organs for, 50–53 ingestion, 56–58
991 [Health issues] interpretation of results, 78–79 landfill issues, 59 leachate concentration, 74 leachate reactions, 61–63 liver, 55 national standards, 58–59 organ systems, effects of lead on, 51 renal system, 52, 54 reproductive toxicity, 53 respiratory tract, 54 solid waste disposal, 59–63 soluble threshold limit concentration, 78 synthetic aids to elimination, 55 synthetic precipitation leaching procedure, 77 total threshold leaching concentration, 78 total threshold limit concentration, 78 toxicity, lead metabolism, 51 toxicity characteristic leaching procedure, 76–77 toxicity mechanisms, 50 toxicity test methods, 74–79 United States government agencies, regulation by, 64 worldwide regulation, 57 lead-free solders, 2–3 nickel use, 72–73 direct contact, 73 ingestion, 72 inhalation, 72 silver use, 70–71 direct contact, 71 inhalation, 71 regulation, 71 tin use, 73 ingestion, 73 inhalation, 73 regulation, 73 zinc use, 67–69 ingestion, 68–69 inhalation, 69 low toxic concern/regulation, 69 Heating methods, lead-tin soldering, 192–194 furnace heating, 193 hand soldering, 194 vapor phase heating, 193 wave soldering, 193–194 Heavy metals, target organs for, 50–53 Hemoglobin synthesis, effect of lead, 51 High density interconnect, 435 High Density Packaging Users Group, 163, 665, 726
992 High lead-low tin solder isothermal fatigue, 229 thermomechanical fatigue, 233 High lead-tin solder, degradation, 964–965 High strain rate effects, degradation, 960 High-definition televisions, 112 High-frequency compatibility, anisotropically conductive adhesives, 762 High-frequency performance of isotropically conductive adhesives joints, microelectronics packaging, 752–753 Highly reactive systems, product formation in, 368–369 High-temperature lead-free solders with dispersoids, 301–330 composite solders, 305–306 defined, 305 reinforcement addition methods, 306 reinforcement requirements, 305–306 reinforcement types, 306 high-temperature applications, 301–302 lead-free composite solders studies, 313–327 bulk solder without reinforcements, 313 fracture characteristics, 326 mechanically added reinforcements, 316–320 reinforcements on mechanical properties, effects of, 320–323 solderability, 325–326 solders with reinforcements, in situ method, 313–316 stress relaxation, 323–325 weakly bonded reinforcements, 326–327 lead/tin system studies, 307–313 dispersoids, effects on microstructural stability, 309 further investigations, 313 interfacial intermetallic compound layers, 311–313 thermal expansion, low coefficient of, effects of, 310–311 ultrafine oxide dispersions, effects of, 309–310 melting point, 304–305 overview, lead-free solder alternatives, 304–305 process challenges, 301 requirements, 302–303 harsh service conditions, 302–303 microstructural/property requirements, 303 process compatibility, 303 use of dispersoids, 302
INDEX High-temperature reflow profiles alternative solutions, 802–803 assembly effects, 802 effects of, 802–803 Hitachi eco-marketing, 157 lead reduction initiatives, 8 lead-free solders utilization in, 27 Homogeneous vs. heterogeneous reaction, 368 Homologous temperature, solders, 2111 Hot air solder leveling, 88, 433, 435, 511–512, 520, 574, 593, 700 Hybrid microcircuits, 195 Hydrometallurgy, 93 Hypertension, effect of lead, 51 Hysteresis loops, superimposed, 235 IARC. See International Agency for Research on Cancer IATA. See International Airline Transport Association IBM. See International Business Machines ICP-J-Std-002, 003, 6 IDEALS project, 695–715 alloys selected for investigation, 697 project goals, 696–697 project organizations, participants, 695–696 property investigations, 697–700 board, component finishes, 700 development of soldering materials, 700 mechanical, physical properties, 698–699 solderability, 697–698 solidification, aged structures, 699–700 reflow soldering, 708–710 solder paste development, 708 time-temperature process window, 708–710 reliability assessment, 710–714 humidity tests, 713–714 intermetallic compound growth, 714 recommendations, 714–715 temperature cycling, 711–712 vibration, shock, 712–713 solder joint rework, 710 test board, 710 rework trials, 710 wave soldering process studies, 700–708 large-scale process trials, 702–708 preliminary trials, 702 test vehicles, 701–702
INDEX IMC. See Intermetallic compound Immersion plating, 514 Immersion silver, 443–446 Immersion tin, 446–447 Impact performance, 758–759 epoxide-terminated polyurethane systems, 759 Improved Design Life and Environmentally Aware Manufacture of Electronic Assemblies by Lead Free Soldering (IDEALS), 161, 695 Impurities, degradation, 957 Impurities in tin, 948 Indium in electronic assemblies, 98 occupational exposure to, 3 regulation of, 57 world reserves of, 13 Induction melting/gas atomization, 308 Industrial ecology, 89, 108–111 industrial ecology assessment, 111 product manufacture, 100–110 product use, 110–111 refurbish, recycle, disposal, 111 resource extraction, 109 transportation, 110 Industry reference, HASL eutectic tin-lead, 436–437 Inert atmospheres, 569–590 board surface finishes, 573–574 equipment, 587–589 reflow systems, implementing nitrogen in, 588 selective soldering systems, use of nitrogen in, 588–589 wave solder systems, implementing nitrogen in, 587–588 impacts, 575 inerted reflow soldering, 570 joint appearance, 587 lead-free solders, nitrogen inerting, 577–581 activators in flux, 577–578 cleaning residues, 580 dross, 579–580 nitrogen inerting improves yields, 580–581 wetting, 578–579 low-solids fluxes, 574 nitrogen, 575, 581–583 double-sided reflow, 584 effect on reliability, yield, 586–587 flux reduction, 581 high-temperature soldering, 585 increased dross formation, 581
993 [Inert atmospheres] in lead-free reflow soldering, 583–585 nitrogen, effect on wetting temperature, 582–583 pastes, reflow profile, 583–584 role of nitrogen, 584 through-hole reflow, 584–585 wetting of lead-free solders, 581–582 nitrogen consumption, cost issues, 585 differences between surface mount, wave soldering, 585 reflow soldering, 585 wave soldering, 585 no-clean, inerting emerges from, 569–570 oil, 569 reflow soldering, 586 residual oxygen level, 572–573 soldering electronics, 569 tinning components, 570–571 wave solder dross formation, 571–572 dross, 571 health issues, 572 metal oxidation, 571 parameters affecting, 571–572 wave soldering, 586 Inert vs. reactive systems, 347 Inerted reflow soldering, 570 Infrared, 536, 570 Ingots, lead usage, 2 Inorganic lead, occupational exposure to, 3 Inorganic tin, occupational exposure to, 3 Insertion mount component, 495, 497 Insulators, degradation, 917 Integrated circuit, 733, 833, 939 Integrated recrystallization theory, 893–896 Intelligence, cognitive, effect of lead, 51 Interconnection levels, lead-tin soldering, 194–197 level 1 interconnections, 194 level 2 interconnections, 194–196 level 3 interconnections, 196–197 Interconnection Technology Research Institute, 916 Interfacial reactions, lead-tin soldering, 188–191 protective finishes, 188–189 solderable finishes, 189–191 Intermediate phases in lead-free solder alloys, intermetallic compounds, formation of, 481–483 Intermetallic compound, 11, 241, 311, 447, 465, 511, 592, 601, 776, 834, 842, 885, 955 effect on stress state, 885–886
994 [Intermetallic compound] lead-tin/metal, lead-free/metal interfaces, 465–494 composition, 480 on copper metallization, 472–474 copper-nickel-tin ternary system, intermediate phases, 483 eutectic tin-lead solder, 472–480 formation, 469–472 gold in, 475–480 intermediate phases in lead-free solder alloys, 480–489 kinetics vs. energetics, 469–472 lead-tin system, 466–467 model for tin/M systems, 480 nickel metallizations, lead-tin solder on, 474–475 solder joint structure, 469 thickness, effect of, 370 International Agency for Research on Cancer, 72 International Airline Transport Association, 64 International Business Machines, high-complexity SMT components to lead-free technology, 646–651 International Organization for Standardization, 152 International Standards Organization certification, lead-free solders, 5–6 International studies, lead-free solder, 665–728. See also Studies International Tin Research Institute, 666, 863 Intragranular versus intergranular failure, 541–542 Inventory management, 594 Iron interface reactions with, 179–180 lead-tin system, interface reactions with, 179–180 IRT. See Integrated Recrystallization Theory ISO. See International Organization for Standardization; International Standards Organization ISO 14001, attributes, features of, 5 Isothermal fatigue, solders, 222–233 change in ratio, 227 cycles-to-failure, determination of, 231–233 failure, definition of, 225–228 fatigue crack morphology, 225 fatigue crack nucleation, 223–225 fatigue crack nucleation energy, 223–225 flaws, as stress risers, 223 flaws act as stress risers, 223
INDEX [Isothermal fatigue, solders] high lead-low tin solder, 229 lead-free solders, 229 macrocrack propagation, 225 maximum stress, reduction in, 226–227 strain range, cycle period, effects of, 228–231 Isotropic conductive adhesives, 729, 763 adhesive matrix, 743–745 latency, rapid curing, 744 low Tg materials, effect of, 744 matrix materials, 743 moisture absorption, effect of, 744–745 conductive fillers, 745–746 low-melt fillers, 745–746 particle shape, size, 745 pure silver vs. silver-coated fillers, 745 silver-copper fillers, 745 description, 742–746 electrical characteristics, 763 electrical conductivity of, 753–755 contact resistance stability, 755–758 corrosion inhibitors, 756–757 increase shrinkage, 755 lubrication layer, 753–754 moisture absorption, 756 oxygen scavengers, 757 prevention, 756–758 resistance increase, 755–756 sharp-edge filler particles, 757–758 transient liquid-phase fillers, 755 flip-chip applications, 746–751 advantages, 746 comparison with soldered joints, 749–750 curing, 747–749 isotropically conductive adhesives process for unbumped chips, 750–751 metal-bumped flip-chip joints, 749–750 print isotropically conductive adhesives, 747 process, 746–749 protective chip pad layer, 746–747 underfill, 749 high-frequency performance, 763 joints, microelectronics packaging fatigue life of, 753 high-frequency performance of, 752–753 manufacturability, yields, 763 percolation theory of conduction, 742–743 reliability, 763 Italy, electronic waste management, 133 ITRI. See Interconnection Technology Research Institute; International Tin Research Institute
INDEX Japan eco-marketing, 155–160 consortia, 156 corporate policies, 156 products, 156–158 first commercial products, 687–688 JEIDA reliability evaluation, 689–692 JIEP project, 693 JWES method, materials evaluations, 692–693 lead restrictions, electronic waste management, 141–145 key program elements, 141–145 lead-free drivers, 141 PC green label, 141–143 recycle focus, 141 lead-free solder roadmap in, 695 New Energy and Industrial Technology Development Organization study, 688 proliferation of products, 688 promotion of lead-free soldering, 687–688 research, development in, 687–695 Japan Electronic Industry Association, 665 Japan Electronic Industry Development Association, 84 Japan Electronics and Information Technology Industries Association, 164, 687 Japan Green Procurement Survey Standardization Initiative, 143 Japan Institute of Electronics Packaging, 156, 304, 665, 687 Japan Welding Engineering Society, 689 Japanese Electronics Industry Development Association, 7 Japanese Welding Association, 156 JEDEC J-Std-620A, 6 JEIDA. See Japan Electronic Industry Development Association; Japanese Electronics Industry Development Association JEITA. See Japan Electronics and Information Technology Industries Association JGPSSI. See Japan Green Procurement Survey Standardization Initiative JIEP. See Japan Institute of Electronics Packaging Joint current density, tin-silver solders, temperature, 240 Kidney, effect of lead on, 51 Kirkendall void formation degradation phenomena, 957–959
995 Landfills, 103–105 construction of sites, 103 contamination, 59 electronic waste, 85 geo-movement, toxic materials, 104–105 leaching, 103–106 Laser ablation, 560–562 Laser soldering, 589 Leachate reactions, 61–63 Leaching, landfills, 103–106 Lead. See also Health issues bismuth-tin solders, 282–288 contamination in crops, 58 corporate policy, 149–166 degradation phenomena, 915–978 effect of, 800 on organ systems, 51 electrically conductive adhesives, 729–768 electromigration in solders, 827–850 electronic assemblies, 95–96. See also Electronic assemblies lead-free materials in, 495–568 lead-free solders in, 769–826 environmental impact, 49–114 health issues, 49–82 leachate concentration, 74 toxicity test methods, 74–79 high-temperature lead-free solders, with dispersoids, 301–330 inert atmospheres, in lead-free soldering, 569–590 inorganic, occupational exposure to, 3 intermetallic compounds, at metal interfaces in solder joints, 465–494 international lead-free solder studies, 665–728 lead-free component conversion, 591–664 lead-free finishes, printed circuit boards, 431–464 legislation, 3–4 marketing trends, 149–166 product trends, 149–166 regional perspectives, environmental stewardship with, 115–149 regulation of, 57 solder from lead-tin system, metallurgical properties, 167–210 solder mechanical properties, 211–238 solder wetting, spreading, 331–430 thermomigration in solders, 827–850 tin-antimony solders, 288–290 tin-copper solders, 290–292 tin-indium solders, 294–296 tin-lead solders, 11
996 [Lead] tin-silver solders, 239–280 tin-whisker formation, structure, kinetics of, 851–914 tin-zinc solders, 292–294 utilization of, 1–48 world reserves of, 13 Lead reduction, initiatives in, 7–8 Lead restrictions, 115 ban on lead, 121 design for environment, 117–118 electronic waste management Austria, 130, 131 Belgium, 130–131 California, 140 Connecticut, 140 Denmark, 131–132 Europe, 125–137 Finland, 131, 132 Florida, 140 France, 131, 132 Germany, 131, 132 Italy, 131, 133 Japan, 141–145 Massachusetts, 140 Minnesota, 140 Netherlands, 133–135 New Jersey, 140 New York, 141 Norway, 131, 135 South Carolina, 141 Spain, 131, 135 Sweden, 131, 135–136 Switzerland, 131, 136–137 United Kingdom, 131, 137 United States, 139–141 Wisconsin, 141 electronics, lead use in, 115–116 European Union, 121–126 banned substances, 122 Danish order to phase out lead, 125–126 end-of-life vehicles directive, 124 exemptions, 122–123, 124 hazardous substances restriction in electronic products, 121–122 materials restrictions, 121 member states’ initiatives, 124–126 Swedish environmental quality objectives, 126 timeline, penalties, 123–124 waste from electronic equipment, 121–122 green procurement standards, 144 green purchasing, 118 life-cycle perspective, 117
INDEX [Lead restrictions] product stewardship, 117–121 regulation of lead, 116–117 take-back/recycling, 118–121 extended producer responsibility, 118–119 scrap reuse, recycling, 120–121 takeback schemes, 119–120 United States, 137–139 PBT-abased modifications, 139 Reid Bill, 137–138 reporting thresholds, 138, 139 toxic release inventory, 138–139 waste disposal, 121 Lead-bearing solders in, replacing, 85–88 Lead-free alloys, 497, 537–539 Lead-free ceramic chip carrier, 672, 676, 683, 717 components, 195 Lead-free component conversion, 591–664 alloy selection, 592 board material, 592–593 component material, finishes, 593 electronic devices, use of lead in, 591–592 flux selection, 592 IBM, 646–651 Panasonic, 595–633 process equipment, 594 synergistic effect, 593–594 Visteon, 640–645 Lead-free finishes, printed circuit boards, 431–464 costs effectiveness, 456–458 nickel-palladium, 457–458 tin, pure, 456 tin-bismuth, 456 tin-copper, 457 tin-silver, 456–457 tin-zinc, 457 electroless plating, 432–433 electrolytic plating, 432 immersion plating, 433 issues with, 461–462 lead-free component finishes, 449–454 nickel-palladium, 453–454 tin-bismuth, 453 tin-silver, tin-copper, 453 lead-free component finishes tin, pure, 454 lead-free printed circuit board finishes, 434–449 lead-free board finish criteria, 435 lead-free printed circuit board finishes, 435–449 reliability, 458–462
INDEX [Lead-free finishes, printed circuit boards] tin whisker phenomenon, 458–461 solderability, 454–456 types of finishes, 432–434 Lead-free HASL, 437–438 Lead-free solder, 9–11, 26 candidate alloys, 20–23 classification, 10 complexity, minimum, 18 cost, 13–14 degradation, 965–966 driving forces for, 2–6 electronic assemblies, solders utilized for, 11 health-related aspects, 2–3 isothermal fatigue, 229 joints, flip chip pull test, 957 market advantages, 4–5 mechanical properties, 5 melt temperature, 14–16 metallurgical complexity, minimum, 18–19 nitrogen inerting, 577–581 activators in flux, 577–578 cleaning residues, 580 dross, 579–580 nitrogen inerting improves yields, 580–581 wetting, 578–579 pastes, 531 patents on, 22–23 properties for operational requirements, 19–20 selection criteria, 12–20 standards, 6 supply, 13 technology, 26–28 toxicity, 12 traditional electronics-based solders, 10–12 wettability, 16–18 Lead-free wave soldering, 546–554 bismuth contamination, effects of, 549–550 copper dissolution, 547–549 double-wave soldering, 546–547 energy consumption, 553–554 iron contamination, 550 lead contamination, effects of, 549–550 rework, 552–553 solder defects, 550–551 underfill, 553 use of inert atmosphere, 547 wave machine material compatibility, 551–552 Lead-free wetting, 420–424 Lead-indium alloy solder joints, thermomigration, 848–849
997 Lead-tin solder, 417–419 joints, flip chip pull test, 956 Lead-tin system, solders from, 167–210 attributes of lead-tin solders, 169 bulk solder, intermetallic compounds in, 182–183 electronic applications, 168 gold, interface reactions with, 181–182 interconnection levels, 194–197 level 1 interconnections, 194 level 2 interconnections, 194–196 level 3 interconnections, 196–197 intermetallic compound formation, 175–176 as interface reaction products, 175–176 lead-tin solder joints, mechanical properties of, 183–184 iron, interface reactions with, 179–180 lead-tin soldering, 185–194 flux categories, 191–192 flux technology, 191–192 function of flux, 191 furnace heating, 193 hand soldering, 194 heating methods, 192–194 inadequate wetting conditions, 186–188 interfacial reactions, 188–191 liquid solder wettability, 185–186 protective finishes, 188–189 solderability performance of lead-tin alloys, 186 solderable finishes, 189–191 vapor phase heating, 193 wave soldering, 193–194 liquid solder interface reactions, 176 microstructures, 169–175 15Pb-85Sn example, 170–172 95Pb-5Sn example, 173–175 binary alloy phase diagram, 169–170 eutectic composition, 173 phase diagram, 169 nickel, interface reactions with, 179–180 palladium, interface reactions with, 181–182 physical, mechanical properties, 197–206 Coffin-Manson model, 202 computational modeling, 203–205 constitutive models, 203–204 corrosion resistance, 205–206 damage models, 204–205 fatigue, microstructural effects, 200–202 fatigue failure studies, 202–203 frequency-modified, Coffin-Manson equation, 202
998 [Lead-tin system, solders from] monotonic strength properties, 199–200 physical properties, 197–199 plane strain levels, Coffin-Manson, 202–203 strain energy approach, 203 time-dependent deformation, 200 time-independent deformation, 199 silver, interface reactions with, 181–182 soft solders containing lead, tin, history of, 167 solid-state interface reactions, 176–179 tin as reactive constituent, 176 Lead-tin versus lead-free alloys, 521–522 Lead-tin/metal, lead-free/metal interfaces, intermetallic compounds, 465–494 eutectic tin-lead solder, 472–480 on copper metallization, 472–474 gold in, 475–480 nickel metallizations, lead-tin solder on, 474–475 intermediate phases composition, 480 formation, 469–472 model for tin/M systems, 480 intermediate phases in lead-free solder alloys, 480–489 kinetics vs. energetics, 469–472 lead-tin system, 466–467 solder joint structure, 469 Learning difficulties, effect of lead, 51 Legislation, lead usage, 3–4 Lethal dose, lower limit, 290 Life cycle analysis, 693 Light-emitting diode, 760 Liquid crystal display, 735 Liquid solder reaction with flip chip terminal pads, degradation, 955 Liquid solder wettability, lead-tin soldering, 185–186 Liquid volume, increased, effect of, 364–365 Liquid-to liquid temperature shock, 741 Liquid/vapor, 334 Low-activity level solders, 949–950 Low-alpha solder, degradation, 945 Low-residue fluxes, 569 Low-solids fluxes, 414, 569, 574 Low-temperature, co-fired ceramic, 195 Macrocrack propagation, 225 Made-to-order solder, 948–949 Manufacturers to initiate lead reduction, 8 Marangoni flows, 349–350 Market advantages, lead-free solders, 4–5
INDEX Marketing Europe, 161–162 consortia, 161 corporate policies, 161 products, 161–162 Japan, 155–160 consortia, 156 corporate policies, 156 products, 156–158 North America, 162–164 consortia, 163 corporate policies, 162–163 products, 163–164 Marketing trends Europe, eco-marketing, 161–162 consortia, 161 corporate policies, 161 products, 161–162 Fujitsu, eco-marketing, 157 green marketing, 155 Hitachi, eco-marketing, 157 Matsushita, eco-marketing, 157–158 North America, eco-marketing, 162–164 consortia, 163 corporate policies, 162–163 products, 163–164 Mass spectrometry, 383 Material safety data sheets, 380 Matsushita eco-marketing, 157–158 lead reduction initiatives, 8 Mechanical properties lead-free solders, 5 solders, 211–238. See also Mechanical properties allotropic modification, 213 atomic level, 212 change in ratio, 227 creep, 214–219 cycles-to-failure, determination of, 231–233 diffusional creep mechanism, 216–217 dislocation related creep, 217 failure, definition of, 225–228 fatigue crack morphology, 225 fatigue crack nucleation, 223–225 fatigue crack nucleation energy, 223–225 flaws act as stress risers, 223 flow stress, 214 high lead-low tin solder, 229, 233 homologous temperature, 2111 interconnections, brittle phases, 214 isothermal fatigue, 222–233 joints, components, 235
INDEX [Mechanical properties] lead-free solders, 229, 233–234 macrocrack propagation, 225 maximum stress, reduction in, 226–227 mechanisms, 215–217 microstructural stability, 212 phase transformation analog, 220 rate of energy reduction model, 220 solubility effects, 235–236 stages of, 214–215 strain range, cycle period, effects of, 228–231 strain rate, effect of, 220 strain rate on flow stress, effect of, 222 stress relaxation, 219–220 stresses, 212–213 stress-strain relations, 220–222 superimposed hysteresis loops, 235 thermal expansion mismatch, coefficient, 211 thermally activated plastic flow, 212–214 thermomechanical fatigue, 233–236 three strain components, 221–222 tin creep, 218 tin-silver eutectic alloy, 218–219 tin-zinc eutectic alloy, 218–219 Mechanically drilled microvias, 560 Melt temperature lead-free solder, 14–16 reduction of, 609–610 tin-silver solders, 243 Memory loss, effect of lead, 51 Metal-bumped flip-chip joints, isotropic conductive adhesives, 749–750 Metal-insulator-metal active panel LSI mount engineering (MAPLE), 735 Metallurgical aspects, solders from lead-tin system, 167–210 attributes of lead-tin solders, 169 bulk solder, intermetallic compounds in, 182–183 electronic applications, 168 gold, interface reactions with, 181–182 interconnection levels, 194–197 ceramic substrate materials, 195–196 level 1 interconnections, 194 level 2 interconnections, 194–196 level 3 interconnections, 196–197 organic laminate substrate materials, 195 package input/output materials, 194–195 intermetallic compound formation, 175–176 as interface reaction products, 175–176 lead-tin solder joints, mechanical properties of, 183–184
999 [Metallurgical aspects, solders from lead-tin system] iron, interface reactions with, 179–180 lead-tin soldering, 185–194 controlled atmospheres, 192 flux categories, 191–192 flux technology, 191–192 function of flux, 191 furnace heating, 193 hand soldering, 194 heating methods, 192–194 inadequate wetting conditions, 186–188 interfacial reactions, 188–191 liquid solder wettability, 185–186 protective finishes, 188–189 solderability performance of lead-tin alloys, 186 solderable finishes, 189–191 vapor phase heating, 193 wave soldering, 193–194 liquid solder interface reactions, 176 microstructures, 169–175 15Pb-85Sn example, 170–172 95Pb-5Sn example, 173–175 binary alloy phase diagram, 169–170 eutectic composition, 173 phase diagram, 169 nickel, interface reactions with, 179–180 palladium, interface reactions with, 181–182 physical, mechanical properties, 197–206 Coffin-Manson model, 202 computational modeling, 203–205 constitutive models, 203–204 corrosion resistance, 205–206 damage models, 204–205 fatigue, microstructural effects, 200–202 fatigue failure studies, 202–203 frequency-modified, Coffin-Manson equation, 202 monotonic strength properties, 199–200 physical properties, 197–199 plane strain levels, Coffin-Manson, 202–203 strain energy approach, 203 time-dependent deformation, 200 time-independent deformation, 199 silver, interface reactions with, 181–182 soft solders containing lead, tin, history of, 167 solid-state interface reactions, 176–179 tin as reactive constituent, 176 Micro vias issues, 563–567 Microbeam x-ray diffractometry, tin-whisker formation, 869–874
1000 Microelectromechanical systems, 751 Microelectronics packaging, 751–753 fatigue life of isotropically conductive adhesives joints, 753 high-frequency performance of isotropically conductive adhesives joints, 752–753 surface mount applications, 751–752 advantages, 752 CSP applications, 752 disadvantages, 752 Micron bump technology, nonconductive adhesives, 759–760 Microstructural stability, solders, 212 Military industry, lead-free solders utilization in, 27 MIL-M-38510, 6 Miniaturization, 496 Miniaturization issues, printed circuit boards, 557–558 Ministry of International Trade and Industry, 7, 156 Minor element additions, influence of, 798–802 MITI. See Ministry of International Trade and Industry Mixed technology, 678 MLCC. See Multilayer ceramic capacitor Mobility of copper, tin-silver solders, 242 Moisture sensitivity, 525, 710, 803 Monotonic strength properties, lead-tin soldering, 199–200 time-dependent deformation, 200 time-independent deformation, 199 MSW. See Municipal solid waste Multicomponent solder paste considerations, 798–799 Multilayer ceramic capacitors, 863, 907 Municipal solid waste, 85, 103, 116 combustors, 105 bottom residue, 105 stack emissions, 105 National Center for Manufacturing Sciences, 163, 287, 304, 665, 916 National Center for Manufacturing Sciences Project, 666–685 alloy selection, 716–717 BGA packages reliability comparison for fleXBGA package, 720–722 reliability comparison for PBGA package, 722–723 conclusions, 723–725 alloys, fatigue performance, 723–724 manufacturability, 724–725
INDEX [National Center for Manufacturing Sciences Project] recommendations for alloy selection, 725 down-selection process, 666–673 down-selected alloys for evaluation, 672–673 economics, 668 toxicology, 667–668 high-temperature fatigue resistant solder project, 715–725 manufacturability assessment, 717–720 80 lead UTQFP, 719–720 0805 chip resistors, 718–719 1206 chip resistor, 717–718 manufacturing trials, 673–678 follow-on assessment, 676–678 initial assessment, 673–676 mechanical properties of lead-free solders, 684 project conclusions, 684–685 project recommendations, 685 project objectives, 666 participants, 715–716 project organization, 666 reliability evaluation, BGA packages, 720–723 reliability trials, 678–684 reliability assessments, 683–684 surface mount thermal cycle testing, 678–682 through-hole thermal cycle testing, 682–683 vibration testing, 683 National Center for Manufacturing Systems, 301 National Center of Manufacturing and Science, 755 National Electronics Manufacturing Initiative, 8, 665, 726, 907, 916 National Institute of Standards and Technology, 163, 667, 716 National standards, lead use, 58–59 National Toxicology Program, 72 NCMS. See National Center for Manufacturing Sciences NEDO. See New Energy and Industrial Technology Development Organization Netherlands, electronic waste management, 133–135 Neurotransmitter release, effect of lead, 51 New Energy and Industrial Technology Development Organization, 156, 688 study by, 688
INDEX Newtonian, vs. non-Newtonian fluids, 500–501 Nickel contamination in crops, 58 in electronic assemblies, 99 health issues, 72–73 direct contact, 73 ingestion, 72 inhalation, 72 world reserves of, 13 Nickel-tin intermetallic phases in tin-silvercopper systems, 482–483 Nitrogen effect on reliability, yield, 586–587 flux reduction, 581 increased dross formation, 581 inert atmosphere, 575, 581–583 in lead-free reflow soldering, 583–585 double-sided reflow, 584 high-temperature soldering, 585 pastes, reflow profile, 583–584 role of nitrogen, 584 through-hole reflow, 584–585 nitrogen, effect on wetting temperature, 582–583 wetting of lead-free solders, 581–582 Nitrogen consumption, cost issues, 585 differences between surface mount, wave soldering, 585 reflow soldering, 585 wave soldering, 585 Nitrogen inerting, cost of, 581 No-clean, inerting emerges from, 569–570 Nokia, lead-free solders utilization in, 27 Nonconductive adhesives, 729, 759–762 3-D CSP application, 761 applications, 760–762 flip-chip applications, 760–761 micron bump technology, 759–760 NCAs vs. anisotropically conductive adhesives in flex circuits, 760 print heads, 760 smart labels, 761–762 SMT applications, 760 Nonwettable material, accumulation of, degradation, 957 Nortel, lead-free solders utilization in, 27 North America eco-marketing, 162–164 consortia, 163 corporate policies, 162–163 products, 163–164 initiatives in, 8 North American Electronics Manufacturing Initiative, 163
1001 Norway, electronic waste management, 135 Nucleation effects, tin pest, 931–934 Obsolete electronics, 84–85 Occupational exposure to lead, 3 Occupational Safety and Health Administration, 72 Oil, inert atmospheres, 569 Optoelectronic multichip modules, 751 Ores, resource extraction, 91–92 Organ systems, effects of lead on, 51 Organic laminate substrate materials, lead-tin soldering, 195 Organic salts, role of, 383 Organic solder preservative, 469 Organic solderability preservative, 435, 442–443, 593, 782 Organic tin, occupational exposure to, 3 Original equipment manufactures, 4 OSHA. See Occupational Safety and Health Administration Osteocalcin, effect of lead, 51 Oxide patches, on wetting, effect of, 371–372 Oxides, used for glass, lead usage, 2 Oxygen-free high-conductivity, 782 Package moisture sensitivity, 555 Packaging electronic circuits, 413 Pad definition type, 515 Palladium interface reactions with, 181–182 lead-tin system, interface reactions with, 181–182 world reserves of. 13 Panasonic lead reduction initiatives, 8 lead-free component conversion, 595–633 lead-free solders utilization in, 27 Paste particle size, effect of, 583–584 Paste transfer ratio, 531 Patented alloys, 24 Patents on lead-free solders, 22–23 PCB. See Printed circuit board Persistent, bioaccumulative toxic chemicals, 115 Personal digital assistants, 732 Phase system, degradation, effect on mechanical properties, 951–953 Phase transformation analog, stress relaxation, 220 Photolithographically defined vias, 558–559 Pigments, oxides used for, lead usage, 2 Pin grid array, 157 Pipes, lead usage, 2
1002 Plastic deformation history, effect of, 324 Plastic dual in-line package, 683 Plastic J-leaded chip carrier, 683 Plastic leaded chip carrier, 676 Plastic strain accommodation, 964–966 degradation phenomena, 964–966 Plated through-holes, 16, 281, 570 Platinum group metals, in electronic assemblies, 99–100 world reserves of, 13 Polybrominated biphenyls, 122 Polybrominated diphenyl ethers, 122 Polychlorinated biphenyl, 737 Polymer flip chip, 746 Polystyrene, 731 Polystyrene divinylbenzene, 740 Polyvinyl chloride, 105 Post-laser processing issues, 563 Potential lead-free solder impacts, 553 Power cycling test, 973 Pregnancy, effect of lead, 51 Preheat units, 544–545 Pressure cooker test, 736 Print heads, nonconductive adhesives, 760 Printability, 502 Printed circuit boards, 1, 141, 239, 274, 281, 286, 496, 507–520, 529, 569, 591, 709, 737, 833, 853, 859 deposition techniques, 509–514 I/O pad design, 514–520 lead-free finishes, 431–464 electroless plating, 432–433 electrolytic plating, 432 immersion plating, 433 issues with, 461–462 lead-free board finish criteria, 435 lead-free component finishes, 449–454 lead-free printed circuit board finishes, 434–449 manufacturability, 456–458 nickel-palladium, 453–454, 457–458 reliability, 458–462 solderability, 454–456 tin, pure, 454, 456 tin whisker phenomenon, 458–461 tin-bismuth, 453, 456 tin-copper, 457 tin-silver, 456–457 tin-copper, 453 tin-zinc, 457 types of finishes, 432–434 pad finishes, 509–514 process temperatures, effect of, 508–509
INDEX [Printed circuit boards] reinforcement materials, 509 utilizing build-up technology, 556–567 Printed wiring board, 7, 88, 110, 436, 444, 673, 676, 769 surface finishes, 803–805 immersion gold, 804–805 vs. electrolytic nickel, 803–804 Process atmosphere reactions, 806–807 cooling rates, effect of, 807 gas contaminants, effect of, 806 Process equipment, lead-free component conversion, 594 Product stewardship, 117–121 Products of incomplete combustion, 105 Protective finishes, lead-tin soldering, 188–189 Protein synthesis, effect of lead, 51 Pull test, 971 Purchasing trends, 150–151 cost savings, 150–151 eco-labels, 151–155 benefits, 152–154 organizations engaged in, 153 types of labels, 152–153 environmental concerns, move towards, 150 Environmental Management Market, 153 environmentally friendly products, procuring, 151 Europe, eco-marketing, 161–162 consortia, 161 corporate policies, 161 products, 161–162 Fujitsu, eco-marketing, 157 Global Ecolabelling Network, 153 green marketing, 155 Green Seal, 153 Hitachi, eco-marketing, 157 industry consensus, 151 International Organization for Standardization, 153 Japan, 155–160 consortia, 156 corporate policies, 156 products, 156–158 Matsushita, eco-marketing, 157–158 North America, eco-marketing, 162–164 consortia, 163 corporate policies, 162–163 products, 163–164 public vs. private sector, 150 selection guides, 151 U.S. Federal Trace Commission, 153
INDEX PWB. See Printed wiring board Pyrometallurgical roasting of ore, 92 Quad flat pack, 243, 599, 676 Raised plateaus, effect on paste activation, 583 Rapid dissolution, 475 Rate of energy reduction model, stress relaxation, 220 RCRA. See Resource Conservation and Recovery Act Reactions with copper pads, 484 Reactions with nickel/gold-plated pads, 484–489 Recrystallization, 963–964 degradation, 962–964 Recycling, 118–121 initiatives in, 7 producer responsibility, 118–119 scrap reuse, recycling, 120–121 waste streams prior to, 85 Redox reactions, 407–411 Reduced rosin content, 413–414 Reduction of hazardous substances, 863 Reflow oven, 593–594 enhancements, 610–612 Reflow soldering temperature profiles, 536–539 Reflow systems, implementing nitrogen in, 588 Reflowed lead-free solder or tin, 438 Regional perspectives, environmental stewardship, 115–149 Regulation of lead, 116–117. See also under specific regulation Reid Bill, 137–138 Relative humidity, 573 Relaxation, degradation, 962–964 Renal system, 52 effect of lead on, 51 Rensselaer Polytechnic Institute, 667 Replacement solder criteria, 281 Reporting thresholds, lead restrictions, United States, 138, 139 Reproductive system, effect of lead on, 51, 53 Residual oxygen level, 570 inert atmosphere, 572–573 Resource Conservation and Recovery Act, 139, 140 Resource extraction, 90–101 abundance, 92 energy consideration, 92–93 hydrometallurgy, 93
1003 [Resource extraction] ores, 91–92 pyrometallurgical roasting of ore, 92 reduction, 93 waste products, 93–94 Response to stresses, tin-silver solders, 241 Restriction of Hazardous Substances, 83, 121 Restriction on lead use, efforts towards, 1–2 Rheology, Newtonian vs. non-Newtonian fluids, 500–501 ROHS. See Restriction of Hazardous Substances Rosin mildly activated, 677, 717 Rosin-activation, 603 Rosin-based classification system, 389–390 Rosin-based fluxes, 383–390 Roughness, surface, effect of, 370 RPI. See Rensselaer Polytechnic Institute Sandia National Laboratories follow-up study, 685–687 Scanning electron microscopy, 264, 288, 371, 436, 459, 481, 599, 711, 839, 852, 868, 966 Second National Health and Nutrition Examination Survey (NHANES II), 53 Secondary particles, soft errors, degradation, 937–939 Self-alignment, 606–607 Semiconductors, degradation, 917–918 Sequential electrochemical reduction analysis, 803 Silicon-on-insulator, 941 Silver in electronic assemblies, 100 health issues, 70–71 direct contact, 71 inhalation, 71 regulation, 71 interface reactions with, 181–182 lead-tin system, interface reactions with, 181–182 regulation of, 57 soluble compounds, occupational exposure to, 3 world reserves of, 13 Silver dust, fume, occupational exposure to, 3 Sinkholes, 783–784 Slump test, 502–503 Small outline integrated circuit, 676 Smart labels, nonconductive adhesives, 761–762 Sodium metabolism, cardiac, effect of lead, 51
1004 Soft errors, 937 degradation, 937–950 alpha particles, 940–943 cosmic rays, 937–939 defined, 937 radiation, 937–943 secondary particles, 937–939 lead-free solders, 973 Solder. See also under specific metal balls, 551 test, 506–507 bismuth contamination, effects of, 549–550 bismuth-tin, 282–288 candidate alloys, 20–23 classification, 10 complexity, minimum, 18 copper dissolution, 547–549 degradation, 965–966 double-wave soldering, 546–547 driving forces for, 2–6 electromigration, 827–850 electronic assemblies, solders utilized for, 11 energy consumption, 553–554 eutectic tin-lead, lead-tin/metal, lead-free/ metal interfaces, intermetallic compounds, 472–480 on copper metallization, 472–474 gold in, 475–480 health-related aspects, 2–3 intermediate phases in, lead-tin/metal, lead-free/metal interfaces, intermetallic compounds, 480–489 iron contamination, 550 isothermal fatigue, 229 joint, flip chip pull test, 957 joint perfection, 496–497 joint pitch, tin-silver solders, 240 lead contamination, effects of, 549–550 lead-free wave, 546–554 lead-tin, 167–210, 417–419 15Pb-85Sn example, 170–172 95Pb-5Sn example, 173–175 attributes of lead-tin solders, 169 binary alloy phase diagram, 169–170 bulk solder, intermetallic compounds in, 182–183 ceramic substrate materials, 195–196 Coffin-Manson model, 202 computational modeling, 203–205 constitutive models, 203–204 controlled atmospheres, 192 corrosion resistance, 205–206 damage models, 204–205 electronic applications, 168
INDEX [Solder] eutectic composition, 173 fatigue, microstructural effects, 200–202 fatigue failure studies, 202–203 flux categories, 191–192 flux technology, 191–192 frequency-modified, Coffin-Manson equation, 202 function of flux, 191 furnace heating, 193 gold, interface reactions with, 181–182 hand soldering, 194 heating methods, 192–194 inadequate wetting conditions, 186–188 interconnection levels, 194–197 as interface reaction products, 175–176 interfacial reactions, 188–191 intermetallic compound formation, 175–176 iron, interface reactions with, 179–180 joints, flip chip pull test, 956 lead-tin solder joints, mechanical properties of, 183–184 level 1 interconnections, 194 level 2 interconnections, 194–196 level 3 interconnections, 196–197 liquid solder interface reactions, 176 liquid solder wettability, 185–186 microstructures, 169–175 monotonic strength properties, 199–200 nickel, interface reactions with, 179–180 organic laminate substrate materials, 195 package input/output materials, 194–195 palladium, interface reactions with, 181–182 phase diagram, 169 physical, mechanical properties, 197–206 physical properties, 197–199 plane strain levels, Coffin-Manson, 202–203 protective finishes, 188–189 silver, interface reactions with, 181–182 soft solders containing lead, tin, history of, 167 solderability performance of lead-tin alloys, 186 solderable finishes, 189–191 solid-state interface reactions, 176–179 strain energy approach, 203 time-dependent deformation, 200 time-independent deformation, 199 tin as reactive constituent, 176 vapor phase heating, 193 wave soldering, 193–194
INDEX [Solder] from lead-tin system, metallurgical properties, 167–210 market advantages, 4–5 mechanical properties, 5, 211–238 homologous temperature, 2111 melt temperature, 14–16 metallurgical complexity, minimum, 18–19 mixed technology, 545 nitrogen inerting, 577–581 activators in flux, 577–578 cleaning residues, 580 dross, 579–580 nitrogen inerting improves yields, 580–581 wetting, 578–579 paste, 497–507, 530–531 characteristics, 499–501 formulation, 498 powder particle size, 498–499 printing efficiencies, 499 tests, 501–507 patents on, 22–23 properties for operational requirements, 19–20 reflow, 539–542 carriers, 540 double side assembly issues, 540–541 forced convection heating, 539 infrared radiation, 539 metallurgical reactions, 541 solder joint structure, 541–542 rework, 552–553 selection criteria, 12–20 solder defects, 550–551 spreading, 331–430. See also Spreading standards, 6 supply, 13 technology, 26–28 tin-lead, 11 tin-silver, 239–280 tin-zinc, 292–294 toxicity, 12 traditional electronics-based solders, 10–12 underfill, 553 use of inert atmosphere, 547 wave machine material compatibility, 551–552 wettability, 16–18 wetting, 331–430. See also Wetting chemical reactions involving flux, 403–413 choosing flux, 413–414 definitions, 376–378 density, 352–354 diffusivity, 360–361
1005 [Solder] dissolution, 363–366 dynamic contact angles, 338–340 dynamics of, 361–376 flux application, 415–417 flux chemistry, 376–417 flux requirements, 378–379 flux types, 380 fluxes in experimental measurements, effect of, 343 fluxless soldering, 414–415 halogen-free organic fluxes, 390–401 history, 376 inert wetting vs. reactive wetting, 332–333 inorganic fluxes, 380–383 intermetallic compound formation on, effects of, 366–371 joining with lead-free solders, 415 lead-free wetting, 420–424 lead-tin solders, 417–419 major flux components, 379–380 no-lead solders, 417–424 organic (rosin-based fluxes), 383–390 orientation, 342 purpose, 378 quantifying, 342–352 sessile drop spreading dynamics, 347–352 solderability, 337–338 spreading, 331–430 static contact angles, 336–337 surface condition, effects of, 371–376 surface tension, 354–358 synthetic fluxes, 401–403 temperature, effect of, 361–363 temperature control, 342–343 test, on basis of manufacturing conditions, 417 thermodynamic treatment of, 340–342 viscosity, 358–360 wetting, definition of, 332 wetting balance method, 343–347 Solid waste disposal, 59–63 test methodology for, 74–76 analyses, 76 procedure, 74–76 Solidification, rapid, 369–370 Soluble threshold limit concentration, 78 Sony lead reduction initiatives, 8 lead-free soldering experience, 651–662 lead-free solders utilization in, 27 Spain, electronic waste management, 135 Spallation, degradation, 960
1006 Sperm morphology, count, effect of lead, 51 SPLP. See Synthetic precipitation leaching procedure Spontaneous abortions, effect of lead, 51 Spread tests, 503 Spreading high solubility on, effect of, 365–366 solder, 331–430 Spreading coefficient, 337 Stack emissions, municipal solid waste combustors, 105 Stacked intermediate compound layers of nicke, 476 Standard reduction potentials, 407 Standards, in lead-free technology, 6 Static random access memories, 937 Stencil printer, 531 Stencils, 530–531 Stick-slip motion, 372 Storage batteries, lead usage in, 2 Strain rate effect of, 220 flow stress, 222 Stress relaxation, solders, 219–220 phase transformation analog, 220 rate of energy reduction model, 220 Stress state, 460–461 Stress-strain relations, solders, 220–222 flow stress, 222 strain rate, effect of, 220 three strain components, 221–222 Structural difference hypothesis, 901 Structural glass, 509 Studies of lead-free solder, 665–728 IDEALS project, 695–715 alloys selected for investigation, 697 board, component finishes, 700 development of soldering materials, 700 humidity tests, 713–714 intermetallic compound growth, 714 large-scale process trials, 702–708 mechanical, physical properties, 698–699 preliminary trials, 702 project goals, 696–697 project organizations, participants, 695–696 property investigations, 697–700 recommendations, 714–715 reflow soldering, 708–710 reliability assessment, 710–714 rework trials, 710 solder joint rework, 710 solder paste development, 708 solderability, 697–698
INDEX [Studies of lead-free solder] solidification, aged structures, 699–700 temperature cycling, 711–712 test board, 710 test vehicles, 701–702 time-temperature process window, 708–710 vibration, shock, 712–713 wave soldering process studies, 700–708 Japan first commercial products, 687–688 JEIDA reliability evaluation, 689–692 JIEP project, 693 JWES method, materials evaluations, 692–693 lead-free solder roadmap in, 695 New Energy and Industrial Technology Development Organization study, 688 proliferation of products, 688 promotion of lead-free soldering, 687–688 research, development in, 687–695 National Center for Manufacturing Sciences Project, 666–685 80 lead UTQFP, 719–720 0805 chip resistors, 718–719 1206 chip resistor, 717–718 alloy selection, 716–717 alloys, fatigue performance, 723–724 conclusions, 723–725 down-selected alloys for evaluation, 672–673 down-selection process, 666–673 economics, 668 follow-on assessment, 676–678 high-temperature fatigue resistant solder project, 715–725 initial assessment, 673–676 manufacturability, 724–725 manufacturability assessment, 717–720 manufacturing trials, 673–678 mechanical properties of lead-free solders, 684 participants, 715–716 project conclusions, 684–685 project objectives, 666 project organization, 666 project recommendations, 685 recommendations for alloy selection, 725 reliability assessments, 683–684 reliability comparison for fleXBGA package, 720–722 reliability comparison for PBGA package, 722–723
INDEX [Studies of lead-free solder] reliability evaluation, BGA packages, 720–723 reliability trials, 678–684 reliability-related materials properties, 668–672 surface mount thermal cycle testing, 678–682 through-hole thermal cycle testing, 682–683 toxicology, 667–668 vibration testing, 683 Sandia National Laboratories follow-up study, 685–687 Superimposed hysteresis loops, 235 Supply chain, 594 Surface excess, concept of, 333–334 Surface insulation resistance, 389, 524, 581 Surface laminar circuitry, 557 Surface mount, 569, 592, 673, 758 applications, microelectronics packaging, 751–752 advantages, 752 CSP applications, 752 disadvantages, 752 components, 495, 497, 553 reliability test vehicle, 678 technology, 248, 281, 286, 435, 496, 584, 729 Surface roughness, 373–376 Surface segregation, intermetallic formation, coupling between, effect of, 371 Surface tension, 334 solder wetting, 354–358 surface oxides, effect of, 412–413 Surfactants, 379 Sweden electronic waste management, 135–136 environmental quality objectives, 126 Switzerland, electronic waste management, 136–137 Synchrotron radiation, tin-whisker formation, 869–874 Synergistic effect, lead-free component conversion, 593–594 Synthetic aids to lead elimination, 55 Synthetic fluxes, 401–403 Synthetic precipitation leaching procedure, 77 Tack tests, 503–506 Tackifiers, 379 Take-back initiatives, 7, 118–121 extended producer responsibility, 118–119 scrap reuse, recycling, 120–121 takeback schemes, 119–120
1007 Tape automated bonding, 511, 735 Target organs, heavy metals, 50–53 TCLP. See Toxicity characteristic leaching procedure Telecommunications industry, lead-free solders utilization in, 27 Temperature coefficient of resistivity, 917 Temperature hierarchy, degradation, 915 Temperatures, during electronics assembly, increase in, 102. See also Thermal Ternary elements, effect of, 422–423 Test conditions vs. industrial process conditions, 346–347 Texas Instruments, Incorporated, 8, 667 Thermal aging, effect of, 476–480, 782–784 Thermal cycling of surface mount test vehicles, 678 of through-hole test vehicles, 678 Thermal gradients, 831 Thermal gravimetrical analysis, 383 Thermal mechanical fatigue, 201, 211, 233, 665, 672 Thermal ratcheting, anisotropy, 926–929 Thermal stability, 523 activity, relationship between, 388–389 Thermally activated plastic flow, solders, 212–214 allotropic modification, 213 atomic level, 212 flow stress, 214 interconnections, brittle phases, 214 stresses, 212–213 Thermomechanical fatigue, solders, 233–236 high lead-low tin solder, 233 in joints, components, 235 lead-free solders, 233–234 solubility effects, 235–236 superimposed hysteresis loops, 235 Thermomigration, 827, 844–849 degradation, 961 in lead-indium alloy solder joints, 848–849 of solutes, 845–847 theory of, 844–849 threshold effects, 844–845 Thixotropic fluids, 501 Through-hole reliability test vehicle, 682 Tin allotropic change between materials classifications, 919 creep, 218 in electronic assemblies, 95 health issues, 73 ingestion, 73
1008 [Tin] inhalation, 73 regulation, 73 low solubility in, 306 organic, occupational exposure to, 3 regulation of, 57 world reserves of, 13 Tin pest, 929–936 allotropic transformation, 930–931 description, 929–931 history, 929 nucleation effects, 931–934 flip chip joint transformations, 933–934 nucleation rate, 932 nuclei formation, 931–932 reaction kinetics, 933 structure-limited deformation, 934–935 other factors, 935–936 preventative methods, 936 Tin-antimony solder, 288–290 application, 289–290 base metal dissolution, 289 benefits, 289 high antimony concentrations, effects of, 289 intermetallic growth, 289 mechanical properties, 289 microstructure, 288 utilization, 290 Tin-based lead-free alloys, 841–842 comparison to lead, 841 fast diffusers in tin, tin-based alloys, 842 testing, 841–842 Tin-based solder, degradation phenomena, 915–925 allotropic changes within metallic system, 918–919 comparison of solder systems, 919–925 materials classifications, 917–918 tin allotropic change between materials classifications, 919 Tin-copper lead finish, 453 Tin-copper solder, 290–292 applications, 292 flip-chip solder bumps, 292 creep, 292 mechanical properties, 291–292 microstructure, 290–291 tin pest, 291 Tin-indium solder, 294–296 applications, 296 cost, 294–295 properties, 295–296 creep, 295
INDEX Tin-lead system, solders from, 167–210 attributes of lead-tin solders, 169 bulk solder, intermetallic compounds in, 182–183 electronic applications, 168 gold, interface reactions with, 181–182 interconnection levels, 194–197 ceramic substrate materials, 195–196 level 1 interconnections, 194 level 2 interconnections, 194–196 level 3 interconnections, 196–197 organic laminate substrate materials, 195 package input/output materials, 194–195 intermetallic compound formation, 175–176 as interface reaction products, 175–176 lead-tin solder joints, mechanical properties of, 183–184 iron, interface reactions with, 179–180 lead-tin soldering, 185–194 controlled atmospheres, 192 flux categories, 191–192 flux technology, 191–192 function of flux, 191 furnace heating, 193 hand soldering, 194 heating methods, 192–194 inadequate wetting conditions, 186–188 interfacial reactions, 188–191 liquid solder wettability, 185–186 protective finishes, 188–189 solderability performance of lead-tin alloys, 186 solderable finishes, 189–191 vapor phase heating, 193 wave soldering, 193–194 liquid solder interface reactions, 176 microstructures, 169–175 15Pb-85Sn example, 170–172 95Pb-5Sn example, 173–175 binary alloy phase diagram, 169–170 eutectic composition, 173 phase diagram, 169 nickel, interface reactions with, 179–180 palladium, interface reactions with, 181–182 physical, mechanical properties, 197–206 Coffin-Manson model, 202 computational modeling, 203–205 constitutive models, 203–204 corrosion resistance, 205–206 damage models, 204–205 fatigue, microstructural effects, 200–202 fatigue failure studies, 202–203
INDEX [Tin-lead system, solders from] frequency-modified, Coffin-Manson equation, 202 monotonic strength properties, 199–200 physical properties, 197–199 plane strain levels, Coffin-Manson, 202–203 strain energy approach, 203 time-dependent deformation, 200 time-independent deformation, 199 silver, interface reactions with, 181–182 soft solders containing lead, tin, history of, 167 solid-state interface reactions, 176–179 tin as reactive constituent, 176 Tin-silver alloy, 788–793 eutectic, 218–219 Tin-silver lead finish, 453 Tin-silver solder, 239–280 aging, 243–233 high temperature stability, 244 interface intermetallic compounds, 244 temperature effect, 243 as-solidified microstructure, 241–242 compatibility, 239 copper dissolution, effect of, 242 die size, 240 effect of, heating rate, 242–243 growth kinetics, intermetallic compound, 244 example, 244 heating rate, 242–243 intermetallic compound layers, morphology, 242 joint current density, temperature, 240 localized microstructure coarsening, 243 mechanical properties, 245 melt temperature, 243 microstructure, 241–242 migration to lead-free solders, 239 mobility of copper, 242 response to stresses, 241 solder joint pitch, 240 stability, microstructural, 242 wetting characteristics, 245 atmosphere, effects of, 245 gold, effect of, 245 Tin-silver-antimony system, 249–250 effect on, melt temperature, 249 mechanical properties, 249–250 microstructure, 249 Tin-silver-bismuth system, 245–248, 791–792 bismuth, effect of, 246–247 low-melt constituents, 245–247
1009 [Tin-silver-bismuth system] mechanical properties, 247–248 creep resistance, 248 ductility, 247 strength, 247 melting point, effect on, 245 microstructure, 245 Tin-silver-bismuth-indium system, 248–249 applications, 248 bismuth, effect of, 248 indium, effect of, 248 mechanical properties, 248–249 microstructure, 248 optimizing composition, 248 silver, effect of, 248 Tin-silver-copper system, 252–271, 789–791 aging, reflow cycles, 261–267 as-aged solder ball structure, 261–262 as-reflowed solder ball microstructure, 261 cooling rate, effects of, 258–259 copper dissolution, rate, effects of, 259–260 creep deformation, 270–271 ductility, 268 eutectic phases, 254–256 microstructure, 253–258 cooling rate effect, 267–270 morphology, 256–258 multiple reflows, effect on tin systems, 262–267 negligible solubility, 253–254 silver content, plate formation, effect of, 259 solidification, 256 strain rate effects, 268–270 strength properties, 267–268 structures, 252–253 ternary concepts, 253 ternary eutectic composition, 253 Tin-silver-copper-antimony system, 275–276, 799–800 applications, 275 fatigue properties, 276 intermetallic compound growth rates, 275–276 mechanical properties, 276 plasticity, 276 strength, 276 toxicity, 275 Tin-silver-copper-bismuth system, 273–274 bismuth, effect on melting point, 273 mechanical properties, 273–274 Tin-silver-copper-boron system, 276–277 boron as microstructure refiner, 277 microstructural comparison, 277
1010 Tin-silver-copper-indium system, 273–275 applications, 274 elemental additions, effect on melt temperature, 274 mechanical properties, 274–275 microstructure, 274 Tin-silver-copper-indium-bismuth-antimony system, 800–801 Tin-silver-copper-lead system, 271–273 lead, effect on melt temperature, 271 low-cycle fatigue, 273 mechanical properties, 272–273 plasticity, 272–273 strength, 272 Tin-silver-indium system, 792–793 Tin-silver-X system, 239–280 Tin-silver-zinc system, 250–252 mechanical properties, 251 melting point depression, 250 microstructure, 250 minor zinc additions, effect of, 250 ternary additions, 250 zinc additions creep deformation, effect of, 251 strength, ductility, effect of, 251 wetting, 251–252 zinc reactivity, 250–251 Tin-whisker formation, 458–461, 851–914 cessation, whisker growth, 884–886 compressive stress, 896–901 cracked oxide theory, 896–904 conditions of tin whisker growth, 896 dislocation glide theory, 866 dislocation theories, 865–866, 868 early dislocation theories, 864 eutectic tin-copper finishes, focused ion beam images, 875–879 externally applied forces, effect on whisker growth rates, 864–865 focused ion beam microscopy, 874–879 kinetic model, 902–904 mass transport of tin, 904–907 radioactive tracer studies, 904–905 voids, 905–907 microbeam x-ray diffractometry, 869–874 microstructural analyses, 886 mitigation accelerated test considerations, 908 accelerated testing, 908–910 cracked oxide, 910–911 dislocation, 910 electromigration, 908–910 overview, 907–908 recrystallization, 910–911
INDEX [Tin-whisker formation] tin deposit type, 911 recrystallization, 880–896 tin-whisker growth kinetics, 884 reliability, 860–863 field problems, 860 industry practices to cope with, 860–863 recommendations, 863 slow growth rates of, 886 spontaneously grown whiskers, growth kinetics of, 884 structure, kinetics of, 851–914 studies, overview, 855–857 surface oxide, role of, 901 synchrotron radiation, 869–874 tin plating types, 857–860 bright tin, 858–859 fused tin, 859 immersion tin, 859 matte tin, 858 tin alloys, 860 tin with underlay, 859 two-stage dislocation models, 866–868 whisker base, whisker growth from, 863–864 whisker description, 854–855 whisker structures, microstructural analysis of, 886–893 Tin-zinc solder, 292–294 high activity metal, 293 interfacial compound formation, 293–294 base metallization, effect of, 294 mechanical properties, 294 melting point, replacement alloys based on, 292–293 microstructure, 292 utilization, 294 wettability, 293 Tin-zinc-bismuth system, 795–798 Tin-zinc-indium system, 793, 795 Tin-zinc-X system, 793–798 TMF. See Thermal mechanical fatigue Toshiba lead reduction initiatives, 8 lead-free solders utilization in, 27 Total threshold leaching concentration, 78 Total threshold limit concentration, 78 Toxic characteristic leaching procedure, 103 Toxic release inventory, 138–139 Toxicity characteristic leaching procedure, 65, 76–77, 139 extraction solution, 76–77
INDEX Toxicity test methods distilled water methods, 77–78 distilled water with salts methods, 78 interpretation of results, 78–79 soluble threshold limit concentration, 78 synthetic precipitation leaching procedure, 77 total threshold leaching concentration, 78 total threshold limit concentration, 78 toxicity characteristic leaching procedure, 76–77 extraction solution, 76–77 Transform infrared spectroscopy, 383 Transmission electron microscopy, 798, 875 Traps, lead usage, 2 TRI. See Toxic release inventory UBM. See Underbump metallurgy Ultrafine oxide dispersions, 309–310 Underbump metallurgy, 287, 292, 746, 783, 833–834, 837, 841, 946, 950 Underfill, effects of, degradation, 969–971 Underfill-like properties, alloys with, degradation, 970–971 Underwriters laboratories, 560 United Kingdom, electronic waste management, 137 United States consumption of lead in, 84 lead restrictions, 137–139 electronic waste management, 139–141 landfills, federal standards, 139 PBT-abased modifications, 139 Reid Bill, 137–138 reporting thresholds, 138, 139 toxic release inventory, 138–139 patents on lead-free solders, 22–23 state recycling programs, 139–141 California, 140 Connecticut, 140 Florida, 140 Massachusetts, 140 Minnesota, 140 New Jersey, 140 New York, 141 South Carolina, 141 Wisconsin, 141 United States Department of Transportation, 64 United States Environmental Protection Agency, 55, 60 United States government agencies, regulation by, 64
1011 USDOT. See United States Department of Transportation USEPA. See United States Environmental Protection Agency Vapor phase heating, lead-tin soldering, 193 Via designs, 515–517 Via-in-pad design, 517–519 Vibration testing of surface mount, 678 Video-cassette recorders, 688 Viscosity, 499–500 modifiers, 379 solder wetting, 358–360 temperature dependence of, 358–359 Visteon Automotive Systems lead-free in automotive systems, 640–645 lead-free solders utilization in, 27 VOC. See Volatile organic compound Voids in interconnections, 786–787 Volatile organic compounds, 581, 696 Waste from electronic equipment, 59–63, 85, 103, 116, 121 Austria, 130, 131 Belgium, 130–131 combustors, 105 bottom residue, 105 stack emissions, 105 Denmark, 131–132 Europe, 125–137 Finland, 131, 132 France, 131, 132 Germany, 131, 132 initiatives, 6–7 Italy, 131, 133 Japan, 141–145 key program elements, 141–145 lead-free drivers, 141 PC green label, 141–143 recycle focus, 141 landfills, 85 lead restrictions, 121 Netherlands, 131, 133–135 Norway, 131, 135 resource extraction, 93–94 Spain, 131, 135 Sweden, 131, 135–136 Switzerland, 131, 136–137 test methodology for, 74–76 analyses, 76 procedure, 74–76 United Kingdom, 131, 137 United States, 139–141 California, 140
1012 [Waste from electronic equipment] Connecticut, 140 Florida, 140 landfills, federal standards, 139 Massachusetts, 140 Minnesota, 140 New Jersey, 140 New York, 141 South Carolina, 141 state recycling programs, 139–141 Wisconsin, 141 Waste streams prior to recycling, 85 Water, contaminated, 3 heavy metals in, 57–63 Water versus alcohol based flux, 553 Wave former, 545 Wave solder dross formation, inert atmosphere, 571–572 dross, 571 health issues, 572 metal oxidation, 571 parameters affecting, 571–572 Wave soldering, 542–546 implementing nitrogen in, 587–588 lead-free solder temperature, 545 lead-tin soldering, 193–194 preheating, 544–545 solder wave configuration, 545–546 wave flux, 542–543 Wear coatings, 552 Wetting, solder, 331–430 definition of, 332 density, 352–354 diffusivity, 360–361 dissolution, 363–366 dynamic contact angles, 338–340 dynamics of, 361–376 flux chemistry, 376–417 application, 415–417 chemical reactions involving flux, 403–413 choosing flux, 413–414 definitions, 376–378 fluxless soldering, 414–415 halogen-free organic fluxes, 390–401 history, 376 inorganic fluxes, 380–383 joining with lead-free solders, 415 major flux components, 379–380 organic (rosin-based fluxes), 383–390 purpose and function, 378 requirements, 378–379 synthetic fluxes, 401–403 test, on basis of manufacturing conditions, 417
INDEX [Wetting, solder] types, 380 fluxes in experimental measurements, effect of, 343 inert wetting vs. reactive wetting, 332–333 intermetallic compound formation on, effects of, 366–371 no-lead solders, 417–424 lead-free wetting, 420–424 lead tin solders, 417–419 orientation, 342 quantifying, 342–352 sessile drop spreading dynamics, 347–352 solderability, 337–338 spreading, 332 static contact angles, 336–337 surface condition, effects of, 371–376 surface tension, 354–358 temperature, effect of, 361–363 temperature control, 342–343 thermodynamic treatment of, 340–342 viscosity, 358–360 wetting balance method, 343–347 Wetting balance curve, 343–345 Wetting characteristics, tin-silver solders, 245 atmosphere, effects of, 245 gold, effect of, 245 Wetting completely oxidized surfaces, 372–373 Wetting conditions, lead-tin soldering, 186–188 Whisker, tin, 851–914 cessation, whisker growth, 884–886 compressive stress, 896–901 cracked oxide theory, 896–904 conditions of tin whisker growth, 896 description, 854–855 dislocation glide theory, 866 dislocation theories, 865–868 early dislocation theories, 864 externally applied forces, effect on whisker growth rates, 864–865 focused ion beam microscopy, 874–879 grain orientation under, 871 kinetic model, 902–904 mass transport of tin, 904–907 radioactive tracer studies, 904–905 voids, 905–907 microbeam x-ray diffractometry (synchrotron radiation), 869–874 microstructural analyses, 886 mitigation accelerated testing, 908–910 cracked oxide, 910–911 dislocation, 910 electromigration, 908–910
INDEX [Whisker, tin] overview, 907–908 recrystallization, 910–911 tin deposit type, 911 recrystallization, 880–896 tin-whisker growth kinetics, 884 reliability, 860–863 field problems, 860 industry practices to cope with, 860–863 recommendations, 863 spontaneously grown whiskers, growth kinetics of, 884 structures, microstructural analysis of, 886–893 studies, overview, 855–857 surface oxide, role of, 901 tin plating types, 857–860 bright tin, 858–859 fused tin, 859 immersion tin, 859 matte tin, 858 tin alloys, 860 tin with underlay, 859 two-stage dislocation models, 866–868 whisker base, whisker growth from, 863–864 Whisker growth models, differences among, 884–885
1013 White tin, degradation, 924 WHO. See World Health Organization World Health Organization, 58 World reserves, metals in microelectronic assemblies, 13 XPS. See X-ray photoelectron spectroscopy X-ray diffraction, 880 X-ray diffractometry, microbeam, tin-whisker formation, 869–874 X-ray photoelectron spectroscopy, 294 ‘‘Young’’ lead, effect of, degradation, 948 Zero headspace extraction, 77 ZHE. See Zero headspace extraction Zinc contamination in crops, 58 in electronic assemblies, 100–101 health issues, 67–69 ingestion, 68–69 inhalation, 69 low toxic concern/regulation, 69 regulation of, 57 world reserves of, 13 Zinc oxide fume, occupational exposure to, 3
Biographies
Tom Baggio Panasonic Factory Automation. Tom is currently the engineering manager of the SMT and Micro-Jointing Product Engineering Team for Panasonic Factory Automation. Tom has been a member of PFA’s Product Engineering Team since 1995. He has been acting as the liaison for Panasonic, dispersing new lead-free developments with OEM customers, contract manufacturers, and vendor partners. Prior to joining Panasonic, Tom worked with AT&T as a process and development engineer at the Montgomery Works’ Printed Circuit Board Fabrication facility. During his more than 7 years of experience in PCB fabrication, Tom was involved with double-sided rigid and multilayer fabrication. While at AT&T, Tom co-developed a patented ‘‘Pre-Plate Cleaning Process’’ used in the dry film development process. An active member of IPC and SMTA, Tom is currently a member of the IPC CAMX Shop Floor Communication Standards Committee. Tom received his bachelor’s degree in Mechanical Engineering from Illinois Institute of Technology in 1987. Dennis Bernier is Chief Technology Officer for Kester Solder, a division of Northrop Grumman. Since 1971 with Kester, he has been responsible for product research and development, technical services, quality systems, safety and environment, and laboratory testing operations. For the 11 years prior to joining Kester, Mr. Bernier was product manager and technical director for Marshall Industries, a distributor of soldering materials and electronic components. He received his Bachelor of Science degree in Chemistry in 1967 from California State University. Graduate studies include courses in organic synthesis, environmental science, and the metallurgy of nonferrous metals. Mr. Bernier received his Master of Science degree in Project Management in 1997 from Keller Graduate School of Management. He is a member of the American Chemical Society and many electronic and advanced technology organizations. Peter Borgesen Dr. Peter Borgesen conducted graduate studies at CalTech but was awarded his Ph.D. in Physics from University of Aarhus, Denmark. After 4 years at a national laboratory in Germany, he joined the Materials Science Department at Cornell University in 1986. Eight years later, he came to Universal Instruments Corporation to build up a major research effort addressing almost all aspects of flip-chip technology and, later, a similar but smaller effort on automated optoelectronics packaging. He is currently the head of process research and working to expand this beyond 1st and 2nd level assembly and reliability to thermal management and other issues. A substantial part of this work is supported by a consortium of 20–40 companies from across the world.
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Sunglak Choi Dr. Choi received his BE degree in Metallurgical Engineering from the Sung Kyun Kwan University, Korea, and his M.S. and Ph.D. degrees in Materials Science from the Michigan State University, East Lansing, Michigan. Sunglak Choi is currently a Senior Engineer at Samsung Electronics in Korea. Before he joined Samsung Electronics, he was a research associate at the Department of Mechanical Engineering, Naval Postgraduate School. He has been involved in works on the mechanical behavior of solder joints in microelectronic packaging. His research interests include deformation characterization, failure mechanism, and reliability issues of electronic devices. He has published several papers in these areas. Woojin Choi—Senior Packaging Engineer–Intel Corporation, Arizona, U.S.A. Mr. Choi is involved in the advanced electronic packaging development for the next-generation microprocessor in the Intel Corporation. He is focusing on the lead-free C4 solder bump joints in the package for the high-speed microprocessors. Woojin Choi obtained a Ph.D. at the University of California, Los Angeles, majoring in Materials Science and Engineering in 2002, and obtained M.S. and B.S. at the Department of Ceramic Engineering at Yonsei University in Seoul, Korea. Richard Chromik Dr. Richard Chromik received an M.S. in Physics in 1997 and completed his Ph.D. in Chemical Physics in 2001. Both degrees were granted by SUNY-Binghamton. His research there focused on characterizing phase transformations in systems of reduced dimension, such as solder/ metal diffusion couples and multilayered thin films of nanometer length scales. He is currently a postdoctoral investigator at Lehigh University studying the mechanical behavior of both Pb-free solder joints and alloyed thin films for MEMS applications. Eric J. Cotts Professor Eric J. Cotts received a Ph.D. in Condensed Matter Physics from the University of Illinois in 1983. After serving as a Research Fellow in Materials Science at the California Institute of Technology, he joined the Physics faculty at the University of Binghamton-SUNY in 1987, where he is now co-director of the Materials Science Program. Cotts studies transport phenomena at small length scales, focusing on fundamental problems of direct relevance to microelectronics and electronic packaging. Steven O. Dunford Steven O. Dunford is a Research Specialist at Nokia Research Center, Irving, Texas. His responsibilities include board-level reliability evaluation of and process development for Pb-free solders and other advanced technology programs. Prior to joining Nokia, he was instrumental in process development for the implementation of area array packaging (BGAs, CSPs) in high reliability military applications at Texas Instruments and Raytheon Circuit Card Assembly operations. His experience also includes process engineering and manufacturing of structural composites for survivability in high-temperature environments. His work in support of TI’s quality improvement objectives was recognized in 1987 with the Missile Systems Quality/Excellence Award in TI’s Business Development division and, in 1993, TI’s Defense Systems and Electronic Group-Site Quality Award for Excellence. In 2001, he received the Dr. George Kozmetsky Award for academic excellence, from the IC2 Institute at the University of Texas in Austin. He has been blessed with a wonderful family and looks forward to time spent with them. His formal education includes a Master of Science in Science and Technology Commercialization, from the University of Texas in Austin and a B.S. in Industrial Engineering from New Mexico State University. Morris E. Fine is Professor Emeritus of Materials Science and Engineering and Member of the Graduate Faculty at Northwestern University. Prior to emeritus status, he was Walter P. Murphy and Technological Institute Professor. In his long career, he has been principal advisor to 69 students who have received their Ph.D. degrees, with the most recent finished in early June 2002. The main threads of his research over the years have been precipitation strengthening and alloy development of metals and ceramics including tin-free solders ca. 1942 and lead-free solders. His research on solders has covered a 60-year period. He has performed extensive studies on precipitation-strengthened, Al-based alloys for
BIOGRAPHIES
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which he received the Douglas Gold Medal from AIME. His current research is on alloys with nanosize precipitates. After receiving his Ph.D. at the University of Minnesota in 1943, he joined the Manhattan Project at the University of Chicago and Los Alamos. Professor Fine came to Northwestern University in 1954, after spending 9 years at Bell Labs in Murray Hill, New Jersey. He joined the faculty of a new metallurgy department. Under his leadership as chairman, this department soon broadened to materials science becoming the first such department. Professor Fine has received many awards for his research and other contributions. These include five gold medals including the Mehl/Institute of Metals Lecture gold medal in 1995. He gave the ASM Campbell Memorial Lecture in 1979. He is an honorary member of AIME and the Japan Institute of Metals, Fellow of four societies, and member of the National Academy of Engineering (1973). He was elected Fellow of the American Academy of Arts and Sciences in the spring of 2003. George T. Galyon—Senior Technical Staff Member/IBM Systems Group–Poughkeepsie, New York Dr. Galyon is currently with the Product Packaging and Cooling Group in IBM’s System Group where he is a technical team leader in the Materials and Process Engineering Department and the chairman of the lead elimination committee for IBM’s Systems Group. Prior to these assignments, Dr. Galyon was the manager of the Materials Laboratory for the IBM Data Systems Division for 18 years. Before joining the Data Systems Division of IBM, Dr. Galyon was a manager and engineer at the IBM Microelectronic Division where he specialized in thin films, insulation technology, diffusion, epitaxial growth, and photoresist technologies. Dr. Galyon received his Ph.D. in Electronic Materials from the Massachusetts Institute of Technology in 1970, his Master’s Degree in Metallurgy and Materials Science from the University of Pennsylvania in 1963, and his Bachelors Degree in Metallurgical Engineering from Lehigh University in 1961. Dr. Galyon is the current chairman of the National Electrical Manufacturer’s Initiative (NEMI) whisker modeling and user group committees. Frank W. Gayle Dr. Frank W. Gayle currently serves as deputy chief of the Metallurgy Division in the NIST Materials Science and Engineering Laboratory (MSEL) and as leader of the Division’s Materials Structure and Characterization Group. His work at NIST has covered a range of research addressing metals characterization and structure–property relationships. His recent work has focused on materials issues in microelectronics interconnects, and he is the leader of the Materials for Microand Optoelectronics Program covering the ceramics, metallurgy, polymers and materials reliability divisions within MSEL. He is also leading the team of experts addressing the steel forensics aspects of NIST’s investigation of the World Trade Center collapses, evaluating steel recovered from the WTC site to determine its quality, mechanical properties, and behavior under impact and high-temperature conditions. Dr. Gayle holds a Doctor of Science degree in Metallurgy from the Massachusetts Institute of Technology (1985). He also earned a Bachelor of Science in Civil Engineering (1975) and a Master of Science in Materials Science (1976) from Duke University. Dr. Gayle spent 11 years in industry at Pratt & Whitney Aircraft and Reynolds Metals Company in the field of alloy development for aerospace applications prior to coming to NIST. Fu Guo Dr. Fu Guo is currently working on the transport property measurement of advanced thermoelectric materials in the Electronic Materials Pulsed Laser Deposition and Transport Characterization Laboratory at Michigan State University. His current research work involves operation and maintenance of the computer-controlled measurement system, which enables the measurement of the temperature-dependent (4.2–800 K) four-probe electrical conductivity, thermoelectric power, Hall effect, and thermal conductivity. His current work is also focused on the fabrication and testing of thermoelectric modules with materials suited for high-temperature operation (f700 K) and materials for low-temperature operation (f200 K). Dr. Fu Guo received his Ph.D. in Materials Science in 2001 from Michigan State University. His doctoral thesis was on the solderability, reliability/failure issues (such as mechanical properties, creep resistance, and thermomechanical fatigue resistance), as well as microstructural characterization and analysis of aging and reflow properties of composite lead-free solders prepared by mechanical mixing method. Dr. Subramanian was a co-advisor in his doctoral program. Dr. Guo has published more than 10 papers on lead-free solders with Dr. Subramanian.
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Even after his graduation, he is still active in publishing papers based on solder studies with Dr. Subramanian. He has also presented several papers in the national meetings of TMS. Dr. Guo received the Highly Commended Paper Award of Soldering and Surface Mount Technology from Literati Club (U.K.) in 2002 for a paper he published with Dr. Subramanian. He received the Most Outstanding Graduate Student Award from the College of Engineering at Michigan State University in 2001. He is a TMS and ASM member. Carol Handwerker Carol Handwerker—Chief, Metallurgy Division–National Institute of Standards and Technology, Gaithersburg, Maryland. In her role as division chief, she leads a staff of approximately 80 scientists and administrative staff members (f40 full-time government employees and 40 guest scientists, research associates, and contractors) in technical programs aimed at developing the materials measurement and standards infrastructure needed in technological areas important to U.S. industrial competitiveness. Dr. Handwerker has directed the Metallurgy Division’s Microelectronics Program since 1992; these projects include research in lead-free solders, high-temperature, high-fatigue-resistant solders, electrodeposited copper for on-chip interconnection, modeling for solder joint design, interconnects to gallium nitride, and solderability measurements for component leads and PWBs. Dr. Handwerker’s major research in the electronic packaging program has been in lead-free solders for electronic assembly. She has actively participated in national and international activities regarding the implementation of lead-free solders in electronics manufacturing, including most recently the NEMI Lead-Free Solder Task Force. Dr. Handwerker received a B.A. in Art History from Wellesley College, an S.B. in Materials Science and Engineering, and S.M. and Sc.D. degrees in Ceramics Science from the Massachusetts Institute of Technology. Dr. Handwerker joined NIST (formerly the National Bureau of Standards) upon completion of her Sc.D. in 1984 and served as staff member and group leader before becoming division chief in 1996. Jasvir (Jesse) S. Jaspal—Senior Technical Staff Member–IBM Microelectronics, East Fishkill, New York. Mr. Jaspal is the manager of Packaging Product Assurance and is responsible for the reliability performance of packaged products produced on site. Prior to working in packaging, he spent the first 15 years of his career working in failure analysis and semiconductor reliability engineering. He has published numerous papers and has co-authored three other book chapters. Jesse received a B.S. in Metallurgical Engineering from the Indian Institute of Technology, Bombay, India, and a M.S. in Materials Science from Carnegie Institute of Technology, Pittsburgh, Pennsylvania. Minna Juuti—EMEA Environmental Affairs Program Manager–IBM, Stockholm, Sweden. Ms. Juuti is working with various pan-EMEA environmental projects. Her current focus is to build internal WEEE (the European Union Directive on Waste Electrical and Electronic Equipment) processes, coordinate implementation of product take back in EMEA, and cooperate externally to communicate an industry-preferred model. Before joining IBM, Minna gained experience in environmental affairs, specifically in the food and pharmaceutical industry sectors, working in Finland and United States. Minna holds a masters degree in Engineering and a major in Environmental Engineering. Minna graduated from Helsinki University of Technology in Finland in 1996 and is, at present, studying for her Master of Business Administration at The Henley Management College. Sung K. Kang received the B.S. degree in Metallurgical Engineering from the Seoul National University, Seoul, Korea, in 1969 and the Ph.D. degree in Materials Science from the University of Pennsylvania in 1973. He was a research scientist at the Carnegie Mellon University and also at the Nova Scotia Technical University, Canada. He taught at the Stevens Institute of Technology, New Jersey. He was a senior scientist at the INCO R&D Center, New York. In 1984, he joined IBM T.J. Watson Research Center, where he has been working on various research and development projects related to microelectronic packaging technologies. Dr. Kang was the chair of the Microelectronics Interconnections and Assembly Committee, ASM International, from 1989 to 1991. He has organized an annual symposium on Microelectronic Packaging Materials at the TMS meetings from 1988 to 2002. He is currently the chair of the Electronic Packaging and Interconnection Materials Committee, TMS.
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Stephen J. Kilpatrick Dr. Stephen J. Kilpatrick—Physical Scientist—U.S. Army Research Laboratory, Adelphi, Maryland. Dr. Kilpatrick is currently involved in research on contacts and passivation layers for GaN wide bandgap devices needed for high-temperature/high-power/high-frequency applications. Before joining the ARL, he worked as a development engineer for IBM Microelectronics at their Hopewell Junction, New York R&D center, serving as program manager for their Pb-free C4 development effort. Previously, he worked at their Essex Junction, Vermont site on process development for IBM’s 0.24-Am SiGe BiCMOS mixed-signal RF technology. He has also worked at Princeton University’s Plasma Physics Laboratory as a member of the Diagnostics Division of the Tokamak Fusion Test Reactor project, focusing on edge plasma diagnostics and research on plasma-materials interactions. After a B.A. in Physics from Gordon College, he received his M.S. from the University of Wisconsin–Madison and his Ph.D. from Lehigh University, both in Materials Science and Engineering. His doctoral studies were focused on the low-temperature oxidation behavior of silicon germanium thin films, and in 1995, he received an AVS Graduate Research Award and was a finalist for the AVS Russell and Sigurd Varian Fellowship. His other research interests include MEMS processing, diamond layers and devices, thin film and interfacial phenomena, and semiconductor–super conductor interactions, and he has expertise in surface analysis by AES and XPS. Dr. Kilpatrick has over 70 publications. He may be reached at his E-mail address, [email protected]. Robert Kinyanjui Mr. Robert K Kinyanjui is a Ph.D. student in the Materials Science Program at the State University of New York in Binghamton. Mr. Kinyanjui obtained his Bachelor and M.Sc. degrees from Egerton University in Kenya. He also has an M.S. degree in Physics from Binghamton University. His principal area of research for the M.S. degree was the thermodynamics and kinetics of solid-state reactions in Sn(Au)/Ni and Pb–Sn(Au)/Ni diffusion couples. He is currently investigating the effect of processing techniques on the ensuing microstructure of Pb and Pb-free solder alloys. Jorma Kivilahti Professor Jorma Kivilahti received his M.Sc. and D.Sc. degrees in Materials Science and Engineering from Helsinki University of Technology (HUT). After a few years’ period of research and development work in industry, he returned to the university where he has been heading the laboratory of Electronics Production Technology as well as the Graduate School of Electronics Manufacturing, both in the department of Electrical and Communications Engineering at HUT. His R&D work covers new environmentally benign materials and the integration of electronics and photonics with low-cost manufacturing processes. In his scientific research, the emphasis is on the physical and chemical compatibility of dissimilar materials controlling the reliability of electronics and photonics. He has published over 200 scientific and technological papers, possesses several patents in the field of electronics manufacturing, given numerous keynote and invited lectures, and received several best paper awards with his colleagues in the fields of materials and manufacturing technologies. He has been appointed to Advanced Research Fellow of Academy of Finland and acted as a tutoring professor in Finnish electronics industry. He is a member of advisory committees and a reviewer of international journals in materials science. He is also a member of the National Research Centre of Excellence in Tissue Engineering and Biomaterials in which position he can dedicate himself to biomaterials and wireless biosensing research. He has received the Order of the White Rose of Finland for his contributions to Finnish electronics industry. Erik E. de Kluizenaar Dr. Erik E. de Kluizenaar—Materials Scientist in Electronic Interconnection– Philips CFT, Electronics Packaging & Assembly, Eindhoven, The Netherlands. Dr. De Kluizenaar is involved with soldering research and technology development, quality, and reliability of soldered joints since 1978 when he joined the Soldering Group of R.J. Klein Wassink in Philips CFT. Lead-free soldering is a major field of work for as long as 10 years and is ongoing. He was a participant in the BRITE/EURAM ‘‘IDEALS’’ project. Topics of research and development were development of leadfree soldering processes, alloys and components, development and standardization of solderability tests for surface mount components and printed boards, the root cause of solder dewetting, metallurgical aspects of soldering and soldered joints, solder fatigue, damage to components by soldering processes, co-development of new components and modules, failure analysis, and many other quality
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and reliability aspects of circuit technology interconnection. Previously, he was with Philips Research for 15 years and focused on surface science research and materials characterization, applying the usual analytical techniques such as ellipsometry, AES-analysis, SIMS, x-ray diffraction, metallography, optical microscopy, and SEM-microprobe. From 1989 to 1996, he was the secretary of IEC TC50 WG16: ‘‘Soldering,’’ an international IEC working group responsible for the standardized IEC solderability tests, and a member of the Dutch standardization committee NEC 104. He is the chairman of the Dutch working group ‘‘Soldering’’ of the Bond voor Materialenkennis (Association for Materials Science) and a member of the Dutch (and European) Associations for Microscopy. He has given innumerous presentations in conferences, workshops, and courses worldwide, published about 40 scientific and technical articles, a book (in Dutch), and a scientific film. Taek-Yeong Lee Assistant Professor, Materials Engineering, Hanbat National University, Daejeon, Korea (South). In 2001, he received a Ph.D. in Material Science and Engineering, from University of California, Los Angeles (UCLA), U.S.A. His thesis was ‘‘Electromigration and Solid State Aging of Flip Chip Solder Joints and Analysis of Sn Whisker on Lead-frame.’’ After finishing his degree, he joined Bell Labs, Lucent Technologies, New Jersey, for 1 year as a post-doctoral fellow. The research was focused on high-frequency applications and the thermal analysis of high-power chips both involving flip-chip solder joints. He then joined the faculty at Hanbat National University in Korea. Currently, he is a member of Center of Electronic Packaging Materials (CEPM) funded by Korea Science and Engineering Foundation (KOSEF). His main research topics are Pb-free solder, electromigration of flip-chip solder joints, tin whiskers, and Sn-pest-related matters. J.R. (Jim) Lloyd Dr. Lloyd is a Research Staff Member at IBM’s T.J. Watson Research Center in Yorktown Heights, New York. His specialty is reliability physics and has concentrated in metallization degradation, principally electromigration and stress voiding on semiconductor devices and packaging applications. Prior to his joining IBM Research Division, he worked at Jet Propulsion Laboratory in Pasadena, California, Digital Equipment Corporation in Hudson, Massachusetts, and IBM Microelectronics Division in East Fishkill, New York. He also spent a year as a visiting scientist at MaxPlanck-Institut in Stuttgart, Germany. For several years, he ran a consulting firm, Lloyd Technology Associates, where he worked with clients worldwide in a wide variety of reliability problems. He has published extensively in the literature and has often appeared as an invited speaker and lecturer in international symposia and workshops. Dr. Lloyd earned his Ph.D. at Stevens Institute of Technology in 1978 working with Prof. Milton Ohring and Dr. Shohei Nakahara. He is an avid private pilot, and in 1986, he reenacted the first flight across the United States in an ultralight replica of the Vin Fiz, a Wright Flyer. Daoquiang Lu Dr. Daoquiang Lu is a Senior Packaging Engineer at Component Research Group of Intel Corporation. He received the M.S. degree in Polymer Science and Engineering and the Ph.D. degree in Materials Science and Engineering from Georgia Institute of Technology in 1996 and 2000, respectively. Prior to joining Intel, Dr. Lu worked for electronic packaging materials group in National Starch and Chemical Company, Electronics Materials Division of Amoco Company, and the Optoelectronics Center of Lucent Technology. Dr. Lu has extensive experience in polymeric materials (such as conductive adhesives for solder replacement, epoxy molding compounds, and flip-chip underfill materials) for electronic packaging applications and materials/processes for optoelectronics applications. Dr. Lu received many awards including ‘‘Best Graduate Student of the Year of Georgia Tech Packaging Research Center’’ in 2000, ‘‘Best Paper of the Session’’ of International Symposium and Exhibition on Advanced Packaging Materials in 2000, ‘‘Motorola-IEEE/CPMT graduate student fellowship for research on electronic packaging’’ in June 1999, and Intel Divisional Recognition Award in 2002. Dr. Lu published more than 40 technical papers in technical journals and conference proceedings. Dr. Lu wrote chapters for three books and holds one U.S. patent and has eight pending patent applications. Dr. Lu is a member of IEEE, IMAPS, and SPE, and currently, he is the publicity chair of IEEE CPMT Phoenix chapter.
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Stephan J. Meschter—Senior Principal Hardware Design, BAE Systems Platform Solutions, Johnson City, New York. Dr. Meschter is the supervisor for the Failure Analysis Laboratories at the BAE Platform Solutions Johnson City, New York and Fort Wayne, Indiana facilities. Dr. Meschter has nearly 20 years of electronic packaging experience in high-reliability industrial, avionic, and space products. In conjunction with his component failure analysis work, he performs mechanical characterization and durability testing of advanced electronic packages, such as ball grid arrays and plastic encapsulated microcircuits. He is also conducting research in the area of wetting and spreading in hightemperature systems at the SUNY Binghamton Mechanical Engineering Materials Processing Laboratory. Dr. Meschter is a member of The Minerals, Metals and Materials Society. He received his BSME (1984) from the University of Hartford, Hartford, Connecticut, and his MSME (1987) and Ph.D. ME (2001) degrees from State University of New York, Binghamton, New York. Susanna Pelzel Susanna Pelzel is an Italian lawyer who graduated at the University of Ferrara, Faculty of Law (Italy) and qualified at the Bar of Venice (Italy). At the time of contributing to this publication, Susanna was practicing as an associate in the Brussels office of the American law firm Hunton & Williams as member of the firm’s Administrative Law Group. Susanna’s practice encompasses assistance to international companies and trade associations on environmental compliance, in particular, European legislation affecting electronics, batteries, take-back regulations, and shipment of electronic waste. Prior to joining Hunton & Williams, Susanna worked as an intern at the Commission to the European Communities (Brussels) and at the UNHCR Brussels Representation Office. As from April 2001, Susanna has relocated in Italy, at Padova, where she is practicing as a self-employed lawyer. Anthony A. Primavera Anthony Primavera is a senior process research engineer in the surface mount laboratory at Universal Instruments Corporation. He is part of a group at Universal focused on assembly process development and has specialized in ultrafine pitch mass reflow, stencil technology, TAB, lead-free solder, CSP, BGA, and DCA technology. He is currently managing a multicompany industrial consortium focused on chip scale packaging and flip-chip technology. He received a M.S. and Ph.D. degree in Mechanical Engineering from the State University of New York at Binghamton. He has authored many journal papers, conference papers, and regularly gives technology presentations on BGA, CSP, and DCA assembly. Karl J. Puttlitz Karl Puttlitz is a Senior Technical Staff Member with the IBM Corporate Staff as the program manager of the Corporate Lead (Pb) Elimination/Reduction Program. He has been involved with the design, development, and evaluation of interconnections utilized in microelectronic packages since the early 1960s. He played an integral role in the development and evaluation of flip-chip technology also known as C4 technology since its inception to the present. His early activities also included the areas of thick films, electroless plating, component bonding, and flip-chip attachment and replacement technologies, many still practiced by IBM and the industry. Karl was instrumental in the development of IBM’s ceramic ball and column grid array (CBGA/CCGA) interconnection and rework technology. He worked with product connector manufacturers to facilitate the availability and compatibility of those connectors with ceramic land grid array (CLGA) chip carriers and co-authored the test regime adopted as a national standard for benchmarking. He received a Ph.D. degree in Metallurgy from Michigan State University, published numerous papers (one of which earned him a CHMT Transactions Prize Paper Award), and credited with over 40 published inventions and patents. Karl is frequently invited to give workshops related to electronic packaging and authored/co-edited ‘‘The Area Array Technology Handbook’’ and a book chapter. His professional memberships include IEEE/CHMT, SAE, AWS, NACE, ASTM, Sigma Xi, Phi Lambda Tau, New York Academy of Sciences, and is a Fellow of ASM International and IEEE. He has biographical citations in American Men and Women in Science, Who’s Who in Science and Engineering, and Who’s Who in America in recognition of his accomplishments. He was awarded the SRC Outstanding Industrial Mentor Award in Electronic Packaging Sciences for his work with the academic community.
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Armin Rahn Armin Rahn—Principal–Rahn-Tec Consultants in Canada and Germany. Armin’s experience in the electronics assembly and soldering process started with industry employment as VP of R&D and Design Engineering with Electrovert in the 1980s. For the last 15 years, he has headed his own consulting firm, which holds public seminars worldwide and consults in companies on problem solving, production improvement, and cost reduction. With over 100 technical publications on the subject of joining technology, Dr. Rahn recently published his book: ‘‘The Basics of Soldering’’ with Wiley-Interscience. Dr. Rahn holds a number of important patents in this field, one of which received the coveted Canadian Export Award. Dr. Rahn is also a well-known speaker at such Conferences as Nepcon West, APEX, and SMTI and has chaired many important technical sessions on four of the five continents. Dr. Rahn holds a bachelor’s and a master’s degree in mathematics, physics, and economics from the Alberts-Ludwigs University in Freiburg, Germany. Armin Rahn received his Ph.D. from the University of Toronto in Toronto, Canada. Rob Schetty Rob Schetty—Technic Inc., Technic Advanced Technology Division, Plainview, New York, U.S.A. Rob Schetty is a VP for Technic Inc. where he has responsibility for worldwide plating chemical sales, marketing, and technology implementation for the Technic Advanced Technology Division. Rob received his Bachelor of Science degree in Chemical Engineering from the University of Pennsylvania, Philadelphia, Pennsylvania, U.S.A. Rob has been with Technic since early 2001 after spending 15 years in various positions at other suppliers, including R&D, a multiyear assignment in Asia, and various senior management positions. Rob has expertise in many aspects of electronics manufacturing and holds several patents related to high-speed electroplating. In addition, Rob has published nearly 20 papers related to electronic and industrial metals plating and has presented at a multitude of international industry conferences and seminars. Timothy J. Singler—Associate Professor of Mechanical and Materials Engineering, The State University of New York at Binghamton, Binghamton, New York. Dr. Singler is director of the Microflow Laboratory and the Materials Processing Laboratory at SUNY. He teaches undergraduate and graduate level courses in transport science, materials science, and engineering mathematics. He is presently conducting research in the areas of wetting and spreading in hightemperature systems, interfacial stability, flows of dense suspensions, and microfluidics. Dr. Singler was an NSF/NRC Research Associate at the Space Science Laboratory at the NASA Marshall Space Flight Center as well as a senior research scientist at the Franklin Research Center of the Franklin Institute. He is an active member of the American Physical Society and the American Society of Mechanical Engineers. He received his B.S. (1977), M.S. (1978), and Ph.D. (1983) degrees in Mechanical and Aerospace Sciences from the University of Rochester. Edwin B. Smith III Edwin B. Smith III—Operations Manager, Hart InterCivic, Lafayette, Colorado. Mr. Smith manages all tangible aspects of election system fulfillment, including health, safety, and environment. Before joining Hart InterCivic, Mr. Smith was Senior Director of Operations for K*TEC Electronics, directing both the manufacturing and engineering functions for this electronic manufacturing services provider. Mr. Smith has a Bachelor of Science degree in Mechanical Engineering Technology from Texas A&M University. He has presented over 20 technical papers, teaches classes in quality improvement techniques, is an American Society for Quality Certified Quality Manager and Auditor, and has held chapter level leadership positions in various professional societies. James Spalik—Analytical Chemist–retired. Dr. Spalik joined IBM, Endicott in 1985 and served as a scientist/engineer for 17 years, being involved in materials engineering development, failure analysis, and advanced process design. He has several flux composition and soldering method patents as well as patents for polymer adhesion improvement and chip cleaning. He received an award for one flux composition patent that was ranked in the top 5% of the Microelectronics Division 1997 most valuable patents. He is also the author of a chapter, ‘‘Bulk Analysis in Electronic Packaging,’’ in Principles of Electronic Packaging (McGraw-Hill, New York, 1989).
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Before joining IBM, Dr. Spalik taught several chemistry and computer programming courses at Broome Community College, including analytical chemistry (instrumental analysis), over a period of 20 years and was chairman of the Chemistry and Chemical Engineering Technology Department for 7 years. He received a Master of Science (Engineering Science) from Clarkson College of Technology at Potsdam, New York in 1972 and his Doctoral Degree from SUNY at Binghamton in 1989. Kathleen A. Stalter—Client Sales Manager–IBM Technology Group, East Fishkill, New York. Kathleen is the North American Sales and Support Manager for OEM Packaging supporting the Microelectronics Division at IBM Corporation. She has 20 years of experience in microelectronics process and product development, applications, and sales. Previously, Kathleen was a program manager for lead-free technology in the Microelectronics Division at IBM as part of IBM’s Corporate Lead Elimination/Reduction core team. Kathleen has also managed OEM Systems in the Design, Applications and Engineering Department for multilayer ceramics. She worked for 13 years in microelectronics interconnection assembly developing new processes for flip-chip join and repair as well as second level (BGA, CGA) interconnections. Many of her rework innovations are currently practiced in the manufacture of multichip modules utilized in IBM’s cost-performance and e-Server systems. She has several publications, including an ISHM prized paper award and 31 U.S. and foreign patents in the area of interconnection and assembly technology. Prior to joining IBM, Kathleen received a B.S. degree in Materials Engineering from Rensselaer Polytechnic Institute, Troy, New York. K.N. Subramanian Dr. K.N. Subramanian—University Distinguished Professor of Materials Science at Michigan State University, East Lansing, Michigan. His research interests have included areas such as mechanical properties of materials, crystal growth, crystallization of glasses, erosion, work hardening, fatigue and fracture, growth and properties of two-phase bicrystals, phase separation and crystallization in glasses, properties of partially crystallized glasses, fracture behavior of cruciate ligaments in dog, mechanical properties of spinodal alloys, composites, laser-induced damage in materials, lead-free solders for electronic applications, and inorganic–organic hybrid polymeric nanocomposites. He has more than 100 papers based on his studies published in peer reviewed scientific journals, among which about 40 are in the area of lead-free electronic solders. He has been active in the development of lead-free electronic solders, especially for severe service environments such as automotive under-the-hood applications, using composite approach over the last 6 years. He leads an active lead-free electronic solder research group at Michigan State University. His group has presented numerous papers on this topic at national meetings. He has organized several symposia on electronic solders for The Minerals, Metals and Materials Society and is a member of The Electronic Packaging and Interconnection Materials Committee of this society. Dr. Subramanian received his doctorate degree in Metallurgy from Michigan State University in 1966 and Masters degree in Metallurgy from University of California, Berkeley, in 1962. His degrees from India include a post-graduate degree in Metallurgy from Indian Institute of Science and a B.Sc. (Hons.) degree in Physics from Annamalai University. Kenichiro Suetsugu Dr. Suetsugu received a bachelor’s degree from Kyoto University in 1978 in the study of high molecule scattering function by statistical mechanics. He received his Master of Arts from Kyoto University in 1980 in the analytical simulation of high molecule scattering function by statistical mechanics. He also received his Doctorate from Kyoto University in 1988 in the study of material design for composite materials. In 1980, Dr. Suetsugu joined Matsushita Electric Industrial Co. (MEI), working for the Production Engineering Laboratory of the Corporate Production Engineering Division, and thereafter, the Circuits Manufacturing Technology Laboratory and the Environment Production Technology Laboratory where he is currently assigned. He is the Chief of Technical Development for MEI’s company-wide ‘‘Lead-free Solder Project.’’ In 1999, he was named Chief of the Experts Committee for the NEDO ‘‘R&D into Lead-free Solder Standardization’’ national project. He is also the deputy leader of the JEITA ‘‘Lead-free Solder Application Roadmap 2002’’ project and the Japanese representative to the World Summit on Leadfree Solder.
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Dr. Suetsugu received the Technology Award of the Society of Material Science, Japan; IPC Special Award, Technology Award of the Japan Institute of Electronic Packaging, Best Paper Award of the Microelectronics Association, and Honorable Mention by the Society of Polymer Science, Japan. Katsuaki Suganuma Dr. Suganuma was born in January 17, 1955 in Japan. He graduated from the doctoral course of Tohoku University in 1982 and received the degree of Doctor of Engineering. He first took the position of a research assistant of ISIR, Osaka University in 1982. He moved to National Defense Academy in 1986 as an associate professor. He returned to Institute of Scientific and Industrial Research (ISIR) as a professor in 1996. Dr. Suganuma has published more than 200 papers on various interface phenomena including ceramic/metal, metal/metal, and soldering. He also published two books on lead-free soldering. Now he has focused on lead-free soldering and conductive adhesives. Dr. Suganuma is currently in charge of the lead-free soldering work group of Japan Institute for Electronic Packaging (JIEP), is a vice chairman of Micro Electronics Symposium (MES, JIEP), and a committee member of MATE (Japan Welding Engineering Society) and of EcoDesign. He has received several awards, e.g., Fularth Pacific Award in 1995, Persons of Scientific and Technological Merit Awards (Science and Technology Agency) in 1993, the Best Paper of JIEP in 2000, the Best Paper of IMAPS in 2000, and Lead-free Soldering Awards (ITRI, U.K.) in 2001. Yukio Sugimoto—Hardware Engineer, PC Service & Option, IBM Japan Ltd. Mr. Sugimoto is the chairperson of IBM Japan’s ECO-Design Committee. This committee was established to achieve ECP objectives and targets which reflect ECP competitiveness in Japan. He had been working for IBMJapan in the area of unique LCD integrated desktop PC development since 1992. The LCD integrated desktop PC, called the GREEN-PC, was released in 1993 in Japan. This focused many companies on environmentally conscious products in Japan. Mr. Sugimoto graduated from Keio University in 1979, majoring in electrical engineering. Michael J. Sullivan—Consulting Engineer, Microelectronics–Lloyd Technology Associates, Inc., Katonah, New York. With 36 years of experience, Dr. Sullivan has been a consultant to the microelectronics industry since 1993, specializing in packaging, solder bump technology, and leadfree soldering. He has participated in all aspects of research, development, and manufacturing of interconnections between chips and various substrates as well as BGA and SMT technology. He has optimized C-4 solder bump processes to eliminate early interface fails, designed reliability test plans, and performed testing and failure analysis. Dr. Sullivan has also supported the building of solder bump manufacturing facilities, including materials and process specifications, equipment purchase, and special tool design and build. His recent involvement in lead-free solder technology includes optimum solder composition determination, process specification, reliability, and special testing for high tin solders. Dr. Sullivan also teaches courses in microelectronic soldering technology and leadfree soldering including such topics as solder reactions, interface properties, accelerated testing and modeling, as well as statistics, burn-in, and other topics. Prior to 1993, he worked for 26 years at IBM on the development of soldering technology and also on Schottky Barrier Diode technology. His work on C-4 solder bump technology included solder reactions with terminal metallization, diffusion barriers, reflow ambient effects, defects, acceleration models, and numerous other topics. Dr. Sullivan earned a Ph.D. in Materials Engineering in 1988 from Rensselaer Polytechnic Institute. He has published numerous papers and co-authored a book on thin film interdiffusion and reactions. He holds six patents and has 31 published inventions. Martin Theriault Martin Theriault serves as Global Marketing Manager, Electronics Manufacturing with Air Liquide, Houston, Texas, U.S.A. Mr. Theriault currently oversees all of Air Liquide activities in electronics packaging, assembly, optoelectronics, and compound semiconductor markets. Mr. Theriault has worked extensively in the past 7 years with electronic assemblers in the field of inert atmosphere soldering and has written and presented several papers on that topic. Additionally, he is strongly involved in the development of new gas applications and products for the electronic assembly
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industry. Mr. Theriault has a mechanical engineering degree from McGill University in Montreal, Canada, and an MBA from Duke University, Durham, North Carolina. King-Ning Tu He received his Ph.D. degree in Applied Physics from Harvard University in 1968. He spent 25 years at IBM T.J. Watson Research Center as a research staff member in the Physical Science Department. During that period, he also served as Senior Manager of Thin Film Science Department and Materials Science Department for 10 years. In September 1993, he joined the Department of Materials Science and Engineering at UCLA and is now chairman of the department. He is a Fellow of American Physical Society, The Metallurgical Society (TMS), and an Overseas Fellow of Churchill College, Cambridge University, U.K. He was president of Materials Research Society in 1981. He received the Application to Practice Award from TMS in 1988 and Humboldt Award for U.S. Senior Scientists in 1996. He has been elected a member of Academia Sinica, Republic of China, in 2002. He has over 350 journal publications, edited 13 proceedings, and co-authored a textbook on ‘‘Electronic Thin Film Science,’’ published by Macmillan in 1992. His research interests are in kinetic theory and processes in thin films, metal–Si interfaces, electromigration, and Pb-free solder metallurgy. Laura J. Turbini Dr. Laura J. Turbini is the Executive Director of the Centre for Microelectronics Assembly and Packaging (CMAP) located at the University of Toronto. She has been involved in the electronics industry for more than 20 years. She has worked in research and engineering management within AT&T, starting at what was Lucent Technology, Bell Labs in Princeton, and ending 12 years later at AT&T’s manufacturing plant in Denver. Dr. Turbini spent 10 years at Georgia Tech, first as the associate director for their Manufacturing Research Center and then as a professor of Materials Science and Engineering. Dr. Turbini holds a Ph.D. in Inorganic Chemistry from Cornell University. She has been active in the IPC and Surface Mount Technology Association and served as a member of the Surface Mount Council. In 1992, she received the EPA Stratospheric Ozone Protection Award for her works on CFC elimination. She is a member of the American Chemical Society, TMS, MRS, and is a senior Member of IEEE. Jason Uner Jason Uner—Research Scientist–Air Liquide, Countryside, Illinois, U.S.A. Jason Uner has spent the past 3 years researching the field of electronic packaging and assembly where he works to develop new approaches and solutions to challenges in the manufacturing, packaging, and assembly processes. During his time in R&D, Jason has worked with customers all over the world to help increase the effectiveness of gas and gas-related technologies in electronics assembly. Jason Uner is a 1996 graduate of the University of Illinois with a degree in Chemical Engineering. At the time of this publication, Jason is pursuing his MBA at the University of Virginia’s Darden Graduate School of Business Administration. E. Jan Vardaman E. Jan Vardaman—President and Founder–TechSearch International, Inc., Austin, Texas. Ms. Vardaman analyzes international developments in the field of semiconductor packaging and assembly. Previously, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC) in Austin, Texas where she analyzed international developments in software including artificial intelligence and semiconductor packaging and assembly. Before joining MCC, she was a computer industry analyst for the U.S. government where she followed international developments in systems from mainframes to personal computers. She is the editor of Surface Mount Technology: Recent Japanese Developments, published by IEEE. She is a columnist with Circuits Assembly magazine and author of numerous publications on emerging trends in semiconductor packaging and assembly. She served on the NSF-sponsored World Technology Evaluation Center (WTEC) study team involved in investigating electronics manufacturing in Asia. She is a member of IEEE’s CPMT society Board of Governors, IMAPS, and SMTA. Ms. Vardaman received her B.A. in Economics and Business from Mercer University in 1979 and her M.A. in Economics from the University of Texas in 1981. Paul T. Vianco Paul T. Vianco received a Ph.D. degree in Materials Science from the University of Rochester (New York) in 1986. He joined Sandia National Laboratories, Albuquerque, New Mexico,
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in 1987 where he is currently a principle member of the technical staff. Paul has been involved in all aspects of soldering technology, including alloy and process development efforts for Sn–Pb (PTH, SMT, and connectors) and Pb-free solders, the use of ultrathin solder joints for microsensor assembly, as well as the modeling of thermomechanical fatigue and solid-state intermetallic compound layer growth in solder joints. Paul is also the author of the Soldering Handbook—Third Edition, which is published by the American Welding Society. Puligandla Viswanadham Puligandla Viswanadham is a principal scientist at Nokia Research Center in Irving, Texas. He is involved in the development and deployment of emerging and maturing technologies into Nokia products. Prior to joining Nokia, he worked at Raytheon Systems Company, Texas Instruments Inc. and International Business Machines Corporation. While at Raytheon and TI, he was involved in area array technology implementation into military products. At IBM, his activities encompassed SLC and BGA technologies, assembly and Reliability of fine pitch QFPs and TSOPs, and tape automated bonding. While at IBM, Austin, Puligandla Viswanadham was site analytical laboratories manager during 1989–1990. At IBM, he was also involved in corrosion studies, analytical methods development, plating, and contamination control. Prior to joining IBM, his research included high-temperature chemistry and thermodynamics of binary and ternary sulfides, atomic absorption, slag-seed equilibria in coalfired magnetohydrodynamics energy generation, and astrophysics. He has authored or co-authored over 85 publications in the areas of microelectronics packaging and a book on Failure Modes and Mechanisms in Electronic Packages published by Chapman and Hall. He has seven patents and 15 invention disclosures. He received the Third IBM Invention Achievement Award, an Excellence Award, and a Fourth Level Author Recognition Award. During 1974–1978, he was on the faculty of Ohio Dominican College, Columbus, Ohio, as assistant professor. He is currently an adjunct faculty at the University of Texas at Arlington in the Mechanical and Aerospace Engineering Department. Puligandla Viswanadham has a Ph.D. in Chemistry from University of Toledo and M.Sc. degree in Chemistry from Saugor University, India. He is a member of IEEE and Surface Mount Technology Association. C.P. Wong C.P. Wong, Regent’s Professor–School of Materials Science and Engineering, and Research Director at the NSF Packaging Research Center, Georgia Institute of Technology, received his B.S. degree in Chemistry from Purdue University and Ph.D. degree in Chemistry from Pennsylvania State University. Dr. Wong spent 19 years at AT&T Bell Laboratories and was elected a Bell Labs Fellow in 1992. His research has been in the areas of polymeric materials, reaction mechanism, IC encapsulation, in particular, hermetic-equivalent plastic packaging, electronic packaging processes, interfacial adhesion, PWB materials, SMT assembly, and component reliability. He received many awards, among which are the AT&T Bell Labs Distinguished Technical Staff and Fellow Awards in 1987 and 1992, respectively, IEEE Components, Packaging and Manufacturing Technology (CPMT) Society Outstanding and Best Paper Awards in 1990, 1991, 1994, 1998, and 2002, University Press (London, U.K.) Award of Excellence in 2002, and the IEEE Exceptional Technical Contributions Award in 2002. He holds over 40 U.S. patents, numerous international patents, and over 450 technical papers. Dr. Wong was elected a member of the National Academy of Engineering in 2000, and he is a Fellow of IEEE, AIC, and AT&T Bell Labs and held several board and committee positions including technical vice president (1990, 1991) and president (1992,1993) of the IEEE-CPMT Society. Anis Zribi Dr. Anis Zribi earned a Masters degree in Physical Chemistry from Polytechnic Institute of Grenoble, France, a Masters degree in Materials Science from Chalmers University of Technology, Sweden, and a Ph.D. in Materials Science from S.U.N.Y. at Binghamton, New York. He joined the Global Research Center of General Electric in 2002 where he has been involved in research and development of nanostructured materials for nano-patterning and also in integration of optoelectronic systems. He is currently developing nanomaterials for optical data storage applications and in designing MEMS sensors.
