Lecture Notes in Computer Science Edited by G. Goos and J. Hartmanis
216 I
I
III
Christer Fernstrom Ivan Kruzela Bertil Svensson
LUCAS Associative Array Processor Design, Programming and Application Studies
Springer-Verlag Berlin Heidelberg New York Tokyo
Editorial Board
D. Barstow W. Brauer P. Brinch Hansen D. Gries D. Luckham C. Moler A. Pnueli G. Seegm(Jller J, Steer N, Wirth Authors Christer Fernstrom Ivan Kruzela Bertil Svensson Department of Computer Engineering, University of Lund P.O. Box 118, 22100 Lund, Sweden
CR Subject Classifications (1985): B.1.4, B.2.1, B.3.2, C.1.2, D.3, F.2.1, G,2.2, H.2.6, 1.4.0, 1.4.3, 1.4,6, 1.4.?
ISBN 3-540-16445-6 Springer-Verlag Berlin Heidelberg New York Tokyo ISBN 0-387-16445-6 Springer-Verlag New York Heidelberg Berlin Tokyo
This work is subject to copyright. All rights are reserved, whether the whole or part of the material is concerned, specificallythose of translation,reprinting, re-use of illustrations,broadcasting, reproduction by photocopyingmachineor similar means, and storage in data banks. Under § 54 of the German Copyright Law where copies are made for other than private use, a fee is payable to "VerwertungsgesellschaftWort", Munich. © by Springer-VerlagBerlin Heidelberg 1986 Printed in Germany Printing and binding: Beltz Offsetdruck, Hemsbach/Bergstr, 2145/3140-543210
PREFACE
Performance requirements for computers are steadily increasing.
New application areas
are considered that pose performance requirements earlier thought unrealistic. history of computing, increased c i r c u i t
In the
growing demands have to a substantial degree been met through
speed,
However~
in
the
most powerful computers of
each t i m e
parallelism has also been introduced because improvements in circuit speed alone have not been sufficient to produce the required performance, The /40 year history
of computing shows that concepts introduced in high-performance
computers often become part of the design of more moderately sized (or at least more moderately priced) wide-spread computers a few years later,
The rgpid progress of Very
Large Scale Integration (VLSI) technology also helped increase the use of parailetismo New computer architectures often originate from the need to efficiently solve problems arising in some specific application areas, these problem classes.
However~
They are~
in a way~
demonstrate great similarities with each other,
Thus~
algorithms
areas on specific
for
solving
machines is evident,
tuned specifically to
many architectures are of a general purpose kind or
problems from
different
the need to discover efficient classes
of
parallel
Existing programming languages are strongly influenced by classical
computer architecture and thus not suited for expressing these algorithms.
Therefore a
need for new languages is aiso evident, The
necessity
of
abandoning the
von
Neumann
architecture
performance systems has been advocated by many authors, 3ohn Backus.
in
the
design
of
high-
One of the most prominent is
He maintains that we are also hampered in our way of designing algorithms
by the habit of always breaking them down into sequential form: "It is an intellectual bottleneck that has kept us tied to w o r d - a t - a - t i m e thinking instead of encouraging us to think in terms of the larger conceptual units of the task at hand" [Backus78], This view points to t h e i m p o r t a n c e of i m p l e m e n t i n g radically new c o m p u t e r a r c h i t e c t u r e s and using them in practice. of computer scientists for With new architectures~ become essential.
Many computational problems have engaged a iarge number decades due to the continued relevance of these problems.
some of these problems may be less important while others wiJl
For example,
when working with a highly parallel computer,
find sorting to be of l i t t l e interest,
we may
yet the problem of routing large amounts of data
IV
between different parts of the machine without conflict now becomes a salient problem, The LUCAS project (Lund University Content Addressable System) is an a t t e m p t to design and evaluate
a
highly
parallel system
while
keeping its size within
still
the
limits
necessary for a university research project. The
initial
plans,
greatly
inspired by
Processors" by Caxton Foster [Foster76], autumn of that same year.
the
monograph "Content
were drawn in 1978.
Addressable Parallel
The project started in
A f t e r simulations and implementation of a prototype,
the
final design (with 128 processors and a general purpose intercennection network including the perfect shuffle/exchange) was decided upon in t980 and fully implemented in 1982.
In
1985 a dedicated input/output processor was added to the system. The main objective of LUCAS design and implementation was to allow a research vehicle for the study of architectural principle% associative array processors.
programming methodology and applicability of
With certain principles and design details fixed (such as
bit-serial working mode and the use of conventional memory circuits),
the implementation
of LUCAS allowed modification of architecture parts to suit certain applications. parts
include
system~
the
and the
network
that
instruction
interconnects
sets at
the
different
processing units,
architectural
processing elements in the design is not limited in itself,
the
levels.
These
input/output
The number
of
but has been fixed to 128 in
the implemented version used for application studies. The algorithms that have been programmed and evaluated on the machine mainly concern three large areas - image processing,
signal processing,
and database processing.
New
programming toots and languages were developed to express parallelism and associativity. This
book
is
an
attempt
to
compile
the
underlying
programming tools and experiences from the project. material
from
Svensson83a].
three Also
PhD
theses
published
in
1983,
included
is
summing
up
of
a
architecture tuned for signal processing,
thoughts,
design
principles,
The greater part of the book is [Fernstrom8%
continued work
(described in [Ohlsson84]),
Kruzela83,
on
an
improved
and on design of a
dedicated I/O Processor [Kerdina85]. The book is organized as follows: Part
1,
Processor Design,
processing,
starts with a chapter introducing parallel and associative
tt continues with a rather detailed description of LUCAS System architecture,
followed by an overview of the basic instructions.
Part 1 concludes with a comparison of
LUCAS to related designs published in the literature. Part 2 is devoted to programming aspects, programming level.
A
both on microprogramming and application
new microprogramming language which
mastering of parallel computing structure is presented. suitable
for
expressing
parallel
algorithms
is
also
greatly
simplifies the
A high level language (Pascal/L), defined.
Comparison
with
other
proposed languages is made. Part
5
of
the
book
comprises
three
chapters
on
applications.
The
first
Chapter 7 - treats "some well known problems" implemented on LUCAS. are taken from three important classes of computations, computation problems.
of
the
discrete
Fourier
Transform,
and
of
these
-
The problems
namely m a t r i x multiplication, solution
of
graph
theoretical
Chapter 8 discusses the use of LUCAS in relational data base processing and
shows that many of the operations in this field can be efficiently implemented. 9 shows the
implementation of image processing algorithms.
Chapter
Chapters 8 and 9 both
compare the results with reported results from other designs. Part /4,
the epilogue,
contains conclusions and description of continued research.
The
proposal for an improved processing element with a bit-serial multiplier is included here, as are the conditions for VLSI implementation of the processor array. Many people have been helpful during the work that resulted in this book. thank Rolf
3ohannesson and the staff
University of Lund.
at
We want to
the department of Computer Engineering at
We are deeply indebted to Lennart Ohlsson and Staffan Kordina for
the permission to include their results in the book.
Anders Ardo has implemented the
t e x t f o r m a t t i n g system which greatly simplified the work of preparing the manuscript. The Swedish National Board for Technical Development has provided financial support. Professor Dines Bjorner,
who served as scientific advisor to the Board,
valuable constructive criticism. Corporation,
University
has given us
We are also grateful for the support from Lund Science
of Halmstad and Cap Sogeti Innovation in France for having
made the publication of this book possible.
Christer Fernstrom Ivan Kruzeta Berth Svensson
CONTENTS
PART 1.
Chapter 1
PROCESSOR DESIGN
Parallel and Associative Processing
1.1
INTRODUCTION
2
1.2
PERFORMANCE IN PARALLEL MACHINES
4
1.3
ASSOCIATIVE ARRAY PROCESSORS
6
1.3.1 Associative Memories
7
1.3.2 Bit-serial Working Mode
11
1.3.3 A Bit-serial Associative Processor
13
INTERCONNECTION NETWORKS IN SIMD SYSTEMS
15
1.4.1 Introduction
15
1.4.2 The Perfect Shuffle
17
Chapter 2 LUCAS System Architecture
27
1.4
2.1
SYSTEM OVERVIEW
2.2
CONTROL UNIT
32
2.2.1 Overview
32
2.2.2 Instruction Timing
33
2.2.3 Microprogram Sequencer
34
2.2,4 Address Processor
35
2.2.5 Common and Mask Registers
39
2.2.6 I/O Buffer Register
39
2.2.7 Status Register
40
PARALLEL PROCESSING ARRAY
41
2.3.1 Processing Elements
41
2.3.2 Memory Modules and Input/output Structure
/45
2.3.3 Communication Between Elements
46
2.3.4 I/O Processor
50
2.3.5 Physical Description
52
2.3
Chapter 3 3.1
Basic Instructions
CLASSIFICATION
OF INSTRUCTIONS
27
54 54
VIII
3.1.1 Basic Types of Instructions Operating on the Associative Memory 3.2
58
MOVES,
60
PERMUTATIONS AND MERGES
3.2.1 Introduction
3.3
3.4
3.5
54
3.1.2 I/O Instructions
60
3.2.2 Basic Moves
60
3,2,3 Use of the [nterconneetion Network
61
3.2.4 Automatic Routing
63
SEARCHES,
66
COMPARISONS AND LOGICAL INSTRUCTIONS
3.3.1 Type
--> <selector>
66
3.3.2 Type --> <selector>
67
3.3.3 Type --> <selector>
67
3.3.4 A More Complex Search
68
ARITHMETIC INSTRUCTIONS
69
3.4.1 Addition and Subtraction
69
3,4.2 Multiplication
70
SUMMARY OF EXECUTION TIMES
74
Chapter 4
Comparison with Related Designs
75
75
/4.1
STARAN
4.2
DAP
76
4.3
PROPAL 2
77
4.4
Vastor
77
4.5
CLIP4
78
4.6
MPP
78 79
/4.7 CONCLUSION
PART 2.
Chapter 5
PROGRAMMING
LUCAS Microprogramming Language
80
84-
INTRODUCTION
84
5,2
MICROPROGRAMMER'S VIEW OF LUCAS
87
5.3
INTRODUCTION TO THE LANGUAGE
89
54
LANGUAGE ELEMENTS
93
5.4.1 Constants
93
5.1
5./4.2 Variables,
Assignments
94
5.4.3 Subroutines
95
5.4.4 Microprograms
97
IX
5.4.5 Statements I - Program Flow Controt
98
5./4.6 Statements II - Array Operations
102
5.5
PROGRAM EXAMPLES
106
5.6
MICROPROGRAM COMPILER
109
5.6.1 Introduction
109
5.6.2 Intermediate Code
109
5.6.3 Code Improvement
tlt
Chapter 6
P A S C A L / L - A High Level Language for LUCAS
114
6.1
INTRODUCTION
114
6.2
OVERVIEW OF PASCAL/L
117
6.3
LANGUAGE DESCRIPTION
119
6,3.1 Declaration of Data
119
6,3.2 Indexing of Parallel Variables
122
6,3.3 Expressions and Assignments
123
6.3.4 Control Structure
125
6.3.5 Standard Functions and Procedures
127
6.3.6 Microprograms
129
6./4
6.5
EXECUTION ON LUCAS
130
6.4.1 Pascal/L Pseudo-machine
130
6.4.2 Paraltet Expressions
t37
6.4.3 Where Statement
138
PROGRAMMING EXAMPLES
142
PART 3.
Chapter 7
7.t 7.2
APPLICATION
STUDIES
Some Well-known Problems Implemented on LUCAS
INTRODUCTION MATRIX MULTIPLICATION
147
7.2.1 n x n Matrices~
n Processors
147
7,2.2 n x n Matrices,
n 2 Processors
151
7.2.3 n x n Matrices~
More Than n But Fewer Than
7.2.4 n x n Matrices,
7.&
1/46
t&6
n 2 Processors
7.3
145
155 More Than n 2 Processors
FAST FOURIER TRANSFORM
156 158
7.3.1 The Discrete Fourier Transform
158
7.3.2 The Fast Fourier Transform
159
7.3.3 Implementation on LUCAS
162
THREE GRAPH-THEORETIC PROBLEMS
168
7.4.I Shortest Path Between Two Given Vertices.
Unit Path
Length
168
7.4.2 Shortest Path Between at] Pairs of Vertices in a Weighted~
Directed Graph
171
7,/4,3 Minimal Spanning Tree
173
7.4.4 Discussion
177
Chapter 8
LUCAS as a Backend Processor for
Relational Database Processing
179
8.1
INTRODUCTION
179
8.2
RELATIONAL ALGEBRA ON LUCAS
181
8.2.1 Introduction
181
8.2.2 Representation of a Relation in the Associative Array
t82
8,2.3 Some Basic Operations in the Associative array
185
8.2./4 Internal Algorithms for Algebraic Operations
189
8.2,5 Performance Analysis
198
8.2.6 Comparison of LUCAS with Alternative Designs
207
8.3
8.4
8.5
8.6
INTERNAL QUERY EVALUATION IN A SIMPLE DATABASE COMPUTER
208
8.3.1 Introduction
208
8.3,2 Database
210
8.3,3 Evaluation of a Query
212
8.3.4 Discussion
217
COMPARATIVE PERFORMANCE EVALUATION OF DATABASE COMPUTERS
217
8./4.1 Introduction
217
8./4,2 Specification of Characteristics of Database Machines
219
8,4,3 Database and Queries
220
8~/4./4 Response Times of LUCAS
223
8./4.5 Performance Comparisons
225
8.4.6 Influence of the Size of the Associative Array
227
8./4.7 Conclusions
229
EXTERNAL EVALUATION OF ,]DIN
229
8.5,1 Introduction
229
8.5.2 System Description
23q
8.5.3 Algorithm and Timing Equations
232
8.5°/4 Discussion
235
CONCLUSIONS
237
Xi
Chapter 9
LUCAS as a Dedicated Processor for Image Processing
241
9.1
COMPUTATIONAL DEMANDS IN IMAGE PROCESSING
241
9.2
DIFFERENT ATTEMPTS TO MEET THE DEMANDS
243
9.2.1 Fast Neighbourhood Access
243
9.3
9.2.2 A Small Number of Special Purpose Processors
243
9.2.3 A Large Number of Conventional Microprocessors
244
9.2./4 A Very Large Array of Simple Processors
245
9.2.5 LUCAS Compared to Other Machines
245
9.2.6 The Advantages of Image Parallelism
246
ORGANIZATION OF PROCESSOR ARRAYS FOR IMAGE PROCESSING
9.4
95
247
9.3.1 Introduction
247
9.3.2 Two-dimensionally Organized Arrays
248
9.3.3 Linearly Organized Arrays
248
IMAGE OPERATIONS ON LUCAS ORGANIZED AS A LINEAR ARRAY OF PROCESSING ELEMENTS
250
9.4.1 Introduction
250
9.4.2 Genuinely Local Operations.
Small Neighbourhood Sizes
252
9~4.3 Genuinely Local Operations.
Larger Neighbourhood Sizes
262
9.4,4 Semi-local Operations
265
9.4.5 Measurements
273
9,4.6 Global Transforms
277
9.4.7 Input/output
278
9,4.8 Larger Images
278
9.4.9 Comparison of Execution Times
280
CONCLUSIONS
283
P A R T 4.
EPILOGUE
Chapter 10.
CONCLUSIONS AND CONTINUED
284
RESEARCH
285
10.1 GENERAL
285
1([I.2 A PROPOSAL FOR A MORE POWERFUL PE ARCHITECTURE
286
10.2.1 The New Design 10.2.2 Execution Times with the New Design 10.3 VLSI IMPLEMENTATION OF THE PROCESSOR ARRAY
286 291 292
10.3.1 Off-chip Memory
293
10.3.2 On-chip Memory
296
10.3.3 No Interconnection Network
296
XII
10.4 FINAL WORDS
297
Appendix 1.
ALU Functions
298
Appendix Z.
LUCAS Micreprogramming Language
301
Appendix 3.
Pascal/L - Syntax in BNF
309
References
312
Part 1 PROCESSOR
DESIGN
Chapter 1 PARALLEL AND
ASSOCIATIVE
PROCESSING
1.1 I N T R O D U C T I O N The rapid development of computers during the last decades has pushed the state of the aft
in two
different
directions:
computers are becoming smatter and they are becoming
more powerful. Advances
in
different
fields
have
progress has influenced speed,
contributed
to
the
development:
cost and size of the components,
been developed for the basic operations,
the
new algorithms have
such as a r i t h m e t i c operations,
of organizing the entire systems are used,
technological
and new forms
where parallel operation between the system
components is exploited. All
these
areas
Unfortunately
have
had
impact
on
the
development
of
more
powerful
we are approaching the speed l i m i t s of gates and flip-flops,
machines.
which means
that the enhancement in c i r c u i t technology atone wilt only allow a r e l a t i v e l y small gain in speed.
It is clear that questions concerning the organization of systems t o g e t h e r with the
development
of
new
algorithms
will
play
an
of
Flynn
increasingly
important
rote
for
further
advances. According
to
a
classification
scheme
categories of computer organization.
kind processes data by a sequence of instructions. and an instruction stream,
[Flynn66],
there
are
four
different
The basis of this scheme is that a processor of any Based on the context of a data stream
the following possibilities exist:
* SISD - Single Instruction stream Single Data stream * SIMD - Single instruction stream M u l t i p l e Data stream * MISD - Multiple Instruction stream Single Data stream * MIMD - M u l t i p l e Instruction stream M u l t i p l e Data stream
The von Neumann architecture belongs to the SISD category. each processing unit
executes the same instruction~
In an SIMD architecture
but on different data.
systems many processors cooperate to solve a common computational task, assigned to the individual processors can all be different. MISD architecture is not fully agreed upon. category,
In MIMD
but the tasks
The exact structure
of the
Some authors put pipehned processors in this
others claim that pipelined processors belong to the SIMD category~
in which
case the MISD category becomes empty. We w i l l in the following only deal with the SIMD category of parallel computers.
This
class of computers is well suited for applications where the same (often rather simple) operation is performed on a large number of well structured data elements, Different
taxonomies for
SIMD computers have been presented,
We w i l l
borrow
the
following definitions from Thurber [Thurber76].
SIMD
processor
a
computer
architecture
characterized
by
an
SIMD
o r i e n t a t i o n of data and procedure streams. Array
processor/parallel processor -
an SIMD processor in which the cells
usually bear some topological relationship to each other. Associative
processor
-
an SIMD
processor
in which
element a c t i v a t i o n is an associative process.
the prime
means of
(The meaning of this w i l l be
explained in Section 1.3.) Generally the celts of an associative processor have a
loose
processor
topological is
relationship
usually
designed
and
are
around
functionally an
very
associative
simple.
memory
The system.
We w i l l use the t e r m associative array processor to denote an associative processor, defined by Thurber~
as
in which a communication network defines a topological relationship
between the processing elements. t e r m processing element ,
As proposed by Stotnick [Slotnick82]~
or PE for short,
suggests a simpler internal structure,
we will use the
rather than "processing unit",
since this
as is commonly the case in SIMD systems.
We t e r m i n a t e this section with the observation that the name "array processor" sometimes is used to designate a processor which is "suitable for processing arrays".
These "array
processors" are usually pipelined back-end computers which serve as attached resources to minicomputers.
In
our
terminology
processor as described above.
"array
processor"
stands
for
an SIiVlD organized
1.2 P E R F O R M A N C E IN P A R A L L E L MACHINES It
is the
computer
need for
larger capacity
system.
Therefore
it
which
is the reason for
is i m p o r t a n t
to
introducing
have accurate
parallelism
methods to
in a
decide the
influence of d i f f e r e n t design parameters on the c a p a c i t y . Three
aspects
bandwidth ~
of
capacity
are
frequently
the speedup and the e f f i c i e n c y
referenced .
in
the
literature~
namely
the
By the bandwidth we mean the number of
operations that can be performed in the system per t i m e unit.
The speedup indicates how
much faster a computation is done in the parallel machine than if i t was executed on a sequential computer.
Efficiency,
finally,
measures the u t i l i z a t i o n of the parallelism in
the machine for a certain computation. To obtain
a value of
the bandwidt%
we
assume that
operations which can be performed simultaneously° are
independent and can be executed w i t h o u t
a computation C consists of n
We assume further that the operations
any f o r m
of
diagram shows the hardware u t i l i z a t i o n as a function of time. diagram
for
the computation
on an array
processor with
interaction,
A
space-time
Figure 1.1 is a space-time
p processing elements~
where
p
Active processors
time
1 t
Figure 1.1 Space-time
2t
diagram
processors (p
for
the
computation
of
C in an array processor with
p
If T is the t o t a l t i m e to compute C, T =
then we have
Fn/pq*t
and the bandwidth, per t i m e uni%
B,
which is equal to the number of instructions
that are e x e c u t e d
can be w r i t t e n :
B = n/(Fntpq*t)
The speedup is s :
n~tt(l"nlpq~t)
= nil-nip-}
The m a x i m u m speedup w i t h p processors is p~
which is obtained when n is a m u l t i p l e of
p. The e f f i c i e n c y e =
is the actual speedup divided by the m a x i m u m possibie speedup:
s/p
An i m p o r t a n t
question when using a p a r a l l e l c o m p u t e r
the t o t a l speedup of a c o m p u t a t i o n . initialize
the
parallel
operations.
We
processor
split
p a r a l l e l part w i t h
the
t :
.
.
.
t
computation
+
.
.
.
.
.
.
.
.
time into
we understand the t i m e needed to
needed to
two
parts,
perform
air
the
one sequential
non-parallel
part
and one
The t o t a l c o m p u t a t i o n t i m e is T and the t i m e of
Then we get"
+ n*(T-t) .
the
the parallelism n.
the sequential part is t.
8
By set up t i m e 9
plus
is how the set up t i m e influences
t/T .
.
.
.
+ n*(1-t/T)
.
r-n/p-[*(T-t)
Figure 1.2 shows the t o t a l speedup as a f u n c t i o n of the r a t i o t / T (the r a t i o of the t o t a l time
that
elements.
is used for
set up) for
It is assumed t h a t n=p.
a r r a y processors w i t h The figure
different
number of processing
i l l u s t r a t e s the great n e g a t i v e i m p a c t any
sequential part of an a l g o r i t h m has on the speedup of the c o m p u t a t i o n . new paralle! machine this f a c t must be t a k e n into consideration.
When designing a
The a r c h i t e c t u r e should
a l l o w set up and parallel c o m p u t a t i o n to be p e r f o r m e d simultaneously.
s
120
80
40
1
F i g u r e 1.2 The
speedup
as
I
I
I
I
;
0.2
0.4
0.6
0.8
1 .0
a
function
of
the
t/T
ratio
for
--- t / T
different
sizes
of
array
processors.
1.3 ASSOCIATIVE A R R A Y
PROCESSORS
In Section 1.1 we defined an associative a r r a y processor as a machine w i t h
the f o l l o w i n g
properties:
* SIMD processor,
i.e.
it consists of many processing elements (PEs) and one
c o m m o n c o n t r o l unit. * Activation is not the
of the PEs may be an " a s s o c i a t i v e process", l o c a t i o n or address of a PE t h a t
i n s t r u c t i o n s f r o m the c o n t r o l unit,
which means t h a t
decides i f
it
will
it
e x e c u t e the
but some p r o p e r t y of the contents in the
m e m o r y of the PE. *
A communication They
can
In the f o l l o w i n g
for
n e t w o r k defines a t o p o l o g i c a l r e l a t i o n s h i p between the PEs. example
form
a
linear
array
we w i l l sometimes use the t e r m
or
processors by describing
two-dimensional
grid.
associative m e m o r y word as a synonym
f o r a processing e l e m e n t t o g e t h e r w i t h its local m e m o r y . associative a r r a y
a
We w i l l s t a r t our d e s c r i p t i o n of
an associative m e m o r y .
By adding c o m p u t i n g
c a p a b i l i t i e s to the words of the a s s o c i a t i v e m e m o r y we wilt f o r m an associative processor.
F i n a l l y we w i l l present d i f f e r e n t networks for data communication between the processing elements.
The
presentation
of
associative
memories
and
processors
is based on the
presentation in [Foster76].
1 3.1 Associative Memories An associative memory, ceil
contains
argument.
the
or content
necessary
Associated
Outside the memory
with
to
each word
compare
the
is a memory where each bit
stored
is a one b i t
result
information register,
with
a search
called the Tag .
are three registers of the same size as the width of the memory
words: the Commmon , To p e r f o r m
logic
addressable memory,
the Mask and the Data registers (see Figure 1.3).
a parallel search,
the search argument is loaded into the Common Register
and a bit map indicating the bits which w i l l be included in the search is put in the Mask. Before the search operation is i n i t i a t e d , searched are set
to ONE.
all Tag registers in the words that are to be
Now a search
is performed
by generating the
two signals
"Match
O" and "Match 1" (see Figure 1.4) in the bit positions where the Mask contains a
ONE.
A
mismatch
in
one
bit
through the OR-gates and finally
position
generates
a misl,~atch
signal
that
propagates
causes the corresponding Tag to be set to ZERO (see
Figure 1.3). After
a search has been executed it is possible to w r i t e data to or read data from the
selected memory~ read
words
-
the
words where
the
Tag contains
a ONE.
When
writing
the contents in the Data register is copied to all selected words~
yields
the
togica!
OR
in
each
bit
position
of
the
into
the
whereas a
selected
words.
Common Register
[
~ t]
Mask Register
Word 1 Word 2
I I I
J
i sters
I I J
J I I
Word N
Data Reg i s t e r
] Match ]
0
I
I
----____
Mismatch
Data In
Dat, Out
F i g u r e 1.3 A s s o c i a t i v e m e m o r y w i t h d e t a i l s h o w i n g one m e m o r y celt.
Wordwr i te Tag Mismatch
I I I L
Common Register
Mask Register
_I
Match
__
Match
Match activate
I
Figure 1.4 Generation of the match signals,
Most likely a unique selection is wanted, is needed.
This is why a so called m u l t i p l e match resolver
In its simplest form this is a select f i r s t
deselects all words except the f i r s t
chain~
which - when a c t i v a t e d -
one where the Tag contains a ONE (see Figure 1o5),
The output f r o m the select f i r s t chain can be used as a Some/None indicator (even when the
select
first
funtion
This i m p l e m e n t a t i o n delay per word.
is not a c t i v a t e d ) and shows i f
a search was successful or not.
of a m u l t i p l e match resolver suffers from being slow with one gate
In the description of L U C A S we w i l l see how the seiect first chain can
be speeded up with
the use of took-ahead.
A general scheme for
high speed m u l t i p l e
match resolvers is found in [Anderson74]. In some operation. accuracy
applications
it
Depending wanted~
is desirable on the
different
size
simultaneously with other activities~
words in the memory~
of
methods
m o d e r a t e and the speed requirements
the f o r m of a shift register~
to
count the may
the
numbers
memory9 be
used,
of
the if
responders
to
speed requirements the
size
of
the
are low or if i t is possible to p e r f o r m
a search and
memory
the is
the count
one way would be to connect the Tag registers in
and to shift the Tags n steps~
counting the number of ONES,
where n is the number of
10
Set Tags
Some S e l e c t In irst
Wr i t e t t
t 1 I
Wordwrite Tag
r
, I 1
Mismatch
J I I 1
Some out
Figure 1.5 The Tag register w i t h a m u l t i p l e m a t c h resolver in the f o r m of a select f i r s t chain,
Another adder
which
also
generates
a
Some/None
signal
from
the
last
word.
possible way to calculate the number of a c t i v a t e d words is w i t h the use of an tree
(see
Figure
1.6).
in
the
first
level,
groups
of
tags
are
processed
c o m b i n a t o r i a l counters which produce the number of a c t i v e tags in each group. t h a t g groups are formed~
each comprising t tag signats~
where g is a power of t w o .
An adder t r e e of tog2g levels is then used to produce the t o t a l sum. an associative
m e m o r y w i t h /4096 words,
4 - b i t numbers a f t e r the f i r s t level.
in
Assume
For example,
16 tags are grouped together,
To produce the t o t a l sum,
producing
in 28
an 8 level adder t r e e is
used. If
the
words in the associative
memory
aiso can be accessed by address it
desirable to c a l c u l a t e the address of a responding word.
might
be
Anderson [Anderson74] proposes
a t r e e - l i k e structure w i t h log2(n)/2 levels of so called p-generators to produce the result. An elegant method~ word's
however,
address is stored.
resolution,
After
would be to reserve log2n bits in each word~ a search is p e r f o r m e d ,
where the
f o l l o w e d by a m u l t i p l e m a t c h
a readout gives the desired address in the reserved bit positions.
11
t
/
/
Counter
tl]
Counter
J
Adder
C
I
iI
Counter
III I
L1
Io°t°rj
IL~~
1
I
Adde[
Counter ]
rl--
Adder .
.
.
Jl
.
~ Adder log g levels II II
1
Adder
I
Figure 1.6 Count responders n e t w o r k in the f o r m of an adder tree,
t . 3 , 2 B i t - s e r i a l w o r k i n g mode Recalling
Figure
1.3 we see t h a t
the c o m p l e x i t y
of the m e m o r y ceil In an associative
m e m o r y is only s l i g h t l y higher than t h a t of a cell in a m e m o r y of random access type. What
prevents
an e f f i c i e n t
implementation
is the number
This makes it possible to i n t e g r a t e only a very l i m i t e d
of connections
to
number of cells per IC package.
A way to o v e r c o m e this problem is to reduce the p a r a l l e l i s m in the m e m o r y . have described can be r e f e r r e d to as a " w o r d - p a r a l l e l - b i t - p a r a l l e l " m e m o r y . the design to a " w o r d - p a r a l l e l - b i t - s e r i a l "
memory~
we lose some speed~
hand this allows i n t e g r a t i o n of the m e m o r y in a m o r e e f f i c i e n t an o r d i n a r y r a n d o m access m e m o r y (RAM)~ the
number
of
words
that
number of bits per word~
are processed
the cells.
manner.
What we
If we change
but on the o t h e r As compared to
we w i l t s t i l l have a great advantag% in each c o m p u t a t i o n
since
step largely exceeds the
in applications where this kind of o r g a n i z a t i o n is used.
12
b bits
Common Register
1
RAM
Bit Address
Word I
RAM
Word 2
RAM
1
I
I
Word N
I I
RAM
Tag C i rcu i t r y
Multiple Match Resolver
Common
bit
Set Tags
I
[
,
I
_
_
I
Multiple -- Match Resolver
-L
Memory b it I
I
Figure 1 7 B i t - s e r i a l
Now
the
memory
:
associative memory.
consists
either
Each R A M
of
shift
"perpendiculary" to their normal usage,
i.e.
by b bits in the associative memory the
Mask can be used to
processed. all,
registers
bit
or
of
RAMs
that
are
accessed
a b word by n bit RAM is used as n words
(see Figure
decide which
is a b words by one bit memory,
1.7).
position%
In the bit-serial or bit
slices,
working that
mode,
are to
be
Bit positions where the Mask contains a ZERO do not have to be processed at
which means that the speed of the b i t - s e r i a l associative memory is not reduced by a
f a c t o r b as compared to the b i t - p a r a t l e l i m p l e m e n t a t i o n ,
but only by a f a c t o r according
13
to the length of the search argument,
A discussion of bit-serial working mode is found in
[Batcher82],
1.3.3 A Bit-serial Associative Processor The bit-serial
associative memory can be transformed into an associative processor by
adding bit processing capabilities to the Tag/mismatch circuitry.
This can take the f o r m
of a few additional one-bit registers and a Boolean function generator (or ALU). to the ALU are the registers,
inputs
the PIE-memory bit and a bit from the Common register.
The ALU produces the new register values.
This extended associative memory will be
referred to as an associative array or a processor array . In addition to the Tag register~ (C-register)
is
a
minimum
reasonable efficiency,
a one-bit result register (R-register) and a carry register for
implementing
bit-serial
which
operations
with
Figure 1.8 shows a possible implementation of a simple PE,
comprises an ALU and three one-bit registers: T~ memory,
arithmetic
is an ordinary RAM~
R and C.
is handled by the Common register.
passes f r o m the common input of the ALU and is loaded into the R register, it may be w r i t t e n into the memory.
It
input of data to the PE The data from where
Output of data is as follows: the memory output is
copied into the R register via the ALU,
When the READ signal is activated,
the data
output shows the value of the logical OR function between the R registers of ai1 selected PEs. A multiple match resolver is implemented in the form of a Some-None/Select-First chain, A central control unit sends the RAM address and the function code to the ALU, controls the Read~
It also
the Write and the Select First functions.
Examples of A L U functions are:
Set
Set all Tags
Mismatch
Reset Tag i f mismatch between the Common and the PE memory bit
Add
Add PE memory bit to R and C.
Put result in R (result bit) and C
(generated carry) Load R
Load the R register from the PE memory
14
From Control Unit I Bit Address Write
/ ALU Common Function
Select First
Read
__
Some In
] r~.... 5ome-None Chain _ _ . ' ~ - -
Some Out
Memory
J
Data In Data Readout Chain
L
- -
Figq,r e 1.8 Processing
element
and
memory
in
a
bit-serial
Data Out
associative
processor,
The control unit plays an i m p o r t a n t role in a b i t - s e r i a l implementation of an associative processor. sizes, PEs.
It must be able to accept instructions
that operate on data items of various
During the execution it generates the necessary sequence of control signals to the We call the data items of various formats
fields ,
several bit slices in the associative memory (see Figure 1.9),
each field occupying one or The task the control unit
performs is basically a transformation of operations on fields to operations on b i t slices, The control unit, register, different registers.
which may be mieroprogramrned,
t w o or three loop counters~ bit
contains a Common register,
a Mask
a number of registers to hold the addresses of
slices in the associative memory,
and logic to load and increment
these
15
W/7777Z (Z//////;
Common
Mask
Associative Array I
t
I
,
T
't
[
Y//Z4 Figure 1.9 Bit slice and Field in the associative memory.
An instruction fields
(their
to the control
bit
unit
includes specification
of the iocation
slice address) and also the length of the operands.
of the operand
Examples of such
instructions are:
ADDCONST
Add
the
ADDFIELDS
Add the contents of two fietds
SEARCH
Compare
MAX
Select
the
contents
the
of
contents
word
which
the
of
Common
register
to
with
the
Common
register
has the
maximum
value
a
a
field
field
in the specified
field
1.4 I N T E R C O N N E C T I O N NETWORKS IN SIMD SYSTEMS
1.4.1 Introduction [n many algorithms there is a need to combine array elements with d i f f e r e n t indices. the case of sequential operation this causes no problem. one a f t e r the other,
In
Since the operands are accessed
the same bus can be used to transport data,
even if the operands
16
are located in d i f f e r e n t m e m o r y modules.
The problem which arises in an SIMD machine
is that all the processing elements must have simultaneous access to the data they need. For
this
purpose,
an i n t e r c o n n e c t i o n
processing elements is defined.
network
for
p a r a l l e l data transport
Once the n e t w o r k has been decided,
between
the
the t o p o l o g y of the
processing a r r a y has also been settled. Since only a small subset of all possible i n t e r c o n n e c t i o n s can be included, these must be guided by the intended applications. the most f r e q u e n t l y
the choice of
[n image processing,
for example,
used operations combine the value of a pixel (picture element) w i t h
the values of its nearest ne]ghbours to f o r m the new value.
In operations on relations in
a r e l a t i o n a l database some a l g o r i t h m may search t w o relations with d i f f e r e n t search keys and then combine the tuples where the search result was a f f i r m a t i v e , applications,
where operations such as the Fast F o u r i e r Transform
in signal processing are common,
other
ways to combine the operands are needed. The most simple f o r m of i n t e r c o n n e c t i o n is when c o m m u n i c a t i o n is l i m i t e d to the nearest neighbours.
Figure 1.10 shows this f o r m of i n t e r c o n n e c t i o n in both a one-dimensiona] and
a two-dimensional control
unit
array.
When
communication
between the elements
issues an instruction
such as READ
ABOVE.
Now,
is needed,
the
each a c t i v e processing
e l e m e n t reads the data coming f r o m the neighbour which is situated i m m e d i a t e l y above in the processing array.
•
.
.
Figure 1.10 One- and t w o - d i m e n s i o n a l processing arrays.
Several machines using the one-dimensional i n t e r c o n n e c t i o n scheme have been designed:
* RAP,
the R e l a t i o n a l
Array
Processor [Ozkarahan
for r e l a t i o n a l database processing.
et a1.75],
which
is used
17
* PEAC,
a Peripheral A r r a y Computer [Schomberg77].
Proposed applications
are computer assisted tomography and high speed solution of nonlinear partial differentia! equations. * PROPAL 2 [Cimsa79],
which is used in image processing and general purpose
array computing. Most of the array processors that have actually been built use an interconnection network where neighbours communicate in a two-dimensional array. built as an 8 by 8 array of PEs,
the MPP [Botcher80] as a 128 by 128 array. image processing,
[ L L I A C IV [Barnes et al.68] is
the [CL DAP [Reddaway79] as a 64 by 64 array and CLIP /4 [Duff79],
uses a two-dimensional structure
which is intended for
where a PE communicates with its
e i g h t neighbours. in the case of ; L L I A C
IV,
it
is true that
quadrant of 8 by 8 processing elements.
the topology defined by the network is a
However,
experience has shown that the size of
this processing area is too small for most of the problems and that it is more often used as a one-dimensional array with 64 processing elements where the i:th PE communicates with the elements i+1,
i-1~
i+8 and i-8.
The l a t t e r two are used to speed up long
"shifts" of data. The advantage of using an interconnection scheme where only neighbours can communicate is of course that i t is f a i r l y easy to implement.
Physically,
all connections can be made
short and there is no need for a large bus since all the data movements are local. the other hand,
for many applications the communication is not efficient.
On
It has been
shown t h a t the t i m e required to perform an a r b i t r a r y permutation in a two-dimensional array of N by N PEs is of the order o ( V ~ * log2N ) [Orcutt74].
1.4.2 The Perfect Shuffle Most of the more elaborate schemes for data communication within an 5IMD computer are
based
on
the
perfect
shuffle
The
usefulness
of
demonstrated by Stone [Stone71].
By then,
the perfect
Golomb
had
how
[Oolomb61]~
and
Pease
shown
it
the
shuffle
could
be
perfect
was
had been studied by used
in
ca[culation of the Fast Fourier Transform on a parallel computer [Pease68]. showed how the Flip Network in STARAN [Botcher77,
shuffle an
efficient
Botcher l a t e r
Botcher79] could be redrawn in the
f o r m of a perfect shuffle network [Botcher76].
Interconnection networks similar to the
perfect
are of
shuffle
do also have properties
which
great
interest
to
fault-tolerant
interconnections [Schlumberger74]. Figure 1.11 shows the perfect shuffle connection between 8 input lines and 8 output lines. We see that
the shuffle,
5,
permutes the input w i t h
index i (i=i2"22
+ it'2
+ i0)
t8
according to: S(i)
=
in the
OF,
2"i
0
<
i < 3
Z'i-7
4 <
i < 7
general case where we have N
integer rn,
inputs and N outputs and N=2 m for some
the input with index i is permuted according to:
S(i)
=
2"i
0
2*i+l-N
N/2
We can see f r o m
(2) that
<
i
the index of
the case where 9 < i < (N/2)-1,
-
1
< N-1 an output i,
(2) element,
o,
can be obtained by
one step to the left.
This is true since in
o=2"i which is equal to a one-step shift of i and since
the most significant b i t of i is ZERO, where N/2 < i < N - l ,
< N/2
< i
r o t a t i n g the index of the input element,
case,
(1)
it is also equal to a r o t a t i o n of i.
the most significant bit of i is ONE.
to a l e f t shift of i where only m (m=log2N) bits are kept.
In the second
Thus 2 * i - N is equal
tf we rota.t.e' i one step,
we
get 2*i-N+1. It
is now
positions.
clear
that
after
m shuffles,
all
the
elements
wit[
return
to
their
initial
19
Figure 1.1.1 The Perfect Shuffte of an 8 element input vector.
One i m p o r t a n t property of the perfect shuffle is its ability of pairing different operands. Assume we use an array processor with a pairwise interconnection between the processing elements,
as in Figure 1.12.
Then it is possible to perform parallel operations on pairs
of elements whose indices d i f f e r in bit 0 only.
A f t e r one shuffle of the elements~
pairs
of elements whose indices d i f f e r in bit m-1 have come in the right position for parallel operation. of their processor.
A f t e r m-1 shuffles~
all pairs of elements whose indices d i f f e r in only one bit
binary representation have been in position for parallel operation in the array This
scheme
is
important
for
the
Transform as we w i l l demonstrate in Section 7,3.
implementation
of
the
Fast
Fourier
20
PE 0
b---
it PE I
--~
k \ X
PE 2
\
;t --'-~
"-/q /I
/t \\ /
/q // /
PE3
J\
I \
\
\
PE N - 2
~
PE N-I I
~----
Figure 1.12 N processing elements with a paJrwise and a perfect shuffle interconnection.
Accordingly,
a
interconnection
is the inclusion of exchange,elements (see Figure 1o15) which allow a
drastic
improvement
of
the
capabilities
pairwise interchange of the outputs from the shuffle network,
of
the
perfect
As we have seen,
shuffle only
tog2N different permutations of the original input vector can be obtained with a pure shuffle connection. (Each shuffling of the data rotates the indices one step so that the original order is restored after togzN shuffles,)
21
Interchange
Straight
Figure 1.13 Permutations in an exchange element.
Depending on the value of a control signal,
the exchange element either gives a straight
or an interchanqed data connection between its two inputs and outputs.
If we allow each
of the N/2 exchange elements to be controlled independently of the others,
it is in fact
possible to obtain any permutation of the N element input vector after a finite number of passes through this shuffle/exchange network. Shuffle/exchange type networks of this kind can be implemented in the farm of a single stage interconnect[on network (see Figure 1.14), register
and recircutated
through
the
settings of the exchange control signa]s, in the register.
shuffle/exchange
interconnections with
different
until at [as[ the desired permutation is obtained
A multi-stage network consists of several cascaded single-stage networks
with or without registers between the stages. the stages,
where the input vector is laaded into a
If the network includes registers between
data can be pipelined through the network which means that the asymptotic
behaviour is like one pass through a single-stage network.
22
Registers
Shuffle Connection
Exchange
\\\
/" /
//~'\ /
\
Figure 1.1/4 One-stage shuffle/exchange network.
[n each stag% the
the exchange elements may either be controlled independently or all have
same setting.
We refer
to
the
two
c o n t r o l " and "individual stage control",
methods
number of possible permutations quite d r a m a t i c a l l y . n stages, given
where n=log2N ,
input-output
connects
them
permutations,
pair
[Pease77]. which
in
of
respectively,
switch
an n-stage
network different
means that
two
as "individual
box
Consider for example a network with
such as the Omega network,
Thus,
setting
individual box control increases the
there
which is described below. is
switch
one
and
settings
the number of permutations
only
cannot
one path yield
For a that
identical
that can be p e r f o r m e d is
23
the same as the number of switch settings.
Far n=4,
i.e.
16 PEs~ this is 232 for a
network with individual box control and 24 for a network with individual stage control. The
Omega
network~
which
]s a shuffle/exchange
individual box control (see Figure 1.15),
network
with
log2N
stages and
has been analysed by Lawrie [Lawrie75].
--1
0
0
1 2
3 P 1
4
~
4
5 6
6
7
F!g,ure 1.t5 The
Omega
network
a
tog N-stage
shuffle/exchange
Although the Omega network is not capable o2-I performing att possible N! an N element input vector in one single pass~
it
network,
N=8.
permutations of
is a very powerfu| interconnection
scheme in that many important permutations can be accomplished such as uniform circular shifts (rotations) and fiip-permutations~ inverted (see Figure 1.16).
where one or several bits of the indices are
24
x a
b
Figure 1,16 Examples
of
c
flip-permutations.
One
d
or
several
bits
in
the
binary
representation of the indices of the input vector are inverted (i = i2"22 + i1~2 + i0).
a) i 0 inverted~
b) i 2 inverted~
c) i 1 and i 0 inverted~
d) i2~
i1
and i 0 inverted,
A simple a l g o r i t h m is used to calculate Omega network.
the settings of the exchange elements in the
Assume that the element S of the input vector should end up in position
D of the output vector and let S = Sm_lSm_2...s 0 and D = dm.ldm_2...d 0 be the binary representations
of
their
sm_2Sm_3...S0Sm_ I .
indices.
Now
the
Sm_2Sm.3...s0dm_ 1 by
using
exchange element:
dm_l=0
if
In
the
exchange
the
bit
first
shuffle
element
is
din_ 1 of
stage
used
the
to
S is shifted place
destination
to
position
S in the
position
address
to
control
then S should be connected to the upper output
the
of the
exchange element and if din_t=1 to the tower output. At
the
inputs
of
stage
i
in
to
position
Figure 1.17 shows the settings of the exchange elements for 5=010 and O=110.
A t the
Sm_iSm.i_l...dm_ldm_2..odm_i+ 1.
the
network,
5
has
been
switched
It is shuffled to position
Sm_i_tSm_i_2...dm_ldm_2...dm_i+lSm_ i and exchanged to position Sm_i_ 1 Sm_i_2...dm_ 1dm_2...dm_i+l dm_ i,
first
and second stages the lower outputs are selected.
A t the third stage the upper
output is selected. When the Omega network simultaneously~
conflicts
is used to permute occur
when
the
two
element require connection to the same output. p e r m u t a t i o n are necessary for a c o n f l i c t
all the N elements of the input vector data
elements arriving at an exchange
L a w r i e has shown which properties of a
free solution and has proved that many useful
permutations have these properties [Lawrie75].
25
2
2
3
3
4
~
5
5
......
Figure 1.17 The
4
element
in
position
2
(010)
7
is
switched
to
position
6
(110).
Several people have come up with schemes for enhancing the performance of the Omega network. Long
[Lang76]
Lawrie's
starts
from
a one-stage
shuffle/exchange
network
(as in
Figure
1.14).
a l g o r i t h m for setting the exchange elements can of course also be used in a
one-stage network since this can be seen as a t i m e multiplexed variant of the Omega network.
Long replaces the exchange elements and the registers by queues,
registers (see Figure outputs of the shuffle difference,
1.18).
Instead of
eonnection~
exchanging data elements that
or FIFO
appear on the
they are placed in the corresponding queue.
as compared to the Omega network~
stage can be connected to the same output,
The
is that both inputs to the exchange
or rather,
more than one data element can
be placed in the same queue during a basic permutation step.
This corresponds d i r e c t l y
to the c o n f l i c t situation which l i m i t s the possibilities of the Omega network. Each basic permutation step,
which is equivalent to one stage in the Omega network,
performed during one or several t i m e steps. the head of
the queues,
is
In each t i m e step elements are taken from
shuffled and appended to the queues.
Associated with each
place in a queue is a one-bit flag whose value indicates if the corresponding data element should be shuffled during the current
p e r m u t a t i o n step.
A permutation step starts by
setting all the flags TRUE and ends when no queue has a TRUE flag in its head element. Long shows t h a t the maximum length of the queues is O(V~) and that the number of t i m e steps needed to perform an a r b i t r a r y permutation also is O(~/N).
26
L~
, 0 queue Shuffle
I queue
0 queue
E
'p 1 queuo I
~,
J
Figure 1,18 The modified one-stage shuffle/exchange network,
Parker has shown that three passes through an Omega network is enough to perform any permutation
of
the
input
vector
and
that
six
passes
is
enough
for
any
connection
(elements of the input vector could be broadcast to several elements in the output vector) [ParkerSO]o
He also claims that two passes might be enough for permutations - it has
been shown for N=4 and a computer simutation for N=8 gives the same result, Unfortunatety no simple algorithm for
the settings of the exchange elements has been
found to perform permutations in multiple passes through the Omega network,
Chapter 2 LUCAS SYSTEM ARCHITECTURE
2.1 SYSTEM OVERVIEW The LUCAS system consists of four parts: the Master Processor~
the Contrat Unit~
the
Processor Array and the [/O processor (Figure 2.1).
Master Processor
Peripheral Devices " ~ - - - ~ "
I/0 Proce]%>-
Control
Unit
Processor Array
J
Figure 2.1 Overview of the LUCAS system.
The Master Processor takes care of user interaction, Processor)~
input/output (together with the I/O
file handling and is responsible for sending instructions to the ControI Unit.
It is interchangeable and an ordinary mini- or microcomputer can be used.
Presently a
Prolog Z80 microcomputer system is used~ which includes a MATROX graphica[ display
28
processor,
a
printer
with
graphic
capabilities
and
a
[ink
to
the
LUNET
data
communication network at the U n i v e r s i t y of Lund. The Processor Array,
or Associative A r r a y ,
consists of 128 processors (Figure 2.2).
The
main parts of a processor are the Memory Module (MM) and the Processing Element (PE). The Memory Module is a /4096 bit memory,
where one bit is accessible at a time.
Memory Modules receive the same address f r o m the C o n t r o l Unit, whole memory
i.e.
area is accessible at a t i m e as indicated in Figure 2.2.
The Processing
Elements work on one-bit data and have four internal one-bit registers. uses data from "its own" Memory Module, to
route
data
from
modules as well.
the
memories
to
the
However, PEs.
All
a b i t - s l i c e of the
Most often a PE
an interconnection network is used This
allows data
access f r o m
other
The system works in full synchronism and the Processing Elements all
get the same control signals each clock cycle from the C o n t r o l Unit.
I
~J II El
I I I
i
! I !
!
t
i
I
I I i
I
I/0 shift registers
Memory modules
Interconnection
Processing elements
network
Select First network
F-igure 2.2 Schematic drawing of the Processor Array.
The ensemble of Memory Modules may be seen as one single content addressabte memory (associative memory). issued to template.
all the
Match/non-match
in each PE. Often,
A t y p i c a l case when this view is adequate is when a command is
Processing Elements to compare the memory contents w i t h is marked in one of the one-bit registers,
When a PE has its Tag set to one~
a certain
the Tag register,
we say that the PE is selected .
data f r o m the Memory Modules of selected PEs are to be read out to the Master
Processor.
To allow sequential access to these,
This takes the f o r m of a Select First network,
a m u l t i p l e match resolver is included. which keeps the f i r s t selected Processing
Element and resets the Tag registers in all the following PEs. can be used i t e r a t i v e ] y to select the PEs in sequence.
The Select First network
29
With every memory module there is an 8-bit shift register,
the I/O Register,
used for
input to and output f r o m the memory moduleo The
Control
Unit
(Figure
2.3)
receives
executes these on the Associative Array.
instructions
from
the
Master
Processor
and
Since the PEs work in a bit-serial fashion~
the
most obvious task for the Control Unit is to translate operations on data items (e.g.
81
16
is
or
32
bit
words)
microprogrammable. Unit itself~
to
sequences
of
The microinstructions
bit partly
p a r t l y direct the Processor Array.
operations. direct
The
Control
Unit
the sequencing of the Control
The set of control signals sent to the
Processor Array consists of:
the bit address to the Memory Modules a function code for the PEs an interconnection selector code * control of memory writing~ The Instruction Register, the
IR,
operands are specified
the [/O Registers and the Select F i r s t - n e t w o r k
holds the current instruction.
in the
Parameter Registers~
parallel addition of two vectors is shown in Figure 2.4. illustrated in this example, same instructions.
The locations and length of PRI...PR4.
As an example,
An important feature of LUCAS,
is the a b i l i t y to t r e a t operands of d i f f e r e n t lengths with the
No extra bits that do not carry any information have to be brought
through the computations. An i m p o r t a n t part of the Control Unit is the Address Processor~
which performs fast
computations of addresses to bit-slices in the Memory Modules (increment, add constant~
compare,
The Control U n i t
also contains a Common (Comparand) Register and a Mask Register,
each 4096 bits wide.
The Common Register holds arguments~
computations by all the PEs~ e.g. item
in all the PEs.
Register
may
decrement~
etc.).
influence
which are used in the
search arguments or constants to be added to a data
Through a test input to the Sequencer the contents of the Mask the flow
of
microinstructions.
Register is to mask out certain bits in search operations.
The normal use of
the
Mask
30
[
JR
]
PRI PR2 PR3
I nstructions TO MASTER PROCESSOR
PR4 Status Microprogram Sequencer
Address Processor
Microprogram Memory Common R e g i s t e r Mask R e g i s t e r
Processor Array Control
Bit-slice Address
Status
TO PROCESSOR ARRAY
Figure 2.3 LUCAS Control Unit.
In applications where very fast input/output is required the dedicated I/O Processor acts as a microprogrammabte interface between various peripheral devices and the Processor Array,
The I/O Processor inctudes a Buffer Memory and an Address Processor.
The
l a t t e r is capable of generating various address sequences to the Buffer Memory in order to reconfigure data according to the input/output conditions at hand. The Master controls the I/O Processor and the Controt Unit in a similar way,
31
CONTROL UNIT
I
ADDFA
3
source
IR
source 1
sou rce 2
i
I
]
PR 1
source 2
PR 2
dest
PR 3
length
PR 4
dest
I I I I I
I
I J
l I
I
I
I
i
I
i
I
I
i
PEs
]ength Figure 2./4 I l l u s t r a t i o n source2,
]ength
of the f o u r - p a r a m e t e r i n s t r u c t i o n dest~
length,
"add fields a l l ' :
ADDFA
sourcet~
32
2.2 CONTROL UNIT 2.2.1 O v e r v i e w The Control Unit,
see Figure 2.5,
has two parts: an interface to the Master and a
microprogrammable execution unit which commands the bit-serial processing in the PEs.
Master Buses
PRI Bus Contro] Status
PR2 PR3 PR4 Mi crop rog ram Sequencer
~I-12 Address Processor
Microprogram Memory
~
j
80
12
ipeline Register
r
I
......l Stack
' Common Register Mask Register
1 SOME
1 16 ProcessorArray Control
12 Memory Module Bit-slice Address
Common
Figure 2.5 LUCAS Control Unit.
LUCAS and the Master communicate via the following registers, the memory space of the Master in the current implementation;
which are mapped into
33
* Instruction Register - I R * P a r a m e t e r Registers - PR1 ...
PR4
* Status R e g i s t e r * I / O B u f f e r Register * Common I / O Register * Mask I / O Register * PE ] / O Registers (one in each PE)
The Control Unit is m i c r o p r o g r a m m a b i e with a m i c r o p r o g r a m memory of 4 k words.
The
m i c r o p r o g r a m memory works in two modes=
* In run mode,
when it
is logically
organized as /4096 words,
each 80 bits
wide * In load mode,
when it is l o g i c a l l y organized as /40960 words,
each 8 bits
wide The mode of operation is determined by the Master Processor. Microprogramming controls
is horizontal,
the same part
of
in
the
sense that
the hardware.
each bit
or group of
bits
always
This organization allows parallelism between
microopevations on d i f f e r e n t parts of LUCAS. In order within
to support simultaneous
the
Control
Unit,
activities,
between the
several buses are used for
Master
and the
Control
Unit
communication
and between the
C o n t r o l U n i t and the I / O Register area in the Associative Array.
2.2.2 Instruction Timing
The
Master
Parameter
stores
instructions
Registers.
in
the
Instruction
Register
with
parameters
the Bus Control logic senses if the Instruction Register is empty, loaded and the Master gets an acknowledge signal.
Register already
the Bus Control logic sends
a non-acknowledge signal which results in the Master entering a w a i t state. the Instruction Register becomes free, is sent
to
the
the
in which case data is
If the instruction
contains an instruction whose execution has not yet started,
signal
in
When the Master tries to w r i t e data into any of these registers,
Master.
The
As soon as
the new instruction is leaded and an acknowledge Instruction
Register
together
with
the
Parameter
34
Registers are referred to as the instruction pip~line . To
protect
Instruction
the
contents
of
the
Parameter
Registers
from
being
overwritten~
the
and P a r a m e t e r Register area is not released a u t o m a t i c a l l y when the execution
of a new m i c r o p r o g r a m starts~
but is under m i c r o p r o g r a m control.
There is one other mode of communication between the Master processor and the C o n t r o l Unity
namely the " C o n t r o l Unit Driven I n t e r r u p t " mode (CDI mode).
programs that asynchronous
concurrent
instructions
are
instructions
by
Master,
In this mode,
the
are executed in the Master and in the C o n t r o l Unit can be seen as two
located
processes. in
the
interrupting
the
They
Master's Master
are
asynchronous
memory~
and this
the
since
Control
is transparent
even
Unit
to
though
reads
the program
its
all own
in the
The t w o concurrent processes share two common resources: the I/O registers and
the Status Register in the Control Unit. resources~ So far,
To guarantee exclusive access to the common
s o f t w a r e semaphores must be used.
the possibilities of the CDI mode have not been fully investigated.
more used~
more e f f i c i e n t
should be considered.
The reason for including this mode~
handle
more
and
involves
If it wilt be
ways of synchronization and p r o t e c t i o n of common resources
overhead~
synchronization problem has been found~
is
that
once
which seems more d i f f i c u l t to an
efficient
programs can be w r i t t e n
the instruction scheduling mentioned earlier.
solution
to
the
w i t h o u t the need for
As soon as instructions for the C o n t r o l U n i t
appears~
they are moved to an instruction buffer where they are fetched by the i n t e r r u p t
routine.
In a way this instruction buffer would act as a many-leveled instruction pipeline.
2.2.3 M i c r o p r o g r a m Sequencer The M i c r o p r o g r a m microinstructions microinstruction divided into itself
Sequencer~
Am2910 [ M i c k
in the Centre[
Memory.
and Brick 80], At
generates the addresses to
the beginning of
a cycle~
(control word) is loaded into the Pipeline Register.
several fields~
is c o n t r o l l e d
by three
each c o n t r o l l i n g fields:
one field
one part of the hardware. defines the instruction
the
current
The control word is The Sequencer
to the Sequencer~
one field specifies the address in case of branch instructions and one field selects a test condition to be used for conditional branching.
The T e s t m u l t i p l e x e r gates d i f f e r e n t signals
to the test input of the Sequencer:
* The current value of the Mask Register output. * The state of the Busy flag~ been loaded. Zero Address Processor status.
which indicates if the Instruction Register has
35
Zero Loopcounter status. * Some/None status from the PEs.
2.2.4 Address Processor
A 16 bit f i e l d of the m i c r o i n s t r u c t i o n Array=
operations performed
input/output
etc.
is used to control the a c t i v i t y
in the ALU:s,
in the Associative
the set-up of the interconnection
Since all computations are bit-serial,
network,
it is i m p o r t a n t that the Control
Unit can generate the bit addresses needed at a high rate. For example,
to add two fields in the Associative A r r a y (ef.
Figure 2.4),
the f o l l o w i n g
sequence of bit addresses should be generated by the C o n t r o l Unit: source1
-
bit
g
/
used
to
fetch
bit
0 of
source
1
source2
-
bit
0
/
used
to
fetch
bit
0 of
source
2
/
used
to
store
the
result
destination
-
source1
-
bit
source2
-
bit
destination
bit
0
bit
0
1 1 -
bit
1
The part of the C o n t r o l Unit which handles this is the Address Processor.
The Address
Processor is a 12-bit processor capable of doing the integer a r i t h m e t i c needed for address computations. Register
A
and
calculated.
new
used to
address is generated access the
Associative
each clock Memory
cycle,
while
stored
in the
Address
the next address is being
]n this way the Address Processor introduces no delay in the execution of
microprograms. The
Address
(Am2901A)
Processor
registers and an ALU. internal
is
implemented
with
three
4-bit
bit-slice
and an external data memory organized as a LIFO stack.
registers~
The stack holds 32 12-bit values.
the LIFO stack,
Operands to the A L U are the
the P a r a m e t e r Registers,
(see Section 2.2.6) and a field of the control word.
microprocessors It has 16 internal
the I/O B u f f e r
Register
36
Operations can be performed on;
- any single operand -
any pair of internal registers
- any register and the top element of the stack - any register and the data presented on the data input
The result
of
an operation
is always stored in the Address Register.
It
may atso be
w r i t t e n back into one of the internat registers and it can be pushed on the stack,
37
Parameter Register Microinstruction Constant I/0 Buffer Register
Stack R0
RI R2
X D~ata
R15,
Inp!t/
t
oou 1
t-
Instruction
l;,:oL r tr
.T I Address Register 1
Bit Address
ZAP
ZLC
Figure 2.6 The Address Processor.
In order to reduce the number of bits needed to control the Address Processors
a subset
of sixteen instructions have been chosen and a PROM is used to code a 4-bit field of the microinstruction
into the 10 bits needed to control the Am2901A,
instruction to the Address Processor~
In addition to the
the microinstruction contains two 4-bit fields which
independently select two of the internal registers for operands (REGA and REGB), Table 2.1 summarizes the instruction set of the Address Processor.
In the tables
REGB
stands for the internal register addressed by the REGB field of the microinstruction and (REGB) for the contents of this register,
D A T A stands for the value of the data inputs.
38
Mnemonic
Internal
Operation
Output
None DATA -> REGB (REGA) - > REGB ( R E G B ) + I - > REGB ( R E G B ) - I - > REGB (REGA)+DATA -> REGB None (REGB)+(REGA) - > REGB ( R E G B ) - ( R E G A ) - > REGB ( R E G B ) + I -> REGB ( R E G B ) - I -> REGB (RECdk)+DATA -> REGB (REGB)+(REGA) -> REGB ( R E G B ) - ( R E G A ) ->REGB DATA -> REGB None
TBZ LDBD LDBA IPCCB DECB AD/~D TAEQB /MZ)BA 5UBBA A lNC:B /~Z)ECB AADAD A~BA ASUBBA ALDBD PLADR
( REGB ) DATA (REGA) (REGB) + t ( REGB ) - 1 ( REGA ) +DATA ( REGB ) - ( REGA ) ( REGB ) + ( REGA ) ( REGB ) + (REGA) ( REGA ) (REGA)
( RECA ) ( REGA ) ( REGA ) ( REGA ) DATA
Table 2.1 Address Processor Instructions
An
instruction
typically the
the
Master
to
the
Control
Unit
often
indicate the location of data within the PEs.
Master
started~
from
includes parameters which
These parameters are stored by
in the Parameter Registers and once the execution of the instruction the
contents
of
the
Parameter
Registers
can be loaded into
the
has
internal
registers of the Address Processor through the data input. A zero-indicator senses an all-zero output f r o m the Address Processor and generates the ZAP (Zero Address Processor) signal~
which is fed into the Testmultiptexer.
This allows
the use of the internal registers as loop counters for m i c r o p r o g r a m looping. Since
the
inner
loops
of
bit-serial
arithmetic
operations
tend
Processor busy in each clock cycle (recall the example above)~ been incorporated
in the Control
Unit,
This 12-bit
sources as the data input to the Address Processor.
to
keep
the
Address
an extra loopcounter has
counter is loaded f r o m
the same
In this way i t is possible to load Jt
d i r e c t l y f r o m a Parameter Register to be used in unnested loops,
in nested loops the
i n i t i a l loopcounter value is held in one of the internal registers of the Address Processor. To set up the innermost [oop~ into
the
Ioopcounter.
Address Processor,
this value is pushed on the stack and then popped back
Loopcounters
for
the
outer loops are handled internally
in the
39
2.2.5 Common and Mask Registers The Control Unit also includes a Common and a Mask Register. size as the PE memories, Register.
4096 bits;
They are of the same
and are addressed by the contents of the Address
Input and output of data is handled through their corresponding [/O Registers
which are 8-bit shift registers,
also accessible f r o m the Master.
has been loaded from the Master, under microprogram control. on the COMMON line.
When an I/O Register
the data is moved into the Common or Mask Register
The output from the Common Register is sent to the PEs
The Mask output is connected to the Testmultiptexer.
In operations where one of the operands is a scalar,
for example in parallel search
operations or when adding a constant to a field in the Associative Array, Register is used to hold this operand.
the Common
The role of the Mask Register is to mask out
certain bits when the operations are performed.
In bit-serial operations,
the Sequencer
can use the mask value to conditionally skip certain addresses by "short-circuiting"
the
loops. The need for a Mask Register in the Control Unit is not evident because its task can apparently be handled by the Address Processor. Associative
Array
can
be loaded
into
the
However,
Mask
microprogram makes it useful in several algorithm% Mu!t!plication. value,
Register
the fact that data from the during
the
execution
of
a
for example:
If we want to m u l t i p l y all the elements of a field with the same
the value is moved to the Mask.
an algorithm which skips over strings
M u l t i p l i c a t i o n can now be performed using
of O's and 1"%
resulting in a significant
speed-up over the standard algorithm (adding and shifting in each step), used to multiply two fields on LUCAS. bit-serial computer,
which is
(Note that this is particulary i m p o r t a n t on a
since addition to the p a r t i a l product takes much longer t i m e
than simply shifting it).
2.2.6 I / 0 Buffer Register An i m p o r t a n t communication link in the Control Unit is the I/O Buffer Register. used to move data from selected.
a selected PE to the Control Unit.
First
It is
one PE should be
This is accomplished by either a complete associative search or by loading the
Tag Registers with
a bit
slice from
previous search may be stored. the Select First chain,
the Associative Memory,
To complete the operation,
in order to make the selection unique,
Read Selected) signal to the PEs.
where the result
of a
the Control U n i t activates and sends an IORS (I/O
The selected PE puts the 8 bit contents of its I/O
Register on the I/O Data Bus to be loaded into the I/O Buffer Register.
40
Once the value has been loaded into the I/O Buffer Register it can be used for several purposes:
The
contents
Registers
of
in
the
all
communication
I/O
the
pattern
selects a data source~
Buffer
PEs.
Register
This
may
be
possibility
between the
PEs:
written
permits
a
into
the
very
[/O
flexible
one associative search operation
a second search selects one or several destinations.
The [/O Buffer Register may be read by the Master.
This implements the
data output register of the Associative Memory. Its contents can be copied into the [/O Register of the Common or the Mask Register. where
In this
the
first
way it
is possible to perform
associative
search
selects
the
linked search operations~ key
to
the
next
search
operation. The 8 bits of the 1/O Buffer Register, be
loaded into
padded with zeroes to the [eft,
the Loopcounter or into
the Address Processor,
may
allowing
indirect address links and ]oop values to be stored in the Associative Memory,
2.2.7 Status Register The Master Processor may at any t i m e interrogate a Status Register in the Control Unit, The Master has only read access to this register.
The status information given contains
the following six bits: BUSY
indicates that the instruction pipeline is full.
NONE
When this status bit is TRUE r
none of the PEs has its Tag set.
A f t e r an
associative search it is often usefui to know whether any word matched the search criterion. ZAP ZLOOPC
This bit indicates Zero Address Processor status, This
bit
indicates
Zero
status
of
the
Loopcounter
in
the
Address
Processor.
sllsz
Two
general
purpose
signals
from
the
Control
defined by a t w o - b i t field of the control word,
Unit.
Their
values are
They can for example be
used to indicate the progression in a running microprogram.
41
2.3 P A R A L L E L
PROCESSING A R R A Y
2.5.1 Processing Elements A Processing E l e m e n t (Figure 2.7) consists of four parts:
* A set of
one-bit
* An A r i t h m e t i c
registers:
T(tag),
R(result),
C(carry),
and X ( a u X i l i a r y ) .
Logic U n i t (ALU).
* A D a t a Selector. * Part of a n e t w o r k that i m p l e m e n t s the SELECT FIRST and SOME functions.
Data Select
FROM CONTROL UNIT From Common Register
SELECT FIRST
Part
RO-
0
M
of
SELECT FIRST network
0
From 0 I ntero Connect ion Network o o 0 X 0
Select Chain in
Function
l
S~1 e c t Chain Out
ALU co
T R
/
C ----~. C
XO
Figure 2.7 A Processing Element.
2.5.1.1 Registers The four registers, The
T
(Tag)
corresponding
T,
register Memory
R, has
C, its
Module.
and X,
have slightly d i f f e r e n t features.
output Thus
connected it
to
the
write
control
can be used as a c t i v a t i o n
logic
control,
of
the
inhibiting
42
change in the memory of those PEs where T equals zero. is connected to the SELECT FIRST-network, Unit resets all Tag registers but one, linear ordering of the PEs.
Furthermore,
the Tag register
which on a control signal from the Control
namely the one with the lowest number in the
The Tag register is also the input to the SOME-network.
This network indicates to the Control U n i t whether some or none of the Tags are set. Finally,
the Tag register controls the I/O
Register of the Memory Module in a way
described below. The R (Result) register is the only register from which data may be w r i t t e n directly into the memory, The C (Carry) register is a general purpose register.
In a r i t h m e t i c operations it is used
to hold the carry bit. The X ( A u X i l i a r y ) register is also general purpose. the ALU.
instead,
Its output is not directly connected ta
one of the Data Selector inputs is used,
as shown in Figure 2.7.
2.3.1.2 A r i t h m e t i c Logic Unit A bipolar Programmable Read Only Memory (PROM) serves as arithmetic logic unit. size of the PROM Js 1024 words of /4 bits each.
The
Five inputs are used to specify the
function; thus 32 functions are available.
Al[ PEs receive the same function code f r o m
the Pipeline Register in the Control Unit.
The remaining five inputs are data inputs.
Since the functions are specified by the contents of a PROM they can easily be altered to suit a specific
application.
An " A L U
assembler" has been w r i t t e n to generate the
PROM contents from the boolean expressions defining the four outputs. A general purpose function set which has proved to be applicable in a wide v a r i e t y of computational
areas~
including
image
processing,
signal
processing
and
data
base
processing is listed in Appendix 1.
2.3.1.3 The Data Selector The
Data
Selector allows a Processing Element to
receive data from
eight
Memory Modules according to the wiring of the Interconnection Network.
different
One of the
eight sources is fixed to be the output of the associated Memory Module (the D input). The remaining seven inputs can be wired to any source. Select cede.
All PEs receive the same Data
43
2.3.t 4 The SOME and SELECT FIRST n e t w o r k s The o u t p u t of the S O M E - n e t w o r k indicates to the C o n t r o l Unit w h e t h e r some or none of the Tag registers are set.
i t has the s t r u c t u r e shown in Figure 2.8,
giving a depth of 16
gates when the number of PEs is 128. When the register
Control
is to
combinatorial
Unit
remain network
issues the set to on% with
the
8-input
gates in the
FIRST
command,
all others are reset.
states
signals to the registers as outputs. the
SELECT
of
all
the
only one (the first)
Tag registers
as inputs
To reduce the depth of the n e t w o r k ,
SOME-network
are used as look-ahead.
SELECT FIRST n e t w o r k is shown in Figure 2.9.
TI--~-
T7 - T 9
-
-
TI5 T16-T17--%. T23
-
T120 TI21
-
Tag
This is done by an i t e r a t i v e
-
-
Figure 2.8 The SOME-network. TI2 7 .....
SOME
and C L E A R
the outputs of
The s t r u c t u r e
of the
44
SELECT SOME FIRST IN
\
TOT1
T7
"\
\~'\
\ ....
\\
\
\
\ \
\
\
\
\ \
Figure 2.9 The SELECT FIRSTProcessing Elements.
\
and
\ SOME-
network
of
a board
of
eight
consecutive
45
2.3.2 M e m o r y Modules and i n p u t / o u t p u t s t r u e t u r e With
each of
the
Processing
Elements
f a c i l i t y for input and output of data.
there
is a M e m o r y
Bit address
sh f t
Write a11
and a
Write
WR 4096 bits
DI
~
Modu|e of /4096 bits
Figure 2.10 shows one of the modules.
I~
DO
Data Selector
f
rom R register
shift
I / 0 data reg i s t e r ....
4
Master or
IRead
I/0 Processor
i
Write
Figure 2.10 A M e m o r y Module w i t h its I/O Register.
The m e m o r y , time,
which is an ordinary 4096 x 1 r e a d / w r i t e
receives a 12 bit address f r o m
When W r i t e - A l l writing
m e m o r y chip w i t h 55 ns access
the C o n t r o l U n i t and t w o d i f f e r e n t
is a c t i v a t e d all M e m o r y Modules are w r i t t e n
int%
w r i t e signals.
whereas Write
gives
in a module only if the Tag register of the corresponding Processing E l e m e n t is
set to one, The
4096
Memory,
bit
memory
PEs w i t h
will
sometimes
the Tag register
be r e f e r r e d set w i l l
to
as a "word"
be r e f e r r e d
of
the
Associative
to as selected PEs,
and the
associated words as selected words. The 8 - b i t
l/O
Registers are used for
input and output
A s s o c i a t i v e A r r a y is in the f o r m of vectors, one m e m o r y time,
word.
The m e m o r y
of data.
words can only input or output one bit
but this may be done in all the 128 words simultaneously.
transform
the data f o r m a t b e t w e e n 8 bits in parellel~
bits in parallel,
Usually,
in the orthogona! d i r e c t i o n .
data in the
w h e r e each i t e m of the v e c t o r is stored in of data at a
The 128 ][/O Registers
as seen by the Master,
and 128
46
A data input process can be divided into two phases: one to f i l l the I/O Registers from the Master processor or the I/O Processor, Array.
The first
one to shift the contents into the Associative
phase needs one w r i t e cycle of the Master or the t/O Processor to
transfer 8 bits,
the second phase transfers 128 bits in one Controt U n i t clock cycle.
The Master w r i t e cycle is several times longer than the clock e y r i e period.
The I/O
Processor w r i t e cycle is of the same length as the clock cycJe.
2.3.3 Communication Between Elements
Two
distinct
paths for
communication between PEs are present: the I/O
Bus and the
Interconnection Network.
2.3.3.1 [/O Bus Communication over the I/O Bus is used to send data from one selected PE to all or to a subset of the PEs,
to the Common or to the Mask Register.
One byte is moved from
its source to its destination(s) as follows: t)
Copy the source field into the I/O Registers
2)
Select the source PE by setting its Tag register to One
3)
Perform
a
READ-SELECTED
operation,
which
copies
the
I/O
Register
of
the
selected PE to the I/O Buffer Register Perform an IOWRALL operation. all the I/O
5)
If
Registers,
including
the destination is Common or
corresponding I/O Register. corresponding
Tags
and
The [/O Buffer Register contents is broadcasted to those of
the Common and the Mask Registers.
Mask then perform
a bit-serial input
from
the
If the destination is one or severat PEs then set the
perform
a
tag-masked
input
[n applications where LUCAS acts as an associative memory, used as a data register for input and output.
To r e t r i e v e data,
Buffer Register after step 3 in the procedure above.
from
the
I/O
Registers
the I/O Buffer Register is the Master reads the I/O
Data which should be w r i t t e n into
the Associative Memory is first placed in the I/O Buffer Register whereafter steps 4 and 5 are executed.
47
2.3.3.2 Interconnection N e t w o r k The interconnection network comprises a 128 b i t wide bus and the Data Selector in the PEs.
The outputs of the PE memories are connected to the interconnection bus,
one line is reserved for each PE.
On the input side~
used to connect each PE with its memory,
where
one input of the Data Selector is
and a strapping area on the PE boards allows
the remaining seven inputs to be connected to any of the 128 lines on the bus (see Figure 2.11). Conceptually,
communication
over the interconnection
network differs in several aspects
f r o m communication over the I / O Bus.
* The source and the destination of all links are f i x e d and not data dependent. * Transport pairs,
of
data
is done
in
parallel
between
different
source-destination
resulting in a permutation of the input data.
Communication
between PEs,
where no d i r e c t link exists,
can be obtained
by m u l t i p l e passes through the network.
Interconnection However,
structures
suitable
for
specific
applications
can
there is also a need f o r a general purpose network~
in a f l e x i b l e way,
be
wired
on
LUCAS.
capable of permuting data
hopefully useful in many application areas.
As a general purpose interconnection network for LUCAS, structure has been chosen.
the perfect
shuffle+exchange
The main reasons are: (1) the generality of the network,
(2)
the few connections needed - only two per PE - and (5) the e f f i c i e n c y of the network for calculation of the Fast Fourier Transform (as shown in [Pease68] and [Stone71]), useful in both signal and image processing.
which is
48
Memory
Module ~
I PE ,
Memory Module I PE 1
" Interconnection" Network .
Memory Module 127 ] PE ,27
128-bit data bus F i g u r e 2.11 I n t e r c o n n e c t i o n structure.
The Data Selector of each PE has t w o inputs f r o m this n e t w o r k - one "shuffle" one
"shuffle+exchange"
Selector is used, used,
input - as shown in Figure
a perfect
both p e r f e c t
shuffle
is made.
2.12.
If
the S input of the Data
If the N (=Neighbour's
shuffle and exchange are made.
input and
shuffle)
input
is
Thus the exchange o p e r a t i o n takes
no e x t r a t i m e . Using the Tag registers as a mask,
individual box c o n t r o l may be used on LLICAS.
This
w i l l be described tater. The p e r f e c t shuffle+exchange structure w i t h individual box control is generally regarded as the most useful general purpose i n t e r e o n n e c t i o n scheme for SIMD computers~ capable of r e a l i z i n g the most f r e q u e n t l y used p e r m u t a t i o n s ([Stone71], and L a w r i e 81]).
In spite of thi%
SIMD c o m p u t e r to use this n e t w o r k .
since it is
[Lawrie76]~
[Yew
L U C A S is - to our knowledge - the f i r s t o p e r a t i o n a l
49
from MB no. <0 p 6 P 5 P 4 P 3 P 2 P l > - ~ - - - -
PE no.
from MM no. ---~
PE no.
Figure 2.12 Connections
to
Data
Selectors
for
the
realisation
of
the
Perfect
Shuffle+Exchange network.
The Interconnection Network above and below,
on LUCAS
also includes data paths from
as shown in Figure 2.13.
the neighbours
These are often used in image processing.
One input to the Data Selector is the output f r o m the X-register of the PE. All Data Selectors receive the same Data Select code from the Control Unit. there is no direct possibility to implement individual box control, that some Data Selectors choose the Shuffle input, i t has to be done in two steps, setting.
In the first step,
Shuffle input.
because this requires
and some the Shuffle+Exchange input.
using the state of the Tag register to decide the box
the R registers of all words are loaded from memory via the
In the second step,
only in selected words,
Therefore,
the R registers are again loaded from memory,
and now using the Shuffle+Exchange input.
but
50
Data Select Code
I
Direct \ Shuffle
S
Shuffle + exchange
a - - A
Above
B
Below
X-register
Figure 2.13 Implemented
connections
From a general point of view,
to
the
Data
Selector of the Processing Element.
data communication over the interconnection network is
useful when the interconnection structure is regular and independent of the data values. It
has
been
Transform.
used
in
e.g.
matrix
operations,
image
processing
and
Fast
Fourier
Communication over the I/O Bus is used in applications where the associative
feature of LUCA5 is predominant, which PEs should communicate,
which means that the current data values determine
i t has mainly been used in database processing.
2.3.4 [/O Processor Computing systems using parallel processing often become [/O bound,
i.e.
the system is l i m i t e d by the capacity of the input/output channel.
To avoid this,
dedicated [/O
Processor [Kordina83] has been attached to LUCA5,
transfer rate from 0.8 Mbytes/second to 10 Mbytes/second.
the speed of a
increasing the data
This allows e.g.
transfer from a disk drive or from an A/D converter sampling a video signal.
fast data
51
Often,
the data comes from the peripheral device in a f o r m a t not suitable for direct
|oading into the Associative A r r a y of LUCAS. line-wise but Processor
For examp[%
an image is usually read
should in some cases be stored in another f o r m a t
is designed to
take care
of
in LUCASo
such necessary rearrangements of
The [/O
data.
It
is
equipped with a Buffer Memory and an Address Processor capable of generating various address sequences.
For rearrangement of data,
the address sequences when w r i t i n g and
reading data t o / f r o m the Buffer are different. The
I/O
Processor diagram
Processor
is
and w i t h
an Am2910
of
the
constructed
processor.
with
Am2901
microprogram MuJti-]eve|
bit-slice
sequencer.
pipelining
is
processors Figure
used
as
the
Address
2.14 shows a brock
because
of
the
speed
requirements.
FROM
CONIROLUNIT
INTERNAL DATA BUS
111111 TO [/0
~GISTB~S
Figure 2.14 The I/O Processor.
The [/O Processor is controlled by the tvlaster Processor through a set of registers mapped into the m e m o r y space of the Master. The
Instruction
Register
(IR)
receives
The registers have the foilowing functions: the
start
address of
the
microprogram
to
be
52
executed.
The register is 8 bits wide.
Parameter Register 1 (PAR1) is used to specify the number of bytes to be read or loaded each time the microprogram is executed.
The register is 12 bits wide.
Parameter Register 2.,.5 (PAR2..,5) are general purpose registers and the use of them depends on the task. Registers, the
in one task where data is loaded into the I/O
the parameters would represent: start address of the Buffer Memory where
data is read, receive
For example~
step size of the buffer address, data and,
finally,
the
number of
start address of the I/O Registers to times this
microprogram should be
executed. Microprogramming of the I/O Processor is similar to microprogramming of the Control Unit.
2,3.5 Physical Descript!q.n The Processor Array,
consisting of
Modules and input/output circuitry, (Photo 2.1 (a)).
128 Processing Elements with associated Memory occupies 16 double layered printed circuit boards
Each board of eight processors measures 220 x 230 mm (Photo 2.1 (b)).
It contains a total of 70 IC packages - 59 implement the processors and 11 are signal buffers and 1/O address decoding circuitry. The Processor Boards are mounted in the top rack of a 2000 x 800 mm cabinet. 2.2).
Immediately below resides the Control Unit which occupies two boards.
(Photo A third
board in this rack contains the circuitry necessary for the loading of mieroprograms into the Microprogram Memory and also a display of the microinstruction word,
which was
used for debugging of the hardware. The next rack contains the Master Processor. bus boards.
It is a Z80 system built from Prolog STD-
It also includes a floppy disk unit and a graphical display system.
53
(a)
(b)
Photo 2.1 (a) The 16 Processor Boards (b) A Processor Board comprising eight Processors
Photo 2.2 LUCAS
Chapter 3 BASIC INSTRUCTIONS
In this chapter we wilt describe the basic types of instructions that can be performed on data in the Processor Array,
Examples of the different instruction types are given and
execution times are calculated.
3.1 CLASSIFICATION OF INSTRUCTIONS At
each moment one bit from each Memory Module is accessible by the PEa.
together these bits form a bit-slice of the total memory. be referred to as the associative memory (AM), a field of the AM.
Taken
The total memory will often
A number of consecutive bit-slices form
(Since the memory chips are of random access type,
that the bits must be consecutive is not necessary~
the constraint
but this is normally the case).
The
contents of the Tag registers may be used to mask out certain words in an operation, We use the term registers.
selector to refer
to the bit vector describing the contents of these
A selector may be stored in a one-bit field of the associative memory.
3.1.1 Basic Types of Instruct!0ns Operat!qg on the Associative Memory The instructions used to manipulate data in the associative memory may be classified according to the types of operands and the types of results. constant,
stored
in the
associative memory. of operand).
Common
P,egister~
or
a vector,
An operand may either be a stored in
a field
of the
(We will use "field" and "vector" alternatingly to denote this type
The result of an operation is either a field or a selector,
i.e a one-bit
field. A selector can always be used in an operation to mask out some PEa. be regarded as an operand,
present in all operation types.
this when we list the different types below.
Thus~ it may also
We do not e x p l i c i t l y indicate
55
This v i e w results in the following six basic instruction classes,
each one illustrated in
Figure 3.1.
(a)
-->
Examples:
Increment field Copy field Permute field (the v e c t o r in the destination field is a certain permutation of the v e c t o r in the source field)
(b)
--> <selector>
Examples;
Maximum value of a field Minimum value of a field
(c)
-->
Examples:
Add fields M u l t i p l y fields M a x i m u m of fietds (The
elements
pairwise
and
of the
the
source
maximum
vectors
of
them
are is
compared
put
in
the
destination field) AND between fields
(d)
--> <selector>
Examples:
Field equal to field (The selector w i l l mark those words where the elements of the two fields are identical) Field greater than field (The
selector
elements
of
will
mark
those
source
field
1 are
words greater
corresponding elements of source field 2)
where
the
than
the
56
(e)
-->
Examples:
Add constant M u l t i p l y by constant Subtract constant Subtract from constant AND w i t h constant
(f)
--> <selector>
Examples:
Exact match Closest match Greater than constant
These basic instruction
types can be combined to
get other types.
consider the merging of two vectors to produce a third vector. selector is used.
In those words,
where the selector is 0,
As an example,
To control the merge,
a
the element of v e c t o r 1 w i l l
be chosen; in those words where the selector is 1 the elements of v e c t o r 2 w i l l be chosen (see Figure 5.2). many different,
i f other inputs to the Data Selector than the direct input are used, useful merges can be obtained.
The merge operation actually is the
result of two successive -to- operations, d i f f e r e n t selectors,
using d i f f e r e n t source fields and
one selector being the complement of the other.
57
(a)
source
(c)
source
2
I
source
2
sou r c e
~
field>
~ <se]ector>
P#/J~
of
field>
~
field>
~ <se|ector>
]
SOU r c e
types
des t
(f)
Basic
field>
I
(e)
F _ ~ u r e 3.1
dest
I
I
~ <selector>
dest
(d)
source
dest
sou rce
I
~
dest
(b)
source
dest
instructions
operating
on t h e a s s o c i a t i v e
memory
58
source
source
destination
2
selector
0
A
A
I
I
B
I
0
2
C
2
0
3
D
D
I
4
E
E
I
5
F
5
0
6
G
6
0
7
H
H
I
Figure 3.2 Illustration of a Merge operation
The specification of an instruction includes the operation and up to four parameters. basic instruction types listed above require between two and four parameters. and (f) require two parameters (field address and field length).
Types (a),
require three parameters (two field addresses and the field length). requires four parameters (three field addresses and the field length). special case%
Types (b) (d) and (e)
Type (c),
finally,
Of course,
the value of parameters may be implied in the operation - e.g.
destination field being one of the source fields,
The
in the
or the length always being eight bits.
3.1.2 [/O Instructions For transfer of data between the associative memory and the outside wortd~ between the associative memory and the Common and Mask Registers~ are used.
However~
associative memory. storage,
and aiso
the I/O registers
these can also be used for data transfer between words of the In the l a t t e r case the I/O Buffer Register is used as temporary
as described in Chapter 2.
Instructions that involve the I/O registers are the following:
59
(a)
-->
(b)
--> A selector may be used as a mask.
(c)
--> This instruction puts the contents of the selected I/O register in the I/O Buffer Register. The selector must have one single "1 ".
(d)
--> 4I/O registers>
I/0 register>
<Mask I/O register>
This instruction puts the contents of the source register in all 1/O registers simultaneously.
I/O register instructions can likewise be combined to form instructions with other formats. As an example,
consider the case of moving the value of the selected word of one field
to all selected words (according to another selector) of another field.
This instruction,
which may be expressed as --> is a concatenation of the following ones; --> --> <[/O Buffer Register> --> --> using the second selector as mask.
in the following sections (5.2 through 5.4) we will give examples of basic, instructions.
widely useful,
Most of the example instructions have been implemented on LUCA5 and
they form part of a general purpose instruction set for the machine.
60
3.2 MOVES,
PERMUTATIONS
A N D MERGES
3.2.1 I n t r o d u c t i o n in
this
section
array.
we
Actually~
associative array.
present some basic merely
instructions
m o v i n g data,
without
for
moving data Jn the
changing
it,
is of
little
Since the c o m m u n i c a t i o n n e t w o r k is b e t w e e n the m e m o r i e s and the PEs,
data
array,
use in the
The reason for m o v i n g data is to put i t in position for o p e r a t i n g on it.
and operation can in many cases be combined. pure
associative
movement
takes place.
However,
One e x a m p l e
data m o v e m e n t
there are also situations where
is input
and output
to
and f r o m
the
another is the case when the data r o u t i n g preceding an o p e r a t i o n must be dane in
several steps because the possibilities o f f e r e d by the i n t e r c o n n e e t i o n n e t w o r k are l i m i t e d . A c o n t e x t where data m o v e m e n t s are c o m m o n is data base processing. moved
within
However, much
the
array
to
form
new
as is shown in Chapter
fiuples
8,
in the
tables
D a t a items are
in a r e l a t i o n a l
data base.
the need to move data is still r e l a t i v e l y small,
tess than when the same data structures
are stored in a c o n v e n t i o n a l c o m p u t e r .
3.2.2 Basic Moves An e x a m p l e of a pure move instruction is the "Load Outdata A l l " instruction L D O A source which
outputs
slice,
plus
an 8 - b i t time
for
field
to the I/O
parameter
registers.
loading,
etc,
This takes one clock in
total
11
cycle per bit
clock
cycles.
The
m i c r o p r o g r a m is included in Section 5.4.6.2 as an e x a m p l e of m i c r o p r o g r a m m i n g . A
pure
move
between
two
fields
in
the
associative
array
is
accomplished
by
the
instruction MOVE source,
destination,
length.
Each bit slice takes t w o clock cycles to move (one read, loading ete,
the t o t a l t i m e is 2b+6,
one write).
With
parameter
w h e r e b is the f i e l d length.
The i n s t r u c t i o n BROADCAST
source,
selector,
destination,
takes the contents of the source field
length
in the f i r s t selected m e m o r y word and broadcasts
it to the d e s t i n a t i o n f i e l d of ell words selected by the
"selector" b i t - s l i c e .
First,
data
61
is moved f r o m the source field to the [/O registers of all words, l/O register to the ]/O Buffer Register, destination
field,
24
clock
cycles
then from the selected
next to all I/O registers, are
needed
to
and finally to the
broadcast
an
8-bit
word,
3.2.3 Use of the [nterconnection N e t w o r k The perfect shuffle+exchange network of LUCAS is illustrated in Figure 3.3.
Memory Modules
Figure 3.3 The
principle
of
PEs
the
perfect
shuffle
+
exchange
network
in
LUCAS
In r e a l i t y - as described in Chapter 2 - the exchange function is controlled by choosing the 5 (as in Shuffle) or N (as in Neighbour's shuffle) input to the Data Selector of the PE.
Since all Data Selectors are controlled by the same signals,
chosen for all PEs.
Thus~
interchange state in others~ steps.
the same input must be
if we want to use the straight state in some PEs and the as shown in Figure
3.3,
the transfer must be done in two
The state of the Tag register is used to control which input is taken.
3.3 the Tags are "1" in the PEs that are to use the shuffle+exchange input. are transferred to selected PEs using this input.
data
Then the Tags are complemented and
data are transferred to selected PEs using the shuffle input. receive data over the shuffle input.
In Figure First~
Alternatively,
all PEs first
In PEs with T=t
these data are then o v e r w r i t t e n
w i t h the data arriving over the shuffle+exchange input.
The l a t t e r procedure is slightly
faster,
since the Tags need not be inverted.
62
3.2.3.1 Merges Since
the
transfer
f e t c h e d from
described above is a t w o - s t e p
different
contain data f r o m
fields in the t w o steps.
both the source fields,
and "O's in the Tags.
As an exampl%
process,
In t h a t
data may equaUy well
be
case the destination f i e l d wilt
i n t e r m i x e d according to the p a t t e r n of
"l"s
Figure 3.4 shows how the upper halves of t w o
fields are merged to form a new field.
[]
a~
a~
[]
b~
al
a4
[]
bl
[]
a2
al
[]
b2
[]
a3
a5
[]
b3
[]
a4
a2
[]
b4
[]
a5
a6
[D
b5
[]
a6
a3
[]
b6
[]
a7
a7
[]
b7
[]
a~
Step 2
Step I
O v e r w r i t e s e l e c t e d from s h u f f l e + exchange input
Load all from shuffle input
Figure 3.Z; Merging the upper halves of two fields
In a merge operation any of the eight inputs to the Data Selector can of course be used. A merge operation is fully characterized by * the addresses of the two source fields * the address of the destination f i e l d * the length of the fields * the Data Selector input used for data from source field 1 in PEs with T=I * the Data Selector input used for data from source field 2 in PEs with
T=O
* the selector (the contents of the Tags). All
these
cannot
be specified
in
the
instruction.
The
Data
Selector
inputs
must
be
63
implicitly specified by the operation code. into t h e Tags in advance.
We also assume t h a t the s e l e c t o r ~s loaded
Our example operation using the N and S inputs,
respectively,
is then expressed MEP, QENS source 1, In words,
source 2,
dest,
length.
we express this; Merge (source 1 shuffled+exchanged) with (source 2 shuffled)
into dest where T=I/0.
With t h e same selector, inputs instead of N and S,
the operation MERGEAD,
which uses the Above and D i r e c t
will merge the e v e n - n u m b e r e d e l e m e n t s of the two sources
into the d e s t i n a t i o n field. The execution t i m e for merge operations on b-bit data is 5b+6. clock
cycles,
or 6.0 microseconds using a 5 MHz
With b=8 this makes 50 Another kind of
merging
operation is the following: The elements of two vectors are compared pairwise,
and the
m a x i m u m of them is put in the destination field.
clock.
This merge is not controlled by the
Tag contents but by the data itself.
3.2.4 A u t o m a t i c Routincj
As has been shown in [Lawrie75] many frequently useful p e r m u t a t i o n s can be done by the Omega network,
which in turn can be i m p l e m e n t e d by n passes through a single-stage
p e r f e c t shuffle+exchange network c o n n e c t i n g 2 n m e m o r i e s with 2 n processors. gives a very simple
algorithm
to
find the switch s e t t i n g s necessary
Lawrie also
for performing
a
certain permutation (see Section 1.4.2). When choosing the switch setting of a certain exchange element according to this scheme, conflicts
may
of
simultaneously.
course
arise
Both inputs may,
when
many
data
for example,
items
are
routed
in
the
want to use the lower output.
network Figure
3.5 shows a c o n f l i c t - f r e e permutation; Figure 3.6 shows one which cannot be implemented in n stages.
In the t a t t e r figure,
the unique path bringing a data i t e m from source 00t
to destination 010 has one connection - the last one - in common w i t h the unique path f r o m 01t to 011.
Therefore a c o n f l i c t occurs.
64
source
dest
dest 1
0o0
,00
o00
010
I11
010
01t
101
011
100
011
100
1
101
~
101
110
000
110
111
010
111
Figure 3.5 A c o n f l i c t - f r e e permutation.
The routing of source 101 to destination 110 is
specifically indicated source
dest
000
001
001
0t0
010
100
011
011
100
000
101
110
110
101
111
111
Figure 3.6 A
0
permutation
of
2.3
elements
that
cannot
be
performed
in
3
passes
Many of the permutations that cannot be performed in n passes can be performed in 2n passes - maybe all can.
Y e w and L a w r i e [ Y e w and Lawrie81] have suggested an extension
of I_awrie's algorithm~
which is capable of deciding switch settings for a large class of
permutations that can be performed in 2n passes.
The algorithm works as follows:
When a conflict occurs in the application of L a w r i e ' s algorithm, upper input is given the privilege to decide.
the control bit of the
This is the same as only using the control
bit of the upper input in all situations. Unfortunately,
Y e w ' s and L a w r i e ' s algorithm does not work for all permutations that
65
can be carried out in 2n passes.
The permutation in Figure 3,6 can be realized in 2n
passes,
but Y e w ' s and L a w r i e ' s algorithm does not find the
as shown in Figure 3.7,
necessary switch settings.
However,
used repeatedly,
it finds a switch setting for 4n
passes.
dest
source
dest
000
flOl
OOl
OlO
010
lO0
010
Oll
011
01%
IO0
OOO
1O0
lOl
llO
II0
lOl
111
111
000 OOl
101 II0 111
Figure 3.7 Realization of the permutation of Figure 3.6 in 6 passes
The strategy used to find the switch settings in Figure 3.7 can be expressed as follows: When a c o n f l i c t
occurs,
let the data i t e m
transferred on correctly; i f routed~
that has earlier been routed c o r r e c t l y be
both have been c o r r e c t l y routed earlier~
or both wrongly
choose the "straight" state.
3.2.4.1 I m p l e m e n t a t i o n
Algorithms
of
the
above kind can be used to
desired destinations. used
to
set
the
a u t o m a t i c a l l y route data
items to the
The destination address is simply sent along with the data and is routing
switches.
The
algorithm
of
Yew
and
Lawrie
has
been
implemented on LUCAS in the following way: Each word of the memory is assumed to contain one item of a data field and one i t e m of
a control
Furthermer%
field.
The l a t t e r
contains
the binary
address of
the destination word.
each ward is assumed to have a field containing the address of the word.
For i:= n-1 to 0 do Load the Tag registers w i t h the pattern 101010. 10.
Begin Merge (position i of control field shuffled) with (position i of shuffled+exchanged) where T=I/0. Put the result in the Tags. (Now,
control field pairs of PEs
66
have the same Tag contents). Merge (data+control field shuffled+exchanged) with (data+control field shuffled) where T=I/0. Put the result back in the same fields. End Compare control field and address field. procedure.
If any mismatch is found,
repeat the above
The Master Processor can determine the success of the routing by reading the "SOME" bit of the Status Register. The instruction needs four parameters, ROUTE data,
3.3 SEARCHES,
control,
address,
The format is the following: data length
COMPARISONS AND LOGICAL iNSTRUCTiONS
Search operations on a set of data elements look for elements with specific properties, e.g.
the element(s) with the greatest numerical value,
argument,
those exactly matching the search
or pairs that consist of identical elements.
These examples represent three
different instruction types according to the classification given in part 3.t.1, types (b),
(f)~
and (d),
namely
respectively.
3.3.1 Type --> <selector> The instruction "Maximum of field, MAXT field address~
tagmasked"
length
marks in the Tag registers the word(s) (among the selected ones) with greatest value in the
field.
It
proceeds from
most significant
bit
to
least significant bit
discarding
candidates with a "0" in the current position if there are candidates with a "1". microprogram is included among the examples in Chapter 5. cycles.
Thus,
The
The time is 3b+5 clock
the maximum element in a vector of t28 8-bit data items is found in (3*8
+ 5)*200 ns = 5.8 microseconds,
using a 5 MHz clock.
67
3.3.2 Type --> <selector> The instruction "Compare fields, COMPFT source1,
source2,
tagmasked" length
marks in the Tag registers those words - of the selected ones - where the contents of the t w o fields are identical. R f r o m M-input, ALU.
This is accomplished by a series of successive L R M A (load
all) and CRMT (Compare R to M-input,
The t o t a l t i m e is 2b+6 clock cycles.
4.4 microseconds,
With b=8,
tagmasked) instructions to the 22 cycles are needed,
which is
using a 5 MHz clock.
The instruction "Field greater than field, GREAFT source1,
source2,
tagmasked"
length
marks in the Tag registers those words - of the selected ones - where the contents of field 1 is greater than the contents of field 2. the result only the sign bit is used.
A c t u a l l y a subtraction is made,
]f o v e r f l o w occurs in the subtraction,
inverted so that a correct result is obtained also in this case. clock cycles,
which for b=8 yields 23 clock cycles,
but of
the sign is
instruction t i m e is 2b+7
or 4.6 microseconds,
using a 5 MHz
clock,
3.3.3 Type , --> <selector> The instruction "Compare field to Common, COCOT field_address,
tagmasked"
length
marks in the Tag registers those words - of the selected ones - where the contents of the examined field is identical to the contents of the same field in the Common Register.
Since bits f r o m both operands can be input to the PEs simultaneously,
this comparison
only takes one clock cycle per bit.
In t o t a l ,
b+4 clock cycles are needed.
search
a
of
for
an
8-bit
data
item
in
vector
128
items
is
Thus,
accomplished
in
a 2.4
microseconds. The instruction "Greater than Common, GREACOT field._address,
tagmasked"
length
marks in the Tag registers those words - of the selected ones - where the contents of a certain
field is greater than the contents of the same field in the Common Register.
The A C I M A function of the A L U (see instruction list in Appendix 1) is used to subtract the Common Register output bit f r o m the Memory output bit, and starting with a "1" in the Carry register,
one bit each clock cycle
The t o t a l t i m e is b+4 clock cycles also in
68
this case. We consider two versions of closest match: minimum arithmetic distance and minimum Hamming distance. The instruction "Closest match, CMACOT field_address,
arithmetically,
to Common,
tagmasked"
length
computes the difference between the Common Register value and the field value in each word,
then forms the absolute values of these differences,
minimum.
and finally searches for the
The t i m e is 7b+constant.
The search for minimum Hamming distance, CMHCOT field_address,
length,
counter_length
proceeds by first forming the exclusive OR between the Common Register value and the field
value,
then counting the number of ones in each of these results,
searching for the minimum value among the counts. time,
the second takes 2bc+constant,
used in each word. is not needed). cycles.
where c is the counter length.
The t i m e can be reduced because,
and finally
The first phase takes 2b+constant
initially,
The third phase is the search for minimum,
(A counter field is
the full counter length which takes 3c+5 clock
In t o t a l 2b+3c+2bc+constant t i m e is used for the operation.
3.3,4 A More Complex Search
As an example of a more complex search instruction, The
maximum
we consider the following:
value in a m a t r i x stored one row per memory word is formed by the
instruction M A X M A T m a t r i x start address,
no.
of columns,
data length.
The execution of this instruction proceeds in the following way:
Find the maximum element of the first column. Move this value to t h a t field of the Common Register that has the same address as the second column. Search for a greater element in this column. If there is one, move its value to that field of the Common Register that has the same address as the third column, else move the old value to this place. etc.
69
At the end of this procedure, value.
a field of the Common Register contains the maximum
A bit slice in the Associative Array and a register in the Address Processor are
constantly updated to keep track of where the maximum value so far is to be found.
3./4 A R I T H M E T I C In
this
section
INSTRUCTIONS
we
describe
how
basic
instructions
for
addition,
subtraction
and
multiplication are implemented on LUCAS. 5.4.1 Addition and Subtraction The instruction "Add fields, ADDFT sourcel~
tagmasked"
source2,
destination,
length
adds the contents of one source field to another, field.
writing the result in the destination
The implementation is a repetition of the following three ALU instructions (see
Appendix t),
constantly incrementing the address pointers. LRMA(sourcel) ADMA(source2) WRRT(destination)
Putting the length in the Loopcounter of the Address Processor makes i t possible to perform the loop counting and test without overhead. is 3b+8.
The total time for the instruction
This means that 128 pairs of 8-bit numbers are added in 6.4 microseconds~
using a 5 MHz clock.
The microprogram can be studied as an example in Chapter 5.
The implementation of the subtract-fields instruction SUBFT source1,
source2,
dest,
length
which subtracts source field 2 from source field 1, instead of ADMA,
differs from the above only in that,
the ADMIA function of the ALU is used,
is set before starting.
and that the carry register
This realizes a subtraction according to the t w o ' s complement
method. Addition of a constant to a field,
with the constant stored in the Common Register~
done with the instruction "Add Common to field~ ADCOFT source,
destination~
This takes shorter time~
is
tagmasked"
length
because bits from both arguments can be input to the ALU
70
simultaneously.
The ALU function used is ACMA~
and the execution time is 2b+6 cycles.
Subtraction o f a constant or subtraction from a constant are made in a similar way~ using the ALU functions ACIMA and ACMIA~
respectively.
Multiplication
3.4.2
3.4.2.1 Multiplication of Two Fields Multiplication of two fields of t w o ' s complement numbers MULFA source1,
source2,
destination,
length
is implemented using Robertson's algorithm in the following way. given in Chapter 5). one,
is used.
(The microprogram is
A product field of twice the length of the source fields,
minus
The bits of the multiplier in the source2 field are scanned from right to
l e f t and put in the Tags.
For each bit~
the multiplicand in the source1 field is added to
the proper positions of the product field,
but only in those words where the Tag = 1.
The sign bit in t w o ' s complement numbers actually has weight = -1.
Therefore,
the
into the product field,
but
final step is a subtraction in words with the sign bit equal to one. The execution time is the fallowing (b is the length of the operands): S t e p 1 : Loading the multiplicand~
adjusted to the right~
only in those words where the rightmost bit of the multiplier is "1".
Double sign bit is
used. Time : 3b+3 cycles. Step 2 : Clearing of the rest of the product field. Time : b-2 cycles. Step 3
:
Repeated
conditional
addition
of
the
multiplicand
on
the
to
the
product
field.
Time : (b-2)(3(b+1)+8) = 3b2+Sb-22 cycles. Step
4
:
Conditional
subtraction
based
sign
bit
of
the
multiplier.
Time : 3b+12 cycles. Total time : 3b2+12b-9 cycles. As an exampt%
b=8 gives 279 cycles,
or 55.8 microseconds.
3.4.2.2 Multiplication of a Field by a Constant Multiplication of a field by a constant has a shorter execution time.
The reason is that
71
the number of additions can be reduced; only when the m u l t i p l i e r contains a "1" at the c u r r e n t position,
an addition has to be made.
When m u l t i p l y i n g by a constant,
the constant may be put e i t h e r in the Mask Register or
in a M e m o r y Module of the Processor A r r a y .
Both can be scanned by the C e n t r e ] U n i t
and the bits tested for zero or non-zero value. a r r a y is to be tested, Tag register,
When a b i t of a constant stored in the
a selector is used to point out the word,
the bit is loaded to the
and the SOME-line is i n t e r r o g a t e d .
The average t i m e for m u l t i p l i c a t i o n
by scalar w i l l be half the t i m e for m u l t i p l i c a t i o n
of
fields. A
further
multiplier
reduction is receded
of
the
into
number
a form
code is such a f o r m [Hwang79]. where 1. stands for -1.
of
that
add-type
operations
has f e w e r non-zero bits.
In an SD number,
be
achieved
if
the
The signed-digit (SO)
the allowed digit set is ( 1 ,0,1),
The weights of digits are the usual powers of two.
The SD code of a number is not unique.
For example,
the decimal number 7 can be
coded into a 5 - d i g i t SD v e c t o r in t h r e e d i f f e r e n t ways." 00111, One of
can
these has a m i n i m a l
number
of non-zero
digits,
0100 1 ,
and 1 1 00 1 .
but in general not even the
m i n i m a l f o r m is unique. A
minimal
signed-digit
SD
vector
that
(CSD) v e c t o r
.
contains
no adjacent
Such a v e c t o r
non-zero
digits
is called
a canonical
can be obtained by the f o l l o w i n g
procedure
(Figure 3,8): Starting m-1
at the least significant
"O's preceded by a " !
bit,
replace sequences of m " l " s ,
" and succeeded by a "1"
I 0 1 1 1 0 1 1
i 1 0 1 1 1 ! 0 - 1
/ 1 1 0 0 0 - 1 0 - 1
/ "1
0 -1
0
O
0 -t
0 -1
Figure 3.8 Receding a number to canonical signed digit code
where m > 1,
by
72
By the f o l l o w i n g method~
we can a r r i v e at a m i c r o p r o g r a m to c o n v e r t a v e c t o r stored in
a f i e l d of the associative m e m o r y to CSD f o r m • The procedure described above is reatized by an a u t o m a t o n scanning the bits of B f r o m r i g h t to l e f t and w i t h the state t r a n s i t i o n graph shown in Figure 3,9.
00/0 ~o/o
10/1 oit~
Bi+lBi/Di 00/1 Figure 3.9 State t r a n s i t i o n graph for bit serial recoder
so is the i n i t i a l state. "1"
is found~
Di=l
state is changed.
is output.
When B i + I = B i = I
As tong as Bi=l
cause us to o u t p u t 1 ~ we r e t u r n to s0~
As tong as B i : 0 we stay in So,
is encountered~
we stay in Sl,
stilt staying in s 1,
o u t p u t t i n g D.=O.l
When a single
Di= 1 is o u t p u t and the
outputting Di=l.
Only if t w o consecutive
Bi=0 ~
Bi+l=l
will
"O's are found wilt
o u t p u t t i n g a "1"
+ Coding so as q=0 and s 1 as q=l gives the f o l l o w i n g n e x t - s t a t e function q : + q
= qBi+ 1 v qB i v B i + I B i
The output is three-valued. uI 0
We choose the f o l l o w i n g code=
u2 0
1
0
1
1
1
1
This gives the expressions +
ul=q u 2 = q + B i ~ where + is add modulus 2 If we equip the
ALUs w i t h functions t h a t suit these expressions exactly~
the conversion
73
can be made at maximum speed,
which is three cycles per bit-slice (one read and two
writes).
If we want to use the standard A L U function set,
needed.
The state is held in both the R and C registers.
6 cycles per bit-slice w i l t be The following sequence of
functions implements the above functions (j and j + l are the bits w r i t t e n into when bit no. i is scanned): Contents
of
registers
C
R
q XORP4vlA~ a d d r e s s WRRA,
i
address
j
LP4vIA, a d d r e s s
i
AEt4~,
i+1
q+B
i
+
address
q (=u) 1
+
q(=u)
LRCA
1 WRRA,
address
j+l,
incr
j,
loop
The relevance of doing the conversion to CSD form in the Processor Array w i l l be seen in Chapter 7, algorithm, Therefore
where m a t r i x m u l t i p l i c a t i o n is described.
each element of one of the matrices is to be used as a m u l t i p l i e r once. it
is convenient to
simultaneousiy.
a
CSD
do the
conversion to
CSD form
of
an entire
column
This is probably a rule for data produced in the array: if one i t e m is
going to serve as a m u l t i p l i e r , Using
During the execution of the
coded
many items are.
multiplier,
the
number
of
add-type
subtractions) in a multiplication w i l l on the average be b/% m u l t i p l i e r [Hwang79].
Therefore,
operations
(additions
and
where b is the length of the
the average t i m e for multiplication by a CSD coded
scalar wilt be one third of the t i m e for
m u l t i p l i c a t i o n of fields.
m u l t i p l i c a t i o n takes on the average 19 microseconds,
For exampte~
8-bit
with a 5 MHz clock.
In Chapter 10 we wilt describe the design of a new processing element that includes a multiplier, length.
resulting
in a m u l t i p l i c a t i o n
time
that
grows only linearly
with
the data
74
3.5 SUMMARY O F EXECUTION TIMES
Table 3.1 gives a summary of execution times of basic operations that we have dealt with in this chapter,
To be able to compare the speed of the 128-PE LUCAS with the speed
of a sequential computer we have also calculated the time in which a sequential computer is required to perform the same operation on one data item~ depending on the instruction type, operation",
or EST,
For example, running with
if
or on a pair of data items 9
We call this time the "Equivalent Sequential Time per
It is given in nanoseconds.
a sequential computer is to have the same performance as LUCAS
a 5 MHz clock,
it
including data fetch and storag%
must be able to add two 8-bit numbers in 50 ns,
addressing and loop counting.
8-bit Microseconds
data EST
16-bit Microseconds
data EST
MOVES AIxDMERGES Load Outdata Move
(8-bit
only)
field
Broadcast Merge
field
fields
2.2
17
4.4
34
7.6
59
4.8
38
9.6
75
6.0
47
10.8
84
5.8
45
10.6
83
SEARCHES AND CCF43ARES Maximum of Compare Field
field
Compare Field
4.4
34
7.6
59
4.6
36
7.8
6t
to Corrrnon
2.4
19
4.0
31
t h a n Corrrnon
2.4
19
4.0
3t
6.4
50
11.2
88
4.4
34
7.6
59
fields
greater field
greater
than
field
ARITHVETIC
Add
(Sub)
fields
Add Corfmon to f i e l d Multiply
fields
Multiply
field
by Corrmon ( a v e r . )
Multipl field by C S D - c o d e d Common ~ a v e r a g e )
56
436
190
28
219
95
1484 742
19
145
63
492
Table 3.1 Execution times for some basic instructions on LUCAS running with 5 MHz clock
frequency.
EST
is
the
Equivalent
Sequential
Time
per
operation
Chapter /4 COMPARISON WITH RELATED DESIGNS
The
interest
increasing. 777
in
associative
computing
started
and Hwang and Briggs
associative computers have been mad%
but
the
fifties
Surveys on the topic can be found in [Thurber75~
Parhami73~
actually
in
used,
so far
lack
of
has
been steadily
Thurber76,
You and Feng
Numerous proposals for
the design of
yet only a few real machines have been built and
Many application areas for
the
changing,
84].
and
cost efficiency
associative computers have been identified, use.
This situation is now
due to the development in semiconductor technology,
has l i m i t e d
their
A few machines with
characteristics similar to those of LUCAS have been built.
We w i l l briefly r e v i e w the
main features of six such designs and compare them to LUCAS.
Two of the machines
have been implemented in a university environment (Vastor and CLIP4), (STARAN~
DAP and PROPAL 2) are commercial products~
have
built,
been
STARAN~
MPP
DAP~
processor arrays~
finally~
PROPAL
is
built
by
industry
Three of them
but very few copies of them for
dedicated
use
by
NASA.
2 and Vastor can be considered as being general purpose
whereas CLIP4 and MPP are designed exclusively for image processing.
4.1 STARAN STARAN
[Botcher78]
from
processor array to be built.
Goodyear
Aerospace
Corporation
was
the
first
The first machine was demonstrated in 1972.
bit-serial
tt was built
from standard off-the-shelf integrated circuits. An array in STARAN
consists of 256 Processing Elements.
together,
Each Processing Element has three flip-flops.
from
memory and one bit
the
memory words are 256 bits long~ A
key element of
[Batcher77].
the
STARAN
from
either
Several arrays can be used
Any Boolean function of one bit
of the flip-flops
can be performed.
The
in later versions extended up to 9 kbits, computer is the muitidimensionat access (MDA) store
Elements of data are scrambled in a certain way as they are w r i t t e n into
m e m o r y so t h a t data can be accessed in d i f f e r e n t directions. word or a 256 bit
slice are accessed equally easy.
For example~
a 256 bit
This is achieved by an ingenious
scheme that always puts two bits of the same word in different memory chips and at d i f f e r e n t addresses,
Therefore~
modifications of the bit-addresses to each memory chip,
and passing of data through a so called Flip network,
are needed.
76
The Flip n e t w o r k also accounts for the routing of data between Processing Elements (see Section 1.4.2).
i t has many characteristics
network implemented on LUCA5.
The S T A R A N network is of multistage type,
LUCAS uses a single-stage network, is d i f f i c u l t
in common with the p e r f e c t shuffle/exchange
individual box control,
whereas
as discussed in Section 1.4.2
to achieve on STARAN but can be programmed on LUCAS as shown in Section
3.2.3. Input/output
takes place over a 32-bit wide data bus.
The Flip network allows d i f f e r e n t
subsets of the PEs to be reached in one I/O operation. 32 bits
to
be stored
parallel i n p u t / o u t p u t , In
conctusion~
in parallel
in one word.
A
Also,
provision
the M D A store allows the is made also for
256 bit
but this requires special purpose peripheral configurations.
STARAN
and L U C A S
have
many
features
in common.
The
STARAN
a r c h i t e c t u r e had great influence on the design of LUCAS.
4.2 D A P The
Distributed
company
in
Array
Processor
England.
The f i r s t
-
DAP
[Reddaway79]
experimental
model
was
developed
by
was operable in 1976.
the
ICL
The f i r s t
customer model was delivered to London U n i v e r s i t y in 1980. The pilot D A P has 1024 PEs arranged in a 32 x 32 array. PEs in a 64 x 6/4 configuration. the North, The
PEs
South,
The customer model has 4096
Each PE can communicate with its nearest neighbours in
East and West directions.
comprise
three
one-bit
registers:
Activity,
Associated with each PE is a /4 kbit memory module. same b i t address~ no address m o d i f i c a t i o n
Carry
and
Result
registers.
A l l memory modules receive the
and p e r m u t a t i o n of data,
as in 5 T A R A N ,
is
"highways" in the v e r t i c a l
and
done. For
the purpose of input/output
h o r i z o n t a l directions are used. processor array, same column.
and data broadcasting,
The w i d t h of a highway is the same as the side of the
thus allowing a PE to send data to all PEs in the same row or in the Thus,
DAP allows 32-bit wide I/O transfer in the pilot version and 64-bit
wide transfer in the customer version. A
special
memory
feature module
arrangement space
of
entirely
the
with of
in which Master
different
DAP
the
any 8-bit computer
ways.
accessed at a t i m e r
is that the t o t a l i t y
Host
While
computer. slice
of
This the
via the I/O on L U C A S
of memory is
in
memory registers. an 8-bit
a
modules forms
way
similar
to
a standard the
LUCAS
can be mapped into the address However, portion
of
data
is accessed in
each memory
word
is
on D A P a 32-bit slice over a row or column of the PE is available.
77
The difference lies in the fact that with LUCAS the Host accesses the t/O data registers which
are the
medium
for data f o r m a t
conversion.
With
DAP
the PEs are accessed
directly.
4.3 PROPAL 2 PROPAL 2 [Cimsa79] is a processor array computer designed and marketed by the French company CIMSA.
The number of processors can be between 8 (one board) and 2048 (8
racks of 32 boards),
arranged w i t h one-dimensional connectivity.
is
PE
included
in
each
together
with
a
16-bit
work
A "condition" f l i p - f l o p
register.
A
Boolean one-bit
a r i t h m e t i c / l o g i c unit takes one bit from the work register and the other bit f r o m either the condition flip-flop,
the associated 256-bit memory word or a parallel input.
An 8-bit
shift register is included which speeds up m u l t i p l i c a t i o n by holding the partial products. The work registers play an important role in interprocessor communication. of
a register
can be transferred
in parallel to
the
The contents
neighbouring PE above or below.
End-around c o n n e c t i v i t y can be used between the top and bottom PEs under control of the Host. Input and output can be performed in two ways: One is through the ensemble of work registers which acts as a 1d-bit wide shift register. the PEs is suspended.
During the shifting,
processing in
The other I/O method uses a one-bit input line of each PE.
Thus,
the parallelism of this path can be e x t r e m e l y large. PROPAL
2 is controlled by a microprogrammable minicomputer.
word is divided into two halves of 48 bits each. itself,
The microinstruction
One is used to centre[ the minicomputer
the other controls the parallel processor.
4.4 Vaster Unlike all other systems surveyed in this section, designed at the University of Toronto~
the Vaster computer [Loucks et aL82]
uses a standard,
off-the-shelf processing element
- the Motorola MC14500B~
which is marketed as a control unit for industrial applications.
The number of PEs is 256.
Each PE has a I02/4 bit memory word and all memory words
receive the same bit address. A shift register with one bit per PE is the medium used for interword communication and input/output. required.
Passing data between PEs takes considerable time unless mere shifting is
The conversion from byte oriented to bit-slice oriented data necessary at input
can be done by the shift registers,
but only in every 8th word at a time.
This makes
input/output quite complicated. The size and cost of Vaster are about the same as of LLICAS.
All other machines that
78
we consider represent much larger i m p l e m e n t a t i o n a l efforts. boards are used and a component cost
In the case of Vaster,
of $2000 is r e p o r t e d for a full
16
256 PE system.
(Only 16 PEs have a c t u a l l y been implemented). P e r f o r m a n c e results r e p o r t e d for Vaster indicate that L U C A S is about 10 t i m e s faster on operations t h a t
do not require i n t e r - P E
communication
and more than a hundred t i m e s
f a s t e r on tasks t h a t require such c o m m u n i c a t i o n .
4,5 CLIP4
CLIP4 [ D u f f 7 9 ] is one system in a series of processor arrays which have been constructed at U n i v e r s i t y College,
London.
[t is e x c l u s i v e l y aimed at image processing.
are arranged as a 96 x 96 array.
92t6 PEs
Each PE c o m m u n i c a t e s w i t h eight neighbours,
four of
which are diagonal. 32 bits of processor
memory that
we
are associated w i t h consider.
The
each PE,
PEs
contain
which three
is much less than any o t h e r one-bit
registers
each.
Two
independent Boolean functions of t w o inputs each can be p e r f o r m e d simultaneously.
4.6 MPP The
Goodyear
Areospace
c o n t r a c t e d by NASA
Corporation,
who
designed
and
marketed
in 1979 to build a "massively parallel processor",
for the processing of satellite images.
5TARAN,
was
MPP [Botcher82],
It has an a r c h i t e c t u r e similar to DAP w i t h 128 x
128 processing elements connected in a t w o - d i m e n s i o n a l arrangement. Each PE has associated a 1 kbit m e m o r y word. the DAP
PEs.
Each one contains five
Boolean logic unit.
Furthermore,
The PEs are slightly more p o w e r f u l than
one-bit registers,
a full adder and a t w o - i n p u t
a v a r i a b l e - l e n g t h shift register is included to speed up
multiplication. An a d d i t i o n a l one-bit register, PE.
When inputing data (i.e.
S,
images),
a r r a y and stored in the S-registers. until,
finally,
interrupted
used exclusively for data routing,
I28 bits are input in parallel at one edge of the
Data is shifted f r o m column to column of S-registers
the whole image is stored
and the
input
is included in each
in the S-registers.
data stored in the memories.
Then the processing is
Input and o u t p u t can proceed
simultaneously so t h a t an input image is shifted in at one edge w h i l e at the same t i m e an o u t p u t image is shifted out at the opposite edge. The PEs of MPP can be said to be connected in t w o d i f f e r e n t ways: For processing a two-dimensional
connection
is used,
128 separate 128-bit shift registers.
whereas for i n p u t / o u t p u t
the PEs are connected as
79
4.7 CONCLUSION The machines surveyed share one i m p a r t a n t property: they all comprise a large amount of b i t - s e r i a l l y working processing elements.
It is probably not the case that l i m i t e d budgets
and technological limitations are the main reasons for this~ of the generality of the bit-serial approach. are in fact rather similar~ others. The
but rather an underst&nding
The processing elements of all the designs
although some of them are slightly more powerful than the
The processing elements of LUCAS fall somewhere near the middle of the scale.
differences
between
the
various
designs
arrangement and the input/output structure.
mainly
concern
the
interconnection
This mirrors the fact that the designers have
had d i f f e r e n t application areas in mind for the d i f f e r e n t machines.
Machines p r i m a r i l y
intended for image processing t y p i c a l l y use a two-dimensional interconnection network and fast input/output, more elaborat%
while machines designed for general purpose show other~ schemes for communication.
As for PE interconnection~ that
LUCAS is most similar to STARAN,
which is the only design
uses a network akin to the perfect shuffle/exchange network.
does not
sometimes
have the
complicated
memory
storage method that
However~
STARAN
utilizes.
LUCAS The
input/output system is also quite different. LUCAS is similar to OAP and MPP in the s i m p l i c i t y of data storage but d i f f e r e n t with regard to interconnection and input/output, The size and cost of LUCAS are like those of Vastor° more expensive,
All other machines are larger and
Part 2. PROGRAMMING
All
applications
programs
on L.LJCA5
are
divided
into
two
parts:
one part
which
is
executed sequentially in the Master Processor and one part which executes in parallel on data }orated in the Associative Array. the
Control
Unit
of
LUCAS.
The parallel part consists of microprograms for
The sequential pert,
assembly language or in high-level language, l/O.
In addition to
this,
the Master
instructions to the Control Unit.
which
may be w r i t t e n
either in
takes care of scalar processing and external
program
is also responsible for
providing the
input and output of data to and from the Associative
Array involves both the Master Processor and the Control Unit: the Master toads or reads the
PE
I/Q
Registers
and the Control
Unit
executes microprograms for
between the PE memories and the [ / 0 Registers.
moving data
81
LUCAS has four programming levels with d i f f e r e n t support tools:
PRYING LEVEL
BASIC SUPPORT TOOL
HIGH-LEVEL
Procedure Library
L~AGE
~ACHINE CODE
File
Micro Program Assembler
CODE
Table
The lowest level,
OTHER TOOL
Pascai/L
lv~cro Library
MICRO CODE
PICO
ELABORATE SUPPERT TOOL
LUCAS M i c r o Prograrrming Language
Handler
Microprogram Debugger
Generator
"picocode",
is used to define the instruction set of the PE ALUs.
These are implemented as programmable read-only memories (PROM),
which allows a
change in the instruction set in order to tune LUCAS to a certain application. generator has been developed,
and produces the PROM contents in the form of a binary hex file. standard
format
accepted
A table
which takes Boolean expressions of the inputs to the ALU
by most
PROM
programmers.
The file f o r m a t is a
The current
instruction
set,
which is of general purpose type and supports both a r i t h m e t i c and Boolean operations,
is
listed in Appendix 1. Microprogramming is supported by several tools:
*
Microprogram assembler
*
High-level like language for microprogramming
* Microprogram debugger
The microprogram assembler was developed at an early stage of the design phas%
when
it
It
proved
to
be
an
important
tool
for
debugging and testing
the
hardware.
is
implemented in the form of a macro definition library to a c o m m e r c i a l l y available macro processor (MAC from D i g i t a l Research) and runs on the Master system. A high-level like language has been designed for microprogramming LUCAS.
It allows
82
microprograms to be w r i t t e n on an "algorithmic level", does not need to deal with
which means that the programmer
low level hardware control (enabling buffers,
waiting for
signals to propagate through the system etc.).
It uses a control structure which is similar
to
etc.).
high-level
languages (if-then-else,
while
An
optimizing
compiler
produces
microcode of approximately the same quality as hand coded microcode. A Microprogram Debugger allows microprograms to run at full speed on LUCAS with a breakpoint
facility.
The
contents
of
both
Associative Memory may be displayed,
the
changed,
Microprogram
Memory
and
of
the
loaded from or w r i t t e n to disk.
The
program has four functional modules;
* Microprogram
Memory
loaded from disk, in
symbolic
Monitor.
This
module allows microprograms to
be
the contents of the microprogram memory to be displayed
form
(microprogram
disassembler)
and
the
contents
of
the
microprogram memory to be changed using symbolic notation (microprogram line assembler). * Execution
Monitor.
This
module
allows
Registers and start a microprogram. case the
microprogram
runs
at
the
user
to
load the
Parameter
A breakpoint may be inserted in which
full
speed up to
this point,
where the
execution is halted. * Associative Array Monitor.
The contents of the PE memories and of the
Common and the Mask Registers may be displayed and updated using several different numbers).
formats (hexadecimal,
ASCII characters,
integers or fixed point
The PE registers may be inspected and an area of the Associative
Array may be stored on disk or loaded from disk. may be output to a graphical display processor,
The PE memory contents
resulting in a "pixel mapped"
image on the TV screen of the display unit. * Communication
Module.
communication
network
Allows at
transparent
the
University
communication of
Lund,
with
the
LUNET.
data The
microprogram compiler runs on a VAX 11/780 which is connected to LUNET. The communication module allows mieroprograms to be developed on the VAX and
transferred
directly
to
the
microprogram
memory
of
For machine level programming a collection of standard microprograms, used rio implement
the parallel part
of
most
programs,
LUCAS.
which can be
has been developed.
These
instructions constitute the standard software interface between the Control Unit and the Master Master.
Processor.
Assembly
programs
are w r i t t e n
in the assembly language for
A macro library defines constants and macros,
with the Control Unit.
the
which are used to communicate
The instructions to LUCAS have the following general format:
83
INSTRLJCTION~
INSTRUCTION serve
PI~
P2~P3~
P4
is the instruction name and the Pis are the optional parameters,
as operand descriptors
to
the
instruction,
The
meaning of
which
the parameters is
standardized as follows: P1
gives the location of the first source operand
P2
gives the location of the second source operand
P3
gives the location of the destination
P4
specifies the length of the operand(s)
A File Handler is defined as a collection of subroutines which can be linked to user programs.
This provides a file handling capacity for the Associative Array.
In order to use LUCAS
in a high-level language environment~
a procedure library has
been defined which constitutes a high-level software interface to a Pascal system~ runs on the Master. simple,
which
Since the interaction between LUCAS and the Master is e x t r e m e l y
the interface,
which is w r i t t e n in assembly code~
could be kept small (less than
1K bytes). This approach allows programs w r i t t e n
in a high-level language to interact with LUCAS
w i t h o u t too much e f f o r t needed for the implementation,
Once the basic structur%
as the memory allocation scheme for the Associative Array~ can
is decided~
easily be added when new microprograms are w r i t t e n .
results in a performance reduction for various reasons.
such
new procedures
However~
the
approach
Memory allocation is done at run
t i m e instead of at compile t i m e and every instruction which is sent to LUCAS results in Pascal procedures being called.
Also~
error checking is minimal and operations on field
variables can not be described in the f o r m of expressions. To overcome these deficiencies~ This
language~
which
is
an
a high-level language has been developed for LUCAS. extension
to
Pascal~
is
described
in
Chapter
6.
Chapter 5 LUCAS MICROPROGRAMMING LANGUAGE
5.1 INTRODUCTION LUCAS
is used in applications where its
parallel
can
be utilized
standard minicomputer.
to
obtain
capabilities of
a significant
processing structured
increase
in processing
image
and
database
processing.
However,
it
which is the case in for is
inefficiencies in the implementation of the bit-serial algorithms. often very tight,
a
The bit-serial nature of the computations performed by LUCAS is
both convenient and efficient for processing low-precision data, example
data in
speed over
t y p i c a l l y 2-5 machine cycles,
extremely
sensitive
to
The innermost loops are
and one or two unnecessary instructions
in the loops have a tremendous impact on the processing speed.
This means that most
users w i l l be forced to w r i t e some parts of their programs in microeode. Disadvantages of programming in microcode are well known,
and not specific for LUCAS.
The programmer must be very well acquaintanced with the underlying architecture of the machine
and
pipetining.
take If
into
consideration
microprogramming
microoperations, simultaneously.
is
all
peculiarities
horizontal
(as
in
with
for
LUCAS)
which control d i f f e r e n t parts of the machine~
example it
is
timing
possible
to
and let
overlap and be executed
Deciding which operations could overlap requires a detailed knowledge of
the internal workings of the computer and optimal or near optimal solutions are very hard and t i m e consuming to find.
On the other hand,
it is important to e x p l o i t this possible
paratlelism. With
an increasing number of microprogrammable computers appearing,
microprogram
development tools is growing.
microprogramming Js appealing. such as block structure,
the interest in
The use of high-level like languages for
A language wh}ch incorporates typical high-level qualities,
procedures and structured control statements of type " i f - t h e n -
else" for selection and "while" for repetition, which f a c i l i t a t e both development,
w i l l support modern programming methods,
maintenance and documentation of programs.
Another
i m p o r t a n t aspect is that the language compiler could be responsible for the tedious task of
forming
the
complete
microinstructions
between the microoperations.
with
optimal (or near optimal)
overlapping
Su['~h a language is not automatically machine independent
but it is obvious that a unified approach to the design of languages of this kind could be adopted.
85
Current
research in the area of
microprogramming techniques has two directions: the
design of suitable programming languages and the development of methods for optimizing the microcode. The request for highly efficient microcode influences the definition of languages. designers agree that the firm demand for machine independent languages, in
the
area
of
high-level
languages,
is
not
applicable
to
Most
which prevails
microprogramming.
Ramamoorthy and Tsuchiya formulate their point of view in [Ramamoorthy74]= "The
desirable properties of
compromise explicit
between
and
a high-level
machine
implicit
microprogramming language must be a
dependency,
parallelism,
and
the
ease
of
innate
detection
and
"naturalness"
representing
required of
all
programming languages to establish effective man-machine communications."
It
deserves to
be mentioned
that
the
independence of high-level languages, different computers.
essential
point
in the argument for
is that programs should be transportable between
It is reasonable to assume that the need for this,
microprogramming,
is
very
machine
small.
Therefore,
microprogramming languages differ in their details.
it
is
less
in the context of important
if
two
What is important is that they use
similar basic constructs and that a unified machine independent methodology far their implementation is developed with
machine independent techniques for
compilation and
optimization. The
MPG
system [Baba and Hagiwara 81] is an example of
approach to high-level microprogramming.
a machine
independent
A program w r i t t e n in the ianguage (MPGL) has
two parts: a machine description (MDS) and an algorithm description (ADS).
The MD5 is
used to initialize the compiler and to prepare it for translation of the ADS part,
which
consists of machine specific algorithms. A
similar
technique has been proposed by DeWitt
[DeWitt76].
His language includes
"extension statements" and "extension operators" which allow the definition of new data types and operations.
The core language includes a high-level like control structure,
integers and p r i m i t i v e assignment statements.
The result is similar to the MPG system: a
program consists of a declaration part where the extensions are defined and an algorithm part which is machine dependent. According
to
Dasgupta
[Dasgupta80],
a
p r i m i t i v e and still be called high-level if independent characteristics, "describe and name,
microprogramming language could
be quite
it has certain machine- and implementation-
such as structured control constructs and a possibility to
arbitrarily,
microprogrammable data objects".
His approach to
machine independent microprogramming takes the form of a generic family of languages, called a schema .
The schema includes all the possible constructs and data types that
can be used when the schema is instantiated into a language for a particular machine.
86
This
instantiation
defines
the
specific
properties
of
the
machine
declarations of the data objects which are available (registers~ flops
ere.)
and specifications
of
the
memories~
a p r i m i t i v e data typ% stack~
The LUCAS
the
form
of
stacks~
flip-
possible operations on these data objects.
The
schema includes several high-level con[rot structures (if-then-else~
array~
in
which is the bit,
cas%
whi[%
repeat)~
and five structured data types: sequence of bit,
record and associative memory. microprogramming language~
which w i l l be presented in this chapter was
defined with the following design objectives: 1)
It should have a machine independent f r a m e w o r k defining a genera[ program structure which resembles that of high-revel languages.
z)
The machine dependent characteristics which are added should allow a change of the PE
instruction
set
without
the
need to re-define
the
language and w i t h
minimal
changes needed in the compiler,
3) The semantics of the language should be close enough to the machine to allow an efficient
implementation,
where the cede produced is of the same quality as hand
w r i t t e n microcode The language has a s~ructure where microprograms and subroutines they use are grouped together in modules.
Variables and constants may be declared either on the module level
or locally in the microprograms or the subroutines. level type.
The control constructs are of high-
The language allows microprograms to be w r i t t e n without dealing with low-
level hardware c o n t r o l
Experience from microprogramming in microprogram assembly code on LUCA5 has shown t h a t the part of the system which is the most d i f f i c u l t to program is the Control Unit~ and especially the Address Processor w i l l become a bottleneck if not properly handled. The use of local and global variables in the tanguage~
a r i t h m e t i c expressions on variables
and automatic handling of parameter passing to subroutines make the Address Processor disappear from the programmer's view. In fact,
no explicit programming of the Control Unit needs to be done at art,
means t h a t the programmer deals w i t h a much less complex architecture. with
the high-level like control
constructs
powerful tool for microprogram development. good~
which simplifies the documentation.
of the language~
This,
which together
have resulted in a very
The readability of programs is also very
87
5.2 MICROPROGRAMMER'S VIEW O F LUCAS
This section describes the architecture of LUCAS as seen by the microprogrammer when using the microprogramming language. array of 128 processing elements (PEs), Register, Figure 5.1).
a Mask Register,
According to this view,
LUCAS consists of an
128 memory modules (PE memories),
Processing of data is done in a bit-serial fashion by the PEs.
I/O Buffer Reg is te r
E--t Common Register Mask Register
I---[
..... I / 0 Register
Figure 5,.,IThe
a Common
an I/O Buffer Register and an Interconnection Network (see
PE Memory
Interconnect ion Network
Microprogrammer's view of L U C A S .
ALU + Regi sters
88
From Common
Above Below Shuffle N.-Shuffle Direct
ALU
Write back to memory
Figure 5.2 Processing Element (PE) in LUCAS.
I c°mm°n V/////d
.
...........] Mask
Associative Array i I
I I
i i
i r
i
I
)
I
Figure 5.3 Bit-slice and fietd in the Associative Array.
A
PE
(see
Figure
5.2)
comprises
an
ALU~
four
one-bit
input/output register and a m u l t i p l e x e r for data selection. (T)~
is used to select the PE.
every instruction it receives.
registers~
an
eight-bit
One of the registers,
the Tag
When the Tag has the value ONE~ the PE w i l l execute If the Tag has the value ZERO~
only instructions which
are destinated for all the PEs w i l l be executed and other instructions wit[ be interpreted as no-ops by the PE. All data paths are one bit wide. t i m e f r o m the PE memories)
This means that only one bit of data is accessible at a
the Common)
the Mask and the I/O Registers.
This is
89
commonly referred to as a bit-slice of data. one bit wide,
Every operation on data which is more than
must be executed as a sequence of operations.
is composed of a number of bit-slices,
Data of this kind,
which
is called a field (see Figure 5.3).
Instructions to the PEs are of the following kind:
Input/Output .
(1) Write the I/O Register output value into the PE memory.
(2)
memory
Shift
the
output
value
into
the
I/O
Register.
(3)
Similar
instructions for the Common and Mask I/O Registers. Register operations with data from PE memory . in the ALU.
Instructions are executed
Operands are the four one-bit registers and the memory output
bit,
which is connected to the A L U via the multiplexer (see Figure 5°2).
The
result
of
the
operation
is
stored
Register operations with data from Common . leaving the result in the registers,
in
the
four
registers.
The same type of operations,
but now the output from the Common
Register is used as an additional operand. Memory w r i t e .
The value of the R Register is w r i t t e n into the PE memory.
The data does not pass through the Interconnection Network,
so data is
w r i t t e n into the corresponding PE memory. I/O Buffer Register operations . selected
PE
into
the I/O
(1) Copy the value in the I/O Register of a
Buffer
Register.
Register contents to at[ the I/O Registers,
(2) Broadcast the I/O
Buffer
including those of Common and
Mask. Operations on the Tag Registers .
Several of the operation types described
above are affected by and a f f e c t the Tags. instructions
to
set
all Tags (to
ONE)
In addition to these,
and to
there are
reset all Tags except one.
5.3 INTRODUCTION TO THE LANGUAGE The entire program t e x t presented for compilation constitutes a compilation unit . syntactical
construct
module starts w i t h
that represents the basic compilation unit,
is the module .
a module heading and terminates with the keyword endmod .
body of the module has two parts~
The A The
a declaration part and a submodule part .
An e n t i t y declared in the declaration part of a module is known,
or visible within the
module and may be referenced from any point following its declaration.
Declared entities
90
are of the
following types:
constants variables subroutines The submodule part can take t w o forms. nested within
the basic module,
It can consist of one or several new modules~
which is then called the 91obal module ,
or i t can be
composed of a number of microprograms. The
microprograms
microprogram Master started,
are
the
only
entities
defines a machine level
computer
when
it
sends an
visible
instruction
instruction
outside for
the
LUCAS
to LUCAS.
it runs to completion w i t h o u t being interrupted.
compilation
unit.
A
and is invoked from
the
Once a microprocjram
has
It terminates its execution with
a microcode branch to a predefined location and LUCAS informs the Master that a new instruction may be sent.
The only place inside a c o m p i l a t i o n unit where a m i c r o p r o g r a m
is visible is in its own body - it can be e x p l i c i t l y aborted. The concept of a subroutine differs from t h a t of a m i c r o p r o g r a m in that the subroutine is visible inside the module where it has been declared~ unit.
A subroutine
may be invoked from
but not outside the c o m p i l a t i o n
a microprogram,
from
another subroutine or
recursivety from itself. Both microprograms and subroutines can have parameters and may declare local constants and
variables,
Figure
5,4 gives the
syntax
diagrams
for
the
general
structure
of
a
c o m p i l a t i o n unit. The scope of a declaration is defined as the part declaration has an effec%
i.e.
of the program t e x t over which the
where the name of the declared e n t i t y is known.
5.5 illustrates the general scope rules of the language.
Figure
91 CompilationUnit Module
Module
[-~Dec]arati°n]~ Subm°du]e~ENDMOD~ part part Declaration part ['~ I l e ~ S u b r o u t i n e ~_~Constant ~__~L~Var'ab L [declaration |declaration dectarationj I
Submodule,,part
t
~
~I Module
-{ Microprogram~
FLqure 5,4 The generalstrucLureof a compilationunit,
j
92
ModuTe var VO
I
..,Subroutine SO
] Externally visible
Module 2 var V1
Subroutine $I
]
IMicroprogram MI va r V2 ......
~I
I
I-
I
Module 3 var V3
\
I Subroutine $2
1
I
Microprogram M3 var V4
i Microprogram M4
Figure 5 5 Scope rules in nested modules,
A slightly modified form of the Backus-Naur form (BNF) wit! be used to represent the syntax of the language.
<
>
":~
This notation has the following metasymbots;
I
/
/x
93
"<" and ">" enclose non-terminats~ rewritten denote slash
"::="
should be i n t e r p r e t e d
"1" should be i n t e r p r e t e d as "or".
as".
repetition
of
is indexed~
the enclosed symbols such
,/x.
as
the
zero or more
meaning
as "means"
A pair of siashes~
is t h a t
times, the
"/'~
or "can be is used to
When the t e r m i n a t i n g
enclosed
symbols
may be
r e p e a t e d at most x times. " < e m p t y > " denotes the e m p t y string. Programs
in a free
are w r i t t e n
numbers~
etc
(Pascal-like
format
notation),
with
the "standard" texical rules for identifiers~
Comments
are
surrounded
by curly
brackets
or
b r a c k e t - a s t e r i x pairs: "(~" "~)',
5,4 L A N G U A G E
ELEMENTS
5.4.1 Constants A constant is an i d e n t i f i e r which is associated w i t h an integer value at the t i m e of its declaration,
This i d e n t i f i e r may l a t e r be used in the program t e x t in place of the integer
value it represents.
The constant d e c l a r a t i o n has the f o l l o w i n g form:
-:= const =<sign> /i=<sign>/; <sign> ::= <empty> I -
::= I The
association
between
the
identifier
and the
value
unless the same i d e n t i f i e r is r e d e c l a r e d in a module~
is valid
nested w i t h i n the module where it was o r i g i n a l l y declared.
const
cl
=
c2
= 256;
100;
throughout
the
modul%
subroutine or m i c r o p r o g r a m which is
94
5.4.2Variables, Declaration
of
microprograms within
the
Assignm.ent..s variables
is either
(see Sections
body
of
5.4.3
implicit and
or e x p l i c i t ,
5,4,4)
are
the subroutine/microprogram,
Parameters
treated
to subroutines
as locally
The f o r m a t
of
the
and
declared variables explicit
variable
declaration is: ( v a r i a b l e declaration>
::=
var ( i d e n t i f i e r > / , ( i d e n t i f i e r > / ;
A
variable
may be assigned values in the range 0 to 4095.
The same rules of scope
apply to variables as to constants,
I var vl,v2,v3;I A variable is used in the following contexts:
* Pointer to data in the Associative A r r a y ,
The current value of the variable
is used to indicate a bit-slice in the Associative Array, * Test variable in control constructs .
The value of the variable is tested in
the condition part of the control statements. A value assigned to a variable in one m i c r o p r o g r a m is valid in any other m i c r o p r o g r a m in the same module until either the variable is re-assigned or a microprogram of some other module is executed. [n the current
implementation of the language,
visible at any point in the compilation unit. variables which restriction
are located
does not
normally
in the registers cause
any
a maximum of sixteen variables may be
(This is due to the allocation scheme for the of the Address Processor.) However,
problem
if
this
local variables are used whenever
possible. The assignment statement has the following general form:
95
::= := <sign> I := I < v a r i a b l e l > : = < v a r i a b l e l > I < v a r i a b l e l > : = < v a r i a b l e l >
::= + I -
This means that a variable can be assigned:
* the value of a constant or number,
optionally negated,
* the value of any variable (including itself), * its current value plus or minus a constant or a number, * its current Variables
can
value plus or minus the value of any variable (including
also
be pushed onto
or
popped from
a predefined stack
itself),
by use of
the
standard procedures SPUSH and SPOP.
v1:=256; vl:=v41 v1:=v1+256; vl:=vl+v2; vl:=vl+vll SPUSH(vl): SPOP(vS);
5.4~3
A
Subroutines
subroutine
declaration
executable body.
consists
of
a subroutine
heading,
local
declarations
and
an
96
<subroutine declaration> ::= <subroutine heading> < s t a t e m e n t part>
<subroutine heading> ::= subroutine ~ I subroutine < i d e n t i f i e r > ( < f o r m a l subroutine p a r a m e t e r list> )i
< f o r m a l subroutine p a r a m e t e r list> ::= < i d e n t i f i e r > /~/
::= <empty> t I I
< s t a t e m e n t part> ::-begin < s t a t e m e n t list> end
<statement
list> ::=
<statement>
/~ <statement>/
The p a r a m e t e r passing convention is c a l l - b y - v a l u e .
The identifiers which are ( i m p l i c i t l y )
declared
subroutine
equivalent program
in
the
to part~
formal
local
parameter
variables of the
list
of
the
subroutine,
whereas any a d d i t i o n a l
local
They
heading
are i n i t i a l i z e d
variables have undefined
are from
conceptually the calling
values when
the
e x e c u t i o n of the subroutine starts, The
subroutine
declared,
may
be invoked
from
any
executable
A c t u a l parameters can be variables~
part
of
constants or numbers.
<subroutine r a i l > ::= call < i d e n t i f i e r > t call ( )
::= /, /
::= I <sign>
the
module where
it
is
97
5.4.4 Microprograms The declaration of a mieroprogram is similar to the subroutine declaration,
only the
heading is different.
<microprogram heading> ::= microprogram ; I mieroprogram ( ( f o r m a l microprogram parameter list> ); ::= <mieroprogram parameter> /,<microprogram parameter>/3 <microprogram parameter> ::= <empty> I The formal parameter list includes a maximum of four parameter% parameter which
occurs in the list is i m p l i c i t l y
separated by " , ' .
A
declared as a local variable to the
microprogram. The difference between a subroutine and a microprogram lies in the invocation procedure. A
subroutine
mechanism
is called is
defined
from in
inside the
the
module
language
for
where calling
it a
is declared~
whereas no
mieroprogram.
Instead,
microprograms are invoked from programs at another level: the machine code level of the Master processor. The parameter passing is of
call-by-value
type;
variables before the microprogram is started. and the Master allows at most four Registers of the Control Unit. parameter
may
be
left
the
Master
initializes the parameter
The hardware interface between LUCAS
parameters to be passed through the Parameter
As seen in the format definition of the parameter list~
blank~
which
denotes that
no value is passed through
a the
corresponding Parameter Register. Microprogram Ml(pl,p2)~ means that parameters are passed through Parameter Registers 1 and 2. Microprogram M2(pl ,,,p2); means that parameters are passed through Parameter Registers 1 and 4. A
mieroprogram
OPFETCH~
terminates
its
execution
which reads the next instruction
corresponding microprogram.
by
branching
to
a
predefined
routine,
coming from the Master and starts the
98
Communication of values between two microprograms is possible via variables dec|ared on the module level. module
together
[f a microprogram needs more than four parameters, with
an
auxiliary
variables declared on the module level,
micreprogram,
which
assigns
its
it is put in a parameters
to
as follows:
Module M1; vat par1 ,par2,parS,par4;
Microprogram Loadparam(pl ,p2,p3,p4); begin p a r l : = p l ; par2:=p2; parS:=p3; par4:=p4 end;
Microprogram Mic(parS,par6,par7,par8); begin ... / [f Loadparam has been executed, _. / par1 - par8 w i l l be defined when Mic starts endl endmod.
5.4.5 Statements I - Progra m Flow Control
5.4.5.1 General The body of a subroutine or a mlcroprogram contains executable statements which are grouped in a statement list.
A statement list is a (possibly empty) list of statements
separated by semicolons. Two basic groups of statements are defined: those that specify operations on data in the Associative A r r a y and those that control the execution flow.
Statements can be of the
f o r m "compound statements" in which case a statement list,
preceeded by the keyword
begin and followed by the keyword end ,
replaces a single statement.
Statements may
also be empty. [n previous sections we have already come upon two kinds of statements= the assignment statement and the subroutine call,
These w i l l not be further discussed,
99
5.4.5.2 Conditions
Most of the constructs used for program flow control are conditional in that they specify two possible ways to proceed in the execution depending on the value of the condition part of the construct.
Conditions can take the values " t r u e " or "false".
::= I 0 I TRUE I FALSE I SOME I NONE I ZMASK() I NZMASK()
::= = I <>
::= I The f i r s t
two conditions test if two variables have the same value and if a variable has
the value zero,
respectively.
" t r u e " and "false". set.
TRUE and FALSE are predefined conditions with the values
SOME has the value " t r u e "
NONE is the complement of SOME.
has the value zero in position address.
if at least one PE has its Tag Register
ZMASK(address) is " t r u e " if the Mask Register
N Z M A S K is the complement of ZMASK.
(When comparing the possible test conditions in the language with the test conditions in the C o n t r o l Unit~
as described in Chapter 2,
it is noted that the conditions which are
generated in the C o n t r o l Unit do not appear in the language.
However,
these eonditons
are i m p l i c i t l y tested by the control mechanisms of the language.)
5.4.5.3 If-Then-Else
The
if-then-else
flow. empty.
construct
is used to
select
one of
In an abbreviated form of the construct~ It
is possible to nest several if-then-else
two
possible paths in the program
the i f - s t a t e m e n t , statements,
should be associated with the most r e c e n t l y encountered then .
the else part is l e f t
in which case each else
100
::= if then <statement> else <statement>
::= if then <statement>
5.4.5.4 Loop Constructs The language has three
loop constructs
for specifying r e p e t i t i o n of statements:
while
repeat and i t e r a t e .
<while statement> ::= while do <statement>
Before each r e p e t i t i o n of the s t a t e m e n t part, the s t a t e m e n t w i l l be executed.
the condition is evaluated.
If it is "false",
If it is "true",
the loop terminates and the execution
continues with the s t a t e m e n t f o l l o w i n g the while construct.
::= repeat <statement list> until
The
repeat
statement
is similar
to
the
white
statement.
condition which is used to control the r e p e t i t i o n ,
The difference
is that
is tested at the end of the loop,
the not
at the beginning as in the while s t a t e m e n t . A minor d i f f e r e n c e is that the construct specifies r e p e t i t i o n of a list of statements rather than
of
one single
statement.
purpose of statement brackets, In many This
cases,
The
the number of times
is especially common
-
until
serves the a d d i t i o n a l
replacing a begin - end pair.
in b i t - s e r i a l
executed a f i x e d number of times, white statement~
keyword-pair repeat
a loop should be repeated is known in advance. processing,
where the basic loops have to be
depending on the precision of the operands.
such a [cop has the f a l l o w i n g form:
Using a
101
b-=noofbits~
w h i l e b>O do begin ...
b:=b-1 end{
We note t h a t the loop c o n t r o l v a r i a b l e , loop,
b in the e x a m p l e above,
is accessible w i t h i n the
w h e r e it f o r e x a m p l e may be used as a p o i n t e r to data in the A s s o c i a t i v e A r r a y .
However,
very o f t e n the loop c o n t r o l v a r i a b l e needs not be accessed in the loop since it
is
used
merely
to
control
the
iteration.
This
kind
of
loop
can
be very
efficiently
i m p l e m e n t e d on L U C A S (by the use of special-purpose loopcounters). A loop construct of this kind is defined in the language:
< i t e r a t e s t a t e m e n t > ::= i t e r a t e t i m e s <statement>
::= I
5.4.5.5 E x i t
An
exit
statement
microprogram.
specifies
a structured
termination
of
a loop,
a subroutine
or
a
Within a loop the e x i t s t a t e m e n t w i l l cause an i m m e d i a t e t e r m i n a t i o n of
the loop and e x e c u t i o n wilt continue w i t h the f i r s t s t a t e m e n t f o l l o w i n g the loop s t r u c t u r e . E x i t f r o m a subroutine means t h a t the c o n t r o l is t r a n s f e r r e d to the calling program.
The
e f f e c t of an e x i t f r o m a m i c r o p r o g r a m is a branch to the OPFETCH m i c r o p r o g r a m .
iterate b times begin CMCT(direct,fielda); if NONE then e x i t ; fietda:=fielda+l ; end;
The e x a m p l e shows the innermost loop of a p a r a l l e l search operation,
where data f r o m a
field
Common
in the
Associative
Array
is compared
to
the
contents
of the
Register.
102
(The CMCT
instruction compares the Common Register contents to the contents of the
PE memory at bit address "fietda".) Normally the loop is executed b times, the word length,
but with the use of the e x i t statement,
where b is
the execution of the loop [s
t e r m i n a t e d when all Tags are false. In the
case of
nested loops,
enclosing the e x i t statement, may
be t e r m i n a t e d
a simple However,
by specifying
subroutines and microprograms, the subroutine/micreprogram, label,
its
exit
causes termination of
any enclosing loop, name
in
the
exit
the smallest loop
subroutine or microprogram statement,
In
the
case of
the name used is the name given in the declaration of A loop structure
may be given a Local name by using a
which preceeds the Loop heading,
LOOPA: while b<>0 do begin
repeat .o,
if b=0 then exit(LOOPA); ,.,
until c=0; .,o
end;
5.4.6 Statements II - Array Operations 5./4.6.1 PE Instructions The PE instructions embrace operations, performed on the registers and on the memory in the Processing Elements, Without parameters,
The instructions are of three kinds: These instructions use the PE registers both as operands and to
store the result, With one parameter,
These instructions use the PE registers as operands but store
the result in the PE memory, With two parameters,
The p a r a m e t e r specifies the PE memory address,
These are instructions where one of the operands comes from
the interconnection network,
The first parameter gives the PE memory address of
103
the source bit.
The second parameter specifies the permutation of data over the
network.
The PE instruction set may be altered by reprogramming the ALU PROMs, instruction set is given in Appendix 2,
LTRA
Load T from R in All PEs
LTRT
Load
WRRA(adr)
The current
The following are examples of PE instructions=
T
from
R
Tagmasked
(in
selected
PEs)
Write R into the PE memories in All PEs at bit address "adr"
LRMA(adr,ABOVE)
Load R from Multiplexer in All PEs.
ABOVE specifies
that the data should come from the memory of the PE immediately above in the Associative Array,
5.4.6.2 Input and Output Input and output of data is physically handled by the I/O Registers, either from the Master Processor,
which are loaded
the t/O Processor or by microcode.
The language
includes instructions for this purpose. Output of data is accomplished by shifting the I/O Registers while specifying the bit-slice address of data to be output. RSHIFT(address) Normally one byte of data is output at a time,
Microprogram LDOA(location); begin iterate 8 times begin RSHIFT(location); location:=location+" end; end; Input of data is handled in a similar fashion.
starting with the least significant bit.
104
WRIA(address) o£ WRIT(address) WRIA
causes the I/O Register output bit to be w r i t t e n into the memory of all PEs.
WRIT is the tag-masked correspondence to WRIA. shifts the I/O Register.
None of these instructions actually
This must be carried out by means of the SHIFT instruction,
which causes all the I/O Registers to be shifted right one step.
iterate 8 times begin WRIT(location); SHIFT; location:=location+l ; end; Note that input and output of data may be performed in one single loop.
This will result
in a more efficient code than if two separate loops are used.
iterate 8 times begin WR]T(inadr); RSHIFT(outadr); /send data to the/ / I/O Register and shift/ inadr:=inadr+l; outadr:=outadr+l; end;
5.4.6.3 Common,
Mask and [/O Buffer Operations
The Common Register and the Mask Register are both 4096 bit random access memories, similar to the PE memories.
They receive the same bit address as the PEs.
The output
from the Common Register may be used as an operand in certain PE instructions and the Mask output is used in conditions (see Section 5.4.5.2). Both the Common and the Mask Register communicate with a corresponding I/O Register. These I/O Registers are either loaded from the Master Processor, by microcode~
exactly as the PE I/O Registers.
the I/O Processor or
Data is output to the I/O Registers
with the same instruction that outputs data to the PE I/O Registers: RSHIFT(address). However,
note that,
since the data in the Common and Mask Registers is static,
output of data is normally not meaningful.
105
Input of data is accomplished with the instructions V~CCM( a d d r e s s ) and V~4VCkSK( add r e s s ) A w r i t e instruction does not shift the I/O Registers.
This must be specified separately.
iterate 8 times begin WRCOM(location); SHIFT; location:=tocation+l end; The I/O Buffer Register provides a flexibte communication link between PEs, PEs and the Common and the Mask Registers,
between
and also between PEs and the Master.
It
can be loaded either with the I/O Register contents of a selected PE or from the Master.
LDIOBS
LOAD from
][/O BUFFER the
I/O
SELECTED.
Register
of
a
Load the I/O Buffer selected
PE
(must
be
Register uniquely
selected). IOBWRALL
Copy
the
I/O
Buffer
contents
to
all
the
I/O
Registers.
106
Example Move
one
byte
at
location
"source"
in
the
tag-selected
PE
to
location
"destination" in every PE where the R Register is ONE.
Microprogram BroadcastSelected(source,destination); begin iterate 8 times begin RSH[FT(source); source:=source+l ; endl SELF;
(* Make selection unique *)
LDIOBS; IOBWRALL; LTRA;
(* Load Tags from R *)
iterate 8 times begin WRIT(destination); SHIFT; destination==destination+l; end; end;
5.5 PROGRAM EXAMPLES The first example shows a microprogram for the operation MAXT - Maximum of Field Tag Masked - see Section 3.3,1.
Microprogram MAXT(Fieid,Length); (* Parameter Field is address to most significant bit *) begin iterate Length times begin CMOT(Field,DIRECT); (* old Tags -2 X~ Select ONEs from remaining *) if NONE then (* restore old Tags *) LTXA; Field:=Field-1 ; end; end;
The next example is the Add Fields Tag Masked - ADDFT - operation from Section 3.4.1:
107
Microprogram ADDFT(Sourcel,Source2,©est,Length); begin CCA; (* Clear the Carries *) iterate Length times begin LRMA(Sourcel~DIRECT); (* Load source bit in R *) ADMA(Source2,DIRECT); (* Add second source bit to R *) WRRT(Dest); (* Write Dest Tag-masked *)
Sourcel :=Sourcel +I; Source2:=Source2+1 ; Dest:=Dest+1 ; end; end;
The
next
example
shows
a
multiplication of integer fields.
complete
module
with
routines
for
2"s
complement
The module contains the microprogram MULFA and two
subroutines which implement addition and subtraction of fields of arbitrary length. algorithm is described in Section 3.4.2.
The steps in the description of the algorithm are
indicated.
(* (*
The
Module for field multiplication
(*
ModuJe FieldMult;
Subroutine AddFieldsT(S1 ,S2,D~L); begin CCA; iterate L times
begin LRMA(SI,DIRECT); ADMA(S2,DIRECT); $I:=$I+I; $2:=S2+I; D:=D+I; end end; Subroutine SubFieldsT(S1,S2,O,L); begin SCA; iterate L times begin LRMA(SI,DIRECT); ADMIA(S2,DIRECT); $I:=$I+I; 52:=$2+1; D:=D+I; end end;
WRRT(D);
WRRT(D);
108 Microprogram MULFA(Multiplicand~Multiptier,Destination,Length); var D,M~K; begin (*STEP 1") LTMA(Multiplier,DIRECT); Muttiplier:=Multiptier+l ; M:=Multiplicand; D:=Oestination; (* First iteration needs no addition since part. prod.= 0 *) iterate Length times begin LRMA(M,D[RECT); ANDTRA; WRRA(D); M:=M+I T D:=D+I; end; WRRA(D); D:=D+I; (* double sign bits *)
(*STEP 2*) (* Clear rest of part. prod. field *) K:=Length-2; iterate K times begin WRRA(D); D:=D+I ; end;
(*STEP 3*) (* Multiplication loop. Use double sign bits *) D:=Destination+l; Length:=Length+l; iterate K times begin LTMA(MultipIier,DIRECT); Multiplier:=Multiplier+l ;
call AddFieidsT(D,Muttiplieand,D,Length); end;
D:=D+I;
(*STEP 4*) LT MA(Multiplier,DIRECT)} call SubFieldsT(D,Multiplicand,D,Length); end; endmod.
109
5.6 MtCROPROGRAM COMPILER
5.6.1 Introduction The translation process for a microprogramming language resembles t h a t of an ordinary high level language in many aspects and standard compilation techniques may be employed in several parts of the compiler, The horizontal microinstruction functional
parts of
performance. and
the
The main difference lies in the code generation scheme. format
provides a potential for parallelism between the
machine which
must be utilized
in order to
assure maximum
A number of strategies for recognizing the parallelism in microprograms
several
algorithms
have
been
proposed
for
compaction is most often used in this context,
microcode
optimization.
The
term
since the algorithms aim at a reduction
in the size of the code w i t h o u t any claims of obtaining an optimal solution. The compiler which has been developed for the LUCAS microprogramming language uses a compaction
algorithm
Tartar76].
This algorithm has been modified to give a better performance and also to
allow
based
microoperations which
on
the
First-Come
First-Served
algorithm
[Dasgupta
and
execute during more than one machine cycle in pipetined
operations, The
compiler
intermediate
has
five
cede,
phases;
code
lexical
improvement
c o n s t i t u t e the f i r s t compilation pass,
i.e.
analysis, and
code
syntax
analysis,
assembly,
The
generation
first
three
and forth
during
phases
when the compiler reads the source code file.
The code i m p r o v e m e n t phase p e r f o r m s several passes over the i n t e r m e d i a t e code, is scanned back
of
this phase.
which
The last phase is basically a two-pass
assembler which produces the final microcode. The p r e s e n t a t i o n given here is a brief outline of the compiler.
For f u r t h e r details the
reader is referred to [Fernstrom83].
5.6.2 I n t e r m e d i a t e Code The first code.
three phases use standard compilation techniques to produce the intermediate
The i n t e r m e d i a t e code consists of a list of pseudo-microinstructions (PMIs).
A PMI
is similar to a microinstruction but with only a l i m i t e d number of its fields defined.
It
controls the smallest meaningful a c t i v i t y in some part of the machine and consists of a microoperation
(MO)
microoperations), C3P ZAP 100
together
with
its
possible
parameters
(which
are
also
For example; Conditional jump to address 100 on zero Address Processor status
110
is a PMI which controls the Sequencer of LUCAS. an instruction
to the Sequencer~
It consists of the MO C,)P~
and its t w o parameters: the MO ZAP~
which is
which controls
the T e s t m u l t i p t e x e r and 100 which defines the value of the Sequencer's data field, The f o l l o w i n g procedures are defined for the generation of i n t e r m e d i a t e code = The
Qen
single
parameter
of
this
procedure
is
the
name
of
an
MO.
The
procedure generates a new PMI containing this MO. 3oin
3oin
Datajoin
This procedure has two parameters; the name of a m i c r o i n s t r u c t i o n an
is
similar
integer
to
value
Gen
but
(number
places
or
the
variable).
MO
The
in
the
last
referenced
generated
fieid
of
PMIo
field and the
last
generated PMI is assigned the integer value. This procedure is used to insert a PMI in the list of PMIs already created.
Insert
It
has two parameters: a p o i n t e r in the list and the name of an MO which will be put
in the
generated PMI.
Subsequent calls
to 3oin and D a t a j o i n
will
operate on the inserted PMI. Chain is used to "connect"
Chain
a sequence of MOs when code for
m u l t i c y c l e ) operations is generated. MOs are moved according last
generated PMI
to c e r t a i n rules.
and the
pipelined (=
During the code i m p r o v e m e n t phase the Calling Chain assures t h a t the
next one produced wilt
keep t h e i r
consecutive
order during code i m p r o v e m e n t .
The PMI in the example above (CJP ZAP 100) is generated by the f o l l o w i n g calls to the code generating procedures= Gen(CJP); Join(ZAP); Oatajoin(Sequencerdata,100);
All the variables of a compiled program are a l l o c a t e d in the sixteen internal registers of the Address Processor. and
it
is t h e r e a f t e r
A l l o c a t i o n is done when a variable is entered in the symbol table never realtocated.
This
simple
solution
is possible since
all the
registers have e x a c t l y the same function. When a subroutine
is cal]ed~
registers b e t w e e n the calling
the c o m p i l e r
checks for
and the called procedure.
overlapping in the a l l o c a t i o n If such an overlap exists~
of the
Address Processor stack is used to save the overlapping registers of the calling program. The i n t e r m e d i a t e code is a symbolic f o r m of the microcode and would~ m i c r o p r o g r a m assembler~
produce executable but i n e f f i c i e n t mierocode.
if processed by a
111
The i n t e r m e d i a t e code is a doubly ]inked list of PMIs.
This structure has been chosen to
allow convenient insertion and deletion of the elements and also to allow scanning of the list in both directions.
The final code which is presented to the microcode assembler (the
last phase of the compiler) consists of a list of microinstructions (MIs).
An MI is formed
in the code improvement phase by merging PMIs according to certain rules.
5.6.3 Code improvement
Two methods for improving the code are used. activities,
The first one preserves the order of art
i f operation j proceeds operation k in the PMI list,
in the resulting code or they are located in the same ML packing of the microcode.
either j still preceeds k
We refer to this method as
Packing is useful for debugging microprograms.
The order of
execution follows the order of operations in the source code and stilt a f a i r l y e f f i c i e n t code is used as compared to executing the PMI list.
A more e f f i c i e n t
microcode is
obtained if the reorganization of the i n t e r m e d i a t e code allows a change of the r e l a t i v e order between the PMIs.
Such a scheme which guarantees that the resulting MI list is
semantically equivalent to the original PMI list is catted a code compaction . The packing process starts with an i n i t i a l l y empty MI list.
Beginning with the first PMI~
subsequent PMIs are merged into one single Mi until a conflict occurs.
The produced MI
is
during
appended to
compilation pas%
the
MI
list.
Actualty~
packing
can
be performed
in which case no list of PMIs has to be created.
outline of the packing algorithm=
the
first
The following is an
1t2
generate empty M[; EMIT==false; CONFLICT:=false; while PMI list not empty do begin get next PMI from list; if PMI has label then CONFLICT:=true (* PMI is a branch target, so must be in new MI *) else if resource conflict between MI and PMI then CONFLICT:=true else if MI must execute before PMI then CONFLtCT:=true else begin add PMI to MI; if PMI is a branch then EMIT:=true; if PMI is part of a pipetined sequence of operations with subsequent operations then EMIT:=true; end; if EMIT or CONFLICT then begin append MI to list; generate empty MI; if CONFLICT then add PMI to MI; EMIT:=false; CONFLICT:=faIse; end~ end (*while *) if MI not empty then append MI to list;
MIs and PMIs are implemented as lists of sets. resources needed,
The sets define data dependencies,
the fields of the microinstruction that are used,
is generated its elements are empty sets.
etc.
the
When a new M1
Adding new PMIs to the MI consists of forming
the union between the sets of the M[ and the PM][ and to assign the resulting sets to the MI.
The meaning of the two Boolean variables EMIT and CONFLICT is as follows: EMIT
is set true when the last PMI was added to the M[ but when a new MI must be generated for the next PMI.
CONFLICT is set true when the last PM] could not be added to the
MI. Local code compaction deals with the compaction of basic blocks ,
where a basic block
is defined as a sequence of consecutive operations (PM][s in our terminology) which may be entered only at the beginning and which is jump-free,
except possibly at its end.
It has been shown [Landskov et al.80] that the problem of finding the optimal solution to the local compaction problem is NP complete.
However,
several non-optimal algorithms
w i t h less computational complexity have proved to be very useful in practice.
113
An i m p o r t a n t the PMIs.
concept in the c o m p a c t i o n process is the data dependency r e l a t i o n between
L e t i and j be t w o PMIs where i precede j in the original PMI list.
is a data i n t e r a c t i o n between i and j, that
the c o m p a c t i o n a l g o r i t h m
must
we say t h a t j is data dependent on i. assure that
If there It is clear
the data dependency relations are kept
i n t a c t when the MI list is produced. The compaction a l g o r i t m in the c o m p i l e r is based on the F i r s t - C o m e First-Served (FCFS) a l g o r i t h m [Dasgupta and T a r t a r 76].
1)
This a l g o r i t h m is as follows:
The PMIs are added to an i n i t i a l l y empty list of MIs.
Every PMI is moved up as far
as i t can go in the list using the rule that a PMI can be moved ahead of an MI if it is not data dependent on any of the PMIs in t h a t MI.
When a data dependeny occurs,
the PMI has reached its rise l i m i t .
2)
Search downwards in the list to find an MI where the PMI may be added with respect to resource conflicts (two PMIs need the same resource or occupy the same field in the
microinstruction).
If
no
such
MI
exists,
a
new
MI
containing
the
PMI
is
appended to the list.
3)
If no rise l i m i t was found in !),
the PMI was not data dependent on any PMI in the
MI list and it may be added to any list element. can be added w i t h o u t a resource c o n f l i c t , of the list. from Practical
If there is no MI to which the PMI
the PMI is placed in a new MI at the top
Placing it at the top rather than at the b o t t o m of the list w i l l keep it
blocking
any
subsequent
experiments [Davidson et
PtvlI
due
to
a
data
al.81] have shown that
dependency
the code obtained is of the
same q u a l i t y as the code produced by the other non-optimal algorithms. FCFS
algorithm
has advantages in both
speed and s i m p l i c i t y .
a l g o r i t h m are described in [ M e z z a l a m a et al.82,
restriction.
In addition,
Implementations
of
the the
Baba and Hagiwara 81].
In the c o m p i l e r we have extended the FCFS a l g o r i t h m by introducing an additional pass. In this pass an a t t e m p t
is made to push PMIs f o r w a r d
in the MI list as far as possible.
If during this pass all the PMIs of an k4I are removed,
the MI is removed from the list.
Using
this
Extended
FCFS
(EFCFS)
algorithm,
the
microcode
obtained
is often
more
c o m p a c t than with the original FCFS and never less compact. In addition to the EFCFS algorithm, for
code i m p r o v e m e n t .
other methods of a more heuristic nature are used
The i m p r o v e m e n t techniques used give good results and o p t i m a l
code is most often obtained.
Chapter 6 PASCAL/L - A HIGH-LEVEL LANGUAGE FOR LUCAS
6.1INTRODUCTION Highly
parallel
machines
of type
assembly like languages.
associative
array
computers
are o f t e n
programmed
in
The reason is t h a t machines of this kind tend to be unique and
d i f f e r in several i m p o r t a n t aspects.
For e x a m p l e :
* N u m b e r of processing elements.
This reaches f r o m 64 elements on I L L I A C IV
[Barnes et at.68] to over 16,000 on the MPP [BateherS0]. Complexity powerful
of
the.....,processing
pipelined
hardware.
elements.
processors,
which
On
ILLIAC
IV,
the
PEs
are
perform
floating
point
arithmetic
in
A t the other end of the spectrum we find machines like S T A R A N
[Batcher79],
the MPP,
DAP [ R e d d a w a y 7 9 ] and LUCAS,
which are all bit-
serial processors. I n t e r c o n n e c t i o n Structure. the PE i n t e r c o n n e c t i o n the
two-dimensional
The t o p o l o g y of the processing a r r a y is defined by
network.
grid
Examples of i n t e r c o n n e c t i o n n e t w o r k s are
on I L L I A C
IV~
the
Staran Flip
network
and the
P e r f e c t Shuffle/Exchange n e t w o r k on LUCAS.
C o m m o n to the languages for SIMD machines is the possibility to declare and to operate on distributed
data,
i.e.
multi-element
data where the single elements are l o c a t e d in
different
processing elements or in d i f f e r e n t
we
that
note
computers,
most
of
are directed
the
languages,
towards a specific
high l e v e l language is to be used, With arose.
the
introduction
of I L L t A C
words of an associative m e m o r y .
which
have been proposed for
machine.
the f a c t
parallel that
if a
it must f i t the a r c h i t e c t u r e welt to be e f f i c i e n t .
IV,
the need for SIMD oriented high l e v e l languages
Several |anguages were proposed of which
used: C F D
This reflects
However,
highly
[Stevens75] - based on F O R T R A N ,
at least three were i m p l e m e n t e d and
Glypnir
[Lawrie74,
Lawrie
based on A l g o l 60 and IVTRAN [ M i t t s t e i n and Muntz 75] - based on F O R T R A N .
et al.75] -
115
The
first
language
designed for
the
ILLIAC
IV
was T R A N Q U I L
[Kuck68],
specified at the same time as the design of the I L L I A C IV system. on Algol 60~
with some minor deletions,
of
and declaration of
statements
declarations, (STRAIGHT
it or
is
possible
SKEWED
to
specify A
the
are stored over the PEs. layout
of
PARTITION
Using its data
variables
in
the
declaration
is
used
previously declared arrays in several ways and to form one (e.g.
was
and includes extensions for parallel execution
arrays that
mapping).
which
T R A N Q U I L is based
subarrays.
PE
memories
to
partition
Parallel execution of
a for-loop) or several statements is specified by means of a SIM statement:
SIM BEGIN ($1; $2; ...
Sn) END
The i m p l e m e n t a t i o n of the language was never completed. Glypnir language
was
the
than
first
implemented
TRANQUIL,
which
language
for
ILLIAC
supports a more
IV.
It
general form
is of
a
less ambitious
parallelism
where
arrays can be of any size and the c o m p i l e r is responsible for "squeezing" them to f i t the I L L I A C IV memory. In contrast
to
this,
all distributed
parallel dimension ( I L L I A C
data variables in Glypnir
IV has 64 processing elements)~
have 64 elements
in its
and it is the p r o g r a m m e r ' s
task to map smaller or larger arrays into this form. C o n t r o l statements are extended~ to control parallel execution.
as compared to Algol~
in that they may also be used
The statement:
IF THEN <Strut-l> ELSE <Stmt-2> results in Stmt-1
being executed in PEs where the corresponding elements of the Boolean
expression are TRUE and Stmt-2 in the PEs where the elements are FALSE. The
Glypnir
compiler
is said
o p t i m i z a t i o n is included.
to
generate
a relatively
efficient
code
even
though
no
A f a c t o r 1.5 to 3 in execution speed is reported as compared to
assembly programming. The I L L I A C
IV I V T R A N
system [ M i l i s t e i n
and Muntz
75~
Millstein73]
is based on the
f o l l o w i n g assumptions"
* The presumptive user is accustomed to programming in F O R T R A N .
The new
language must be of F O R T R A N type. * It
should be possible to
use the system for
existing programs~
written
in
standard F O R T R A N . This resulted
in a new [anguage~
defined in terms of parallel extensions to F O R T R A N .
in order to allow standard F O R T R A N programs to be used~
a pre-processor was added to
116
the IVTRAN
compiler,
where parts
expressed in IVTRAN~
of
are r e w r i t t e n .
the source program,
which
This part of the complier~
could have been
which is called the
"Paralyzer" (Parallelism Analyser and Synthesizer) [Presberg and 3ohnson 75]~ produces an IVTRAN program from the FORTRAN source program.
The form of the tVTRAN program
is either source code (intended for the interested user) or - since the Paralyzer works on an i n t e r m e d i a t e f o r m of the program which is produced by the parser - in a f o r m suitable for the next compiler phase. Parallel Pascal [Reeves et el,80,
Reeves and Brunet 80,
languages which have been proposed for the MPP. extensions to Pascal.
Reeves et al.81] is one of the
The language is defined in terms o f
As compared to standard Pascal,
the new language is extended in
several ways;
* Data can be declared as "parallel",
which means that it should be located in
the parallel processing array of the MPP. * Expressions can be formed w i t h parallel arrays. Several standard included.
functions,
which
may
be used with
parallel arrays are
These are defined for all sizes and shapes of arrays.
Functions
include Shift and Rotate of arrays any number of steps along one or several of its dimensions.
Reduction functions,
functions in APL, * To
specify
based on the p r i m i t i v e reduction
are also included. an
that
operation
should
be
performed
processing elements of the parallel processing array, the
meaning
of
the
if-then-else
construct
in
in
The language,
which
of
the
Parallel Pascal extends
a way
As part of the Phoenix Project [Feierbach and Stevenson 78], has been defined [Perrott79].
a subset
similar
to
Glypnir.
a language called Actus
is based on Pascal,
is in many
aspects similar to both Parallel Pascal and to Pascal/L.
However i t includes constructs,
such as independent indexing in the processing elements~
which could not be e f f i c i e n t l y
implemented neither on the MPP nor on LLJCAS. Special purpose languages have also been described for use in important application areas for associative array processors.
Pixai [ L e v i a l d i et al.80] consists of parallel extensions to
Algol 60 and is directed towards image processing.
Its FRAME
construct
is used to
specify an environment to each ceil in the array upon which operations are performed. Another
language which
defined in terms
of
is suitable
extensions to
executed simultaneously
by
two
or
for
image
Pascal. more
procedures which are declared as parallel.
processing is PascalPL [Uhr79].
Parallel operations (instructions processing
elements) can be included
A STRLJCTURE specification,
it
which
is are
inside
similar to the
117
FRAME construct in Pixal is defined. A
language which
implements a very flexible
indexing scheme is APLISP (A
Language for Image and Speech Processing) [Muelier et at.80]. are t r e a t e d as sets and subsets are chosen by "index sets". such as the Cartesian product, of the operands,
Parallel
Here the parallel arrays
Operations on the index sets,
intersection or concatenation,
allow a powerful indexing
including both alignment and "window specification" similar to the ones
defined in PixaI and PascalPL. Several
languages
for
database
processing
proposed [Resnick and Larson 757
on
associative
Bratsbergseugen et al.79,
computers
have
also
been
Love75].
6.2 OVERVIEW OF PASCAL/L There are two d i f f e r e n t approaches to the design of a high-level language for a parallel compute['.
Either the parallelism of the computer has a correspondance in the syntax of
the language and special constructs are used to express parallel operations on data~ the language does not contain any p r i m i t i v e s for parallel processing,
or
in which case the
compiler is responsible for detecting inherent parallelism in programs t h a t are w r i t t e n in a sequential language. In
the
Both have advantages and disadvantages.
second approach the
user
does not
have to
learn a new language.
programs can d i r e c t l y be moved to the parallel computer.
Existing
Programs can be developed
and tested on an ordinary sequential computer before they are transported to the parallel machine.
The language is also independent of the parallel structure of any particular
machine. However,
if
the
parallelism
is not
apparent in the language,
the user w i l l not be
m o t i v a t e d to design algorithms which are suitable for parallel computation. forces
the
sequential code.
language
It
transformed
to
run
programmer
to
transform
is also unlikely t h a t efficiently
an
inherently
parallel
A sequential algorithm
a completely sequential a l g o r i t h m
on a parallel machine.
Thus in the
interest
into
could be both of
efficiency and understanding of parallel algorithms we have favoured a language where the parallelism is visible. For several reasons it
is preferable to use an existing sequential language as a base,
when defining the new language:
* Sequential
operations
language anyway.
are
indeed
necessary
and
must
be
included
in
the
118
* The
implementation may be simplified
in
that
existing
compilers
can
be
modified to accept the new language, * The user needs to [earn r e l a t i v e l y few new concepts. * The use of the language is not restricted to paraltel algorithms and the same language can be used to program the entire system including compilers and operating system,
When
designing
a high-level
considered for
the
language for
LUCAS,
several d i f f e r e n t
choice of a suitable sequential language.
languages were
APL deals with
parallel
arrays of data in a very generai way and many of the ideas in APL are relevant to parallel processing on an StMD computer.
However,
the dynamic data structures in APL
and the powerful operations on these would make it very d i f f i c u l t to achieve an e f f i c i e n t implementation.
FORTRAN
is
currently
applications where LUCAS may be used.
the
most
used
language
On the other handy
makes i t unsuitable for database processing~
in
many
of
the
its poor data structures
which is one of the pilot application areas
for LUCAS. Pascal
is a well
structured
language w i t h
powerful
makes it suitable for many d i f f e r e n t applications.
control and data structures
which
It has strong typing of variables,
and
a large amount of error detection is possible both at compile time and at run time. Compilers for
Pascal are r e l a t i v e l y uncomplicated to impiement.
chosen so that only one symbol lookahead is needed~ techniques.
The syntax has been
enabling the use of simple parsing
To f a c i l i t a t e the code generation and to allow compilers to be portabl%
an
i m p l e m e n t a t i o n scheme with code generation for a stack oriented virtual machine is used. The
fact
that
portable
compilers
-
written
in
Pascal
-
exist,
simplifies
the
i m p l e m e n t a t i o n on d i f f e r e n t machines. We decided t h a t the new language, terms
of
extensions to Pascal.
corresponds to operations,
the
PascaI/L(UCAS) [Fernstrom82],
should be defined in
The extensions are chosen so that
processing capabilities of
LUCAS.
the new language
This means t h a t
where one instruction operates on several data items,
typical
SIMD
can be specified.
A
characteristic property of associative processing is the a b i l i t y to designate the part of data which w i l l be subject to parallel computations in terms of properties of the data, regardless of where it is stored. Since
the
use
architecture,
of
LUCAS
is restricted
to
algorithms
which
are well
suited
for
the
only constructs which can be e f f i c i e n t l y implemented have been included.
Floating point a r i t h m e t i c ,
for example,
is not included.
The following extensions to Pascal are defined:
119
* Declaration of variables that wiU be allocated to the Associative Array. the
following
these w i l l
be referred
to
as "parallel
variables"~
In
whereas
"scalars" or "sequential variables" stand for variables which are located in the memory of the Master Processor, * An indexing scheme to access parts of parallel variables. * Expressions and assignments involving parallel variables.
* An
extended control
structure,
allowing the
use of
parallel variables as
control variables. * Standard functions for data alignment,
input and output of parallel variables.
6.3 LANGUAGE DESCRIPTION 6.3.1 Declaration of Data The one-dimensional organization of the Associative Array makes it especially suited for operations on one- and two-dimensional arrays. could be represented in LUCAS,
In principle,
arrays of any dimension
but the natural storing scheme where adjacent array
elements also are physical neighbours,
would be lost.
Pascal/L is therefore restricted to
arrays of one or two dimensions. Parallel variables are characterized by their dimension and their range . subscripts
in the declaration defines the dimension of the variable.
The number of
The range can be
seen as a measure of parallelism and is given by the size of the first subscript. There are t w o kinds of parallel variables: selectors and parallel arrays .
6.3.1.1
A
Selectors
selector defines
a Boolean vector over the Processing Elements and is intended to
control the parallelism of operations.
(At execution time this is accomplished by setting
the Tags in these PEs where the corresponding selector element has the value TRUE.) <selector type>
::=
selector[] I selector[] := ()
120
::=
,.
::=
=>
::=
I .. I .. step
::= t r u e I false
We use the same f o r m of BNF as in C h a p t e r 5 to r e p r e s e n t the syntax, F o r example= vat SEL = s e l e c t o r [0_99]; declares a s e l e c t o r w i t h the range 0_99,
i.e.
a s e l e c t o r w i t h e l e m e n t s in the f i r s t t 0 0
PEs, v a t 5EL : s e l e c t o r [0..99]:=(0-98 step 2 => true); declares
a selector
with
the
range 0..9£
where
all the
elements w i t h
even indices are
i n i t i a t e d to the value T R U E and all others to the value FALSE,
6,5.1.Z P a r a l l e l A r r a y s A p a r a l l e l a r r a y consists o f a f i x e d number o f components which are all of the same t y p e and which are l o c a t e d in the A s s o c i a t i v e A r r a y o f L U C A S . or t w o dimensions. range of the a r r a y .
It has the p r o p e r t y t h a t when the f i r s t index is i n c r e m e n t e d by one
in an a r r a y r e f e r e n c e , component
will
referenced, fixed
value
while keeping a possible second index unchanged,
be l o c a t e d
the
Associative Array.
second a r r a y
index~
all
the PE m e m o r y . components
This means t h a t
are l o c a t e d
in
a field
f o r any of the
The d e f i n i t i o n implies t h a t in a t w o - d i m e n s i o n a l a r r a y all c o m p o n e n t s
of a r o w are l o c a t e d in the same PE, d i f f e r e n t PEs.
the new a r r a y
in the PE whose index is one higher than the PE o r i g i n a l l y
but on the same address w i t h i n of
P a r a l i e l arrays can be o f one
The size of the f i r s t subscript in the d e c l a r a t i o n is r e f e r r e d to as the
while the components of a column are l o c a t e d in
121
A component of a parallel array can be of any of the following types: signed integer, unsigned integer,
fixed point number,
Boolean,
character or string.
array with components of any of the first three types,
When declaring an
a precision is specified in the
declaration.
The precision gives the number of bits used in the computations in the case
of integers,
and the number of bits on each side of the "fraction mark" (binary point) in
the case of fixed point numbers.
The maximum length of a string component (number of
characters) is given in the declaration. <parallel array type> ::=
parallel array[] o f <parallel type> 1
parallel array[,..] o f <parallel type> <parallel type>
::=
<parallel type i d e n t i f i e r ) I <parallel standard type> I record <parallel field list> end
<parallel type identifier> ::= <parallel standard type>
::=
integer() I unsigned integer() I fixed(.) I Boolean I char I string() <parallel field list> ::= <parallel record section> /;<parallel record section>/ <parallel record section> ::= /,/ : <parallel standard type> ::=
For example: va__ ! PARA : parallel array [ 0 - 9 9 , 0 - 2 ] of integer(32); declares a two dimensional array,
where the components are of type signed integer with
a precision of 32 bits (including the sign bit). the first 100 PEs with 3 components in each PE.
Components of the array are located in
122
y a r OBSERVATION
parallel array[1..64] o~f
:
record SITE : string(20); TEMP
: fixed(8,4);
endl declares a one dimensional array where each PE f r o m record has two
fields ,
the f i r s t
is a string with
1 to 64 stores a record.
Each
a maximum of 20 character%
the
second a f i x e d point number where the integer part has a precision of 8 bits (including the sign bit) and the f r a c t i o n part a precision of 4 bits. In
correspondence
with
the
components of a record.
Pascal
in the Associative A r r a y of LUCAS. parallel array
of record,
terminology,
the
word
"fieid"
is used to
denote
We have already used the same word when r e f e r r i n g to "fields" However,
a logical field
this should cause no confusion since in a
always is allocated to a physical field
in the
Associative Array.
6.5.2 indexing of Parallel Variables indexing of a variable of array type in Pascal is used to single out one component of the array.
When operating on a parallel variable,
Pascai/L makes it possible to reference
several components along the parallel dimension at the same time. is referred
to
as the referenced
range of
the
variabl%
This set of elements
as compared to the declared
range which is specified in the declaration of the variable. The indexing scheme allows simultaneous access to a column or a subset of the column components of a t w o dimensional array, a r o w or a diagonal.
but not to any other part of the array,
such as
The components of a row are all located in the same PE,
means that they must be sequentially processed.
To access a diagonal,
which
or any other part
of the array where the components are located in d i f f e r e n t PEs - except a column - the PEs would have to include an index register to allow d i f f e r e n t
addresses being used in
d i f f e r e n t PEs. Several ways of specifying the f i r s t index exist. is denoted by a star " * " by constant indices~ a
selector
in the index position.
If an entire column is referenced,
in which case the referenced part is known at compile t i m %
expression.
When
a
selector
this
A part of a column is referenced either
expression
is
used,
the
array
or by
components
referenced are i d e n t i f i e d by the indices where the expression takes the value TRUE.
A
one-dimensional parailel array may be used w i t h o u t any index at all (and no brackets),
in
which case all components of the array are referenced.
123
::= <parallel v a r i a b l e i d e n t i f i e r > I <parallel v a r i a b l e i d e n t i f i e r > [ ] t <parallel v a r i a b l e i d e n t i f i e r > [ ,<expression>]
<parallel v a r i a b l e i d e n t i f i e r > ::=
< f i r s t index> ::= * 1 I .. I <selector expression>
Examples: P0
Select
all
PI[*,0]
Select column O of P1.
PI[S,O]
Where
P112..80,0]
Select a subset of column 0 of P1.
S
the
is
a
elements PI
selector:
of
the
one-dimensional
variable.
is a t w o - d i m e n s i o n a l p a r a l l e l variable.
select
a
subset
of
column
0
of
P1
6.3.3 Expressions and Assignments It
is possible to
type
conflict
combine sequential and p a r a l l e l variables in expressions as long as no
occurs.
This means for
example that
it
is allowed to
form
expressions
w h e r e a scalar i n t e g e r is combined w i t h a p a r a l l e l a r r a y of integers. An
expression,
which
sequential value. p a r a l l e l vaIu%
only
contains
An expression,
sequential
variables
and
constants
results
in
a
which includes at least one p a r a l l e l v a r i a b l e results in a
unless the p a r a l l e l variable(s) is used as a p a r a m e t e r t o a f u n c t i o n which
returns a scalar result. In the c o m p u t a t i o n
of a p a r a l l e l expression,
all r e f e r e n c e d ranges to p a r a l l e l variables
must be i d e n t i c a l and any sequential value is p a r a l l e l i z e d to this range b e f o r e e v a l u a t i o n of the expression.
This means t h a t
4+PARA[*] results in /4 being added to all the components of P A R A and
4+PARA[2.. 5] results in 4 being added to components 2~3,4 and 5 of P A R A .
124
There are four kinds of assignment statements: 1)
The left hand side and the right hand side are both scalars.
This is the normal
Pascal assignment statement 2)
The left hand side is a parallel variable and the right hand side is a sequential expression.
In this case all the components within
the referenced range of the
parallel variable are assigned the value of the scalar expression. 3)
The l e f t hand side is a sequential variable and the right hand side is a parallel expression. value
4)
The referenced range of the parallel variables must be such that the
of
the
The l e f t
right
hand
side
expression
includes
one
component.
hand side is a parallel variable and the right hand side is a parallel
expression.
The referenced components of the left hand side variable are assigned
the corresponding elements of the right hand side expression. expression must be equal to,
or overlap~
The following program exemplifies different kind of assignments. Program Assign; vat ODD :
selector[0..127]:=(1..127 step 2 => true);
EVEN, :
selector[0_127];
P1,P2 : paral!e[ array[0,.127] o f integer(16); I :
integer;
begin EVEN:=no___ktODD; PI[EVEN]:=P2*2;
(* Both sides parallel. Same range *) (* Both sides parallel. The range (* of the rigth hand side expression (* overlaps the referenced range of PI *)
PI[ODD]:=0;
(* Left hand side parallel~ right hand (• side scalar. All the odd elements of (* P1 are assigned the value zero *)
I:=P215];
(* Left hand side scalar, right hand (~ side parallel, but the referenced (* range includes one single element ~)
SEL:=P1 > P2;
The range of the
the referenced range of the l e f t hand side
variable.
SEL
single
(* Both sides parallel. Same range *)
125
h=P2[SEL]~
(* L e f t hand side is scalar, r i g h t hand (* side is paraUet. SEL must have one (* single component w i t h the value TRUE *)
end.
5.5.& C o n t r o l Structure
Pascal contains five structured if
,
case ,
while ,
actions taken
~
constructs which control the sequential program flow: the
and fo_.Lr statements.
In a sequential Pascal program,
all the
can be ordered according to the t i m e i n t e r v a l in which they occur.
This
ordering defines the program flow and is directed by the control statements and by the order
in which
LUCAS
differs
interval,
each
statements are w r i t t e n from in
this
in that
a different
in the program.
as many
The execution of programs on
as 128 actions
Processing
Element.
In
may occur
the
same
constructs in Pascal determine the execution along the t i m e dimension, included
in Pascal/L to allow the control
during the same
way
as the
control
new concepts are
of selection and r e p e t i t i o n along the parallel
dimension. The construct:
if then <true-statement> else
in Pascal selects one of two d i f f e r e n t paraUel s t a t e m e n t , determine
if
the
paths in the program flow.
the Boolean expression yields a selector. true-statement
or
the
false-statement
in the corresponding
Elements of the selector will
be
executed
on
the
corresponding data elements. In a global perspective this means that
both paths w i l l
be f o l l o w e d and that
true-statement
are
but
different
PEs.
and
the
Rather
false-statement than to
extend the
executed~
on
different
meaning of the if-then-else
data
both the and
construct~
in we
define a parallel selection with the foUowing form: where <selector expression> do <true-statement> elsewhere
where the elsewhere-part is optional. Analogous to the Pascal case statement,
Pasca[/L defines a parallel form
of the case-
126
statement,
in accordance to the where-do-elsewhere construct,
not result in one execution path being fotlowed~
but all,
the parallel case does
each working on d i f f e r e n t data.
The form of the parallel case statement is: case where <parallel expression> of : <statement>i : <statement>i
: <statement>i others
: <statement>;
end~ where the others-part
is optional.
compound statements~
i.e.
Like
in Pascal,
statements may be of the form
a list of statements surrounded by a begin - end -pair.
In a similar way an extension to the Pascal while do <statement>
is defined to control repetition for parallel data: while and where <selector expression> d o <statement>
Here the statement is repeated as long as the selector expression takes the value TRUE in
any element,
However,
during
each
repetition
of
the statement~
the
selector
expression also decides in which PEs the statement should be executed. The following example shows how V[I] modulus N[[] can be calculated for every element of the t w o vectors V and N using repeated subtractions: vaT. V,N
:
paratie[ array[0..127] o f integer(16);
whiie and where V >= N d_£ V:=V-N;
127
6.3~5 Standard Functions and Procedures
6.3.5.1 Data Alignment in expressions and assignments where the components of the parallel variables are located in different PEs,
the variables must be aligned.
The kind of alignment needed is defined
by the programmer in terms of standard functions,
which correspond to the possible data
movements over the interconnection network in LUCAS. shift(<parallel variable identifier>,][) rotate(<parallel variable identifier>,I) The first
of these functions shifts a parallel variable I steps along its first dimension,
placing component N in position N+L
Zero-elements are shifted in from the edge.
The
rotate function is similar to the shift function except that the elements that are shifted out at one edge are shifted in at the opposite edge of the parallel variable. shuffle(<paraJlei variable identifier>) exshuffte(<parallel variable identifier>) The
elements
of
the
parallel
variable
Shuffle/Exchange network on LUCAS. the declared range 0..127. component N with Section 1.4.2).
index
permuted
according
to
the
Perfect
The first function performs a shuffle of the elements,
placing
index n0nln2...n k in position Shuff|e(N) with index nln2...nkn 0 (see
The second function performs a shuffle followed by a pairwise exchange
of the elements, with
are
These functions are only defined for variables with
placing component N with
nln2,..nkn0" ,
where
nO"
index n0nln2...n k in position £xshuffle(N)
denotes
that
the
last
bit
in
the
index
is
complemented.
6.3.5.2 Selector Operations first(<selector expression>) This function is used to find the first component of a selector expression with the value TRUE.
It returns a new selector with only this element TRUE.
next(<selector i d e n t i f i e r ) ) The next-procedure assigns the value FALSE to the first true element of the parameter,
128
which must be a variable.
This is useful when processing selected elements sequentially.
any
The any-function returns the value FALSE if a previous call to the first-function or the next-procedure returned an all-false selector,
otherwise it returns the value TRUE.
some(<setector expression>)
A call to the some-function evaluates the selector expression and returns the value TRUE if it contained at least one TRUE element,
otherwise the value FALSE is returned.
Example:
vat PAR1 : p a r a l t e l array[0..99] o f unsigned integer(12);
SEL
: .selector[0..99];
SUM
: integer;
begin SUM:=0; SEL:=PAR1 > 10; white some(SEL) do begin SUM:=SUM+PARIEfirst(SEL)]; next(SEL); end;
In the example SUM gets the sum of all the elements of PAR1 whose values are greater than 10.
6.3.5.3 Input and Output The Pascal standard procedures read and w r i t e are extended to allow input and output of parallel variables. out.
Details of how this should best be accomplished have not been worked
As a preliminary a t t e m p t
the
procedures are extended so that
variables denoting parallel arrays as parameters~ be read or w r i t t e n .
they
may take
meaning that whole parallel arrays may
129
6.3.6 Microprograms It
is
possible to
explicitly
microprogramming language.
invoke
a microprogram
which
has been written
in the
This allows a significant speedup for parts of the program
that can be expressed in microcode,
i.e.
parts which only include parallel operations.
Examples of such operations are matrix multiplications and image operations. A microprogram should be declared in the declaration part of the program. of
the
declaration
is
similar
to
the
syntax
of
microprogram
The syntax
headings
in
the
micraprogramming language( see Section 5.4.4): <microprogram declaration> ::= microp£ogram <microprogram parameter list> I external~ <microprogram parameter list> ::= <empty> 1 ( <microprogram parameter> /~<microprogram parameter>/3 <microprogram parameter> ::= <empty> I
A standard function which is used in conjunction with microprograms is the following:
location(<parallel variable identifier>) This function results in an integer value,
which indicates the bit address to the least
significant bit of the parallel variabte in the Associative Array. Invocation of microprograms is similar to procedure calls. va.._Zr MI~M2~M3 : parallel array[0..127~0..127] o__finteger(16)~ Microprocjram Matmult(A~B~C~precision); externall begin ..o°
Matmult(Loeation(M1)~Location(M2)~Location(M3)~l6)i o...
end__;
130
6.4 EXECUTION ON LUCAS In most impiementations of Pascal,
a v i r t u a l stack-oriented "pseudo-machine" is used as
the target computer for the generation of i n t e r m e d i a t e code by the compiler (p-code). order to execute a compiled program, interprets
the p-code,
In
either a software emulator of the v i r t u a l machine
or a final compilation phase translates the p-code into actual
machine code. In this section we w i l l define some of the extensions to a Pascal pseudo-machine, are needed to implement Pascai/L. Pascal/L pseudo-machine,
which
We w i l l present a part of the instruction list for the
which is adequate to describe the execution of two i m p o r t a n t
constructs in Pascal/L; parallel expressions and t h e where-do-elsewhere statement. The use of the Pascai/L pseudo-machine as the t a r g e t computer for the Pascal/L compiler has the additional advantage that an emulator for the pseudo-machine can be implemented on any standard computer, moved to LUCAS.
This means that programs can be tested before they are
The tests can include relevant performance estimations and extensive
error-checking on the p-code level,
6.4.1 Pascal/L Pseudo-machine The Pascal/L pseudo-machine has several registers and uses three distinct memory areas as shown in Figure 6.1.
On LUCAS,
two of the memories are located in the memory
area of the Master Processor (the Program Memory,
the Stack) and the third in the
Associative Array (the Parallel Memory). The Program Memory holds the instructions of the program being executed. PC,
A register,
points to the instruction that w i l l be executed next,
The Stack contains sequential variables, in the Stack,
the Program Memory and the Parallel Memory.
locations in the Stack: SP, AP,
the
sequential temporaries and pointers to locations
activation
the stack pointer,
pointer,
to
the
Two registers point to
points to the top-of-stack element and
activation
record
of
the
currently
executing
procedure. The Parallel Mern0r X holds parallel variables and parallel temporaries. Parallel Memory
is a 128-element vector and is defined by a descriptor ,
located in the Stack. format
Each entry in the
specification
which
is
A descriptor consists of a pointer to the Parallel Memory and a giving
the
precision
of
the
variable.
The
Parallel
Memory
is
131
organized in the f o r m of two stacks: the Parallel Stack and the Range' Stack . The register PSP points to the top element of the Parallel Stack, variables
and
parallel
temporaries
(used
during
expression
which contains parallel
evaluation
to
held
the
i n t e r m e d i a t e results). Each parallel variable has an associated bit-slice r the
declared
range
of
the
variable.
Each
the range indicator ~
temporary
on
the
which indicates
Parallel
Stack
has a
corresponding range indicator giving its actual range. The register RP points to the top element of the Range Stack. the
Current
(evaluation) Range is stored,
paralle! control statement,
e.g.
This is a bit-slice where
This range is set either when executing a
the where-do-elsewhere statement~
or as the result of
an indexing operation. The Stack is essential far the evaluation of expressions and is used to reference all the operands.
In stack-oriented machines all operands are pushed onto the stack from where
they
removed
are
by
the
arithmetic
and
logical
completed the result is pushed back onto the stack.
operators.
Once
the
operation
is
When operating on parallel variabtes~
it is often enough to push a descriptor on the Stack without also pushing the variable itself
onto
the
Parallel Stack.
In many simple
expressions (like adding two
parallel
variables and storing the result in a third) this w i l l result in a considerable reduction of the overhead involved.
132
Stack
Variables
Program Memor
128
Parallel Memory
Figure 6.1 The Pascal/L pseudo-machine,
The value of an entry in the Stack may have several interpretations=
a scalar value * a pointer to another entry in the Stack * a pointer to a location in the Program Memory * a descriptor to a variable in the Parallel Memory a descriptor to a temporary on the Parallel Stack, Upon procedure entry~
a local data area for the procedure is created both in the Stack
and in the Parallel Memory. area for
scalar
indicating
the
On the Stack this takes the form of a reserved memory
variables and for declared
ranges of
descriptors to the local parallel variables. the
local
parallel
variables are
Bit-s|ices
loaded and selector
133
variables are i n i t i a t e d if needed. The instructions needed to demonstrate expression evaluation and the where-do-elsewhere construct w i l l now be described. the
Stack
and OP for
instruction.
In the f o l l o w i n g ,
the Stack
entry
which
TOS stands for the entry on top of
is addressed by the operand f i e l d of an
(TOS) and (OP) stand for entries in the Parallel Stack whose descriptors are
TOS and OP r e s p e c t i v e l y .
LOAD
type,lev,disp
This instruction puts a variable on top of the Stack. on the values of " l e v " and " d i s p ' .
The location of the variable depends
Lev indicates the number of static levels to traverse
in order to find the a c t i v a t i o n record and disp is the offset within the a c t i v a t i o n record to find the variable.
Together they define the OP entry in the Stack.
value of the t y p e - p a r a m e t e r , Load a scalar. and
the
Load
value
a parallel
The value of the scalar is pushed on the Stack. is
Depending on the
d i f f e r e n t actions are taken:
put
variable.
in
the
location
indicated
by
the
(SP is incremented new
value
of
5P.)
The descriptor of the variable is pushed on the Stack,
but the variable is not moved to the Parallel Stack.
LIT
value
This i n s t r u c t i o n loads the literal specified in the p a r a m e t e r
COPY
on
the Stack.
type
Push TOS onto the Stack,
i.e.
make a duplicate of the element on top of the Stack.
Depending on the t y p e - p a r a m e t e r the f o l l o w i n g actions may be taken; O
Copy a scalar.
The value of TOS is pushed on the Stack.
Copy a parallel variable.
The descriptor which is in TOS is pushed on the Stack,
but the variable is not moved to the Parallel Stack.
Copy a parallel t e m p o r a r y .
The descriptor which is in TOS is pushed on the Stack,
a copy of the t e m p o r a r y is pushed on the Parallel Stack.
134
type,lev,disp
STORE
This
instruction
parameter~ O
stores TOS in the OP location.
Depending on the value of the type-
the following actions may be taken:
TOS
and
OP
are
both
scalars.
Copy
TOS and OP are both parallel variables.
TOS
into
location
OP
and
First compute a selector by p e r f o r m i n g
the operation A N D between the declared range of OP and the Current by register
RP.
Then use this
operation in the Parallel Stack. selector, if
i.e.
not~
TOS
a
selector while
performing
Range - as a field
copy
Check that the declared range of TOS overlaps the
that TOS is defined in every component which has been copied~
raise
is
TOS.
They are both represented on the Stack by
descriptors to entries in the P a r a l l e l Stack.
indicated
pop
a
parallel
run
time
error.
temporary
and
Pop OP
is
the a
TOS
parallel
descriptor
off
variable.
They
the are
represented on the Stack by descriptors to entries in the Parallel Stack. the same actions as in 1),
and
Stack. both
Perform
then pop (TOS) o f f the Parallel Stack by adjusting PSP.
TOS is scalar and OP is a parallel variable.
Compute a selector as above and use
it
the
while
performing
a
field
load
in
TOS is a parallel variable and OP is a scalar. that
this
error. location.
selector
has one single TRUE
Parallel
Stack.
Pop
Compute a selector as above.
element,
and if
not,
TOS. Check
raise a run t i m e
Use the selector to read out the variable element and store it in the OP Pop the TOS descriptor off the Stack.
TOS is a parallel temporary and OP is a scalar.
Perform the same actions as in 4),
then pop (TQS) o f f the Parallel Stack.
ST[N
type
This store-indirect instruction is similar to S T O R E , second element of the Stack (TOS-I),
but the target address is in the
and not specified in the instruction.
parameter has the same meaning as in the S T O R E
instruction.
The type-
135
NOT/NEG
These
type
are
unary
negation.
instructions
for
forming
They operate on TOS,
the
Boolean
complement
and
the
arithmetic
pop the Stack and push the result back on the Stack.
Depending on the value of the t y p e - p a r a m e t e r we have" g
TOS
is
a
scalar.
Perform
TOS is a parallel variable. entry
It
in the Parallel Stack.
Stack which
the
operation
and
replace
TOS
with
the
result.
is represented on the Stack by a descriptor to an
Execute the instruction
is described by TOS.
on the entry
in the Parallel
Push the result on the Parallel Stack with
the
declared range of TOS stored as range i n d i c a t o r and replace TOS by a descriptor to the new element. TOS is a parallel t e m p o r a r y .
[t is represented on the Stack by a descriptor to an
entry
Execute the instruction
in the Parallel Stack.
Stack.
on this value in the Parallel
Leave the result in the same location of the Parallel Stack w i t h o u t changing
the range indicator.
ADD/SUB/IvLILT/D[V/IvlOE)
type
These instructions represent binary operations which operate on the two top elements of the
Stack.
Similar
to
the previous
instructions,
the t y p e - p a r a m e t e r
operands are scalars or if one or both operands are parallel, scalars, at
least
indicates if
both
in the case where both are
the result is pushed onto the Stack a f t e r the two operands have been popped. one
of
Associative A r r a y ,
the
operands
is
paratle],
then
the
operation
is
performed
in
If the
leaving the resuit on the Parallel Stack a f t e r the operands have been
popped. The t y p e - p a r a m e t e r can take any of the values 0 to 8,
as seen in Table 6.1.
136
TOS-1
is
= = = = = = = =
parallel temporary
parallel variable
scalar TOS i s = = = = = =
scalar
1
2
parallel variable
4
5
7
8
parallel
temporary
Table 6.t The value of the type-parameter in binary operations
SETR~E
Compute
type a new value of Current
Range by performing a Boolean AND
Current Range and the selector in (TOS). the Range Stack.
between the
Push the old value of the Current Range onto
Depending on the value of the type-parameter,
the following actions
are also taken:
0
TOS
is
a
parallel
variable.
TOS is a parallel temporary.
Pop
the
TOS
descriptor
off
the
Stack.
Pop (TOS) off the Parallel Stack and pop the TOS
descriptor off the Stack.
POP~ Restore Current Range to a previous value by popping the Range Stack.
137
SWAPRANGE
Exchange the Current Range with the top element of the Range Stack.
6.4.2 Parallel Expressions In order to use the pseudo-machine for evaluation of a parallel expression in a Pascal/L program~
the expression is translated by the compiler to a form of postfix notation.
This form is ideal when a stack is used to compute the expression, simple rule may be used,
since the following
while scanning the expression from left to right"
If the next symbol is an operand then push its value on the stack,
else (it is an
operation) use the element(s) on top of the stack as operand(s) to the operation, pop the operand(s) off the stack and push the result.
When starting the computation, reached, as
well
the stack is empty and when the end of the expression is
the result is the only element [eft on the stack. as
constant%
the
notation
is
extended
so
Since we deal with variables
that
an operand no
longer
is
represented by its value but by an instruction which should be executed in order to put the value on top of the stack. This describes a commonly used technique for the intermediate code in language compilers and is the philosophy behind the Pascal p-code [Wirth71].
The code generated from the
Pascal/L compiler consists of instructions similar to those described in Section 6.4.1. Without dealing w i t h how the transformation process works~
we w i l l took at an example
of a parallel assignment statement in Pascal/L;
var P1,P2 ODD I
:
parallel array[0..127] o f integer(32)~ : selector[0..127];
: integer~
begum
PI[ODD]:=P2-P1 *(2+I);
The statement PI[ODD]:=P2-PI~(2+I) has been translated into parallel p-code and w i l l be executed on the Pascal/L pseudo-machine. Figure 6.2, refer to.
In the p-code program~
which is shown in
we have replaced the lev/disp-parameters w i t h the name of the variable they
138
Instr. .
.
.
1 2 3 4 5 6 7 8 9 10 11 12
.
.
.
.
.
.
.
.
.
Parameter .
.
.
.
.
LOAD LOAD SETRANGE LOAD LOAD LIT LOAD ADD IvUI_T SUB STIN POPRANGE
.
.
.
.
.
.
.
.
.
.
.
.
.
TOS becomes .
.
.
.
1,P1 1,ODD 0 1,P2 1,P1 2 O,I 0 1 7 2
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
descriptor t o p a r . v a r . PI descriptor to selector ODD descriptor t o p a r . v a r . P1 descriptor t o p a r . v a r . P2 descriptor t o p a r . v a t . P1 scalar ( t h e v a t u e 2) scalar (value of I) scalar (value of 2+I) descriptor to par. temp, descriptor to par. temp. <empty> <empty>
Figure 6.2 Parallel p-code for the statement PI[ODD]:= P2-P1*(2+I).
6.4.3 Where Statement The general idea for executing a control statement of the form: where selector expression do statement-a elsewhere statement-b on the Pascai/L pseudo-machine is that the selector expression is used to calculate two new values of Current Range which are used when executing statement-a and statement-b respectively.
By using the Range Stack to save the old value of Current Range,
the
problem of how to handle nested where-statements (and similar constructs) is solved. Upon entry of a where-statement,
Current Range is pushed on the stack and restored
after the statement has been executed. A first a t t e m p t to translate the where-do-elsewhere construct results in the p-code given in Figure 6.5. (R5),
In the figure the Current Range (CR) and the contents of the Range Stack
with the top element to the left,
are shown.
139
Instr. .
.
.
.
.
.
.
.
.
.
.
.
Parameter .
.
.
.
.
.
.
0
selector
1 2 } 4 5 6 7 8
expression COPY blOT SETRPC,~E SWAP~ SETRANGE statement-a POP~E SWAP~
9 10
statement-b POPFUXNGE
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
CR .
.
.
.
.
.
.
.
.
.
.
RS .
.
R0 1 or 1 or 1
Z 2
0 or
t
R0 R0 Rb R0 Ra Ra R0 Rb
R0 Rb R0~Rb R0,Rb Rb R0 RO
Rb R0
Figure 6.3 Preliminary translation of the where-construct.
Before executing the instruction on line 1, (TOS).
Depending on the type of expression,
parallel temporary. Stack.
we assume that the selector expression is in
The first
this is either a parallel variable or a
instruction produces a copy of this value on the Parallel
Instructions 2 and 5 invert the value and calculate a new range,
the Current Range. following
SWAPRANGE
statement-a.
After
by masking with
This range will be used during the execution of statement-b. and
SETRANQE
execution
of
operations
statement-a,
calculate the
Range
the
Current
Stack
is
Range
popped,
The for and
SWAPRANGE sets the Current Range to the previous calculated value for statement-b. Execution of the where-statement terminates with restoring Current Range to its initial value. In Section 6.5.4 where the control statements of Pascal/L were introduced~ discuss the semantic aspects of executing them on an SIMD computer.
we did not
Intuitively,
we
feel that the execution of the do-part and the elsewhere-part of a where-statement ought to be independent and that no order should exist between statement-a and statement-b. However, processed
when one
executed
after
the
on other.
LUCAS The
as described above, following
example
the
two
illustrates
statements
why
the
are
scheme
presented is insufficient to assure that the result corresponds to the desired semantics of the construct.
140
vat
P1,P2 = parallel array[0..5] o f integer(52); ODD
: selector[0..3]:=(1,5 => true);
begin °.*
where ODD d o Pl:=rotate(P2,1) elsewhere P2:=rotate(Pl,1);
Assume that the i n i t i a l values are as shown in Figure 6.4 (a). execution of the statements, decide
that
the
independent of statement-a
result
the result w i l l be d i f f e r e n t
of
whether
executing
statement-a
one
Depending on the order of
as seen in the figure.
statement,
say
statement-b,
has been executed or not,
does not change any variables until
statement-b
we
must
If we
should require
has been executed.
be that And
similarly the other way around. Figure 6.4 (b) shows the result in the case where both statements calculate their results and
update
the
independent Range.
variables
of
when
the order
of
both
are
terminated.
execution since
they
Note
that
use d i f f e r e n t
these
updates
values on the
are
Current
Figure 6.4 (c) shows the result when statement-a is executed before s t a t e m e n t - b
and Figure 6.4 (d) when statement-b is executed before statement-a.
index .
.
.
.
.
P1 .
.
.
.
.
.
P2 .
.
.
.
.
P1 .
.
.
.
.
.
.
.
.
P2 .
.
.
.
P1 .
.
.
.
.
.
.
.
.
P2 .
.
.
.
P1 .
.
.
.
.
.
.
.
P2
.
.
.
.
0 1
a b
A B
a A
d B
a A
C B
a d
d B
2 5
c d
C D
c C
b D
c C
A D
c b
b D
a)
b)
c)
Figure 6.4 Result depends on the order of execution. excution.
(c)
statement-a
executed
d)
(a) i n i t i a l values.
before
statement-b.
(b) independent (d)
statement-b
executed before statement-a.
In order to obtain independence between the two statements, be used to store the new values of assigned parallel variables, shown in Figure 6.5.
t e m p o r a r y locations must resulting in the p-code
141
[nstr. .
.
.
.
0 1 2 3 4 5 6 7 8 9 I0 11
.
.
.
.
.
.
Parameter .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
CR .
.
.
.
.
.
.
.
.
.
RS .
.
.
.
.
.
.
.
.
R0
selector expression COPY 1 or 2 NOT 1 or 2 SETRANGE 1 SWAPRANGE SETRANQE 0 or 1 statement-a (mod i f i e d ) POPRANGE SWAPRANGE statement-b POPRANGE copy temporaries to parallel variables
RO RO Rb R0 Ra Ra
R0 Rb RO~Rb RO~Rb
R0 Rb Rb R0
Rb R0 R0
Figure 6,5 Translation of the where-construct.
While executing statement-a~
all parallel variables which appear on the l e f t hand side of
an assignment (statement-a may be a compound statement) are copied to a t e m p o r a r y area.
For each variable copied~
used when updating the variable. Statement-a is now executed,
there is also an "modify-selector"~
Which w i l l tater be
This selector is initiated to an all-false value. but the following
modifications have been made in the
code:
Ail
assignments
are
to
the
temporary
locations
of
the
variables.
The
corresponding modify-selector is updated to r e f l e c t which elements have been changed in the temporary location. When using a variable which have been copied to a temporary location~ value Statement-b
is is
taken
from
executed with
t e m p o r a r y locations~
this
Iocation~
no changes.
Finally
not
from
variables are
the
its
variable.
updated from
their
using the corresponding modify-selectors as indices in the updates.
A similar technique is employed for the parallel case-statement.
142
6.5 PROGRAMMING EXAMPLES
Examples of programs written in Pascal/L can be found in the following chapters, only two examples wiU be presented here.
and
They are both related to the application
studies in the chapters 8 and 9. Example 1.
Outer Perimeter of Object s
An algorithm for
finding the outer perimeter of objects in a binary image works as
follows (see Example 14 of Section %4.4): 1) 2)
Mark
one
Propagate
picture the
element
marker
to
at
the
neighbours
edge in
the
which
belongs
edge column
to which
the
background
belong
to
the
baekgound 3)
Copy
markers
to
elements
4)
Propagate the markers to neighbeurs in the column which belong to the background
5)
Scan back
and forth
in
over the
the
next
entire
column
image until
This algorithm can be expressed in Pascal/L. as follows:
Program Perimeter; (* Find outer perimeter of objects in Boolean image [ *) vat I,M : parallel array[O..127,0..127] of Boolean; finished : Boolean; k : integer; (*used to indicate columns*) begin (* edge column *)
white and where not(M[*,O]) and not(l[*,O]) and (shift(M[*,O],1) or shift(M[*,O],-1)) do M[*,O]:=true; finished:=false; white not finished do begin finished:=true; (* scan l e f t *) for k:=l to 127 do begin M[*,k]:=net([[*,k]) and M[*,k-1];
which
belong to
the background
no new markers are
produced
143
while and where not(M[%k]) and not(it%k]) and (shift(M[*,k],l) or shift(M[*,k],-t)) do begin M[%k]:=true; finished:=false; end~ end; (* scan right *) if not finished then for k:=126 downto 0 do begin M[**k]:=not(I[*~k]) and M[%k+l]; while and where not(M[*~k]) and not(It%k]) and (shift(M[*,k],t) or shift(M[%k],-1)) do begin M[%k]:=true; finished:=false; end; end; end; end.
Example 2.
Project
One commonly
used operation
in
the
relational data
base model :s the
PROJECT
operation: PROJECT R1 OVER A GIVING R2 where R1 and R2 are relations and A an attribute of R1. relation~
R2,
This operation creates a new
from R1 by discarding attributes other than A.
After that~
all redundant
tuples are removed from R2. Each relation has a corresponding mark selector which indicates where tupies are defined. A description of the operation can be found in [Kruzela83].
Program Project~ vat R I M A R K : selector[0..127]: (* shows where R1 defined *) R2MARK : selector[0..127]; (* shows where R2 defined *) TEMP1 = selector[0..127]; (* marks remaining tuples in R1 *) TEMP2 : selector[g..127]~ (* marks all duplicates of the (* tupte that is under comparison *) RI : parallel array[O..127] of record A,B,C : string(20); end~ INSTANCE : string(20);
144 begin ..... (* relation R1
is input and R I N I A R K
TEMPI :=R1MARK; INSTANCE:=RI[first(R1MARK)].A;
is initiated *)
(* select first instance of (* attribute A *)
while any do begin TEMP2:=(INSTANCE=RI[TEMPI].A); (* select duplicates *) TEMPI[TEMP2]:=not TEMP1; (* mark as analylzed *) R2MARK[first(TEIx4P2)]:=true; (* the first is included in R2 *) INSTANCE:=RI[first(TEMP1)].A; (* get the next distinct instance end~ (* of attribute A *) end.
Part 3
APPLICATION STUDIES
Chapter 7 SOME WELL-KNOWN PROBLEMS IMPLEMENTED ON LUCAS
7.1 INTRODUCTION It
is
often
seen
that
computations
performed
in
separate application
common m a t h e m a t i c a l tools and computational techniques.
If
areas rely
on
it can be shown that a
particular computer design is well suited for the application of one or several widely used tools,
it means that the computer may be useful in many application areas.
In this c h a p t e r we study the i m p l e m e n t a t i o n on LUCAS of three important classes of computations,
namely
matrix
multiplication,
computation
of
the
discrete
transform (DFT) by means of the fast Fourier transform (FFT) algorithm, graph theoretic problems.
Fourier
and solution of
They all represent tools and techniques that are not l i m i t e d to
any specific realm of computation. Studies of m a t r i x multiplication on parallel computers have been made in connection with the DAP project [F|anders et ai.77] and in [Pease'/7]. very d i f f e r e n t from the one used on LUCAS, data
routing
problem.
The approach
The DAP interconnection scheme is
which results in d i f f e r e n t solutions to the
taken by
Pease on a proposed cube-connected
processor array also differs widely f r o m the methods reported here. The FFT algorithm for the calculation of the DFT has been known since 1965 [Cooley and Tukey65].
It is well known that it can be mapped e f f i c i e n t l y onto a perfect shuffle-
connected processor array [Pease68,
Stone71].
However,
the implementation on LUCAS
is probably the first one in practice. Graph theoretic problems are relevant in many application areas. open to e f f i c i e n t
Very often they are
solution on parallel computers [Quinn and Dee 84].
solving the shortest path problem on LUCAS is given.
An algorithm for
On other graph theoretic problems
we also demonstrate how algorithms designed to be e f f i c i e n t on conventional computers can be adapted to a parallel computer like LUCAS. The three computational areas dealt with in this chapter put rather diverse demands on LUCAS.
Matrix
multiplication
and
Fourier
transformation
utilize
interconnection network to a high degree and require that it be effective,
the
parallel
so that full
147
parallelism carried
can be m a i n t a i n e d all the t i m e ,
out
performed
without
conflicts.
The graph
efficiently,
and
also
that
LUCAS
turns
out
to
performed.
7.2 M A T R I X
which
means that c o m m u n i c a t i o n
theoretic some
problems require
that
unconventional
data
quite
meet
these
diverse
demands
must be
searches be passing fairly
be well.
MULTIPLICATION
The m u l t i p l i c a t i o n
of t w o n by n e l e m e n t m a t r i c e s consists of the f o r m a t i o n of n 2 inner
products of pairs of n - e l e m e n t vectors.
An inner product of t w o v e c t o r s is defined as
* = a l b t + a2b 2 +...+ anb n. When m u l t i p l y i n g t w o matrices,
A and B,
the e l e m e n t of the i:th row of column no.
is f o r m e d as the inner product of the vectors comprising row no.
j
i of A and column no.
jofB. The
traditional
sequentially,
method
for
multiplication
one a f t e r the other.
of
two
matrices
computes the inner products
Each inner product is likewise c o m p u t e d sequentially,
as a sequence of m u l t i p l i c a t i o n s and additions. Paratlelizing number
the
of
computation
processors
can
available
be
made
compared
in many to
the
various ways. size
of
the
Depending matrices,
on the different
approaches may be f a v o u r a b l e .
7.2.1 n x n M a t r i c e % We f i r s t
n Processors
consider the case when n processors are a v a i l a b l e .
The most obvious way of
using the p a r a l l e l i s m is to c a l c u l a t e the n m u l t i p l i c a t i o n s of an inner product c o m p u t a t i o n simultaneously.
This is known as the " i n n e r - p r o d u c t
m e t h o d " [Hackney and 3esshope 81].
The r e m a i n i n g addition of the terms of each inner product can be made by n processors in
O(log
n)
time
shuffle+exchange addition
is small
using
network.
a
suitable
Since,
compared
to the
a d d i t i o n step is not v e r y severe. The t w o vectors that we m u l t i p l y w i t h each other, the A - m a t r i x
communication
on a b i t - s e r i a l multiplication
However,
network,
computer,
time,
the
perfect time
the reduced p a r a l l e l i s m
in the
in order to compute an inner-product must be aligned
is stored one column in each processor's m e m o r y ,
the B - m a t r i x
If
must be
This w i l l align the rows of A w i t h the columns of B.
If the m a t r i c e s are loaded into the m e m o r y for m u l t i p l i c a t i o n only, However,
for
there are o t h e r problems w i t h this approach:
so t h a t corresponding elements are available to the same processor.
stored one r o w in each m e m o r y .
any problem.
e.g
the e x e c u t i o n
this need not cause
if the m a t r i c e s are c r e a t e d in the parallel a r r a y or are subject
148
to
other
operations that
perhaps demand the
same storage method for
alignment problem has to be solved in the array. Multidimensiona! accessible.
Access
Memory
both,
the
STARAN has this possibility through its
[Batcher77],
where
both
rows
and
columns
are
This is not possible on LUCAS.
Instead of computing each inner product with the largest possible parallelism, products can be computed simultaneously.
many inner
( A total of n2 inner products are to be
computed). Referring to Figure 7.1,
in order to form the first column of the result matrix,
the
following n inner products must be computed=
A A ...A > * 00 01 02 0,n-1 00 10 20 n-l,O * 10 11 12 1,n-1 00 10 20 n-l,O
n-l~0
A
n-1,1
...A
n-l,n-1
> *
B B ...B > 00 10 20 n-l,0
These expressions show that the first column of A is to be multiplied by BOO, column by B10 , accumulated,
the third by B20 ,
etc.
the second
The results of these multiplication