Advances in Monolithic Microwave Integrated Circuits for Wireless Systems: Modeling and Design Technologies

Advances in Monolithic Microwave Integrated Circuits for Wireless Systems: Modeling and Design Technologies Arjuna Marz...

Author: Arjuna Marzuki

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Advances in Monolithic Microwave Integrated Circuits for Wireless Systems: Modeling and Design Technologies Arjuna Marzuki Universiti Sains Malaysia, Malaysia Ahmad Ismat Bin Abdul Rahim Telekom Malaysia R&D Sdn. Bhd, Malaysia Mourad Loulou University of Sfax, Tunisia

Senior Editorial Director: Director of Book Publications: Editorial Director: Acquisitions Editor: Development Editor: Production Editor: Typesetters: Print Coordinator: Cover Design:

Kristin Klinger Julia Mosemann Lindsay Johnston Erika Carter Development Editor Sean Woznicki Natalie Pronio, Jennifer Romanchak Jamie Snavely Nick Newcomer

Published in the United States of America by Engineering Science Reference (an imprint of IGI Global) 701 E. Chocolate Avenue Hershey PA 17033 Tel: 717-533-8845 Fax: 717-533-8661 E-mail: [email protected] Web site: http://www.igi-global.com Copyright © 2012 by IGI Global. All rights reserved. No part of this publication may be reproduced, stored or distributed in any form or by any means, electronic or mechanical, including photocopying, without written permission from the publisher. Product or company names used in this set are for identification purposes only. Inclusion of the names of the products or companies does not indicate a claim of ownership by IGI Global of the trademark or registered trademark.

Library of Congress Cataloging-in-Publication Data

Advances in monolithic microwave integrated circuits for wireless systems: modeling and design technologies / Arjuna Marzuki, Ahmad Ismat Bin Abdul Rahim, and Mourad Loulou, editors. p. cm. Includes bibliographical references and index. Summary: “This book is a central source of knowledge on monolithic microwave integrated circuit development, containing research on theory, design, and practical approaches to integrated circuit devices”-- Provided by publisher. ISBN 978-1-60566-886-4 (hardcover) -- ISBN 978-1-60566-887-1 (ebook) -- ISBN 978-1-61350-119-1 (print & perpetual access) 1. Microwave integrated circuits--Design and construction. 2. Microwave amplifiers--Design and construction. 3. Low noise amplifiers--Design and construction. I. Marzuki, Arjuna, 1975- II. Abdul Rahim, Ahmad Ismat bin, 1971- III. Loulou, Mourad, 1968TK7876.A325 2012 621.381’32--dc23 2011014214

British Cataloguing in Publication Data A Cataloguing in Publication record for this book is available from the British Library. All work contributed to this book is new, previously-unpublished material. The views expressed in this book are those of the authors, but not necessarily of the publisher.

List of Reviewers Amiza Rasmi, Telekom Malaysia Research & Development Sdn. Bhd., Malaysia Norhapizin K., Telekom Malaysia Research & Development Sdn. Bhd., Malaysia Norlaili Mohd. Noh, Universiti Sains Malaysia, Malaysia Lim Chee Peng, Universiti Sains Malaysia, Malaysia Mohd Fadzil bin Ain, Universiti Sains Malaysia, Malaysia Arjuna Marzuki, Universiti Sains Malaysia, Malaysia Mohd Tafir Mustaffa, Universiti Sains Malaysia, Malaysia Mohd Nizam Osman, Telekom Malaysia Research & Development Sdn. Bhd., Malaysia Siti Maisurah Binti Mohd Hassan, Telekom Malaysia Research & Development Sdn. Bhd., Malaysia Ahmad Ismat Abdul Rahim, Telekom Malaysia Research & Development Sdn. Bhd., Malaysia M. Fakhfakh, University of Sfax, Tunisia Meriam Ben Amor, EleCom/LETI & National Engineering School of Sfax, Tunisia M.Loulou, University of Sfax Tunisia, Tunisia Hassene Mnif, National Engineering School of Sfax (ENIS), Tunisia Mohamed Mabrouk, ISETCOM de Tunis and CIRTA’COM/SUPCOM, Cité Technologique des Communications, Tunisia

Table of Contents

Preface.................................................................................................................................................... xi Section 1 Theory Chapter 1 Multi-Standard Multi-Band Reconfigurable LNA................................................................................... 1 Mohd Tafir Mustaffa, Universiti Sains Malaysia, Malaysia Chapter 2 LNA Inventions...................................................................................................................................... 24 Norlaili Mohd. Noh, Universiti Sains Malaysia, Malaysia Chapter 3 Multiband Multi-Standard LNA with CPW Transmission Line Inductor............................................. 48 M. Ben Amor, University of Sfax, Tunisia M. Loulou, University of Sfax, Tunisia S. Quintanel, ENSEA University of Cergy Pontoise, France D. Pasquet, Microelectronics and Semiconductor Physics Laboratory (LaMIPS), NXP-CRISMAT-ENSICAEN, France Chapter 4 Design of Low Noise Amplifiers through Flow-Graphs and their Optimization by the Simulated Annealing Technique............................................................................................................................. 69 M. Fakhfakh, University of Sfax, Tunisia M. Boughariou, University of Sfax, Tunisia A. Sallem, University of Sfax, Tunisia M. Loulou, University of Sfax, Tunisia Chapter 5 Optimization of CMOS Quadrature VCO Using a Graphical Method.................................................. 89 Hassene Mnif, University of Sfax, Tunisia Dorra Mellouli, University of Sfax, Tunisia Mourad Loulou, University of Sfax, Tunisia

Section 2 Design Chapter 6 The Design and Modeling of 2.4 and 3.5 GHz MMIC PA.................................................................. 105 Chin Guek Ang, Universiti Sains Malaysia, Malaysia Chapter 7 The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA...................................................... 157 Ching Wen Yip, Universiti Sains Malaysia, Malaysia Chapter 8 Design of Medium Power Amplifier Using GaAs PHEMT Technology for Wireless Applications......................................................................................................................................... 185 Amiza Rasmi, Telekom Malaysia Research & Development Sdn. Bhd., Malaysia Chapter 9 The Design and Modeling of 30 GHz Microwave Front-End............................................................. 205 Wan Yeen Ng, Universiti Sains Malaysia, Malaysia Xhiang Rhung Ng, Universiti Sains Malaysia, Malaysia Section 3 Practical Approaches Chapter 10 Inventions of Monolithic Microwave Integrated Circuits................................................................... 240 Arjuna Marzuki, Universiti Sains Malaysia, Malaysia Chapter 11 RF and Microwave Test of MMICs from Qualification to Mass Production...................................... 333 Mohamed Mabrouk, ISETCOM de Tunis and CIRTA’COM/SUPCOM, Cité Technologique des Communications, Tunisia Compilation of References................................................................................................................ 346 About the Contributors..................................................................................................................... 358 Index.................................................................................................................................................... 362

Detailed Table of Contents

Preface.................................................................................................................................................... xi Section 1 Theory Chapter 1 Multi-Standard Multi-Band Reconfigurable LNA................................................................................... 1 Mohd Tafir Mustaffa, Universiti Sains Malaysia, Malaysia In this chapter, the aim is to design and implement a new low noise amplifier (LNA) for a multi-standard mobile receiver based on reconfigurability concept. The LNA design is based on the inductivelydegenerated common-source (IDCS) topology as it has been proven to be a good choice in designing multi-standard multi-band LNA. The design is using 0.18 µm CMOS technology. The reconfigurable LNA has been designed to operate in two bands of standards consisting the bands range from 800 to 1000-MHz (lower band) and 1800 to 2200-MHz (upper band). The simulation results exhibit gain S21 of 12.9-dB for lower band and 12.4-dB for upper band, input reflection S11 of -14.5-dB and -17.2-dB for both bands, and output return loss S22 of -14.7-dB and -26-dB for lower and upper band making the LNA suitable for most of the mobile communication applications. The LNA also exhibits the noise of figure of 2.55-dB and 2.3-dB for lower and upper band respectively. The circuit consumes 26.5 mW when operating in lower band mode and uses 18.8 mW of power when operating in upper band mode. Chapter 2 LNA Inventions...................................................................................................................................... 24 Norlaili Mohd. Noh, Universiti Sains Malaysia, Malaysia The main design goals of an LNA are to achieve low noise figure, high gain, good linearity and good matching and reverse isolation. The choice of the LNA topology is therefore very important to suit the design application. Five LNA topologies were studied, analyzed and compared in this chapter. The topologies are the Simultaneous Noise and Input Matching (SNIM), Power-constrained Simultaneous Noise and Input Matching (PCSNIM), Current-reuse (CR) and Folded-cascode (FC) LNAs. The last topology is the PCSNIM with buffer. The circuits are analyzed in detail in terms of their functionality and compared based on the LNAs typical performance metrics. From the analysis, the PCSNIM technique can improve matching and noise performance of the inductively degenerated cascode. The current-reuse

is found to consume less current but maintaining the circuit’s transconductance to achieve the desirable gain. The folded-cascode operates at lower voltage and hence is suitable for low-powered designs. Consequently, it is also resulting in the lowest noise-figure amongst the other designs. Chapter 3 Multiband Multi-Standard LNA with CPW Transmission Line Inductor............................................. 48 M. Ben Amor, National Engineering School of Sfax, Tunisia M. Loulou, National Engineering School of Sfax, Tunisia S. Quintanel, ENSEA University of Cergy Pontoise, France D. Pasquet, Microelectronics and Semiconductor Physics Laboratory (LaMIPS), NXP-CRISMAT-ENSICAEN, France LNA is one very essential block in the RF receiver. Due to the growth of the standard evolution, this component must handle several frequency bands with the best performances. This chapter presents a wide band LNA design for IEEE802.16 standard with the CMOS 0.35µm technology. In this LNA, the authors use a CPW transmission line to design the inductive degeneration inductor of 0.38nH. This circuit has a S21 of 12dB, a noise figure less than 3dB and an input/output reflexion coefficient less than -10dB between 2 and 6GHz. The CPW line presents a characteristic impedance of 120Ω, an inductance of 0.38nH, a capacitance of few fF and a resistance less than 2Ω on the desired frequency band. Chapter 4 Design of Low Noise Amplifiers through Flow-Graphs and their Optimization by the Simulated Annealing Technique............................................................................................................................. 69 M. Fakhfakh, University of Sfax, Tunisia M. Boughariou, University of Sfax, Tunisia A. Sallem, University of Sfax, Tunisia M. Loulou, University of Sfax, Tunisia This chapter presents the optimal design of Low Noise Amplifiers (LNAs). The basic idea consists of optimizing performances of LNAs by a direct action on the scattering parameters. A symbolic approach, namely the Coates Flow-Graph technique, is used to automatically generate symbolic expressions of the impedance parameters and, thus, those of the scattering parameters. The Simulated Annealing optimization technique is applied to determine the optimal sizing of the LNA. ADS simulation results are given to show the viability of the proposed approach. Chapter 5 Optimization of CMOS Quadrature VCO Using a Graphical Method.................................................. 89 Hassene Mnif, University of Sfax, Tunisia Dorra Mellouli, University of Sfax, Tunisia Mourad Loulou, University of Sfax, Tunisia This chapter describes the design and the optimization of Quadrature Voltage Controlled Oscillators (QVCOs) based on the coupling of two LC-tank VCO. This work covers the phase noise analysis, a graphical optimization approach, already used to optimize LC oscillator phase noise (Andreani, Bonfanti, Romano, & Samori, 2002), to optimize QVCO phase noise while satisfying design constraints such as

power dissipation, tank amplitude, tuning range and start up condition. The cross-coupling transistors impact on phase noise for different configurations is especially addressed. The obtained BS-QVCO, using 0.35µm CMOS process, can be tuned between 2.2GHz and 2.58GHz, and shows a phase noise of -129 dBc/Hz at 1MHz offset from a 2.4 GHz carrier, for a current consumption of 9.25mW. The equivalent phase error and amplitude error between I and Q signals are respectively 0.65° and 1.87%. Section 2 Design Chapter 6 The Design and Modeling of 2.4 and 3.5 GHz MMIC PA.................................................................. 105 Chin Guek Ang, Universiti Sains Malaysia, Malaysia This chapter discusses the design of MMIC power amplifiers for wireless application by using 0.15 μm GaAs Power Pseudomorphic High Electron Mobility Transistor (PHEMT) technology with a gate width of 100 μm and 10 fingers at 2.4 GHz and 3.5 GHz. The design methodology for power amplifier design can be broken down into three main sections: architecture design, small-signal design, and largesignal optimization. For 2.4 GHz power amplifier, with 3.0 V drain voltage, the amplifier has achieved 17.265 dB small-signal gain, input and output return loss of 16.310 dB and 14.418 dB, 14.862 dBm 1-dB compression power with 12.318 % power-added efficiency (PAE). For 3.5GHz power amplifier, the amplifier has achieved 14.434 dB small-signal gain, input and output return loss of 12.612 dB and 11.746 dB, 14.665 dBm 1-dB compression power with 11.796 % power-added efficiency (PAE). The 2.4 GHz power amplifier can be applied for Wireless LAN applications such as WiFi and WPAN whereas 3.5 GHz power amplifier for WiMax base station. Chapter 7 The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA...................................................... 157 Ching Wen Yip, Universiti Sains Malaysia, Malaysia LNA is an electronic amplifier that is required in receiver systems to increase the amplitude of the very low level signals from the antenna without adding too much noise. Software Advance Design System (ADS) was used to simulate the circuit and design the layout. LNA was designed using cascode topology with feedback techniques which produces better matching and unconditionally stable over the entire desired frequencies. For the 2.4 GHz operation, the amplifier achieves gain of 14.949 dB, noise figure of 1.951 dB and input reflection coefficient of -10.419 dB. With operating voltage supply at 3V, the total current consumption is 13 mA. For 3.5GHz amplifier, gain is 22.985 dB, noise figure is 1.964dB, input reflection coefficient is -12.427 dB and current consumption is 18 mA. Chapter 8 Design of Medium Power Amplifier Using GaAs PHEMT Technology for Wireless Applications......................................................................................................................................... 185 Amiza Rasmi, Telekom Malaysia Research & Development Sdn. Bhd., Malaysia

This chapter presents the design of single-stage and two-stage medium power amplifiers (MPAs) using GaAs PHEMT technology for the wireless applications. The single-stage MPA was designed using 0.15 μm GaAs PHEMT technology to be operated at 3.5 GHz whereas the two-stage MPA was designed using 0.5 μm GaAs PHEMT technology to be operated at 5.8 GHz. The MPAs employ a simple RC feedback in order to linearize the stages as well as to improve the circuit stability and to control the gain. In addition, the load-pull technique was used in order to define the optimum load and maximum output power. Therefore, the performance of the proposed amplifier in this paper is discussed in terms of stability, gain, power-added efficiency (PAE), and output power. The simulated data of the proposed MPAs is then compared with the measured data of the fabricated MPAs. Chapter 9 The Design and Modeling of 30 GHz Microwave Front-End............................................................. 205 Wan Yeen Ng, Universiti Sains Malaysia, Malaysia Xhiang Rhung Ng, Universiti Sains Malaysia, Malaysia This chapter aims to discuss a millimeter wave integrated circuit (MMWIC) in frequency of 30 GHz especially switch (SPDT), medium power amplifier (MPA) and low noise amplifier (LNA). The switch is developed using a commercial 0.15 µm GaAs pHEMT technology. It achieves low loss and high isolation for millimeter wave applications. The circuit and layout drawing of SPDT switch are done by using Advanced Design System (ADS) software. The layout is verified by running the Design Rules Check (DRC) to check and clear all the errors. At the operating frequency of 30 GHz, the reported SPDT switch has 1.470 dB insertion loss and 37.455 dB of isolation. It also demonstrates 26.00 dBm of input P1dB gain compression point (P1dB) and 22.975 dBm of output P1dB. At a supply voltage of 3.0 V and 30 GHz operating frequency, this two-stage LNA achieves an associated gain of 21.628 dB, noise figure (NF) of 2.509 dB and output referred 1-dB compression point (P1dB) of -11.0 dBm, the total power consumptions for the LNA is 174 mW. At a supply voltage of 6.0 V and 30 GHz operating frequency, a 2-stage MPA achieves a linear gain (S21) of 13.236 dB, P1dB of 22.5 dBm, power gain of 11.055 dB and the PAE of 14.606%. The total power consumption for the MPA is 1.122 W. The 30 GHz LNA and PA can be applied in direct broadcast satellite (DBS), automotive radar transmitter and receiver. Section 3 Practical Approaches Chapter 10 Inventions of Monolithic Microwave Integrated Circuits................................................................... 240 Arjuna Marzuki, Universiti Sains Malaysia, Malaysia This chapter deals with the concept of first time right IC. A development of subsystems for wireless application is used as test case. The subsystems are Low Noise Amplifier (LNA), Medium Power Amplifier (MPA) and Variable Signal Generator (VSG). Several issues such as suitable multiband design flow and high speed switch must be solved. A new design methodology of integrated circuits for multiband application is presented. The design methodology is modified from a typical Monolithic Microwave Integrated Circuit (MMIC) flow. Core based design, parasitic aware approach and power constrained optimization are introduced into the new design flow. The same core circuit topology is used as main

block to design 2.4 GHz and 3.5 GHz LNA and MPA. A power constrained optimization is applied to a test case amplifier i.e. broadband amplifier to get the optimized RF performance. The optimization is simulation-based technique. A 0.15 µm 85 GHz PHEMT is used in designing the LNA, MPA and broadband amplifier. This chapter also introduces the inventions of Voltage Controlled Oscillator (VCO), Mixer, Low Noise Amplifiers (LNA), Power Amplifiers (PA) and Transmit-Receive Switch (T/R). These circuits are crucial components for RF and Microwave front-end integrated circuits. The elements of inventions of circuits are clearly explained. The inventions reflect the requirement or the need of solving current problem using available technology. Chapter 11 RF and Microwave Test of MMICs from Qualification to Mass Production...................................... 333 Mohamed Mabrouk, ISETCOM de Tunis and CIRTA’COM/SUPCOM, Cité Technologique des Communications, Tunisia This chapter describes some basic characteristic responses that must be known for each Monolithic Microwave Integrated Circuits. The main parameters such Return Loss, Insertion Losses or Gain, Power at 1dB compression, InterModulation Products or Noise Figure are very important and have to be measured before using the device in final applications. Basic rules of Test and Measurement in RF and Microwaves, as well for characterization on benches as for high volume production using Automatic Test Equipments installed in test platforms, are summarized for helping today’s test engineers to develop their own test solutions. The device, that was characterized on bench and tested in production environment, is a monolithic, integrated low noise amplifier (LNA) and mixer usable in RF receiver Front End applications for Personal Communications functioning on frequency wideband between 0.1 and 2.0 GHz. Compilation of References................................................................................................................ 346 About the Contributors..................................................................................................................... 358 Index.................................................................................................................................................... 362

xi

Preface

One of the creative device innovations in recent decades is the mobile phone, which provides users with a simple anytime and anywhere communication tool. Originally designed for interpersonal communication, today mobile phones are capable of connecting their users to a wide variety of Internet-enabled services and applications, which can vary from a simplified web browser to a GPS-enabled navigation system. So far, current research has focused mostly on applications designed for 2G, 3G and 4G (i.e., for the communications sector). Now, with emerging new wireless devices, understanding the development techniques of the integrated circuit devices has become very important. The future impact of these integrated circuit devices include green technologies, healthcare and safety/security technologies. Monolithic Microwave Integrated Circuits (MMIC) are one of the integrated circuit devices which support the development of the mobile phone and corresponding infrastructure. They are also widely used in all high frequency wireless systems. In developing MMIC as a product, understanding the process, analysis techniques, design techniques, modeling, measurement methodology and awareness of current product invention are therefore essential. Example of MMIC devices are low noise amplifier, mixer, power amplifier, oscillator and T/R switch. The integration of these devices into a single monolithic (transceiver) is a norm for radio frequency range (up to GHz). The design of these MMIC devices depend on the process/device technology. State of the art silicon technology is normally employed for low frequency and therefore a transceiver design is doable. For higher frequency (multi GHz), compound technology is normally employed. In the future, there will be more integration of these devices using this technology. Electronic Design Automation (EDA) is available for digital integrated circuit design, but for MMIC design, it only confines around computer aided design (CAD). Hopefully, in the future will be more work on EDA as a tool for MMICs. Undoubtedly, three segments of knowledge are important in developing these MMICs devices. They are theory, design and practical approaches. This book is a collective effort of many researchers and practitioners from industry and academia. It offers a variety of perspectives on MMIC and RFIC and provides several experience reports with experiments and surveys. The book opens with the a section on theory, which consists of five chapters. Chapter 1, Multi-Standard Multi-Band Reconfigurable LNA by Mohd Tafir Mustaffa describes a new low noise amplifier (LNA) for a multi-standard mobile receiver based on reconfigurability concept. The LNA design is based on the inductively-degenerated common-source (IDCS) topology as it has been proven to be a good choice

xii

in designing multi-standard multi-band LNA. The design is using 0.18 µm CMOS technology. Chapter 2, LNA Inventions by Norlaili Mohd. Noh surveys five LNA topologies. They were studied, analyzed and compared in this chapter. The topologies are the Simultaneous Noise and Input Matching (SNIM), Power-Constrained Simultaneous Noise and Input Matching (PCSNIM), Current-Reuse (CR) and FoldedCascode (FC) LNAs. The last topology is the PCSNIM with buffer. Chapter 3, Multiband Multi-Standard LNA with CPW Transmission Line Inductor by M. Ben Amor, M. Loulou, S. Quintanel and D. Pasquet, presents a wide band LNA design for IEEE802.16 standard with the CMOS 0.35 µm technology. In this LNA, a CPW transmission line is used to design the inductive degeneration inductor of 0.38 nH. The circuit has a S21 of 12 dB, a noise figure less than 3 dB and an input/output reflection coefficient less than -10 dB between 2 and 6GHz. Chapter 4, Design of Low Noise Amplifiers through Flow-Graphs and their Optimization by the Simulated Annealing Technique by M. Fakhfakh, M. Boughariou, A. Sallem, and M. Loulou presents the optimal design of Low Noise Amplifiers (LNAs). The basic idea consists of optimizing performances of LNAs by a direct action on the scattering parameters. A symbolic approach, namely the Coates Flow-Graph technique, is used to automatically generate symbolic expressions of the impedance parameters and, thus, those of the scattering parameters. The Simulated Annealing optimization technique is applied to determine the optimal sizing of the LNA. Chapter 5, Optimization of CMOS Quadrature VCO Using a Graphical Method by Hassene Mnif, Dorra Mellouli and Mourad Loulou describes the design and the optimization of Quadrature Voltage Controlled Oscillators (QVCOs) based on the coupling of two LC-tank VCO. This work covers the phase noise analysis, a graphical optimization approach, already used to optimize LC oscillator phase noise, to optimize QVCO phase noise while satisfying design constraints such as power dissipation, tank amplitude, tuning range and start up condition. Designs are discussed in the second part of the book. Chapter 6, The Design and Modeling of 2.4 and 3.5 GHz MMIC PA by Chin Guek Ang discusses the design of MMIC power amplifiers for wireless application by using 0.15 μm GaAs Power Pseudomorphic High Electron Mobility Transistor (PHEMT) technology with a gate width of 100 μm and 10 fingers at 2.4 GHz and 3.5 GHz. The design methodology for power amplifier design can be broken down into three main sections: architecture design, small-signal design, and large-signal optimization. Chapter 7, The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA, by Ching Wen Yip describes the LNA that was designed using cascode topology with feedback techniques which produces better matching and unconditionally stable over the entire desired frequencies. Chapter 8, Design of Medium Power Amplifier Using GaAs PHEMT Technology for Wireless Applications by Amiza Rasmi presents the design of single-stage and two-stage medium power amplifiers (MPAs) using GaAs PHEMT technology for the wireless applications. The single-stage MPA was designed using 0.15 μm GaAs PHEMT technology to be operated at 3.5 GHz whereas the two-stage MPA was designed using 0.5 μm GaAs PHEMT technology to be operated at 5.8 GHz. The MPAs employ a simple RC feedback in order to linearize the stages as well as to improve the circuit stability and to control the gain. Chapter 9, The Design and Modeling of 30 GHz Microwave Front-End by Wan Yeen Ng and Xhiang Rhung Ng discusses a millimeter wave integrated circuit (MMWIC) in frequency of 30 GHz especially switch (SPDT), medium power amplifier (MPA) and low noise amplifier (LNA). The switch is developed using a commercial 0.15 µm GaAs pHEMT technology. It achieves low loss and high isolation for millimeter wave applications. The circuit and layout drawing of SPDT switch are done by using Advanced Design System (ADS) software.

xiii

Practical approaches are discussed in the last section of the book, which consists of two chapters. Chapter 10, Inventions of Monolithic Microwave Integrated Circuits by Arjuna Marzuki introduces the inventions of Voltage Controlled Oscillator (VCO), Mixer, Low Noise Amplifiers (LNA), Power Amplifiers (PA) and Transmit-Receive Switch (T/R). A first time right IC concept is also discussed in the chapter. Last chapter, RF and Microwave Test of MMICs: from Qualification to Mass Production by Mohamed MABROUK describes some basic characteristic responses that must be known for each Monolithic Microwave Integrated Circuits. The main parameters such Return Loss, Insertion Losses or Gain, Power at 1dB compression, InterModulation Products or Noise Figure are very important and have to be measured before using the device in final applications. With an in-depth coverage of a variety of advances in Monolithic Microwave Integrated Circuits for Wireless Systems, this book aims to to provide a central source of reference on MMIC development which covers knowledge in analysis, design, modeling, measurement and inventions. Today, there is a growing trend of multistandard and multiband, which will lead to an increased interest in publications covering different aspects of circuit techniques and methodology to make multimode SOC. This book will be of interest to researchers in industry and academia working in the areas of circuit design, integrated circuit, and RF and microwave, to graduate and undergraduate students, and anyone with an interest in monolithic wireless devices development. The editor would like to acknowledge the help of all involved in the collation and review process of the book, without whose support the project could not have been satisfactorily completed. Most of the authors are also served as referees for articles written by other authors. Thanks to all those who provided comprehensive reviews. Their comments, but constructive, about the chapters have been very useful and much appreciated. Special thanks also go to the publishing team at IGI Global. In particular to Julia Mosemann. Finally, I wish to thank all of the authors for their insights and excellent contributions to this book. Arjuna Marzuki Universiti Sains Malaysia, Malaysia Ahmad Ismat Bin Abdul Rahim Telekom Malaysia R&D Sdn. Bhd, Malaysia Mourad Loulou University of Sfax, Tunisia

Section 1

Theory

1

Chapter 1

Multi-Standard Multi-Band Reconfigurable LNA Mohd Tafir Mustaffa Universiti Sains Malaysia, Malaysia

ABSTRACT In this research, the aim is to design and implement a new low noise amplifier (LNA) for a multi-standard mobile receiver based on reconfigurability concept. The LNA design is based on the inductivelydegenerated common-source (IDCS) topology as it has been proven to be a good choice in designing multi-standard multi-band LNA. The design is using 0.18 µm CMOS technology. The reconfigurable LNA has been designed to operate in two bands of standards consisting the bands range from 800 to 1000-MHz (lower band) and 1800 to 2200-MHz (upper band). The simulation results exhibit gain S21 of 12.9-dB for lower band and 12.4-dB for upper band, input reflection S11 of -14.5-dB and -17.2-dB for both bands, and output return loss S22 of -14.7-dB and -26-dB for lower and upper band making the LNA suitable for most of the mobile communication applications. The LNA also exhibits the noise of figure of 2.55-dB and 2.3-dB for lower and upper band respectively. The circuit consumes 26.5 mW when operating in lower band mode and uses 18.8 mW of power when operating in upper band mode.

INTRODUCTION High demands for multi-standard multi-band devices (to cover standards available in almost anywhere in the world) with more functionality (i.e. video call, games, email etc.) for wireless mobile devices invites the radio frequency integrated circuit (RFIC) community to focus on the design of compact systems. Consequently, nowadays, mobile devices come with several standards to support multiple functions. Third-generation or popularly known as 3G systems generally support multiple mobile communication standards such as Global Standard for Mobile (GSM900), Digital Cellular System (DCS1800), Personal Communication System (PCS1900) and Universal Telecommunication System (UMTS) or Wide Code Division Multiple Access (WCDMA) (Universal Cellular Engineering (UCE), n.d.; 3rd DOI: 10.4018/978-1-60566-886-4.ch001

Copyright © 2012, IGI Global. Copying or distributing in print or electronic forms without written permission of IGI Global is prohibited.

Multi-Standard Multi-Band Reconfigurable LNA

Generation Partnership Project, 2008a; European Telecommunications Standards Institute (ETSI), 1999; 3rd Generation Partnership Project, 1999; 3rd Generation Partnership Project, 2008b). With respect to these standards, current multi-standard multi-band mobile devices support parallel architecture of the RF receiver system on a single-chip. Specifically, industries use parallel components such as RF filters and LNAs at the front-end receiver of mobile devices to support those standards (Qualcomm CDMA Technologies, n.d.; Texas Instruments RF Technologies, n.d.). Unfortunately, this implementation is very area inefficient, costly and consumes relatively high power. Thus, a better solution is needed to produce a compact mobile device to meet the need for a multi-standard multi-band system with more functions that could result in the reduction of the cost and complexity of the system as well as power consumption. Referring to work presented in Brandolini, Rossi, Manstretta, & Svelto (2005), it proposed a single multi-standard LNA in combination with several RF filters at the front-end circuit to meet the need for multiple standards devices. In another proposal (Veljanovski, Stojcevski, Singh, Faulkner, & Zayegh, 2003; Boeck, Pienkowski, Circa, Otte, Heyne, Rykaczewski, Wittmann, & Kakerow, 2003), reconfigurable architecture is used, using the concept of hardware sharing with also multiple RF filters at the very front-end of the RF receiver. The proposed architectures reduce the complexity, power consumption and components used in current solutions. In conclusion, multi-standard radio architecture involves a lot of design issues such as the following (Brandolini, Rossi, Manstretta, & Svelto, 2005; Mustaffa, Zayegh, Veljanovski, & Stojcevski, 2006): • •

A multi-standard receiver must have minimum component count and area and to continue miniaturization. All the considered standards do not need to be covered at the same time, i.e., when specific band or standard is active, the others can be switched off or in idle mode, in order to save power and reuse hardware resources.

To highlight more details on the concepts of mobile communication system and issues regarding it as mentioned above as well as the design and implementation of the multi-standard reconfigurable LNA, this chapter is divided into several sections which are Multi-standard RF Systems, Reconfigurable Multi-standard Mobile Terminals, Design and Implementation of Reconfigurable Multi-Standard Multi-Band LNA and Conclusion.

MULTI-STANDARD RF SYSTEMS Multi-standard RF systems consist of several standards such as GSM and 3G standards. In this section, some details on the RF standards in terms of frequency allocation, modulation techniques used, etc are provided. Then, followed by the presentation of RF receiver architectures used to support those standards. Finally, this section will end up with the discussion of the recent and past developments of the multi-standard RF mobile systems.

RF Standards In this section, the requirements of the GSM and 3G standards are systematically mapped onto set of measurable specifications for receiver architecture.

2

Multi-Standard Multi-Band Reconfigurable LNA

RF Standards to Receiver Specifications RF standards can be categorised in two groups: GSM and 3G/WCDMA/UMTS. GSM consists of several standards such as GSM850 and GSM900 with carrier frequencies of 850 MHz and 900 MHz. Other standards which fall in this group are the DCS1800 and PCS1900 with carrier frequencies of 1800 MHz and 1900 MHz (3rd Generation Partnership Project, 2008a). While WCDMA/UMTS standards consist of bands with carrier frequencies of 850 MHz to 2100 MHz, also known as UMTS band I to VI (European Telecommunications Standards Institute (ETSI), 1999; 3rd Generation Partnership Project, 2008b). The original version of the GSM standards was developed by European Telecommunication Standards Institute (ETSI) and evolved through out the time. Table 1 shows the frequency allocation for the GSM systems. Specifically, GSM850, GSM900 and DCS1800 are used in Europe, while PCS1900 is deployed in the United State (U.S.). While, Table 2 gives the summary of the band allocation for 3G. In terms of the characteristics of the GSM and 3G systems such as modulation scheme, channel bandwidth, etc., the most relevant parameters that refers to both standards are summarized in Table 3. 3rd Generation Partnership Project (2008a) clearly shows that the receiver requirements for all the GSM standards are very similar. Though they are very similar, GSM900 is considered to be the strictest version in terms of receiver specifications. Hence, for the sake of clarity, our analysis will be based on this standard. Similarly, for 3G, all the standards are very similar but 3G standard (Band I) is the common standard and is believed to be the first draft (3rd Generation Partnership Project, 1999). For that, 3G standard (Band I) will be referred for the discussion in this chapter. To understand the behavior of GSM and 3G systems, the key characteristics of these systems such as sensitivity, selectivity and linearity are needed to be understood. Sensitivity, selectivity and linearity are Table 1. Frequency allocation for GSM systems (Universal Cellular Engineering (UCE), n.d.; 3rd Generation Partnership Project, 2008a) Operating Band

Uplink Frequencies; Mobile transmits, base receives.

Downlink Frequencies; Base transmits, mobile receives.

GSM850

824 MHz to 849 MHz

869 MHz to 894 MHz

GSM900

890 MHz to 915 MHz

935 MHz to 960 MHz

DCS1800

1710 MHz to 1785 MHz

1805 MHz to 1880 MHz

PCS1900

1850 MHz to 1910 MHz

1930 MHz to 1990 MHz

Table 2. Frequency allocation for UMTS systems (3rd Generation Partnership Project, 2008b) Operating Band

Uplink Frequencies; Mobile transmits, base receives.

Downlink Frequencies; Base transmits, mobile receives.

I

1920 - 1980 MHz

2110 -2170 MHz

II

1850 -1910 MHz

1930 -1990 MHz

III

1710-1785 MHz

1805-1880 MHz

IV

1710-1755 MHz

2110-2155 MHz

V

824 - 849 MHz

869-894 MHz

VI

830-840 MHz

875-885 MHz

3

Multi-Standard Multi-Band Reconfigurable LNA

Table 3. Signal characteristics for GSM/3G systems Parameters

GSM

3G

Modulation Technique

GMSK

QPSK

Channel Bandwidth

200-kHz

3.84-MHz

Channel Separation

200-kHz

5-MHz

Data Rate

270.8-kbs

3.84-Mbs

modeled in terms of the system performance parameters, including noise figure (NF), carrier to noise ratio (CNR) and TOI or also known as third-order intercept point (IP3). The required system characteristics are directly governed by the standards to be supported by the system. Every wireless communication standard has clearly defined characteristics for radio transmission and reception (Universal Cellular Engineering (UCE), n.d.; 3rd Generation Partnership Project, 2008a; European Telecommunications Standards Institute (ETSI), 1999; 3rd Generation Partnership Project, 1999; 3rd Generation Partnership Project, 2008b). Critical transmission and reception limits are defined by the standard along with the modulation, demodulation schemes and other parameters. In this chapter, only NF, gain and TOI are discussed as these are the most important parameters that will be required for LNA characterization or derivation from the receiver specifications which will be covered later in the following section. Sensitivity, as one of the key specification of receiver design, is defined as the ability of the receiver to detect minimum signal in the presence of the noise and interferers at an acceptable bit error rate (BER). The system NF of the receiver for the GSM standard is normally used as the measure of the sensitivity. For GSM900, a sensitivity level of -102 dBm is required with system NF of 10 dB. Meanwhile, the system NF for WCDMA is 9 dB and a sensitivity level of -117 dBm is required. On the other hand, the system transfer function must be linear over the wide dynamic range of the input signal in the presence of the blocking interferers. Linearity of the system is modeled by IP3. Input IP3 (IIP3) for GSM systems is about -19.0 dBm. For 3G, IIP3 required is a bit lower with the value of -19.1 dBm. Another major specification to be considered in the receiver system is gain. The required system gain for GSM and 3G standards is generally more than 60 dB. This required gain is distributed amongst all the RF front-end components. The maximum gain achievable by any component is limited by the circuitry. Table 4 gives the summary of the specifications for GSM and 3G systems. The complete set of RF specifications set by the 3rd Generation Partnership Project (3GPP) can be found in (3rd Generation Partnership Project, 2008a; European Telecommunications Standards Institute (ETSI), 1999; 3rd Generation Partnership Project, 1999; 3rd Generation Partnership Project, 2008b). In addition, more explanations about the RF specifications are described in Li & Ismail (2002).

From Receiver Specifications to LNA Specifications Having reviewed the requirements for RF receiver specifications, the specifications have to be translated into specifications for receiver’s components, in particular LNA. According to the previous work in (Mustaffa, Zayegh, Veljanovski, & Stojcevski, 2006), Table 5 gives the summary of the requirements for the LNA derived from the system simulation which has been carried in advanced design system

4

Multi-Standard Multi-Band Reconfigurable LNA

Table 4. Receiver specifications for GSM/3G systems and the proposed specifications for multi-standard system (Mustaffa, Zayegh, Veljanovski, & Stojcevski, 2006; Li & Ismail, 2002) Specification

GSM

3G

Multi-standard

Sensitivity (dBm)

-102

-117

-117

CNR (dB)

10

9

9

System IIP3 (dBm)

-19

-19.1

-19

System NF (dB)

10

9

9

Gain (dB)

> 60

> 60

> 60

(ADS) from Agilent. Also, in Table 6 the collection of extracted specifications of LNA from literature as comparison to the ideal LNA specifications are presented. Tables 5 and 6 show that the specifications for LNA are not fixed but is flexible, depends on the requirements of the receiver’s specifications. For example, if the specifications for the LNA are set to be stringent, this means that the specifications for the following blocks of the receiver’s component can be relax or vice versa. In addition, for IIP3, the achieved specification values were ranging from -2.5 to -4.0 dBm as in Pieńkowski (2004) and Moreira, Kerherve, Jarry, & Belot (2006) down to -7.2 to -14.0 dBm (Dao, Bui, & Park, 2007; Kawazoe, Sugawara, Ito, Okada, & Masu, 2005). This is probably due to the different optimization were took place and it is always hard to trade-off between various specifications (i.e. NF, gain etc.) Same goes for the NF, where in Pieńkowski (2004), it achieved the best NF performance compared to others.

RF Receiver Architectures A system is needed to support mobile communication standards. Part of that system is called RF receiver section. There are several RF architectures which are being used for decades and becoming popular

Table 5. Ideal LNA specifications proposed for multi-standard multi-band system Specification

Optimum range

Optimum point

Gain (dB)

10 to 20

20

NF (dB)

1 to 6

1

IIP3 (dBm)

-5 to 5

5

Table 6. Typical LNA specifications proposed for multi-standard multi-band system Gain max. (dB)

NF (dB)

IIP3 (dBm)

Pieńkowski (2004)

12

0.76

-2.5

Moreira, Kerherve, Jarry, & Belot (2006)

≤14.2

≤2

≤ -4

Dao, Bui, & Park (2007)

≤ 14

≤ 2.9

-14

Kawazoe, Sugawara, Ito, Okada, & Masu (2005)

14.2

5.2

-7.2

5

Multi-Standard Multi-Band Reconfigurable LNA

overtime. These are super heterodyne architecture and homodyne architecture or known as direct conversion receiver (DCR). The adaptability to different receiver requirements is a major advantage of the heterodyne receiver. It provides superior performance in terms of selectivity and sensitivity; however, the need for a large number of external components and the complexity of the structure, make it virtually an impossible choice for high level of integration if needed. The major drawback of this architecture is the external components used which are expensive and bulky. Also, important disadvantage of the heterodyne receiver architecture is its missing adaptability to different wireless standards and modes. Moreover, since external intermediate frequency (IF) filters are optimized for a certain mode of operation (i.e. GSM900 or DCS1800), which results in a fixed bandwidth and center frequency, it cannot be re-used for a different mobile communication standard (Kawazoe, Sugawara, Ito, Okada, & Masu, 2005). Compared to heterodyne, DCR architecture is considered as the most suitable architecture for singlechip multi-standard multi-band mobile device, because no intermediate stage required, less off-chip components used, leading to low power consumption with possible integration as a single-chip radio (Kim, Son, Parkhomenko, Hwang, Cho, Nah, & Park, 2005; Guillou, Gaborieau, Gamand, Isberg, Jakobsson, Jonsson, Déaut, Marie, Mattisson, Monge, Olsson, Prouet, & Tired, 2005; Song, Koo, Jung, Lee, Chu, & Chae, 2005). Therefore, since the demand for multi-standard mobile device increases, RF engineers have started to design systems using parallel architecture based on DCR architecture as it is easier to implement. The external review has been received on recent systems including many LNAs that increase the cost, complexity, and power consumption of the system. This is substantiated in the following reference papers: (Boeck, Pienkowski, Circa, Otte, Heyne, Rykaczewski, Wittmann, & Kakerow, 2003; Mustaffa, Zayegh, Veljanovski, & Stojcevski, 2006; Kim, Son, Parkhomenko, Hwang, Cho, Nah, & Park, 2005; Guillou, Gaborieau, Gamand, Isberg, Jakobsson, Jonsson, Déaut, Marie, Mattisson, Monge, Olsson, Prouet, & Tired, 2005; Song, Koo, Jung, Lee, Chu, & Chae, 2005). These papers show the examples of the current research and development, even the marketed products of RF receiver system based on parallel architecture. For instance, Figure 1 shows how several standards such as GSM, Enhanced-GSM (EGSM), DCS and PCS of GSM group can be integrated into one system using parallel structure. In another example, similar approach has been developed as shown in Figure 2. It is even more interesting because it give more functionality to the mobile device, where the system currently employs UMTS or 3G standard with multiple bands and other wireless standard i.e. Global Positioning System (GPS) (Qualcomm CDMA Technologies, n.d.). This system is currently available in the market, supplied by the well-known company (QUALCOMM) which provides chipset solutions to all mobile manufacturers. Based on the reviewed RF receiver architectures, it can be concluded that, most of these architectures are limited in terms of standards of mobile communications covered in the design. Also, the implemented RF receiver’s architectures are used to cover either single standard or few standards in parallel form. For that reason, these architectures can be modified by making it reconfigurable to provide multistandard multi-band capability. For instance, if only GSM system is available at certain place, the architecture should adjust itself to respond to the system. Thus, it is essential to find a better solution in order to produce a mobile device with a compact architecture based on reconfigurable concept which meets the need for multi-standard multi-band system. This, in return could reduce the cost of the system and also provide a system with longer battery life at a very affordable price.

6

Multi-Standard Multi-Band Reconfigurable LNA

Figure 1. Parallel DCR architecture for multi-standard mobile as in Song, Koo, Jung, Lee, Chu, & Chae (2005)

RECONFIGURABLE MULTI-STANDARD MOBILE TERMINALS In this research, the term reconfigurable architecture means that the system hardware can adjust itself to serve multi-standard multi-band mobile terminals. Therefore, reconfigurable terminals represents the system that uses multiple ways to reconfigure the available architectures either at system level or at component level, with the objective to provide better performance that is more efficient in cost, area and power consumption. The following sub-section will highlight the development of reconfigurable receiver’s architectures and followed by reconfigurable LNAs for multi-standard mobile terminals.

Recent Developments of Reconfigurable Multi-Standard System In the previous section on RF receiver architectures, the concept of multi-standard multi-band systems which cover most of the cellular standards and other wireless standards has been discussed. But the concept of parallel system is no longer suitable to support the current trend for high data rates and global mobility. Thus, RF engineers and researchers around the world have come up with an idea of designing a mobile device that could support as many as possible the cellular and wireless standards in one terminal using the concept of reconfigurability. Based on reconfigurability concepts, several systems appears in the literature to support multi-standard terminals that consists of several combinations of cellular and wireless standards such as GSM, UMTS, Bluetooth, GPS, wireless local area network (WLAN), etc. For instance, in Figure 3, the reconfigurable architecture combines the advantages of both heterodyne and homodyne architecture that support two standards: UMTS and WLAN. In this architecture, the use of heterodyne provides good rejection between RF and local oscillator (LO) port and good selectivity. On the other hand, the use of homodyne or

7

Multi-Standard Multi-Band Reconfigurable LNA

Figure 2. QUALCOMM chip solution (Qualcomm CDMA Technologies, n.d.)

DCR for UMTS system reduces the problem with I/Q imbalance (Pieńkowski, 2004; Kakerow, Mueller, Pieńkowski, Circa, & Boeck, 2005). In addition, to demonstrate the concept of reconfigurability being adopted successfully, Figure 4 shows another proposal and implementation of reconfigurable receiver architecture and a reconfigurable RF design technique using a switchable passive network. The architecture is targeted to cover WCDMA,

8

Multi-Standard Multi-Band Reconfigurable LNA

Figure 3. Reconfigurable receiver architecture as in Pieńkowski (2004)

802.11a/b/g WLAN, and WiBro (Wireless Broadband) with a single receiver chain (Kim, Jang, & Yoo, 2007). At this point, it has been shown that the available reconfigurable architectures just cover some standards in one implementation, i.e. as in Pieńkowski (2004) and Kakerow, Mueller, Pieńkowski, Circa, & Boeck (2005). These designs just cover the GSM1800 and WCDMA standards for personal mobile communications and WLAN for wireless communication only. Then in Kim, Jang, & Yoo (2007), it only adds WiBro on top of what have been implemented in Pieńkowski (2004) and Kakerow, Mueller, Pieńkowski, Circa, & Boeck (2005). The dream then is to design a single system (as introduced by QUALCOMM) which covers almost all of the personal wireless communication standards (GSM and UMTS) and other wireless standards such as GPS and Bluetooth. Also, this new system based on reconfigurable architecture should needs less components (e.g. less inductor), cheaper and less power consumption. The simplest idea is to use one reconfigurable LNA that could be reconfigured to serve multiple standards for GSM and UMTS (i.e. GSM850, GSM900, DCS1800, PCS1900, and UMTS – Band I to VI). This approach will reduce number of required components, leading to a system with less complexity, less area and more importantly less power consumption. Figure 4. 2-6 GHz multi-standard receiver architecture (Kim, Jang, & Yoo, 2007)

9

Multi-Standard Multi-Band Reconfigurable LNA

In addition, with all the presented examples and proposed concepts of reconfigurability, so far, there’s no single method to be followed by the RF designers to design such reconfigurable terminal for multi-standard system. There are two possible initiatives in the process of developing the reconfigurable terminals for multi-standard systems which are (Kakerow, Mueller, Pieńkowski, Circa, & Boeck, 2005): • •

Necessity: Dictated by the differences in standards and frequency bands in different geographical regions. Economically: e.g. development of GSM/UMTS multi-standard terminals that takes advantage of superior data rates of UMTS and full coverage of GSM.

In this work, these two directions are followed in designing a personal wireless communication unit. Hence, Figure 5 shows a proposed multi-standard terminal that uses DCR as the architecture of choice. It employs only one terminal of a reconfigurable LNA (in conjunction with other components that are also made multi-band components i.e. multi-band RF filters, multi-band mixers, etc.), to accommodate multiple bands and standards. This results in a great reduction in the system complexity, and significantly reduces the system power consumption and cost.

Recent Developments of Reconfigurable Multi-Standard LNA Recall from the previous section on RF receiver architectures, it tells that the concept of parallel system is no longer suitable to support the current trend for high data rates and global mobility. For that reason, researchers have come up with an idea of designing a mobile device system using the concept of reconfigurability. Despite all the limitations of such technology (i.e. CMOS), different standard requirement, etc., based on this concept, a few systems appear in the literature with different levels, including as many available standards as possible to support the demand for functionality and global mobility. At components level, for instance, the design of LNA had several approaches and implementations to meet the requirement of multi-standard multi-band system. Therefore, reviewing some of reconfigurable LNA at this time is important. Figure 6 shows a new topology of multiband reconfigurable LNA based on positive feedback for a system that cover DCS/UMTS/802.11b-g standards (Liscidini, Brandolini, Sanzogni, & Castello, 2006). The feedback loop (reflection from the load to the input) allows three difFigure 5. Proposed receiver architecture

10

Multi-Standard Multi-Band Reconfigurable LNA

Figure 6. Multiband LNA architecture (Liscidini, Brandolini, Sanzogni, & Castello, 2006)

ferent bands selection of 1.8, 2.1 and 2.4 GHz. Moreover, the use of shunt positive feedback configuration provides enhanced current gain compared with other feedback topologies, thereby improving the overall receiver noise figure. On top of that it uses variable gain and tunable load to meet the different requirement for DCS/UMTS/802.11b-g standards. Another example, Figure 7 shows an implementation of LNA based on Bipolar CMOS (BiCMOS) Silicon Germanium (SiGe) technology (Moreira, Kerherve, Jarry, & Belot, 2006). The LNA uses cascode topology with inductive emitter-degeneration which offers better trade-off between gain, noise figure, power consumption and linearity. The most area consuming elements, the on-chip inductances are shared between the two involved standards, DCS1800 and WCDMA. The selection of the operating standard Figure 7. Dual-standard LNA (Moreira, Kerherve, Jarry, & Belot, 2006)

11

Multi-Standard Multi-Band Reconfigurable LNA

is performed through a bias scheme that selects the appropriate current reference, bias circuitry and load resonant frequency. It also uses variable gain (low-gain and high-gain) that can also be selected through the switch implementation which adds a low resistance in parallel with LNA load. Therefore, it is clear that, there are multiple ways to implement a reconfigurable LNA for multistandard receiver architecture. However, all the above mentioned examples are limited to a few combinations of the personal mobile communication standards (i.e. DCS1800 and WCDMA standards) and other wireless communications standards (i.e. WLAN) as in Pieńkowski (2004) and Kakerow, Mueller, Pieńkowski, Circa, & Boeck (2005). Meanwhile, in the rest of the literature (Tzeng, Jahanian, & Heydari, 2008 Vahidfar & Shoaei, 2006), the LNAs are either developed for standards other than mobile communication standards (e.g., Tzeng, Jahanian, & Heydari, 2008) or only a combination of two personal mobile communication standards and wireless standards (Vahidfar & Shoaei, 2006). For this reason, a new multi-standard multi-band reconfigurable LNA is needed that could cover more standards but in compact mode.

DESIGN AND IMPLEMENTATION OF RECONFIGURABLE MULTI-STANDARD MULTI-BAND LNA Design Consideration In order to design multi-standard multi-band LNA with a good performance, a good topology for such device is needed to support the required specifications. Hence, IDCS topology has been chosen as it proved to be a good choice in designing multi-standard multi-band LNA (Dao, Bui, & Park, 2007). To design such LNA, design considerations should be taken as follow: •

•

•

12

Reconfigurability: The concept of reconfiguration here means, finding a way to realize the multistandard multi-band in two modes of operation without degrading the LNA performance with respect to a single multi-standard LNA. Those two modes of operation are: Mode 1 which is operating in lower band (800 to 1000 MHz) and Mode 2 which is operating in upper band (1800 to 2200 MHz). LNA parameters: In this matter, as only one active circuit (i.e. one cascode LNA) will be used at a time, hence there will be a trade-off between power consumption and design parameters (refers to Figure 8), such as W / L of the transistor M 1 , LG , LS , LD , L1 , R1 , Cex1 , Cex2 , CD1 and CD2 . This means that, it will be even harder to find the best values of passive components especially inductors which should compromise between two bands of standards (lower and upper frequency bands) as the design will use the same fixed inductors provided by the foundry. Full integration: As the LNA is targeted to be fully integrated; the trade-off between minimum NF and full integration is to be considered. To achieve full integration of the LNA, component sharing is implemented by introducing active switches in the circuit. The introduction of these active components will theoretically introduce an extra noise to the circuit. Therefore, the design of those switches also need to be carefully done to reduce the noise as much as possible.

Multi-Standard Multi-Band Reconfigurable LNA

A Reconfigurable Multi-Standard Multi-Band LNA The design of the reconfigurable LNA is based on the previous works in Mustaffa, Zayegh, Veljanovski, Stojcevski, & Zulkifli (2008a) and Mustaffa, Zayegh, Veljanovski, Stojcevski, & Zulkifli (2008b) respectively. The LNAs were designed using wide band approach to cater the frequency of 800 to 1000 MHz and 1800 to 2200 MHz respectively. One of the important properties of the wide band LNAs is the use of the external gate-source capacitance ( Cex ). This property is used to obtain the input matching by providing the extra degree of freedom at the input circuit. The fact that this Cex can be exploited to design a reconfigurable LNA for two bands of interest will therefore be discussed here. The LNA is designed to operate in upper band as a default mode because in this mode, it uses lower inductance (theoretically will give lower series resistance) at the input. The idea is to use the same coils ( LG and LS ), the same transistors M 1 and M 2 and by altering the value of the external gate-source capacitance allows the LNA to operate in lower band mode. In this way, a simple reconfigurable LNA is obtained. The coils’ sharing has an advantage because chip area is reduced and the need for another coil is avoided. Figure 8 shows the circuit considered as a single mode LNA, where Cex1 and Cex2 are the external gate-source capacitances at the input which represents the capacitances required for the upper band and lower band modes respectively. CD1 and CD2 are the load capacitances at the output which represent capacitances for upper band and lower band modes respectively. LG , LS , LD , L1 and R1 are the input and load inductors and load resistor which represents the shared components for upper and lower band modes. Transistors SW0 , SW1 , and SW2 are the switches which will be used to switch on and off to change the external gate-source capacitance at the input of the LNA as well as the load at the output of the LNA respectively. These switches determine the mode of the LNA function, either in upper band or lower band mode. Figure 9 shows the corresponding small-signal model for the reconfigurable LNA. In this model, new parameter is introduced for the calculation of NF. This parameter is RSW which represents the reFigure 8. Circuit diagram of a reconfigurable multi-standard multi-band LNA

13

Multi-Standard Multi-Band Reconfigurable LNA

sistance of the transistor SW0 . This condition applies when the LNA is operating at lower band mode only. Therefore equations (1.1) and (1.2) are used to define the noise factor (F) and NF respectively. For upper band mode, expressions (1.3) and (1.4) are used for the calculation of NF (Lee, 2004). F =1+

R sw RS

+

Rl RS

+

Rg RS

+

γ χ  ωo    α QL  ωT 

 R R R γ χ  ωo    NF =10 log[F]=10 log 1+ sw + l + g + RS R S R S α QL  ωT      R R γ χ  ωo    F =1+ l + g + R S R S α QL  ωT   R R γ χ  ωo    NF =10 log[F]=10 log 1+ l + g +  R S R S α QL  ωT 

(1.1) (1.2)

(1.3) (1.4)

In term of input impedance matching, Figure 9 shows the introduction of Cex . This parameter represents the total external gate-source capacitance which sets the input impedance matching of the LNA. The values of capacitors Cex1 and Cex2 have to be determined in such away that the matching conditions for upper band and lower band are satisfied. Depending on the condition of SW0 whether in ON of OFF mode, the LNA will operate either at upper band frequency or lower band frequency. Therefore, the following expressions are used for the impedance matching at the input of the LNA. At upper band mode ( SW0 =OFF), Cex

=

Cex1

=

C gsex, upper

Figure 9. Revised IDCS small-signal model for reconfigurable LNA

14

(1.5)

Multi-Standard Multi-Band Reconfigurable LNA

and Zin,upper ≈ s (LG +LS ) + RS

g m1LS 1 + Cgg1 + C gsex, upper s Cgg1 + C gs per ex, upp

(

)

g m1LS =50 Ω Cgg1 + C gsex, upper

=

(1.6) (1.7)

At lower band mode ( SW0 =ON), Cex

=

Cex1

+

Cex2

=

C gsex, lower

(1.8)

and Zin,lower ≈ s (LG +LS ) + RS

=

g m1LS 1 + Cgg1 + Cgsex, lower s Cgg1 + Cgs ex, low wer

g m1LS =50 Ω Cgg1 + C gsex, lower

(

)

(1.9) (1.10)

where C gsex, upper is the external gate-source capacitance when the LNA operate in upper band mode and C gsex, lower is the external gate-source capacitance when the LNA operate in lower band mode. Here, g m1 , Cgg1 = Cgs1 +Cgd1 +Cgb1 , LG and LS are the transconductance, total gate capacitance, and gate and sourcedegenerative inductors, respectively. The total gate capacitance is the summation of gate-source, gatedrain and gate-bulk capacitances, respectively. In term of output impedance matching, SW1 , and SW2 play an important roles in determining the load at the output. The on and off of these switches will set the output impedance matching of the LNA either to operate at upper band or lower band mode. The LNA is operating as follows: •

•

To set the output impedance of the LNA at upper band mode, SW1 has to be in ON mode and SW2 in OFF mode. In this condition, the total resistance (resistor between the drain and source of SW1 and R1 ) is representing the resistor which is in series with L1 . Together with CD1 , and LD , it will set the output impedance matching for upper band mode. This technique is actually a new approach which has been introduced in Mustaffa, Zayegh, Veljanovski, Stojcevski, & Zulkifli (2008a and 2008b) to avoid the use of buffer circuit for the output matching. On the other hand, the output impedance of LNA operating at lower band mode is obtained when SW2 in ON mode and SW1 in OFF mode. In this condition, only R1 is representing the resistance which is in series with L1 . Together with total load capacitance ( CD1 + CD2 ), and LD , it will set the output impedance matching for lower band mode.

15

Multi-Standard Multi-Band Reconfigurable LNA

Therefore, to determine the impedance matching at the output of the LNA, based on Mustaffa, Zayegh, Veljanovski, Stojcevski, & Zulkifli (2008a and 2008b), the following new expressions for upper band and lower band modes are obtained. For upper band, YL,upper = sCD1 + ∴ Z L,upper =

1 YL,upper =

1 1 + r+sL D R sw1  R1 +sL1  1    (r+sL D )  (R upper +sL1 ) =   sCD1 

Rupper r + s (Rupper L D + L1r ) + s 2L1L D

(1.11)

(1.12)

1 + sCD1 (r + Rupper ) + s 2CD1 (L1 +LD )

For lower band, YL,lower =s (CD1 + CD2 ) + ∴ Z L,lower =

1 YL,lower =

1 1 + r+sL D (R1 ) +sL1

 1     (r+sL )  (R =  +sL1 ) D lower  sCD,lower  Rlower r + s (Rlower LD + L1r ) + s 2 L1L D

1 + sCD,lower (r + Rlower ) + s 2CD,lower (L1 +LD )

(1.13)

(1.14)

where R upper =R sw1  R1 , R lower =R1 and CD,lower =CD1 +CD2 . Then, to determine the gain of the LNA at upper and lower band, gain expression in Mustaffa, Zayegh, Veljanovski, Stojcevski, & Zulkifli (2008a) is revised and the following expressions are obtained: Gain of the upper band, v S21 =2 vout ≡ Gm21 (s).ZL,upper (s) in

(1.15)

Gain of the lower band, v S21 =2 vout ≡ Gm21 (s).ZL,lower (s) in

(1.16)

Circuit Implementation of Reconfigurable Multi-Standard Multi-Band LNA The reconfigurable multi-standard multi-band LNA which will be operating in two modes of operation: lower band at 900 MHz and upper band at 2 GHz, has been designed and implemented using 0.18 μm CMOS technology and simulated in Spectre RF. The components values are obtained based on the following design steps and design equations as in (1.17) to (1.21). The design steps are as follows:

16

Multi-Standard Multi-Band Reconfigurable LNA

•

Choose a correct starting value of overdrive voltages ( Vgs − Vt ) to satisfy the requirement for good linearity (Soorapanth & Lee, 1997; Colomines, Arnaud, Parra, Graffeuil, & Plana, 2000). Find the aspect ratio W / L , and the transconductance ( g m ) of transistor M1 based on a given power budget that should satisfy the operation of two bands of interest (upper band and lower band) (Lee, 2004). Find the best value of LS that could satisfy the simultaneous noise and input matching. Together with this, the additional capacitance Cex that gives extra degree of freedom for noise and input matching for both bands should be chosen correctly. This value should compromise between the available power gain and the size of LS . One more consideration is the fact that large value of Cex leads to gain reduction (Nguyen, Kim, Ihm, Yang, & Lee, 2004). Find the best value of LG that could satisfy the simultaneous noise and input matching for both bands of interest. This step is very hard as the inductors provided by the foundry are fixed to specific values.

•

•

•

Then together with the design steps, the following equations are used to determine the components values for the reconfigurable LNA (Lee, 2004; Nguyen, Kim, Ihm, Yang, & Lee, 2004; Soorapanth & Lee, 1997; Colomines, Arnaud, Parra, Graffeuil, & Plana, 2000).   1 8 1 2 Vod 1+ αVod  (1+αVod )    2 3α ∴ IIP3 ≈ Vod IIV3=

Wopt =1.5(ωo LCox R sQin,opt,P )-1 1 ≈ 3ωLCox R S ωo2 =

1 Cgs (LG +LS )

ωT

gm Cgs

≈

=

Cgs,t =Cgs,int

D

(1.17)

(1.18)

(1.19)

gm 2 WLCox 3 +

Cex

(1.20) (1.21)

where Cgs,t and Cgs,int are the total gate-source capacitance of the LNA and intrinsic gate-source capacitance of M1 . First, (1.17) to (1.21) are used to determine the LNA’s components values for the upper band which operates at 2 GHz. For example, the width of the transistor and the Cex of the LNA to operate at 2 GHz were obtained to be 350 μm and 60 fF. Accordingly, the components values for lower band which operates at 900 MHz were obtained as shown in Table 7. From (1.19) and (1.20), the transconductance ( g m ) of lower band and upper band have been calculated and the calculations show that g m,lower > g m,upper . Also, total gate-source capacitance ( Cgs,t ) of

17

Multi-Standard Multi-Band Reconfigurable LNA

Table 7. Component values for reconfigurable multi-standard multi-band LNA Case Frequency

Condition Upper band (2 GHz)

Lower band (0.9 GHz)

M1 = M2 (W/L)

(350/0.18) mm

SW0 = SW2 (W/L)

(60/0.18) mm

SW1 (W/L)

(25/0.36) mm

L1 / LD / LG / LS

4.21 /15.8 /12.9/0.55 nH

CD,upper

/

(CD,lower = CD1 +CD2 )

Cex,upper

/

(Cex,lower = Cex1 +Cex2 )

RT = ( Rsw1 *  R1 ) / R1

100

fF

60 fF 62 || 79

Ω

(100 + 915)

fF

(0.06 + 2.63)

pF

79

Ω

Rsw1* is obtained from simulation.

lower band is higher than Cgs,t of upper band. This applies on Cex where Cex,lower > Cex,upper . Therefore, the tail current of the LNA operating at lower band frequency has to be higher than the tail current of the LNA operating at upper band frequency. For that reason, in each mode of operation, two values of tail current have been used. Those values are: 8.75 mA and 10.45 mA for upper band, and 12.43 mA and 14.7 mA for lower band respectively. The higher value used for lower band is to compensate for the gain reduction due to higher value of Cex used at the input. In relation to this matter, as shown in Nguyen, Kim, Ihm, Yang, & Lee (2004), for Cex =1.5 Cgs , the maximum available gain of the LNA is degraded by 1 dB. Table 7 presents the corresponding components values used for reconfigurable multi-standard multiband LNA. Figure 10 shows a complete circuit implementation of the reconfigurable LNA where bond pads capacitance at the input and output are included.

Discussion of the Results Table 8 shows the comparable performance summary of the reconfigurable LNA versus the wide band LNAs from Mustaffa, Zayegh, Veljanovski, Stojcevski, & Zulkifli (2008a and 2008b). For power gain, it shows that the reconfigurable LNA achieved a gain of almost similar to LNA in Mustaffa, Zayegh, Veljanovski, Stojcevski, & Zulkifli (2008b) for the 2 GHz operation. Meanwhile, for 900 MHz, the reconfigurable LNA achieved a 1.6 dB higher than that of LNA in Mustaffa, Zayegh, Veljanovski, Stojcevski, & Zulkifli (2008a). But, to achieve such a comparable gain for reconfigurable LNA at both modes of operation, power consumption will be higher compare to the wide band LNAs. This is due to different size of gate inductor ( LG ) used for input matching which translates to a higher transconductance ( g m ) of the transistor M1 . Moreover, to operate at lower band mode, the use of a

18

Multi-Standard Multi-Band Reconfigurable LNA

Figure 10. Complete circuit implementation of a reconfigurable LNA

Table 8. Performance summary of the reconfigurable LNA versus wide band LNAs Wide band LNAs

Reconfigurable LNA

Mustaffa, Zayegh, Veljanovski, Stojcevski, & Zulkifli (2008a) (900 MHz)

Mustaffa, Zayegh, Veljanovski, Stojcevski, & Zulkifli (2008b) (2 GHz)

Lower band (900 MHz)

Upper band (2 GHz)

S21 (dB)

11.3

12.6

12.9

12.4

S12 (dB)

- 62

- 53

- 61

-52

S11 (dB)

- 47.7

- 24.4

- 14.5

- 17.2

S22 (dB)

- 23.9

- 11.21

-14.7

- 26

NF (dB)

2.2

1.91

2.55

2.3

IIP3 (dBm)

+ 8.28

+ 8.4

+ 9.6

+ 7.7

P1dB (dBm)

- 2.06

- 2.02

- 2.5

- 0.5

Power (mW)

12.8

12.2

26.5

18.8

19

Multi-Standard Multi-Band Reconfigurable LNA

higher value of external gate-source capacitance ( Cex ), also contributes to higher power consumption due to the gain compensation. This is the price to gain full integration. In terms of input and output return losses, the achieved results for reconfigurable LNA are comparable to the wide band LNAs. Meanwhile, for reverse isolation, the attained results of the reconfigurable LNA are very close to the achieved results of the wide band LNAs in Mustaffa, Zayegh, Veljanovski, Stojcevski, & Zulkifli (2008a and 2008b). Table 8 also shows a comparable result for NF between reconfigurable LNA and wide band LNAs. However, the achieved NF for both bands of the reconfigurable LNA is a bit higher than that of the wide band LNAs. This is due to the use of a higher value of gate inductor LG (higher series resistance) and the use of the switch SW0 at the input of the LNA. The use of the switch contributes extra noise to the circuit when the reconfigurable LNA operates at lower band mode due to the on resistance of SW0 . However, looking at the simulated NF for lower band mode compared to upper band mode, the difference is marginal. Regarding linearity, the attained results are comparable between reconfigurable LNA and wide band LNAs in Mustaffa, Zayegh, Veljanovski, Stojcevski, & Zulkifli (2008a and 2008b). For reconfigurable LNA, the achieved result for certain parameter, i.e. P1dB is better than that of wide band LNA (-0.5 to -2.02 dBm). This could be explained by the use of more power consumption in the reconfigurable LNA compared to wide band LNAs.

CONCLUSION In this chapter, details on the concepts of mobile communication system and issues regarding it as well as the design and implementation of a reconfigurable multi-standard multi-band LNA have been presented. The reconfigurable LNA which use IDCS technique as the base, adopted new technique to achieve good output impedance matching and much better linearity without the need for buffer section. It has been shown that the reconfigurable LNA works in two modes of operation and proven by the simulation results. This reconfigurable LNA is fully integrated and achieved a relatively minimal noise figure for a specified power budget. The concept of hardware sharing introduced for the purpose of gaining full integration reduces the chip area. This was done by using less and smaller inductors. In terms of performance of the reconfigurable LNA, especially NF as one of the important parameter in the design, the simulation results show a good agreement with the targeted specification outline in previous section.

REFERENCES Boeck, G., Pienkowski, D., Circa, R., Otte, M., Heyne, B., Rykaczewski, P., et al. (2003). RF Front-end Technology for Reconfigurable Mobile Systems. Paper presented at the IEEE International Microwave and Optoelectronics Conference, IMOC2003, Iguazu Falls Parana Brazil. Brandolini, M., Rossi, P., Manstretta, D., & Svelto, F. (2005). Toward Multistandard Mobile Terminals— Fully Integrated Receivers Requirements and Architectures. IEEE Transactions on Microwave Theory and Techniques, 53(3), 1026–1038. doi:10.1109/TMTT.2005.843505

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Multi-Standard Multi-Band Reconfigurable LNA

Colomines, S., Arnaud, T., Parra, T., Graffeuil, J., & Plana, R. (2000). Low noise, high linearity and low power BiCMOS mixer for RF applications. In Proceedings of the Third IEEE International Caracas Conference on Devices, Circuits, and Systems (pp. C16/1 -C16/6). Dao, V. K., Bui, Q. D., & Park, C. S. (2007). A Multi-band 900MHz/1.8GHz/5.2GHz LNA for Reconfigurable Radio. IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Honolulu (pp. 69-72). European Telecommunications Standards Institute (ETSI). (1999). Digital cellular telecommunications system (Phase 2+); Universal Mobile Telecommunications System (UMTS). 3rd Generation mobile system Release 1999 Specifications, vol. 3G TS 21.101. Guillou, Y. L., Gaborieau, O., Gamand, P., Isberg, M., Jakobsson, P., & Jonsson, L. (2005). Highly Integrated Direct Conversion Receiver for GSM/GPRS/EDGE With On-Chip 84-dB Dynamic Range Continuous-Time ∑∆ ADC. IEEE Journal of Solid-state Circuits, 40(2). Kakerow, R., Mueller, M., Pieńkowski, D., Circa, R., & Boeck, G. (2005). Reconfigurable Receiver Approach for 4G Terminals and Beyond. The 3rd International IEEE-NEWCAS Conference (pp. 9-12). Kawazoe, D., Sugawara, H., Ito, T., Okada, K., & Masu, K. (2005). Reconfigurable CMOS Low Noise Amplifier for Self Compensation. IEEE International Symposium Circuits and Systems, ISCAS ’06, Melbourne (pp. 1-5). Kim, J. H., Jang, Y. K., & Yoo, H. J. (2007). Design of reconfigurable RF front-end for multi-standard receiver using switchable passive networks. Springer Journal of Analog Integrated Circuits and Signal Processing, 50(2), 81–88. doi:10.1007/s10470-006-9000-1 Kim, Y. J., Son, Y. S., Parkhomenko, V. N., Hwang, I. C., Cho, J. K., Nah, K. S., & Park, B. H. (2005). A GSM/EGSM/DCS/PCS Direct Conversion Receiver With Integrated Synthesizer. IEEE Transactions on Microwave Theory and Techniques, 53(2). Lee, T. H. (2004). The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge: Cambridge University Press. Li, X., & Ismail, M. (2002). Multi-standard CMOS Wireless Receivers: Analysis and Design. Kluwer Academic Publishers. Liscidini, A., Brandolini, M., Sanzogni, D., & Castello, R. (2006). A 0.13 µm CMOS Front-End, for DCS1800/UMTS/ 802.11b-g With Multiband Positive Feedback Low-Noise Amplifier. IEEE Journal of Solid-state Circuits, 41(4), 981–989. doi:10.1109/JSSC.2006.870890 Moreira, C. P., Kerherve, E., Jarry, P., & Belot, D. (2006). A Reconfigurable DCS1800/W-CDMA LNA: Design and Implementation Issues. In Proceedings of the 9th European Conference on Wireless Technology, Manchester UK, September 2006 (pp. 357-360). Moreira, C. P., Kerherve, E., Jarry, P., & Belot, D. (2006). A Reconfigurable DCS1800/W-CDMA LNA: Design and Implementation Issues. In Proceedings of the 9th European Conference on Wireless Technology, Manchester UK (pp. 357-360).

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Multi-Standard Multi-Band Reconfigurable LNA

Mustaffa, M. T., Zayegh, A., Veljanovski, R., & Stojcevski, A. (2006). Optimised Low Noise Amplifier for Multi-standard Receiver Architecture. In Proceedings of Advanced Technologies in Telecommunications and Control Engineering, (ATTCE), 28-29 August 2006, Malaysia. Mustaffa, M. T., Zayegh, A., Veljanovski, R., Stojcevski, A., & Zulkifli, T. Z. A. (2008a). 0.18 µm Fully Integrated 900 MHz CMOS LNA with Input and Output On-chip matching for Multi-standard Mobile Receiver. In Proceedings of IEEE International Conference on Microelectronics, 14-17 December 2008, Sharjah, UAE. Mustaffa, M. T., Zayegh, A., Veljanovski, R., Stojcevski, A., & Zulkifli, T. Z. A. (2008b). Fully Integrated 2-GHz LNA with On-chip matching for Multi-standard Mobile Receiver using 0.18 µm CMOS Technology. In Proceedings of IEEE TENCON International Conference, 18-21 November 2008, Hyderabad, India. Nguyen, T. K., Kim, C. H., Ihm, G. J., Yang, M. S., & Lee, S. G. (2004). CMOS Low-Noise Amplifier Design Optimization Techniques. IEEE Transactions on Microwave Theory and Techniques, 52(5). doi:10.1109/TMTT.2004.827014 Pieńkowski, D. (2004). CMOS Low-Noise Amplifier Design for Reconfigurable Mobile Terminals. Ph.D. dissertation, Von der Fakultät IV Elektrotechnik und Informatik der Technishen Universität, Berlin. Qualcomm CDMA Technologies. (n.d.). MSM6275TM Chipset Solution. Retrieved from http://www. cdmatech.com/ products/ msm6275_ chipset_ solution.jsp 3rd Generation Partnership Project (1999). Technical Specification Group Radio Access Network; User Equipment (UE) radio transmission and reception (FDD), (R’99). V1.0.0. 3rd Generation Partnership Project (2008a). Technical Specification Group GSM/EDGE Radio Access Network; Radio transmission and reception (Release 7). V7.14.0. 3rd Generation Partnership Project (2008b). Technical Specification Group Radio Access Network; User Equipment (UE) radio transmission and reception (FDD), (Release 8). V8.3.0. Song, E., Koo, Y., Jung, Y. J., Lee, D. H., Chu, S., & Chae, S. I. (2005). A 0.25-µm CMOS Quad-Band GSM RF Transceiver Using an Efficient Local Oscillator (LO) Frequency Plan. IEEE Journal of Solidstate Circuits, 40(5). Soorapanth, T., & Lee, T. H. (1997). RF Linearity of Short-Channel MOSFETs. In Proceedings of the First International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (pp. 81-84). Springer, A., Maurer, L., & Weigel, R. (2002). RF System Concepts for Highly Integrated RFICs for W-CDMA Mobile Radio Terminals. IEEE Transactions on Microwave Theory and Techniques, 503(1). Texas Instruments, R. F. Technologies (n.d.). TRF6151 Transceiver Solution. Retrieved from http:// www.ti.com Tzeng, F., Jahanian, A., & Heydari, P. (2008). A Multiband Inductor-Reuse CMOS Low-Noise Amplifier. IEEE Transactions on Circuits and Wystems. II, Express Briefs, 55(3), 209–213. doi:10.1109/ TCSII.2008.918922

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Multi-Standard Multi-Band Reconfigurable LNA

Universal Cellular Engineering (UCE). (n.d.). GSM and UMTS/WCDMA standards. Retrieved from http://www.uce-international.com Vahidfar, M. B., & Shoaei, O. (2006). A Triple Mode LNA Enhanced by Dual Feedback Loops for Multi Standard Receivers. 49th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS ‘06 (pp. 159-162). Veljanovski, R., Stojcevski, A., Singh, J., Faulkner, M., & Zayegh, A. (2003). A Highly Efficient Reconfigurable Architecture for an UTRA-TDD Mobile Station Receiver. Paper presented at the IEEE International Symposium on Circuits and Systems, ISCAS ‘03.

23

24

Chapter 2

LNA Inventions Norlaili Mohd. Noh Universiti Sains Malaysia, Malaysia

ABSTRACT The main design goals of an LNA are to achieve low noise figure, high gain, good linearity and good matching and reverse isolation. The choice of the LNA topology is therefore very important to suit the design application. Five LNA topologies were studied, analyzed and compared in this chapter. The topologies are the Simultaneous Noise and Input Matching (SNIM), Power-constrained Simultaneous Noise and Input Matching (PCSNIM), Current-reuse (CR) and Folded-cascode (FC) LNAs. The last topology is the PCSNIM with buffer. The circuits are analyzed in detail in terms of their functionality and compared based on the LNAs typical performance metrics. From the analysis, the PCSNIM technique can improve matching and noise performance of the inductively degenerated cascode. The current-reuse is found to consume less current but maintaining the circuit’s transconductance to achieve the desirable gain. The folded-cascode operates at lower voltage and hence is suitable for low-powered designs. Consequently, it is also resulting in the lowest noise-figure amongst the other designs.

INTRODUCTION The inductively-degenerated common-source (CS) cascode is preferred over other architectures such as CS with shunt-input resistor, common-gate (CG), and shunt-series amplifiers (Lee, 2004) due to its ability to provide low noise figure. In this chapter, four LNA topologies of the modified inductively-degenerated cascode LNA were studied, analyzed and compared. The topologies studied are the Simultaneous Noise and Input Matching (SNIM), Power-constrained Simultaneous Noise and Input Matching (PCSNIM), Current-reuse (CR) and Folded-cascode (FC) LNAs. As the name implies, the SNIM method enables simultaneous noise and input matching. However, there is a constraint in implementing this method as the NF will differ away from the NFmin when the device gets smaller or when the design is for low power implementation (Nguyen et al., 2004). The PCSNIM is an evolution of the SNIM which enables simultaneous noise and input matching even for small devices and low power operation (Nguyen et al., 2004). With the addition of a buffer at the output of the PCSNIM, impedance transformation is obtained to to enable the DOI: 10.4018/978-1-60566-886-4.ch002

Copyright © 2012, IGI Global. Copying or distributing in print or electronic forms without written permission of IGI Global is prohibited.

LNA Inventions

output stage of PCSNIM to be matched to a lower impedance load. In the CR, an NMOS in a cascode is replaced with an inverter-like combination of PMOS and NMOS to reduce power consumption but maintaining the transconductance in order not to reduce the gain (Karanicolas, 1996). Finally, the FC LNA was not only designed for low voltage operation but also for good noise performance (Abou-Allam & Manku, 1998). From the analysis of the topologies modified from the inductively-degenerated cascode LNA, a new topology is given to provide good gain and noise performance without the need of external matching circuitries. This chapter is divided according to the five topologies involved in the study. Under each division, the functionality of each topology is studied. The characteristics that distinguished one topology from the rest are analyzed. Comments on the capabilities of each topology in achieving the desired performance metrics are given. Derivations of equations are given to enable better understanding on how the circuits perform. Simulations were performed on all five designs based on the typical performance metrics of the LNA and the results given. Results will be discussed and followed by conclusions.

BACKGROUND Amplifier Topologies Common-Source (CS) Amplifier with Shunt-Input Resistor This topology is shown in Figure 1. The CS amplifier provides reasonable 50 Ω termination due to the 50 Ω resistor, R1, across the input terminals (Shaeffer & Lee, 1997; Lee, 2004). The input impedance of the circuit is Zin = Z1 // R1 where Zin is the input impedance to the amplifier and Z1 is the input impedance to the transistor. RS is the source resistance and RL is the load resistance. vin is the input voltage and vout is the output voltage. Since R1 = RS = 50 Ω and Z1 = 1 / sCgs is much larger than 50 Ω for frequencies up to a few GHz, Zin is almost 50 Ω. Cgs is the transistor’s G-S capacitance. Unfortunately, the presence of R1 will attenuate the signal by a factor of 2 ahead of the transistor. The reason is obvious by looking at the circuit in Figure 1, where

v = gs

(R1 / /Z1) v (R1 / /Z1) + R S in

(1.1)

Because of the value possessed by R1 and Z1, the voltage at the MOS input, vgs, will be almost half of the input voltage vin (R1 // Z1 ≈ R1 = 50 Ω). Furthermore, like any other resistor, R1 adds to thermal noise. Thus this type of topology results in very high NF. It is given in Lee (2004) that the noise factor of this circuit is F ≥ 2 + (4 γ / α)(1 / gmR) where R = RS = R1, γ is the noise parameter and α = gm / gd0. gm is the transistor’s transconductance and gd0 is the transistor’s drain-source conductance at 0 VDS. This noise factor term is for low frequency of operation and not including the gate noise. For high frequency of operation, and if gate noise is to be considered, the noise performance will be much more degraded. As reported in (Lee, 2004), the NF can reach 11 dB for an 800MHz of operation.

25

LNA Inventions

Figure 1. CS amplifier with shunt-input resistor (ac representation)

Common Gate (CG) Amplifier The CG amplifier is shown in Figure 2. This circuit has resistive input impedance as Zin = 1 / gm (Allstot et al., 2004). Because of this, proper selection of the device size and bias current can provide the desired 50 Ω resistance. The noise factor of this circuit is given by F ≥ 1 + γ / α (Lee, 2004) for low frequency and not considering gate noise. So, for long-channel devices, as γ = 2 / 3 and α = 1, F ≥ 1 + 2 / 3 = 1.67. Hence NF = 2.23 dB. For short-channel devices, the NF will increase to 4.8 dB if γ / α is assumed to be 2. This assumption is reasonable as α for short-channel devices will be less than unity and γ for shortchannel devices is always taken as double to triple its value for long-channel devices. γ is in the range of 1 to 2 for short-channel devices (Lee, 2004).

Shunt-Series Amplifier The shunt series amplifier shown in Figure 3 provides broadband real input impedance. It does not reduce signal with noisy attenuator before amplifying, therefore, NF is better than the first topology (Shaeffer & Lee, 1997; Lee, 2004). Although suffering fewer problems than the CS with shunt input resistor, it still generates thermal noise due to the existence of the resistive feedback, Rf. The amplifier with this Figure 2. CG amplifier (ac representation)

26

LNA Inventions

Figure 3. Shunt-series amplifier

topology will never present to the transistor an impedance equals to the optimum source impedance of the noise, Zopt, at any frequency (Lee, 2004). Hence, F > Fmin where Fmin is the minimum noise factor. However, the broadband capability of this circuit compensates for the drawback in the noise performance. Therefore, this topology is normally found in many LNA applications. The existence of resistors in all the three topologies described above present noisy resistance in the signal path. Consequently, these circuits suffer NF degradation. There is one topology that provides resistive input impedance without having to use resistors. This topology is the inductively degenerated CS LNA shown in Figure 4.

Inductively-Degenerated CS Amplifier The inductively-degenerated CS LNA is to ease input matching (Gharpurey et al., 2003). To calculate the input impedance, the small-signal model in Figure 5 is used. The following derivations can show how the input can be easily matched to the source resistance:

Figure 4. Inductively-degenerated CS amplifier (Adapted from Shaeffer & Lee, 1999)

27

LNA Inventions

 1  vin = iin  + sLg + R Lg  + (iin + g m v gs ) (sLs + R Ls )   sCgs v gs =

iin sCgs

(1.2) (1.3)

 1   i  v in = iin  + sLg + R Lg  + iin + g m in  (sL s + R Ls )    sCgs sCgs   g L  1 Zin = s (L g + L s ) + R Lg + R Ls + m s  + (1 + g m R Ls )   Cgs  sCgs

(1.4) (1.5)

Hence, Zin is a series RLC network with a resistive term that is directly proportional to the inductance value (Pärssinen et al., 1998; Goo et al., 2002; Guo & Huang, 2002). At resonance, the real term in Zin includes Ls. Therefore, this degenerated inductor is used for input matching. As a result, the presence of Ls helps in presenting a proper input impedance to terminate the off-chip RF filter preceeding the LNA, in the typical case, matched to 50 Ω. Lg on the other hand will resonate with Cgs and ensure that the input frequency will be tuned to the operating frequency. At resonance: R S = R in = R Lg + R Ls + s (L g + L s ) +

gm Ls Cgs

≈ R Lg + R Ls + ωT LS = 50 Ω

1 (1 + g m R Ls ) = 0 sCgs

jω o ( L g + L s ) =

j (1 + g m R Ls ) ωo Cgs

Figure 5. Small signal model for the inductively-degenerated CS amplifier

28

(1.6)

LNA Inventions

Lg =

1 (1 + gm R Ls ) - Ls ωo Cgs 2

(1.7)

The inductively-degenerated CS LNA has always been considered to give the best noise performance due to the absence of resistors (with the exception of the series resistor in the inductors) compared to the CS. However, it has a drawback of being sensitive to gate induced current noise (if compared to CG) (Zhuo et al., 2005). This noise is proportional to the quality (Q) -factor of the input circuit (Andreani & Sjoland, 2001) and hence, the Q-factor of the input circuit should not be too high for this reason.

Inductively-Degenerated Cascode LNA An example of a single stage LNA is the typical inductively-degenerated CS open-drain cascode shown in Figure 6. The benefits of cascoding are stated as the following: 1. The interaction between the output and the input stages is reduced. This means that the input matching, size of input transistor and load can be separately optimized. Due to this separation, reverse isolation is also improved and hence LO feedthrough (from the mixer back to the LNA input) can be better suppressed (Lee et al., 2003). Besides this, the stability of the LNA is improved as the cascode minimizes feedback from output to input. If the same circuit is implemented but without the cascode transistor, the circuit will be prone to oscillation (Razavi, 1998, Pärssinen, 2001). 2. The effect of M1’s Cgd (Miller effect) is reduced. This is due to the input resistance of the cascode transistor (M2) being much smaller than the ouput resistance of the CS M1. The result is that the Figure 6. Single-stage inductively-degenerated CS open-drain cascode LNA (Adapted from Shaeffer & Lee, 1997, Guo & Huang, 2002)

29

LNA Inventions

bandwidth and gain of the LNA will not be significantly affected by the Miller effect if it operates at high frequency. Cascode amplifiers had been very popular for almost three quarter of a century (Sedra & Smith, 2004). The reason is that this topology combines the high input resistance and large transconductance offered by a CS amplifier with the current-buffering capability and good high-frequency response of a CG amplifier. Although the cascode is actually a cascade of a CS with a CG, it is normally treated as a single-stage amplifier (Sedra & Smith, 2004). As for the advantage of the open-drain connection, Ld will enable node capacitance at the drain of M2 to resonate with it to tune the output to the resonating frequency and provide additional band-pass filtering. To give more flexibility in tuning the output to the desired frequency and additional filtering, Cd is included in the circuit. A further advantage of this topology is that Ld will let only a very small voltage across it due to its series resistance. Hence, this type of connection is very beneficial for low power design. M3 is for biasing the LNA circuit as M3 and M1 are in the current mirror connection. The ratio of M3 and M1 determines the current flowing through the cascode branch. Proper selection of M1’s width will determine the voltage across G-S of M1. R2 isolate the signal path from the current mirror. In this way, the input signal will be ac coupled to the LNA input. The value of R2 is not critical as long as it is much greater than the input impedance of the cascode LNA. The Ls in this circuit has the contributions as such described in sub-section Inductively-degenerated CS amplifier. This degeneration inductor enables more flexibility in matching the input stage to 50 Ω. It also influences the gain of the LNA. Combination of Ls and Lg will tune the input to the desired frequency.

LNAS WITH NOISE AND INPUT MATCHING TECHNIQUES Circuit techniques were developed to obtain good noise and gain performance. The popular ones are the Simultaneous Noise and Input Matching (SNIM) and Power-constrained Noise Optimization (PCNO) techniques which were invented to provide simultaneous noise and input matching. The latest is PCSNIM which evolved from the former two techniques (Nguyen et al., 2004).

Classical Noise Matching (CNM) LNA In CNM, the LNA is designed for minimum NF by presenting the optimum noise impedance, Zopt to the amplifier (Haus et al., 1960). This is implemented by adding a matching circuit between the source and the input of the amplifier. No degeneration- inductor in this type of circuit. Input gain mismatch can occur if there exists mismatch between the noise impedance and the complex conjugate of the amplifier’s input impedance (Nguyen et al., 2004). Hence, a compromise between the gain and noise performance was unavoidable. Figure 7 (a) shows the schematic of the CNM cascode LNA. This is followed by Figure 7 (b) which represents the small-signal model with noise sources of the CNM cascode LNA. For simplification, the CG transistor’s effects on the noise and frequency reponse in this figure is neglected. The same assumption applies to the parasitic resistances of the transistors.

30

LNA Inventions

Figure 7. (a) The CNM cascode LNA, (b) the small-signal model with noise sources of the CNM cascode

Mean-squared channel thermal noise is given by the following equation: id 2 = 4kT γgdo ∆f

(1.8)

where gd0 is the D-S conductance at Vds = 0 V, k = Boltzmann constant, T = absolute temperature and Δf = bandwidth, γ = 1 at Vds = 0 V and 2/3 when the transistor is in saturation. γ increases at high Vgs and Vds and can be higher in short channel device (Lee, 2004; Knoblinger et al., 2000). Due to the channel thermal noise, there exists fluctuation in the channel potential. This fluctuation will be capacitively coupled to the gate terminal, subsequently causing a noisy gate current. In a MOS device, when the device is biased so that the channel is inverted, fluctuations in the channel charge will induce a physical current in the gate due to capacitive coupling. This noise current is normally not included in the simple noise model for MOS. A more precise noise model must therefore include this induced gate current noise and is shown in Figure 8. When the device is in saturation, ig 2 ∆f

= 4kTδg g

(1.9)

31

LNA Inventions

Figure 8. Gate circuit model including induced effects (Adapted from Shaeffer & Lee, 1997)

where ig is the shunt noise current and g g =

ωo 2 Cgs 2

is a real, noiseless conductance in the gate circuit 5g d0 (van der Ziel, 1970; Shaeffer & Lee, 1997). This conductance is not the same as the polysilicon resistance. δ is the coefficient of gate noise and is normally stated as having a value of 4/3 for long channel devices. 2

The mean-squared gate-induced noise current, ig 2 , was given by Equation (1.9). Gate noise coefficient, δ = 4/3 (which is 2 x γ) for long channel devices (Lee, 2004). The presence of the induced gate noise complicates the analysis of F significantly. As there exist correlation between the channel noise current and the gate induced noise current, the two are related by the correlation coefficient, c, for long channel devices given by (Shaeffer & Lee, 1997). c=

ig i*d ig id 2

2

≈ j0.395

(1.10)

Their relationship was expressed by Equation (1.10). As stated in Equation (1.10), c = j0.395 for long-channel devices (Lee, 2004). c is purely imaginary indicating the capacitive coupling between the channel and gate-induced noise sources. The noise parameters for the cascode amplifier are given below (Nguyen et al., 2004). Noise resistance:

Rno = αγ g1

m

.

(1.11)

Optimum noise admittance: Yopto = αωoC gs

32

 δ 2 (1 − c ) − sC gs 1 + α c  5γ

δ  . 5γ 

(1.12)

LNA Inventions

Minimum noise factor: Fmino = 1 +

2 ωo 5 ωT

2

γδ(1 − c ) .

(1.13)

Transition radian frequency, ωT = gm/Cgs, and α = gm / gd0 = 1 for long-channel devices. Equations (1.11) to (1.13) have superscripted “o” to differentiate these parameters from the same parameters but for other topologies. Observing Figure 7 (b), it is obvious that the input admittance to the circuit is purely capacitive, Yin = jωoCgs. By comparing the complex conjugate of this admittance with Equation (1.12), it is seen that the Yopto contains a real term which is not available in Yin. This indicates that input matching and minimum noise figure cannot be simultaneously obtained from this topology.

SNIM LNA In SNIM, a feedback technique is adopted by using a degeneration inductor, Ls. The schematic is being shown in Figure 9 (a) while its small-signal model with noise sources is represented by Figure 9 (b). This technique can shift the Zopt to a desired value (Nguyen et al., 2004). This type of input matching is suitable for narrow-band applications and also for large transistor, thus high power dissipation, and high frequency of operation. From Equation 1.15, problem can occur if the size of the transistor is small, Figure 9. (a)The SNIM cascode LNA, (b) the small-signal model with noise sources of the SNIM cascode

33

LNA Inventions

giving low gm and Cgs (Darabi & Abidi, 2000). For the same reason, the SNIM topology will not be suitable for circuits requiring low power consumption and device having small ωT. For operation under these conditions, the minimum noise factor can even be higher than the Fmin of the typical CS amplifier, hence it defies the purpose of adopting SNIM. From Nguyen et al. (2004):  2    δ    2   1 + s C gs (Lg + Ls ) 1+ | c | α     γ 5      2  1    F = 1 + 2 γgd 0  δ   −(sC gs Rs )2 1+ | c | α gm Rs      5γ      αδ 2 2 2 2 − (1− | c | )gm (sC gs ) (Rs − sLg )    5

(1.14)

Rn = Rno = αγ g1

(1.15)

Zopt = Zopto − sLs

(1.16)

m

ω

2 o Fmin = Fmino = 1 + 5 ωT

2

γδ(1 − c )

 δ δ  (1− | c |2 ) + j 1 + α | c |   5γ 5γ  2  2     α δ δ   (1− | c |2 ) + 1 + α | c |   oC gs   5γ  5γ    

(1.17)

α

Zopto = 1 / Yopto =

(1.18)

ω

Zin = s (Ls + Lg ) + 1 + gmLs = s (Ls + Lg ) + 1 + ωT Ls sC gs C gs sC gs

(1.19)

Equation (1.19) shows that there is a real term in the Zin equation. The modification to the circuit which includes Ls in the cascode is important as it creates a possibility of making Zin to be the same as the Zopto. The conditions that enables simultaneous noise and input matching are (Nguyen et al., 2004), Zopt = Zin *

(1.20)

Re [Zopt] = Re [ZS]

(1.21)

Im [Zopt] = Im [ZS]

(1.22)

Im [Zin] = -Im [ZS]

(1.23)

With the SNIM topology, there seems to be no problem in achieving simultaneous noise and input matching as long as Equations 1.22, 1.23 and 1.25 are fulfilled and Equations 1.17 to 1.19 are valid. How-

34

LNA Inventions

ever, from Equation 1.20, when the operating frequency is low or/and when the device size is small, the real part of Zopto will be high. At a given ωo, the increased real part of Zopto due to the reduction in device size will require a large Ls in order to satisfy Zopt = Zin *. Problem arises if Ls is made larger than a certain value that causes the expression of Fmin = Fmino becomes invalid and instead Fmin increases significantly (Goo et al., 2002) making it larger than Fmino and, thus, making the reason for utilizing SNIM unworthy.

PCNO Technique In PCNO technique, simultaneous gain and noise matching is possible at any amount of power dissipation. This is achieved by proper selection of Ls at any given Cgs (Shaeffer & Lee, 1997). Under fixed drain current, there exists a transistor’s width which can result in a low NF. The derivation for achieving the expression which relates noise parameters with the transistor’s size to give minimum noise factor is explained in great detail in (Lee, 2004). The width of the optimum device is written here as follows (Lee, 2004): Wopt,P = D

3

1

2 ω LCox R s Qs,opt,P o

(1.24)

D

where, Qs,opt,P is the quality factor of the input circuit of the LNA that leads to the power-constrained minimum noise figure (Lee, 2004) and is defined by the following: D

Qs,opt,P = c D

5γ δ

  δ   3   + + +  1 1 1   2  5γ    c   

(1.25)

where | c |= 0.395 and γ δ = 0.5 to give Qs,opt,P ≈ 4 (Lee, 2004). In Equation 1.24, Cox is the oxide capacitance, RS = 50 Ω and L is the transistor’s length. Referring to Lee (2004), a more exact analysis is said to give an optimum value of Qs closer to 4.5 for the 0.35 μm process that Lee’s design (Lee, 2004) was implemented on. Nevertheless, a variation of Qs,opt,P from 1.5 to 5.5 changes the NF by only 0.1 dB and because of this, the NF is said to be insensitive to the change of Qs in this particular range (Shaeffer & Lee, 1997; Lee, 2004). In this chapter, the noise contours for PD versus Qs were plotted and given in Figure 10 for a 0.18 μm CMOS process. This noise contours show that for a fixed NF, a variation of Qs in the range of 1.5 to 4.5 will result in constant power dissipation. It is also given by Abou-Allam & Manku (1998) that the minimum noise factor under PCNO is: D

D

Fmin,P = 1 + 2.4 (γ α )(ωo ωT ) D

(1.26)

which is higher than the minimum noise factor of the CS transistor. The minimum noise factor of the CS transistor is (Lee, 2004):

35

LNA Inventions

Figure 10. PD versus Q plot at different NF for a 0.18 μm CMOS process

 2 Fmin = 1 + (2 5 )(ωo ωT ) γδ 1- c  



(1.27)

The reason for the difference between Equations 1.28 and 1.29 is because of the mismatch between the input impedance of the LNA, Zin, and Zopt and/or high value of Ls as had been described earlier.

PCSNIM LNA The last noise and input matching technique is PCSNIM, which enables simultaneous noise and input matching for low-power implementations (Andreani & Sjoland, 2001; Nguyen & Lee, 2003). The basic SNIM in Figure 9 does not allow this. PCSNIM is especially suitable for low-power implementation in mobile radio transceivers. The difference between the SNIM and PCSNIM is the additional Cex in parallel with Cgs. In this technique, even if the transistor is small in size and resulting in small Cgs, noise and input matching can still be achieved by manipulating the value of Cex. The schematic and small-signal model with noise sources that represents the PCSNIM topology is shown in Figure 11(a) and (b) respectively. 2 2 ig 2 = 4kT δeff ω C t ∆f 5gd 0 C 2 δeff = δ gs1 Ct

Ct =Cgs +Cex

36

(1.28) (1.29) (1.30)

LNA Inventions

Noise parameters:

Rn = αγ g1

(1.31)

m

C δ δ   (1- | c |2 ) + j  t + α | c |   Cgs 5γ 5γ  - jω o L s Zopt = 2   2   δ   αδ C (1- | c |2 ) +  t + α | c | ωo Cgs    5γ  Cgs 5γ         δ α 1-|c|2  5γ  Re[Zopt ] =       2        α2δ   C    δ  2 t      1-|c| + + α |c| ωo Cgs          5γ   C  5γ   gs   C δ   j  t + α | c |   Cgs 5γ  - jω o L s Im[Zopt ] = 2   2   αδ δ   C ωo Cgs  (1- | c |2 ) +  t + α | c |   5γ  Cgs 5γ     α

Fmin = 1 + ( 2









5 ) (ωo ωT ) γδ 1- c 2 

(1.32)

(1.33)

(1.34)

(1.35)

Input impedance,      Zin = 1 + sLg + s1  1 + 1  + 1 + gm s1  1 + 1  sLs Cex Cex sCc C gs   C gs 

    = 1 + sLg + s1  1 + 1  + sLs + gm s1 sLs  1 + 1  C ex Cex sCc C gs  C gs      = 1 + sLg + s1  1 + 1  + sLs + gmLs  1 + 1  Cex Cex C gs  C gs  sCc

Zin =

g L 1 1 + sLg + + sL s + m s sCc sCt Ct

Re[Zin ] =

gmL s Ct

s(Lg + Ls ) + 1 s [(1 Ct ) + (1 Cc )] = 0

(1.36) (1.37) (1.38)

In the case where the device is small, there is no need to increase Ls to maintain Zopt = Zin* as Cex can be manipulated to perform this task. The size of Ls can, in fact, be made smaller than what has been

37

LNA Inventions

Figure 11. (a)The PCSNIM cascode LNA with additional capacitor across the input transistor, (b) the small signal model with noise sources of the PCSNIM LNA (Adapted from Nguyen & Lee, 2003)

calculated for SNIM LNA and thus, generating a better gain and NF. It was shown by Equation (1.14) that lowering the Lg + Ls will increase voltage gain. NF can be improved with the lowering of Ls because the series resistance grows with the value of inductance and the noise factor is proportional to this series resistance. Hence, PCSNIM topology enables the noise factor to be close to the minimum value possible.

CR LNA Power consumption is a major concern in portable wireless systems. The demand from consumers is for light and small mobile devices. In fact, the weight and size of a device determines whether a device can be called “mobile”. To prolong the time between battery recharge, devices like the mobile telephones must employ power conscious ICs in their systems (Abidi et al., 2000). CR is a technique that enables larger transconductance at the same bias current (Karanicolas, 1996). The circuit is such that the inverter-like combination of M1 and M2 in Figure 12 replaces the commonsource M1 in the inductively-degenerated cascode LNA. Since transconductance determines gain, and gain and power consumption are two very important performance metrics of the LNA, this criteria of the CR is a very important asset. To understand how the CR circuit works, the current consumption and transconductance of the three connections shown in Figure 12 are very necessary to be analyzed first.

38

LNA Inventions

Transconductance in Figure 12 (a) is: g m = 2µnCox (

W )(ID ) L

(1.39)

Since the size of M1 and M2 are the same, gm1 = gm2. Thus, total transconductance in Figure 12 (b) is gmT = gm 1 + gm 2 = 2 2µnC ox (

1W 1 W )( I D ) = 2µnC ox I D = gm 2 L 2 L

(1.40)

Hence, for 2 NMOS in parallel, the total current and total transconductance is the same as having just 1 NMOS in the circuit. For the circuit in Figure 12 (c): gm 1 = 2µnC oxn (

1W 1 1 W )( I D ) = 2µnC ox ID 2 L 2 2 L

(1.41)

gm 2 = 2µpC oxp (

1W 1 1 W )( I D ) = 2µpC oxp ID L 2 L 2 2

(1.42)

Hence, gm 2 =

µ  1 1 W W 2  n C oxp 2µnC oxn ID ≈ ID  3.9  2 4 L L

(1.43)

From the specifications given by the foundry for a 0.18 μm process, the mobility of the electrons is 3.9 times that of the holes (µn = 390 cm2/Vs, µp = 100.1 cm2/Vs). For this derivation, the assumption is Coxn = Coxp, to simplify the derivation. This assumption is quite true as toxp is very close to toxn (3.9 nm and 1.6 nm, respectively) resulting in Coxn = 9.45 mF/m2 and Coxp = 8.9 mF/m2. Total transconductance, Figure 12. (a) Single NMOS. (b) two NMOS in parallel. (c) NMOS and PMOS in inverter connection (Adapted from Karanicolas, 1996; Fouad et al., 2001)

39

LNA Inventions

gmT = gm1 + gm2 = 0.75 gm. The total current consumed by the inverter circuit is ½ ID. This means that for half the current consumed by circuit Figure 12(b), Figure 12 (c) is able to provide ¾ of the gm. Another way of looking at the situation is that if the current flowing through Figure 12 (a) and Figure 12 (c) are the same (ID), the amount of transconductance generated by the latter is more by 0.5gm (or 0.48gm if the precise values of Coxn and Coxp are used). gm 1 = 2µnC oxn

W W I D = 2µnC ox ID L L

W W I D = 2µnC ox I L L D + g = 1.5g

gm 1 2µnC oxn gmT = gm 1

m2

m

(1.44) (1.45) (1.46)

Hence, CR is used to increase the amplifier transconductance without having to increase current and power dissipation. The input capacitance to Figure 12 (a) is Cgs = (2/3)WLCox and the input capacitance of Figure 12 (c) is CgsT = Cgsn+Cgsp. Cgsn = (1/2)(2/3)WLCox and Cgsp = (1/2)(2/3)WLCox. Thus, CgsT = Cgs. As M1 and M2 in Figure 12 (c) are in the inverter combination and both transistors have to be in their saturation mode, the precise DC voltage has to be at the input (or the gate) of these transistors. This can be seen from Figure 13 which shows the operating regions of the NMOS and PMOS transistors in an inverter configuration (Kang & Leblebici, 2003). Table 1 lists these regions of operation and the corresponding critical input and output voltage levels (Kang & Leblebici, 2003). It can be seen from Figure 13 that the Vin region which has both transistors in their saturation mode of operation is very narrow. This value of Vin needs to be determined to ensure that both transistors are ON. Figure 14 shows the CR LNA which utilizes the inverter connection shown in Figure 12 (c) to replace the M1 in the inductively-degenerated cascode LNA. The second stage of the CR consists of M4, which is a common-gate device. The main function of M4 is to increase the overall gain of the LNA and to isolate the output stage from the input. CC1 is to isolate the biasing of M4 from the M1 and M2 branch. Cex1 and Cex2 serve the same function as the Cex in a PCSNIM LNA. Ld is to resonate with Cd to tune the output signal to the desired frequency. A resistor can perform the task of a current source in the M4 branch, but at the expense of a degradation in the NF of the LNA. Thus, transistor M5 performs this function better.

FC LNA The folded-cascode is basically to convert the input voltage to a current. The total bias current, however, is higher than the conventional cascode in order to achieve a comparable performance (Razavi, 2001). The schematic of the FC LNA used in this work is shown in Figure 15. The circuit is based on the topology shown by Abou-Allam et al. (2001). In Figure 15, the CS M1 is to amplify the signal and M2 acts as the current buffer. The supply voltage for this circuit is close to the bias voltage and thus the output swing is limited (Razavi, 2001). For W-CDMA application, this is not an issue as the input signal is small (as low as -117 dBm i.e. 0.3 µV) (Floyd et al., 2005). The folding of the CG helps to eliminate the parasitic

40

LNA Inventions

Table 1. Operating regions and corresponding critical input and output voltage levels of a CMOS inverter (Kang & Leblebici, 2003) Region

Vin

Vout

NMOS

PMOS

A

VOH

cut-off

linear

B

VIL

high ≈ VOH

saturation

linear

C

Vth

Vth

saturation

saturation

D

VIH

low ≈ VOL

linear

saturation

E

>(VDD +Vth0p)

VOL

linear

cut-off

VIH = high input voltage, VIL = low input voltage, VOH = high output voltage and VOL = low output voltage. Vth = threshold voltage of the input and output voltages. VDD is the supply voltage to the inverter circuit. Vth0p = zero-bias threshold voltage of the PMOS and Vth0n = = zerobias threshold voltage of the NMOS.

Figure 13. Operating regions of the NMOS and PMOS transistors in a CMOS inverter (Adapted from Kang & Leblebici, 2003)

capacitances at the drain of the CS M1 by resonating with Ld. Elimination of the parasitic capacitance helps to suppress the noise contribution of CG transistor at the output. Lo is to resonate with the output capacitance at the operating frequency. To be comparable with the other two topologies, the same type of current-mirror biasing circuit was utilized. From Abou-Allam & Manku (1998), the minimum noise factor for this topology is given as:

F

min

= 1 + 4πCgs1f

(

ξ αsat R Lg1 + R Ls1 1

K1VDD

)

(1.47)

where, K1 = µn Cox1 W1 L1 and ξ1 is the parameter representing VDS to VOV ratio required for velocity saturation to occur. αsat ≥ γ , depending on the substrate conductivity. RLg1 and RLs1 are the series resis-

41

LNA Inventions

Figure 14. The CR LNA

tances of Lg and Ls, respectively. For comparison, the minimum noise factor of the typical cascode is given by (Abou-Allam & Manku, 1998): F

min

+R ) 0.5 α ( R = 1 + 4πCgs1f ξ1 +(K1 K 2 )  sat Lg1 Ls1 





 K1 (VDD -Vth2 )

(1.48)

Comparing Equation (1.48) with Equation (1.47), it is clear that the folded-cascode has a better noise performance.

PCSNIM LNA with Output Buffer The SNIM and PCSNIM LNAs may require matching circuitries at their input and output stages. The need for a matching network at the input stage of the LNA may not be as critical as at the output stage since all of the LNA topologies described in this chapter had utilized the degenerative inductor, Ls, to enable on-chip input matching. A one-stage LC matching network is sufficient to be included at the input if there is a need to obtain an extremely good input matching. However, a different consideration for matching has to be made at the output stage of these LNAs. The SNIM and PCSNIM LNAs in this work utilized the cascode as their basic structure. A basic cascode has a high output impedance (Sedra & Smith, 2004; Gray et al., 2001). If the LNA is to be characterized, a 50 Ω output matched cascode has to be implemented.

42

LNA Inventions

Figure 15. The FC LNA

L-C on-chip matching circuits will demand much larger space as inductors are huge passive components. If a single T L-C network is connected at each input and output stage of the PCSNIM LNA, an extra four inductors and two capacitors will have to be implemented on the design. In this work, a PCSNIM with output buffer was implemented to avoid using inductors as the matching components. Two extra capacitors and transistors, and a resistor are required in this design. A common-drain (CD) transistor is used to act as the buffer and this transistor is shown as M4 in Figure 16. M5 is operating as a current-source. The space consumed by the two extra transistors does not significantly increase the overall layout size. Ld is to resonate with Cd, Cgs_M4, Co, Cgd_M5 and the bondpad capacitance to provide tuning at the desired frequency. Cc1 is the coupling capacitor that will isolate the biasing of the buffer from the cascode. A large capacitor in pF will perform the function. A resistor can perform the same function as the M5, but at the expense of an increase in layout size. Ro is to function the same way as R2. The transistor M2 has a width of half of the width of M1. This is to accomplish a better IIP3 based on the study by Guo & Huang (2002). It was shown in this paper that M2 has more influence on the linearity performance of the cascode as compared to M1. If the linearity of the LNA needs to be optimized, modifications should be performed on M2. In the same study performed by Guo & Huang (2002), it was found that the IIP3 of M2 improves with the increase of DC biasing of M2. Increasing the supply voltage can increase the DC biasing of this transistor, but at the expense of increasing the power consumption of the whole cascode. An alternative method to increase the DC bias of M2 without resulting in a higher power consumption is by optimizing the width at a suitable bias voltage. At the same time, the DC bias voltage of M1 should be optimized to reduce the power consumption of the design and achieve good noise performance. The width of M2, WM2, should be designed at ≥ ½ the width of M1, WM1. If WM2 is less than half of WM1 (in the study by Guo & Huang (2002), a 250 μm WM1 should not have a WM2 of less than 100 μm for a design on a 0.35 μm process), a condition maybe reached where the output resistance of M2 will be much larger than that of M1. The bias voltage of M2 will be much higher than the bias voltage of M1 resulting in the M1 not to be able to operate in the saturation mode. If WM2 ≥ ½ WM1, both M1 and M2 43

LNA Inventions

Figure 16. The modified PCSNIM with output buffer LNA

will operate in the saturation region and under this condition, the WM2 has little effect on the minimum NF of the cascode architecture. On the other hand, the WM1 was found by Guo & Huang (2002) to have little effect on the linearity performance of the cascode. In their work, the change in the OIP3 is 8% only with the variation in WM1. Table 2 presents the distinct features that differentiate the four modified inductively-degenerated cascode LNA topologies discussed in this chapter. The SNIM is the conventional inductively-degenerated cascode LNA.

CONCLUSION The SNIM is the conventional inductively–degenerated CS cascode. This topology is widely used as it provides simultaneous noise and input matching with good reverse isolation due to the cascode connection. The PCSNIM is a modified SNIM which has a capacitor connected across the input of the amplifying transistor. This topology is to obtain noise input impedance that closely matches the circuit input impedance. The CR enables lower current consumption without deteriorating the transconductance much. Hence, a high gain can be achieved at a lower current consumption. As for the FC, the supply voltage is slightly more than the biasing voltage. Thus, this configuration is suitable for low-voltage and consequently, low power operation. Finally, the PCSNIM with output buffer enables the output stage of the PCSNIM to be matched to a low impedance load. As a result, the gain and noise figure will also improve.

44

LNA Inventions

Table 2. Summary of the comparison between the different modified inductively-degenerated cascode LNA LNA Topology

Features

SNIM

This is the conventional inductively –degenerated CS with Ls as its degeneration inductor.

PCSNIM

Contains Ls and an additional capacitor, Cex, across the G-S of the input transistor. This configuration is to obtain noise input impedance that closely matches the circuit input impedance.

CR

An NMOS and a PMOS in a CMOS inverter configuration replaces the input NMOS transistor in the SNIM. This configuration enables lower current consumption without deteriorating the transconductance much.

FC

The NMOS and PMOS in a folded-cascode configuration. The supply voltage is slightly more than the biasing voltage. This configuration is suitable for low-voltage operation.

PCSNIM with output buffer

The buffer transforms the high output impedance of the cascode to a value equals to the 50 Ω required. The buffer is a common-drain with a common-source current source. The output impedance of the common-drain determines the output impedance of this LNA and can be made to equal 50 Ω by setting the size of M4. With the improvement in the output matching, gain and NF also improve.

REFERENCES Abidi, A. A., Pottie, G. J., & Kaiser, W. J. (2000). Power-conscious design of wireless circuits and systems. Proceedings of the IEEE, 88(10), 1528–1545. doi:10.1109/5.888993 Abou-Allam, E., & Manku, T. (1998). A low voltage design technique for low noise RF integrated circuits. Paper presented at the Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (ISCAS ’98) Monterey, CA. Andreani, P., & Sjoland, H. (2001). Noise optimization of an inductively degenerated CMOS low noise amplifier. Circuits and Systems II: Analog and Digital Signal Processing. IEEE Transactions on, 48(9), 835–841. Darabi, H., & Abidi, A. A. (2000). A 4.5-mW 900-MHz CMOS receiver for wireless paging. Solid-State Circuits. IEEE Journal of, 35(8), 1085–1096. Floyd, B. A., Reynolds, S. K., Zwick, T., Khuon, L., Beukema, T., & Pfeiffer, U. R. (2005). WCDMA direct-conversion receiver front-end comparison in RF-CMOS and SiGe BiCMOS. Microwave Theory and Techniques. IEEE Transactions on, 53(4), 1181–1188. Fouad, H., Sharaf, K., El-Diwany, E., & El-Hennawy, H. (2001). An RF CMOS cascode LNA with current reuse and inductive source degeneration. Paper presented at the Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems (MWSCAS 2001) Michigan State, USA. Gharpurey, R., Yanduru, N., Dantoni, F., Litmanen, P., Sirna, G., & Mayhugh, T. (2003). A direct-conversion receiver for the 3G WCDMA standard. Solid-State Circuits. IEEE Journal of, 38(3), 556–560. Goo, J. S., Ahn, H. T., Ladwig, D. J., Yu, Z., Lee, T. H., & Dutton, R. W. (2002). A noise optimization technique for integrated low-noise amplifiers. Solid-State Circuits. IEEE Journal of, 37(8), 994–1002.

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Gray, P. R., Hurst, P. J., Lewis, S. H., & Meyer, R. G. (2001). Analysis and design of analog integrated circuits (4th ed.). New Jersey: John Wiley & Sons. Guo, W., & Huang, D. (2002). The noise and linearity optimization for a 1.9-GHz CMOS low noise amplifier. Paper presented at the Proceedings of the 2002 3rd International Conference on Microwave and Millimeter Wave Technology Beijing, China. Haus, H., Atkinson, W., Branch, G., Davenport, W., Fonger, W., Harris, W., et al. Talpey, T. (1960). Representation of noise in linear twoports. Proceedings of the Institute of Radio Engineers (IRE) 48(1), 69-74. Kang, S. M., & Leblebici, Y. (2003). CMOS digital integrated circuits, analysis and design (3rd ed.). McGraw-Hill. Karanicolas, A. N. (1996). A 2.7-v 900-Mhz cmos lna and mixer. Solid-State Circuits. IEEE Journal of, 31(12), 1939–1944. Knoblinger, G., Klein, P., & Baumann, U. (2000). Thermal Channel Noise of Quarter and Sub-Quarter Micron NMOS FET’s. Paper presented at the Proceedings of the IEEE 2000 International Conference on Microelectronic Test Structures (ICMTS 2000), Monterey, USA. Lee, K. Y., Lee, S. W., Koo, Y., Huh, H. K., Nam, H. Y., & Lee, J. W. (2003). Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver. Solid-State Circuits. IEEE Journal of, 38(1), 43–53. Lee, T. H. (2004). The design of CMOS radio-frequency integrated circuits (4th ed.). Cambridge Univ Press. Nguyen, T. K., Kim, C. H., Ihm, G. J., Yang, M. S., & Lee, S. G. (2004). CMOS low-noise amplifier design optimization techniques. Microwave Theory and Techniques. IEEE Transactions on, 52(5), 1433–1442. Nguyen, T. K., & Lee, S. G. (2003). Noise and gain optimization technique for RF-integrated CMOS low noise amplifier. Paper presented at the Proceedings of the 2003 IEEE Conference on Electron Devices and Solid-State Circuits Hong Kong. Pärssinen, A., & ebrary, I. (2001). Direct conversion receivers in wide-band systems: Kluwer Academic Publishers. Parssinen, A., Lindfors, S., Ryynanen, J., Long, S., & Halonen, K. (1998). 1.8 GHz CMOS LNA with on-chip DC-coupling for a subsampling direct conversion front-end. Paper presented at the Proceedings of the 1999 IEEE International Symposium on Circuits and Systems (ISCAS 1999) Monterey, CA, USA. Razavi, B. (2001). Design of Analog CMOS Integrated Circuits: McGraw-Hill Series in Electrical and Computer Engineering. New York, USA: McGraw-Hill. Razavi, B., & Behzad, R. (1998). RF microelectronics: Vol. 46. PTR. NJ: Prentice Hall. Sedra, A. S., & Smith, K. C. (2004). Microelectronic Circuits (5th ed.). New York: Oxford University Press. Shaeffer, D. K., & Lee, T. H. (1997). A 1.5-V, 1.5-GHz CMOS low noise amplifier. Solid-State Circuits. IEEE Journal of, 32(5), 745–759.

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Shaeffer, D. K., & Lee, T. H. (1999). The design and implementation of low-power CMOS radio receivers. Springer Netherlands. Van Der Ziel, A. (1970). Noise in solid-state devices and lasers. Proceedings of the IEEE, 58(8), 1178– 1206. doi:10.1109/PROC.1970.7896 Zhuo, W., Li, X., Shekhar, S., Embabi, S., de Gyvez, J. P., Allstot, D., & Sanchez-Sinencio, E. (2005). A capacitor cross-coupled common-gate low-noise amplifier. Circuits and Systems II: Express Briefs. IEEE Transactions on, 52(12), 875–879.

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48

Chapter 3

Multiband Multi-Standard LNA with CPW Transmission Line Inductor M. Ben Amor National Engineering School of Sfax, Tunisia M. Loulou University of Sfax, Tunisia S. Quintanel ENSEA University of Cergy Pontoise, France D. Pasquet Microelectronics and Semiconductor Physics Laboratory (LaMIPS), NXP-CRISMAT-ENSICAEN, France

ABSTRACT LNA is one very essential bloc in the RF receiver. Due to the growth of the standard evolution, this component must handle several frequency bands with the best performances. This chapter presents a wide band LNA design for IEEE802.16 standard with the CMOS 0.35µm technology. In this LNA, we use a CPW transmission line to design the inductive degeneration inductor of 0.38nH. This circuit has a S21 of 12dB, a noise figure less than 3dB and an input/output reflexion coefficient less than -10dB between 2 and 6GHz. The CPW line presents a characteristic impedance of 120Ω, an inductance of 0.38nH, a capacitance of few fF and a resistance less than 2Ω on the desired frequency band.

INTRODUCTION Traditional wireless communication systems are designed for only one standard. However, the demand for wireless services convergence, in which users can access different standards with the same wireless device, is driving the multi-bands multi-standards transceivers development. Thus, future RF front-ends need to operate over a multiple frequency bands with the best performances such as low cost, least size and with low power. DOI: 10.4018/978-1-60566-886-4.ch003

Copyright © 2012, IGI Global. Copying or distributing in print or electronic forms without written permission of IGI Global is prohibited.

Multiband Multi-Standard LNA with CPW Transmission Line Inductor

Different receiver architectures exist in the literature and the objective of any designer is to find the best full receiver integration solution for multi-standards applications. One of the multi-band receiver components is the low noise amplifier LNA which has to be able to operate over multi-bands frequencies with the same specifications especially in term of gain, noise, matching and linearity. In the integrated circuit of the RF systems, passives elements are widely used especially in the impedance matching between the different blocs of the receiver such as between antenna-LNA or between LNA-mixer. These passives can be lumped (spiral inductor) or distributed (transmission line) and in both cases they have an important role. This chapter treats the design of a multi-bands LNA for the WiMAX receiver with the use of a coplanar wave guide CPW transmission line inductor. In the second section we will present the different receivers architectures and the choice of the best one for WiMAX applications. In the third section we will present the different multi-bands LNA structures in the literature, followed by the proposed wide band LNA circuit design. Next, transmission lines types are described and a comparison between them is done to choose the best and performed one which is the CPW line for the design of a low value inductor. Finally, simulation results are presented.

RECEIVER ARCHITECTURE In the receiver path, the main role of the RF part is the transposition of the modulated signal, which was received by the antenna, to the base band. The difference between one receiver and other in RF systems is presented in the disposition and in the number of blocs. (Super)Heterodyne, homodyne zero IF and low IF are the three existing receivers architectures. Each one has its advantages and its drawbacks.

Heterodyne Receiver The super heterodyne architecture [L. Lévy, http://perso.club-internet.fr/dspt/LEVY.htm], Figure 1, provides the best and superior selectivity and sensitivity with the use of two down conversion steps of the desired RF signal. The first down conversion of the signal is around a fixed intermediate frequency (IF) and the second down conversion to the base band is centered on the central frequency of the desired channel. These two steps are realized with two local oscillators. However, an undesired image signal will be created after the first mixing which has to be attenuated with an image reject filter and this last constitutes the major drawback of this architecture. RF and IF filters integrations are very difficult because the inductors have high quality factors. Moreover, this receiver requires an impedance matching between every two blocs, presents higher power consumption and it isn’t adaptable for multiband applications.

Homodyne Receiver (Zero IF) In the previous receiver, the frequency down conversion is done in two steps. To resolve the image reject problem, the homodyne receiver (Colebraok, http://www.thevalvepage.com/radtech/synchro/synchro. htm), Figure 2, or zero IF receiver doesn’t need an IF frequency and therefore there is a direct conversion to the base band. There is no image problem and therefore no need of a reject filter neither a necessity

49

Multiband Multi-Standard LNA with CPW Transmission Line Inductor

Figure 1. Heterodyne receiver architecture

to impedance match between the LNA and the filter. Moreover, the channel filtering is done at the base band and thus its filter can have a high quality factor and can be integrated. However, this architecture has some problems. DC-offset phenomenon is one of these problems. Since the signal is directly converted to the baseband without filtering (only one band select filter), some DC signals can appear as parasitic signals. Using an AC coupling capacitor at the mixer output is a way to cancel this problem. In the wide band systems (LAN systems), AC coupling capacitor can be on chip and in the narrow band system they are off chip

Direct Conversion Receiver (Low IF) This architecture (B. Razavi 1998), Figure 3, is an alternative of the direct conversion receiver to resolve the DC-offset problem. It’s an intermediate solution between the two previous one. In this case the signal is converted to a low intermediate frequency IF and not directly to the base band. The image signal is again a problem. To resolve it, some methods are developed with Harlely (M. Steyart, et al., 1998) or Weaver.

Figure 2. Homodyne receiver architecture

50

Multiband Multi-Standard LNA with CPW Transmission Line Inductor

To achieve the multiband band performances, homodyne architecture (Zero/Low IF) is the most advantageous. Table 1 shows a comparison between the three described receiver architectures. The RF part of the homodyne receiver is fully integrated and has the lowest power consumption. It presents also less bloc number than the heterodyne.

WiMAX Receiver WiMAX or Worldwide Interoperability for Microwave Access or the IEEE802.16 is the new generation of wireless communication systems. It covers 50km and supports data rates of 70Mbps. This technology provides fixed and mobile wide band wireless access. Point to point is the configuration supported by this standard to satisfy the wide band access. Mobile WiMAX or IEEE802.16e has a frequency range between 2 and 6GHz which is formed with licensed end unlicensed frequency bands subdivided to 3 groups as shown in Figure 4. Each standard presents its own characteristics such as the sensitivity ‘S’, the signal to noise ratio ‘SNR’ and the noise figure requirements. The WiMAX receiver for mobile application has a sensitivity which is estimated to be -68dB with OFDMA modulation (Orthogonal Frequency Division Multiple Access) for 20MHz channel bandwidth (variable from 1.25 to 20MHz) and with the using of 3/4 coding rate 64-QAM (Quadrature Amplitude Modulation) (IEEE standard 802.16, 2008). The maximum input power is -30dBm and the receiver NF is 8dB (in addition of implementation losses 5dB). The receiver has 22dB for the second order intercept point IIP2. Figure 3. Low IF direct conversion receiver architecture

Table 1. Comparison of the receiver architecture integration and multi-standard Capabilities Receiver architecture

Integration capabilities

Multi-standard capabilities

Super-heterodyne

Low

Medium

Homodyne

High

High

Low IF

High

Medium

51

Multiband Multi-Standard LNA with CPW Transmission Line Inductor

Figure 4. WiMAX frequency bands

Each receiver is formed with a filter, LNA, Mixer, a second filter and a VGA (Voltage Gain Amplifier). With a budget simulation, we can estimate the WiMAX receiver specifications as given in Table 2:

MULTIBAND LNA Multiband Receiver The LNA is an important component in each RF receiver. Since it is the first active block in the receiver front-end, it has to provide a considerable gain and a low noise figure. There are several receives kinds which ensure the multi-band and multi-standards functionalities. The simplest multi-band receivers are formed, using one front-end for each frequency band (TriQuint Semiconductor, 1995), Figure 5 (a). The LNA in that case is simple band operating at one central frequency and therefore the multi-bands LNA is formed by a parallel multi-simple band LNAs. Due to the increasing number of standards, this approach requires many inductors and therefore a large chip area and high power consumption and thus a high cost. Using one multi-band receiver presents also a second solution (C.-W Kim & M.-S. Kang, 2005). This one can be dual bands or multi-band and it is based on the use of only one receiver with one multi-band front-end. The Figure 5 (b) shows the dual band case, operating at two different frequency bands (M. Ben Table 2. WiMAX receiver specifications

52

Parameters

LNA

Mixer

VGA

Gain(dB)

≥10

10

5

NF(dB)

≤3

10

16

IIP3(dBm)

≥-5

5

16

Multiband Multi-Standard LNA with CPW Transmission Line Inductor

Amor, A. Fakhfakh, H. Mnif & M. Loulou, 2008). In this case, the receiver is formed by a dual bands antenna, dual bands filter, dual bands LNA and a dual bands frequency down conversion. This solution presents an advantage especially since there is attenuation of the unwanted and out of band frequencies and therefore a low noise figure, low area and low power consumption. The drawback of this architecture is that the design is more difficult for cases superior than two frequencies bands. Actually, The most performed solution that meets the requirements of the market and which exists face to the increased number of standards is the use of a receiver which contains one wide band LNA, Figure 5 (c). This LNA has to be able to handle multiple carriers frequencies in a broad bandwidth with the same performances as the LNA is optimized for only one carrier frequency.

Multiband LNA Topologies The wide band LNA must has sufficient gain, low noise figure and an input/output impedance matching over a large frequency band. Several topologies and techniques are proposed in the literature to be requested to those specifications. Negative feedback configuration (C J.-H.C. Zhan & S.S. Taylor, 2006), Figure 6 (a), can ensure wide band performances. This technique can provide flat gain, wide band input matching and can also reduce the circuit sensitivity of the MOS transistor parameters However, this architecture presents a drawback since the feedback, and especially the resistive feedback, increases the LNA noise and reduces the gain; this is due to parasitic capacitance of the transistor. Distributed Amplifier DA(B.M.Ballweber, R.Gupta, & D.J.Allstot, 2000), Figure 6 (b), is also a topology which ensures a broad bandwidth and low amplification. DA is formed by two transmissions lines input and output coupled by transistors transconductances. Transmission lines are formed using inductors and designated by gate and drain lines. Gate line is regularly charged by the gate to source capacitor of the MOS transistor and is connected to its characteristic impedance Z0 at the end. RF signal passes through the gate line. The transistor ensures thus the signal transfer to the drain line through its Figure 5. (a) Parallel multiband receiver architecture, (b) Dual band receiver architecture and (c) Wide band receiver

53

Multiband Multi-Standard LNA with CPW Transmission Line Inductor

transconductance. The signal at the output passes in the opposite direction will be absorbed by the gate line load. Due to the large number transconductance stages used, the DA power consumption is very high compared to other LNA topologies, in addition to the drawback of the large area occupied by the circuit. Thermal noise cancelled LNA, Figure 6 (c): Feedback amplifiers need generally two amplification stages to provide sufficient gain and therefore much power dissipation. Moreover, the input impedances of these amplifiers are the function of their gain. To resolve these problems, the thermal noise cancelled technique was used by (F. Bruccoleri, E.A.M. Klumperink & B. Nauta, 2004). By choosing the best Av, the MOS transistor noise contribution will be equal to zero and therefore a low noise figure can be obtained for a large frequency range. In spite of these advantages, the frequency band can be limited at high frequencies. Moreover, the noise figure increases with frequency and this is due to the parasitic capacitance. There is another drawback which is the high power consumption of this topology.

Wide Band LNA Design Finding the performed method that simultaneously provides impedance and noise matching (low noise figure) and high gain, represents the most important target in LNA design. For the wide band case, these conditions have to be established for all frequency bands. There is a great and particularly relation between the impedance matching and the noise conditions. In that case, circuit parameters have to be extremely initialized and designed to achieve that conditions. One important key in the LNA design, is the impedance matching and this is due to nature of the MOS transistor input which is approximately purely capacitive. In that case, if we want to ensure 50Ohms impedance at the circuit input, we have to provide a good match to the transistor source without degrading noise performances. For wide band LNA, the input matching has to be wide band and we have to provide the desired resistive input at the whole frequency band. To achieve this condition, there are numerous solutions as shown at Figure 7: Resistive termination, Figure 7 (a): This approach presents the most basic and simple solution to achieve the 50Ω wide band input matching. This topology presents a high bandwidth function of the transistor input capacitor. R1 which is placed at the input of the LNA helps to provide the wide band input matching. However, this resistance has a thermal noise (T. N. Lee, 1998) that will be added to the circuit noise and therefore an increased circuit noise factor. Figure 6. (a) Feedback LNA, (b) Distributed Amplifier and (c) Thermal noise cancelled LNA topology

54

Multiband Multi-Standard LNA with CPW Transmission Line Inductor

Figure 7. Wide band input matching: (a) Resistive termination, (b) Resistive Shunt Feedback (c) Common Gate and (d) LC-Ladder Filter Based impedance matching network

Resistive Shunt Feedback (C.-W Kim, M.-S. Kang, 2005), Figure 7 (b): This topology presents another way to achieve a wide band input matching. Since the bandwidth is inversely proportioned to the quality factor and since this last is inversely proportioned to the input resistance, adding the resistance Rf, is a solution to decrease Q and therefore to increase the bandwidth. The feedback resistor generates its own thermal noise and therefore this causes a high circuit noise figure. Moreover, the use of the feedback causes stability problem. This topology needs large power consumption or an advanced technology to obtain an acceptable noise figure. Common-Gate Input (Xiaohua Fan, Sanchez-Sinencio & E., Silva-Martinez, 2005), Figure 7 (c): This is another solution to ensure wideband input matching. This one is different since the input impedance is seen at the source not at the gate of the transistor and it’s equal to 1/gm. Therefore, with a best transistor sizing and with a suitable polarization (bias current), a wide band matching can be realized. Fixing gm for the desired source resistance presents a drawback of this configuration. Other drawbacks are the induced gate noise which will increase the noise factor, the high cost and the high power consumption. LC-Ladder Filter(Bevilacqua, & A.M.Niknejad, 2004): Figure 7 (d): This topology ensures the wideband impedance matching without modifying or fixing the transconductance and without degrading the noise factor. In fact, the inductive source degeneration matching technique offers the matching properties, but only at a single frequency around a narrow band. To extend matching on a large frequency range and, since the input impedance of the cascode amplifier can be seen as a part of a filter, the use of a band-pass LC filter at the input of the LNA can achieve a broadband input matching and dissipating a small power.

Wideband LNA Structure Analyze The target of this work is the design of a low noise amplifier for the WiMAX standard. From its frequency spectrum, we can note two approaches: the first one is the wideband LNA which covers all the frequency range from 2 to 6GHz and the second one is the dual wideband LNA which covers the two sub wide bands from 2 to 4GHz and from 5 to 6GHz (M. Ben Amor, M. Loulou, S. Quintanel & D. Pasquet, 2008) Classical wide band LNA circuit, Figure 8 (a), with the use of LC input network ensures all wide band performances as the flat gain, wideband impedance matching and the low noise figure. This LNA

55

Multiband Multi-Standard LNA with CPW Transmission Line Inductor

Figure 8. Wide band LNA structure, (a) classical, (b) proposed

is formed with a pass band filter at the input and a resonator network at the output to resonate at the central frequency. An additional capacitor Cd is added in parallel with the gate to the source capacitor Cgs and to increase the equivalent transistor gate to the source capacitor. However, this topology presents a low gain even if it’s flat. Figure 8 (b) shows the proposed wide band CMOS LNA. This circuit is composed of two cascading common-source amplifiers. These two stages share the same supply current in order to reduce the power dissipation and consumption: “current reuse topology “. This topology is a technique to improve the amplifier gain through the multiplication of these two stages transconductances. (M. Ben Amor, A. Fakhfakh, H. Mnif & M. Loulou, 2008 & TriQuint Semiconductor, 1995). Cr, Lr and C2 are the coupling capacitor, RF choke and the bypass capacitor providing AC ground, respectively. Lf is an inductor which is added to compensate the transistor parasitic drain to bulk capacitance Cdb. It improves the bandwidth and provides gain peaking at higher frequencies. Rs, R1 and R2 present the source and the bias resistors respectively.

Input Matching Narrow band LNA has to achieve input matching at a one frequency. However, wide band amplifier has to ensure this specification not only at one frequency but over a wide bandwidth. The Figure 9 shows the used wide band filter which is embedded at the input of the circuit. To ensure wide band input matching. The circuit elements are chosen so that: ωL ≈

56

R 1 R 1 ≈ , ωU ≈ ≈ L1 RC t L2 RC 1

(1)

Multiband Multi-Standard LNA with CPW Transmission Line Inductor

ωL and ωu represents the low and upper frequencies respectively. R (50 Ohms) is the matching resistor. The input impedance of an inductively degenerated transistor is in general equivalent to an RLC series network. As shown in Figure 9, this network is the same as the right part (series tank) of the band-pass filter. Consequently, the band-pass filter can embed the inductively degenerated transistor to acquire the desired input impedance value. In equations (1), L2 represents the source degeneration inductor which ensures the 50 Ohms input RC matching: L2 = s t . gm is the transconductance of transistor M1. C3 is a coupling capacitor to block gm

the DC. Its value should be so large to neglect the LC tank resonance modification. Ct is a sum of two capacitors: transistor gate to source capacitor Cgs and the parallel capacitor Cd. this last gives supplementary degrees of freedom to the matching network. Lg is a series inductance at the gate of the transistor and which may be needed to ensure the whole input network resonance at the center frequency of 4GHz. (L3, C3, L1, C1, L2, C2) values depend on the frequency band of interest.

Output Matching Since negative feedback circuit improves the bandwidth performance of the amplifier, therefore in the proposed LNA structure, a conventional inductive shunt feedback (Lf, Rf) is embedded at the output to ensure a large bandwidth and also to achieve wide band impedance matching. Moreover, another reason to use this circuit is the current reuse topology which was used. In fact, this technique increases the gain but only at one frequency, so a small bandwidth and the use of the feedback structure is a solution to extend this bandwidth especially because the output resistance doesn’t affect the noise figure of the LNA. The input stage is the stage which has the most noise contribution. The load network is designed to fulfill a flat gain over the bandwidth from 2 to 6GHz. LL must be sizable to have large gain and RL is chosen to have an output Q-factor equal to one (or a bandwidth of 4GHz).

Noise Contribution The noise is one important parameter in low noise amplifier blocks. These blocks have different noise sources. One of the noise contributions sources is the input-matching network losses due to the matching inductors which have a finite Q. In fact, the inductor series resistance creates thermal noise at the Figure 9. Input matching network

57

Multiband Multi-Standard LNA with CPW Transmission Line Inductor

circuit input and reduces the pass band gain. The other noise source in the LNA circuit is the input device M1. The most contributors on the device noise are the thermal drain current noise and the induced gate current noise. With reference to the model developed by Andreani et al. (P.Andreani & H.Sjoland 2001), a noise analyze on the LNA output response can be done. The Figure 10 shows the LNA circuit equivalent small signal diagram. This diagram shows the different thermal noise sources generated by the different inductor serial resistance in,R of the circuit (L1, Lg, Lf, L5). There is also the thermal noise of the gate resistance Rg, the source resistance and the output resistance. Transistors M1 and M2 noise sources are represented with the drain and gate current noise in,d(1,2) and in,g(1,2). The noise factor is expressed as follow: F=

2 2 2 2 2 2 2 2 2 2 + in,o,g + in,o,c + in,o,R in,o,R + in,o,R + in,o,d + in,o,g + in,o,c + in,o,rf + in2,o,R + in,o,d s

t

1

1

f

1

2

2

2 n,o,R s

i

2

out

(2)

2 2 2 in,o,R = in,o,R + in,o,R . t f 2 in,o,i represents the equivalent power spectral density of noise source indexes (i) which is calculated at 2 the LNA output. in,o,c is the power spectral density correlation between drain and gate. The simplified noise factor expression is:

F = 1+

γ γ1β1 g2 1 1 2 2 β1(Q 2 + )P 2 m + 1 gdn + cPgm + RQ gm + t gdn Rout 4 4 4

where c=0.4, β1=1, γ1=2.5, P =

RsQ 2gm2

(3)

C gs Ct

LNA Design Approach One difficulty in LNA design is to find the best and efficient methodology which can satisfy the amplifier characteristics, which are the high gain, the low noise figure and the impedance matching, at the same Figure 10. LNA small signal diagram

58

Multiband Multi-Standard LNA with CPW Transmission Line Inductor

Table 3. Input network components L1

C1

L2 (Lg+Ls)

C2(Cgs+Cd)

L3

C3

Butterworth

3.97 nH

0.53 pF

1.32nH

1.59pF

-

-

Chebyshev

2.31

0.91

2.05nH

1pF

2.05 nH

1 pF

time for all desired frequencies. However, the optimal source impedance for the best performance in term of noise is in general dissimilar from the matching condition for the maximum power dissipation. Consequently, it is very important to find the best design decisions of the different parameters in that LNA circuit and this due to the important relation between the impedance matching conditions and the noise contribution. In wide band LNA circuit, all these constraints have to be considered not only at one frequency but at a large frequency range. The wide band input matching is the most important and serious criteria in the wide band LNA design. Thus, the first design step is the search of the best input network to achieve the 50 Ohms impedance from 2 to 6GHz. The used input network is a wide band filter. Its components are obtained by setting the appropriate bandwidth. The center frequency is 4GHz. Table 3 summarizes two filters types structures values; the two-section Butterworth and three-section Chebyshev. We note that the Butterworth filter requires a capacitor Ct=1.59pF. This raised capacitor value requires an extremely high transistor transconductance gm to provide a sufficient gain (at resonate frequency f0 and at matching case), and low noise performance. Therefore this leads to an increased power dissipation or a high transistor width. If we compare the two filter structures values, we note that Chebyshev filter presents the decreased value of the capacitor Ct than Butterworth. This justifies the choice of this filter kind to embed it at the LNA input for providing the wide band input matching. The next design step is the determination of transistors sizes and the bias current that satisfies impedance and noise matching. These parameters are affected by three factors: minimum noise figure, the input quality factor (it should be equal to one) and the increased gain at the central frequency 4GHz. Q=

1 2RsC t ω0

(4)

Figure 11 shows the noise figure of the circuit NF versus the transistor width W and the bias current Id. This figure helps to determine the best (Id, W) combination which gives the minimum noise figure at the central frequency 4GHz. Some simplifications are considered in the noise figure expression. It can be note that a current superior than 20mA and a transistor width superior than 200µm which can give the low noise figure. A quality factor equal to one at the frequency 4GHz gives a transistor width W=370µm. Figure 12 (a) and (b) show the NF verses the transistor width and the bias current, respectively. By considering the three mentioned points and the previous input network components values, the width of transistor M1 is set to 330µm. This value is also chosen for the second transistor M2. The bias current is fixed at 25mA. These (W, Id) values gives Ls=0.38nH, Lg=1.5nH and Cp=0.1pF.

59

Multiband Multi-Standard LNA with CPW Transmission Line Inductor

Figure 11. NF versus the supply current Id and the width transistor W

INTEGRATED 0.38NH SELF After the determination of all components values the next step is the circuit design. The used technology is AMS CMOS 0.35µm. This process presents some limitations: first, there is the inductor values limitation and therefore we haven’t a degree of liberty in the inductance value choice. Second, the less given inductor value is 1nH and thus a design difficulty with values less than the given limit value. In the proposed wide LNA circuit, the source inductor Ls has the value of 0.38nH. This component has an important role for the input impedance matching and on the amplifier gain. One solution to implement the small inductor is the use of a transmission line. We can find several line types and the most popular and used on integrated circuit are the microstrip line and the coplanar wave guide CPW line, Figure 13.

Microstrip Line Microstrip transmission line (H. Hasegawa, M. Furukawa & H. Yanai, 1971), Figure 13 (a), geometrically consists of a conductive strip (‘w‘ strip width, ‘t‘ strip thickness) and a wider ground plan which are separated by a dielectric layer (‘h‘ substrate thickness). This line type is the most popular one, mainly for microwave integrated circuits and MMICs. Its main advantage is that all active components can be mounted on the top of the board. The disadvantage is that, sometimes some circuits such as filters or switches need high isolation and in that case we have to consider some external shielding.

CPW Structure Coplanar Waveguide CPW (V. Milanovic, M. Ozgur, D. C. DeGroot, J. A.Jargon, M. Gaitan & M. E. Zaghloul, 1998), Figure 13 (b), is a transmission line which is formed by a central conductor (center strip width ‘w‘) atop a substrate (height ‘h‘), separated from two ground plans (strip to ground space‘s‘). One advantage of CPW line, as microstrip, we can mount active devices on top of the circuit (L. N.Tran, D.

60

Multiband Multi-Standard LNA with CPW Transmission Line Inductor

Figure 12. (a) NF vs. W for Id=25mA, (b) NF vs. Id for W=330µm

Figure 13. (a) TFMS, (b) CPW transmission line cross section

Pasquet, E. Bourdel & S. Quintanel, 2008). Moreover, it can offer particularly high frequency response (100GHz or more) because the connection to the CPW line does not cause any parasitic discontinuities in the ground plan. Other advantage is that the coplanar transmission line presents less parasitic losses than microstrip, between the surfaces where the component is mounted and the ground especially the resistive losses. Despite of these advantages, CPW line presents some disadvantages such as design difficulties with some features (open and shorted stubs) and the heat dissipation which depends on the dielectric thickness.

Transmission Line Sizing Transmission line whatever its nature has a classical model. The per-unit-length model of a lossy line, Figure 14, is formed with series and parallel apparent distributed elements: inductance ‘L‘, capacitance ‘C‘, resistance ‘R‘ and conductance ‘G‘. These elements are derived from the propagation parameters (Gupta K.C., Garg R.,Bahl I. & Bhartia B., 1996):

61

Multiband Multi-Standard LNA with CPW Transmission Line Inductor

Figure 14. Transmission line electrical model

R + jLω = γZc G + jC ω =

γ Zc

(5)

γ is the propagation constant and Zc is the characteristic impedance of the line. γ and Zc can be determined from the S-parameters (R. Eisenstadt & Y. Eo, 1992): γ=

2 tanh−1 d

Zc = Z 0

 (1 + S − S )(1 − S − S )  11 21 11 21   (1 − S + S )(1 + S + S ) 11

21

11

(1 + S + S )(1 + S − S ) 11 21 11 21    (1 − S − S )(1 − S + S )  11

21

11

21

(6)

21

Z0 is the reference impedance (50Ω). ‘d‘ is length of the line (µm). The transmission line can be equivalent to an inductor or a capacitor considering its characteristic impedance and thus the geometric parameters. Table 4 summarizes this equivalence for the two line types. If the characteristic impedance is high, the line will be equivalent to an inductor and if the characteristic impedance is low, the line will be equivalent to a capacitor. Our interest is the inductor. In that case, the CPW line must be designed with low strip width and high strip to ground space. The microstrip line must be designed only with low width.

Application on LNA Circuit The target is the design of inductor with a CPW line and with the AMS CMOS 0.35µm technology for a wide band LNA circuit. This process presents four metal layers, four oxide layers atop silicon substrate. The high width and high level layer is metal 4, that’s why the line will be designed at this layer in order to ensure the lowest substrate losses. The source degeneration inductor Ls supports 25mA bias current which is the transistor M1 drain current Id. The used technology presents a rule for the use of each metal layer for the desired current. This rule is defined with a current-metal width ratio. This ratio is equal to 5mA/µm for the metal 4 and 1mA/ µm for the metal 1. To support 25mA current, the metal 4 width must be at least 5µm and the metal 1 width must be at least 25µm. Reducing these widths less than 5µm and 25µm can cause lines destruction. A line with a width of 25µm is not a good solution to design an inductor, because whenever the

62

Multiband Multi-Standard LNA with CPW Transmission Line Inductor

Table 4. Line equivalence in each transmission line types CPW

Microstrip

Strip width (w)

Low

High

Low

High

Strip to ground space(s)

High

Low

-

-

Characteristic impedance Zc

High

Low

High

Low

Line equivalence

L

C

L

C

width is lower, the inductor can be more created. This presents another advantage of the use of metal 4 layer, for the line design.

Design of a Microstrip Line The geometry of the microstrip line shows that this one needs a ground plan. However, the used technology doesn’t have this layer in the silicon substrate. By choosing one metal layer and connect it to the ground, can ensure the ground plan functionality. Metal 1 will be the best choice, if metal 4 is selected for the line design. The line width of 5µm (with metal 4) doesn’t perform the desired value inductor. The best width is 2µm which doesn’t respect the technological ratio and therefore there is a possibility of the line destruction. One solution to avoid this problem is by increasing the line length but this can increase resistive losses. Figure 19 shows the microstrip simulated parameters with a length of 350µm. The highest value of Zc, 170Ω as shown in Figure 15, implies that the line is equivalent to an inductor. This can be confirmed by comparing L and C line parameters which are showed in this figure. The inductance is about 0.38nH (0.4nH
Design of CPW Line This line type is simple to design. With the width of 5µm (metal 4), we can obtain the desired inductor and this because there is another parameter to sweep which is the strip to ground space in order to obtain high characteristic impedance. A CPW line with a width ‘w’ of 5µm, a strip to ground space ‘s’ of 40µm and a length ‘d’ of 350µm ensures an impedance Zc equal to 119Ω, Figure 16. This highest value of Zc gives an inductance of 0.38nH. The line capacitance C is about some fF and this value is so small and that the inductance will dominate. The resistance value of this line is between 1 and 2Ω from 2 to 6GHz. A low R implies a low influence on the circuit specification particularly on the input impedance matching and the noise figure. Table 5 shows a comparison between the two designed lines types. By comparing the two mentioning lines, we note that the coplanar wave guide has the best performances than microstrip line. The more important performance is the less resistive losses. Moreover, it has more degree of freedom in the design (more geometrical parameter). This leads to the CPW transmission line choice for the 0.38nH inductor design.

63

Multiband Multi-Standard LNA with CPW Transmission Line Inductor

Figure 15. Characteristic impedance Zc and the per-unit-length parameters R, L, C of the microstrip line

Table 5. Comparison between TFMS and CPW lines Zc(Ω)

L(nH)

C(fF)

R(Ω)

Microstrip

170

0.4-0.38

14-13.5

2-8

Coplanar

120

0.4-0.38

32-25

1-2

SIMULATIONS RESULTS This section presents the wide band LNA circuit simulation results from 2 to 6GHz. This LNA presents a wide band input/output matching. Figure 17 shows the simulated S11 and S22 from 2 to 6GHz. These two parameters prove that the two used techniques in the input and the output achieve a broad band matching. The LNA circuit ensures a flat gain about 12dB on the desired frequency range. The figure Figure 18 shows the simulated power gain, max available gain, the reverse isolation S12 and the input and output return loss. This figure shows that the power gain and the max available gain are almost equal from 2 to 6GHz. S11(dB) and an S22(dB) are below –10dB and this shows too, that the LNA circuit ensures a wide band input and output matching. Figure 19 shows the circuit noise performances. This circuit is noise matched since NF (or nf(2) in the Figure) is equal to NFmin on the whole frequency band. The NF value is below 3dB. To estimate the linearity circuit performance, the third intercept point IP3

64

Multiband Multi-Standard LNA with CPW Transmission Line Inductor

Figure 16. Characteristic impedance Zc and the per-unit-length parameters R, L, C of the coplanar line

Figure 17. Simulated S11 and S22, (b)

65

Multiband Multi-Standard LNA with CPW Transmission Line Inductor

Figure 18. Simulated power gain S21_dB, max available gain, S11_dB and S22_dB Input and output reflexion coefficients and the reverse isolation S12_dB

Figure 19. Wide band LNA noise Figure: NF and NFmin vs. frequency

is the best parameter to simulate. The presented wide band LNA presents an IIP3 of 4dBm, 7dBm and 8dBm at the frequencies 2GHz, 4GHz and 6GHz, respectively as shown in Figure 20.

CONCLUSION This chapter describes the design and integration of an essential component in the multiband RF receiver which is the multiband band low noise amplifier for the WiMAX standard from 2 to 6GHz. Initially, the different RF receiver architectures were presented and compared for the multiband performances to perform the WiMAX receiver specifications. Next, an overview of the different multiband and wide band LNA structures was presented. After that, the proposed wide band LNA structure and the design

66

Multiband Multi-Standard LNA with CPW Transmission Line Inductor

Figure 20. IIP3 of the Wide band LNA at (a) 2GHz, (b) 4GHz and (c) 6GHz

steps and method were presented. The proposed wideband LNA circuit uses the Chebyshev filter and an inductive shunt feedback for the broad band input and output matching respectively. The used feedback in the output can extend the circuit bandwidth and ensure a flat gain with respect to the noise factor. In this structure, the use of current reuse technique ensures the high gain without any constraint on the power dissipation. Finally, two transmission lines were presented, detailed and compared to design a low value inductor. The choice is set on the CPW line to design the 0.38nH inductor since it presents more advantages than microstrip line especially resistive losses.

REFERENCES Andreani, P., & Sjoland, H. (2001, September). Noise Optimization of an Inductively Degenerated CMOS Low Noise Amplifier. IEEE Transactions on Circuits and Systems, 48, 835–841. doi:10.1109/82.964996 Ballweber, B. M., Gupta, R., & Allstot, D. J. (2000, February). A fully integrated 0.5-5.5GHz CMOS distributed amplifier. IEEE Journal of Solid-state Circuits, 35(2), 231–239. doi:10.1109/4.823448 Ben Amor, M., Fakhfakh, A., Mnif, H., & Loulou, M. (2008, March). Dual Band CMOS LNA design with current reuse topology. International Journal of Electronics, 95(3), 193–210. doi:10.1080/00207210701827863 Ben Amor, M., Loulou, M., Quintanel, S., & Pasquet, D. (2008, March). Dual Wide Band low Noise Amplifier Design For The 4G of Wireless Applications. IEEE International Conference on Design and Technology of Integrated System in Nanoscale Era, 26-28, Tozeur, Tunisia. Bevilacqua, A., & Niknejad, A. M. (2004, December). An Ultra wideband CMOS low noise amplifier for 3.1-10.6GHz wireless receivers. IEEE Journal of Solid-state Circuits, 39(12), 2259–2268. doi:10.1109/ JSSC.2004.836338 Bruccoleri, F., Klumperink, E. A. M., & Nauta, B. (2004, February). Wide-band CMOS low-noise amplifier exploiting thermal noise cancelling. IEEE Journal of Solid-state Circuits, 39(2), 275–282. doi:10.1109/JSSC.2003.821786

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Multiband Multi-Standard LNA with CPW Transmission Line Inductor

Colebraok (n.d.). Retrieved from http://www.thevalvepage.com/ radtech/ synchro/ synchro.htm Eisenstadt, R., & Eo, Y. (1992, August). S-Parameter based IC Interconnect Transmission Line Characterization. IEEE Transactions on Comp. Hybrids. Manuf. Technology, 15, 483–490. doi:10.1109/33.159877 Fan; X., Sanchez-Sinencio, E., & Silva-Martinez (2005, August). A 3GHz-10GHz common gate ultra wide band low noise amplifier.. 48th Midwest Symposium on Circuits and Systems, 2005 (Vol. 1., pp. 631-634 Vol. 1 Gupta, K. C., Garg, R., Bahl, I., & Bhartia, B. (1996). Microstrip Lines and Slotlines. Norwood, MA: Artech House. Hasegawa, H., Furukawa, M., & Yanai, H. (1971, November). Properties of microstrip line on Si-SiO2 system. IEEE Transactions on Microwave Theory and Techniques, 19(11), 869–881. doi:10.1109/ TMTT.1971.1127658 IEEE standard 802.16 (2008). Air Interface for Fixed Broadband Wireless Access Systems. part 16. Kim, C.-W., & Kang, M.-S. (2005, February). An Ultra-Wideband CMOS Low Noise Amplifier for 3-5GHz UWB System. IEEE Journal of Solid-state Circuits, 40(2). Lee, T. N. (1998). The Design of CMOS Radio-Frequency Integrated Circuits (1st ed.). New York: Cambridge University Press. Lévy, L. (n.d.). Retrieved from http://perso.club-internet.fr/ dspt/ LEVY.htm Milanovic, V., Ozgur, M., DeGroot, D. C., Jargon, J. A., Gaitan, M., & Zaghloul, M. E. (1998, May). Characterization of broadband transmission for coplanar waveguides on CMOS silicon substrate. IEEE Transactions on Microwave Theory and Techniques, 46(5), 632–640. doi:10.1109/22.668675 Razavi, B. (1998). RF Microelectronics. Prentice Hall. Steyart, M., et al. (1998). A Single-Chip CMOS Transceiver for DCS-1800 Wireless Communications. In Proceedings of the 1998 ISSCC (pp. 48-49). Tran, L. N., Pasquet, D., Bourdel, E., & Quintanel, S. (2008, March). CAD-Oriented Model of a Coplanar Line on a Silicon Substrate Including Eddy-Current Effects and Skin Effect. IEEE Transactions on Microwave Theory and Techniques, 56, 663–670. doi:10.1109/TMTT.2008.916941 TriQuint Semiconductor. (1995). TQ9203, Low-current RFIC downconverter. In Wireless Communication Products. Retrieved from: www.Triguint.com/ company/ divisions/ wireless/ docs/ TQ9203/ TQ9203.pdf Zhan, J.-H. C., & Taylor, S. S. (2006). A 5GHz Resistive-Feedback CMOS LNA for Low-Cost MultiStandard Applications. In Proc. of the IEEE International Solid-State Circuits Conf. (pp. 200–201).

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Chapter 4

Design of Low Noise Amplifiers through Flow-Graphs and their Optimization by the Simulated Annealing Technique M. Fakhfakh University of Sfax, Tunisia M. Boughariou University of Sfax, Tunisia A. Sallem University of Sfax, Tunisia M. Loulou University of Sfax, Tunisia

ABSTRACT This chapter presents the optimal design of Low Noise Amplifiers (LNAs). The basic idea consists of optimizing performances of LNAs by a direct action on the scattering parameters. A symbolic approach, namely the Coates Flow-Graph technique, is used to automatically generate symbolic expressions of the impedance parameters and, thus, those of the scattering parameters. The Simulated Annealing optimization technique is applied to determine the optimal sizing of the LNA. ADS simulation results are given to show the viability of the proposed approach.

INTRODUCTION Low Noise Amplifiers (LNAs) compose a decisive building block in any radio-frequency front-end (Razavi, 1998). According to (Friis, 1944), when using a LNA, the noise effect of all the receiver’s subsequent stages is reduced by the gain of the LNA which noise is directly injected into the received signal. Accordingly, it is compulsory for a LNA to boost the desired signal power while adding as little noise DOI: 10.4018/978-1-60566-886-4.ch004

Copyright © 2012, IGI Global. Copying or distributing in print or electronic forms without written permission of IGI Global is prohibited.

Design of Low Noise Amplifiers through Flow-Graphs and their Optimization

and distortion as possible, so that the retrieval of the useful signal is possible in the following stages. The design task of such high performance circuit is tedious and time consuming. Besides, it generally relies on the designer’s experience. CAD tools can considerably reduce this design time. However, a tool customized for the design of such circuits is not so far available. Some published works have tried to contribute in this field (see for instance (Tulunay, & Balkir, 2005; Cheung, & Wong, 2006; Tulunay, & Balkir, 2004; Nguyen, Kim, Ihm, Yang, & Lee, 2004)). Main contributions have been proposed by (Tulunay, & Balkir, 2004) and (Tulunay, & Balkir, 2005). In (Tulunay, & Balkir, 2005), the modified nodal analysis (MNA) (Ho, Ruehli, & Brennan, 1975) was used for the generation and resolution of the circuit matrix equations. In (Tulunay, & Balkir, 2004), an equation based optimization methodology was proposed. It is also based on the use of the simulated annealing heuristic. Besides, the multi-objective multi-constrains problem is transformed into a monoobjective unconstrained one. Scattering parameters are decisive parameters in the design of LNA’s since they reflect the power gain and the input and output matching of the circuit. This chapter deals with optimizing the scattering parameters via the LNA’s impedances, which symbolic expressions are computed automatically using a graph approach, namely, the Coates flow-graph technique (Coates, 1959; Starzyk, & Konczykowska, 1986). Afterwards, the simulated annealing optimization technique, which is a generic probabilistic metaheuristics that is widely adopted for solving global optimization problems, is used to solve such NP-hard problem. i.e. generating the design variables’ optimal values that satisfy constraints imposed on the performances’ metrics (such as noise figure), and maximize objective functions (such as gain).

A BRIEF OVERVIEW ON THE SCATTERING PARAMETERS The definition of the Scattering Parameters, noticed S-Parameters, is based on the theory of the incident and reflected waves (Kurokawa, 1965; Kurokawa, 1969). Thus, S-parameters describe the relationship between the different waves of a system. Figure 1 represents a network with two ports including the incident and reflected microwaves. With (Scott, 1993): • •

a1: the electric field of the microwave signal entering the network input, b1: the electric field of the microwave signal leaving the network input,

Figure 1. A two-port network with incident and reflected waves

70

Design of Low Noise Amplifiers through Flow-Graphs and their Optimization

• •

b2: the electric field of the microwave signal leaving the network output, a2: the electric field of the microwave signal entering the network output. Therefore, the S-parameters are defined by expressions (1)-(4):

S11 =

S 21 =

S12 =

S 22 =

b1 a1 b2 a1

a 2 =0

b1 a2

a1 =0

b2 a2

(1)

(2)

(3)

(4)

a2 =0

a1 =0

Consequently, S-parameters are reflection or transmission coefficients which are defined as follows (Rogers, & Plett, 2003): • • • •

S11 is the input reflection coefficient, S21 is the forward transmission coefficient, S12 is the reverse transmission coefficient, S22 is the output reflection coefficient.

The measurement of the S-parameters depends on the value of the termination impedance. Generally, this impedance is equal to 50Ω because the coax cable exhibits a minimum loss insertion at this impedance (Ellinger, 2007). In addition to S-parameters, there are many parameters which characterize a network. The Z-parameters and the Y-parameters can be mentioned and they represent respectively the impedance and the admittance parameters. These parameters are measured in function of the voltage and current of the network. The expressions (5) and (6) represent these parameters for two-port network (Rogers, & Plett, 2003): v1  Z 11 Z 12  i1   =   v 2  Z 21 Z 22  i2      

(5)

i1  Y11 Y12  v1   =   i2  Y21 Y22  v 2      

(6)

71

Design of Low Noise Amplifiers through Flow-Graphs and their Optimization

where: • • •

v1 and v2 represent respectively the voltage in port 1 and in port 2, i1 and i2 represent respectively the current in port 1 and in port 2, Zij and Yij represent respectively the impedance and the admittance in each port.

In (Rogers, & Plett, 2003; Ellinger, 2007) conversion relationships between Z-parameters and Sparameters were proposed, they are reported in Tables 1 and 2. with: •

∆Z = (Z 11 + Z 0 ) (Z 22 + Z 0 ) − Z 12 Z 21 ,

• •

Z 0 represents the termination impedance which is equal to 50Ω, The symbol “ ” means that the parameter is a complex number.

THE SYMBOLIC APPROACH Electronic circuits are composed of active and passive components. They form nodes and loops (Gielen, & Sansen, 1991; Breuer, Sarrafzadeh, & Spmenzi, 2000). On the base of KCL and KVL (Kirchoff Current and Voltage Laws) transfer functions (TFs) are computed. Generally obtained system is written in the matrix form: A.X = B

(7)

where A=[aij]nxn is the coefficient matrix, XT=[x1, x2, …, xn] and BT=[b1, b2, …, bn]; the input vector. If the coefficient matrix is non singular, the solution of the above matrix system can be written as follows: xk =

∑b ∆ i

ik

det (A)

Table 1. Conversion table from Z-parameters to S-parameters

72

(8)

Design of Low Noise Amplifiers through Flow-Graphs and their Optimization

Table 2. Conversion table from S-parameters to Z-parameters

where ∆ik denotes the correspondent cofactor. However, this representation is not suitable for automating the design. Representing the circuit by a graph is of a very high importance. It is an intuitive representation that can allow automating the approach. Unlike already published works proposing symbolic analyzers, see for instance (Tlelo-Cuautle, Quintanar-Ramos, Gutiérrez-Pérez, & González-de-la-Rosa, 2004; Martins, & Gielen, 2008; Biolek, 2000; Tlelo-Cuautle, & Sánchez-López, 2004), the proposed approach consists of developing an analyzer, which is based on the use of the (directed) graph approach, to automatically compute transfer functions (TFs). In the following we detail the adopted approach and present the first module of the symbolic analyser. Two other modules are now under construction: • •

A semi-symbolic/simulation module, and An optimization module based on the use of an evolutionary algorithm and associated to a simulation based one (Guerra-Gómez, Tlelo-Cuautle, Li, & Gielen, 2008) to remedy to non-precise adopted models (transistors).

Actually, diagrams and graphs are an intuitive and very useful representations used in modeling systems in engineering problems. The directed graph, or di-graph, approach can be used when analysing engineering problems and particularly linear ones. Indeed, since the associated graph can be, in many cases, generated directly by inspection of the treated system without any need of formulating mathematical equations, these approaches seems to be of great interest. From the first representation of graphs introduced to solve the königsberg Bridge problem, graph theory has evolved and now is used in a lot of engineering fields (Diestel, 2000.). Graphs are formed by vertices, trees and paths. In our field of interest, i.e. in the electrical field, we focus on studying sub graphs and especially spanning ones. Since an electrical circuit must be a spanning sub graph, i.e. which must contain all vertices of the treated graph. Connectivity is also studied when studying electrical networks because there have to exist a path between any two vertices in the graph. Besides particular forms of directed trees have to be determined when we have to calculate the transfer function between two given vertices: the input node and a chosen output one.

73

Design of Low Noise Amplifiers through Flow-Graphs and their Optimization

The directed graph approach is of a particular interest in the analysis of electrical network problems, since the associated directed graph can be directly given by simple inspection of the circuit with out any necessity of formulating mathematical equations. The basic idea of associating graphs and directed graphs with an electrical system was introduced by Mason (Mason, 1953). It gives a way to associate a directed graph with a given matrix, which is known as signal flow graph. In our work we focus on using such approaches for analyzing analog circuits. The transfer function representation given by expression (7) is not adequate for automating the computation of the TF (Ismail, & Franca, 1990). To the above matrix system we associate a directed graph. A useful link between a determinant of a matrix and its corresponding graph is obtained by referring to the definition of a determinant: det(A) = ∑ αi 1 i 2 ... inai 1ai 2 ...ain

(9)

i

Since αi 1 i 2 ... inai 1ai 2 ...ain represent, in reality, all possible combinations between the graph edges. We can so get all loops present in the graph. Also, and by mean of the same approach, the permanent of the modified matrix A• obtained from the adjacency matrix A by adding the vector B to the left side of A ' and by adding a row of zeros at the top of this matrix and force the element aαβ to 1 ( α and β refer to input and output vertex number). Rearranging the ratio of the obtained expressions leads to have the TF between α and β nodes. In fact, the determinant formula can be expressed as given in (10). det(A) = (−1)

n

∑ (−1)

yy

f (x )

(10)

x

where yy denotes the number of directed circuits in the sub-graph. In addition, we notice that for the given matrix we calculate the permanent of this matrix to verify connectivity of the graph. Thus the treated netlist is checked before any calculus. per (A) = ∑ ai 1ai 2 ...ain

(11)

(i )

Moreover, we notice that cofactors ∆ij of the (i,j) element of matrix A can be calculated as given in (12) and (13). ∆ii = (−1)

n −1

∑ (−1)

y

f (x )

(12)

x

∆ij = (−1)

n −1

y

∑ (−1) f (X ) X

where ∆ij is the cofactor of the (i,j) element of A. X and x denote connections in the graph.

74

(13)

Design of Low Noise Amplifiers through Flow-Graphs and their Optimization

Expression (13) allows us computing the corresponding determinant, for a non singular matrix A, known as the 1-factor: ll

det(A) = ∑ (−1) f (ll )

(14)

ll

We also prove that: n

∑b ∆ i

il

=

i =1

L

∑

X (n +1)

(−1) f (X (n +1)l )

(15)

Expression (15) is known as the 1-factorial connection. Finally, combining expressions (8) and (9) lead to expression (16):

xl =

∑

L

X (n +1)

(−1) f (X (n +1)l ) ll

∑ (−1) f (ll )

(16)

ll

It is important to notice that the numerator and the denominator are calculated separately. The block diagram of the developed tool can be depicted as shown in Figure 2, where s is Laplace operator and x refers to circuit’s parameters.

THE SIMULATED ANNEALING OPTIMIZATION TECHNIQUE Analogue circuit design is a complex and delicate process, because it is related not only to the placement and the routing of the components, but also to their sizing. Generally, the analog circuit sizing is a slow, tiresome and iterative process, and carried out by experiment and intuition of the designer. Optimizing the sizes of the analog components automatically is an important issue towards a rapid design of high performance circuits (Toumazou & Lidgey, 1993). The best-known approaches in literature are based on fixed topologies and/or statistical techniques (Medeiro, Rodríguez-Macías, Fernández, Domínguez-Astro, Huertas, & Rodríguez-Vázquez, 1994). They are generally initialized with a ‘good’ solution (a DC quiescent point) provided by a skilled analogue designer. These methods then seek to improve the solution by different techniques such as simulationbased tuning procedures. The problem with these methods is that they are often very slow and they don’t guarantee convergence to a global optimum. The use of new methods is required. Heuristics are available for solving NP-hard optimization problems. Among these heuristics, some are adaptable to many different problems. They are called metaheuristics. Their ability to solve a problem from a minimum of information is balanced by the fact that they offer no guarantee about the optimality of the best solution found. Only an approximation of the global optimum is given. These methods generate new points in

75

Design of Low Noise Amplifiers through Flow-Graphs and their Optimization

Figure 2. Flowchart of the symbolic tool architecture

76

Design of Low Noise Amplifiers through Flow-Graphs and their Optimization

the search space by applying operators to current points and statistically moving toward more optimal places in the search space. In the literature, there are two main types of metaheuristics: •

•

Global search approaches: Known as evolutionary algorithms, they use the concept of biological evolution to solve problems, such as Genetic Algorithms (GA) (Holland, 1975), Evolutionary Computation (EC) (Schwefel, 1995), Ant Colony Optimization (ACO) (Dorigo, Dicaro, & Gambardella, 1999), Particle Swarm Optimization (PSO) (Kennedy, & Eberhart, 1995)… Local search approaches: they are suitable for complicated problems where the global optimum is hidden among many local optima. Some of these methods include Simulated Annealing (SA) (Kirkpatrick, Gelatt, & Vecchi, 1983), Tabu Search (TS) (Glover, 1989)…

Each major type of metaheuristic has a number of parameters that must be set before executing the algorithm. Table 3 summarizes the basic parameters of a selection of the most known metaheuristics. Generally, the performance analysis of algorithms concentrates on the following two quantities: • •

The quality of the final solution obtained by the algorithm (the difference between the final solution and a globally minimal configuration); The running time required by the algorithm.

In order to overcome these requirements, a set of physical process inspired heuristic optimization algorithms was proposed. It is known as Simulated Annealing techniques. This method, a heuristic local search algorithm, is effective in network reconfiguration problems for large-scale distribution systems (Clements, Crawford, Joslin, Nemhauser, Puttlitz & Savelsbergh, 1997), and its search capability becomes more significant as the system size increases. Moreover, the cost function with a smoothing strategy enables the simulated annealing to escape more easily from local minima, and to reach rapidly to the Table 3. Popular metaheuristics and their standard parameters

77

Design of Low Noise Amplifiers through Flow-Graphs and their Optimization

vicinity of an optimal solution (Kwang, & El-Sharkawi, 2008). In this chapter, we focus on the use of SA for the optimal design of LNAs. SA was introduced by (Kirkpatrick, Gelatt, & Vecchi 1983). This technique simulates the annealing process in which a solid in a heat bath is heated above its melting temperature, and then progressively the temperature is lowered slowly to produce the crystalline lattice, which reduces its energy probability distribution. This crystalline lattice is an attractive example of nature finding an optimal configuration (Haupt, & Haupt 2004). In a large combinatorial optimization problem, an appropriate perturbation method, cost function, solution space, and cooling schedule are required in order to find an optimal solution with SA. Generally, SA exploits the Metropolis Algorithm (Metropolis, Rosenbluth, Teller, & Teller, 1953) which provides the criterion for acceptance of a solution, say x’ constructed by disrupting the current solution x. This process gives the possibility of moving away occasionally of a local minimum to allow a widening of the research field of the ideal solution. There are several distinct steps that the SA process has to go through as the temperature is condensed and randomness is applied to the input values. Figure 3 presents a flowchart of this method. The SA algorithm can be summarized as follows. • • • •

Step 1: The SA process starts with a random guess of the cost function variable values(x). Step 2: A small random change is made in the current solution (x’). Step 3: The objective function value of the new solution is evaluated and compared with that of the current solution, ie.., Δf (x) = f(x’) – f(x). Step 4: Acceptance with the criterion of Metropolis: A move is made to the new solution if it has a better value or if the probability function implemented in SA has a higher value than a randomly generated number. Otherwise, a new solution is generated and evaluated. The probability of accepting a new solution is given by the following functions:

p = 1   −∆f   p = exp   T  

if if

∆f ≤ 0 ∆f > 0

(17)

T represents the temperature parameter. According to expression (17), the calculation of this probability relies on the temperature parameter, which has an influence on the convergence of the SA algorithm. To avoid getting trapped at a local minimum, the rate of reduction should be slow. Many different cooling schedules are possible. If the initial temperature is T0 and the ending temperature is TN and Tn the temperature at step n, some potential cooling schedules are as follows (Haupt & Haupt 2004): Linearly decreasing: Tn = To −

n.(T0 − Tn ) N

Geometrically decreasing: Tn = αTn-1

78

(18) (19)

Design of Low Noise Amplifiers through Flow-Graphs and their Optimization

Figure 3. Flowchart of the SA algorithm

Hayjek optimal: Tn =

β log(1 + n )

(20)

where α is a constant in the interval [0, 1] and β is the smallest variation required to get out of any local minimum. In the LNA optimization problem, the geometrically decreasing method to reduce the temperature has been used. The temperature is usually lowered slowly so that the algorithm has a chance to find the correct valley before trying to get to the lowest point in the valley. The algorithm may be terminated after a certain volume fraction when the structure has been reached, or after a pre-specified run time. Implemented in MATLAB, the pseudo- code of the SA algorithm is as follows in Figure 4. Knowing that an optimization problem has the form given by expression (21), and that classical SA cannot handle inequality constraints, the constrained problem is transformed using the penalty trick.

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Design of Low Noise Amplifiers through Flow-Graphs and their Optimization

Figure 4. The SA pseudo code

    Thus, the objective function f (x ) is transformed to F (x ) , as shown in expression (22). (Turkkan, 2003; Eiben, & Smith, 2003)   Minimize f (x )

(21)

  Subject to: g (x ) ≤ 0   and: h (x ) = 0         F (x ) = f (x ) + P .(max(0, g (x ))2 + h (x )2 )

(22)

     k m n l   where f (x ) ∈ R , g(x ) ∈ R , h(x ) ∈ R , x ∈ R . k, m, n and l denote numbers of objectives, inequality constraints, equality constraints and parameters, respectively. P is the penalty coefficient.

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Design of Low Noise Amplifiers through Flow-Graphs and their Optimization

OPTIMIZING LOW NOISE AMPLIFIERS In the following we present an example of application of the proposed approach. A common source structure with an inductive degeneration LNA, which is presented in Figure 5 is optimized for an UMTS application. The common gate transistor M2 improves the stability of the circuit by minimizing the feedback from the output to the input (Razavi, 1998). The input matching is realized thanks to inductors (LS) and (Lg) and the parasitic gate to source capacitor Cgs of transistor M1 as well. The output matching is achieved by the LC circuit (Lch,Cch) and the equivalent output impedance of transistors M1 and M2. The sub-circuit formed by transistor M3 and resistors R1 and R2 ensures biasing the LNA. The main problem consists of optimizing the sizing of all the components comprising the LNA to meet imposed specifications, such as impedance matching, maximum noise figure level, etc. (see Table 4), while satisfying inherent constraints, such as saturation conditions of MOS transistors. The symbolic approach was used to automatically compute Z-impedances and then S-parameters. We notice that the noise figure expression was taken from (Andreani, & Sjoland, 2001). In Figure 6 we present the flow-graph corresponding Figure 5. A single band LNA

Table 4. The LNA Specifications

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Design of Low Noise Amplifiers through Flow-Graphs and their Optimization

Figure 6. The equivalent flow-graph

to the considered LNA. Node X refers to the input current source. It is applied at node 1 when impedances Z11 and Z21 have to be computed, and it is applied at node 6 to compute impedances Z22 and Z12. it is to be highlighted that Figure 6 is presented just to depict the adopted approach. Actually, the graph is not drawn, but the corresponding theory is programmed using MATLAB software (Fakhfakh, M., & Loulou, M. 2008). Thanks to the symbolic analyzer, symbolic expressions of impedances Zij were automatically computed. Sij expressions were derived from these expressions. Due to their large number of terms, expressions of Zij are not given. SA was used to solve the LNA optimization problem. Figure 7 illustrates evolution of the S21 parameter versus the temperature stages. Table 5 presents the optimal values of the parameters obtained by the SA method corresponding to a supply voltage equals to 2.5V. Table 6 presents the optimal values of the parameters obtained by the SA according to the algorithm parameters given in table 5. The technology under consideration is CMOS AMS 0.35 µm, voltage supply specification is 0V/+2.5V. Table 7 gives a comparison between theoretical (SA) and simulation (ADS) obtained results. It is to be highlighted that differences between the theoretical and the simulation results are mainly due to the substrate effect and to the parasitic elements that were not taken into consideration in the circuit model. Figures 8-10 show the good agreement between ADS simulation results and the theoretical ones (MATLAB) obtained by applying SA. Imposed and inherent constraints are satisfied, for instance, Figure 11 shows that NF at the considered frequency satisfies the specifications given in table 4.

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Design of Low Noise Amplifiers through Flow-Graphs and their Optimization

Figure 7. S21 vs. temperature stages

Table 5. The SA algorithm parameters

Table 6. Parameters values of optimal solution

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Design of Low Noise Amplifiers through Flow-Graphs and their Optimization

Table 7. Theoretical and simulation results at 2.140GHz

Figure 8. S11 (a:ADS, b:MATLAB)

Figure 9. S21 (a:ADS, b:MATLAB)

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Design of Low Noise Amplifiers through Flow-Graphs and their Optimization

Figure 10. S22 (a:ADS, b:MATLAB)

Figure 11. Noise Figure

CONCLUSION In this chapter we presented an approach for the optimal design of LNAs. It is based on the automatic computation of the symbolic expressions of the scattering parameters using a Coates digraph-based symbolic analyzer. The graph approach was detailed. The simulated annealing heuristic was used to compute optimal values of elements forming the LNA that satisfies inherent and imposed constraints, and maximizes the objective functions. Theoretical and simulation results were given to show the viability of the proposed approach and the good agreement between both results.

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Design of Low Noise Amplifiers through Flow-Graphs and their Optimization

REFERENCES Andreani, P., & Sjoland, H. (2001). Noise optimization of an inductively degenerated CMOS low noise amplifier. IEEE Transactions on Circuits and Systems, 9(42), 835–841. Biolek, D. (2000). SNAP-Program with symbolic core for educational purposes. In Mastorakis, N. (Ed.), Systems and Control: Theory and Application (pp. 195–198). World Scientific, Electrical and Computer Engineering Series. Breuer, M. A., Sarrafzadeh, M., & Spmenzi, F. (2000). Fundamental CAD algorithms. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 12(19), 1449–1475. doi:10.1109/43.898826 Cheung, W. T., & Wong, N. (2006). Optimized RF CMOS low noise amplifier design via geometric programming, The IEEE International Symposium on Intelligent Signal Processing and Communication Systems. Clements, D. P., Crawford, J. M., Joslin, D. E., Nemhauser, G. L., Puttlitz, M. E., & Savelsbergh, M. W. P. (1997). Heuristic Optimization: A hybrid AI/OR approach. Workshop on Industrial ConstraintDirected Scheduling. Coates, C. L. (1959). Flow-graph solutions of linear algebraic equations. Institute of Radio Engineers, Transactions on circuit theory, (CT-6), 170-187. Diestel, R. (2000). Graph theory. Springer Verlag. Dorigo, M., Dicaro, G., & Gambardella, L. M. (1999). Ant algorithms for discrete optimization. Artificial Life Journal, 5, 137–172. doi:10.1162/106454699568728 Eiben, A. E., & Smith, J. E. (2003). Introduction to evolutionary computing. Springer. Ellinger, F. (2007). Radio frequency integrated circuits and technologies. Springer-Verlag. Fakhfakh, M., & Loulou, M. (2008). A Software for the Automated Computing of Symbolic Transfer Functions of Analog Circuits. The International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design. Friis, H. T. (1944). Noise figures of radio receivers. Institute of Radio Engineers, 32, 419–422. Gielen, G., & Sansen, W. (1991). Symbolic analysis for automated design of analog integrated circuits. Kluwer Academic Publishers. Glover, F. (1989). Tabu search- part I. ORSA Journal on Computing, 3(1), 190-206. Guerra-Gómez, I., Tlelo-Cuautle, E., Li, P., & Gielen, G. (2008). Simulation-based optimization of UGCs performances. IEEE International Caribbean Conference on Devices, Circuits and Systems. Haupt, R. L., & Haupt, S. E. (2004). Practical genetic algorithms. John Wiley & Sons. Ho, C. W., Ruehli, A. E., & Brennan, P. A. (1975). The modified nodal approach to network analysis. IEEE Transactions on Circuits and Systems, 6(22), 504–509. Holland, J. H. (1975). Adaptation in natural and artificial systems. University of Michigan Press.

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Ismail, M., & Franca, J. (1990). Introduction to analog VLSI design automation. Kluwer Academic Publishers. Kennedy, J., & Eberhart, R. C. (1995). Particle swarm optimization. IEEE International Conference On Neural Networks. Kirkpatrick, S., Gelatt, C. D., & Vecchi, M. P. (1983). Optimization by simulated annealing. Journal of Science, 220, 671–680. doi:10.1126/science.220.4598.671 Kurokawa, K. (1965). Power waves and the scattering matrix. IEEE Transactions on Microwave Theory and Techniques, 2(13), 194–202. doi:10.1109/TMTT.1965.1125964 Kurokawa, K. (1969). An introduction to the theory of microwave circuits. Academic Press. Kwang, Y. L., & El-Sharkawi, M. A. (2008). Modern heuristic optimization techniques: theory and applications to power systems. John Wiley & Sons. Martins, E., & Gielen, G. (2008). Classification of analog synthesis tools based on their architecture selection mechanisms, Integration, the VLSI journal, 41, 238-252. Mason, S. J. (1953). Feedback theory-some properties of signal flow graphs. Institute of Radio Engineers, 9(41), 1144–1156. Medeiro, F., Rodríguez-Macías, R., Fernández, F. V., Domínguez-Astro, R., Huertas, J. L., & RodríguezVázquez, A. (1994). Global design of analog cells using statistical optimization techniques. Analog Integrated Circuits and Signal Processing, 3(6), 179–195. doi:10.1007/BF01238887 Metropolis, N., Rosenbluth, A., Rosenbluth, M., Teller, A., & Teller, E. (1953). Equation of state calculations by fast computing machines. The Journal of Chemical Physics, 6(21), 1087–1092. doi:10.1063/1.1699114 Nguyen, T. K., Kim, C. H., Ihm, G. J., Yang, M. S., & Lee, S. G. (2004). CMOS low-noise amplifier design optimization techniques. IEEE Transactions on Microwave Theory and Techniques, 5(52), 185–188. Razavi, B. (1998). RF microelectronics. Prentice Hall Press. Rogers, J., & Plett, C. (2003). Radio frequency integrated circuit design. Norwood, MA: Artech House. Schwefel, H. (1995). Evolution and optimum seeking. Wiley. Scott, A. W. (1993). Understanding microwaves. John Wiley & Sons. Starzyk, J. A., & Konczykowska, A. (1986). Flowgraph analysis of large electronic networks. IEEE Transactions on Circuits and Systems, 3(33), 302–315. doi:10.1109/TCS.1986.1085914 Tlelo-Cuautle, E., Quintanar-Ramos, A., Gutiérrez-Pérez, G., & González-de-la-Rosa, M. (2004). SIASCA: Interactive system for the symbolic analysis of analog circuits. IEICE Electronics Express, 1(1), 19–23. doi:10.1587/elex.1.19 Tlelo-Cuautle, E., & Sánchez-López, C. (2004). Symbolic computation of NF of transistor circuits. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 9(E87A), 2420-2425.

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Toumazou, C., Lidgey, F. J., & Haigh, D. G. (1993). Analog integrated circuits: the current mode approach. IEEE circuit and systems series. Tulunay, G., & Balkir, S. (2004). A compact optimization methodology for single ended LNA. The IEEE International Symposium on Circuits and Systems. Tulunay, G., & Balkir, S. (2005). Design automation of single-ended LNAs using symbolic analysis. The IEEE International Symposium on Circuits and Systems. Turkkan, N. (2003). Discrete optimization of structures using a floating-point genetic algorithm. Annual Conference of the Canadian Society for Civil Engineering.

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Chapter 5

Optimization of CMOS Quadrature VCO Using a Graphical Method Hassene Mnif University of Sfax, Tunisia Dorra Mellouli University of Sfax, Tunisia Mourad Loulou University of Sfax, Tunisia

ABSTRACT This chapter describes the design and the optimization of Quadrature Voltage Controlled Oscillators (QVCOs) based on the coupling of two LC-tank VCO. This work covers the phase noise analysis, a graphical optimization approach, already used to optimize LC oscillator phase noise (Andreani, Bonfanti, Romano, & Samori, 2002), to optimize QVCO phase noise while satisfying design constraints such as power dissipation, tank amplitude, tuning range and start up condition. The cross-coupling transistors impact on phase noise for different configurations is especially addressed. The obtained BS-QVCO, using 0.35µm CMOS process, can be tuned between 2.2GHz and 2.58GHz, and shows a phase noise of -129 dBc/Hz at 1MHz offset from a 2.4 GHz carrier, for a current consumption of 9.25mW. The equivalent phase error and amplitude error between I and Q signals are respectively 0.65° and 1.87%.

INTRODUCTION One of the largest growth areas in Radio-Frequency over the past decade has been in the application of mobile communication system, and it’s ever growing demand has caused renewed interest and generated more attention towards wireless architectures and applications. Mobile phones and radios, operating in several modes, are typically switch between receiving and transmitting frequencies, and therefore, require low phase noise signal sources (oscillators) in each of the switch band. DOI: 10.4018/978-1-60566-886-4.ch005

Copyright © 2012, IGI Global. Copying or distributing in print or electronic forms without written permission of IGI Global is prohibited.

Optimization of CMOS Quadrature VCO Using a Graphical Method

Quadrature voltage controlled oscillators (QVCOs) are so essential building blocks of modern RF transceivers architectures. The QVCO performance in terms of tuning range, power dissipation, and phase noise determines many of the basic performance characteristics of a transceiver. This chapter investigates an effective method to optimize the phase noise of the oscillator by visualizing the design constraints graphically. This approach of optimization is already used to optimize the phase noise of an oscillator LC (Ming-Chun & Chia-Wei, 2002), in this case it will be used to optimize a quadrature oscillator QVCO. This chapter is organized as follows: after the introduction, we describe the QVCO circuit with different configurations; then we present the optimization approach and we investigate the graphic optimization strategy for the two quadrature oscillators P-QVCO and BS-QVCO respectively followed by the simulation results. Finally, we give some concluding remarks.

QUADRATURE OSCILLATORS In low-IF or Zero-IF transceivers, quadrature signals (0° and 90°) are needed for I/Q (modulation / demodulation). It is important to offer quadrature generation at a minimal phase noise and power consumption. A way for obtaining quadrature signals is through the use of a VCO design enabling to deliver such signals. In principal, a ring oscillator fulfills this requirement, however its notorious high phase noise disqualifies this choice for most application in modern radio transceivers (Andreani & Bonfanti, 2002). A more attractive approach to direct quadrature synthesis relies on the possibility of coupling two symmetric LC-tank VCOs to each other, thereby exploiting the good phase performance of LC-oscillator (Tiebout, 2001, pp. 1018-1024). As exemplified by the block schematic in Figure 1, the combination of a direct connection and a cross connection forces the two VCOs to oscillate in quadrature. The original QVCO based on the cross-coupling transistors Mcpl placed in parallel with the switch transistors Msw (Rofougaran & Rael, 1996, pp.135-136) (Figure 2-a), was known to have a poor phasenoise behavior. This QVCO design will be referred as the parallel QVCO (P-QVCO). To improve overall performance we will place Mcpl in series with Msw, rather than in parallel (Figure 2-b). This choice is motivated by the fact that Mcpl in the P-QVCO is responsible for a large contribution to the phase noise, and placing Mcpl in series with Msw, should greatly reduce the noise from the cascade device. Since, in this case Mcpl is placed at the bottom of Msw. This is the bottom series QVCO (BS-QVCO). The architecture of each LC-VCO is a cross-coupled structure with NMOS and PMOS transistors. The inductance-capacitance (LC) resonant circuit comprises an inductor and a differentially tuned varacFigure 1. Block schematic and signal phases for a QVCO

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Optimization of CMOS Quadrature VCO Using a Graphical Method

tor. The tail current source is a simple NMOS current mirror. The resonant circuit and the cross-coupled complementary N-PMOS pair are fully differential to reduce the sensitivity to power supply variations and substrate interferences and noise. The oscillation frequency f0 is controlled by the LC-tank and can be expressed by: f = 0

1 2π L (C var +Cpar )

(1)

Where L is the inductance, Cvar is the varactor capacitance and Cpar is the parasitic capacitances of the transistors and the varactors.

QVCO DESIGN STRATEGY Optimization Approach In this section, we will detail the adopted optimization methodology which is based on the following steps: • • • • • •

Specifications definition QVCO model determination taking into account the coupling transistors; System constraints and performance functions formulation; Bias condition and phase noise determination; Graphical optimization method applying And performance verification based on simulation results.

Figure 2. Conventional QVCO schematic: (a) P-QVCO; (b) BS-QVCO

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Optimization of CMOS Quadrature VCO Using a Graphical Method

The optimization approach is based on a graphic method allowing the visualization of the different design constraints. It is described as follows: •

•

Firstly, we use three dimensional phase noise analysis, this analysis diagram comprises an (X-Y) plane, which describes the tank amplitude (Vtank) and the tank current (Itank), and a Z-axis corresponding to phase noise prediction. This analysis allows to determine the bias current and to pick an initial guess of the phase noise. Secondly, the process of optimization is performed through the minimization of phase noise while satisfying all different design constraints such as startup condition, tank amplitude and frequency tuning range. This graphical representation corresponds to the design constraints plot in the (Wn, Cvmax) plane suing the selected bias current, where Wn represents the active transistors width and Cvmax the maximum varactor capacitance.

The design constraints formulations must be represented in the (Wn, Cvmax) plane. If there are more than one feasible design points in this plane, we proceed to decrease the bias current and repeat until the feasible region shrinks to one point. The single point in the (Wn, Cvmax) plane represents the optimal value of Wn and Cvmax. In the following sections, we will analyze step by step the process of modelization and optimization of the QVCO topology.

Inductor Model The equivalent model of an integrated inductor, called a symmetric model, is illustrated by the Figure 3-a. It is an analytical model used for the graphical optimization. In this model, the effective parallel equivalent conductance of the inductor, gL, is given by: gL =

RS 1 + R p (ω L s ) 2

Figure 3. Inductor model: (a) Symmetric; (b) Asymmetric

92

(2)

Optimization of CMOS Quadrature VCO Using a Graphical Method

where Rp, Rs and Ls are the parasitical elements of the inductance. The model shown in Figure 3-b is more accurate and is used in simulation. This model, called asymmetric model, was developed using ASITIC optimizers to address the physical asymmetry of the spiral structure mainly due to the metal underpass (Niknejad, 1998).

Varactor Model The varactor used is based on PMOS transistors in accumulation mode with the drain and source connected together. The varactor capacitance varies from a minimum value Cv,min to a maximum value Cv,max. The ratio Cv,max/Cv,min is limited due to physical limitations of the varactor and is determined by simulation. We modelize the varactor as an ideal capacitance in series with a resistor Rsv. The effective parallel equivalent varactor conductance, gv, is given by: g = V

Cω 1 = v Rsv Qv

(3)

Transistor Model We describe an analytical model for the transistor, very useful for the graphical optimization and visualization of design constraints. Transconductance gm: a simple model for the transconductance of short-channel devices is given (Lee, 1998) by:

g

m

= µC WE /2 ox sat

(4)

where µ is the mobility, Cox is the oxide capacitance; Esat is the field at which the carrier velocity reaches half its saturation velocity and W is the transistor width. Output conductance gd: the model of the output conductance of short-channel devices with (Hershenson & Boyd, 1998) is given by:

g = λI 0, 6lc -1W 0, 4 d

(5)

where I is the transistor drain current, lc is the transistor channel length and λ is a fitting parameter. Capacitances: the gate-to-drain (Cgd) capacitance and the gate-to-source (Cgs) capacitance are given respectively by the following expressions (Hershenson & Boyd, 1998): C gd = WLdC ox

(6)

2  C gs =  lcanal + L WC d ox  3

(7)

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Optimization of CMOS Quadrature VCO Using a Graphical Method

Tank Model The QVCO model is illustrated in Figure 4 taking into account the coupling transistors for the two configurations (P-QVCO and BS-QVCO). The dashed line presents the effective AC ground for differential operation. The main tank parameters are defined in Table 1 for both the P-QVCO and the BS-QVCO.

Figure 4. Quadrature oscillator models: (a) P-QVCO configuration; (b) BS-QVCO configuration

Table 1. Tank parameters formulation P-QVCO Tank inductance

L

Tank capacitance

C tank =

Tank conductance

g

Tank negative effective conductance

g

tank

tank

BS-QVCO

= 2L 1 2

=

(4C 1 2

neg, tank

(8)

gd,n + 2Cgs,n + 4Cgd,p +Cgs,p +C L +C V +C load

)

C tank =

1 2

(4C

gd,n + Cgs,n + 4Cgd,p + Cgs,p + CL + C V + Cload

1  gd ,n

  +gd , p +gv +gL   2 2

(2gd,n +gd ,p +gv +gL )

g

 2gmn +gmp   = -  

 gmn   +gmp   2   g = -   2 neg, tank   



2



tank

=

* gmn and gmp present respectively the transconductance of the NMOS and PMOS transistors.

94

)

(9)

(10) (11)

Optimization of CMOS Quadrature VCO Using a Graphical Method

Phase Noise Predict Han & Chi (2000) establish an equation describing the quantitative phase noise model of a QVCO oscillator: 2

4FkTR  ω0  L(ω) =   Vtank 2  2Q ∆ω 

(12)

Where F= 8γRI bias 8 2+ + γg m R + 9 πVtank   π ϕ   tg  +    4 2    4γαKR 2 cos ϕ + 2 sin ϕ − sin(2ϕ) ln   ϕ   π 1 + α2   tg     2    

(13)

 α  W  and α = cp With ϕ = arcsin   1 + α2  Wsw k is the Boltzmann constant, T is the temperature, R is the resistance, Vtank is the oscillation amplitude, ω0 is the oscillation frequency, Q is the quality factor, Δω is the offset frequency from the carrier and Ibias is the bias current.

Design Constraints The main goal of optimization is to minimize the phase noise while satisfying all design constraints such as tank amplitude, startup condition, power dissipation, frequency tuning range and diameter of spiral inductors. •

The maximum power dissipation constraint is imposed by the limitation of the circuit bias current Imax thus:

Ibias ≤ Imax

(14)

In order to ensure a large enough voltage swing, the tank amplitude is required to be larger than Vtank,min: I bias = V V tank tank, min g tank

(15)

Where Vtank,min = 1.5V The oscillation tuning range is limited by two values depending of the center frequency ω0:

95

Optimization of CMOS Quadrature VCO Using a Graphical Method

L

L

1 C  2 tank tank ω max C tank tank



1 2 ω min

(16)

(17)

Where Ltank and Ctank denote the total tank inductor and capacitor respectively. The startup condition is fixed by: g active



σ

g min tank, max

(18)

Where σmin = 3 is the small-signal loop gain, gactive and gtank,max are the active and the tank conductance respectively. We define the maximum diameter for the spiral inductors: d d

max

(19)

Graphical Optimization The process of optimization consists on the representation of the design constraints in the variable plane; therefore we must first of all define the design variables.

Design Variables There are ten initial design variables associated with this specified oscillator: the geometric parameters of the on-chip spiral inductors, the MOS transistors dimensions (Wn, Wp, Ln and Lp) and the maximum and minimum values of the varactors (Cv,max and Cv,min). The number of these design variables can be reduced as follow: • • • •

First, the geometric parameters of the inductors are determined and optimized with ASITIC. Second, the channel length Ln and Lp are set to the minimum allowed by the process technology, thus, a symmetric active circuit is used which establishes a relation between Wn and Wp. Third, the ratio Cv,max/Cv,min is constant and determined by simulation. Therefore, the varactor introduces only one design variable. Finally we reduce the number for only two design variables, the transistors width Wn and the maximal varactor capacity Cv,max which will be referred to C. Consequently, the design constraints must be represented in the (Wn, C) plane.

BS-QVCO Optimization The formulations given by equations (15) to (18) will be expressed as functions of Wn and C variables as following: 96

Optimization of CMOS Quadrature VCO Using a Graphical Method

Tank amplitude 0.4    0.6   µ    I  Rs  Qv  2I 1  0.4  1 n    C ≤ −  λWn  +    + +  ω V 2  µp   Rp (Lω)2  l      tan k, min  canal 

(20)

Tuning range      µn   2 1  1   C ≤  2 − 1 +   lcanal + Ld C oxWn + 4C ox LdWn  + C p + C load + C s   βv  Lωmax  µp   3     1 C ≥ − 2 Lωmin      1 + µn   2 l   C L W C C C + + + + 4 + L C W   canal d ox n ox d n  p load s     µp   3   

(21)

(22)

Start-up condition 0.4    0.6   µ    I 0.4  1 Rs  Qv  3µC ox Esat 1  n      C ≤ Wn −  λWn  +    + + 2 ω  4σmin l  2  µp   Rp (Lω)    canal 

(23)

Divider regime 0.4    0.6   µ    I 0.4  1 Rs  Qv  2I 1  n    + C ≤ −  λWn  +    +  ω V 2  µp   Rp (Lω)2  l      sup ply  canal 

(24)

Bias Condition and Phase Noise Determination To start the optimization process, we begin with an initialization of the current bias. Figure 5 presents a three-dimensional presentation of the BS-QVCO phase noise. In this figure, the x-axis presents Ibias, the y-axis presents Vtank, and the z-axis the phase noise prediction. Therefore, the (x-y) plane describes the bias condition of this BS-QVCO and the z-axis corresponds to phase noise. Thus, we can select an initial bias condition which presents the minimum phase noise. The coordinate of this minimum is given by: • • •

Ibias = 4.375 mA Vtank = 2.49 V Phase noise L(ω) = -115.85 dBc/Hz

97

Optimization of CMOS Quadrature VCO Using a Graphical Method

Figure 5. Phase noise three-dimensional presentation

Optimization Process The design constraints given by (20) to (24) are visualized in Figure 6 in the (Wn, C) plane using the initial bias condition already determined. The line representing the limit of the tank amplitude is obtained using (20), the region below this line corresponds to the Vtank larger than 1.5 V. The tf1 and tf2 lines define the maximum and minimum frequency of the tuning, and are obtained respectively from (21) and (22). A tuning range of 15% with a center frequency of 2.4 GHz is obtained if a design point lies between the tf1 line and the tf2 line. The startup line is obtained from (23). To guarantee startup, the point must be located on the right-hand of the startup line for σmin = 3. The regime divider line presents the limit of the voltage-limited regime and the current-limited regime. The region with shadow in Figure 6 (a) satisfies all the design constraints and represents a set of feasible design points. The optimum point is defined by the intersection of the startup line and tf2 line since this point has the low parasitic capacitances. However we noticed that the optimum point is located in the voltage limited regime (below the regime divider) therefore, the design suffers from waste of power. Then, the bias current should be reduced until the optimum point will be located on the regime divider line. Figure 6 (b) shows the optimum design which Ibias=3.71 mA and no further action is necessary. We can notice that the tuning range constraint remains the same independently of the bias current. The startup constraint shows weak dependence on the bias current as the transconductances of the transistors. However, the regime divider and tank amplitude constraints show strong dependence on the bias current. The obtained optimum point is:

98

Optimization of CMOS Quadrature VCO Using a Graphical Method

Figure 6. Design constraints for: (a) Ibias = 4.375 mA ; (b) Ibias = 3.71 mA

• • •

Wn = 37 µm C=Cv,max = 1.42 pF Ibias = 3.71 mA These values give a tank amplitude value of 2.04V.

P-QVCO Optimization In this section, we apply the same method of optimization, using the same stages described before. The same specifications such as inductor, capacitor and transistors model will be used. Therefore the design constraints formulations will be expressed as a function of Wn and C variables using the P-QVCO model. Tank amplitude Q C ≤ v ω

0.4    0.6   µ    2I   Rs  2I 1  0.4  n     + −  λWn 1 +    +  V  µp   Rp (Lω)2  l    tan k, min  canal 

(25)

Tuning range  1     1 + µn   2 l   + + + − C W + 4 C L W C C C    ox n ox d n  p load s  Lω 2    canal    µ 3  max   p

C ≤

1 βv

C ≥

1 − 2 Lωmin

    1 + µn   2 l  4 C W + C L W C C C + + +   p load s ox n ox d n    µp   3 canal  

(26)

(27)

99

Optimization of CMOS Quadrature VCO Using a Graphical Method

Start-up condition 0 .4    0.6   µ    I 0.4  Rs  Qv  3µC ox Esat 1  n    + C ≤ Wn −  λWn 1 +    +   µp   Rp (Lω)2  ω  4σmin l        canal

(28)

Divider regime

C ≤

0.4    0.6   µ    2I 0.4  Qv  2I Rs  1  −  + λWn 1 +  n   +   µp   Rp (Lω )2  ω V l      sup ply  canal 

(29)

The optimum point for the P-QVCO is given by: • • •

Wn = 20 µm C=Cv,max = 1.6 pF Ibias = 3.85 mA These values give a tank amplitude value of 2.04V.

Simulation Results The verifications of the graphic optimization and the analytic equations made in the previous sections were performed using simulations. The performance evaluation of the two oscillators was carried out through ADS software simulations with an AMS CMOS 0.35µm technology. Simulations are carried out, using an asymmetric inductor model. The simulation results show that the obtained P-QVCO can be tuned between 2.2GHz and 2.58GHz, and shows a phase noise of -125 dBc/Hz at 1MHz offset from a 2.4 GHz carrier, for a current consumption of 3.85mA from a 2.5V power supply. The equivalent phase error and amplitude error between I and Q signals are respectively 1.32° and 2.5%. The BS-QVCO presents best performances with a phase noise of -129dBc/Hz at 1MHz offset from a 2.4 GHz carrier, for a current consumption of 3.7mA from a 2.5V power supply. The equivalent phase error and amplitude error between I and Q signals are respectively 0.65° and 1.87% (Figures 7 and 8).

PERFORMANCE COMPARISON Table 2 presents a comparison between theoretical (graphical optimization method) and simulation (ADS software) results for the two quadrature oscillators. We notice the excellent agreement between both results for the P-QVCO oscillator and the BSQVCO oscillator. As it can be seen, we notice the difference of the optimum point of the two types of quadrature oscillator, due to the difference of the equivalent tank model. From the graphic optimization or the simulation results, the P-QVCO has a higher phase noise than the BS-QVCO oscillator. Therefore, we conclude that

100

Optimization of CMOS Quadrature VCO Using a Graphical Method

Figure 7. Tank amplitude: (a) BS-QVCO; (b) P-QVCO

Figure 8. Phase noise: (a) BS-QVCO; (b) P-QVCO

the place of the coupling transistors Mcpl plays a significant role in the improvement or the degradation of the performance of a quadrature oscillator. Placing Mcpl in series with Msw can greatly enhance the phase noise oscillator. According to the simulations results, we can also note that the power consumption, phase error and amplitude error associated with a BS-QVCO oscillator are lower than a P-QVCO oscillator. Thus, it appears interesting to use a BS-QVCO quadrature oscillator counts held of its performance in terms Table 2. Comparison between theoretical and simulation results for the P-QVCO and BS-QVCO oscillators BS-QVCO

P-QVCO

Graphic optimization

Simulation

Graphic optimization

Simulation

Center frequency (GHz)

2.4

2.39

2.4

2.39

Tuning range (%)

15

16.09

15

14.67

Tank amplitude (V)

2.04

2.06

2.038

2.047

Phase noise @ 1MHz (dBc/Hz)

-127.58

-129

-125.38

-125.1

101

Optimization of CMOS Quadrature VCO Using a Graphical Method

Table 3. Comparison of VCO’s performances Ref

Tech

F0 [GHz]

P [mW]

Phase noise @1MHz [dBc/Hz]

FOM [dBc/Hz]

This work P-QVCO

CMOS 0.35µm

2.4

9.6

-125.1

183.56

This work BS-QVCO

CMOS 0.35µm

2.4

9.27

-129

187

Ming-Chun & Chia-Wei

CMOS 0.25µm

2.44

3

-123

184

Han & Chi

CMOS 0.25µm

2.26

7.5

-117.17

175.53

Ham& Hajimiri

CMOS 0.35µm

2.6

10

-115

177.73

Krout & Mnif

CMOS 0.35µm

2.6

8.175

-124.95

184.12

of phase noise, power consumption, its weak error phase and quadrature to ensure a good quality of quadrature signals. A common figure of merit (FOM) is used to compare the performance of the designed QVCO with other designs reported recently in literature. Its expression is a follows (Ham & Hajimiri):

(

FOM = L {∆f } dBc/Hz + 10log PDC

  mW − 20log  ω0     ∆ω   

)

(30)

Table 3 presents the performances obtained using the graphic optimization method and compared to designs proposed in some of published papers. As we can state, the proposed BS-QVCO achieves better phase noise FOM that others works.

CONCLUSION An optimization method was described for the sizing of a quadrature oscillator QVCO. The design consists on the visualization of the different constraints such as tank amplitude, startup condition and tuning range in order to choose the point which allows the minimization of phase noise satisfying all these constraints at the same time. Two types of quadrature oscillator (P-QVCO and BS-QVCO) are optimized and the performences were compared. This comparison proves that the phase noise of the BS-QVCO is lower than a P-QVCO oscillator. The proposed BS-QVCO achieves -129 dBc/Hz of phase noise at 1 MHz offset frequency for 2.4GHz carrier frequency and a figure of merit of 187.03 dBc/Hz is observed.

REFERENCES Andreani, P., Bonfanti, A., Romano, L., & Samori, C. (2002). Analysis and design of 1.8GHz CMOS LC quadrature VCO. IEEE Journal of Solid-state Circuits, 37(12). doi:10.1109/JSSC.2002.804352 Ham, D., & Hajimiri, A. (2000). Design and Optimization of a low noise 2.4GHz CMOS VCO with Integrated LC tank and MOSCAP Tuning. Paper presented at IEEE International Symposium on circuits and Systems.

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Optimization of CMOS Quadrature VCO Using a Graphical Method

Ham, D., & Hajimiri, A. (2001). Concepts and method in optimization of integrated LC VCOs. IEEE JSSC, 36(6), 896–909. Han, S., Chi, B., & Wang, Z., (2000). Phase noise analysis in CMOS LC Quadrature VCO. Hershenson, M., Boyd, S., & Lee. T. H., GPCAD. (1998). A tool for CMOS op-amp synthesis. In IEEE, ACM International Conference on Computer Aided Design (pp. 296-303). Krout, I., Mnif, H., Fakhfakh, M., & Loulou, M. (2008). A novel heuristic for the optimal design of LC Voltage Controlled Oscillators. IEEE ICECS. Lee, T. H. (1998). The design of CMOS radio-frequency integrated Circuits. Cambridge University Press. Niknejad, A. M., & Meyer, R. G. (1998). Analysis, design, and optimization of spiral inductor and transformers for SI RF’ICs. IEEE Journal of Solid-state Circuits, 33(10). doi:10.1109/4.720393 Rofougaran, A., Rael, J., Rofougaran, M., & Abidi, A. (1996). A 900MHz CMOS LC- Oscillator with Quadrature Outputs. In Proc. ISSCC 1996 (pp. 392-393). Su, M.-C., Wu, C.-W., & Hsu, K. Y.-J. (2002). Phase Noise Analysis of an Integrated Voltage-Controlled Oscillator with a novel Graphical Optimization Method. In IEEE Asia –Pacific Conference (pp. 189192, 6-8). Tiebout, M. (2001). Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS. IEEE Journal of Solid-state Circuits, 36, 1018–1024. doi:10.1109/4.933456

103

Section 2

Design

105

Chapter 6

The Design and Modeling of 2.4 and 3.5 GHz MMIC PA Chin Guek Ang Universiti Sains Malaysia, Malaysia

ABSTRACT This chapter discusses the design of MMIC power amplifiers for wireless application by using 0.15 μm GaAs Power Pseudomorphic High Electron Mobility Transistor (PHEMT) technology with a gate width of 100 μm and 10 fingers at 2.4 GHz and 3.5 GHz. The design methodology for power amplifier design can be broken down into three main sections: architecture design, small-signal design, and large-signal optimization. For 2.4 GHz power amplifier, with 3.0 V drain voltage, the amplifier has achieved 17.265 dB small-signal gain, input and output return loss of 16.310 dB and 14.418 dB, 14.862 dBm 1-dB compression power with 12.318% power-added efficiency (PAE). For 3.5GHz power amplifier, the amplifier has achieved 14.434 dB small-signal gain, input and output return loss of 12.612 dB and 11.746 dB, 14.665 dBm 1-dB compression power with 11.796% power-added efficiency (PAE). The 2.4 GHz power amplifier can be applied for Wireless LAN applications such as WiFi and WPAN whereas 3.5 GHz power amplifier for WiMax base station.

INTRODUCTION Modern microwave and radio frequency (RF) engineering is an exciting and dynamic field, due to recent advances in modern electronic device technology and the current explosion in demand for voice, data, and video communication capacity. Prior to this revolution in communications, microwave technology was the nearly exclusive domain of the defense industry and dramatic increase in demand for communication systems for such applications as wireless paging, mobile telephony, broadcast video, and tethered as well as untethered computer networks is revolutionizing the industry. Microwave technology is naturally suited for these emerging applications in communications and sensing, since the high operational frequencies permit both large numbers of independent channels for the wide variety of uses envisioned as well as significant available bandwidth per channel for high speed communication (Golio, 2001). DOI: 10.4018/978-1-60566-886-4.ch006

Copyright © 2012, IGI Global. Copying or distributing in print or electronic forms without written permission of IGI Global is prohibited.

The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

This invention relates generally to RF power amplifiers for wireless communications, and more particularly, the invention relates to microwave and millimeter wave integrated circuit (MMIC) power amplifiers having output impedance matching network. This shift has a dramatic effect not only on the design of systems and components, but also on the manufacturing technology and economics of production and implementation as well. The main purpose of WLANs is used to extend a service provided by a wired network, hotspot. Applications of WLAN can include enabling printers, servers, and routers to be shareable with a wireless equipped computer. The designed MMIC power amplifiers in this chapter are using 0.15 μm GaAs Power Pseudomorphic High Electron Mobility Transistor (PHEMT) is targeted for wireless applications. The major applications of 3.5 GHz band are wireless internet access, wireless local loop subscriber units/base stations, W-CDMA, WiMax base station and MMDS (Multi-channel Multipoint Distribution Service) whereas for 2.4 GHz band are WLAN, WiFi and WPAN.

Objectives The main objective of this chapter is to detail out the basic design of MMIC power amplifiers by using 0.15 µm GaAs pHEMT technology for wireless applications at low frequency points which are 2.4 GHz and 3.5 GHz and to analyze power amplifier function, performances and applications. Power amplifier plays a very important role in transmitter in order to generate and transmit sufficient power signals. A state-of-the-art power amplifier design has to meet the system requirements for high gain, high efficiency and meet the desired output power while the device and process technology of choice plays a crucial role in realizing the performance of the power amplifier. Software Advanced Design System (ADS) is used to simulate the power amplifier in order to obtain the best performance of the power amplifier. The design methodology for power amplifier design can be broken down into three main sections which are architecture design, small-signal design, and largesignal optimization. In addition, layout and optimization of the power amplifier is also one critical element in designing the amplifier because layout design is a critical part. It will determine the performance of the power amplifier after fabrication process. Layout design needs to be referred to the layout rules. Signal path using schematic with the transmission line and optimize layout size must be simulated.

Scope of the Design The main specification of the MMIC medium power amplifier operating at 2.4 GHz and 3.5 GHz are shown in Box 1 and Table 1.

Box 1. Specifications for power amplifier Operating Conditions: Vdd = (2.5 to 3) V Vbias = (-1 to 0) V

106

Impedance Matched Zin/Zout = 50 Ohm Pin = 0 dBm

The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Table 1. Specifications of Power Amplifier Operating at 2.4GHz and 3.5GHz Parameter

Typical Value

Higher Linear Gain

24 dB – 30 dB

Power Gain at 1 dB Compression Point

22 dB – 29 dB

Pout at 1 dB Compression Point (P1dB)

24 dBm – 33 dBm

PAE at 1 dB Compression Point

15% – 26%

3 Order Intermodulation (IM3) (Δf = 10MHz, Pout = 17 dBm)

35 dBc – 47 dBc

rd

High Linearity, OIP3

-

Drain Current, Idd at 1 dB Compression Point

350 mA - 1000 mA

Input Return Loss S(1,1)

- 10 dB

Output Return Loss S(2,2)

- 10 dB

RF and microwave design is performed primarily in the frequency domain, probably because the original sources were continuous wave (CW) devices, and different signals were separated by their frequencies. Time-domain analysis of RF and microwave components is becoming more important in communication systems which employing extremely complex modulation schemes, but the majority of work is still undertaken in the frequency domain. The 2.4 GHz ISM band is very important in wireless LAN application for IEEE802.11x (K. Yamamoto, 1999). LAN applications have driven the demand for personal wireless communications terminals, and these items need to be low-cost, low-operating-voltage and small size (A. Raghavan, 2002). Power amplifiers among these terminals play a very important role in these systems. So, the application ambit of this power amplifier MMIC is the key component for researching the advanced systems of WLAN. Until recently, WiMAX systems have used technology processes such as Gallium Arsenide (GaAs) to obtain the performance needed from the RF circuits. Although these technologies provide the functional performance required by radios today, they do not support the cost/scalability business model. But as the MOS technology is being developed, more research is currently investigating the use of these technologies in radio frequency systems, such in power amplifiers for frequencies upper than 2 GHz, as they present acceptable cost. The higher switching speeds that result from the smaller geometries being developed in MOS are enabling the design of analog circuits at very high frequencies, within a limit, with very good gain and linearity. Monolithic microwave integrated circuit (MMIC) power amplifier design is much more complicated than small-signal amplifier design because the larger voltages and currents within the circuit can cause the MMIC components to behave nonlinearly. Simulation of a circuit with nonlinear components no longer has a unique solution and requires iterative techniques.

Chapter Organization Introduction presents an introduction of this chapter. It gives an overview of the system background and wireless technologies. Section background presents the literature review. The theories and concept that are related to this the discussed design in this chapter such as active device, passive device, power amplifier parameters and design. 107

The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Section Theory and Design presents methodology of the design and simulations of power amplifier. It describes the device characteristic of active device, DC bias, and feedback topology, the matching network for input and output impedance and cascade topology of the circuit of power amplifier design. The steps with the several standard stages, which include Specification, Circuit Design, Schematic Entry, Simulations, Optimization or Tuning, Layout Design and Verification are described. Section results show the simulation results and present the analysis and interpretation of the results. Besides, layout implementations for single and two-stage power amplifier are also showed in this chapter. Finally the chapter is concluded at the last section.

BACKGROUND The MMIC Advantage MMICs emerged because they combined high-performance microwave transistors with low-loss passive components and transmission lines and could be formed as complex circuits with multiple interconnections using just a few photolithographic process steps. A hybrid microwave and millimeter wave integrated circuit (MMIC) RF power amplifier includes an integrated circuit in which an amplifier circuit is fabricated and an output impedance matching network comprising metal-insulator-metal (MIM) capacitors mounted on the integrated circuit chip with bonding wire inductors connecting the amplifier circuit with the capacitor elements. The resulting structure has a smaller form factor as compared to conventional power amplifiers employing planar transmission lines and surface mount technology capacitors. The microwave frequency response of the transistors also required microns of dimensions so that the resulting size of the chips was only a few millimeters. The small dimensions of MMICs also provide less weight than their hybrid microwave integrates circuit (MIC). These two features of MMICs make them ideally suited to mobile electronic applications. The low cost advantage if MMICs is only ensured when high numbers of the chips are required and the design produces a high-yielding circuit (Steve Marsh, 2006).

Transistor Type The two basic types of active devices used in MMICs are the field effect transistor (FET) (Lilienfeld, 1926) and the bipolar transistor (Brattain, 1968) (Table 2). The High Electron Mobility Transistor (HEMT) referred to the literature as heterostructure FETs or heterojunction FETs (HFETs) operates likes any other FET except the channel is constructed from a junction of two different types if semiconductor material to give the free electrons in the channel higher mobility(Morkoc, 1984). The type of transistor used for this design is Pseudomorphic High Electron Mobility Transistor (PHEMT). PseudomorphicHEMTs (PHEMTs) used an extremely thin layer of the different semiconductor typically indium gallium arsenide (InGaAs), which is strained to the lattice constant if the surrounding semiconductor typically aluminum gallium arsenide (AlGaAs), making a pseudomorphic layer (Marsh, 2006).

108

The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Passive Components Passive elements are composed of lumped elements such as resistors, capacitors, and inductors and distributed elements such as transmission lines. The performance of the design is strongly depending on the quality of passive elements.

Resistors MMIC resistors are produced either by MMIC atop the active semiconductor layer or laying down thin films of resistive metal alloys above the surface as the resistive material. The resistors are constructed with metal contact pads at end of the resistive material film as shown in Figure 1. Two types of resistors are commonly used in MMIC fabrication. Thin films of lossy metals and lightly doped GaAs active layer (mesa resistors). Titanium tungstosilicate (TiWSi) can have film resistivity of 500 Ω to 1500 Ω per square. Metal thin-film resistors are more temperature stable and are used as precision resistors of low to moderate values which fabricated by using Nichrome (NiCr) and tantalum nitride (TaN) and they have film resistivity from 20 Ω to 50 Ω per square Table 2. MMIC circuit types best suited to the different transistor types Transistor types

Bipolar

FET

CMOS

SiGe HBT

GaAs/InP HBT

MESFET

HEMT

Oscillator

_

✓

✓

_

_

Mixer

_

✓

✓

_

_

Low-noise amplifier

_

✓

✓

_

✓

Power amplifier

_

_

✓

_

✓

Switch

_

_

_

✓

✓

Digital

✓

✓

_

_

_

Figure 1. Resistor construction

109

The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Resistance = sheet resistance x length/ width

(1)

Capacitors Capacitance is a measurement of a component’s ability to store electric charge and determines the impedance to RF signals, expressed as coulombs per volt. RF signals can pass through capacitors by charging and discharging them. More charge storage capacity, more current they allow per volt of signal. Hence, the larger capacitor is the lower impedance. Z= (Volts / current)

(2)

MMIC capacitors are formed by two main methods, one uses the fringing capacitance between interdigital metal strips and another one is metal-insulator-metal (MIM) capacitor. The interdigital capacitor relies on the fringing capacitance between the long common-edge areas of the metal fingers which are separated by just a few microns depending on the minimum gap allowed by the foundry. The fringing capacitance is fairly low so the capacitors are able to reach capacitance value around 1pF. Metal-insulator-metal (MIM) capacitors are constructed from two relatively large plates of metal separated by a smaller distance with the gap filled with an insulating dielectric material. This further increases the capacitance values (Mondal, 1987). The range of capacitance values are from 50 fF up to 200 pF.

Inductors MMIC inductors are fabricated using lengths of interconnect metal formed as narrow transmission lines, either on their own or wound around a central point to create a spiral transmission line inductor. The DC inductance value of inductor is determined from the total length, the number of turns, spacing and line width for the spiral inductor. Narrow tracks are more inductive but carry less current so there is a trade-off between them. Spiral track inductors have more inductance because the magnetic fields from each turn of the spiral add up, creating a larger field through the middle of the spiral and mutual inductance between all the turns. Many different types of spiral inductor are used in MMIC process such as circular air bridge cross inductor, square air bridge cross inductor, and octagonal spirals.

Transmission Lines The most common type of transmission line used in MMICs is microstrip (Edwards, 1981) which consists of a metal track on a dielectric substrate with an infinite ground plane on the back surface show in Figure 2. The track width and substrate height are finite dimensions whereas the ground plane and substrate weight and length are assumed to be infinite. The characteristic of the microstrip transmission line are determined by the ratio w/h, i.e. the track width to the height of dielectric because it mainly influences the magnetic field and electric field pattern. A track with width similar to the substrate height look like a parallel plate capacitor has more parallel electric field underneath the track and looks more capacitive. While a track with width much narrower

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Figure 2. Microstrip transmission line

than the substrate height has magnetic field tightly packed that look similar to a simple wire. Hence, it behaves more inductively and has higher characteristic impedance. In an MMIC process, the substrate height usually fixed at 100 µm or 200 µm, as a result the track impedance is set by the track width. The range of track width is from around 6 µm to 120 µm which corresponds to microstrip characteristic impedances about 120 Ω down to 40 Ω.

Power Amplifier Operation Classes Two major kinds of power amplifier are widely used. They are linear amplifier and switching amplifier. In linear amplifier, its output is linearly proportional to its input. Class A, B, AB, C are some common types for linear amplifier (Narayanaswami, 1998). As for switching amplifier like class E and F, the amplifier is driven with large amplitude of signal turning the transistor ON and OFF (Figure 3).

Figure 3. Classes of power amplifier (Cripps, 1999)

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Choosing the bias point of an RF Power Amplifier can determine the level of performance ultimately possible with the PA. In order to operate a transistor for a certain class, the gate and drain DC voltages have to be biased carefully to certain operation point (quiescent point or Q-point), regarding the desired class. The reason is that the choice of Q-point greatly influences the linearity, power handling and efficiency. In addition, as can be seen further, the choice of optimal Q-point is limited by a safety region which prevent the transistor from being heated badly and damaged. Details on operation classes can be found in (Cripps, 1999). Class AB Class-AB amplifiers are popular candidates in power amplifiers designs. The transistor response of class-AB is wider than for class-B due to the operation point, and its power efficiency is higher than for class-A. So class-AB is shown as a compromise between linearity and efficiency (Table 3).

Loadline Linear amplifier operates at constant gain is based on load-line theory illustrated in Figure shows that the maximum power that can be delivered to the load is depends on the maximum current of the transistor and supply voltage. When the transistor load is a large inductor, the maximum voltage swing possible at the drain is two times the supply voltage. The loadline is plotted from equation: Ropt= 2 Vmax / Imax

(3)

Where the optimum resistance of a load, Ropt is obtained by the relationship of maximum power supply, Vmax to a load, which is usually equal to Vdd while Imax = 2Vdd/RL, indicating the maximum load current obtained.

Power Amplifier Properties The most important parameters of a power amplifier are discussed in this section such as efficiency, power gain, linearity and stability.

Table 3. Characteristic of power amplifier’s classes Modes

Gate Bias

Maximum Efficiency (%)

Output Power

A

Vpinch-off /2

50

Moderate

Large

Good

AB

Current Source

Near Vpinch-off

60

Moderate

Moderate

Medium

Class

B

Linearity

Vpinch-off

78

Moderate

Moderate

Medium

C

< Vpinch-off

90

Small

Small

High

D

Vpinch-off

100

Large

Small

High

Vpinch-off

100

Large

Small

High

Vpinch-off

85

Large

Small

High

E F

112

Gain

Switch

The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Efficiency Efficiency is one of the most important parameters in power amplifier design. It measures how many percent of the supply power is translated to output power. The most commonly definitions used in power amplifier designs for the efficiency are: drain efficiency and power added efficiency. Drain efficiency is the ratio of the RF-output power to the dc input power. η=

Pout Pdc

(4)

POUT is fundamental output power at the 1dB compression point P1. Pdc is the power consumption of power amplifier: Pdc =Vdc Idc.

(5)

Practically, 100% of efficiency is impossible to achieve. The efficiency is trade off with linearity so both of them need to be compromised for better efficiency. Power-added efficiency (PAE), however, takes the power of the input signal into account and can be expressed by: PAE =

Pout − Pin Pdc

(6)

Where Pout is the output power of power amplifier, Pin is the input power provided and Pdc is the power consumption of power amplifier. PAE is generally used for analyzing PA performance when the gain is low and used to compare power amplifiers with different input power levels. This parameter is particularly important from powerconsumption point of view.

Figure 4. Loadline

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Gain In microwave designs, the gain is represented by different definitions. Its most representative definition is the transducer power gain. It is the ratio between the power delivered to the load and the power available from the source. The power gain will equal to the voltage gain of the amplifier if the input and output impedance are the same Transducer gain can be expressed by: G=

PL PS

(7)

Where PS is the RF input power and PL is the RF output power. Linearity The RF power amplifiers are inherently non-linear and are the main contributors for distortion products in a transceiver chain. Power amplifiers can affect the utilization of the spectrum through nonlinear performance. Non-linearity is typically caused due to the compression behavior of the power amplifier, which occurs when the RF transistor operates in its saturation region due to a certain high input level. Usually non-linearity is attributed to gain compression and harmonic distortions resulting in imperfect reproduction of the amplified signal. It is characterized by various techniques depending upon specific modulation and application. Some of the widely used figures for quantifying linearity are the: • •

1 dB compression point – Dynamic range Third order intermodulation distortion - Linearity

1 dB Compression Point (P1dB) Non-linear response appears in a power amplifier when the output is driven to a point closer to saturation. As the input level approaches this saturation point, the amplifier gain falls off, or compresses. The output 1 dB compression point can be expressed as the output level at which the gain compresses by 1 dB from its linear value. The gain corresponding to the 1 dB compression point is referred to as G1dB and is computed as G1dB = G0-1dB, where G0 is the small-signal gain (or 10log |S21| 2). Pout, 1dB at the 1 dB compression point can be expressed in dBm if it is related to the corresponding input power Pin, 1dB as: Pout,1dB (dBm)=G1dB (dB)+Pin,1dB (dBm)=G0 -1dB+Pin,1dB (dBm)

(8)

Figure 5 shows the relationship between the input and output power of a typical power amplifier. Intermodulation Distortion Intermodulation Distortion is a phenomenon of generation of undesirable mixing products, which distort the fundamental tones and gives rise to intermodulation products. The third order intermodulation products have the maximum effect on the signal, as they are the closest to the fundamental tone. The unwanted spectral components, such as the harmonics, can be filtered out. But the filtering does not work with the third order intermodulation products, as they are too close to the fundamental tone.

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Figure 5. Pout vs. Pin, 1dB compression point

Figure 6 shows the frequency domain representation of the intermodulation distortion caused due to a two-tone signal. Intermodulation products higher than third order, the odd harmonics (fifth, seventh) are important to consider when Pout exceeds the 1dB compression point (Charles Nader, June 2006). Stability Stability is a practical problem frequently encountered in the design of linear PA. Instability can be subdivided into two distinct categories: Low-frequency oscillation and in-band instability. In band instability is avoided by designing the gain to meet the criteria for unconditional stability; i.e., the Rollet k factor must be greater than unity for both in-band and out-of-band frequencies. Meeting this criterion usually requires sacrificing some gain through the use of absorptive elements. Large RF power devices typically have very high transconductance, and this can produce low-frequency instability unless great care is taken to terminate both the input and output at low frequencies with impedances for unconditional Figure 6. Two tone intermodulation distortion

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

stability. Because of large separation from the RF band, this is usually a simple matter requiring a few resistors and capacitors. The main reason behind unstable behavior of the active device is a reverse feedback from output to input. Several factors are used in estimating the stability in class AB amplifier. The Rollet’s conditions are based on the two-port S-parameters matrix expressed as: | ∆ |=| S11 ⋅ S 22 = S12 ⋅ S 21 | K =

1− | S11 |2 − | S 22 |2 + | ∆ |2 2⋅ | S12S 21 |

(9)

For unconditional stability: k > 1 and |Δ| <1, otherwise the stability has to be taken into account.

Power Amplifier Design The design methodology for power amplifier design can be broken down into three main sections: architecture design, small-signal design, and large-signal optimization. Architecture design is the process of determining the basic layout of the circuit, such as the number and size of the active devices required, working from the specification through to rough design. This design plan should be capable of meeting the gain and power specification. Small-signal design is designing the matching and biasing networks to achieve the basic bandwidth, gain and input match. Large-signal optimization is the optimization of the output-matching circuits for the best performance under large-signal operating conditions. This involves tweaking the output-matching circuit using the minimum amount possible of time-consuming nonlinear analysis to take account if the weak nonlinearities encountered at the extreme ends of the load line. Popular large signal simulation of nonlinear circuits is known as harmonics balance.

Architecture Design Architecture design is the initial processes for power amplifier design by taking the requirement specification and deriving from it basic layout and structure of the power amplifier. This involves deciding which MMIC process to use, what size of unit cell device, how many gain stages and which bias point and efficient mode to operate at. Two-Stage Power Amplifier Power amplifier design strongly depends on the operating frequency and applications. The cascade topology is utilized for designing a multi-stage transistor amplifier and to form a circuit having an enormous amount of gain and power. The gain per stage in an amplifier is typically around 10dB but higher gain per stage is desirable because of two reasons: 1. The higher gain per stage the fewer the stage requires and the design complexity can be significantly reduced.

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

2. The overall amplifier efficiency is improved if fewer higher-gains are used. Power Amplifier Efficiency Power amplifier efficiency, PAE is a measure of how efficiently the design converts the DC bias power into additional power at the RF frequency. PAE = (Pout –Pin)/ Pdc

(10)

Where Pin is the input RF power, Pout is the output power and Pdc is the power consumption. The output RF power Pout is the input RF power Pin multiplied by the power gain (G) of the amplification stage. RF output power (Pout) = GPin

(11)

High power gain in an amplification stage improves efficiency because at the limit of infinite stage gain, Pin tends to 0 and the power-added efficiency reduces to simply the output RF power Pout divided by the DC bias power Pdc. PAE (G very high, Pin→0) = Pout/ Pdc

(12)

The expression in (12) is also referred to as the drain efficiency of an amplification stage as it relates how efficiently the DC drain bias is converted to RF output power from the drain port of a single stage FET amplifier. Figure 7 shows two stage power amplifier schematic diagram. The efficiency of the output stage increases as it exhibits more power gain. Thus, peak efficiency is achieved when all the gain is in the last stage because there is only one gain stage and the PAE is the output power (Pout) divided by only the output stage DC bias (Pdc2), given by Equation (13). Any addition gain stages before the output gain stage increase the overall amplifier gain but do not increase the output power capacity of the output stage. These additional input gain stages require their own DC bias power and increase the overall DC power consumed by the amplifier as indicated by Equation (14), and decreases the overall amplifier efficiency.

Figure 7. Schematic diagram of a two-stage amplifier

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

PAE = Pout/ Pdc2

(13)

Pdc = Pdc1 + Pdc2

(14)

Cascaded 1 dB Compression Point Power amplifiers are commonly specified to have high efficiency at the P1dB compression point. The peak efficiency in the output stage occurs when the input power to this stage is high enough that the gain is compressed by 1 dB. The overall gain compression is the sum of the compression of each stage, so if earlier gain stages compress then the overall amplifier reaches the P1dB compression point before the output stage is fully compressed by 1 dB. Then some of the DC power in the output stage is wasted if the large output stage is not operating at its own P1dB compression point and the PAE of the overall amplifier at P1dB is reduced. Therefore, for peak efficiency, the power amplifier should be designed to exhibit all of the gain compression in the output stage and have all the preceding input stages operating within their linear region (Marsh, 2006).

Small-Signal Design Once the architecture of the power amplifier is defined, the matching circuit for the active devices must be designed and incorporated with DC bias networks. At the beginning of power amplifier design, the power amplifier can be assumed as linear amplifiers with the output-stage matching adjusted for the weak nonlinearities at the P1dB compression point, so the matching circuits are initially designed by linear small-signal techniques. This is a fast and simple way of designing the matching and biasing networks to achieve the basic specification for bandwidth, gain and input match. Bias and Matching Networks This part of the chapter investigates the general steps that should be followed to design the bias network and the input-output matching network. The block diagram, Figure 8, represents a typical circuit conFigure 8. Block diagram of an amplifier

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

sidered in the design process. It consists of on a Bias Network (BN), Input Matching Network (IMN), Output Matching Network (OMN), Accessories Networks (AN) and the input and output ports that are assumed to be 50 Ohm. Bias Network The bias network is an important part of the power amplifier design. In fact, the BN control the operation class of the transistor and at the same time it prevents the RF signal from leaking to the DC source and prevents the DC signal from leaking to the RF trajectory. The BN of a high power amplifier differ from the normal amplifier by the fact that it is nonresistive. The main reason behind that choice is that high power amplifier consumes high current, so to prevent additional heating in the system, non-resistive bias network is used. Usually, BN consists on blocks of capacitance and inductance whose objective is to work as DC Feed-RF Block in the DC track, and as DC Block-RF Feed in the RF track. Their values depend on the frequency range the power amplifier is supposed to work in. Input/Output Matching Networks In power amplifier designs, to achieve high accuracy and maximum power transmission, a matching network is required on the input and output to minimize the reflection (standing waves) problems. Matching networks are passive, consisting of microstriplines, inductors, capacitors and resistors. To realize a conjugate match at the input and a power match at the output, the reference impedance RO (normally 50 Ohm) must be transformed to the optimum input and output impedance, Zin_opt and Zout_opt as shown in Figure 9. Accessories Networks Finally, the existence of accessories networks (AN) is mentioned. They are different methods and facilities to improve stability and linearity characteristics of the amplifier. Feedback Because almost all of the power devices are potentially unstable, another important issue in the design of a power amplifier is the stability.

Figure 9. Schematic of a single-ended Class AB power amplifier

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

• • • •

Give very flat gain. Achieve moderate power levels. Stabilizing the device. Make the input and output impedances more closely to the desired 50 Ω.

Parallel Feedback One of the design constraints in the power amplifier design is stability. In order to increase the stability of the device, a resistor network is used to provide a negative feedback (Kang, 2002). The negative feedback is formed by adding a resistor network from the drain to the gate so that the amplifier is always unconditionally stable and the effect of feedback is to make the input and output impedances more convenient for matching. Series Feedback Series feedback entails by inserting an inductor into the source of an active device to make the device stable at a lower frequency and improve the noise figure.

Large-Signal Optimization The final stage of power amplifier design is the optimization of the output-matching circuits for the best performance under large-signal operating conditions. This involves tweaking the output-matching circuit using the minimum of time-consuming nonlinear analysis to take account of the “weak” nonlinearities. Under large-signal operation, for example at 1 dB gain compression, certain active device parameters become nonlinear. These parameters are mainly the gate-to-source capacitance Cgs, the gate-to-drain capacitance Cgd, the transconductance Gm and the output resistance Rds. The harmonic signals interact with the linear matching circuits and a proportion is reflected back to the active device which in turn produces more harmonics. Large-signal simulation of nonlinear circuits is known as harmonic balance because the simulator must adjust the power levels in all the harmonics until the signals transmitted and reflected from the linear matching circuits balance with the signals transmitted and reflected from the nonlinear device. This is an interactive process and continues until the errors between the signals drop below a predetermined level. To achieve the peak output power performance, the output-matching circuit on the last stage must be optimized for nonlinear large-signal operation.

THEORY AND DESIGN Device Characteristic The choice of device size is a critical step in designing a MMIC power amplifier. Device size will affect the bandwidth, DC power consumption, efficiency and nonlinear performance. Additionally, drain bias affects amplifier gain. With insufficient current, gain will be low. Decreasing the drain voltage will reduce DC power consumption, but the drain voltage must be high enough for the device to operate in its saturation region and enable amplification. In this chapter, MMIC power amplifier is using 0.15 μm GaAs Power Pseudomorphic High Electron Mobility Transistor (PHEMT) with unit gate width (UGW) of 100 μm and 10 fingers.

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Figure 10 shows the schematic of DC characteristic simulation in order to define the drain current. The drain voltage, Vds was sweep from 0V to 7V while the gate voltage, Vgs was sweep from -1 V to 0 V. Figure 11 shows the IdVd characteristics for transistor with NOF is 10 and the gate width is 100 um. For the bias condition of drain voltage, Vds is 3 V and gate voltage, Vgs is -0.9 V, the drain current, Ids of 82 mA was obtained. The maximum current IMAX is 451mA at Vds equal to 1.3 V. The curve is significantly decreased because of the self-heating. Figure 10. Schematic of DC characteristic simulation

Figure 11. IdVd characteristic

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Figure 12 shows that the transistor threshold has the threshold voltage, Vth of -1.45 V. In order for the power amplifier working in class AB, the bias of Vgs must between -1.450 V to -0.300V by refer back to Figure 3, Classes of power amplifier (Cripps, 1999). Therefore, the gate and drain DC voltages have to be biased carefully to certain operation point regarding the desired class in order to operate a transistor for a certain class.

DC Bias Injection The drain DC bias current applied to the transistor is by self-biasing technique which enables the transistor to be biased from a single power supply rail (Figure 13). The gate is grounded at ground DC through an Figure 12. Id versus Vgs graph

Figure 13. The self-biasing of DC bias network

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

inductor. The source is raised to a positive DC potential, equal in magnitude to the desired gate-source voltage, by inserting a small resistor in the source. In order to prevent a loss of RF gain, the source is grounded with a large decoupling capacitor. The advantage of the single power supply is considerable, particularly for battery operation but there are some disadvantages because of the slightly increased DC power consumption.

Feedback Topology Parallel Feedback One of the design constraints in the power amplifier design is stability. In order to increase the stability of the device, a resistor network is used to provide a negative feedback (Kang, 2002). The capacitor, CF and resistor, RF are added between the drain and gate of transistor as shown in Figure 14(a) to provide an RC feedback or commonly known as negative feedback in order to produce broadband matching and also to increase the stability of the device; so that the amplifier is always unconditionally stable. CF can normally be chosen so that it is large enough to be a short circuit over the frequency of interest. In addition, the effect of feedback is to make the input and the output impedances more convenient for matching. Another advantage of employing this feedback is the properties of the circuit can be made to depend primarily on the values of the feedback circuit elements and to be more-or-less independent of the particular characteristics of the active device (such as transistor β, bias current, etc.).

Series Feedback Series feedback entails inserting an inductor into the source of an active device shown in Figure 14(b) in order to make the device stable at a lower frequency. With an inductor the noise figure may actually improve and the noise matching impedance may be brought closer to the power matching.

Figure 14. Stabilizations methods: (a) parallel feedback, (b) series feedback

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Matching The complete schematic of the designed power amplifier are shown in Figure 15 where LG, LS, LD and LO are all implemented with on-chip spiral inductors. The inductors LG and LS are chosen to provide the desired input impedance. The inductor LD is a current source for the MPA and is used for output power matching. An RF bypass capacitor CD is parallel element that acts like a short circuit to microwave signals, but here it is meant to reflect RF signals by shorting them out and to ensure good ac ground is achieved. The capacitor CC at the output plays a role for both DC block and output matching. The capacitor CO is used for network matching. Both input and output are matched to 50 Ohms.

Input Matching Network The S-Parameter simulation was performed to obtain the input impedance before matching, Zin of Zo*(1.250-j2.361) Ω that is (62.5 - j 118.05) Ω. Input matching before matching is the input impedance includes the feedback and Cgs impedance. Figure 16 shows the Smith chart of impedance Zin of S11 before input matching at 2.4 GHz frequency. After the input matching network with inductor of 4138.17 pH, the input impedance has significantly improved and the Figure 17 shows the schematic of input matching network. From the smith chart shown in Figure 18 the input impedance obtained after matching is Zo *(1.007+ j 1.740) Ω that is equal to (50.35+ j 87) Ω with the magnitude and phase of 0.655/ 48.838 at 2.4 GHz, respectively.

Figure 15. Circuit schematic of the PHEMT single-ended medium power amplifier

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Figure 16. Input impedance before matching in Smith chart

Figure 17. Schematic after added input matching network

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Figure 18. Input impedance of power amplifier in Smith chart

Output Matching Network After the input matching, the output impedance before matching can be obtained from the simulation result, Zout= Zo* (0,777+ j 0.337) Ω which equal to (38.85+ j 16.85) Ω. The output impedance before matching is the impedance includes the feedback impedance. Figure 19 shows the Smith chart of impedance Zout or S22 before output matching at 2.4 GHz frequency. After the output matching network with capacitors and inductors, the impedance have slightly improved and the Figure 20 shows the schematic of output matching network. From the Smith chart, the output impedance obtained after matching is Zo *(1.178-j 0.353) Ω that is equal to (58.9-j 17.65) Ω with the magnitude and phase of 0179/-54.078 at 2.4 GHz, respectively (Figure 21).

Close-Loop Gain The close-loop gain can derive from the feedback topology of the power amplifier as shown in Figure 22 and below (GF, GS, AOL is conductance of feedback resistance, conductance of source resistance and open-loop gain respectively). 1 1 Vout =− AoL, Rf = , Rs = Vx Gf Gs

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Figure 19. Output impedance before matching in Smith chart

Figure 20. Schematic after added output matching network

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Figure 21. Output impedance of S22 in Smith chart

Figure 22. (a) Feedback topology, (b) Close loop system for the feedback of the power amplifier

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Vout −Vx Vx −Vin = Rf Rs Vout +

Vout AOL

Rf Vout Gf (1 + Vout (G f + Vout =− Vin

Vout =− Vin

Av = −

− =

Vout −Vin AOL Rs

VoutGs 1 )= − −Vin Gs AOL AOL

Gf AOL

+

Gs ) = −Vin Gs AOL

Gs Gf

G Gf + + s AOL AOL

(15)

1 1 ) G f (1 + AOL 1 + Gs AOL

1 1 ) G f (1 + AOL 1 + Gs AOL

From Equation 17, Av = −

(16)

(17)

1 1 ) G f (1 + AOL 1 + Gs AOL

Compare with the formula, the feedback factor β equals to: G f (1 + β=

Gs

1 ) AOL

(18)

The closed-loop gain will be equal to an open loop gain if GF approaches zero. In this case, the open loop gain is referring to transistor gain without feedback topology. For the calculation of the close-loop gain, Av, see Figures 23, 24 and 25. From the Figure 24, gm is equal to 0.340 at the point of Vgs= -.9 V and Ids= 82mA.

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Figure 23. Schematic of GmVG curve

Figure 24. GmVG curve

From the linear region of IDVD characteristic curve at Vgs = -0.9 V, ΔVDS is (3-0.9) V = 2.1 V and Δ IDS is (82-53) m A = 29 mA. ro =

∆VDS 2.1 = = 72.41 Ω ∆ IDS 0.029

AOL=gmro, R f = 294.54Ω, R s =50Ω 1 1 Gf = 50 294.54 −1 = 3.395 m Ω−1 = 0. 02 Ω

Gs =

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Figure 25. IDVD characteristic

Substitute the ro = 72.41 Ω and gm= 0.340 into Equation 19: AoL =gm ro = 0.340 x 72.41W = 24.62 Av =

From Equation 17,

(19)

1 1 G f (1 + ) AOL 1 + Gs AOL 1

= 3.39x 10−3 (1 + 0.02

1 ) 24.62 +

1 24.62

= 4.60 Calculation of Av in dB by,

Av

= 20 log ( 4.60 ) = 13.26 dB

Cascade Topology In order to increase the small signal gain of the amplifiers, the multi-stage configuration can be applied. However, the circuit complexity increases significantly as the number of stages of the amplifier increase. For example, to design a two-stage amplifier is complex. However, independent single-stage amplifier can first be designed separately, and then combine these two single-stage amplifiers into one two-stage amplifier with matching network between the output of the first single-stage amplifier and the input of

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

the second single-stage amplifier. In this chapter, a two-stage GaAs PHEMT MMIC power amplifier was designed using such a method.

Design Flow The design flow of the MPA can be illustrated in Figure 26. The tool is Advance Design System (ADS) with 0.15 µm GaAs pHEMT technology library (WIN). The design start with the several standard stages, which include Specification, Circuit Design, Schematic Entry, Simulations, Optimization or Tuning, Layout Design, Verification and Fabrication. The first step for the circuit design is getting the general schematic of lumped components of power amplifier. The schematics will be simulated with ADS in Simulation stage. The simulation results are then compared to the specifications and then tuning is done to obtain the best performance of the power amplifier is done. When the best simulation results is obtained then the design can be proceeded to Layout Design or else the design will need to be replaced or altered by repeating the same procedure until obtain the best simulations results which most conform to the specifications is achieved. Figure 26. Design flow of the MPAs

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

In Layout Design, the main focus is to construct a layout of the designed power amplifier with a minimum area in order to reduce the cost of fabrication. Next, the constructed layout will proceed to Verification, which includes Design Rule Check (DRC).

Simulation The schematics will be simulated with Advance Design System (ADS) in Simulation stage. First of all, the 0.15 µm GaAs pHEMT technology library was installed in software ADS and the lump components in the power amplifier schematics were changed to the (Wireless Information Networking) WIN components. Then, the schematics with the WIN components were simulated by using ADS. Figure 27 shows the schematics of the 2.4 GHz power amplifier with the WIN components. Simulation Analyses The following analyses are used to simulate the parameters of power amplifier. a. S-parameter Analysis (sp) ◦◦ Higher Linear Gain (S21) ◦◦ Input and Output Return Loss (S11, S22) ◦◦ Stability, K b. One Tone Harmonic Balance Simulation ◦◦ Power Gain at 1dB Compression Point Figure 27. Schematics of the 2.4 GHz power amplifier with the WIN components

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

◦◦ Power-Added Efficiency, PAE ◦◦ Pout at 1dB Compression Point, P1dB ◦◦ Drain Current, Idd at 1 dB Gain at Compression Point c. Two Tone Harmonic Balance Simulation ◦◦ Intermodulation Distortion

Layout Design Layout design is a critical part since it will determine the performance of the power amplifier after fabrication process. After the best simulation result is obtained from the schematics of power amplifier, then layout of the designed power amplifier with a minimum area were constructed. The procedure that is required during the layout design was referred to the layout design rules. Signal path simulation also needs to be included by simulating signal path using schematic with the transmission line. The transmission line was represented by the double metal microstriplines Metal1+ Metal 2, MLIN_D, MTEE and MCORN.

Figure 28. Schematics of the 2.4 GHz single stage Power Amplifier power amplifier distributed circuit

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Simulation process and layout design are interrelated because they need to refer to each other from time to time to tackles the desired specifications. Firstly, the components are arranged so that pack to each other and then connected by microstriplines such as MLIN_D, MTEE, MCORN to each others with the optimization size consideration in the layout. After layout part has been completed, the corresponding schematics have to be added with microstriplines, with substrate’s parameters: εr =12.90, H=100 μm, T=3 μm, TanD= 0.001, Zo=50Ω which refer to the layout design. The schematic then repeating the same procedure from the step of schematic entry to optimization until obtain the best simulations results similar or better than the simulation result before added microstriplines which is most conform to the specifications. Figure 28 shows the schematics of the 2.4 GHz power amplifier after microstripline is added. Figure 29 shows the schematic of the 2.4 GHz two-stage power amplifier without microstriplines. The schematic are combination of two single-stage amplifiers. The microstriplines (transmission line) then added to connect the components of the circuits after the design of cascade power amplifier (Figure 30).

Figure 29. Schematic of the 2.4 GHz two-stage power amplifier without microstriplines

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Figure 30. Schematic of the 2.4 GHz two-stage power amplifier distributed circuit

Figure 31. Circuit schematic of the single-ended 2.4GHz medium power amplifier

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

SIMULATION RESULT AND DISCUSSION Single-Stage Power Amplifier 2.4 GHz Power Amplifier The supply voltage, VDD for this simulation is 3.0 V and drain current, Idd is 77 mA. The power consumption of the device is 231 mW. The small-signal performance of the single-ended MPA is shown in Figure 32 over the 1 to 6 GHz frequencies. The linear gain (S (2, 1)) is 8.384 dB, input return loss is 10.647 dB and output return loss is 9.659 dB at a frequency of 2.4 GHz. Figure 33 shows a stability factor, K as a function of frequency for this single-ended MPA. At 2.4 GHz, a stability factor, K for this device is 1.238. The MPA is in unconditionally stable condition due to the stability factor for the MPA is higher than 1 at the whole range of frequency. Figure 32. Gain, input return loss and output return loss as a function of frequency for single stage 2.4 GHz medium power amplifier

Figure 33. Stability factor, K of single stage 2.4GHz medium power amplifier

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Figure 34 shows the output power, power gain and the power added efficiency, PAE as a function of input power. The MPA has an output power of 14.197 dBm at 1dB gain compression (P1dB), a power gain of 7.197dB and the power added efficiency (PAE) of 9.313% for an input power, Pin of 7 dBm, exhibits a maximum PAE of 16.945% for input power 12.6 dBm. The two tone inter-modulation powers, as shown in Figure 35. The 3rd intermodulation distortion is 9.313 dBc with the single carrier output power level of 17 dBm.

3.5 GHz Power Amplifier With the supply voltage, VDD for this simulation is 3.0 V and drain current, Idd is 74 mA. The power consumption of the device is 222 mW. The small-signal performance of the single-ended MPA is shown in Figure 37 over the 1 to 6 GHz frequencies. The linear gain (S (2,1)) is 7.150 dB, input return loss is 12.390 dB and output return loss is 11.532 dB at a frequency of 3.5 GHz. Figure 34. Output power, power added efficiency and power gain versus input power for single stage 2.4GHz medium power amplifier

Figure 35. 9.313 dBc of 3rd intermodulation distortion @F1=2.404 GHz, F2= 2.414 GHz for single stage 2.4 GHz medium power amplifier

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Figure 36. Circuit schematic of the single-ended 3.5 GHz medium power amplifier

Figure 37. Gain, input return loss and output return loss as a function of frequency for single stage 3.5 GHz medium power amplifier

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Figure 38. Stability factor, K of single stage 3.5 GHz medium power amplifier GHz, F2= 2.414 GHz for single stage 2.4 GHz medium power amplifier

Figure 39. Output power, power added efficiency and power gain versus input power for single stage 3.5 GHz medium power amplifier

Figure 38 shows a stability factor, K as a function of frequency for this single-ended MPA. At 3.5 GHz, a stability factor, K for this device is 1.254. The MPA is in unconditionally stable condition due to the stability factor for the MPA is higher than 1 at the whole range of frequency. Figure 39 shows the output power, power gain and the power added efficiency, PAE as a function of input power. The MPA has an output power of 14.046 dBm at 1dB gain compression (P1dB), a power gain of 6.046 dB and the power added efficiency (PAE) of 8.549% for an input power, Pin of 8 dBm, exhibits a maximum PAE of 17.963% for input power 13.8 dBm. The two tone inter-modulation power is shown in Figure 40. The 3rd intermodulation distortion is 11.162 dBc with the single carrier output power level of 17 dBm.

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Figure 40. 11.162 dBc of 3rd intermodulation distortion @F1=3.505 GHz, F2= 3.515 GHz for single stage 3.5 GHz medium power amplifier

Two Stage Power Amplifier 2.4 GHz Power Amplifier In order to increase the gain of the amplifiers, the multi-stage configuration can be applied. In this design a two-stage GaAs PHEMT MMIC power amplifier was designed using such a method of combining these two single-stage amplifiers into one two-stage amplifier with matching network between the output of the first single-stage amplifier and the input of the second single-stage amplifier show in the Figure 41.

Figure 41. Circuit schematic of the PHEMT two-stage 2.4 GHz medium power amplifier

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Simulation Result of Two Stage Power Amplifier The bias condition for this design is 3 V and the drain current, IDS is 160 mA which includes approximately 77 mA for the first stage and 83 mA for the output stage. Figure 42 illustrates the small-signal performance of the 2-stage MPA over 1 GHz to 6 GHz frequencies. The linear gain (S21) of this amplifier was about 17.265 dB. The input (S11) and output (S22) return loss were 16.310 dB and 14.418 dB in the operating frequency band shown in Figure 42. Figure 43 shows a stability factor, K as a function of frequency for this two-stage MPA. At 2.4 GHz, a stability factor, K for this device is 2.419. The MPA is in unconditionally stable condition Figure 42. Small-signal characteristic of the two-stage 2.4 GHz medium power amplifier

Figure 43. Stability factor, K of two-stage 2.4 GHz medium power amplifier

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Figure 44 shows the output power and power gain as a function of input power for 2.4 GHz at the same bias condition. The output power at the 1 dB compression point (P1dB) is 14.862 dBm was obtained at -0.5 dBm input power. Figure 45 shows the power added efficiency, PAE as a function of fundamental output power at 2.4 GHz. Furthermore, it was found that the PAE of P1dB at 2.4 GHz was 12.318% at input power -0.5 dBm, exhibits a maximum PAE of 19.459% is achieved at input power 6 dBm. The two tone inter-modulation product, as shown in Figure 46 at 2.4 GHz two-stage power amplifier. The 3rd intermodulation distortion is 12.318 dBc with the single carrier output power level of 17 dBm. A 3.5 GHz Power Amplifier is shown in Figure 47.

Figure 44. Output power and power gain versus input power of the two-stage 2.4 GHz medium power amplifier

Figure 45. Power added efficiency versus input power for two stage 2.4GHz medium power amplifier

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Figure 46. 12.318 dBc of 3rd intermodulation distortion @F1=2.404 GHz, F2= 2.414 GHz for two-stage 2.4 GHz medium power amplifier

Figure 47. Circuit schematic of the two-stage 3.5 GHz medium power amplifier

Simulation Result of Two Stage Power Amplifier The bias condition for this design is 3 V and the drain current, IDS is 154 mA which includes approximately 74 mA for the first stage and 80 mA for the output stage. Figure 48 illustrates the small-signal performance of the 2-stage MPA over 1 GHz to 6 GHz frequencies. The linear gain (S21) of this amplifier was about 174.434 dB. The input (S11) and output (S22) return loss were 12.612 dB and 11.746 dB in the operating frequency band.

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Figure 48. Small-signal characteristic of the two-stage 3.5 GHz medium power amplifier

Figure 49. Stability factor, K of two-stage 3.5 GHz medium power amplifier

Figure 49 shows a stability factor, K as a function of frequency for this two-stage MPA. At 3.5 GHz, a stability factor, K for this device is 2.419. The MPA is in unconditionally stable condition. Figure 50 shows the output power and power gain as a function of input power for 2.4 GHz at the same bias condition. The output power at the 1 dB compression point (P1dB) is 14.862 dBm was obtained at -0.5 dBm input power. Figure 51 shows the power added efficiency, PAE as a function of fundamental output power at 2.4 GHz. Furthermore, it was found that the PAE of P1dB at 24 GHz was 12.318% at input power -0.5 dBm, a maximum PAE of 19.459% is achieved at input power 6 dBm.

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Figure 50. Output power and power gain versus input power of the two-stage 3.5 GHz medium power amplifier

Figure 51. Power added efficiency versus input power for two stage 3.5 GHz medium power amplifier

The two tone inter-modulation products is shown Figure 52. The 3rd intermodulation distortion is 12.264 dBc.

Implementation Layout for Single Stage Power Amplifier Figures 53, 54, 55 and 56 show the schematics and layouts of the 2.4 GHz and 3.5 GHz power amplifier.

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Figure 52. 12.264 dBc of 3rd intermodulation distortion @F1=3.505 GHz, F2= 3.515 GHz for two-stage 3.5 GHz medium power amplifier

Figure 53. Schematics of the 2.4 GHz single stage power amplifier distributed circuit

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Figure 54. Layout design for single stage 2.4 GHz power amplifier

Figure 55. Schematics of the 3.5 GHz single stage power amplifier distributed circuit

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Figure 56. Layout design for single stage 3.5 GHz power amplifier

Figure 57. Schematic of the 2.4 GHz two-stage power amplifier without microstriplines

Layout for Two-Stage Power Amplifier Figures 57, 58, 59, 60, 61 and 62 show the schematics and layouts of the 2.4 GHz and 3.5 GHz power amplifier.

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Figure 58. Schematic of the 2.4 GHz two-stage power amplifier distributed circuit

Figure 59. Layout design for two-stage 2.4 GHz power amplifier

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Figure 60. Schematic of the 3.5 GHz two-stage power amplifier

Figure 61. Schematic of the 3.5 GHz two-stage power amplifier distributed circuit

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Figure 62. Schematic of the 3.5 GHz two-stage power amplifier distributed circuit

Overall Result Simulation Result for 2.4 GHz MPA Tables 4 and 5 show the overall simulation result for the MPA operating at 2.4 GHz and 3.5 GHz respectively.

Table 4. Simulation result for 2.4 GHz MPA Parameter

Spec

Theoretical Result

Single stage

Single stage Distributed Circuit

Two stage

Two stage Distributed Circuit

Higher Linear Gain (dB)

24-30

20

8.261

8.384

17.650

17.265

Power Gain at 1 dB Compression Point (dB)

22-29

19

7.424

7.197

16.144

15.362

15

14.224

14.197

14.544

14.862

Pout at 1 dB Compression Point (dBm)

24-33

PAE at 1 dB Compression Point (%)

15-26

> 6.32

9.373

9.313

5.861

12.318

3rd Order Intermodulation (IM3)(dBc)

35-47

-

12.063

12.279

12.289

12.078

High Linearity,OIP3

-

-

-

-

-

-

Drain current Idd at 1 dB Compression Point (mA)

350-1000

< 300

78

77

157

160

Input return loss S11 (dB)

-10

< -10

-11.14

-10.65

-16.29

-16.31

Output return loss S22 (dB)

-10

< -10

-10.14

-9.66

-15.28

-14.42

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Table 5. Simulation result for 3.5 GHz MPA Parameter

Spec

Theoretical Result

Single stage

Single Stage Distributed Circuit

Two stage

Two stage Distributed Circuit

Higher Linear Gain (dB)

24-30

20

7.234

7.150

14.862

14.434

Power Gain at 1 dB Compression Point (dB)

22-29

19

6.129

6.046

13.377

12.665

Pout at 1 dB Compression Point (dBm)

24-33

20

14.329

14.046

14.477

14.665

PAE at 1 dB Compression Point (%)

15-26

> 9.9

9.088

8.549

5.809

11.796

3rd Order Intermodulation (IM3)(dBc)

35-47

-

13.076

11.162

9.884

12.264

High Linearity,OIP3

-

-

-

-

-

-

Drain current Idd at 1 dB Compression Point (mA)

350-1000

< 300

75

74

152

154

Input return loss S11 (dB)

-10

< -10

-10.64

-12.39

-15.13

-12.61

Output return loss S22 (dB)

-10

< -10

-12.56

-11.53

-13.21

-11.75

Comparison Result with Other Work Table 6 summarizes the performance of this work compared with other published different design approaches for 3.5 GHz power amplifier. It is shown that the PAE of this work is better than those of the amplifiers presented in (Cortese, 2006). However, the gain and P1dB proposed in (Cortese, 2006) achieved better than this work. This is because the proposed amplifier in this work utilized a different technology and design topology compared to (Cortese, 2006). Table 7 summarizes the performance of this work compared with other published different design approaches for 2.4 GHz power amplifier

Table 6. Comparison and summary of MPA performance for 3.5 GHz Parameter

This Work

(Cortese, 2006)

Process

0.15μm GaAs PHEMT

0.5μm GaAs PHEMT

Type

Two–stage

Two–stage hybrid

Frequency (GHz)

3.5

3.5

S21(dB)

14.4

17.0

PAE (%)

11.8

10.0

P1dB (dBm)

14.7

30.0

S11 (dB)

-12.6

-15.0

S22(dB)

-11.8

-10.0

Drain current Idd at 1 dB Compression Point (A)

0.154

1.2

Voltage Supply (V)

3

8

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The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

Table 7. Comparison and summary of MPA performance for 2.4 GHz Parameter

This Work

(Chu, C. K.)

Process

0.15μGaAs PHEMT

0.4μm GaAs PHEMT

Type

Two–stage

Two–stage

Frequency (GHz)

2.4

2.4

S21(dB)

17.3

29.8

PAE (%)

12.3

24.2

P1dB (dBm)

14.9

23.5

S11 (dB)

-16.3

-10.0

S22(dB)

-14.4

-16.6

Drain current Idd at 1 dB Compression Point (mA)

160

280

Voltage Supply (V)

3.0

3.3

CONCLUSION AND FUTURE WORK In this chapter, two-stage MPA operating at 2.4 GHz and 3.5 GHz respectively were designed for wireless application by using 0.15μm GaAs Power Pseudomorphic High Electron Mobility Transistor (PHEMT) technology with a gate width of 100 μm and 10 fingers has been presented. Software ADS was used in the designing process. It has been demonstrated that at a 3.0 V drain voltage, the amplifier has achieved 17.265 dB small-signal gain S21, input and output return loss of 16.310 dB and 14.418 dB, P1dB of 14.862 dBm with 12.318% power-added efficiency (PAE) for 2.4 GHz power amplifier. On the other hand, for 3.5GHz power amplifier, the amplifier has achieved 14.434 dB small-signal gain, input and output return loss of 16.310 dB and 14.418 dB, 14.665 dBm P1dB with 11.796% power-added efficiency (PAE). The designed MPA are in unconditionally stable condition due to the stability factor for the MPA are higher than 1 at the whole range of frequency. The die sizes of the amplifiers from the layout design are 1mm x 2.08mm and 1.07mm x 2.09mm for 3.4 GHz and 3.5 GHz MPA respectively. In order to improve the performance of the system and achieve a higher output power, the matching system should be designed in a specific way. So an interesting future work would be to improve the ADS model of the transistor by extracting its parameters and bias characteristics and then to redesign the power amplifier which should lead to a good improvement in the power performance.

REFERENCES Agilent Technologies. (2005). Agilent ADS 2005A. Momentum. Brattain, W. H. (1968, March). Genesis of the Transistor. The Physics Teacher, 109–114. doi:10.1119/1.2352401 Chu, C. K., Huang, H. K., Wang, C. C., Wang, Y. H., Hsu, C. C., Wu, W., et al. (2004). A 3.3 V selfbiased 2.4–2.5 GHz high linearity PHEMT MMIC power amplifier. In Proceedings of the 29th European Solid-State Circuits Conference, 2003 (pp. 667-670).

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Cortese, P., Akkul, M., Mayockl, J., Pilcherl, I., & Sanhaml, J. (2006). 3.5Ghz 10-Watt Power Amplifier for WiMax Application. In The 9th European Conference on Wireless Technology, 2006 (pp. 182-184). Cripps, S. C. (1983). A theory for the prediction of GaAs FET load-pull power contours. 1983 IEEE MTT-S International Microwave Symposium Digest (pp. 221-223). Cripps, S. C. (1999). RF Power Amplifier for Wireless Communications (pp. 45–72). Artech House, Inc. Deukhyoun, A. R. H., Moonkyun, M., Sutono, A., Kyutae, L., & Laskar, J. (2002). A 2.2-V operation, 2.4-GHz single-chip GaAs MMIC transceiver for wireless applications. 2002. IEEE MTT-S International Microwave Symposium Digest. IEEE MTT-S International Microwave Symposium, 2, 1019–1022. Edwards, T.C. & Wiley, J. (1987). Foundations of Microstrip Circuit Design. Golio, M. (2001). The RF and Microwave Handbook. Boca Raton, FL: CRC Press LLC. Kang, D. M., Lee, J. H., Yoon, H. S., Kim, S. J., Shim, J. Y., & Lee, K. H. (2002). Wideband 36- to 44- GHz MMIC Power Amplifier Using a 0.2-μm PHEMT Process. Journal of the Korean Physical Society, 41(4), 524–527. Lilienfeld, J. E. (1926, October). Method and Apparatus for Controlling Electric Current. U.S. Patent Application No. 17,451,745. Marsh, S. (2006). Practical MMIC Design (pp. 74–179). Artech House. Marzuki, A., et al. (2004). A Broadband RF Feedback Amplifier Design with Simple Feedback Network. RF and Microwave Conf. (pp. 1-4). Mondal, J. P. (1987, April). An Experimental Verification of a Simple Distributed Model of MIM Capacitors for MMIC Applications. IEEE Transactions on Microwave Theory and Techniques, 35, 403–408. doi:10.1109/TMTT.1987.1133662 Morkoc, H., & Solomon, P. M. (1984). The HEMT: A Superfast Transistor. IEEE Spectrum, 21(2), 28–35. Nader, C. (2006, June). Design Of A Power Amplifier Based On Si-LDMOS For WiMAX At 3.5GHz. Narayanaswami, S. (1998, May). The Design if a 1.9GHz 250mW CMOS Power Amplifier for DECT. Master’s Report, UC Berkeley. Pedro, J. C., & Carvalho, N. B. (2003). Intemodulation Distortion in Microwave and Wireless Circuits. Artech House. Rasmi, A., Marzuki, A., Azmi Ismail, M., Abdul Rahim, A. I., Razman Yahya, M., & Fatah Awang Mat, A. (2008). Design of 2-Stage Medium Power Amplifier Using 0.5 μm GaAs PHEMT for Wireless LAN Applications. In TENCON 2008 – 2008 IEEE Region 10 Conference (pp. 1-5). Smith, P. M., et al. (1987). Advances in HEMT Technology and Applications. In Proc.IEEE Microwave Theory Tech. Symposium, Las Vegas, NV, June 9-11 (pp. 749-752).

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Tian, Y. J., & Haigh, D. G. (2006). Investigation into RF Feedback for Improving the Efficiency-Linearity Trade-Off in Power Amplifiers. In Proceedings of Asia-Pacific Microwave Conference. Yamamoto, K., Moriwaki, T., Fujii, T., Otsuji, J., Miyashita, M., Miyazaki, Y., & Nishitani, K. (1999, April). A 2.4 GHz high efficiency SiGe HBT power amplifier with high-Q LTCC harmonic suppression filter. IEEE Journal of Solid-state Circuits, 34(4), 502–512. doi:10.1109/4.753683

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Chapter 7

The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA Ching Wen Yip Universiti Sains Malaysia, Malaysia

ABSTRACT LNA is an electronic amplifier that is required in receiver systems to increase the amplitude of the very low level signals from the antenna without adding too much noise. Software Advance Design System (ADS) was used to simulate the circuit and design the layout. LNA was designed using cascode topology with feedback techniques which produces better matching and unconditionally stable over the entire desired frequencies. For the 2.4 GHz operation, the amplifier achieves gain of 14.949 dB, noise figure of 1.951 dB and input reflection coefficient of -10.419 dB. With operating voltage supply at 3V, the total current consumption is 13 mA. For 3.5GHz amplifier, gain is 22.985 dB, noise figure is 1.964dB, input reflection coefficient is -12.427 dB and current consumption is 18 mA.

INTRODUCTION The LNAs to be designed are at 2.4 and 3.5 GHz. All these design can be applied in RF front end applications. Table 1 shows the LNA applications at a different frequency operation. The LNA specs that we have to achieve are shown in Box 1 and Table 2. The purpose of this chapter is to present the MMIC LNA design applicable to 0.15µm GaAs pHEMT technology. The chapter first covers LNA properties such as stability, gain, noise figure, etc. In addition, some LNA topologies are reviewed in this chapter. The next section of the chapter discusses the methodology in designing a LNA. Besides that, there is an analysis on topologies used in the LNA design and discuss on the advantages of the topologies. A later section includes a discussion on the simulation results between distributed circuit, lumped circuit, and using win components’ circuit. In addition, there is an implementation and discussion on layout. Finally, conclusions and suggestions are included in order to improve the performance of the LNA for future work. DOI: 10.4018/978-1-60566-886-4.ch007

Copyright © 2012, IGI Global. Copying or distributing in print or electronic forms without written permission of IGI Global is prohibited.

The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA

Table 1. Low noise amplifier applications Frequency

Applications

0.9 GHz

Cellular phone

2.4 GHz

WiFi

3.5 GHz

WiMax base station, W-CDMA

5.5 GHz

802.11a application, Hiperlan2 Portable WLAN

Table 2. Specifications Parameter

Typical Value

Stability

More than 1

Noise Figure, NF

0 dB - 2 dB

Associated Gain

16 dB – 23 dB

Input P1dB

More than -10 dBm

Input IP3

Less than 1 dBm

Drain Current, Idd at 1 dB Gain Compression Point

9 mA – 20 mA

Input Return Loss (S11)

- 10 dB

Output Return Loss (S22)

- 10 dB

Box 1. Operating conditions Operating Conditions: Vdd = (2.5 to 3) V

Impedance Matched Zin/Zout = 50Ω

Vbias = (-1 to 0) V

Pin = 0 dBm

BACKGROUND Receiver System Introduction In the receiver systems, there are signals received from the antenna. A receiver should have some requirements such as sensitivity, selectivity, and dynamic range in order to meet the design specifications. The sensitivity of a receiver is largely driven by the performance of its front -end low noise amplifier as shown in Figure 2. Sensitivity of a receiver is defined as the lowest available signal power that a receiver can detect output from the antenna for demodulation while providing an adequate signal-tonoise (SNR) (Rohde and Bucher, 1988). Selectivity is defined as the ability of a receiver to extract the desired signal in the presence of strong adjacent frequency interference and channel blockers. The ratio of the maximum signal to the minimum signal at the receiver input defines as dynamic range.

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Figure 1. Process of transmitting and receiving signal

Antenna The first block in the receiver chain is antenna. The antenna and low noise amplifier should be co-designed to achieve full transmission of power without reflection. However, it is difficult to design a high efficiency and matched antenna over a wide bandwidth. Thus, there are some alternatives in designing the antenna and low noise amplifier. One of the alternatives is matching issue.

Bandpass Filter Bandpass filter is required after the antenna in the receiver architecture. Bandpass filter can be implemented in active component or passive components. It must satisfy requirements like selectivity, wide dynamic range, and low noise. It is required to remove the out-of –band interference from entering the subsequence stages. Therefore, filter with sharp cut-off is needed to attenuate interference and select the desired channel.

LNA Low noise amplifier is the first gain element in the receiver chain. The incoming RF signal is amplified by the LNA while generated as little noise as possible in order to avoid RF signal loss. LNA must have low noise figure characteristic. Figure 2. Block diagram of a satellite receiver front-end

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The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA

LNA Properties In RF system, the analysis of the transistor stability, linearity, and proper matching network selection are required. To achieve a good amplifier with low-noise performance, it depends strongly on the required LNA device input impedances and the choice of impedance-matching topologies. For a low noise amplifier, matching for the input must be in the circles of constant noise figure. Besides that, the reduction in the signal due to losses during transmission, reception and power dissipation in circuit components must be compensated by using the low noise amplifier to provide sufficient gain for the receiver circuit. Stability Stability of an amplifier is major concern due to its potential for oscillation. We can determine the stability factor K by using scattering parameter (s-parameter) (Rollett, 1962). There are two types of stability. When the value of K > 1, this means that the transistor is unconditionally stable. Moreover, it will not oscillate no matter what impedances are presented to the input or output of the transistor. On the other hands, when the value of K < 1, the transistor is said to be operate in conditional stable state. It means the stability condition of a network is frequency dependent. It is possible for an amplifier to be stable at its design frequency but unstable at other frequencies. a. Unconditionally stable: the network is unconditionally stable if │Γin│< 1 and │Γout│<1 for all passive source and load impedances (i.e., │Γs│< 1 and │ΓL│<1). b. Conditional stability: the network is conditionally stable if │Γin│< 1 and │Γout│<1 only for a certain range of passive source and load impedances. This case is also referred to as potentially unstable. Therefore, we need to make sure the stability is more than 1 in all the entire frequencies range. 2

K=

2

1 − S11 − S22 + D 2 S12 S21

D = S11S22 – S12S21

2

(1) (2)

Impedance Matching When no matching is provided, the transistor has a much higher noise figure and potentially unstable over the entire frequencies range. Therefore, impedance matching is often a larger part of design process for a microwave component or system. It involves the efficient transfer of signals. Passive elements connected between the load and source is used to accomplish the matching. The resistance of the different parts of the circuit needs to be same or matched to obtain most efficient transfer of power from the source to the load. This is known as maximum power transfer theorem. The transmission line can be made to 50Ω but the impedances of active devices are seldom purely resistive. In fact, load impedances must be complex conjugate of the source impedances Zload = Zsource* to get maximum power transfer. Note that a positive reactance is inductive (jωL) whereas a negative reactance is capacitive (-j/ωc). The conjugate condition implies that they are equal and resonate at a frequency of fres= 2Πωres = 2Π/√LC. In the case of a lossless matching network, the perfect conjugate match condition implies that zero reflection at a single frequency.

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The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA

Based on the available power gain and noise figure circles in a Smith chart, one must select the load reflection coefficient ΓL that provides maximum gain and select source reflection coefficient ΓS to obtain the lowest noise figure. With ΓS = Γopt, lowest noise figure is achieved. In conditionally stable designs, the optimum reflection coefficient ΓS may fall into an unstable region in the source reflection coefficient plane. Once ΓS is selected, ΓL is selected for the maximum gain ΓL = ΓOUT and ΓL must again be checked to be in the stable region of the load reflection coefficient plane. In unconditionally stable designs, ΓL is  S ⋅ S Γ  ΓL S 22 + 12 21 opt   1 − Γopt ⋅ S11  • •

(3)

Zopt (Zee optimum) is the impedance presented to the input of the device that minimizes the noise figure. It can also be expressed as reflection coefficients (Γopt) (Gonzalez, G., 1984). ZGain (Zee gain) is the impedance presented to the input of the device that maximizes the gain (White, 2004).

If the active device were unilateral, S12 = 0 thus no feedback between the output port and the input port. The impedance for maximum gain would be S11*. 1-dB Compression Point (P1dB) 1-dB Compression Point (P1dB) is defined as the output power at which the output power of the network is 1dB less than it would have been had its input to output characteristic remain linear. It can be shown in Figure 4. Third Order Interception Point (IP3) Two input signals with equal amplitude frequencies, f1 and f2 are applied simultaneously to a nonlinear network. Figure 5 shows the outputs of the network contains frequency components at DC, f1, f2, 2f1, 2f2, (2f1-f2), (2f2-f1), 3f1, 3f2, and so forth. From the output, there are some components not harmonics of the input frequencies such as distortion products that fall at frequencies (2f1-f2) and (2f2-f1). The filtering does not work with the third order mixing products.

Figure 3. General matching circuit for transistor amplifier

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The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA

Figure 4. 1-dB Compression point, P1dB

Third order interception point, IP3 by applying two equal amplitude sinusoidal signals, while increasing their power. The power at the output of fundamental (either f1 or f2) and nth order inter-modulation product (either (2f1-f2) or (2f2-f1)) are plotted. In short, the harmonics grow with a slope equal to their harmonic number. The nth order intercept point IPn is defined in terms of the power levels of the power levels of fundamentals and the nth order products as extrapolated from their asymptotic small signal behavior. Noise Figure In the RF system, noise figure is a key performance. A low noise figure provides improved signal/noise ratio (SNR) for analog receivers, and reduces bit error rate in digital receivers. Noise figure represents the degradation in signal/noise ratio as the signal passes through a device. Figure 5. Two tone inter-modulation distortion

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The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA

Figure 6. Graph signal-to-noise

The noise figure of a system (see Figure 6) can be defined as: NF=

SNRin SNRout

 SNRin  = SNR in,dB – SNR out,dB NFdB = 10 log   SNRout 

(4)

When expressed in decibels the noise power ratio is called the noise figure, NF: Noise figure = NF = 10 log F

(5)

Transistors require an optimum source reflection coefficient, ΓOPT, or equivalently optimum source impedance, ZOPT, at their input in order to deliver lowest noise factor, FMIN. F = Fmin

(6)

Since source reflection coefficient (or equivalently, source impedance) is specified, the available gain design method is used for low noise amplifiers. If the source is not equal to ΓOPT, then the actual noise factor F of the amplifier is given by; | Γs − ΓOPT | Rn  Zo 1 − Γs 2  | 1 + ΓOPT |2   The noise factor contributions of each stage in a chain as in Figure 7:

F=FMIN +

F = F1 +

F2 − 1 F3 − 1 + G1 G1G2

(7)

(8)

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The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA

Figure 7. Noise factor of multistage LNA

If just two stages in a chain and the first stage gain G1 are high, it will make the second stage contribution small so that F will be mostly determined by F1 alone. A low-noise receiver almost invariably begins with a low-noise, high-gain RF amplifier. The noise factor F of a linear two-port network is the ratio of the available noise power at its output, PNO, divided by the product of the available noise power at its input, PNI, times the network’s numeric gain G. Thus, F=

PNO G PNI

(9)

LNA Topologies There are many topologies in LNA such as feedback topology, series inductive feedback, and cascode topology. Feedback topology and series inductive feedback is used in amplifier design to achieve unconditionally stable. DC bias injection includes self-biased topology and inductor as RF choke. Feedback Amplifier This output-to-input path can be used for several purposes such as to control output voltage, control gain, provide good input and output matches, and improve stability. The feedback topology give isolation between input and output at the desired band while maintaining high gain and low noise features of the circuit (Hossein, et al., 2003). It is achieved by connecting a resistor, capacitor, and inductor from the drain to the gate as shown in Figure 8. LFB introduces a degree of frequency dependence into the feedback loop but at low frequencies it has no effect. RFB controls the gain level whereas CFB is acts as a DC block. DC block is used to isolate the positive drain bias from negative gate bias. Series Inductive Feedback Series inductive feedback is placed between the HEMT source contact and ground as shown in Figure 9. It gives low noise figure and good input matching for a narrow-bandwidth system. It is frequently used to make the input impedance of the transistor more resistive and bring S11* closer to Γopt. It increases the stability factor but also decreases the gain slightly. Cascode Amplifer The cascode topology was invented to solve Miller effect (Miller, 1920) in triode amplifiers and used in transistor circuits (Gray, et al., 1969). Cascode topology is a combination of a common source HEMT

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The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA

Figure 8. Feedback topology

Figure 9. Series inductive feedback

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The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA

followed by a common gate HEMT as shown in Figure 10. Miller effect will affect the gain bandwidth product of the transistor. Cascode transistor provides some isolation between input and output that can increase the stability (Hossein, et al., 2003). Moreover, cascode topology is used to obtain high gain compared to common source amplifier. This is because the gain does not roll off as quickly versus frequency.

DESIGN Matching Matching is important to minimize power loss and improve signal to noise ratio. LG and LS are used as input matching components. Tuning is optimization. The tuning interface makes the design tasks simpler. This is shown in Figure 12.

Input Matching To obtain the input impedance before matching Zin’, S-Parameter simulation was performed. Input impedance before matching is the input impedance includes the feedback and Cgs impedance. Figure 10. Cascode topology

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The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA

For 3.5GHz Figure 13 shows the smith chart of S11 before input matching at 3.5 GHz frequency. From the Smith chart, Z in = Zo *

(0.752 − j 2.328) (0.752 − j 2.328)

= 50 * = 37.6 − j 116.4Ω

Figure 11. Input noise matching

Figure 12. Tune parameters in ADS

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The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA

Figure 13. Input impedance before matching in smith chart

From the Smith chart (Figure 14), Z in = Zo * Z N

= 50 * (0.721 − j 0.311) = 36.05 − j 15.55Ω

After the input matching network with inductor 4138.17pH (Lg), the imaginary part of the input impedance has significantly improved.

Output Matching To obtain the output impedance before matching, S-Parameter simulation was performed. The output impedance is shown in Figure 15. For 3.5GHz From the Smith chart,

(0.799 + j 2.136) 50 * (0.799 + j 2.136)

Zout = Zo *

= = 39.95 + j 106.8Ω

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The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA

Figure 14. Smith chart of Zin

Figure 15. Output impedance before matching in smith chart

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The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA

From the Smith chart (Figure 16),

(0.802 − j 0.262) 50 * (0.802 − j 0.262)

Zout = Zo *

= = 40.1 − j 13.1Ω

After the output matching network with capacitor 376.2fF, the output impedance has significantly improved.

Self-Biased Topology Transistor M2 used self-biased topology to remove the need for a bias voltage supply to the gate. Therefore, there is no need two voltages at the drain and gate. It just uses a single bias supply on the drain. This self-biased circuit can be achieved by placing a shunt resistor RS and capacitor CS from the source to ground as shown in Figure 17. RS is used to set voltage condition at M2 gate. CS is used to short RS at interested frequencies.

Others Factors A series capacitor CD and resistor RD at the drain of transistor M1 is shown in Figure 18. It is used to increase the stability network. Figure 16. Smith chart of Zout

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The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA

Figure 17. Self-biased topology

Resistor RG placed at the gate of transistor M1 to provide voltage to the device. While capacitor CG at the gate is used to eliminate any noise from the bias network (see Figure 19). All the above topologies are implemented in the LNAs design for frequencies 2.4 GHz and 3.5 GHz. To make sure the signal is fully grounded, there is a capacitor added parallel to the DC as shown in Figure 20. At 2.4 GHz, the gain can achieve the specification which is 16 dB until 23 dB. However, the gain value for 3.5 GHz does not meet the specification. This problem can be solved by cascading the design. Cascade topology can double the gain. A large value inductor need be to add to act as a RF chokes as Figure 18. Series RC topology

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The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA

Figure 19. Eliminate noise topology

Figure 20. Fully grounding signal topology

shown in Figure 21. The bias voltage at the gate terminal of the transistor at second stage must be zero volts so that the transistor is “ON”.

RESULTS 2.4 GHz Amplifier Using Win Components with MLIN Figures 24, 25, 26, 27, 28 and 29 show the performance of 2.4 GHz amplifier.

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The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA

Figure 21. Cascade topology

Figure 22. Graph stability versus frequency in distributed circuit

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The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA

Figure 23. Graph noise figure versus frequency in distributed circuit

Figure 24. Graph associated gain versus frequency in distributed circuit

OIP3 = Po +

[ IM3 / 2 ]

= 1.826 + (1.826 –  = 17.86 dBm

(−30.242)) / 2

IIP3 = OIP3 – gain = 17.86 – 14.949 = 2.911 dBm Table 3 shows the performance of 2.4 GHz amplifier with different type of components.

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The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA

Figure 25. Graph output return loss versus frequency in distributed circuit

Figure 26. Graph input return loss versus frequency in distributed circuit

Discussions: 1. The performance of win circuit without MLIN is slightly different from the performance with MLIN because the MLIN will act as a device too. 2. The high input and output return in the lumped circuit loss means that the matching is poor. 3. For the distributed circuit, the gain obtain are not within the range spec because there are a tradeoff between gain and noise figure. 4. The low current is suited for the LNA design because lower noise figure obtained. 5. Make sure the stability is more than 1 in all the entire range of frequencies. 6. Low noise figure is important to LNA because the function of LNA is to minimize the noise as low as possible.

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The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA

Figure 27. Graph drain current in distributed circuit, I_dd = 13 mA

Figure 28. Graph input IP3 in distributed circuit

7. The input at 1 dB has good linearity because the value obtained in the range of spec and the graph Pout versus Pin slope is not steeper. 8. For the win and distributed circuit, the output matching is good because the output return loss is at the sharpest point of the graph. It means that the loss is minimized. 9. For the distributed circuit, the input matching is more suitable for frequency 2.6 GHz than 2.4 GHz because at that frequency the input return loss is the best.

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The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA

Figure 29. Graph input P1dB in distributed circuit

Table 3. Overall performances for 2.4 GHz Parameter Stability

Typical Value

Ideal Components

Win Components without MLIN

Win Components with MLIN

More than 1

2.595

3.892

3.710

Noise Figure, NF

1.5dB-2dB

1.489dB

1.968dB

1.951dB

Associated Gain

16dB-23dB

16.394dB

15.176dB

14.949dB

More than -10dBm

-7.0dBm

-5.6dBm

-5.4dBm

Less than 1dBm

3.1545dBm

3.5585dBm

2.911dBm

9mA-18mA

13mA

13mA

13mA

Input Return Loss (S11)

Less than -10dB

-4.230dB

-8.313dB

-10.419dB

Output Return Loss (S22)

Less than -10dB

-6.978dB

-19.844dB

-18.912dB

Input P1dB Input IP3 Drain current, Idd at 1dB Gain Compression Point

3.5 GHz Amplifier The two stages amplifier is formed by cascading the first stage. It can achieve unconditionally stable condition because the stability is more than 1 in all the entire frequencies range at the first stage, as well as the second stage too. The stability at point 3.5 GHz after cascade is 15.202. LNA design achieved a gain of 22.985 dB while consuming 18 mA of current which is still in spec 18mA. The input and output return loss is -12.427 dB and -19.713 dB respectively. The noise figure is 1.964dB and the input third order interception point (IIP3) is -6.757 dBm. Figures 30, 31, 32, 33, 34, 35, 36 and 37 show the performance of 3.5 GHz amplifier.

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The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA

Figure 30. Graph stability versus frequency in distributed circuit

Figure 31. Graph noise figure versus frequency in distributed circuit

OIP3 = Po +

[ IM3 / 2 ]

= − 3.038 + (−3.038 –  = 16.2275 dBm IIP3 = OIP3 – gain = 16.2275 – 22.985 = − 6.7575 dBm

178

(−41.569)) / 2

The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA

Figure 32. Graph associated gain versus frequency in distributed circuit

Figure 33. Graph output return loss versus frequency in distributed circuit

Figure 34. Graph input return loss versus frequency in distributed circuit

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The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA

Figure 35. Graph drain current in distributed circuit, I_dd = 18 mA

Figure 36. Graph input IP3 in distributed circuit

Table 4 shows the performance of 3.5 GHz amplifier with different type of components. Discussions: 1. The performance of win circuit without MLIN is slightly different from the performance with MLIN because the MLIN will act as a device too. 2. There must be some element loss in the win design kit components because it is not an ideal component. The two stage design is a cascade of the single stage. The overall noise figure should obey the well known law given in equation below (Fukui, 1981).

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The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA

Figure 37. Graph input P1dB in distributed circuit

Table 4. Overall performances for 3.5 GHz amplifier Parameter

Typical Value

Lumped Components

Win Components without MLIN

Win Components with MLIN

Stability

More than 1

4.483

11.724

15.202

Noise Figure, NF

1.5dB-2dB

1.242dB

1.912dB

1.964dB

Associated Gain

16dB-23dB

31.250dB

26.893dB

22.985dB

More than -10dBm

-21.6dBm

Input P1dB Input IP3

Less than 1dBm

Drain current, Idd at 1dB Gain Compression Point

-18.6dBm

-14.8dBm

-9.7615dBm

-6.7575dBm

9mA-18mA

18 mA

18 mA

18 mA

Input Return Loss (S11)

Less than -10dB

-5.877dB

-12.214dB

-12.427dB

Output Return Loss (S22)

Less than -10dB

-8.273dB

-22.347dB

-19.713dB

F = F1 +

F2 −1 G1

NF 2 − 1 G1 1.862 − 1 = 1.862 + 12.034 = 1.934dB

NF = NF 1 +

The total noise figure from the simulation is 1.964 dB. It is more than the total value calculated because NA is not included in the input of second stage.

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The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA

Figure 38. Layout design for 2.4 GHz

4. For the distributed circuit, the input return loss can be considered good matching because the S (1, 1) value is -12.427 dB which is almost near the sharpest point. 5. The noise figure increased with the frequency. 6. The associated gain obtained is good because the highest gain point almost near frequency 3.5 GHz. It means that the LNA design is suited for this frequency. Besides that, there is a sudden decrease at frequency 2 GHz and can be determine that the design is tend to be not suitable for that frequency. 7. It is in unconditionally stable condition because the stability is more than 1 dB at all the entire frequencies range. 8. The output return loss in the distributed circuit at frequency 3.6 GHz has less loss than frequency 3.5 GHz. Therefore, the output matching is fit for 3.6 GHz.

Implementation Layout design must be performed because we need to transform the schematic design to physical representation. It is required for chip fabrication. The layout size for 2.4 GHz is 1.65 mm x 1.38 mm (Figure 38). For the 3.5 GHz, the layout size is 2.86 mm x 1.57 mm (Figure 39).

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The Design and Modeling of 2.4 GHz and 3.5 GHz MMIC LNA

Figure 39. Layout design for 3.5 GHz amplifier

CONCLUSION The monolithic microwave integrated circuit low noise amplifier specified at frequency 2.4 GHz and 3.5 GHz are designed using 0.15µm GaAs pHEMT technology are presented. Simulation and design layout are done by using software advance design system (ADS). The matching for a lumped circuit and using win design kit components circuit are different. This is because the ideal components have no loss. However, the win design kit components have losses. For example, the spiral inductor will cause losses because of the parasitic of layout. Therefore, after the lumped circuit is replaced with win circuit, the matching network for lumped circuit cannot be used for the win circuit.

REFERENCES Agilent Technologies. (2005). Agilent ADS 2005A: SPARAM Azmi Ismail, M., Abdul Rahim, A. I., Kushairi, N., Rasmi, Sanusi, R.,Marzuki, A., Razman Yahya, M., & Fatah Awang Mat, A. (n.d.). Telekom Research & Development Sdn Bhd, 0.15µm GaAs pHEMT Cascode Low Noise Amplifier (LNA) for Wireless Applications. Cazaux, J.-L. (1994). MMICs for Space-Bourne Applications: Status and Prospectives. GaAs IC Symposium. Chan, A. N. L., Guo, C. B., & Luong, H. C. (2001). A 1V 2.4GHz CMOS LNA with Source Degeneration as Image-Rejection Notch Filter. The 2001 IEEE International Symposium on Circuits and Systems (pp. 890-893). Sydney, Australia.

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Cronin, G. R., & Haisty, R. W. (1964). The Preparation of Semi-Insulating Gallium Arsenide by Chromium Doping. Journal of the Electrochemical Society, 111, 874–877. doi:10.1149/1.2426273 Edwards, T. C. (1981). Foundations of Microstrip Circuit Design. New York: John Wiley. Fukui, H. (Ed.). (1981). Low-Noise Microwave Transistors and Amplifiers. New York: IEEE Press. Gonzalez, G. (1984). Microwave Transistor Amplifiers. Upper Saddle River, NJ: Prentice Hall. Gray, P. E., & Searle, C. L. (1969). Electronic Principles: Physics, Models, and Circuits (pp. 523–524). New York: Wiley. Gupta, K. C. (1996). Microstrip Lines and Slotlines (2nd ed.). Norwood, MA: Artech House. Henderson, T. (1986). Microwave Performance of a Quarter- Micrometer Gate Low- Noise Pseudomorphic InGaAs/ AlGaAs MODFET. IEEE Electron Device Letters, 7, 645–651. doi:10.1109/EDL.1986.26507 Hossein, S., Lavasani, M., & Kiaei, S. (2003). A New Method to Stabilize High Frequency High Gain CMOS LNA. In Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and System (pp. 982-985). Kushairi, N., Marzuki, A., Azmi Ismail, M., Sanusi, R., Rasmi, A., Ahmad Ismat, A.R, Sauli, Z., & Md Shakaff, A.Y. (n.d.). Telekom Research & Development Sdn Bhd, GaAs pHEMT Cascode Low Noise Amplifier for Wireless Applications. Miller, J. M. (1920). Dependence of the Input Impedance of a Three- Electrode Vacuum Tube upon the Load in the Plate Circuit. Scientific Papers of the Bureau of Standards, 15(351), 367–385. Mondal, J. P. (1987). An Experimental Verification of a Simple Distributed Model of MIM Capacitor for MMIC Applications. IEEE Transactions on Microwave Theory and Techniques, 35, 403–408. doi:10.1109/TMTT.1987.1133662 Mullin, J. B., Stranghan, B. W., & Brickell, W. S. (1965). Journal of Physics and Chemistry of Solids, 26, 782. doi:10.1016/0022-3697(65)90034-X Postoyalko, V. (1986). Green’s Function Treatment of Edge Singularities in Quasi-TEM Analysis of Microstrip. IEEE Transactions on Microwave Theory and Techniques, 34(11), 1092–1095. doi:10.1109/ TMTT.1986.1133504 Robertson, I. D., & Lucyzyn, S. (2001). RFIC and MMIC design and technology. Rohde, U., & Bucher, T. (1988). Communication Receivers Principles and Design. McGraw-Hill. Rollett, J. M. (1962). Stability and Power-Gain Invariants of Linear Twoports. I.R.E. Trans. Circuit Theory. Shaeffer, D. K., & Lee, T. H. (1997). A 1.5V, 1.5GHz CMOS Low Noise Amplifier. IEEE Journal of Solid-state Circuits, 32(5), 745–759. doi:10.1109/4.568846 White, J.F. (2004). Approach Increases Amplifier Gain. Microwaves RF, ED Online ID #8835, September 2004.

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Chapter 8

Design of Medium Power Amplifier Using GaAs PHEMT Technology for Wireless Applications Amiza Rasmi Telekom Malaysia Research & Development Sdn. Bhd., Malaysia

ABSTRACT This paper presents the design of single-stage and two-stage medium power amplifiers (MPAs) using GaAs PHEMT technology for the wireless applications. The single-stage MPA was designed using 0.15 μm GaAs PHEMT technology to be operated at 3.5 GHz whereas the two-stage MPA was designed using 0.5 μm GaAs PHEMT technology to be operated at 5.8 GHz. The MPAs employ a simple RC feedback in order to linearize the stages as well as to improve the circuit stability and to control the gain. In addition, the load-pull technique was used in order to define the optimum load and maximum output power. Therefore, the performance of the proposed amplifier in this paper is discussed in terms of stability, gain, power-added efficiency (PAE), and output power. The simulated data of the proposed MPAs is then compared with the measured data of the fabricated MPAs.

INTRODUCTION The wireless communications industry has grown rapidly in recent years. In any wireless communication, the transmitter is a one part of this system. As the last stage of amplification in the transmitter chain, the power amplifiers (PAs) are a critical and most challenging component in a transmitter system as shown in Figure 1; where the signal should be at a high level to cross the desired distance. DOI: 10.4018/978-1-60566-886-4.ch008

Copyright © 2012, IGI Global. Copying or distributing in print or electronic forms without written permission of IGI Global is prohibited.

Design of Medium Power Amplifier Using GaAs PHEMT Technology for Wireless Applications

Since they are designed to drive a large power into a load such as an antenna or a transmission line by the supply circuit, PAs are frequently the most power-hungry Radio Frequency (RF) component, often dominating the power dissipation of an entire transceiver (Razavi, 1998). The PA, which is a critical element in a transmitter system, is expected to provide a suitable output power at a very good gain with high efficiency and linearity so they cannot be approximated as small signal devices. The efficiency considerations lead to various classes of power amplifier such as Class A, B, and AB are linear power amplifiers, whereas Class C, D, and E are nonlinear power amplifiers. The output power of a PA must be sufficient to get a reliable transmission. High gain reduces the number of stages in an amplifier that are required to deliver the desired output power, hence reduces the size and manufacturing cost. On the other hand, thermal management, battery lifetime and operational costs are improved by high efficiency. In addition, good linearity is necessary for bandwidth efficient modulation (Cripps, 1999). All these requirements make a tradeoff and an optimization is needed for a typical power amplifier design. This paper will thoroughly discuss the design of a medium power amplifier (MPA) using 0.15 μm and 0.5 μm GaAs PHEMT technology. The Gallium Arsenide (GaAs) Pseudomorphic High Electron Mobility Transistor (PHEMT) has good performances on the frequency range, noise figure, output power, and high efficiency with low distortion (Weitzel, 2003; Huang, Lee, & Chen, 2005; Platzker, & Bouthillete, 1995; Komiak, Wang, & Roger, 1997). Because of its superior performance over the metal oxide semiconductor (MOS) transistors, GaAs transistors have been used extensively to build the Radio Frequency (RF) power amplifiers and play an important role in the wireless communications. PHEMT power amplifiers are making serious inroads into handset cellular (800 MHz to 2.3 GHz) and Wireless LAN (WLAN) (2.4 GHz to 5.85 GHz) applications (Fujii, Morkner, & Brown, 2004). The IEEE 802.11 WLAN standards have extended the frequency band from 2.4 GHz to 5 GHz bands in order to increase the data transmission rate. The new generation of 802.11a WLAN and HiperLAN/2 standards operating in the 5 GHz spectrum using OFDM modulation are becoming popular due to high speed, greater system capacity and low interference (IEEE Draft Supplement to IEEE Standard 802.11., 1999). Each of these standards requires a power amplifier as the final amplification block of the transmitter and each of them allows a specific maximum output power generated by the power amplifier. Therefore, the application ambit this power amplifier is the key component for researching the advance systems of WLAN and other wireless network systems. A start-of-the-art power amplifier design has to meet the system requirements for high gain, high efficiency and meet the desired output power while the device and process technology of choice plays a crucial role in realizing a working system. The operating frequency for the proposed MPA in this work Figure 1. Power amplifiers are used at the output of transmitter (Queen’s Learning Wiki, 2008)

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Design of Medium Power Amplifier Using GaAs PHEMT Technology for Wireless Applications

are 3.5 GHz and 5.8 GHz. GaAs-based devices have been found to be more suitable for high power applications with higher efficiency and better linearity than those of Si devices (Lan, Johnson, Knappenberger, & Miller, 2002). In addition, the GaAs technology has lower R&D cost than CMOS R&D cost, and it is another factor that lures companies to use the technology in power amplifier design (Meng, & Wu, 2008). The performance of the proposed amplifier will be discussed in terms of stability, gain, power-added efficiency (PAE), and output power.

STUDY ON EFFECT OF FEEDBACK IN POWER AMPLIFIER DESIGN Feedback is an important concept in circuit design, where a signal or voltage derived from the output is superimposed on the input. This output-to-input path can be used for several purposes such as to control output voltage, to control gain, to reduce distortion, to improve stability, or to create instability, as in an oscillator (Breed, 2006). The RC feedback that was used in this proposed MPA design is to linearize the stages as well as to improve the circuit stability and increases the bandwidth.

Stability vs. RC Feedback One of the design constraints in the power amplifier design is stability. Stability or resistance to oscillation in a microwave circuit can be determined by the S-parameters. Oscillations may exist in a two-port network if either or both the input and the output port have negative resistance. This condition occurs when the magnitude of the input or output reflection coefficients is greater than one, |Γin|>1 or |Γout |>1. Stability for an amplifier can be classified in two types, unconditionally stable and conditionally stable. In the former, the real part of the input and output impedances of the amplifier is greater than zero for all passive load and source impedances. However, the amplifier is said to be conditionally stable or potentially unstable if the real part of the input or output impedances of the amplifier is less than zero for at lest a passive load or source impedances. The stability test should be done for every frequency in the desired range. The Rollet’s stability factor, K (Rollett, 1962; Meys, 1990; Lombardi, & Neri, 1999) is based on the two-port S-parameter matrix. In general, the two necessary and sufficient conditions to guarantee unconditional stability (meaning no possibility of oscillation when the input and output of the device are both terminated in any passive real impedance) are: (a) K > 1 and (b) |Δ| < 1 where 2

K =

2

1 − S11 − S 22 + ∆ 2 S12 × S 21

2

>1

and ∆ = S11 × S 22 − S12 × S 21 < 1

(1) (2)

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Design of Medium Power Amplifier Using GaAs PHEMT Technology for Wireless Applications

In practice, most of the microwave transistor amplifiers are potentially unstable because of the internal feedback. There are two ways to overcome the stability problem of the transistor amplifier. Firstly is to use some form of feedback to stabilize the amplifier. Secondly is to use a graphical analysis such as the stability circles (Doudorov, 2003; Nader, 2006) in order to determine the regions where the values of ΓS and ΓL (source and load reflection coefficients) are less than one, which means the real parts of ZIN and ZOUT are positive. It is a useful tool to avoid the unstable area when designing the matching networks with a Smith chart. In this work, a feedback is employed in the circuit in order to overcome the stability problem. Figure 2 shows the feedback topology that is used in the MPA circuit. The capacitor, CF and resistor, RF are added between the drain and the gate of transistor providing an RC feedback or commonly known as negative feedback (Kang, Lee, Yoon, Kim, Shim, & Lee, 2002) in order to produce broadband match and also to increase the stability of the device; thus the amplifier is always unconditionally stable. Amplifiers without RC feedback have a tendency to be rather unstable. The effect of an unstable amplifier is the output becomes distorted in an unpredictable and random way. Another advantage of employing this feedback is the properties of the circuit can be made to depend primarily on the values of the feedback circuit elements and to be more-or-less independent of the particular characteristics of the active device (such as transistor β, bias current, etc.). As shown in Figure 2, resistor RF forms the feedback and capacitor CF is added to allow independent biasing of the gate and drain of the transistor. CF can normally be chosen so that it is large enough to be a short circuit over the frequency of interest. In addition, the effect of feedback is to make the input and the output impedances to be more convenient for matching. Power amplifiers utilizing resistor as a Figure 2. Feedback topology (Rasmi, Azmi Ismail, Abd Rahim, Marzuki, Razman Yahya, & Fatah Awang Mat, 2007; Rasmi, Marzuki, Azmi Ismail, Abdul Rahim, Razman Yahya, & Fatah Awang Mat, 2008)

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feedback is discussed in Tian & Haigh (2006) and Marzuki, et.al. (2004). The input and output impedances of the amplifier with feedback (the closed-loop amplifier) become sensitive to the gain of the amplifier without feedback (the open-loop amplifier); that exposes these impedances to the variations in the open loop gain, for example, due to parameter variations or due to nonlinearity of the open-loop gain. From Figure 1, the closed-loop gain, AV is given as below (Rasmi, Marzuki, Azmi Ismail, Abdul Rahim, Razman Yahya, & Fatah Awang Mat, 2008); AV = −

1   GF ( 1 + 1 )   AOL 1  +   GS AOL      

where GF, GS, AOL is the conductance of feedback resistance, conductance of source resistance and openloop gain respectively. The closed-loop gain will be equal to an open-loop gain if GF approaches zero. An amplifier with the resistor feedback can achieve self matching (Marzuki, et.al., 2004).

Result and Discussion Feedback is used to control gain and to reduce distortion, as well to provide other important functions in modern electronic designs. In this work, a 0.15µm GaAs PHEMT single-stage MPA and 0.5µm GaAs PHEMT 2-stage MPA using a simple RC feedback amplifier to operate at 3.5 GHz and 5.8 GHz were designed. The RC feedback in amplifiers is commonly used to improve the circuit stability and also linearity. The stability of the circuit is increased by feeding a small fraction of the output to the input which results a change in phase and a decrease of gain amplifier. The Rollet’s stability factor, K, for the proposed MPAs was obtained using ADS simulator (Agilent Technologies, 2008) for a different bias condition and frequencies operation. K is established by deriving a set of S-parameters from measured data and simulated data. i.

3.5 GHz Single-stage MPA using 0.15μm GaAs PHEMT Technology: The single-stage MPA was designed and fabricated using 0.15 μm GaAs PHEMT technology to be operated at 3.5 GHz. The Rollet’s stability factor of this proposed MPA is shown in Figure 3. The simulated stability factor is compared with measured data.

Figure 3 shows the Rollet’s stability factor, K, as a function of frequency for the single-stage MPA with the bias condition is 3 V of supply voltage, VDD and 0V of gate voltage, VGS. This single-stage MPA has achieved a stability factor, K of 1.25 for simulated data and 1.37 for measured data at 3.5 GHz, respectively. ii. 5.8 GHz 2-stage MPA using 0.5μm GaAs PHEMT Technology: The two-stage MPA was designed using 0.5 μm GaAs PHEMT technology to be operated at 5.8 GHz. The Rollet’s stability factor of this proposed MPA is shown in Figure 4. The simulated stability factor is compared with measured data.

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Figure 3. Rollet’s stability factor, K versus frequency of the 3.5 GHz single-stage MPA using 0.15μm GaAs PHEMT technology

Figure 4 shows the Rollet’s stability factor, K, as a function of frequency for the 2-stage MPA with the bias condition is 5 V of supply voltage, VDD and 0V of gate voltage, VGS. This 2-stage MPA has achieved a stability factor, K of 1.82 for simulated data and 13.60 for measured data at 5.8 GHz, respectively. From this result, the K factor value for the measured data is very high than simulated data. These two result shows that the circuit is unconditionally stable over the frequency because the stability factor of this amplifier is more than 1. If the K factor is greater than unity at the frequency and bias level, then expressions for matching impedances at input and output can be evaluated to give a perfect conjugate match for the device. Amplifier design in this context is mainly a matter of designing matching networks, which present the prescribed impedances over the necessary specified bandwidth. If the K factor is less than unity, negative feedback or lossy matching must be employed in order to maintain an unconditionally stable design. The Rollet’s stability factor, K of these circuits is depending on the RC feedback that was employed in the circuit as shown in Figure 2. There are cases where a device has a very high K factor value as showed in the Figure 4, but very low gain in conjugate matched condition. The physical cause of this can be traced to a device, which has gain roll-off due to the carrier-mobility effects, rather than parasitics. In such cases, introduction of some positive feedback reduces the K factor and increases the gain in conjugately matched conditions, while maintaining unconditional stability.

STUDY AND SIMULATION ON MATCHING IMPEDANCE OF POWER AMPLIFIER In many types of amplifier, matching networks are used to avoid standing wave problem (Doudorov, 2003). Matching networks can be built from passive components like strip lines, inductors, and capacitors. The source impedance is generally 50Ω and to make a proper transformation, matching network is needed between this source and the input of power amplifier. Similarly, another matching network

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Design of Medium Power Amplifier Using GaAs PHEMT Technology for Wireless Applications

Figure 4. Rollet’s stability factor, K versus frequency of the 5.8 GHz 2-stage MPA using 0.5μm GaAs PHEMT technology

is needed between the output and the load impedance. With the help of matching networks, maximum gain and output power can be achieved. In this work, the “Load-Pull” technique is used to obtain a proper matching. In load-pull technique, the output impedance seen by the amplifier is swept and the amplifier performance is measured. Similarly, in source pull technique, the input impedance is swept while the performance of the amplifier is measured. From the results of these two simulations, desired source and load impedances are found. These desired impedances are illustrated in Figure 5. The designer may need to choose an optimum impedance value to reach the optimum efficiency, power and gain levels. If these desired impedances are obtained, power amplifier will give the best performance. The load impedance value found by load pull is required in order to have the maximum efficiency. On the other hand, source pull is helpful to suppress the second harmonic effects.

Output Matching Analysis using Load-Pull Simulation Load pull matching technique gives the optimal output load impedance to achieve optimum efficiency and output power values by sweeping the impedance. Nowadays, the load-pull technique is used in the advanced CAD tools in order to simulate the optimal load impedance. The concept used for the simulation is the same as the one used in measurement. The source and load reflection coefficients are calculated as a function of gain and output power. The power and efficiency contours can be generated empirically by connecting various loads to the amplifier and by measuring the gain and the output power at each value of the load impedance. Maximum output power delivered is more concerned than the gain. In power amplifier design, to achieve high accuracy and maximum power transmission, a matching network is required on the input and output in order to minimize the reflection problems. Input matching

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Design of Medium Power Amplifier Using GaAs PHEMT Technology for Wireless Applications

Figure 5. Load and Source Impedance for maximum efficiency (Tonga Karakaş, 2007)

Figure 6. Large-signal model of PHEMT (Rasmi, Marzuki, Azmi Ismail, Abdul Rahim, Razman Yahya, & Fatah Awang Mat, 2008)

network and output matching network provide proper transformation of impedance between source (50 Ohm) and the PA as well as between PA and load, in order to achieve maximum gain and output power. The first matching network for power amplifier is the output matching where this network is designed to transfer the maximum output power from transistor to the 50 Ohm system. The output matching network provides the final stage with optimum load impedance for maximum output power across the band. The required optimum large-signal load impedance Zopt is determined from load-pull simulation using ADS simulator based on the large-signal model of PHEMT as shown in Figure 6. The model is extracted based on the measurement data. Then, the input network is designed to flatten the small signal gain and to improve impedance matching for better input return loss. i.

192

3.5 GHz Single-stage MPA using 0.15μm GaAs PHEMT Technology: In this work, a singlestage MPA using 0.15μm GaAs PHEMT technology to operate at 3.5 GHz was designed. As mentioned previously, maximum output power can be obtained by having optimum load impedance, Zopt, thus the load-pull simulation based on the large-signal PHEMT model is used in order to find the value of Zopt. Figure 7 shows the optimum load impedance, Zopt for transistor that was used in this MPA design. The maximum PAE and output power delivered from this circuit are

Design of Medium Power Amplifier Using GaAs PHEMT Technology for Wireless Applications

Figure 7. Simulated load impedance, Zopt at 3.5 GHz

shown in these results. In addition, Smith Chart shows the output impedance where these maximum values can be delivered. The value of Zopt achieved is 8.394 + j0 Ohm with a maximum power-added efficiency (PAE) of 46.84% and a maximum power delivered of 27.69 dBm. This Zopt was obtained at 3.5 GHz operating frequency with the input power of 16 dBm and a bias condition is 3 V of supply voltage and 0 V of gate voltage. ii. 5.8 GHz 2-stage MPA using 0.5μm GaAs PHEMT Technology: In this work, a 2-stage MPA using 0.5µm GaAs PHEMT process to operate at 5.8 GHz was designed. As mentioned previously, maximum output power can be obtained by having an optimum load impedance, Zopt, thus the loadpull simulation based on the large-signal PHEMT model is used in order to find the value of Zopt. Figure 8 shows the optimum load impedance, Zopt for transistor that was used in the last stage of this MPA design. The maximum PAE and output power delivered from this circuit are shown in these results. In addition, Smith Chart shows the output impedance where these maximum values can be delivered. The Zopt for the transistor at the final stage of this 2-stage MPA is 40.054 + j 17.199 Ohm with a maximum power-added efficiency (PAE) of 35.70% and a maximum power delivered of 24.29 dBm. This Zopt was obtained at 5.8 GHz operating frequency with the input power of 10 dBm and a bias condition is 5 V of supply voltage and 0 V of gate voltage.

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Figure 8. Simulated load impedance, Zopt at 5.8 GHz

Power Amplifier Performance and Discussion Power amplifier design strongly depends on the operating frequency and applications, as well as on the available device technology in the market. The performance of the proposed amplifier in this work will be discussed in terms of small-signal analysis, power gain, power-added efficiency (PAE), and output power. i.

3.5 GHz Single-stage MPA using 0.15μm GaAs PHEMT Technology: Figure 9 shows the schematic drawing of 3.5 GHz single-stage MPA using 0.15 µm GaAs PHEMT. It is the schematic of the whole amplifier including the feedback topology, input matching network, and the output matching network. The inductor LG as shown in Figure 9 provides the desired input impedance. The capacitor CC, a DC block capacitor, is also used for output matching network. The output is matched for high output power. Based on these essential matching networks, optimizations and simulations were performed to achieve the required circuit performance.

A single-stage MPA presented herein consists of a single amplification stage with the gate peripheries are 10x100 µm. The estimation of the required transistor size is an iterative process using the DC characteristics of the transistor. Figure 10 shows the layout for 3.5 GHz single-stage MPA. This layout, completed with a launch pad, was fabricated in Taiwan using 0.15μm GaAs PHEMT technology. The chip size is 1.2 mm x 0.7 mm. All the passive components were integrated on-chip. This process uses a backside via-ground method, which eliminates the need for wire bonding to the ground. The performances of 3.5 GHz single-stage MPA were measured on-wafer using microprobe station and ADS simulator was used extensively to predict the performances. The frequency was swept from 1

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Design of Medium Power Amplifier Using GaAs PHEMT Technology for Wireless Applications

Figure 9. Schematic of 3.5 GHz single-stage MPA using 0.15 µm GaAs PHEMT

Figure 10. A fabricated 3.5 GHz single-stage MPA chip

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Design of Medium Power Amplifier Using GaAs PHEMT Technology for Wireless Applications

GHz to 6 GHz, and the bias condition is 3 V of the supply voltage, VDD and a gate voltage, VGS is 0 V. The simulated drain current, IDS is 78.0 mA and the measured drain current, IDS is 80.7 mA. The power consumption of the circuit is 234.0 mW and 242.1 mW was obtained for simulation and measurement, respectively Figure 11 illustrates the simulated and measured data for input return loss (S(1,1)) and output return loss (S(2,2)) of the single-stage MPA over 1 GHz to 6 GHz frequencies with the same bias condition and operating frequency. At 3.5 GHz, the input return loss of 18.10 dB was obtained for simulation and 14.11 dB was obtained for measurement. In addition, the output return loss of 10.35 dB and 12.38 dB was achieved at 3.5 GHz for simulation and measurement, respectively. The measured data for output return loss of this circuit is better than simulated data. In addition, this circuit is internally matched because the input and output return loss is more than 10 dB. Figure 11. Simulated and measured data of input return loss and output return loss as a function of frequency for 3.5 GHz single-stage MPA

Figure 12. Simulated and measured data of small-signal gain as a function of frequency for 3.5 GHz single-stage MPA

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Figure 12 shows the small-signal gain as a function of frequency for simulated and measured data. The small-signal gain of 11.36 dB and 8.34 dB are achieved for simulation and measurement at 3.5 GHz. The measurement data has a lower gain about 3dB different than simulation data. The big variation of gain beyond 2.5GHz might due to other effects and now still under investigation. Figure 13 shows the measured power-added efficiency (PAE), output power (Pout) and power gain as a function of input power for 3.5 GHz MPA at the same bias condition. This MPA circuit was achieved an output power, Pout of 16.81 dBm at 1dB compression point (P1dB) with the input power, Pin of 10 dBm. From -10 dBm to 9 dBm, this amplifier shows a linear Pin-Pout characteristic and no gain compression until Pin reaches 10 dBm and the output power starts to saturate from 12 dBm of input power. The power gain of 6.81 dB was obtained at 10 dBm input power. In addition, this single-ended MPA exhibits a power-added efficiency (PAE) of 16.74% at P1dB. Table 1 summarizes the performance of this work compared with previously reported 3.5 GHz power amplifiers. It is shown that the power gain and return loss of this work is better than those of the amplifiers presented in Chu, Huang, Liu, Chiu, Lin, Wang, & Wang (2004) and Nader (2006). However, the PAE and P1dB proposed in Chu, Huang, Liu, Chiu, Lin, Wang, & Wang (2004) achieved the best value than this work but the PAE of this work is better than Nader (2006) whereas the P1dB proposed in Nader (2006) is better than this work. This is because the proposed amplifier in this work utilizes different technology and design topology compared to Chu, Huang, Liu, Chiu, Lin, Wang, & Wang (2004) and Nader (2006). The proposed amplifier in Chu, Huang, Liu, Chiu, Lin, Wang, & Wang (2004) and Nader (2006) is a 2-stage cascade amplifier using AlGaAs/InGaAs/GaAs technology while a single-stage amplifier is proposed in Platzker, & Bouthillete (1995) using Si-LDMOS technology. Figure 13. Power gain, output power (Pout), and power added efficiency, PAE versus input power for 3.5 GHz single-stage MPA

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ii. 5.8 GHz 2-stage MPA using 0.5μm GaAs PHEMT Technology: Figure 14 shows the schematic drawing of 5.8 GHz two-stage MPA using 0.5 µm GaAs PHEMT technology. The schematic of the whole amplifier including of the feedback topology, input matching network, interstage network, and the output matching network is presented.

Table 1. Summary of the PA performance at 3.5 GHz Parameter

This Work

Nader (2006)

Chu, Huang, Liu, Chiu, Lin, Wang, & Wang (2006)

Process

0.15um GaAs PHEMT

MET Si-LDMOS

0.4um AlGaAs/ InGaAs/ GaAs PHEMT

Type

single-stage

Single-stage

2-stage cascade

Frequency (GHz)

3.50

3.50

3.50

S21 (dB)

8.34

6.17

30.40

Power Gain (dB)

6.81

5.50

-

PAE (%)

16.74

9.27

37.10

P1dB (dBm)

16.81

25.78

34.00

S11 (dB)

-14.11

-14.20

-15.00

S22 (dB)

-12.38

-2.285

-

Ids (mA)

80.7

242

700

VDD(V)

3.0

20.0

8.0

Die size

1.2 mm x 0.7 mm

-

1.97 mm x 1.33 mm

Figure 14. Schematic of 5.8 GHz 2-stage MPA using 0.5 µm GaAs PHEMT

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The inductors LG and LS are chosen to provide the desired input resistance. The inductor LD and LO is a current source for the MPA and is used for output power matching. The LG, LS, LD and LO are all implemented with on-chip spiral inductors. The capacitor CC at the output plays a role for both DC block and output matching. The capacitor CO is used for network matching. The output is matched for output power. Based on these essential matching networks, optimizations and simulations were performed to achieve the required circuit performance. A 2-stage MPA presented herein consists of two amplification stages with the gate peripheries are 2x75 µm at the first stage and 8x100 µm at the output stage. The estimation of the required transistor size is an iterative process using the DC characteristics of the transistor. In this 2-stage MPA design, the first stage was designed for maximum gain while the output stage was designed for maximum output power. The 2-stage design was used since a single stage was unable to meet the power gain at the desired frequency. Figure 15 shows the layout for 2-stage MPA. This layout completed with a launch pad, was fabricated in Taiwan using 0.5µm GaAs PHEMT process technology. The chip size is 1.7 mm x 0.85 mm. All the passive components were integrated on-chip. This process uses a backside via-ground method, which eliminates the need for wire bonding to the ground. The performances of 5.8 GHz 2-stage MPA were measured on-wafer using microprobe station and ADS simulator was used extensively to predict the performances. The frequency was swept from 100 MHz to 10 GHz, and the bias condition is 5V of the supply voltage, VDD and a gate voltage, VGS is 0V. The simulated drain current, IDS is 106.25 mA which presents approximately 29 mA for the first stage and 77.25 mA for the output stage. Whereas, the measured drain current, IDS achieved is 200.2 mA, presenting approximately 52.7 mA for the first stage and 147.5 mA for the output stage. The power consumption of the circuit is 531.25 mW and 1001 mW for simulation and measurement, respectively. Figure 16 illustrates the simulated and measured data for input return loss (S(1,1)) and output return loss (S(2,2)) of the 2-stage MPA over 50 MHz to 10 GHz frequencies with the same bias condition and

Figure 15. A fabricated 5.8 GHz 2-stage MPA chip

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operating frequency. The input return loss of 15.25 dB was obtained for simulation and 15.30 dB was obtained for measurement at 5.8 GHz. In addition, the output return loss of 12.16 dB and 16.66 dB was achieved at 5.8 GHz for simulation and measurement, respectively. The measured data for the input and output return loss of this circuit is better than simulated data. In addition, this circuit is internally matched because the input and output return loss is more than 10 dB. Figure 17 shows the small-signal gain, S(2,1) as a function of frequency for simulated and measured data of 2-stage MPA. The small-signal gain (S21) for this 2-stage MPA is 16.39 dB and 8.33 dB for simulation and measurement data at 5.8 GHz. The simulated data has a very high gain than measured data. The measured gain is diminished about 50% than simulated which is found due to the parasitic effects and loss from the measurement connection. Figure 16. Simulated and measured data of input return loss and output return loss as a function of frequency for 5.8 GHz 2-stage MPA

Figure 17. Simulated and measured data of small-signal gain as a function of frequency for 5.8 GHz 2-stage MPA

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Figure 18 shows the simulated output power (Pout), power gain and power-added efficiency (PAE) as a function of input power (Pin) for MPA circuit at 5.8 GHz. The MPA circuit was achieved an output power, Pout of 20.18 dBm at 1dB gain compression (P1dB) with the input power, Pin of 5 dBm. From -20 dBm to 4 dBm, this amplifier showed the linear Pin-Pout characteristic and no gain compression until input power reached 5 dBm and the output power will saturate started from 10 dBm of input power. The power gain of 15.08 dB was obtained at 5 dBm of input power. In addition, the power added efficiency (PAE) of 18.13% for this MPA was obtained at P1dB and the maximum PAE of 25.30% was obtained at 10.50 dBm of input power, Pin. Table 2 summarizes the performance of this work compared with previously reported 5.8 GHz power amplifiers. It is shown that the PAE of this work is better than those of the amplifiers presented in Choi, Lee, Lee, Kim, Kim, & Hong (2000) and Simbürger, Bakalski, Kehrer, Wohlmuth, Rest, Aufinger, Boguth, & Scholtz (2006). However, the gain and P1dB achieved in Choi, Lee, Lee, Kim, Kim, & Hong (2000) and Simbürger, Bakalski, Kehrer, Wohlmuth, Rest, Aufinger, Boguth, & Scholtz (2006) better value than this work. This is because the proposed amplifier in this work utilizes different technology and design topology compared to Choi, Lee, Lee, Kim, Kim, & Hong (2000) and Simbürger, Bakalski, Kehrer, Wohlmuth, Rest, Aufinger, Boguth, & Scholtz (2006).

CONCLUSION In this work, the proposed single-stage and two-stage MPA were designed and fabricated using GaAs PHEMT technology to be operated at 3.5 GHz and 5.8 GHz. The proposed MPA employs a simple RC feedback. The feedback is used in order to linearize the stages as well to improve the circuit stability.

Figure 18. Power gain, output power (Pout), and power added efficiency, PAE versus input power for 5.8 GHz 2-stage MPA

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Table 2. Summary of the PA performance at 5.8GHz Parameter

This Work

Choi, Lee, Lee, Kim, Kim, & Hong (2000)

Simbürger, Bakalski, Kehrer, Wohlmuth, Rest, Aufinger, Boguth, & Scholtz (2006)

Process

0.5um GaAs PHEMT

0.25um GaAs PHEMT

0.8µm Si-Bipolar

Type

Two-stage

Two-stage hybrid

Two-stage push-pull

Frequency (GHz)

5.80

5.80

5.80

S21 (dB)

8.33

22.00

20.00

Power gain (dB)

15.18

-

11.90

PAE (%)

18.13

15.00

11.00

P1dB (dBm)

20.18

21.00

21.90

S11 (dB)

-15.30

-15.00

-

S22 (dB)

-16.66

-20.00

-

VDD(V)

5.0

7.0

2.7

Die Size

1.7 mm x 0.85 mm

2.1 cm x 1.4 cm

1.56 mm x 1.0 mm

A single-stage MPA operating at 3.5 GHz was designed and fabricated using 0.15 µm GaAs PHEMT technology with a gate width of 100 µm and 10 fingers. The die size of the amplifier is only 1.2mm x 0.7mm. With a supply voltage, VDD of 3V, P1dB of 16.81 dBm, power gain of 6.81 dB and the PAE of 16.74% is achieved at 3.5 GHz. The simulated drain current, IDS is 78.0 mA and the simulated drain current, IDS is 80.7 mA. The power consumption of the circuit is 234.0 mW and 242.1 mW was obtained for simulation and measurement, respectively. In addition, the amplifier also attains a small-signal gain (S21) of 11.4 dB, input return loss of 18.1 dB, and output return loss of 10.4 dB at 3.5 GHz for simulated data. For measured data, the amplifier achieves a small-signal gain (S21) of 8.34 dB, input return loss of 14.11 dB, and output return loss of 12.38 dB at 3.5 GHz. The amplifier in this work outperforms previously reported medium power amplifiers in the literature; especially in terms of PAE and power gain. This proposed single-ended MPA with high linearity is suitable for 802.16 WiMAX applications and wireless local loop (WLL) applications. A 2-stage MPA operating at 5.8 GHz was designed and fabricated using 0.5 µm GaAs PHEMT technology with the gate peripheries are 2x75 µm at the first stage and 8x100 µm at the output stage. The die size of the amplifier is only 1.7mm x 0.85mm. With a supply voltage of 5.0V, the simulated drain current, IDS is 106.25 mA which includes approximately 29 mA for the first stage and 77.25 mA for the output stage. Whereas, the measured drain current, IDS is 200.2 mA, presenting approximately 52.7 mA for the first stage and 147.5 mA for the output stage. The power consumption of the circuit is 531.25 mW and 1001 mW for simulation and measurement, respectively. The input return loss of 15.25 dB was attained for simulation and 15.30 dB was obtained for measurement at 5.8 GHz. In addition, the output return loss of 12.16 dB and 16.66 dB was achieved at 5.8 GHz for simulation and measurement, respectively. The small-signal gain (S21) for this 2-stage MPA is 16.39 dB and 8.33 dB for simulation and measurement data at 5.8 GHz. With same bias condition, the P1dB of 20.18dBm, power gain of 15.18 dB and the PAE of 18.13% is achieved at input power of 5dBm and 5.8 GHz operating frequency. The amplifier in this work outperforms

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previously reported medium power amplifiers in the literature; especially in terms of PAE. Therefore, the proposed 2-stage MPA is suitable for 802.11a wireless LAN applications and HiperLAN/2 applications. Hence, the proposed MPAs were successfully designed, fabricated and measured in order to bear out the performances. The performances of the proposed MPAs show that the proposed MPAs are suitable for wireless applications.

REFERENCES Agilent Technologies. (2008). Agilent ADS 2008A:Momentum. ADS User Guide. Breed, G. (2006, July). Feedback Fundamentals: Basic Concepts and Circuit Topologies. High Frequency Electronics, 46-50. Choi, H. K., Lee, J. C., Lee, B., Kim, J. H., Kim, N. Y., & Hong, U. S. (2000). The Design of Power Amplifier for 5.8 GHz Wireless LAN Application Using GaAs Substrate. 2000 Asia-Pacific Microwave Conference (pp. 1131-1134). Chu, C.-K., Huang, H.-K., Liu, H.-Z., Chiu, R.-J., Lin, C.-H., Wang, C.-C., & Wang, Y.-H. (2004). A 3.5GHz 2W MMIC Power Amplifier using AlGaAs/InGaAs/GaAs PHEMTs. The 2004 IEEE Asia-Pacific Conference on Circuit and Systems (pp. 101-104). Cripps, S. C. (1999). RF Power Amplifiers for Wireless Communications. Norwood, MA: Artech House. Doudorov, G. (2003, June). Evaluation of Si-LDMOS Transistor for RF power Amplifier in 2-6 GHz Frequency Range. Unpublished Master’s Thesis, Linköping University, Sweden. Fujii, K., Morkner, H., & Brown, E. (2004). A Novel Low Cost Enhancement Mode Power Amplifier MMIC in SMT Package for 7 to 18 GHz Applications. 12th GaAs Symposium, pp. 599-602. Huang, C.-C., Lee, S.-M., & Chen, K.-Y. (2005). GaAs PHEMT Characterization for OFDM Power Amplifier Application. 10th International Symposium on Microwave and Optical Technology, pp. 767-770. IEEE Draft Supplement to IEEE Standard 802.11. (1999, September). Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: High speed Physical Layer in the 5 GHz Band. Kang, D. M., Lee, J. H., Yoon, H. S., Kim, S. J., Shim, J. Y., & Lee, K. H. (2002). Wideband 36- to 44GHz MMIC Power Amplifier Using a 0.2-µm PHEMT Process. Journal of the Korean Physical Society, 41(4), 524–527. Komiak, J., Wang, S., & Roger, T. (1997). High Efficiency 11watt Octave S/C-band PHEMT MMIC Power Amplifier. 1997 IEEE MTT-S Int. Microwave Symp. Dig (pp. 1421-1424). Lan, E., Johnson, E., Knappenberger, B., & Miller, M. (2002). InGaP PHEMTs for 3.5GHz W-CDMA applications. Microwave Symposium Digest, IEEE MlT-S International, 2, 1039-1042. Lombardi, G., & Neri. (1999, June). Criteria for the evaluation of unconditional stability of microwave linear two-ports: a critical review and new proof. IEEE Transactions on Microwave Theory and Techniques, 47, 746–751. doi:10.1109/22.769346

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Marzuki, A., et al. (2004, October). A Broadband RF Feedback Amplifier Design with Simple Feedback Network. RF and Microwave Conference (pp. 1-4). Meng, C.-C., & Wu, T.-H. (2008, February). A 5 GHz RFIC Single Chip Solution in GaInP/GaAs HBT Technology. Microwave Journal, 51(2), 132. Meys, R. (1990, November). Review and discussion of stability criteria for linear 2-ports. IEEE Transactions on Circuits and Systems, 37, 1450–1452. doi:10.1109/31.62423 Nader, C. (2006, June). Design of A Power Amplifier Based on Si-LDMOS for WiMAX at 3.5 GHz. Unpublished Master’s Thesis, University of Gävle, Sweden. Platzker, A., & Bouthillete, S. (1995). Variable Output, High-Efficiency Low-Distortion S-band Power Amplifiers. 1995 IEEE MTT-S Int. Microwave Symp. Dig (pp. 441-444). Queen’s Learning Wiki. (2008). Introduction to Microwave Amplifier Design. Retrieved September 19, 2008, from http://bmf.ece.queensu.ca/ mediawiki/ index.php Rasmi, A., Azmi Ismail, M., Abd Rahim, A. I., Marzuki, A., Razman Yahya, M., & Fatah Awang Mat, A. (2007). 0.15 μm Pseudomorphic HEMT Medium Power Amplifier for Wireless LAN Application. In Proceedings of the International Conference on Robotics, Vision, Information and Signal Processing ROVISP2007 (pp. 804-807). Rasmi, A., Marzuki, A., Azmi Ismail, M., Abdul Rahim, A. I., Razman Yahya, M., & Fatah Awang Mat, A. (2008, November). Design of 2-Stage Medium Power Amplifier Using 0.5 μm GaAs PHEMT for Wireless LAN Applications. Paper presented at the International Technical Conference of IEEE Region 10 (TENCON 2008), Hyderabad, India. Razavi, B. (1998). RF Microelectronics. Upper Saddle River, NJ: Prentice Hall PTR. Rollett, J. (1962, March). Stability and power-gain invariants of linear two ports. IRE Trans. Circuit Theory, 9, 29–32. Simbürger, W., Bakalski, W., Kehrer, D., Wohlmuth, H. D., Rest, M., & Aufinger, K. (2006). A Monolithic 5.8 GHz Power Amplifier in a 25 GHz FT Silicon Bipolar Technology. Alma Mater Studiorum - Università di Bologna. Tian, Y.-J., & Haigh, D. G. (2006). Investigation into RF Feedback for Improving the Efficiency-Linearity Trade-Off in Power Amplifiers. In Proceedings of Asia-Pacific Microwave Conference (pp. 449-452). Tonga Karakaş, N. (2007, February). Design of Combined Power Amplifier Using 0.35 Micron SiGe HBT Technology for IEEE 802.11a Standard. Unpublished Master’s Thesis, Sabanci University, Istanbul Turkey. Weitzel, C. E. (2003). RF Power Amplifiers for Cellphones. GaAs MANTECH Inc.

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Chapter 9

The Design and Modeling of 30 GHz Microwave Front-End Wan Yeen Ng Universiti Sains Malaysia, Malaysia Xhiang Rhung Ng Universiti Sains Malaysia, Malaysia

ABSTRACT This chapter aims to discuss a millimeter wave integrated circuit (MMWIC) in frequency of 30 GHz especially switch (SPDT), medium power amplifier (MPA) and low noise amplifier (LNA). The switch is developed using a commercial 0.15 µm GaAs pHEMT technology. It achieves low loss and high isolation for millimeter wave applications. The circuit and layout drawing of SPDT switch are done by using Advanced Design System (ADS) software. The layout is verified by running the Design Rules Check (DRC) to check and clear all the errors. At the operating frequency of 30 GHz, the reported SPDT switch has 1.470 dB insertion loss and 37.455 dB of isolation. It also demonstrates 26.00 dBm of input P1dB gain compression point (P1dB) and 22.975 dBm of output P1dB. At a supply voltage of 3.0 V and 30 GHz operating frequency, this two-stage LNA achieves an associated gain of 21.628 dB, noise figure (NF) of 2.509 dB and output referred 1-dB compression point (P1dB) of -11.0 dBm, the total power consumptions for the LNA is 174 mW. At a supply voltage of 6.0 V and 30 GHz operating frequency, a 2-stage MPA achieves a linear gain (S21) of 13.236 dB, P1dB of 22.5 dBm, power gain of 11.055 dB and the PAE of 14.606%. The total power consumption for the MPA is 1.122 W. The 30 GHz LNA and PA can be applied in direct broadcast satellite (DBS), automotive radar transmitter and receiver.

INTRODUCTION Microwave switches are essential elements for a number of widely varying applications, ranging from highly sophisticated space communications systems to more common applications simply requiring the switching of an RF signal from one part to another. Circuits that switch RF and microwave signals are very useful, especially for applications such as phased-array radar and instrumentation. The best MMIC technology for switches is the FET because of the inherent isolation between the gate contact and the DOI: 10.4018/978-1-60566-886-4.ch009

Copyright © 2012, IGI Global. Copying or distributing in print or electronic forms without written permission of IGI Global is prohibited.

The Design and Modeling of 30 GHz Microwave Front-End

source and drain contacts, and because the gate draws virtually zero current in both control states (on and off) (Ayasli, 1982). GaAs FET-based switches have been the dominant technology for the RF transmit/receive (TxRx) switch due to their low DC power consumption (Feng Jung Huang et. al., 2001). SPDT switches are also an integral part of transceivers, where they are used to switch a device between receiver and transmitter modes, and receiver front end for diversity application (Ketterl, et. al., 2004). The 30 GHz low noise and power amplifier are mostly used in direct broadcast satellite (DSB) and automotive radar. Direct Broadcast Satellite (DBS) is a satellite-delivered program service meant for home reception. DBS programming is in most respects, the same as that available to cable television subscribers. MMIC power amplifier is much more complicated than the small-signal amplifier design because the larger voltages and currents within the circuit can cause the MMIC components to behave nonlinearly. The simulation of a circuit with nonlinear components no longer has a unique solution but require iterative techniques. Advanced Design System (ADS) software is used to implement the design from schematic, layout design and analysis level. The objectives for this work are as follows: i. To study and understand switch function, performances and applications. ii. To compare the simulation results between switch without distributed components and with distributed components. iii. To integrate the SPDT switch, MPA and LNA. This chapter is organized as follows. Introduction presents the overview of the project’s scope. Background emphasizes the basic theory of designing the switch. Design methodology section details the method and the mathematical calculation are presented which clearly showed the outlined of the switch, LNA and MPA design. Results is the section that showed the result and the discussion of the switch, low noise amplifier and medium power amplifier designs. Final section gave the overall conclusion of this chapter and discussed the future challenges.

BACKGROUND FET Switch Device Behaviors In most processes, the FET can be accurately modeled by an on-resistance, Ron, and an off-capacitance, Coff, in these regimes and at frequencies representative of the communication systems mentioned. Coff is defined as the total capacitance from drain-to-source with the gate biased by a high-impedance source. Both parameters affect the switching speed, insertion loss and isolation of a switch, so a FET process can be evaluated for its efficacy as a switch process by the product of Ron-Coff.Table 1 compares the Ron-Coff figure-of-merit from the several process technologies (Dylan Kelly et. al., 2005). Insertion loss of GaAs switch IC can be estimated by the product of the off-state capacitance and the on resistance of the employed FET (Y. Ayasli, 1982). Shortening the gate length of the FET is effective to reduce this product. However decreasing the insertion loss is limited due to the directly coupled drain to source capacitance, namely Cds (T. Tanaka et. al., 1997). It can be expected that the insertion loss will

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Table 1. Survey of Ron-Coff from the several process technologies Process Technology

Ron (Ωmm)

Coff (fF/mm)

Ron-Coff (fs)

0.15µm pHEMT

1.5

290

435

0.5µm pHEMT

1.5

240

360

0.5µm 100Å Tox SOS

2.8

270

756

0.5µm 50Å Tox SOS

1.6

280

448

be improved by reducing the directly coupled Cds capacitance. So that, narrowing the area of the drain/ source regions can drastically reduce the off-state-capacitance that is interdigitally distributed between source and drain region (S. Makioka et. al., 2001). The FET of the switch IC is almost equivalent to a two-port device when a bias resistor with sufficiently large resistance is inserted into the gate bias circuit, as shown in Figure 1(a). An equivalent circuit of the FET in the on-state is a simple resistor, as shown in Figure 1(b) and in the off-state it is replaced by a simple capacitor, as shown in Figure 1(c) (S. Makioka et. al., 2001). The switch IC is composed of the shunt FET and the series FET. The shunt FET becomes a capacitor with an equivalent circuit of the switch, and series FET becomes resistant with it. Hence, the product of the off-state-capacitance and the on-resistance of the employed FET structure are determining insertion loss of the GaAs switch IC. Figure 2 shows series and shunt SPDT switch.

FET Switch Model The configuration of a switching FET is indicated in Figure 3(a). In the on-state the gate is biased at 0 V. The on-state can be adequately modeled by the dc on-resistance between the source and the drain Figure 1. (a) FET model for switch circuit, (b) open-channel state, (c) pinched-off state

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(Ron), as shown in Figure 3(b). Additional parasitic elements are present, but have no significant RF effect, particularly if the gate bias circuitry is isolated with large value resistor, as is indicated in Figure 3(a). In the off-state the gate is biased beyond pinch-off. A complete equivalent circuit in the off-state is shown in Figure 3 (b). The off-state source to drain leakage resistance Rds is generally large enough to be neglected in circuit modeling. The source and the drain are capacitively coupled directly Csd and also through the gate (Cgs and Cgd). All of these capacitances have series parasitic resistive elements (Rgs and Rgd for Cgs and Cgd; Rs and Rd for Csd). A simplified FET model is indicated in Figure 3 (c). The on-state equivalent circuit is unchanged but the off-state equivalent circuit has been reduced to a simple series resistor and capacitor. Since Rds is typically very large, it has been neglected. It is straightforward to include Rds if needed. Roff and Coff can be calculated from the resistive and capacitive elements in Figure 3 (b) (Manfred J. Schindler, et. al, 1989).

On/Off Ratio of a Single Switch Element The simple switching quality factor (Qs) is defined as the ratio of the “on” state device impedance to the “off” state device impedance. For the equivalent circuit as shown in Figure 3, this yields the following relationship: Qs =

Ron [(Roff ) + (1 / ωCoff )2 ]1/2 2

(1)

But since (1/𝜔Coff) >> Roff, the relationship can be simplified to Qs = ωR on Coff = 2pfo R on Coff , whereω = 2pfo

Ron is on resistance, Coff is off capacitance and fo is the frequency.

Figure 2. (a) Series SPDT switch, (b) Shunt SPDT switch

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The Design and Modeling of 30 GHz Microwave Front-End

Figure 3. (a) FET in switching configuration, (b) Complete equivalent circuit, (c) Simplified equivalent circuit

Performance for T/R Switches The performance of a T/R switch is characterized by several parameters in the transmit and receive modes. A brief description of each of these is presented as below.

Insertion Loss (IL) For an ideal switch, there is no power loss in the switch. Insertion loss is the power loss in the T/R switch under matched conditions. The loss which results from inserting a transmission line between a source and a load is called the Insertion Loss of the line. If the power transmitted by the source is PT and the power received by the load is PR, then the insertion loss is given by PR divided by PT. The ratio is always less than one. For a WLAN system, a T/R switch with an IL < 1.5 dB is desirable.

Isolation Isolation is a measure of the signal attenuation from the signal port to the unused port. For example, in the Tx mode, isolation is measured from the Tx port to the unused Rx port. Although, isolation is usu-

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The Design and Modeling of 30 GHz Microwave Front-End

Figure 4. Transceiver block diagram

ally in the negative dB range, it is common practice to use its absolute value. Isolation greater than 30 dB is desirable to protect the unused port from high power and minimize loss.

Return Loss Return loss is amount of power which is reflected back to the source from an incorrectly terminated line. Measurement of return loss can reveal line faults due to mismatching. This parameter is a measure of the input and output matching conditions. If the power transmitted by the source is PT and the power reflected back is PR, then the return loss is given by PR divided by PT. The ratio PR/PT should be as small as possible, if express in dB, the return loss should be as large a negative number as possible. For example a return loss of -40 dB is better than one of -20 dB. A return loss greater than 10 dB, at the input and the output, usually indicates acceptable power transfer conditions.

DESIGN METHODOLOGY RF Front-End Design RF front-end design employing SPDT transmit and receive configuration is shown in Figure 4. In the transceiver, the antenna is play as a transmitting and receiving signal. In addition, it also needs a Single Pole Double Throw (SPDT) switch to control the operation modes of transceiver, either transmission or reception. The two filters are needed to reduce the interference signal. The switch is designed to be part of the microwave applications for switching system between transmitting and receiving modes.

Behavior of PHEMT Transistor GaAs based pHEMT switches offer high isolation, low insertion loss, and high switching speed. A pHEMT device structure was selected as optimum for high-frequency switching and control functions. The resistances and capacitances forming the pHEMT equivalent circuit can be subdivided into configurations representing the two switch states (on and off). For most control applications, at frequencies of most interest, the on-state impedance is mostly resistive while the off-state impedance is mostly capacitive. The modeled capacitances and resistances can be combined to form an equivalent circuit that represents the two states of the pHEMT control device. It is well known that the on-state resistance,

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Ron, and the off-state capacitance, Coff. When used as a switch, a pHEMT is operated with the drain and source at positive volts DC. The RF signal path is drain to source and the gate is the control terminal. With depletion mode PHEMTs, Vg ≥ 0V results in a low resistance signal path (low Rds) and the transistor is on. For Vg below pinch-off, the transistor presents a high resistance signal path (high Rds) and the transistor is off. The simple equivalent circuit is shown in Figure 5. The gate resistor (Rg) is providing extra isolation between the signal and control path.

Determine the Ron Ron is the sum of a resistance between source and gate, a channel resistance beneath the gate and a resistance between gate and drain. Among them, a channel resistance takes the most part. The channel resistance is decreased by shortening the recess length. When the voltage at the gate is 1.5V, the transistor will at “on” state. The “on” state can be sufficiently modeled by the DC “on” resistance between source and the drain. Thus, the transistor will become Ron. When the width of transistor increases, Ron value will decrease. Due to the higher ohmic contact resistance of pHEMT, it will increase insertion loss. Figure 6 is the comparison different unit gate width (Ugw) of the transistor to find the Ron. With using the different Ugw of the transistor, there will different value of Ron. In the Figure 6 (a), the Ugw is 90µm and Figure 6 (b), the Ugw is 60µm. The number of finger (NOF) is 2 for low current. From the simulation, when the Ugw is 90µm, the value of Ron is 8.769 Ω, whereas when the Ugw is 60µm, the value of Ron is 12.5 Ω. The higher Ron will increase the insertion loss. So, to make the design to have low insertion loss, it is decided to use higher unit gate width. R on = =

Delta(V (m1) − V (m2)) Delta(I (m1) − I(m2)) (1 − 0.5)V (108.4 − 51.38) mA

= 8.769Ω

Figure 5. Equivalent circuit of a switching, (a) Simulation Ron with 90 µm unit gate width

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The Design and Modeling of 30 GHz Microwave Front-End

Figure 6. (a) Simulation Ron with 90 µm unit gate width, (b) Simulation Ron with 60 µm unit gate width

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R on = =

Delta(V (m1) − V (m2)) Delta(I (m1) − I(m2)) (1 − 0.5)V (69 − 299) mA

= 12.5Ω

Insertion Loss To estimate the insertion loss of a pHEMT switch, it can directly be calculated using Ron. The smaller width pHEMT may increase insertion loss. The equation (2) can be used in the calculation. IL=20 log (

Ron + 2Zo ) 2Zo

(2)

From the Figure 6 (a), Ugw = 90µm, Ron = 8.769Ω Ron + 2Zo ) 2Zo 8.769 + 2(50) ) = 20 log ( 2(50) = 0.7730 dB

IL = 20 log (

From the Figure 6 (b), Ugw = 60µm, Ron = 12.5Ω Ron + 2Zo ) 2Zo 12.5 + 2(50) = 20 log ( ) 2(50) = 1.023dB

IL=20 log (

It is obviously that 90 µm total gate periphery has lower insertion loss than 60µm total gate periphery. To have a low insertion loss design, the bigger width of transistor is required.

Single Series-Shunt Switch Switch isolation can be improved without causing excessive increases in insertion loss by incorporating shunt mounted transistors, as shown in Figure 7. The resistor between source and drain contacts is controlled by the voltage applied to the gate contact through a value of resistor. Transistor M1 performs the main switch function, while the shunt transistor M2 is use to improve the isolation of the switch.

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The Design and Modeling of 30 GHz Microwave Front-End

Figure 7. Single series-shunt switch

Both transistors are control by the voltage V1 and V2. When the main switch transistor is on, and the shunt transistor is off, the switch performs as a usual switch. Whereas the main switch is ‘off’, the shunt transistor is ‘on’ to ground the leakage signal. Rg1 and Rg2 are the gate bias resistances. These resistors are used to improve DC bias isolation.

Series-Shunt SPDT Switch Figure 8 is the schematic of series-shunt SPDT switch with using lumped component. The parameters such as resistors and capacitors were tuned to optimize circuit performance to get the specification. Figure 9 is the parameter tune value for resistors and capacitors. Figure 8. Series-shunt SPDT switch

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The Design and Modeling of 30 GHz Microwave Front-End

Figure 9. Tune parameters

Figure 10 are simulation results of series–shunt SPDT switch. The transmitter part is in the on-state, while the receiver path is in the off-state. In Figure 10 (a), the insertion loss has decreased a little. In Figure 10 (b), the isolation will increase around 20 dB compared to the simple series transistor design. It should be noted that the simulations have assumed ideal grounding for the shunt transistor. In Figure 10 (c), the return loss of the Rx (S33) is close to the zero. Thus, there is no RF signal travelling from the antenna to the Rx (receiver path), which mean, receiver path is not function at all. By adding a shunt transistor, isolation will be improved. Key figures of SPDT switch are low insertion loss, high isolation between Tx and Rx. Thus, this is a better choice for design a SPDT switch configuration. The schematic design has a symmetrical structure of transmitter part and receiver part. Transistors M1 and M2 perform the main ‘on’ and ‘off’ switching function, while the shunt transistor M3 and M4 are used to improve the isolation of the switch by grounding RF signals on the side which is turned off. The gate resistances R1, R2, R3 and R4 are implemented to improve DC isolation. The switch also connects coupling capacitors C1 and C2 which allow dc biasing of the transmitter, Tx and receiver, Rx nodes of the switch.

Layout Design Layout design plays an important role in a design process. Fabrication process will be done after finish the layout design. It will determine the performance of the switch after fabrication process. The layout design will be constructed after the best simulation results of the SPDT switch are obtained. In Advanced Design System (ADS) software, the schematic can be generated into a layout by selecting Layout > Generate/Update Layout. Hit OK, and ADS will begin turning the schematic into a layout. When it is done, a layout window will show the components from schematic. ADS may place some traces immediately beside one another. In this case the component will be needed to move and/or rotate. The layout design rules such as minimum feature sizes and spacing and metallization constraints will be referred during drawing the layout. Transmission line was formed between two components. The microstrip line such as double metal (Metal1+ Metal2), MLIN_D, MTEE and MCORN were used during the layout design. Span layer is used to separate bottom metal and top metal to avoid interconnection between metal. 215

The Design and Modeling of 30 GHz Microwave Front-End

Figure 10. (a) Simulation result of series-shunt SPDT switch for insertion loss, (b) Simulation result of series-shunt SPDT switch for isolation, (c) Simulation result of series-shunt SPDT switch for return loss

After the layout is completed, Design Rules Check (DRC) was done. DRC is performed by a program that scans the layout data file and measures the distances from every polygon border to every other polygon border, then compares these distances to the specified design rules. DRC was run to check the error and clear the error.

Distributed Component Finally, the distributed components were added in the schematic by referring back to the layout. Distributed elements made of transmission lines are particularly effective when their size becomes smaller, as the frequency is higher. The WIN components are connected together using traces. The simplest in most cases is to use microstrip transmission lines that are listed on the component palette as Tlines-Microstrip. The element MLIN in the palette is a simple trace whose width and length which must referred back to the layout drawing. Note that all junctions should be done using the MTEE element rather than joined with multiple wires. A connection to the ground plane are added using the BACKVIA element. Microstrip

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The Design and Modeling of 30 GHz Microwave Front-End

Substrate (MSUB) is placed and the parameters are set as εr =12.9, H=100µm, T=3 μm, TanD= 0.001, Z=50Ω. The final design is shown in Figure 11.

LNA Design Methodology There are various topologies exist for LNA circuits, but the common-source topology was chosen for this design. A common-source topology has a design which the source of the transistor is grounded and the RF input signal is applied to the gate of the transistor while the amplifier RF output signal is extracted from the drain. The input and output matching networks perform impedance transformations to provide noise and power matching, respectively. Ideally, an LNA would have low noise and high gain characteristics. In order to achieve power matching and noise matching the two different requirements are approaches, as a result two different solutions are applied. The maximum output power occurs when the input impedance equals the conjugate match of the source impedance, resulting in Gin = Gs*. The condition for minimal noise is met when Gs = Gopt. An input matching network (IMN) is designed to impedance match Gopt of the transistor to 50 W, where Gopt is the optimum reflection coefficient for the lowest noise figure at a particular frequency. Figure 12 illustrates a common-source low noise amplifier circuit with IMN (Input Matching Network), and OMN (Output Matching Network) and the bias network. In order to achieve a high gain LNA, a two-stage design is employed in this project. This architecture allows for the first stage to be designed with an extremely low noise figure, hence setting the overall

Figure 11. Final design

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The Design and Modeling of 30 GHz Microwave Front-End

noise figure of the LNA. Then the second stage provides the necessary amplification to achieve an overall high gain. •

Define the Device Characteristics: The choice of device size is a critical step in designing a MMIC LNA. Device size will affect the LNA’s bandwidth, DC power consumption, noise figure, and nonlinear performance. The drain bias current affects the noise figure more than the drain voltage. Additionally, drain bias affects amplifier gain. With insufficient current, gain will be low. Decreasing the drain voltage will reduce DC power consumption, but the drain voltage must be high enough for the device to operate in its saturation region and enable amplification. In addition to an increased noise figure and reduced gain as a device shrinks, there are other drawbacks in using a too-small device.

For the second stage design, the depletion-mode pHEMT transistor (micro-strip type) with number of finger (NOF) of 2 and unit gate width (UGW) of 50 um has been selected. Figure 13 shows the schematic of DC characteristic simulation in order to define the drain current for DMODE pHEMT transistor. The drain voltage, Vds was swept from 0V to 7V while the gate voltage, Vgs was swept from -1V to 0V. Figure 14 shows the IV characteristics for transistor with NOF is 2 and the gate width is 50 um. The marker 2 shows the current is 0.045A when the VGS is 0. The marker 3 represents the low-noise operating point with the transistor biased at VDS=3V, the VGS=-0.8V, and the ID is about 10-20% of IDSS, the best performance of noise figure is obtained. However, the gain obtained in this operating point is very small. Therefore, the operating point with higher drain current as shown in marker 7 is chosen in order to obtain a higher gain. •

Biasing: Figure 15 shows the biasing network at gate and drain of the transistor using WIN component. The inductor acts as RF chokes, with DC blocking capacitors used at the input and output to isolate the bias from other circuits. The inductor act as an ideal DC feed to the RF device which is a low DC resistance but a high RF resistance to ensure that the RF circuit is not loaded and RF signals do not flow onto the supply lines (Where they could find their way back onto the input of the RF device causing gain ripple and possibly instability).

Figure 12. Common-source LNA topology

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The Design and Modeling of 30 GHz Microwave Front-End

Figure 13. Schematic of DC characteristic simulation

Figure 14. I-V characteristics for transistor

At lower frequencies (up to ~1.5GHz) the RF bias consists of an inductor which ‘chokes’ any RF signal, in other words the RF circuit see’s an open circuit looking into the inductor. However, at very low frequencies where RF devices have high gain the inductor will appear as a short circuit, i.e. will appear invisible to the RF circuit.

219

The Design and Modeling of 30 GHz Microwave Front-End

Figure 15. Biasing network, inductors as bias choke

•

•

Stability: The next step in the design process is to stabilize the transistor. Because the LNA is being designed for a minimum NF, the stabilizing network should be placed on the output side of the LNA. The method of stabilizing the transistor that used in this project is a feedback resistor and capacitor between the drain and gate. DC blocking capacitors are also utilized to isolate the inter-stages of the amplifier in addition to the external RF ports on the amplifier from the various bias voltages. Feedback Topology: Feedback is an important concept in circuit design, where a signal or voltage derived from the output is superimposed on the input. This output-to-input path can be used for several purposes such as to control output voltage, control gain, reduces distortion (or increase linearity), increase bandwidth, and improve stability.

The resistor RF forms the feedback resistor and capacitor CF (Figure 16) is added to allow for independent biasing of the gate and drain of the transistor. Since the LNA is being designed to operate via a battery, it is essential to minimize wasted power loss in any portion of the stabilizing network. Therefore, DC blocking capacitors were used in series with the stabilizing resistors to minimize the amount of power dissipated by the resistors. In addition, the effect of negative feedback is to make the input and output impedances more convenient for matching. Another advantage of employing this feedback is the properties of the circuit can be made to depend primarily on the values of the feedback circuit elements and to be more-or-less independent of the particular characteristics of the active device (such as transistor β, bias current, etc.). The feedback topology has the close loop gain, Av.

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The Design and Modeling of 30 GHz Microwave Front-End

Figure 16. Feedback network

Av = −

1 ,     1 G 1 +    F    A  1 OL   +   G A S OL      

(3)

where the GF, GS, AOL is the conductance of feedback, conductance of source resistance and open loop gain respectively. To find the Av, first we need to find AOL, where AOL = gm r0

(4)

Gm is the transconductance of the transistor, ro is output resistance. • • •

Single-Stage Design: After designing the input and output matching networks, a completed singlestage design is shown in Figure 17. Two-Stage Design: After the ideal single stage design yielded promising results, two identical single stages were cascaded together as shown in Figure 18. Final Two-Stage Design: Next, the design was optimized and tuned again to obtain the required performance. As a result, the matching impedance will change. The cascaded system is shown in Figure 19.

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The Design and Modeling of 30 GHz Microwave Front-End

Figure 17. Single stage complete design

Figure 18. Two-stage complete design

MPA Design Methodology For this MPA design, the methodology includes:

Define the Device Characteristics The amplifier used in this project is class AB (see Figure 21). The class A medium power amplifier is at the point that the current is IMAX/2 which is at point I_Probe1 = 0.079A. The class B medium power 222

The Design and Modeling of 30 GHz Microwave Front-End

Figure 19. Two-stage complete design after tuning

Figure 20. The schematic to check the MPA operation

amplifier is at the point that the current equals to zero (when VGS = -1.55). The current used in this project is class AB since the current used in this project is smaller than 0.079. The bias point in this work will be VDS = 6V, the VGS=-0.5, the IDS=0.077A But this MPA will swing to become more a class A medium power amplifier. The test bench is shown in Figure 20. •

Biasing: The method of biasing is self-biasing techniques (see Figure 22). The gate is grounded at DC through an inductor. The gate is raised to appositive DC potential, equal in magnitude to the desired gate-source voltages, by inserting a small resistor in the source. In order to prevent a loss of RF gain, the source is grounded with a large decoupling capacitor. This self-biasing technique

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The Design and Modeling of 30 GHz Microwave Front-End

Figure 21. The classes of medium power amplifier used in this project

Figure 22. Biasing network

benefit of only a single power is considerable. But the disadvantage is the DC power consumption will increase. Stability: The method of stabilizing the transistor that used in this project is a feedback resistor and capacitor between the drain and gate.

•

The feedback network used is as shown in Figure 23.

Input and Output Matching Network for MPA Figures 24, 25, 26, 27, 28, 29, 30 and 31 show the matching circuits and the results. Single-Stage Design: After designing the input and output matching networks, a completed single-stage medium PA design is shown in Figure 32.

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The Design and Modeling of 30 GHz Microwave Front-End

Figure 23. Feedback network

Figure 24. Schematic without matching network for single stage MPA

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The Design and Modeling of 30 GHz Microwave Front-End

Figure 25. Input impedance of transistor and feedback network for single stage MPA

Figure 26. Schematic with input matching network for single stage MPA

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The Design and Modeling of 30 GHz Microwave Front-End

Figure 27. Total impedance of input matching network for single stage MPA

Figure 28. Schematic without matching network for single stage MPA

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The Design and Modeling of 30 GHz Microwave Front-End

Figure 29. Output impedance of transistor and feedback network for single stage MPA

Figure 30. Schematic with output matching network single stage MPA

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The Design and Modeling of 30 GHz Microwave Front-End

Figure 31. Total impedance of output matching network single stage MPA

Figure 32. Completed single stage PA designs

• •

Two-Stage Design: After the ideal single stage design yielded promising results, two identical single stages were cascaded together as shown in Figure 33. Final Two-Stage Design: Next, the design was tuned and optimized again to obtain the required performance. As a result, the matching impedance will be changed. The cascaded system is shown in Figure 34.

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Figure 33. Completed two-stage design

Figure 34. Completed two-stage design after tuning

Compensating for Transmission Line Effect The Figure 35 (a) shows the single-stage amplifier without transmission lines (MLIN) matching impedance and Figure 35 (b) shows the single-stage amplifier with transmission lines (MLIN) matching impedance. Figure 35 shows that transmission lines have improve the input matching and degrade the output matching. As the matching network change, the stability, gain, current, P1dB, noise figure, and PAE of the circuit will also be affected. Therefore, the layout design is a critical step in a amplifier design.

The Integration of SPDT Switch, LNA and MPA After the design of switch is completed, the other part is to integrate between 30 GHz single pole double throw (SPDT) switch, medium power amplifier (MPA) and low noise amplifier (LNA). Figure 36 is a

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Figure 35. (a) The single-stage amplifier matching impedance, (b) The single-stage distributed amplifier matching impedance

Figure 36. Block diagram of the integration

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block diagram of the integration. The MPA connected to the transmitter part and the LNA connect to the receiver part. If RF signal must travels from the antenna to the LNA. So that the LNA is needed to be functioned in ways to allow the RF signal to travel from the antenna to the LNA without passing through the MPA. Therefore the control voltage of Vin1 need to be set to -3 V and Vin2 is set to 1.5 V. The transistor M2 and M3 are short circuit while M1 and M4 are open circuit. Figure 37 is a schematic integration of SPDT switch, LNA and MPA.

RESULTS Simulation Results of Integrated SPDT Switch, LNA and MPA The schematic integration can be referred at Figure 37 in previous section. Below are the results when 30 GHz MPA combined with SPDT switch in transmitter part and MPA is functioning. Figure 38 is the P1dB exhibits linear output power of 9.600 dBm of input P1dB which corresponds to 22.974 dBm of output P1dB. The simulation result for Power Added Efficiency, PAE at P1dB is 17.057% at Figure 39

Figure 37. Schematic integration 30 GHz between SPDT switch, LNA and MPA

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Figure 38. Simulation result P1dB for 30 GHz integration when MPA is functioned

Figure 39. PAE

and the power gain at 1 dB is 13.374 dB at Figure 40. At Figure 41, simulation result for input return loss S(3,3) is 6.279 dB and output return loss S(1,1) is 26.535 dB for 30 GHz integration. At the receiver part, 30 GHz LNA combined with SPDT switch. Below are the results for integration when the LNA is functioning. Figure 42 shows the simulation result for noise figure (nf) of 30 GHz integration. The result of noise figure is 4.108 dB and the result of Pout at 1 dB Gain Compression Point (P1dB) is 14.779 dBm as shown in Figure 43. In Figure 44, the simulation result for associated gain is 20.250 dB. Figure 45 and Figure 46 is the return loss simulation, it demonstrates input return loss S(1,1) 12.305 dB and output return loss S(2,2) is 12.706 dB.

CONCLUSION In this chapter, the design of a SPDT switch with a very low insertion loss and very high isolation is presented. The design used a commercially available 0.15µm GaAs pHEMT technology and the simulation and layout design were done by Advanced Design System (ADS) Software.

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Figure 40. Simulation result power gain for 30 GHz integration when MPA is functioned

Figure 41. Simulation result input return loss S(3,3) and output return loss S(2,2) for 30 GHz integration when MPA is functioned

The SPDT switch had been designed that able to transmit signal and receive signal. During the design, some simulations were included to help more understanding on the transistor. The design is done step by step beginning from a simple transistor. A single series SDPT switch was designed and the performance was investigated. Poor isolation was obtained from the simulation result. To find a way to improve isolation, a series-shunt SPDT switch configuration was replaced to the single series SPDT switch. Tuning method was done to optimize the best performance for the switch. Low insertion loss and high isolation between Tx and Rx are obtained from the simulation result. In this project, the objectives are achieved.

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Figure 42. Simulation result noise figure for 30 GHz integration when LNA is functioned

Figure 43. Simulation result Pout at 1 dB Gain Compression Point (P1dB) for 30 GHz integration when LNA is functioned

Integration between SPDT switch, medium power amplifier (MPA) and loss noise amplifier (LNA) was presented.

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Figure 44. Simulation result associated gain for 30 GHz integration when LNA is functioned

Figure 45. Simulation result input return loss for 30GHz integration when LNA is functioned

Figure 46. Simulation result output return loss for 30GHz integration when LNA is functioned

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REFERENCES Ayasli, Y. (1982). Microwave Switching with GaAs FETs. Microwave Journal, 25(11), 61–74. Azmi Ismail, M., Abd. Rahim, A.I., Kushairi, N., Rasmi, A., Sanusi, R., Marzuki, A., Razman Yahya, M., & Fatah Awang Mat, A. (n.d.). 0.15μm GaAs pHEMT Cascode Low Noise Amplifier (LNA) for Wireless Applications. Devlin, L. (1999). The Design of Integrated Switches and Phase Shifters. In Proceedings of the IEE Tutorial Colloquium on “Design of RFICs and MMICs” (pp. 2/1-14). Hsu, Y. C., et al. (2007). Single-chip FR Frount-end MMIC using InGaAs E/D-pHEMT for 3.5 GHz WiMAX Applications, In Proceedings of the 2nd European Microwave Integrated Circuits Conference, Munich Germany, Oct, 2007 (pp. 419-422). Huang, F.J., & O., K. (2001). A 0.5-&m CMOS T/R Switch for 900-MHz Wireless Applications. IEEE Journal of Solid State Circuit, 36(3), 486-492. Kelly, D. (2005). The State-of-the-Art of Silicon-on-Sapphire CMOS RF Switches. IEEE CSIC Digest, 2005, 200–203. Ketterl, T., & Weller, T. (2005). SPDT RF MEMS switch using a single bias voltage and based on dual series and shunt capacitive MEMS switches. European Microwave Conference 2008 (Vol. 3, p. 4). Makioka, S. (2001). Super Self-Aligned GaAs RF Switch IC with 0.25 dB Extremely Low Insertion Loss for Mobile Communications Systems. IEEE Trans. On Electron Devices, 48(8), 1510–1514. doi:10.1109/16.936499 Marsh, S. (2006). Practical MMIC Design. Norwood, MA: Artech House. Mayer, M., & Arthabar, H. (2001). RF Power Amplifier Design. Department of Electrical Measurements and Circuit Design, Vienna University of Technology. Naders, C. (2006). Design of a Power Amplifier Based On Si-LDMOS for WiMAX at 3.5GHz. Rasmi, A., Marzuki, A., Azmi Ismail, M., Abdul Rahim, A. I., Yahya, R., & Mat, F. A. (2008). Design of 2-Stage Medium Power Amplifier Using 0.5 μm GaAs PHEMT for Wireless LAN Applications. In TENCON 2008 – 2008 IEEE Region 10 Conference (pp. 1-5). Raton, M. G. B. (2001). The RF and Microwave Handbook. CRC Press LLC. Robertson, I. D., & Lucyszyn, S. (2001). RFIC and MMIC design and technology. London, UK: The Institution of Electrical Engineers. Schindler, M. J. (1987, Dec.). DC-40 GHz and 20-40 GHz MMIC SPDT Switches. IEEE Transactions on Electron Devices, ED-34(12), 2595–2598. doi:10.1109/T-ED.1987.23359 Simcoe, E. (2007). E.A 3.3V, 2.4GHz 0.5μm GaAs Common-Source, Two-Stage Low-Noise Amplifier. John Hopkins University.

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Smith P. L. (2006). MMIC Design. Sweet, A. (2003). RFIC Design Elen 351, Lecture 9: RF Switch Design (pp. 1-53). Takasu, H. (1996). W-Band SPST Transistor Switches. IEEE Microwave and Guided Wave Letters, 6(9), 315–316. doi:10.1109/75.535830 Tanaka, T. (1997). Low-voltage operation GaAs spike-gate power FET with high power-added efficiency. IEEE Transactions on Electron Devices, 44, 354–359. doi:10.1109/16.556143

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Practical Approaches

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Chapter 10

Inventions of Monolithic Microwave Integrated Circuits Arjuna Marzuki Universiti Sains Malaysia, Malaysia

ABSTRACT This chapter deals with the concept of first time right IC. A development of subsystems for wireless application is used as test case. The subsystems are Low Noise Amplifier (LNA), Medium Power Amplifier (MPA) and Variable Signal Generator (VSG). Several issues such as suitable multiband design flow and high speed switch must be solved. A new design methodology of integrated circuits for multiband application is presented. The design methodology is modified from a typical Monolithic Microwave Integrated Circuit (MMIC) flow. Core based design, parasitic aware approach and power constrained optimization are introduced into the new design flow. The same core circuit topology is used as main block to design 2.4 GHz and 3.5 GHz LNA and MPA. A power constrained optimization is applied to a test case amplifier i.e. broadband amplifier to get the optimized RF performance. The optimization is simulation-based technique. A 0.15 µm 85 GHz PHEMT is used in designing the LNA, MPA and broadband amplifier. This chapter also introduces the inventions of Voltage Controlled Oscillator (VCO), Mixer, Low Noise Amplifiers (LNA), Power Amplifiers (PA) and Transmit-Receive Switch (T/R). These circuits are crucial components for RF and Microwave front-end integrated circuits. The elements of inventions of circuits are clearly explained. The inventions reflect the requirement or the need of solving current problem using available technology.

INTRODUCTION Due to increase in demand of multiband solution, it is therefore necessary to understand design methodology of multiband transceiver. A typical Monolithic Microwave integrated circuit (MMIC) flow (Bahl, 2005) is normally used in designing MMIC and Radio Frequency Integrated Circuit (RFIC). It has a comprehensive flow starting from defining specification until two-dimensional analysis of layout. Nevertheless, the flow requires many iterations in designing stage, due to uncertainty in layout and parasitic. DOI: 10.4018/978-1-60566-886-4.ch010

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Inventions of Monolithic Microwave Integrated Circuits

The design flow does not specifically cater for multiband design. This will be discussed in this chapter. Apart from the design flow, core circuit, LNA, MPA and switch design will be also covered. This is important for ‘First time right IC’ concept. In designing Monolithic Microwave Integrated Circuit (MMIC) for commercial needs or research endeavor, the knowledge of the current state of the art of current work is important. Nevertheless, one must be cautious not to infringe the design or inventions. This chapter has five main circuits or inventions to be discussed; the VCO, Mixer, LNA, PA and T/R Switch. These five circuits are arranged under different topics for clarity. Multiband and reconfigurable concept is current state of the arts and also future trend for integrated circuit solution to support advanced technology such as 4-G technology.

FIRST TIME RIGHT IC CONCEPT Background Design Flow A Typical MMIC or RFIC design flow is to start with topology analysis with respect to specifications. Topology is then simulated at schematic level to verify the performance against the specification. Selection of device (transistor) size is important for bandwidth, DC power consumption, noise figure and non linear performance tradeoff. In addition to the tradeoff, the right size of devices can facilitate easier input and output matching. The design is then convert into the layout and post-layout simulation which is could be in the form of 2-D simulation is done to verify the performance against the schematic simulation or specifications. If the performance is not similar to the specifications, the design layout has to be modified. The process is repeated until the specifications are met. The flow (Bahl, 2005) is reproduced in Figure 1 for clarification. Smith chart (Smith, 1969) is one of the earliest synthesis tools for impedance matching for microwave transistor amplifier. One of the earliest work employing smith chart as part of synthesis technique is reported in (Siddiqui, 1979). The work employs smith chart to locate the noise and gain contour, the matching circuit is then synthesized using numerical calculation. The technique can be divided into three major parts, generation of the broadband impedances to be presented at the device input and output terminals for obtaining, respectively, the gain and output power performance as a function of frequency, construction of a positive real driving point impedance function to represent the above impedances, and realization of a lossless lumped-distributed network terminated in a 50 Ω resistance, derived from the impedances. The impedances is derived using reverse application of the asymptotic techniques. The impedance that leads to instability must be avoided and magnitude and phase of the impedance must be compatible. Recent synthesis tool released by Applied Computational Science (ACS) (Henkes, 2005) used smith chart heavily in automate low noise amplifier design. Couple with simulation tool (analysis tool), a design such as LNA can be performed in only a matter of minutes. However, the synthesis tool is meant to be used for RF discrete design i.e. not RFIC. Eagleware-Elanix produces two synthesis modules (AMPLIFIER and MIXER) (Eagleware-Elanix, 2005) in year 2005. The MIXER synthesis module allows the user to design and analyze mixer configuration. 11 topologies of the mixers are available. While, the AMPLIFIER synthesis module facilitates

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Figure 1. Typical MMIC design flow

the design of linear low noise RF amplifier. The tool is friendly with system level simulation tool is a bonus for RF design. Work (Siddiqui, 1979; Henkes, 2005; Eagleware-Elanix, 2005) can be considered simulation-based synthesis tool. Work (Zhang, Dengi, & Carley, 2002) is also one of simulation-based synthesis tool. The work is capable to produce several designs which are placed in database. Clearly mentioned by the authors, the simulation-based synthesis tool requires minimal preparatory effort compared to knowledge-based tools. The design of a radio frequency circuit whether for discrete or integrated design involves numerous trade-offs between competing specifications including power, noise, gain, linearity, stability, impedance match among others. Unlike most optimization/tuning tools, the synthesis tool does not require a starting point. This work uses cascode LNA for a test case, the required inputs are test benches (S- Parameter, Noise Figure and DC, IIP3 and large signal 1 dB compression point) and design variables which are set by rough hand calculation. The authors further remark that optimization approach tackles an optimization problem with multiple goals by decomposing in into a few sub problems and solving them one by

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Figure 2. Synthesis flow diagram

one such the approach require many design iterations to meet all the goals. Unlike a circuit synthesizer synthesize all design variables at the same time. Figure 2 shows a typical circuit synthesizer, the results are stored in design database, the results are normally processed through data mining to understand the trade-offs. The drawback of the work is it requires 2 days to complete the task. Basic Analog/RF circuit synthesis and optimization offers to increase design productivity. The goal of analog circuit synthesis is to create a ‘sized’ circuit schematic from given specifications (Gielen, 2006). The sizes and biasing of all devices in the circuit have to be determined such that the circuit meets the specification. It is the optimization engine that determines these ‘optimal’ values. Typical optimization algorithms used are simulated annealing and genetic or evolutionary algorithms. Another recent trend is the move towards multi-objective optimization. This approach generates a set of design solutions, spread over the pareto-optimal trade-off hyperfront, so that designers can a posteriori decide on the final design. A warning by the authors regarding the simulation-based optimization methods is the run time. Work (Massoud, 2006;2007) summarizes a unique solution on the LNA synthesis. The work offer accuracy in synthesizing of LNA where numerical synthesis is applied. The work closely integrated the function of synthesis and optimization of the LNA. The authors claimed the work is suitable for systemon-chip (SoC) technology, where it takes account deep sub-micron effects. The proposed work employs numerical optimization and synthesis technique. It can achieve performance, area, and power specifications that are not possible to obtain using conventional equation-based design techniques. The authors have also claimed, the design automation techniques can deliver high yield. The mentioned conventional equation-based design technique make use of explicit expressions for the LNA design parameters that optimize certain figure of merits such as noise figure, return losses, gain and numerous others. These techniques provide important insights into the relationships between design parameters, which are essential for the development of new LNA topologies and initial manual design efforts. Nevertheless, due to the simplifying assumptions necessary to create explicit expression for optimum component values, these techniques may not account for the inductor or device parasitics and lack the flexibility to realize component values that are suitable for SoC application. Analytical model of fully integrated LNA is developed with all the parasitics components; this complex model is well-suited for numerical LNA optimization. The proposed work shows the capability to do either multi objective optimization or single

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objective optimization. To synthesize LNA with multi objective optimization, pareto-optimal trade-off surfaces relating each of these design metrics is created. The pareto surfaces can be created by utilizing either the Normal Boundary Intersection (NBI) method or the ε-constraint method. For single objective optimization, sequential quadratic programming which is a nonlinear programming technique that exploits the gradients of the objective and constraint functions at each iteration to accelerate convergence. As mentioned in previous paragraph, equation-based design technique provide important insights into the relationships between design parameters, which is essential for the development of new LNA topologies and initial manual design efforts, therefore it normally used in design optimization (Nguyen, Kim, Ihm, Yang, & Lee, 2004). EM Simulator is normally used to analyze 2-Dimensional analysis of matching network (distributed components); the simulator can be used to model circuit elements such as waveguide structures, discontinuities, coupling between transmission line, structures using multilayer dielectric, capacitors, via holes and crossover. There is yet available comprehensive EM simulator for complex MMIC chips such as T/R chips because of the large circuit size and increase CPU time.

Broadband LNA Design Based on Basic Shunt Feedback (Marzuki et al, 2004) Crucial parameters of the LNA are low noise figure, high gain, high linearity and low power consumption. These parameters are difficult to achieve simultaneously. The Input matching and output matching to the amplifier would be the fundamental elements for good return losses of the LNA. The input and output matching circuit can be implemented off-chip or on-chip. To design the matching circuit on-chip would be costly as matching circuit components such as inductor and capacitor consume silicon area. The inductor is normally not precise and has low Q factor. To ease the matching, the right size of transistor must be used and it is often difficult to modify the transistor for a designer needs as the foundries fix the transistor size. It is found that by implementing a feedback element between transistor’s collector and base gives good return loss; in fact the input and output matching are no more needed. It is also found that the feedback amplifier has achieved reasonable noise figure and gain. Parasitic components are also important and must be included in the final design. There are at least two methods to design a Monolithic Microwave Integrated Circuit (MMIC) amplifier. The first method is to use the scattering parameters (s-parameters) method and the second method is the impedance method. The s-parameters method uses the gamma opt, noise resistance, noise circles and gain circles to design a MMIC amplifier. This method is normally used at high frequency typically at microwave and millimeter range. The method is used to enhance the impedance method, which is not quite useful at high frequency. Even though the s-parameters are related to impedance of the device but it is often disguised as scattering signal. The impedance method or equation-based method is mentioned in previous section is a low level method and has accuracy issue compared to the s-parameters method. This method is easy, cheap and with good understanding the results of using it is still acceptable as using the s-parameters method. Basically there are many topologies for the broadband amplifier. Some of them are Darlington amplifiers and multistage amplifiers. Most of the amplifier topologies use some sort of negative feedback element to enhance the bandwidth of the amplifier. To design MMIC amplifier requires special attention to the input and output of the amplifier compare to low frequency amplifier or opamp. A special amplifier such as LNA requires special attention to the noise elements in the amplifier. Majority of the

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feedback amplifiers can be categorized into 4 kinds of feedback amplifiers i.e. series-shunt, shunt-shunt, shunt-series and series-series configuration. The most popular feedback amplifier is shunt-shunt amplifier (Figure 3). This amplifier is also known as transimpedance amplifier. From small signal analysis the shunt-shunt amplifier input resistance Z i is: Z i ≅ Z F AV

(1)

Where Z F is the feedback impedance and AV is the gain. The output resistance, Zo is: Zo = Z F gm

(2)

Where Z F is the feedback impedance and the gm is transconductance. From the above equations, output resistance can be set low, near 50 Ω, hence higher input and output return loss can be achieved. The biggest advantage of this topology is wide bandwidth. The noise is still acceptable even though the main culprit of noise now would come from the feedback element. For the noise analysis of the shunt-shunt amplifier, the amplifier is assumed to be a bipolar transistor in common emitter configuration (Leach, 1994). Thermal noises and shot noises are covered in the Equation (3). Because of the high operating frequency the flicker noise is omitted in the equation. The equivalent input noise current, N i is:  4kT ∆f Ni =   R || Z F  S  r 2qI b ∆f 1 + b  R

  1 + rb + rE  +  RS || Z F  2

+ rE   +  S || Z F 

2 1  rb + rE VT    1     2qI c ∆f  + +  I c     β RS || Z F  β 

(3)

12

Figure 3. Feedback amplifier

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Setting the feedback impedance larger than the source resistor and making emitter resistor small can minimize the noise. Optimizing the current consumption would also reduce the noise. In order to design an LNA, carefully chosen parameters such as Z F , the base spreading resistance, rb and emitter resistance, rE and current consumption, I c must not affect the other parameters such as the return losses and power gain. The current gain, β of transistor is also crucial in the noise equation. For accurate high frequency noise analysis the β must be frequency dependent not DC current gain. The noise factor of the amplifier is the ratio of equivalent input noise current, N i to the noise current of the source resistance. The model accuracy of the passive component is also important especially for the bond pad and capacitor. The bond pad is modeled as 0.5pF capacitor and bondwire as 1nH inductor. In this design, capacitor size will be much bigger than resistor size therefore the capacitor model is more crucial than resistor model. The high frequency model for capacitor is shown in Figure 4.

The Effect of Parasitic Components to LNA Performance This SiGe process technology has three metals and silicon dioxide as dielectric. The capacitance per unit area (metal 3-metal 2) is 0.5fF/sq μm, capacitance per unit area between metal 2-substrate is 0.02fF/sq μm, capacitance per unit area for the silicon substrate is 0.0008fF/sq μm, conductance per unit area is 0.01μS/sq μm, metal 3 sheet resistance is 0.018 Ω/sq and contact resistance is 0.3 Ω. The series capacitance, Cs in the model is designated value i.e. 1pF. Using the equations derived in (Yue et al, 2008), series inductance, Ls is 17pH, series resistance, Rs is 0.32 Ω, oxide capacitance, Cox is 0.04pF, substrate capacitance, Csi is 1.6fF and substrate resistance, Rsi is 50k Ω. From Figure 5, S21 (marker m1) with parasitic components is 11.97dB, which is about 2.7dB lower than S21 (marker m2) with ideal components. S12 (marker m3) with parasitic components is about 1.6dB higher than S12 (marker m4) with ideal components.

MOSFET as a Switch NMOS Switch A MOS transistor by itself can form a simple on-off switch with a source (S), gate (G) and Drain (D). Figure 6 shows the symbol for an NMOS transistor. The gate controls the conductivity of the two termiFigure 4. Capacitor high frequency model

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nals. The drain and source can be interchangeable due to the device is symmetric. Hence a MOS switch is a bi-directional switch. When operating as a switch, a channel is conducted between the source and the drain if a potential difference of at least VTH exists between the gate and source. The switch is said to be “on”. Similarly, if the voltage different between the gate and source is less than VTH, the switch is “off”. The off state of a transistor creates a high impedance condition, Zhi at the drain. No current flows from source to drain. An NMOS device has positive threshold voltage and higher operating frequency as compared to PMOS device, so NMOS is normally chosen to operate as a switch (Razavi, 2001, Huang & K, 2000, Jin & Nguyen, 2005). An ideal switch should have an infinite off-resistance and zero on-resistance. However, an NMOS switch has a drawback such that the conductivity of the channel between the two terminals is strongly dependent on the potentials of the terminals, relatives to the channel potential. The on-resistance can be expressed in the simplified Equation (4) (Lillebrekke, Wulff, & Ytterdal, 2002).

Figure 5. S21 and S12 with parasitic and no parasitic results

Figure 6. Symbol of NMOS transistor

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RON ≈

1 = gds

1 W µ ×COX (V −VTH ) L GS

(4)

Optimizing the performance of an MOSFET switch requires a number of trade-offs. If the width/ length ratio is increased to reduce RON, the parasitic capacitance of the gate oxide will increase proportionately resulting in lower bandwidth (Li & O, 2005). In analog or high-frequency applications, detail study and investigation are needed for the NMOS switch because in reality an NMOS switch is impossible to be an ideal switch. Some imperfections of the NMOS switch will bring crucial defection of the design.

Transmission Gate Shown in Figure 7 is a simple view of CMOS transmission gate. CMOS transmission gate (TG) is a simple switch circuit consists of one NMOS and one PMOS transistor, connected parallel. The gate voltages applied to these two transistors are set to be complimentary signals. As such, the CMOS TG operates as a bi-directional switch between the nodes A and B, which is controlled by signal C. If the control signal C is logic-high (equal to VDD), both transistors are turned ‘on’ and provide a low-resistance current path between node A and B. If the control signal C is low, then both transistors will be ‘off’ and the path between nodes A and B will be an open circuit. This condition is also called the high-impedance state. The biggest advantage of a transmission gate is the constant total equivalent resistance. It is independent of the output voltage. This is desirable as compared to the individual equivalent resistance of the NMOS and PMOS transistors are strongly dependent on output voltage (Kang & Leblebici, 2003). Transmission gate is popular in logic circuit design. For example, a multiplexer can be obtained easily by using transmission gate. In high frequency design, due to the complementary clocking input is not perfect, the charge injection problem becomes harder to be resolved.

Figure 7. Transmission gate

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Charge Injection In reality, it is not possible to have an ideal MOS switch. When the MOS transistor conducts, a finite amount of mobile carriers are stored in the channel. The total charge in the inversion layer can be expressed as Qch = WLCOX (VDD −Vin −VTH )

(5)

When the transistor turns off, the channel charge exits through the source and drain terminals as shown in Figure 8. This phenomenon called “charge injection”. The charge injected to the input node is absorbed by the input source, creating no error. However the charge injected to the output node superposes an error component to the output voltage, where a negativegoing voltage spike is manifested. In addition to the charge from the intrinsic channel, the charge associated with the feedthrough effect of the gate-to-diffusion overlap capacitance also enlarges the error voltage after the switch turns ‘off’. The fraction of charge that exits through the source and drain terminals is a relatively complex function of various parameters such as the impedance seen at each terminal to ground and the transition of the on-off control signal (Razavi, 2001, Shieh, Patil, & Sheu, 1987).

NMOS Switch-Design Issues and Discussion A quick simulation of the NMOS switch is shown in Figure 9. The (W/L) of NMOS device used in this simulation is 50 μm/1μm. The input signal is an ideal sine wave with amplitude 200 mV and frequency 3.35 GHz. It is clear to see that the switch does not perform ideally according to the specification. There are two major issues in the NMOS switch that need to be eliminated in order to get a good switch. They are: transient spike at the transition from the switch “off” to switch “on”; and the negative going voltage when the switch is off. A MOS device exhibits inherent parasitic capacitances. These capacitances cannot be avoided. A non-ideal switch can be modeled as in Figure 10. Terminal C is the gate of transistor; terminal A or B can be drain or source. Vc controls the switch to be on or off, the ron is ideally 0 while rOFF is ideally infinite. All the capacitors represent the parasitic capacitance and IOFF is the leakage current when the switch is off. As can been seen an NMOS switch in Figure 11, where the C represents the total parasitic capacitance between the gate and the output node.

Figure 8. Charge injection when the switch turns off

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Figure 9. Transient response of single NMOS switch

It is known that C = dQ / dV ABC , where dQ is the magnitude of differential change in charge on one plate as a function of the differential change in voltage dV across the capacitor. The fundamental property of capacitor is it resists any sudden change of voltage across it. Thus when there is a sudden change in VG, from 0V to VDD, the voltage at the output node is increased for the amount that is sufficient to maintain the charge between the capacitor. Hence a voltage spike equal to the difference occurs at the output node. When the switch is on, there is a channel conducting under the NMOS gate and between the source and drain to allow the input signal passes to output node. Certainly there are some charges present in the channel. The charge in the channel is on the order of COX (VGS-VTH). When the switch is turned off, these charges either flow to the input source or the output node. The total charges flow to the input source or output node is a function of several parameters, which include input impedance, source impedance, control voltage falling edge and etc. To the first order, 50% distribution between the input source and output node can be assumed. This charge injection phenomenon makes the switch not totally off in off state.

THEORY AND CONCEPT Parasitic-Aware-Core-Base (PACB) Typical MMIC or RFIC design flow is to start with topology analysis with respect to specifications. Topology is then simulated at schematic level to verify the performance against the specification. Selection of device (transistor) size is important for bandwidth, DC power consumption, noise figure and non linear performance tradeoff. In addition to the tradeoff, the right size of devices can facilitate easier input and output matching. The design is then convert into the layout and post-layout simulation which is could be in the form of 2-D simulation is done to verify the performance against the schematic simula-

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Figure 10. Model of non-ideal switch

tion or specifications. If the performance is not similar to the specifications, the design layout has to be modified. The process is repeated until the specifications are met. The flow (Bahl, 2005) is reproduced in Figure 12 again for clarification. In order to reduce design iterations (especially iteration 2) as shown in Figure 12, a design flow as reported in (Wang, 2006) can be used to give full considerations for the effects that parasitic have on circuit performance. The concept of this flow is to run schematic simulation with known parasitic information that might come from transmission line, inductor, resistor and etc. Thus, this will reduce number of iteration. Reduction in iteration 2 indicates reducing number of design cycle using the 2-D simulation. This flow is suitable for millimeter wave frequency application; it is however normally ignored for circuit design with frequency of operation less than 3 GHz. Figure 11. NMOS switch with parasitic capacitance

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The circuit design flows discussed above does not explicitly cater for multiband solution, and low power design. Multiband RFIC designs use many approaches; wideband design, parallel design and single design with flexible matching components. This work discusses core-based design approach which can also deliver Multiband RF and microwave frequency circuits. The approach is similar to the latter approach and it will replace the circuit topology process as shown in Figure 12. This new process would allow different frequency band amplifier to be designed. This is done by using the same core circuit but with different components for matching. This approach is useful for highly integrated multi-standard application integrated RF Front-end silicon based design (Rossi, Liscidini, Brandolini, & Svelto, 2005). The proposed approach does not cater analytical modeling. Work (Ragheb & Nieuwoudt, 2007) does cater on analytical modeling but not on multiband solution. The work does however have the capability of multiband solution. A custom model which is based on measurement must first be developed. The models are interconnect and passive device models. This custom model is used in core circuit topology parasitic aware process (see Figure 13). For high frequency design, the tradeoff between power consumption and bandwidth Figure 12. Typical MMIC design flow

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is more complex for two stage amplifier. The design of the amplifier is optimized using Agilent ADS to meet simultaneously multiple design specifications such as bandwidth, noise figure, power gain and power consumption. This is called power constrained analysis and it combines with stability analysis. The proposed design flow is clearly depicted in Figure 13. The proposed design flow with custom model suggests that for first time right IC requires at least 2 times fabrication for any integrated circuits.

LNA, MPA and Broadband Amplifier Circuits Theory In this section, some of circuits are implemented using the proposed design flow, namely Low noise amplifier, Medium power amplifier and broadband amplifier. This section discusses design theory of these circuits. A 0.15 μm Pseudomorphic High Electron Mobility Transistors (PHEMT) technology is used in designing these circuits. The selected components value will be discussed in the simulation result section.

Figure 13. Proposed design flow

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Low Noise Amplifiers Several RF front-ends in parallel, each dedicated to a single standard, are usually adopted (Kaczman et al., 2006). Broadband topologies have been proposed to process signals belonging to different standards (Bruccoleri, Klumperink & Nauta, 2003) (Adiseno, Ismail & Olsson, 2002). The main disadvantages of this approach is it cannot meet stringent linearity requirement Basically, applying shunt feedback to a common source amplifier as shown in Figure 14 is a good core circuit for broadband amplifier. This technique allows the amplifier to be matched over a broad bandwidth while having minimal impact on the noise figure of the stage (Rogers, 2003). Referring to Figure 14 the resistor forms the feedback and the capacitor is added to allow for independent biasing of the gate and drain of the transistor. The capacitor can normally be chosen so that it is large enough to be a short circuit over the frequency of interest. This topology offers inferior isolation between output and input. The work in this research is focused on developing this circuit as core circuit and consequently devices for 2.4 GHz and 3.5 GHz application.

Shunt Feedback Amplifier From Figure 14, the amplifier closed-loop gain, AV AV = −

1   GF (1 + 1 )   AOL 1  +   GS AOL      

(6)

where GF, GS, AOL is conductance of feedback resistance, conductance of source resistance and openloop gain respectively. The closed-loop gain will be equal to an open-loop gain if GF approaches zero. In Figure 14. Shunt feedback amplifier

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this case, the open loop gain is referring to transistor gain without feedback topology. An amplifier with the resistor feedback can achieve self matching (Marzuki, Zulkifli, Mohd-Noh, & Abdul-Aziz, 2004)

Core Circuit S-Parameter Analysis At low frequency, the core circuit can be represented as output current source and output load (see Figure 15) (Archer, Weidlich, Pettenpaul, Petz, & Huber, 1981). To define input resistance of the above circuit, test current is applied into the gate of transistor. I in =

VIN −VOUT RF

(7)

Rearrange Equation (7), I in =

VIN − AVVIN V , where AV = OUT RF VIN

Therefore, input resistance, Rin =

RF 1 − AV

(8)

Figure 16 is used to define gain. The feedback current, −I F = gmVIN +

VOUT Rload

Figure 15. Core circuit with test current, Iin

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Inventions of Monolithic Microwave Integrated Circuits

and −

(Vout −VIN ) V = gmVIN + OUT , RF Rload

re –arrange this equation into gain, VOUT (1 − gm Z F )RLOAD = VIN Rload + RF

(9)

Equation (9) can also be arranged as AV =

VOUT −(gm − g F )RLOAD = VIN 1 + g F RLOAD

(10)

where gF = 1/RF. Replace into Equation (8) yields RIN =

1 + g F RLOAD g F (1 + g F RLOAD + (gm − g F )RLOAD

Figure 17 shows S11-Gamma In relationship. Input reflection coefficient or Gamma In, Γin =

b1 RIN − RO = , a1 RIN + RO

Figure 16. Circuit to define gain

256

(11)

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where RO is characteristic impedance (Zo). Gamma In = S11 if S12 is large enough or a2 = 0, i.e. very high isolation, or device is unilateral. By replacing Equation (11) into Gamma In, and for Rload = RO. 1 − (gm g F )RO 2 S11 = 1 + 2g F RO + gm g F RO 2

(12)

From Figure 17, the power gain, S21 = b2/a1 when a2 = 0 Figure 18 shows S21 explanation. VIN = a1 + b1, VOUT = a2 + b2 = b2 [a2 = 0]. Using KCL at node A, we have −

(Vout −VIN ) V = gmVIN + OUT , rearrange RF Ro

VOUT (RO + RF ) = VIN (1 − gm Z F )RO , and b 2(RO + RF ) = (a1 + b1)(1 − gm Z F )RO and because b1=S11*a1 b 2(RO + RF ) = (a1 + S11 * a1)(1 − gm Z F )RO , so b 2(RO + RF ) = a1(1 + S11 )(1 − gm Z F )RO , Since, S21 = b2/a1, Figure 17. Circuit to explain S11- gamma in relationship

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Figure 18. Circuit to explain S21

S 21 =

(1 + S11 )(1 − gm Z F )RO , or (RO + RF )

S 21 = (1 + S11 )AV ,

(13)

Obviously, the power gain is proportional to voltage gain, AV.

High Frequency Core Circuit Analysis The transmission line has self inductance which is LSELF (H ) = propagationdelay(s / µm ) × impedance(Ω) × Length(µm )

(14)

Where propagation delay is approximately square root of effective permittivity divide by speed of light, impedance is impedance of the transmission line and length is the length of the transmission line. At high frequency the core circuit can be represented as output current source and output load with Zin’ (frequency dependent component). This is shown in Figure 20. To define input resistance of the above circuit, voltage source, VIN is applied into the gate of transistor. So KCL at node A. input current, I in =

VIN (V −VIN ) − OUT Z in ' RF

Rearrange Equation (15) I in =

258

VIN (A − 1)VIN V − V , where AV = OUT Z in ' RF VIN

(15)

Inventions of Monolithic Microwave Integrated Circuits

Figure 19. Basic core circuit

Therefore, the final input impedance, Z in =

Z in ' Z F Z F − Z in '(AV − 1)

(16)

b1 Z in − ZO = , where ZO is characteristic impeda1 Z in + ZO ance (Zo). Gamma In = S11 if S12 is large enough or a2 = 0, i.e. very high isolation, or device is unilateral. By replacing Equation (16) into Gamma In, The input reflection coefficient, Gamma In, Γin =

S11 =

Z F + ZO (AV − 1) − j ωC gs Z F ZO Z F − ZO (AV − 1) + j ωC gs Z F ZOo

Where, Zin ' =

(17)

1 jωCgs

Figure 20. Core circuit with voltage source, VIN

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Figure 21 and 22 show single transistor model with its noise sources. Vi is equivalent input noise voltage, while Idn is output noise current. To convert output noise current to become Vi, short circuit input and load both circuits. For Figure 21, Io = Idn where I dn 2 = 4kTΔfgmP, and P = 2. For Figure 22, Io = gmVi, so equate two condition, Vi 2 = I dn 2 /gm2 Figure 23 shows shunt feedback amplifier with noisy transistor. Feedback resistor, Rf has its equivalent noise source, If, the value is I f 2 =4kTΔfgf. Figure 24 depicts the amplifier with its equivalent noise sources. To define the input noise voltage, Ii, both circuits (Figure 23 and 24) must be open circuit and equate with output noise. From Figure 24, I i 2 = IO 2 while from Figure 23, IO 2 = I i 2 + I f 2 + Vi 2 / Rf2. If equivalent input noise current of transistor is zero, now IO 2 = I f 2 + Vi 2 / Rf2. Therefore the equivalent noise current of the amplifier, I i 2 = I f 2 + Vi 2 / Rf2. The equivalent noise voltage of the amplifier can be assumed to be same as the transistor, i.e. Vi 2 = I dn 2 /gm2. Figure 25 is normally used for Noise Figure representation of an amplifier. The input noise voltage of the amplifier is Vi 2 + I i 2 *Ro2. The noise factor (F) or figure (in dB) is the ratio of total input noise voltage over noise voltage due to source resistor. F=

VS2 + Vi2

F = 1+

VS

+ I i2 *R o 2 2

, where VS2 = 4kTΔfRs, so by replacing all the values, the noise factor,

PRo P + + gf Ro gm Ro gm Rf 2

With conditions as below gm >> 1/rds, Ro<< rds

Figure 21. Equivalent of transistor with noise sources

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(18)

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Figure 22. Equivalent of transistor with Vi

Input return loss of the core circuit, S11, Z + Z (A − 1) − j ωC Z Z F O V gs F O S = 11 Z − Z (A − 1) + j ωC Z Z F O V gs F O

(19)

And S21 = AV(1+S11)

(20)

Figure 23. Shunt feedback amplifier with noisy transistor

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Figure 24. Shunt feedback amplifier with equivalent noise sources

LNA Design Figure 26 shows the schematic of the LNA. CO, LG and LD are matching components for LNA while the LNA core circuit is within the dashed box. M1 and M2 are depletion mode devices, RS is used to set voltage condition at M1 gate. CS is used to short RS at interested frequencies. RG is used to provide voltage to M2 while CG is used to eliminate any noise from the bias network. LS is used for stability. CD and RD are used to further stabilize the LNA core circuit. For a simple and intuitive gain equation of LNA, AV =

RFOUT = RFIN

gmcs Z L 1+

ZL + sC m 2−gd Z L rocs

(21)

Figure 25. Shunt feedback amplifier with equivalent noise sources and termination for noise figure calculation

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gmcs is transconductance of M1 with feedback network, ZL is load impedance of the LNA, rocs is output impedance of the M1 with feedback network. Obviously, RF which forms the feedback network will affect the gain of the LNA.

Medium Power Amplifiers The complete schematic of MPA with core circuit as discussed in previous section is shown in Figure 27. LG, LS, LD and LO are all implemented with on-chip spiral inductors. The inductors LG and LS are chosen to provide the desired input impedance. The inductor LD is a current source for the MPA and used for output power matching. The capacitor CC at the output plays a role for both DC block and output matching. The capacitor CO is used for network matching. The outputs are matched for high compression point, P1dB. The transistor size in the core circuit is bigger than transistor size in the core circuit in LNA section.

Broadband Amplifier The optimization process as shown in Figure 13 is discussed in this section. The purpose of the optimization is to design an amplifier with objective of achieving optimum performance in bandwidth, noise figure, power gain and power consumption. The optimization technique used here is simulation based technique. Agilent ADS software is used to implement the optimization. This technique would reduce the number of design cycles. Figure 28 shows two stage RC feedback amplifier. Two RC Feedback amplifiers topology is used due its high gain performance while RC feedback is employed for stability

Figure 26. LNA circuit for 2.4 GHz and 3.5 GHz

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Figure 27. Single-ended medium power amplifier for RF frequency of 2.4 GHz and 3.5 GHz

and easy matching (Marzuki, Zulkifli, Mohd-Noh, & Abdul-Aziz, 2004). CCC in the circuit is a coupling capacitor while L is external components. Input resistor, RIN, Input capacitor, CIN, output resistor, ROUT, output capacitor, COUT, output resistor of second stage amplifier, ROUT2, and output capacitor of second stage, COUT2, are primarily used to stabilize the circuit whereas source resistor, RS, bypass capacitor, CS, source resistor of second stage, and Figure 28. Two stage RC feedback amplifier

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Inventions of Monolithic Microwave Integrated Circuits

RS2, bypass capacitor of second stage, CS2 are used to bias M1 and M2. In addition, feedback resistor, RFB, feedback capacitor, CFB, feedback inductor, LFB, feedback resistor of second stage amplifier, RFB2 and feedback capacitor of second stage, CFB2, are used as feedback networks for M1 and M2 respectively. These feedback components are undoubtedly can affect the performance of the whole circuit. Amplifiers are often compared using figure of merit (FOM) (Linten et al., 2004), the better the FOM the better is the design. The formula of FOM is shown in Equation (22). This FOM will be used as the performance parameter in the optimization. FOM =

S21 × Bandwidth (NF-1) × PDC

(22)

Where S21 is power gain, Bandwidth is 3-dB bandwidth, NF is noise figure and PDC is power consumption.

Variable Signal Generator Design The variable signal generator is designed with target technology of the Silterra 0.18 μm CMOS processing at a supply voltage of 1.8V. There are a few solutions to implement a variable signal generator. In this work, a direct and simple topology called “active oscillators” is proposed.

Active Oscillators Design Methodology “Active oscillators” is a method proposed to achieve the objective of variable signal generator in a direct way. It employs three local oscillators with center frequency of 3.35 GHz, 3.85 GHz and 4.35 GHz respectively based on the UWB specification. A switching network is used to switch between the center frequencies. Figure 29 shows the architecture of a variable signal generator with active oscillators topology. Assume that the sequence pulse generator that is used to control the switch is ideal and external; the focus is on the switch and oscillators design. Some design challenges can be expected based on the architecture proposed. Firstly the designed switch need to operate approximately to an ideal switch, which means it is able to pass the input signal to output node without distortion and with negligible delay during the “on” state; and it is able to block the input signal from passing through and no leakage during the “off” state. Only with good performance switches then the variable signal generator designed is possible to produce ideal waveform. Although the phase noise for oscillator is not a main concern in this work, the isolation between the oscillators and switch is important so that no leakage signal can pass through the switch. The design of active oscillators based or variable signal generator is mainly divided to three parts. The first part is the switch design, where an NMOS switch is investigated in details from the point of device physics concepts then the unwanted effect is identified. After that another switch topology is proposed to solve the problems. The second part would be the oscillator design. The main specifications of the oscillator are center frequency and amplitude. Phase noise of oscillator is not a major concern in this work. After the switch and oscillator are designed properly, they are integrated to form a part of variable signal generator. The load comes from switch will influence the oscillator and degrades the

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Figure 29. Block diagram of active oscillator solution

signal generated. In order to improve the performance, some modifications and optimization need to be done. Finally three oscillators and three switches are integrated to form a full variable signal generator.

Switch-Series Shunt Topology Series-shunt topology is proposed mainly to solve the charge injection phenomenon. In addition to charge injection, since the switch designed is operating at high frequency, the parasitic drain-source capacitance CDS provides a path for signals to pass through from drain to source. This is unwanted because it will degrade the off-state of the switch (Jin & Nguyen, 2005). Figure 30 shows the schematic of a series-shunt switch. Transistor M1 performs the main switching function, while the shunt transistor M2 are used to improve the isolation of the switch (Huang & K, 2000) The two transistors are controlled by complementary control voltage. When the main switch transistor is on and the shunt transistor is off, the switch performs as a usual NMOS switch. When the main switch is off, the shunt transistor is on to ground the leakage signal due to the parasitic drain-source capacitance. The shunt transistor also provides a path for the extra charge to be shorted to ground, and hence reduce the charge injection problem. The width of the shunt transistor is half of the main switch. This ratio can be intuitively selected based on the assumption that 50% of charges stored in the M1 channel are distributed to the output node when M1 turns off. CB1 is the bypass capacitor, which allows DC biasing of the output node of the switch. By applying the same DC voltage on the top plate of the bypass capacitor as the output node, DC power consumption is made negligible. RG1 and RG2 are gate bias resistances used to improve DC bias isolation. The typical value of the gate bias resistance is about 5 kΩ (Li & O, 2005). Without the gate bias resistances, the fluctuations of VGD and VGS of the transistors will be higher. These fluctuations will affect the channel resistance and also result in excessive voltage across the gate dielectric and cause breakdown (Huang & K, 2000)

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Figure 30. Schematic of series-shunt switch

The top plate of bypass capacitor, the output node, as well as the input node are biased at the same DC voltage to reverse bias the drain/source-to-substrate p-n junctions. This is purposely to reduce the junction capacitances and RF signal coupled to the substrate and thus decrease the insertion loss (Huang & K, 2000). In this work, all the three nodes are biased at 0.6V.

Oscillator Design – Cross-Coupled LC Oscillator A fully differential cross-coupled LC oscillator is used as the topology in this final year work. The schematic used is shown in Figure 31. The main reason the LC oscillator is chosen is due to the oscillation frequency can be easily controlled by the inductance and capacitance in the LC tank circuit. There are three oscillators that need to be designed in order to provide three different frequencies in variable signal generator. The values of L and C will determine the oscillating frequency based on fosc = 1 / 2π LpCp . The amplitude of the output would be IoRp, swing above or below VDD. Io is the overall current supplied by the current source and Rp is the resistance presents in the tank circuit. For the oscillator part, 0.6 V is used as VDD so that the integration of the oscillator and the switch can directly utilize the 0.6V offset voltage as the DC biasing voltage for the input node of the switch. The oscillators are designed by using silterra SILCMOS018 library. There are only ten fix values of inductance available in this library. Hence the value of L and C are calculated to get the desired frequency. As for the output amplitude, we a current value is decided and the value of Rp is calculated to get the amplitude that meets the design specification. Anyway, the first order calculation will never be accurate. Some tuning on the transistor width, value of C and R are needed to get the target result.

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Figure 31. Cross-coupled oscillator with NMOS current source (Razavi, 2001)

Design Issues and Discussion After the three local oscillators are designed, each oscillator is integrated with a switch. The switch directly connected to the oscillator definitely brings the effect of loading to the oscillator. A transistor is approximate to a resistor with the value of on-resistance when it is operating in triode region. When the transistor is cut-off, its resistance is very high and approximate to open-circuit. So when the seriesshunt switch directly connected to the RLC tank circuit, the loading effect is mainly comes from the main switch, M1 and the effect are different when the switch is on and off. As shown in Figure 32, it is clear that when the switch is on, the load connected to oscillator is the on-resistance of transistor M1. When the switch is off, M1 acts as open-circuit and it can be assumed that no load is connected to oscillator. So it is expected that the amplitude of the oscillating signal will be different when the switch is on and off. When the signal amplitude becomes not stable, it can be expected due to the occurrence transition noise. Thus a modification is done on the switch by adding another shunt transistor at the input node as shown in Figure 33. This brings a more symmetrical solution of switch and when the switch is off, transistor M3 is turned on and acts as RON3. If the width of M3 is chosen to be same as M1, the RON3 is equal to RON1. As a result, no matter the switch is on or off, there is a same load connected to the oscillator. Hence the amplitude of the oscillating signal would be stable regardless the switch is on or off. However this loading effect will give influence on the RLC tank circuit and bring some changes to the amplitude and frequency of the oscillator. So, after the integration, the value of W, Rp and Cp must be optimized in order to get the desired frequency and amplitude.

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Figure 32. Equivalent circuit of series-shunt switch when it is turned on or off

Three oscillators and three switches are integrated to form a complete variable signal generator. By properly controlling the pulse generator, the output can be switched between the three oscillators. However, now every output node of the switch is loaded by another two switches and oscillators. This loading effect will again degrade the output amplitude. The value of Rp in the oscillator must be tuned to recover back the amplitude. The width of the switch transistors is adjusted to get smoother transition of signal. Smaller width will have smaller parasitic capacitances and hence smaller transition spike. However smaller width will bring to larger on-resistance and thus the amplitude of the output signal is degraded more. The width of the switch must be tuned so that there is a balance between the tradeoffs. The full architecture of the variable signal generator is shown in Figure 34. Figure 33. Modified series-shunt switch

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Figure 34. Block diagram of multiband VCOs

Implementation The Gallium Arsenide (GaAs) Pseudomorphic High Electron Mobility Transistor (PHEMT) has good performances on the frequency range, noise figure, output power, and high efficiency with low distortion (Weitzel, 2003;Platzker & Bouthillete, 1995; Huang, Lee, & Chen, 2005; Komiak, Wang, & Roger, Figure 35. 200 µm and 1000 µm width transistors

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1997). Because of its superior performance over the metal oxide semiconductor (MOS) transistors, GaAs transistors have been used extensively to build the Radio Frequency (RF) power amplifiers and play an important role in the wireless communications. GaAs technology has lower R&D cost than CMOS R&D cost is another factor which lures companies to use the technology in power amplifier design (Meng & Wu, 2008). In this section, three circuits development are discussed; namely LNA, MPA and broadband amplifier. This section is divided according to the implementation of the devices involved in the study. Under each division, the functionality of each device is studied. The concept of PACB is implemented and discussed. Core circuit development is discussed and studied. Power-constrained technique which is part of proposed design flow is also discussed here.

Transistor Characterization The proposed design flow as discussed in section of theory and concept suggests a custom model must be developed. This section discusses the implementation of the model by characterization of transistor Cgs and transconductance. Cgs of the transistor can be extracted from s-parameter measurements,

Figure 36. CGS vs. width of transistors

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Figure 37. 200 µm, 400 µm, 600µm and 1000 µm width transistors Gm, drain current vs. VGS

C gs = −

1  1  2π f ⋅ Im   Ygs 

(23)

Where f is the interested frequency, Ygs = Y11 + Y12, this Y-parameters can easily be converted from s-paramerters.

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Figure 38. Normalized Gm, drain current vs. VGS

Experimental 4 different sizes of transistor, i.e. 200 μm, 400 μm, 800 μm and 1000 μm transistor width are fabricated and tested. In order to derive the Cgs density equation, two methods are evaluated. Two points method is simple gradient calculation based on the measured plot, whereas single point method is the ratio of Cgs over the 400 μm. Two points method gives Cgs density of 9.425x10-16 F/ μm while one point method gives 8.825x10-16 F/ μm. From Figure 36, it is obvious that one point method yields a close result to the measurement Cgs. The polynomial equation of CGS is equal to1.287 × 10−15 •Width(µm ) − 9.433 × 10−14 . Figure 37 shows the measured performances of fabricated transistors. From Figure 38, the polynomial equation for Gm vs Vgs, Gm(ms/mm)=0.4018-0.230∙Vgs-0.354∙Vgs2

(24)

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Inventions of Monolithic Microwave Integrated Circuits

Core Circuit Design For simplicity the analysis of the core circuit is only done at 5 GHz. Final core circuit is shown in Figure 39. Transistor; number of finger (NOF) = 10, unit gate width (UGW) = 100 µm, CF = 8 pF, Cs = 20 pF, RF = 500 Ω and Rs = 10 Ω. (g − gm )Ro Knowing, AV = F , and when gf = 1/500, gm = 0.2 S and Ro = 50 Ω. AV = - 9. To find S21, 1 + g F Ro S11 must first be calculated. Knowing that Equation (19), S11 =

Z F + ZO (AV − 1) − j ωC gs Z F ZO Z F − ZO (AV − 1) + j ωC gs Z F ZOo

, for Cgs = 3 pF and frequency = 5 GHz,

S11 = -0.847 – j0.3596, the magnitude is therefore equal to 0.919, or -1 dB. S21 = AV(1+S11), by replacing AV and S11 value, S21 = 10.98 dB. This RF performance is achieved when the transistor is self-biased with RS and consumed of 80 mA. This analysis will be compared with the simulation and measurement results in the results chapters.

Parasitic Aware in the Core Circuit Figure 40 shows the implementation of parasitic aware for the core circuit in ADS schematic.

LNA Design Figure 41 shows the complete schematic of the LNA. CO, LG and LD are matching components for LNA while the LNA core circuit is within the dashed box. M1 and M2 are depletion mode devices, RS is used to set voltage condition at M1 gate. CS is used to short RS at interested frequencies. RG is used to provide voltage to M2 while CG is used to eliminate any noise from the bias network. LS is used for stability. CD and RD is used to further stabilize the LNA core circuit. For LNAs design, the transistor M1 and M2 are Depletion-Mode pHEMT and have a gate width of 100 µm and 4 fingers. Transistor M1 and M2 is

Figure 39. Core circuit

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Inventions of Monolithic Microwave Integrated Circuits

Figure 40. Parasitic aware in the core circuit

Figure 41. 2.4 GHz and 3.5 GHz LNA

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biased at 0 V and 1 V respectively. In addition, all the components include inductors are on-chip passive components. Figure 42 and Figure 43 show the LNAs implementation in ADS.

Medium Power Amplifiers LG and LO square inductor while LS and LD are round inductor. All are implemented with on-chip spiral inductors. The inductors LG and LS are chosen to provide the desired input impedance. The inductor LD is a current source for the MPA and used for output power matching. The capacitor CC at the output plays a role for both DC block and output matching. The capacitor CO is used for network matching. The outputs are matched for high compression point, P1dB. The transistor size in the core circuit is bigger Figure 42. 2.4 GHz LNA

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than transistor size in the core circuit in LNA section. Figure 45 and 46 shows the MPAs implementation in ADS.

Broadband Amplifiers Transistor Size Determination In order to reduce input port sensitivity with respect to the load, transistor size must be determined. Figure 48 and 49 are simulated result using transistors measurement-based model with standard s-parameter test bench as shown in Figure 47. Figure 48 shows the range of transistor finger for S12 < -20 dB. Low S12 could reduce the sensitivity (Antonocelli, Antonocelli, Rizzi, & Castagnolo, 2000). Figure 49 shows S21 of transistor with different finger values. The required power gain of the amplifier is 18 dB, therefore it is decided to choose device finger which can deliver minimum gain of 14 dB throughout the operating frequency.

Figure 43. 3.5 GHz LNA

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Based from Figure 48 and 49, it is clear that finger value from 2 to 10 is chosen for the optimization Figure 50 shows two stage RC feedback amplifier. M1 is biased by using external bias Tee. Both transistors are depletion mode device and therefore, 0 V voltage is provided at the gate of M1. CCC in the circuit is a coupling capacitor while L, CC, RS, RL are external components with RS and RL equal to 50 Ω, CC equal to 100 pF and L equal to 0.1 μH. Input resistor, RIN, Input capacitor, CIN, output resistor, ROUT, output capacitor, COUT, output resistor of second stage amplifier, ROUT2, and output capacitor of second stage, COUT2, are primarily used to stabilize the circuit whereas source resistor, RS, bypass capacitor, CS, source resistor of second stage, RS2, bypass capacitor of second stage, CS2 and input resistor of second stage, RIN2, are used to bias M1 and M2. This configuration will ensure voltage at gate M1 and M2 to be 0 V. In addition, feedback resistor, RFB, feedback capacitor, CFB, feedback inductor, LFB, feedback resistor of second stage amplifier, RFB2 and feedback capacitor of second stage, CFB2, are used as feedback networks for M1 and M2 respectively. The gate width of M1 and M2 is 50 µm. Threshold voltage of the transistor is about -1.2 V. The target specifications for the amplifier is power gain, S21 = 18 dB, noise figure, NF = 3 dB, Bandwidth = 12 GHz and power consumption is 70 mW. The amplifier must stable at all frequencies (k > 1 (mu_load and mu_source). Table 1 shows the design variables which will be optimized to achieve the required speciFigure 44. Simulation schematic of the PHEMT single-ended medium power amplifier for RF frequency of 2.4 GHz and 3.5 GHz

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Figure 45. 2.4 GHz MPA circuit

Figure 46. 3.5 GHz MPA circuit

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Figure 47. Transistor simulation bench

Figure 48. Reverse transmission (S12) vs. frequency (VDD = 1.5 V, VGS = 0 V, UGW = 50 µm)

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Figure 49. S21 vs. frequency

Figure 50. Two stage RC feedback amplifier simulation setup

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fications. These design variables are the same for power-constrained and non-power-constrained. The current budget is 50 mA for the power constrained while no current budget for non-power-constrained. Figure 51 shows the setting for the optimization in Agilent ADS. OptimGoal5 is used to define the priority (Expr = ‘ID’) of the power consumption, by setting weight = 50, the design is optimized for power-constrained. OptimGoal1 with weight of 1 is for mu_source. OptimGoal2 is for mu_load, the setting is the same as mu_source. OptimGoal3 is for gain optimization with weight of 1 and OptimGoal4 is for noise figure optimization, the weight is 5. The selected optimization type is Gradient. It offers the fasted optimization time.

Variable Signal Generators The components value for switch will be tuned during simulation. This will be further discussed in next chapter.

Table 1. Synthesis Setup of Design Variables Design Variables

From

To

Step

RFB (Ohm)

10

550

1

Finger

2

10

1

CFB (pF)

4

7

0.1

ROUT (Ohm)

100

300

1

COUT (pF)

2

20

1

RIN (Ohm)

500

1000

1

CIN (pF)

2

20

0.1

LFB (nH)

1

10

0.1

CCC (pF)

1

20

0.1

RS (Ohm)

5

50

1

CS (pF)

1

20

0.1

RS2 (Ohm)

5

50

1

Figure 51. Goals and optimization

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Inventions of Monolithic Microwave Integrated Circuits

Oscillator Design: Cross-Coupled LC Oscillator A fully differential cross-coupled LC oscillator is used as the topology in this research. The schematic used is shown in Figure 52. Firstly, the Lp and Cp values for the tank circuit are determined. For the oscillator to oscillate at frequency 3.35 GHz, with inductance Lp = 2.26nH available in SILCMOS018 library, the value of capacitance Cp is f =

1 2π LpCp

3.35GHz =

1 2π 2.26nH ×Cp

(25)

C = 0.536pF Secondly, a reasonable current value is chosen, Io to calculate the width of transistors and resistance Rp. In this work, Io is chosen as 2 mA. The NMOS in SILCMOS018 library has the parameter as shown in Table 2. Figure 52. Cross-coupled oscillator with NMOS current source

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Inventions of Monolithic Microwave Integrated Circuits

Table 2. Model parameters Parameter

NMOS

Mobility of Carrier, μ / cm2/Vs

390.3



Gate Oxide Thickness,

tOX / A

36.5

Threshold Voltage, Vtho / V Dielectric Coefficient of Silicon-Dioxide, εOX

0.415

/ F / cm

3.9 × 8.854 × 10−14

Thus, the gate oxide capacitances per unit area for NMOS is C ox ,n =

=

εox tox ,n

3.9 × 80854 × 10−14 F / cm 36.5 × 10−8 cm

(26)

= 9.46 × 10−7 F / cm 2 To flow current of 2mA, the width of the current source transistor is calculated using Equation (27) by assuming that VGS −VTH ≈ 0.1V ID =

1 W µnC ox ,n (VGS −VTH )2 2 L

(27)

2I o L1 µnC ox ,n (VGS −VTH )2

(28)

∴ W1 =

=

2 × 2m × 0.18um 390.3cm / VS × 9.46 × 10−7 F / cm 2 × 0.12 2

= 195 μm Thus for M2 and M3 to flow Io/2, W2 = W3 =

284

2 × Io / 2 × L2,3 µnC ox ,n (VGS −VTH )2

(29)

Inventions of Monolithic Microwave Integrated Circuits

1 = W1 2 = 97.5 μm Amplitude of output is equal to IoRp, so in order to get 200 mV amplitude, i.e. 400 mVp-p of output swing, Rp =

200mV 2mA

(30)

= 100Ω The same calculation steps are repeated to get the RLC values and transistors width of 3.85 GHz oscillator and 4.35 GHz oscillator. The summary is shown in Table 3.

Control Signal Since the drain and source of the switch is biased at 0.6 V, we can use a voltage of 0.5 V to turn off the switch and 1.8 V to turn on the switch. Vs = 0.6V andVTH ≈ 0.5V , If VG = 0.5V , ∴ VGS = −0.1V (< VTH) → switch “off”If VG = 1.8V , ∴ VGS = 1.3V (>VTH) → switch “on” VD = VS = 0.6V , ∴ VDS ≈ 0V ( < VGS −VTH ) → Triode region Hence the switch is always operating in triode region when it is turned on. With the DC biasing at the drain and source of the switch, we can control the switch easily regardless of the input signal. Figure 54 shows the voltage pulses that are supplied to control the switches (see Figure 53) in order to realize a variable signal generator.

Table 3. Physical design parameters for LO1, LO2 and LO3 W1 (μm)

W2, W3 (μm)

Lp (nH)

Cp (pF)

Rp (Ω)

LO1

195

97.5

4.21

0.536

100

LO2

195

97.5

2.26

0.756

100

LO3

195

97.5

2.26

0.592

100

285

Inventions of Monolithic Microwave Integrated Circuits

Figure 53. Block diagram of full variable signal generator

Figure 54. Control voltage pulses

Biasing Circuit A diode connected NMOS as the biasing circuit is employed to provide the DC biasing voltage to the switch. The biasing circuit is shown in Figure 55. In this work, DC biasing voltage of 0.6 V is needed to bias the switch. With a power supply of 1.8 V,

286

Inventions of Monolithic Microwave Integrated Circuits

Figure 55. Biasing circuit

Rbias 1 =

VDD −VD ID

(31)

Since no current is flow at gate, there is no voltage drop across Rbias2. Hence VG = VD = Vbias = 0.6V . Rbias2 is chosen as 2.5 kΩ. If the (W/L) ratio of the NMOS to be (20μm/0.36μm), thus ID =

1 W µnCOX ,n (VGS −VTH )2 2 L

(32)

Where µn = 0.039 m 2 V , C ox ,n = 9.4562 × 10−3 F m 2 , VTH ≈ 0.5V ∴ ID =

 20µm  1  × (0.6V − 0.1V )2 = 0.1mA × (0.039m 2 / V ) × (9.456 × 10−3 F / m 2 ) ×   2  0.18µm 

Thus from Equation (31): Rbias1 =

1.8V − 0.6V = 12kΩ 0.1mA

Output Buffer If the output of variable signal generator directly connected to the port, the 50 Ω characteristic impedance of the port will load the variable signal generator. In order to avoid this loading effect, an output buffer is put after the variable signal generator output to isolate the impedance. In this work, a source follower is used as the buffer. Source follower exhibits high input impedance and a moderate output impedance and hence it is suitable to be used as buffer. Figure 56 shows the circuit of source follower with the design parameter. The source follower is operated at power supply of 1.8 V and DC biasing of 1.4 V. A source follower has gain approximately to one. It senses the signal at the gate and drives the load at the source, allowing the source potential to follow the gate voltage.

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Inventions of Monolithic Microwave Integrated Circuits

SIMULATION RESULTS This section discusses core circuit, LNA, MPA, broadband amplifier, I/Q demodulator and VCS simulation results.

Core Circuit The core circuit is simulated using ADS simulator (Agilent Technologies, 2005). The performance of core circuit is compared as shown in Figure 57. The S(1,1), S(1,2), S(2,1) and S(2,2) are result when parasitic aware approach is used in schematic level simulation. The layout information is added to circuit by adding transmission line model between transistor source and capacitor. The model is customized model for the core circuit design. The S(5,5) S(5,6), S(6,5) and S(6,6) are schematic simulation results. From Figure 57, it can be concluded that parasitic information does affect the input and output reflection coefficient of the core circuit. The input impedance and output impedance of the core circuit is important information for MPA and LNA design. All circuits use active and passive models from the foundry with transistor; number of finger (NOF) = 10, unit gate width (UGW) = 100 µm, CF = 8 pF, Cs = 20 pF, RF = 500 Ω and Rs = 10 Ω. The calculated S21 and S11 are 10.9 dB and -1 dB respectively. Whereas the simulated S21 and S11 are 11.8 dB and -1.5 dB respectively, this shows that the analysis quite accurate in predicting high frequency characteristics.

LNA Figure 58 shows the mu_load and mu_source parameters which indicate stability of the LNA core circuit. From Figure 58, it is obvious that the stability network of CD and RD is required to ensure unconditional stable for core circuit for frequency from 1 GHz to 10 GHz. Transistor width gate width of 100 μm and 4 fingers are used in the LNA core circuit as discussed in previous section. Table 4 shows the simulation results and components value for 2.4 GHz LNA. Figure 56. Source follower

288

Inventions of Monolithic Microwave Integrated Circuits

Figure 57.Comparison between parasitic aware approach simulation and circuit simulation results

Figure 58. Mu_load and Mu_source vs. frequency

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Inventions of Monolithic Microwave Integrated Circuits

Table 4. 2. 4 GHz LNA simulation results and components value Parameter Gain(dB)

Schematic

Parasitic-Aware

22.34

14.30

NF (dB)

1.5

1.8

Input P1dB(dBm)

-18

-16

S11(dB)

-11.53

-10.53

S22(dB)

-8

-9

VDD(V)

3

3

ID (mA)

18

18

RF(Ω)

1500

1500

CF (pF)

8

8

RS (Ω)

50

50

CS (pF)

33

33

CD (pF)

10

10

RD (Ω)

520

520

RG (Ω)

5000

5000

CG (pF)

10

10

LS (nH)

0.3

0.3

CO (pF)

0.6

0.6

LD (nH)

6.7

6.7

LG (nH)

5.2

5.2

Note: Italic words are core-circuit components

Table 5 shows the simulation results and components value for 3.5 GHz LNA. Obviously from Table 4 and 5, schematic simulation with parasitic-aware approach has significant differences compared with schematic simulation result. This has shown that the parasitic aware approach in simulation is very crucial.

MPA The core circuit was employed in the single-ended MPA device for both 2.4 GHz and 3.5 GHz frequency operation. The supply voltage, VDD for this simulation is 3 V. Table 6 shows the simulation results and components value for 2.4 GHz MPA. Table 7 shows the simulation results and components value for 3.5 GHz MPA. Again, as expected, for the MPA simulation results (Table 6 and 7), the parasitic aware does show significant effect to the schematic simulation.

Broadband Amplifier Table 8 is reproduced from Table 1 shows the design variables which will be optimized to achieve the required specifications.

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Inventions of Monolithic Microwave Integrated Circuits

Table 5. 3. 5 GHz LNA simulation results and components value Parameter

Schematic

Parasitic-Aware

Gain(dB)

16.01

10.2

NF (dB)

1.7

1.9

Input P1dB(dBm)

-19

-18

S11(dB)

-9

-8.5

S22(dB)

-7

-6.6

VDD(V)

3

3

ID (mA)

18

18

RF(Ω)

1500

1500

CF (pF)

8

8

RS (Ω)

50

50

CS (pF)

33

33

CD (pF)

10

10

RD (Ω)

520

520

RG (Ω)

5000

5000

CG (pF)

10

10

LS (nH)

0.3

0.3

CO (pF)

0.3

0.3

LD (nH)

5.3

5.3

LG (nH)

2.2

2.2

Note: Italic words are core-circuit components

Table 6. 2.4 GHz MPA simulation results and components value Parameter

Schematic

Parasitic-Aware

Gain(dB)

10.9

10

PAE(%)

20.1

18

Output P1dB(dBm)

17

19

S11(dB)

-6

-7

S22(dB)

-5.6

-6

ID (mA)

79

79

LG (nH)

2.16

2.16

LS (nH)

0.3

0.3

LD (nH)

4.1

4.1

CC (pF)

7.7

7.7

LO (nH)

2.43

2.43

CO (pF)

1.4

1.4

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Inventions of Monolithic Microwave Integrated Circuits

Table 7. 3.5 GHz MPA Simulation Results and Components Value Parameter

Schematic

Parasitic-Aware

Gain(dB)

11.4

9.4

PAE(%)

26.5

23.5

Output P1dB(dBm)

18

19

S11(dB)

-18

-15

S22(dB)

-10

-9

ID (mA)

79

79

LG (nH)

2.16

2.16

LS (nH)

0.3

0.3

LD (nH)

5.3

5.3

CC (pF)

4.2

4.2

LO (nH)

1.65

1.65

CO (pF)

1.0

1.0

Table 8. Synthesis Setup of Design Variables Design Variables

From

To

Step

RFB (Ohm)

10

550

1

Finger

2

10

1

CFB (pF)

4

7

0.1

ROUT (Ohm)

100

300

1

COUT (pF)

2

20

1

RIN (Ohm)

500

1000

1

CIN (pF)

2

20

0.1

LFB (nH)

1

10

0.1

CCC (pF)

1

20

0.1

RS (Ohm)

5

50

1

CS (pF)

1

20

0.1

RS2 (Ohm)

5

50

1

Table 9 shows the optimized design variable. The current consumption for non-power-constrained is 60 mA. VDD is set at 1.5 V, VGG is 0 V. The broadband amplifier is unconditionally stable; this is shown in Figure 59. The mu_load and mu_source is more than 1. Table 10 summarizes most of broadband amplifier works. Amplifiers are often compared using figure of merit (FOM), the better the FOM the better is the design. Works (Cherkashin et al, 2005, Janssens at al., 1997, Marzuki et al., 2004, Ismail & Abidi, 2004, Wang &Wang, 2006) do not use any simulation based optimization and non power constrained design. These works are more on to meet the bandwidth requirement. Work (Jajoo et al., 2006, Bevilacqua & Niknejad, 2004) uses current as one of the constraints for the broadband amplifier design, but there are no reports on the performance of these work on non power constrained.

292

Inventions of Monolithic Microwave Integrated Circuits

Table 9. 1Optimized Design Variables of Power Constrained and 2Non Power- Constrained Design Variables

Constrained1

No Constrained2

RFB (Ohm)

542

514

Finger

3

3

CFB (pF)

6.4

6.2

ROUT (Ohm)

135

106

COUT (pF)

2

2

RIN (Ohm)

707

785

CIN (pF)

10.4

10.3

LFB (nH)

7.4

6.8

CCC (pF)

18

18.3

RS (Ohm)

23

14

CS (pF)

19.6

19.6

RS2 (Ohm)

28

26

Table 10. Broadband Amplifiers, *Non Power-Constrained Work

S21(dB)

BW(GHz)

NF(dB)

Power (mW)

FOM

Technology

Jajoo et al., 2006

17.2

2.9

2.8

16.5

1.406

0.35μm SiGe BiCMOS

Cherkashin et al, 2005

12

13

2.15

90

0.898

0.2μm PHEMT

Janssens at al., 1997

24

0.76

3

35

0.3458

0.4μm CMOS

Marzuki et al., 2004

13

2

2.4

30

0.403

0.35μm SiGe BiCMOS

Bevilacqua and Niknejad, 2004

9.3

5.9

7

9

0.478

0.18μm CMOS

Ismail and Abidi, 2004

21

8

4.4

30

1.706

0.18μm SiGe BiCMOS

Wang and Wang, 2006

12

9

6

17

0.707

90nm CMOS

This work (simulated)

19.8

12.5

2.5

73.5

2.153

0.15μm PHEMT

This work* (simulated)

19.8

12.5

2.5

90.5

1.753

0.15μm PHEMT

This work has shown that power-constrained technique is capable to improve the performance, this can be seen from the FOM of power-constrained is 0.4 better than non power constrained. Figure 60 shows S21 of the amplifier, 3-dB bandwidth is 12.5 GHz. Figure 61 shows noise figure vs. frequency. Maximum noise figure is 2.5 dB. Monte-Carlo analysis is done for Noise Figure and S21. The analysis is done with standard deviation of 2 for RS, RS2, RFB and RFB2. The results are shown in Figure 61 and 62. Both analysis results show that the parameters are still within the specification.

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Inventions of Monolithic Microwave Integrated Circuits

Figure 59. Mu_load and Mu_source of the amplifier

Figure 60. S21 vs frequency

Variable Signal Generator(VSG) Cadence Spectre is used to determine the performance specifications of the variable signal generator designed in 0.18 μm Silterra high performance CMOS process. Spectre is a fast and highly accurate analog simulator provided by Cadence. Table 11 shows the details control signal input sources used in the simulations.

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Inventions of Monolithic Microwave Integrated Circuits

Figure 61. Noise figure Monte-Carlo analysis

Figure 62. S21 Monte-Carlo analysis

Simulation Result of Series-Shunt NMOS Switch Figure 63 and 64 shows the simulation result of series-shunt NMOS switch with biasing voltage of 0.6V at the drain and source of transistors. Figure 63 is the result with large gate length while Figure 64 is the result with the minimum gate length. Both have the same transistor width of 50 μm for main switch and 25 μm for shunt switch. An ideal sine wave with 400 mVp-p amplitude is used as the input.

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Inventions of Monolithic Microwave Integrated Circuits

Figure 63. Transient response of series-shunt NMOS switch with L = 1 μm

Figure 64. Transient response of series-shunt NMOS switch with L = 0.18 μm

It is clear to see from Figure 64 that the series-shunt NMOS switch is able to eliminate the charge injection problem. The switch is almost totally turned off and only has a negligible small swing at the 0.6 V offset voltage. Width/Length (W/L) ratio of the transistor is important to determine the performance of a switch, but it requires a number of trade-offs. This means that reducing the gate length L or increasing the width will reduce the on-resistance. Besides, parasitic capacitance is proportional to both W and L. Thus the W and L of the transistor need to be adjusted up to the acceptable parasitic capacitance and on-resistance. Transition spike of the switch is mainly caused by parasitic capacitance. So the size of transistors has to be optimized to get rid of the transition spike. However at the same time, it is necessary to make the

296

Inventions of Monolithic Microwave Integrated Circuits

Figure 65. Transient response

drop across the switch as low as possible to prevent signal loss. Hence the size of transistors also needs to be optimized to have low on-resistance. Since it is clear that reducing the gate length L will then reduce both parasitic capacitance and onresistance, the smallest allowable gate length of the technology library as the switch transistor length in this work, which is 0.18 μm is used. As for the transistor width, W, it has to be adjusted so that the transition spike is small and the drop across the switch is low.

Simulation Result of Cross-Coupled LC Oscillators The first order calculation in theory section cannot give accurate result as expected. So W, Cp, Rp and Lp have to be optimized to obtain target oscillating frequency and amplitude. Figure 65, 66 and 67 shows the simulation result of the first oscillator, LO1 with frequency 3.35 GHz. The transient response of the switch in Figure 65 shows that the oscillator needs some time to reach the steady state. After around 10 ns to 20 ns then only the oscillator oscillates with constant amplitude. Figure 66 and Figure 67 show the result of periodic steady state response. By using the PSS simulation, the frequency and amplitude of the oscillator can be clearly observed. Table 12 summarizes the parameters before and after optimized, the oscillating frequency and the amplitude of all three oscillators. Table 13 shows the performance of local oscillators. The simulation results had proved that the concept in theory section is correct although the calculation is not very accurate. The amplitude of the oscillating signal depends only on current Io and resistance Rp. Thus after the width of the transistors is adjusted to flow a fix current, the value of Rp is optimized to get the desired amplitude. The value of Rp for all three oscillators are similar proves that amplitude does not depend on Cp and Lp at the fix current. While the oscillating frequency of the oscillators depends on Lp and Cp. The value of Rp only gives slightly influence on it.

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Inventions of Monolithic Microwave Integrated Circuits

Simulation Result of Variable Signal Generator Integration of Single Oscillator and Switch A single oscillator and switch are integrated to determine the effect of the switch on oscillator. Figure 68 shows the result of LO1 connected to series-shunt switch. It is found that when the series-shunt switch is turned on and off, the transition is not as smooth. Observe the signal from oscillator, which is directly connected to the switch input as shown in Figure 68, it is found that the amplitude is different when the switch is on or off. The switch input impedance is different for on state and off state. So the effect on the RLC tank circuit is also different, and hence resulting a difference of the amplitude. An unstable input will definitely provide a not smooth output.

Figure 66. Fundamental frequency

Figure 67. Magnitude and frequency of LO1

298

Inventions of Monolithic Microwave Integrated Circuits

In addition, the signal amplitude is degraded across the switch. It is mainly due to the switch acts as a resistor with a value equal to its on resistance when it is turned on. Thus it causes some loss when the signal passes through it. In order to obtain a smooth transition, the differential series-shunt topology is used. The modified switch had improved the switch performance during transition period as shown in Figure 70 and 71. In fact, the effect on the RLC tank circuit is approximately the same and hence the amplitude of the output signal from oscillator is almost constant regardless the state of the switch.

Table 11. Properties of control signal input sources Pulse generator for main switch 1, Vpulse1

V1= 0.5V, V2 =1.8V; Pulse width = 4ns Period = 12ns

_____ Pulse generator for shunt switch 1, Vpulse1

V1 = 0.5V, V2 = 1.8V Delay = 4ns; Pulse width = 8ns Period = 12ns

Pulse generator for main switch 2, Vpulse2

V1= 0.5V, V2 =1.8V; Delay = 4 ns; Pulse width = 4ns Period = 12ns

_____ Pulse generator for shunt switch 2, Vpulse2

V1 = 0.5V, V2 = 1.8V Delay = 8ns; Pulse width = 8ns Period = 12ns

Pulse generator for main switch 3, Vpulse3

V1= 0.5V, V2 =1.8V; Delay = 8 ns; Pulse width = 4ns Period = 12ns

_____ Pulse generator for shunt switch 3, Vpulse3

V1 = 0.5V, V2 = 1.8V Delay = 12ns; Pulse width = 8ns Period = 12ns

Table 12. Calculated and optimized physical design parameters of local oscillators W1 (μm)

W2, W3 (μm)

Lp (nH)

Cp (pF)

Rp (Ω)

Cal.

Opt.

Cal.

Opt.

Cal.

Opt.

Cal.

Opt.

Cal.

Opt.

LO1

195

354

97.5

177

4.21

2.26

0.536

0.300

100

136

LO2

195

354

97.5

177

2.26

1.65

0.756

0.355

100

139

LO3

195

354

97.5

177

2.26

1.65

0.592

0.152

100

133

Table 13. Performance of local oscillators Oscillating Frequency,

fosc

(GHz)

Amplitude, (mV)

LO1

3.35

201.79

LO2

3.85

200.043

LO3

4.35

200.302

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Inventions of Monolithic Microwave Integrated Circuits

Figure 68. Transient response of LO1 connected to switch

Figure 69. Transient response of output signal from oscillator

Although increase the transistor width will lower the on resistance and then reduce the signal loss, large width must be avoided so that the parasitic capacitance is small. Thus, the Rp, Cp and W in the oscillator are tuned again to get the target amplitude and frequency, with the switch in on state as the load. The switch transistor width is also optimized to get the balance between on-resistance and parasitic capacitance. Table 14 shows the optimized parameters of all the oscillators and switches after the integration. Since the integration brings effect mostly on amplitude, only the value of Rp is tuned a lot as compared to Table 12. Figure 72 and Figure 73 shows the transient and periodic steady state response of the first oscillator and switch. It has proved that the integration of oscillator and switch manage to produce the target frequency and amplitude when the switch is turned on and no signal is generated at all when the switch is turned off.

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Inventions of Monolithic Microwave Integrated Circuits

Figure 70. Smooth transition of transient response

Figure 71. Constant amplitude of oscillator’s output signal, with modified differential series-shunt switch

Table 14. Optimized design parameters after integration of oscillator and switch Switch

Local Oscillator

WM1,WM3 (μm)

WM2 (μm)

W1 (μm)

W2,W3 (μm)

Lp (nH)

Rp (Ω)

Cp (pF)

1st

10

5

352

176

2.26

192

0.392

2nd

10

5

352

176

1.65

197

0.351

3

10

5

352

176

1.65

185

0.150

rd

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Inventions of Monolithic Microwave Integrated Circuits

Integration of Three Signal Generators In order to form the full variable signal generator, all three oscillators and switches are integrated together with the output buffer, and apply the control signal as discussed in Table 11. Now every switch output is connected to another two switches, hence causing loading effect and the load connected to the oscillator is not balance when the switch is on and off. However since the unbalance loading effect is not significant in this case, and the spike at the transition period is negligible, all the switch transistors at remain same size with individual signal generator. The capacitance Cp is tuned slightly as well so that the signal is swing at the targeted frequency. The value of Rp in oscillators is tuned and the final result is shown in Figure 74. In this case, a discrete Fourier transform is used to check the frequency and amplitude of the signal generated. Figure 72. Transient response of first signal generator

Figure 73. Frequency and amplitude of the first signal generated

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Inventions of Monolithic Microwave Integrated Circuits

Figure 75 shows the closer look of the signal generated. It can be clearly seen that the signal generated is sinusoidal waveform without clipping and the frequency is different for every 4 ns. The amplitude of the signal swing is stable and the transition is considered smooth. Figure 76, Figure 77 and Figure 78 show the Fourier transform spectrum frequency of all three different frequencies generated by variable signal generator (multiband VCOs). From the three spectrum frequencies, it can be concluded that the frequencies of the signal generated are 3.32GHz, 3.82GHz and 4.33GHz respectively. The amplitude of the signal is approximately 200 mV. Table 15 shows the final design parameters of the variable signal generator designed in this research. The performance of the variable signal generator designed in this research is summarized in Table 16. Figure 74. Signal generated from VSG

Figure 75. Closer look of signal generated

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Inventions of Monolithic Microwave Integrated Circuits

Figure 76. Spectrum frequency of first frequency generated

Figure 77. Spectrum frequency of second frequency generated

EXPERIMENTAL RESULTS Core Circuit Figure 79 shows photo of fabricated core circuit. PHEMT transistor with a gate width of 100 µm and 10 fingers is used.

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Inventions of Monolithic Microwave Integrated Circuits

Figure 78. Spectrum frequency of third frequency generated

Table 15. Final design parameters of VSG Switch

Local Oscillator

WM1,WM3 (μm)

WM2 (μm)

W1 (μm)

W2,W3 (μm)

Lp (nH)

Rp (Ω)

Cp (pF)

1st

10

5

352

176

2.26

200

0.392

2

10

5

352

176

1.65

209

0.335

10

5

352

176

1.65

200

0.120

nd

3

rd

Note: the value of bypass capacitor = 0.05 pF, Bias resistors for shunt transistor = 1 kΩ

Table 16. Performance summary of VSG Center Frequency

Amplitude

Specification

Simulation

Specification

Simulation

1

st

3.35 GHz

3.32 GHz

200mV

203.289mV

2nd

3.85 GHz

3.82 GHz

200mV

198.104mV

3

4.35 GHz

4.33 GHz

200mV

198.679mV

rd

This microphotograph completed with a launch pad was fabricated in Taiwan using 0.15 μm GaAs PHEMT process technology. All the passive components used were integrated on-chip. This process uses a backside via-ground method, which eliminates the need for wire bonding to the ground. In the S-Parameter results (Figure 80), the orders of the charts are S11 and S22 in term of Unit Smith Chart while S21 and S12 in the Magnitude (dB). The S-parameter measurement is performed in the frequency ranges from 2 GHz to 8 GHz and the bias conditions is 2.5 V of drain voltage, VDS and a gate voltage, VGS is 0 V. The drain current, ID is 83 mA.

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Inventions of Monolithic Microwave Integrated Circuits

Figure 79. Core circuit microphotograph

Figure 80. Simulation and measurement results of core circuit

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It can be seen from Figure 80, the schematic level simulation results with parasitic aware approach (S(1,1), S(2,1), S(1,2) and S(2,2)) is almost similar with the measurement results (S(3,3), S(4,3), S(3,4) and S(4,4). At 2.4 GHz, the core circuit simulation achieved small-signal gain (S(2,1)) of 12.55 dB whereas the measured small-signal gain (S(4,3)) is 12.07 dB. Overall, core circuit measurement result almost matches with the parasitic aware approach. This has shown the approach can reduce the design cycle and consequently the accuracy of the simulation.

LNA A fully integrated 2.4 GHz LNA with spiral inductor has been designed and fabricated. As shown in Figure 81, the LNA employ round inductors for matching components and MIM capacitor, round inductor for output matching. The 3.5 GHz LNA used square inductor instead of round as input matching component. This can be seen in Figure 82. Figure 83 shows the measured s-parameters of the 2.4 GHz LNA. The S11 is lower than -10 dB from 2.3 GHz to 3.5 GHz. The measured gain (S21) is 14.3 dB at 2.4 GHz. The isolation (S12) is -35 dB at 2.4 GHz. The LNA is biased with VDD = 3V and it consumes 18 mA. Figure 84 shows the measured s-parameters of the 3.5 GHz LNA. The S11 is lower than -10 dB from 2.3 GHz to 3.5 GHz. The measured gain (S21) is 10.6 dB at 3.5 GHz. The isolation (S12) is -39 dB at 3.5 GHz. The LNA is biased with VDD = 3V and it consumes 18 mA. Overall, S21 of 2.4 GHz and 3.5 GHz LNA is almost similar to simulation result (parasitic aware approach). Thus, the core-base approach has proved that it can be used in designing multiband LNA. Figure 81. Die photo of the 2.4 GHz LNA

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Figure 82. Die photo of the 3.5 GHz LNA

Figure 83. S-parameters of LNA of 2.4 GHz LNA

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Figure 84. S-parameters of LNA of 3.5 GHz LNA

MPA A fully integrated 2.4 GHz MPA with spiral inductor has been designed and fabricated. As shown in Figure 85, the MPA employ square inductors for input matching components and MIM capacitor, square inductor for output matching. The 3.5 GHz MPA (Figure 86) used round inductor as one of output matching components. Figure 87 shows the measured s-parameters of the 2.4 GHz MPA. The S11 is lower than -10 dB from 2.4 GHz to 5.5 GHz. The measured gain (S21) is 10.0 dB at 2.4 GHz. The isolation (S12) is -18 dB at 2.4 GHz. The MPA is biased with VGG = 0 V and VDD = 3V and it consumes 83 mA. Figure 88 shows the measured s-parameters of the 3.5 GHz MPA. The S11 is lower than -10 dB from 2.8 GHz to 5.5 GHz. The measured gain (S21) is 9.0 dB at 3.5 GHz. The isolation (S12) is -16 dB at 3.5 GHz. The MPA is biased with VGG = 0 V and VDD = 3V and it consumes 83 mA. The S21 of both MPAs is almost similar to parasitic aware approach schematic simulation result. This has proved some merit in using core based design approach in designing multiband MPA.

CIRCUIT TECHNIQUES: PATENTS STUDY The inventions discussed in this chapter are some of the solutions for IC of 4-G technology. However, the inventions concept can also be applied to technology other than communication technology. This chapter will discuss VCO with integrated transformer, VCO with insensitive frequency operation to power supply variation and VCO with low common mode noise in VCO topic. In Mixer topic, Mixer with high conversion gain, Mixer with noise reduction technique and High Linearity Mixer will be discussed. An LNA with plurality of gain steps, LNA with variable frequency operation-gain and LNA with Cd for

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Figure 85. Die photo of the 2.4 GHz MPA

Figure 86. Die photo of the 3.5 GHz MPA

PCSNIM are discussed in one of the topics in this chapter. Power Amplifier with enhanced efficiency and Power Amplifier with amplifying unit will be discussed in next topic. Topic of T/R switch will discuss the conventional approach of T/R switch and negative voltage generator circuit. It is therefore, the objective of this chapter is to address the current state of the art of inventions for reader to apprehend and appreciate the problems and solution that has been found. Figure 89 shows block diagram of LNA, PA, Mixer and T/R switch in a typical RF and microwave Front end. Band pass filter is normally employed to eliminate out of band signal.

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Figure 87. S-parameters of 2.4 GHz MPA

Figure 88. S-parameters of 3.5 GHz MPA

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Figure 89. Block diagram of a typical RF-front end

VOLTAGE CONTROLLED OSCILLATOR Differential Voltage Controlled Oscillator (VCO) with Integrated Transformer Differential VCO is an oscillator with differential output signal which its frequency can be varied. An example of a conventional differential VCO circuit is shown in Figure 90. The VCO has a negative resistance circuit, transistors M1 and M2 act as buffers to pass the signal from LC tank to other circuit. These transistors consume current. RB is used to set DC current for buffers. Coupling capacitor is employed to isolate DC while allow signal to pass through. A new type of differential type VCO is shown in Figure 91 (Park, Hong & Seo, 2003). The VCO has a negative resistance circuit and couple of LC tanks. At each LC tank, a transformer is connected to form a buffer. The transformer utilizes inductor, L as a primary inductor. This approach will reduce the overall power consumption. Capacitor (by pass capacitor) can be connected to the secondary coil of the transformer to form a band pass filter, thereby attenuating a harmonic signal included in the output signal. If the capacitors used in the VCO are varactors, voltage control, VC can be applied to change its capacitance.

VCO with Insensitive Frequency of Operation to Power Supply Variation The controlling circuit element of a voltage controlled oscillator (VCO) for use in a phase lock loop (PLL) is a varactor, example of the circuit is shown in Figure 92. Here, L, C and capacitance of varactor determine the frequency of the VCO. Rb is used to bias or control (Vtune) the varactors, it uses to isolate ac ground (Vtune) from the resonator. Here, one may change the capacitance by bias positive terminal more negative than negative terminal. This is accomplished through Vtune. Vtune is normally output of voltage of loop filter of PLL. Example of a loop filter is depicted in Figure 93. Tuning voltage, Vtune as mentioned earlier is normally negative in order to change the capacitance of the varactors. Negative voltage requires complex circuit design, thus there is a need to find a way to use

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Figure 90. Conventional VCO circuit with transistors as buffers

Figure 91. VCO with transformers

only positive voltage. Figure 94 shows remedy of to have positive Vtune. The cathode of varactors is connected to VDD, but this has problem with power supply variation, so to avoid this problem, the ground of loop filter must be connected to VDD as well. As a result, a variation of VDD will also appear at the anodes of the varactors (Jones, 2004).

VCO with Low Common Mode Noise External noise from tuning voltage and negative resistance circuit or active circuits can degrade the performance of VCO. An implementation of blocking capacitor (Cb) to reduce common mode noise and differential tuning voltage is described in Figure 95. This approach has some problems, even though the design is differential (differential approach supposedly can suppress noise), but the approach only reduces

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Figure 92. VCO with conventional Varactor tuning method

Figure 93. Loop filter

the VCO sensitivity, Kvco. The circuit still susceptible to common mode noise due negative terminal of varactors is exposed to common noise from tuning voltage (Vtunen). To elevate the problem, two pairs of varactors are used, this is shown in Figure 96. The two varactors, V1 and V2 are parallel with each other in differential operation. The common mode noise such as thermal noise of resistors and digital noises are cancelled due to the effect of ‘equal and opposite’ signal (Talwalkar, 2006). Similar action happens with V3 and V4. The two capacitors, Cb serve to block noise originating from negative resistance circuit at low frequency from affecting the varactors.

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Figure 94. VCO using positive Vtune

Figure 95. VCO using differential Vtune

MIXER Mixer with High Conversion Gain Let’s take a look at prior art Gilbert Mixer circuit as shown in Figure 97. The main drawback of the circuit is it cannot operate at low voltage. Current source transistor, M1 is operating in the saturation region, to obtain higher transconductance. The minimum drain voltage, VD1 is therefore equal to VGS1-VT. The differential pair M2 and M3 must have its drain voltage > 2(VGS1-VT). If voltage drop across load resistor, VL, then these three stacks of voltages, VD1, VD2 and VL dictate the minimum power supply. To improve the voltage operation, M2 and M1 can be operated as transmission gate (Chien, 2002). The DC drain source voltage, VD2 is equal to the voltage drop across the resistance, Ron or M2 or M3. By ensuring, VD1= VG1-VT, 315

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Figure 96. VCO using differential Vtune (improved CM noise rejection)

Figure 97. Mixer

DC current of M1, ID =

K  2 (VGS −VT )VDS −VDS 2  2 

(33)

Where K is transconductance parameter. VT is threshold voltage. Slope is ∆I D = K (VGS −VT −VDS ) ∆VDS If we let RF signal = Vrf sin (ωrf t ) and LO signal = Vlo sin (ωlot ) And due to source follower action, ∆VDS = Vlo sin (ωlot )

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(34)

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So ∆I D = K VGS +VRF sin (ωrf t ) −VT −VDS  ×Vlo sin (ωlot ) =   KVlo sin (ωlot ) ×Vrf sin (ωrf t ) + K (VGS −VT −VDS ) ×Vlo sin(ωlot ) The first term on the right side of equation above, yields a beat frequency Vif, Vif =

KVloVrf  cos (ωrf − ωlo ) t    2

The sum frequency term in above equation can be filtered out in the IF amplifier and K (VGS −VT −VDS ) =0. This circuit has 21/2 times the conversion gain of the conventional Gilbert mixer gate (Chien, 2002).

Mixer with Noise Reduction Technique Figure 98 shows a another conventional mixer circuit other than as shown in Figure 97 for combining a differential signal (Vin1-Vin2) and RF signal. M3 is used as biasing transistor for the circuit. M1 and M2 form gain stage for the mixer circuit. Output signal of the mixer circuit is taken at the drains of M1 and M2. RL is used as load of the circuit. The biasing transistor, M3 introduces noise to the mixer circuit, thus limit the capability of the mixer circuit to detect very small signal (eg 10uV). A frequency dependent current shunt circuit (Z(ω)) is added to the conventional circuit (Razavi & Zhang, 2004) between VDD and drain of M3. At low frequency, shunt circuit will shunt a greater portion of the bias current to VDD away from gain stage transistor M1 and M2. More bias current will be provided to M1 and M2 at the frequencies of interest. This allows the circuit to achieve high gain without noise penalty associated with high bias current. This concept is described in Figure 99. An example of the shunt circuit is shown in Figure 100. The shunt circuit employs inductor and resistor, parasitic components of capacitor and resistor are usually associated with integrated inductor.

High Linearity Mixer So far only, low noise mixers and high conversion gain mixer are discussed in this topic. Linearity is important performance for a receiver. Downconverter mixer predominantly determines the linearity, therefore it is important to design high linearity mixer. By swapping RF signal and LO signal inputs as shown in Figure 97, high linearity mixer can be achieved (Komurosaki, Sato & Ueda, 2003). This is due by ensuring M1 is biased at triode region. This is achieved by setting VG2-VGS1
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Figure 98. Another conventional mixer

Figure 99. Low noise mixer

Figure 100. Shunt circuit

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LOW NOISE AMPLIFIER (LNA) LNA with Plurality of Gain Steps Gain variation of RF-Front end is important to improve the receiver performance. Figure 101 shows an example of conventional variable gain amplifier. Transistor M1 and M2 are configured as cascode configuration. The frequency operation of the circuit is determined by inductor, L and capacitor, C. Resistors, R1 and R2 determine the variation of the gain. The selection of gain is done through switches, S1 and S2. The main disadvantage of the circuit is drifted frequency operation. This could happen if R1 and R2 are transistors in triode region. The total capacitance of the circuit is changed each time a transistor resistor is turned ON and OFF. To overcome the effect of frequency operating changes when gain is changed, a circuit using current steering method is normally used. An example of the circuit is shown in Figure 102 (Darabi, 2003). Transistor M1 is configured as common source. Transistors M2 and M3 acts as resistors. For maximum gain, both M2 and M3 are ON while for minimum gain, M3 is turned OFF and M4 is ON, there will be less current flow through inductor, L, therefore less output voltage. Signal C and C_ba are used to turn ON and OFF M3 and M4.

LNA with Variable Frequency Operation and Gain In the receiver, multiband and multimode operation is important. Multiband operation can be achieved using wideband amplifier of LNA Figure 103 shows an example wideband LNA. Feedback resistor, R linearizes the bandwidth. The circuit has mediocre noise figure and not suitable for multiband operation, as the undesired noise could not be suppressed through single filtering bandwidth. An example of the circuit which could solve the problem is depicted in Figure 104 (Razavi & Kay, 2006). The low noise amplifier includes a switched loading circuit (L and C) having plurality of loading

Figure 101. Conventional variable gain amplifier

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Figure 102. Variable gain amplifier using current steering method

Figure 103. Wideband LNA

units, each of the loading units determines a center frequency of the amplifier. Switches, SW1, SW2 and SW3 are used to select first band, second band and third band. The switches can also simultaneously turn ON to achieve different or more than 3 bands. Implementation of gain variation in the circuit is shown in Figure 105. Maximum gain is achieved when M3 is OFF, thus i1=i2, we have maximum current. To vary the gain, i2 should be varied. Therefore M3 is configured as variable resistors.

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Figure 104. Multiband LNA

Figure 105. Implementation of gain variation in the multiband LNA

LNA with Cd for Power Constraint Simultaneous Noise Input Matching (PCSNIM) High quality (Q) factor of the input circuit is good to reduce channel noise, but from Equation (35), this leads to large CT or big devices. CT consists of Cgs. Big Cgs is bad for gate induced current noise as shown in Equation (4). To overcome this trade off, external capacitor can be applied between gate and source, Cd. Now CT = Cd + Cgs. Therefore, Cgs of the device can be maintained low, while high Q is achieved (Andreani & Sjoland, 2004). The circuit is shown in Figure 106. Lg is input inductor and LS is source inductor. Both inductors are used as matching components. Lout acts as load for the circuit. With proper current optimization, a very low noise and high power gain low noise amplifier can be simultaneously achieved.

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Q=

1 2RS ωoCT

(35)

Where CT is input capacitance of the circuit. Gate induced current noise, δ (ωC gs )

2

2

i n, g = 4kBT

5gdo

∆f

(36)

POWER AMPLIFIER Power Amplifier with Enhanced Efficiency A power amplifier as shown in Figure 107 has different efficiency with respect to output power. An enhanced efficiency power amplifier using two power amplifiers is shown in Figure 108. Low power amplifier is ON when low output is required, while high power amplifier is ON when high output power is wanted. Both power amplifiers can also simultaneously turn ON when large output power is required. Input impedance matching circuit and output impedance circuit are sometimes implemented for low power amplifier. High pass circuit can be used as input impedance matching circuit while low pass circuit can be used as output impedance matching circuit (Kim, 2004).

Figure 106. PCSNIM

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Power Amplifier with Amplifying Unit It is always a demand to design a power amplifier which can provide continuous output power for constant envelope signals and amplitude-variable signals. Figure 109 shows an example of the circuit. The amplitude adjuster adjusts amplitude of the input signal in response to control signals from controller. The controllers also control or turn ON/OFF each of power amplifier. Figure 110 shows the concept of the invention (limit to N = 2) (Chien, Suzuki & Hirota, 2006). For input signal < P1, only 1st PA is turned ON. Amplitude adjuster ensures the input signal of 0 to Pa is transformed to 0 to P1. When signal between P1 and P2, only 2nd PA is ON, while signal between P2 and P3 will force both power amplifiers to turn ON. By adding a predistort in front of saturation power amplifier, we can have a very linear Pout vs. Pin Power Amplifier. Figure 111 shows examples of power amplifier units. Two methods can be used, control through biasing or switch. Concept in Figure 112 is used to combine all the power. It is a current combiner with output matching that can be varied upon power requirement. Variable output matching is chosen to reduce loss in the combiner. The variable output matching is shown in Figure 113. Reactive components, such as inductors or capacitors can be used as the matching components. Selects block receives signal from controller.

Figure 107. Conventional power amplifier

Figure 108. Enhanced efficiency power amplifier

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Figure 109. Power amplifier with amplifying unit

Figure 110. Concept of the invention (limit to N = 2)

TRANSMIT-RECEIVE (T/R) SWITCH A conventional single pole double throw (SPDT) FET switch is shown in Figure 114 (Bharj & Goyal, 1987). The FETs are arranged in two mirror-image series-series shunt configuration at the common RF input node (antenna). The series FETs provides a through path for the ON ports, while the shunt FETs provide isolation for the OFF ports. Resistors are connected to gate of FETs to provide high impedance at the gate and isolation between control circuits and RF path.

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Figure 111. Examples of power amplifier units

Figure 112. Power combiner

Two stacked FETs are normally employed to increase isolation for the OFF ports. A low cost GaAs technology does normally have depletion devices, i.e. FETs which have negative threshold voltage. It is therefore, there is a need to design negative voltage generator as control circuits for the switch. Figure 115 depicts block diagram level of negative voltage generator (NVG). The NVG consists of multivibrator, driver and charge pump. Multivibrator provides continuous wave (CW) signal of several hundreds megahertz, driver is considered as buffer to provide isolation between charge pump and multivibrator. Charge pump function is to provide charge transfer mechanism. Figure 116 is an example of charge pump circuit. Signal of hundreds megahertz within ground and VDD will charge Cin. Transistor M1 and M2 function is to transfer charge to Cout. M1 and M2 are depletion devices, thus the top plate voltage of Cout will be a voltage to turn ON M1, and this will ensure the charge

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Figure 113. The variable output matching

Figure 114. Conventional T/R switch

is transferred from Cin to Cout. To suppress any ripple in the negative voltage, complimentary operation of charge pump circuit must be employed (Yamamoto, Moriwaki & Fujii. 1999).

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Figure 115. Negative voltage generator block diagram

Figure 116. An example of charge pump circuit

CONCLUSION There are many inventions in MMIC, this chapter could not or would not cover all the inventions. Some inventions on VCO, Mixer, LNA, PA and T/R switch are discussed. These circuits or inventions are discussed due to their importance in RF or microwave transceivers. These circuits are designed with improvement in the performance compared to the old or conventional circuits. Besides low power requirement for portable application, multiband, low noise, high linearity, gain variation and high efficiency are main invention objectives. These performances are required in complex systems of 3G and 4G system. These inventions are useful and can be applied to any process or technology, but it could prove essential for GaAs technology as the process is getting cheaper and the application of wireless appliances or devices are getting bigger. Three circuit techniques for VCO, Mixer and LNA are discussed in this chapter, while two circuit techniques for PA are discussed. One circuit technique is discussed for T/R switch. The circuit techniques are derived from references. These circuits can be used as prior art or basis of further improvement of the invention circuitry. These circuits can also be integrated as RF-Front end as shown in Figure 1 with some modifications. A new design methodology or flow of integrated circuit is presented which has potential in reducing a MMIC or RFIC design cycle, especially iteration 2 (see Figure 3.2). This is proved by the measured Sparameters of core circuit is almost similar to schematic simulation result when parasitic aware approach

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is employed. Power-constrained optimization technique or process in design flow is also discussed. It can be used to optimize the components value of amplifier for optimum performance. The optimization can be done during or after core circuit topology + parasitic aware process (see Figure 3.2). A custom polynomial model of gm and transcoductance of transistor is developed for core circuit analysis and development. A LNA and MPA of 2.5 GHz and 3.5 GHz are designed with PACB approach. The measurement results of devices have shown similarity with simulation results (PACB approach). This has shown a merit of using the approach for designing multiband integrated circuit. Amplifier with performance of 12.5 GHz for 3dB-bandwidth, 73.5 mW of power consumption, Noise Figure of 2.5 dB and power gain of 19.8 dB was designed. Simulation-based optimization technique is used to design the broadband amplifier. For this work, common source with resistor and capacitor feedback from drain to gate was employed for the design. Two amplifiers are arranged in cascade to achieve sufficient power gain. The setting weight = 50 of OptimGoal5 will ensure the optimization is constrained by the current consumption requirement. Further studies of the weight must be done in order to improve the optimization technique. A designed broadband amplifier with power-constrained optimization technique achieved the FOM of 0.4 better than non power-constrained design. In this research, multiband VCOs or variable signal generator, targeting fast switching between three different center frequencies that are suitable for UWB wireless application is presented. The design is done by using Silterra 0.18 μm CMOS technology and the simulation is done by Cadence. The objective of this research is to design a signal generator that is able to generate a 400mVp-p signal with center frequency 3.35 GHz, 3.85 GHz and 4.35 GHz at every 4 ns interval. The signal generated is targeted to have a smooth transient response without transition noise. Active oscillators topology is used to realize the variable signal generator in this project. A switch is developed that is able to pass the signal from oscillators to output without transition spike. The switch was designed such that it would not give unbalance-loading effect to the oscillator’s RLC tank circuit when it is turned on or turned off. The optimization of transistor size was the key point to determine the switch performance. The weakness of a single NMOS switch is investigated then developed a topology that was capable to pass the signal with good transient response. Additionally, three oscillators with targeted center frequency using LC cross-coupled topology are designed. The problems and issues when integration of the oscillators with switches are investigated. A modification of the switch and optimized the design parameters to solve the problems is developed. The designed variable signal generator is capable to produce a signal with three center frequencies, i.e. 3.35 GHz, 3.85 GHz and 4.35 GHz at 400 mV peak-to-peak swing. The frequency is switched in every 4ns with negligible transition noise. In summary, a new approach to provide short signal at different center frequency for UWB applications is presented. The solution is simple and direct to achieve the objective.

ACKNOWLEDGMENT Thanks to Dr. Ahmad Ismat Abdul Rahim, Telekom R&D Sdn. Bhd for the support of the research. Acknowledge the supervision of Prof Ali Yeon Md. Shakaff and Assoc. Prof Zaliman Sauli, the contribution of my student, Khor Teng Teng in switch development and the contribution of Mr. Zulfa Hasan Abrar on LNA and MPA development.

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Marzuki, A., Zulkifli, A. Z. T., Mohd-Noh, N., & Abdul-Aziz, A. Z. (2004). A Broadband RF Feedback Amplifier Design with Simple Feedback Network. 2004 RF and Microwave Conf (pp. 1-4). Massoud, Y. (2006). Automated Design Solutions for Fully Integrated Narrow-Band Low Noise Amplifiers. 6th International Workshop System on Chip for Real Time app. (pp. 109-114). Massoud, Y. (2007). Modeling and Design Automation for on-chip Analog and RF Circuits. Retrieved from http://rand.rice.edu/mixedsig.htm Meng, C. H., & Wu, T. H. (2008). A 5 GHz RFIC Single Chip Solution in GaInP/GaAs HBT Technology. Microwave Journal, 51(2), 132. Nguyen, T. K., Kim, C. H., Ihm, G. J., Yang, M. S., & Lee, S. G. (2004). CMOS Low Noise Amplifier Design Optimization Techniques. IEEE Transactions on Microwave Theory and Techniques, 52(5), 1433–1441. doi:10.1109/TMTT.2004.827014 Park, S.-H., Hong, S.-C., & Seo, Y.-G. (2003). Differential type voltage controlled oscillator. United States Patent, Pat. No. US 6,621,363 B2 Platzker, A., & Bouthillete. (1995). Variable Output, High-Efficiency Low Distortion S-band PowerAmplifier. IEEE MTT-S. Int. Microwave Symposium, 1421. Ragheb, T., & Nieuwoudt, A. (2007). Parasitic-Aware Analytical Modeling of Integrated CMOS Inductively Degenerated Narrowband Low Noise Amplifier. Analog Integrated Circuits and Signal Processing, 51, 11–17. doi:10.1007/s10470-007-9042-z Razavi, B. (2001). Design of Analog CMOS Integrated Circuits. McGraw Hill. Razavi, B., & Kang, H.-C. (2006). Low noise amplifier and related method. United States Patent Application, Pub. No. US 2006/0066410 A1 Razavi, B., & Zhang, P. (2004). Mixer noise reduction technique. United States Patent, Pat. No. US 6,748,204 B1 Rogers, J., & Plett, C. (2003). Radio Frequency Integrated Circuit Design. Norwood, MA: Artech House. Rossi, P., Liscidini, A., Brandolini, M., & Svelto, F. (2005). A Variable Gain-RF Front-End, Based on Voltage-Voltage Feedback LNA, for Multistandard Application. IEEE Journal of Solid-state Circuits, 40(3), 690–697. doi:10.1109/JSSC.2005.843631 Shieh, J. H., Patil, M., & Sheu, B. J. (1987). Measurement and Analysis of Charge Injection in Analog Switches. IEEE Journal of Solid-state Circuits, 22(2). doi:10.1109/JSSC.1987.1052713 Siddiqui, J. (1979). A Generalized Synthesis Design Technique for a 2-8 GHz 1 W Power FET Amplifier. IEEE SSCC, 116-117. Smith, P. H. (1969). Electronic Applications of the Smith Chart. Kay Electric Company. Talwalkar, N. (2006). Low noise voltage-controlled oscillator. United States Patent, Pat. No. US 7,015,768 B1

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Wang, C.-S., & Wang, C.-K. (2006). A 90nm CMOS Low noise amplifier using noise neutralizing for 3.1-10.6GHz UWB System. In Proceedings of the 32nd European Solid State Circuits Conference (pp. 251-254). Wang, Y. (2006). Millimeter wave transceiver frontend circuits in advanced SiGe technology with considerations for on-chip passive component design and simulation. PhD Thesis, Cornell University. Weitzel, C. E. (2003). RF Power Amplifiers for Cellphones. GaAs MANTECH Inc. Yamamoto, K., Moriwaki, T., & Fujii, T. (1999). A 2.2-V operation, 2.4-GHz single-chip GaAs MMIC transceiver for wireless applications. IEEE Journal of Solid-state Circuits, 34(4), 502–512. doi:10.1109/4.753683 Yue, C. P. (2000). Physical Modeling of Spiral Inductors on Silicon. IEEE Trans. On Electron Devices, 47(3), 560–568. doi:10.1109/16.824729 Zhang, G., Dengi, A., & Carley, R. (2002). Automatic Synthesis of A 2.1 GHz SiGe Low Noise Amplifier. IEEE RFIC Symposium (pp. 125-128).

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RF and Microwave Test of MMICs from Qualification to Mass Production Mohamed Mabrouk ISETCOM de Tunis and CIRTA’COM/SUPCOM, Cité Technologique des Communications, Tunisia

ABSTRACT This chapter describes some basic characteristic responses that must be known for each Monolithic Microwave Integrated Circuits. The main parameters such Return Loss, Insertion Losses or Gain, Power at 1dB compression, InterModulation Products or Noise Figure are very important and have to be measured before using the device in final applications. Basic rules of Test and Measurement in RF and Microwaves, as well for characterization on benches as for high volume production using Automatic Test Equipments installed in test platforms, are summarized for helping today’s test engineers to develop their own test solutions. The device, that was characterized on bench and tested in production environment, is a monolithic, integrated low noise amplifier (LNA) and mixer usable in RF receiver Front-End applications for Personal Communications functioning on frequency wideband between 0.1 and 2.0 GHz.

INTRODUCTION In Microelectronic industry, the Test and Measurement “T&M” is a challenge of great importance for devices qualification and characterization in laboratory, and for high volume mass production. T&M is at the beginning and end of each Monolithic Microwave Integrated Circuits (MMICs) function design. All of semiconductor manufacturers remain preoccupied by test time and cost of MMICs for accelerating the delivery to customers and reducing as well as the time to market. All of these constraints are dictated and imposed by customers and competition pressure especially in wireless communications systems and applications which is the economic driver of semiconductors industry.

DOI: 10.4018/978-1-60566-886-4.ch011

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RF and Microwave Test of MMICs from Qualification to Mass Production

What matter is really important is most of us have one or more wireless devices, like mobile phone, organizer, PC, Bluetooth, automotive, identification… Electronic part of all of these equipments are consisting of several RF and Microwave components cascaded (such LNA, Filter, Mixer, HPA,…) and assembled on small and miniature PCB. These components have to be designed and characterized separately and carrefully for meeting standards specifications of qualification and policies of regulatory authorities. Semiconductor manufacturers remain the main providers of MMICs for the market of wireless communications systems and applications. They have to qualify their RF/Microwave components on specific correlation benches before bringing devices to mass production tests. Usually, the correlation benches are consisting of several measurement instruments such Microwave VNA (Vector Network Analyzer), Spectral Analyzer, Power Meter, Noise Figure Meter,… and theirs specifications have to be chosen correctly. Measurement method is usually based on removable test fixture, socket solution or soldered package solution. The introducing of product in high volume facilities test floor is very delicate step. For a large range of complex RFIC and RFSOC wireless device applications, the mixed-signal and RF devices tested are intended to wireless LAN, Bluetooth®, set-top box (STB), 3G and 4G cellular, WiMAX™ and new emerging standards like LTE. The main and known manufacturers of Automated Test Equipments (ATE) can offer some standard and dedicated RF testing solutions with different performance levels. We can quote the following testers as examples (Agilent Technologies, Z2090B-4xx; LTX-Credence, X-Series; Teradyne, UltraWave 12G™). These testers are operating on test floors in different locations throughout the world. Different RF testers based on ATE are used for both on-wafer and final tests. In the final test, an automatic handler is putting device into socket for achieving test steps, and removing it from socket before going to the next device. In order to know the intrinsic parameters of Device Under Test (DUT) with good level of precision, a comparison is usually made between experimental results and those obtained theoretically by simulation model. At presently, the MMICs are operating in telecommunications applications and subsystems under high frequencies and connected together each to other by transmission lines. To characterize these devices on benches or in mass production, we are facing at least two difficulties: • •

What is the characterization method have we to use that must be suitable to DUT technology in order to determine its performances? Interface circuits between input ports of DUT and output ports of measurement instruments have to be repeatable; also they should have low dispersion and insertion losses in order to be actual standards.

In this work, the DUT (NS, 1995) is a monolithic, integrated low noise amplifier (LNA) and mixer usable in RF receiver Front-End applications. The DUT was characterized on benches and automatically tested using ATE testers. As for the benches instruments, ATE testers also have several mixed-signal microwave test configurations suitable for customers dedicated solutions.

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The chapter consists of three main parts. In the first part, some basics about the Test and Measurement in RF and Microwave are explained. Systematic and random measurement errors and their correction are presented. The main and known calibration procedures are reviewed, examples of coaxial and onwafer verification measurement of used calibration are given. Because any RF/Microwave measurement doesn’t have sense only if it’s repeatable, the repeatability principle and measurement example of test fixture is also showed. In the second part, a typical measurement example of compression power at 1.0 dB at the output of LNA versus frequency is carried out on VNA and presented. For the same LNA, some examples of VNA and Tester correlation measurements of return loss and power gain are showed. In the third and last part, measurement example of third order output intermodulation products of LNA is carried out on advanced mixed signals tester an presented. Distribution and plot statistics of Noise Figure measured 100-times on tester is given. All of the measurement examples were carried out using different VNA available on the market and usable by test and measurement experts now.

TEST AND MEASUREMENT IN RF AND MICROWAVE Nowadays, the measurements are at the heart of studies and production controls. The experimental characterization of MMICs is tightly depending on de-embedding reliability of DUT intrinsic parameters. For a DUT that is having one port, or more ports, which can be modelized and represented by network model, the RF/Microwave parameters are obtained from Scattering Matrix [S] measured on VNA systems. This S matrix is based on network theory and gives all of leaving (reflected or depending) waves versus entering (incident or non-depending) waves (HP, 1967; Kurokawa, 1965; Penfield, 1961; Youla, 1961). For all of RF/ Microwave devices, which are described by general two-port network, the coefficients of [S] matrix, commonly called S-parameters, correspond to the input and output reflection coefficient or Return Loss (RL); and input and output transmission coefficients, called Power Gain or Insertion Losses (IL). To avoid mismatching impedance problems, the S-parameters of DUT are usually measured using VNA systems with 50Ω source and load. For complying with tests lists and customer requirements, RF/Microwave measurements must have instrumentation with high precision receivers, dynamic range, low noise and good resolution. The imperfection of instrumentation hardware gives wrong measurements with systematic and random errors. So the instrumentation has to be calibrated and errors have to be corrected before doing any transmission or reflection measurements. The true measurements are consisting to take into account of these errors and removing them before giving the actual measurements values with good precision level. In RF/Microwave, all of the dimensions are important and we cannot neglect the dimensions of circuit elements with regard to the guided wavelength. When a length equals a number of wavelengths, the corresponding transmission line may be transparent regarding to the insertion phase or may introduce some parasitic reflections totally or partially. That’s why the RF/Microwave measurement doesn’t have sense only if it’s made between reference plans. So it’s very important to rigorously define the measurement plans (Jones & Strid, 1987; Mabrouk, 1991 & 1992; Wong, 2007). In general, these plans correspond to the input and output of DUT.

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SYSTEMATIC AND RANDOM MEASUREMENT ERRORS In characterization and high volume production tests, the source of measurement systematic errors is coming from the instrumentation hardware. These errors are repeatable and predominating, so they are correctable after one-port or two-port error modelling. These errors are due to bad directivity of measurement system, impedance mismatching, leakage signals, isolations between measurement reference plans and system frequency response (HP, 1980; Rytting, 1981; Mabrouk, 1992). All of these errors vary versus frequency and have to be known at each frequency. They are obtained from measurements steps of known and traceable standards which are open-short-load terminations and thru connection. These standards are commercially supplied under calibration kits form (HP, 1988), and this procedure is called OSLT calibration. The Open-Short-Load (OSL) standards are connected one after other for achieving one-port calibration (i.e. reflection reference only). The transmission calibration is consisting to connect both two-ports together, i.e. Thru connection step (T). Rytting (1981) reported that the calibration does not remove all of errors but the measurement accuracy is greatly improved with 20.0 dB minimum after correction. The measurement random errors are non-repeatable variations and difficult to be corrected. They are mainly due to temperature drift, noise, operator, test bench stability and environment (cables position and connector handling level). This kind of errors can be negligible and minimized if some cautions were carefully taken. For example, the RF cables have to be kept in the same position and not bended or forced. The RF coaxial connectors have to be tightened with dedicated torque wrench and with the same tightening level. For the wafer test, the probing station has to be continuously stabilized, the wall effect has to be avoided, the probe tips spacing has to be the same during calibration procedure and DUT measurement.

CALIBRATION AND CORRECTION OF SYSTEMATIC MEASUREMENT ERRORS Several different calibration procedures are known, used and suitable to the DUT technologies (coaxial, planar, waveguide,…). One-port, full 2-ports or Response calibration like OSLT, TSD, TRL, and LRM are very known and used. TRL (Engen, 1979; HP, 1987) and TSD (Speciale, 1977) and their varieties such TMR (Eul, 1988) or LRM (Lautzenhiser, 1990) are the most known calibration procedures because they are suitable for wideband RF DUT testing in planar technologies (PCB, in-fixture and on wafer). The calibration standards of these procedures can be auto-designed by user. For all of these calibration procedures, their validities have to be verified by measuring known devices which can be specially designed for this operation (Air-Line, Delay-Line, Attenuator, Mismatched impedance,…). Below are some verification measurement examples. The first one (Mabrouk, 1992) is concerning a very low insertion loss 150mm-air-line reflection (S11) and transmission (S21) coefficients measurements. These measurements were made for verifying a coaxial OSLT-3.5mm calibration (see Figure 1) for a frequency wideband from 2 to 18.0GHz and confirm that the measurements precision has a good level. Below is the second one (Mabrouk, 2008) that is showing S21 transmission coefficient measurement of on-wafer thru standard of Infinity-probes-GSG100 of CASACADE® MICROTECH (see Figure 2). The precision of transmission measurement also has a good level. So it shows S21 of this standard which has length of 200µm. This insertion loss does not exceed 0.08 dB.

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Figure 1. Verification of OSLT-3.5mm calibration: Airline (Hewlett-Packard’s VNA-8510A)

Figure 2. Verification of on-wafer response calibration: thru standard (Agilent’s VNA-8720ES)

Below is the third one (Mabrouk, 2007) that is showing the insertion loss of 5250µm-delay-line (see Figure 3), i.e. S21 parameter, of available devices of Infinity-probes-GSG100 of CASACADE® MICROTECH. The precision of transmission measurement also has a good level because S21 does not exceed 0.4 dB and confirms a good validity level of this response calibration.

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MEASUREMENT REPEATABILITY For each measurement, the test fixture or test setup has to be reproducible and repeatable, i.e. it must allow reproducing the same setup and connection states at all of its reference plans (input and output). The principle of test fixture repeatability (Dunleavy & Katehi, 1987; Mabrouk, 1992) consists to measure the Sij parameter (reflection or transmission coefficient) at the desired reference plan, disconnect the test fixture, reconnect and measure this Sij parameter second time, compute the difference between successive two measurements. For N connections and disconnections of test fixture, the difference SijNSijN+1 in dB is called the Repeatability which can be wrote R(dB)=20∙log(SijN -SijN+1). Below is the repeatability of test fixture (see Figure 4) (Mabrouk, 1992) measured 10 times. This test fixture was designed (Mabrouk, 1991) for enabling a precise characterization of monolithic microstrip line for different applied voltages and presents a good repeatability. In general, the repeatability has to be great than 50.0dB.

ATE AND BENCH MEASUREMENTS AND CORRELATION As mentioned before, the used DUT (NS, 1995) is a monolithic, integrated low noise amplifier (LNA) and mixer usable in RF receiver Front-End applications. Today, the RF/Microwave testers cannot be accepted without the use of correlation test benches using external instruments (VNA, Power Meter, Spectrum Analyzer and Noise Figure Meter) for confirming tester’s capabilities. The design of test device interface board (DIB), DUT card, socket and calibration standards have to be considered. All of these steps are very important, unavoidable and necessary but Figure 3. On-wafer transmission measurement of 5250µm delay-line (Agilent’s VNA-8720ES)

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may to be at the origin of a long test development plan and delay time to market. The goal is to have an efficient RF testing floor, a good test quality, a test development cycle and time to market reduction and a low cost of test hardware. So we have to take time because we do not have to make a mistake, so we have to make an extensive review of various RF platforms. But we are hurry because the competition perhaps is working more hard and more than us! The qualification is a very important step allowing team test to know the level of viability and validity of testing methodology which will be used during high volume mass production. During the whole of qualification step, the product designer and manager have to define together all of electrical characteristics to be known for each device. Also, qualification process is allowing defining the tests list to be carried out for each product and verifying their feasibility. For example, for our DUT (NS, 1995), the tests list consists of some test conditions (Vcc, Temperature, frequency, Zc, Power level,…) under which the DC and AC tests have to be done, typical values, low and upper limits of each parameter. The qualification allows to define and choose the tester instrumentation and to operate the entire mother and channel cards during a long time and saving their functioning states into file called “log-file”. This file restores the cards states (Pass or Fail) and the team test engineers have to verify the entire data’s file and understand the possible failings. Finally, the product designer and manager, but also the test engineer and tester itself cannot go away from the qualification process, and all of steps must be checked during it.

Figure 4. Repeatability of test fixture (Hewlett-Packard’s VNA-8510A)

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Figure 5. Measured compression power of LNA versus frequency (Anritsu’s VNA-37325A)

All of the RF tests have to correlate between bench and tester before to be accepted. That is why some correlation examples are showed below. Firstly, this DUT was characterized on bench using Anritsu VNA-37325A. One of the main aggressive specifications for LNA is the output power at 1dB compression. For this DUT, this power was measured on VNA from 100.0 MHz to 2.4 GHz. The measurement shows that this DUT is suitable to 900.0 MHz cellular phones because it has the best linearity with highest compression power at this frequency (see Figure 5). Other important parameters also have to be measured on both bench and tester. A correlation measurement between Anritsu VNA-37325A and Teradyne A585 tester is showed below. The two measurements of return loss (reflection coefficient S11) and power gain (transmission coefficient S21) of LNA on bench and tester confirm a good agreement and efficient tester hardware. These measurements also have good agreement with test values given by DUT data sheet (NS, 1995). (see Figure 6 and Figure 7) We can see when the measurements were carried out correctly, i.e with the great cautions recalled previously; a good correlation can be obtained between characterization on-bench and ATE measurements. And even if a difference was existing, that one will be minimized. Another aggressive specification is the 3rd Output Intermodulation Products. In Figure 8, we can see this parameter measured on tester and confirms its good capabilities. Another very important specification is the Noise Figure (NF) for LNA. The signal-to-noise ratio at the output of receiving system is very important criterion in wireless communication systems. The noise figure and sensitivity are closely related. There is a difference between NF and F. F is linear and called Noise Factor. NF is logarithmic and called Noise Figure. The measurement showed below confirm that tester results are complying with test values given by DUT data sheet (NS, 1995). This shows specific ATE results, under histogram form, which have to contain the lower and upper limit values (-∞ & 6.0 dB), minimum and maximum values (5.5897 dB & 5.7674 dB), mean value (5.6724 dB), standard deviation (0.0361277), number of tests (100). These ATE results confirm that the test is passing (bin 1)

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Figure 6. VNA and tester correlation measurements of LNA return loss (S11)

Figure 7. VNA and tester correlation measurements of LNA power gain (S21)

and is complying with DUT data sheet where the typical NF of LNA is 4.8 dB and maximum value is 6.0 dB (see Figure 9). The qualification process for the noise factor and correlation measurements is very important especially for LNA as for our DUT (NS, 1995). It requires a noise figure measurement bench which consists of an external noise source with calibrated Excess Noise Ratio (ENR) and an RF receiver. The measurement reference is set up and the bench is calibrated when the noise source is bias with a DC current and connected directly to the noise figure meter.

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Figure 8. Measured 3rd output intermodulation products of LNA for F1=1.999 GHz and F2=2.0 GHz (Teradyne A585 tester)

Figure 9. Distribution and plot statistics of measured LNA-noise figure for 100 tests (Carried out on Teradyne A585 tester)

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The Y-factor (HP, 1983) is one of several methods used by receivers for calculating noise figure. The noise source is applied to the input of the DUT and two measurements are made, one with the noise source ON and one with the noise source OFF. The DUT output signals corresponding to both measurements are routed to the noise figure meter of the bench, and to the ATE tester receiver. The two measurements are plugged into an equation which calculates the Noise Figure of the DUT considering the known ENR.

FUTURE TRENDS In MMICs market, semiconductor manufacturers are continuously requiring both standard and dedicated RF testing solutions. The standards ones are intending for generic and common tests; dedicated are for differentiating products allowing customer to gain and increase its market share. RF/Microwave test market needs reliable instrumentation, low cost equipments, human expertise and resources for fast both on-site and hot-line technical supports. Suppliers of Automatic Test Equipment have to make efforts continuously for offering turn-key RF/Microwave ATE solutions. These ones have to be used to test complex electronics in the consumer electronics, automotive, computing, telecommunications, aerospace and defense industries, high-end RF and mixed-signal test services.

CONCLUSION Both RF/Microwave Characterizations on-bench and ATE measurements both need some rules and cautions. Between bench characterization and production testing, a long time may be taken. During this time, we need to think about the test feasibility, called testability, on-wafer and final tests, the test cost, the test time, the test complexity or/and flexibility, the time to market. Also we have to think about the measurements precision level, the measurements repeatability, the dynamic range, the RF sources linearity and accuracy, the instruments sensitivity and noise floor, so we have to evaluate carefully our RF test needs. The suppliers of benches and ATE equipments have to be very reactive to complying with customer requirements and they have to take care with the volatility that has always affected the semiconductor industry with cycles of surging demand followed by strong declines. Scattering parameters (S-Parameters) are very useful in RF & Microwave testing. One-port or two-ports DUT need a suitable calibration procedure which has to be very well thought for improving measurements accuracy. If we need to make a good RF measurements and testing, we have to manage carefully the test fixture, the socket and handler, the wafer and probes station.

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Rytting, D. (1981, April). An analysis of vector measurement accuracy enhancement techniques. Paper presented at Hewlett-Packard RF & Microwave Measurement Symposium and Exhibition, Santa Rosa, CA. Speciale, R. A. (1977). A generalization of the TSD network-analyzer calibration procedure, covering n-port scattering parameters measurements, affected leakage errors. IEEE Transactions on Microwave Theory and Techniques, 25, 1100–1115. doi:10.1109/TMTT.1977.1129282 Wong, K. (2007). A Very Brief History of Network Analyzer Calibration. Agilent Measurement Journal, 1, 53. Youla, D. C. (1961, July). On Scattering Matrices Normalized to Complex Port Numbers. Proceedings of IRE, 49, 1221.

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About the Contributors

Arjuna Marzuki obtained his B.Eng (Hon) in Electronic (Com) from the Department of Electronic & Electrical Engineering at the University of Sheffield in United Kingdom, MSc from Universiti Sains Malaysia and PhD from Universiti Malaysia Perlis. He co-founded C-RAD Technologies (http://www.cradtech.com.my) in year 2005 and remains as technical consultant with the company. Since 2006, Arjuna has joined School of Electrical and Electronic Engineering, Universiti Sains Malaysia as a lecturer. He teaches analog circuit design and integrated circuit design. He is also an associate research fellow with Collaborative µElectronic Design Excellence Centre (CEDEC), USM. Arjuna has gained professional qualification as professional engineer when he was elected to the Register of The Society of Professional Engineers, SPE(UK) (http://www.professionalengineers-uk.org). He is also a corporate member of Institute of Engineering and Technology (IET)- MIET, a fellow of The International Institute of Engineers (IIE), a senior member of International Association of Computer Science & Information Technology (IACSIT). Arjuna has to-date filed 4 international patents and published more than 20 technical papers. He has developed more than 20 commercial products during his employment with Hewlett-Packard/Agilent Technologies and IC Microsystems. Ahmad Ismat Abdul Rahim ([email protected]) was born in Penang, Malaysia in 1971. He received his B.Eng (Hons.) in Electrical Engineering, MSc. in Microelectronics Systems Design and Ph.D in Microelectronics in 1994, 1995 and 1999 respectively, all from the University of Southampton, England, U.K. He was Technology Development Leader with MIMOS Berhad (www.mimos.my) involved in the development of 0.35um CMOS, BiCMOS and SiGe technologies; Wafer Fabrication Specialist & TCAD Sales Engineer for IC Microsystems Sdn. Bhd. (www.icmic.com) and Senior Design Engineer, Penang Design Center, Intel Microelectronics (M) Sdn. Bhd. responsible for design-process interaction analysis and device physics-design investigation and for P1263 (90nm) process model characterization for next generation chipset design. He is currently Associate Principal Researcher in the Advanced Physical Laboratory at Telekom Malaysia R&D Sdn. Bhd. (www.tmrnd.com.my), involved in the development of MMICs and RFICs for applications in Radio-Over-Fiber (ROF) and Fiber Wireless (FiWi) systems for Gbps Next Generation Broadband communication systems. Ahmad Ismat has published over 50 technical papers and filed 4 patents. His research interests are in device and circuit design and modeling for MMICs and RFICs. Mourad Loulou was born in Sfax, Tunisia in 1968. He received the Engineering Diploma from the National School of Engineers of Sfax in 1993. He received his Ph.D. degree in 1998 in electronics system design from the University of Bordeaux France. He joined the electronic and information technology

About the Contributors

laboratory of Sfax “LETI” since 1998 and he has been assistant Professor at the National School of Engineers of Sfax from 1999. Since 2004 he obtained his HDR from the University of Sfax and he has been an associate Professor. Currently he supervises the Analogue, Mixed Mode and RF Design Group EleCom of LETI Laboratory. His current research interests are on Analogue, Mixed and RF CMOS integrated circuits for communications and design automation of analogue CMOS Integrated Circuits. He is senior member IEEE; he is currently the IEEE Tunisia Section and CAS Chapter chair. *** Amiza Rasmi was born in Perlis, Malaysia in 1981. She received her B.Sc in industrial physics from Universiti Teknologi Malaysia in 2004 and M.Sc. in Microelectronic Engineering from Universiti Malaysia Perlis in 2006 respectively. Currently she is a researcher in Telekom R&D Malaysia Sdn. Bhd. who worked on the GaAs PHEMT Technology for low and high frequency applications. Her research interest includes RF technologies, microelectronic and nanotechnology devices. Amin Sallem was born in Sfax, Tunisia in 1981. He received the electrical engineering diploma and the master degree in electronics from the National Engineering School of Sfax (ENIS) in 2004 and 2008, respectively. Since 2004, he is a PhD student at the Electronic and Information Technology Laboratory of Sfax (LETI/ENIS). In February 2008, he joined the Higher Institute for Technological Studies of Sousse (ISET) where he is working as an assistant. His current research interests are on analogue CMOS integrated circuits design and on optimization techniques. Chin Guek Ang graduated from school of electrical and electronic engineering, Universiti Sains Malaysia, Malaysia. Now she is working in Malaysia as an engineer. Ching Wen Yip graduated from school of electrical and electronic engineering, Universiti Sains Malaysia, Malaysia. Now she is working in Malaysia as an engineer. Daniel Pasquet (M’86, SM’96) is a professor at Ecole Nationale Supérieure de l’Electronique et de ses Applications in Cergy, France and has his research activity at LaMIPS in Caen, France. He gained his Ph.D at Lille University in 1975. He is currently IEEE France Section chair, MTTS chapter coordinator for Region8 and member of TC-11. Dorra Mellouli was born in Sfax, Tunisia, in 1984. She received the engineering degree in Electrical Engineering and the Master degree in Electronics Engineering from Sfax National School of Engineers (ENIS), Tunisia, respectively in 2007 and 2008. In 2008, she joined the Sfax Preparatory Institute for Engineering Studies, Tunisia, as an Assistant. She is currently working toward the Ph.D degree at Electronic and Information Technology Laboratory of Sfax University, Tunisia. Her current research interests design and modeling of Radio Frequency Integrated Circuits Hassene Mnif was born in Sfax, Tunisia, in 1975. He received the engineering degree in electrical engineering and the Master degree in electronics respectively in 1999 and 2000 from the National School of engineers of Sfax, then he received the Ph.D. degree in electronics from the University Bordeaux 1,

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About the Contributors

France, in 2004. Then, he joined the Electronics and Communications Superior Institute as an Assistant Professor as well as a researcher in the Electronic and Information Technology Laboratory of Sfax University, Tunisia. Since 2008, he has been a Director of Electronic Department. His research interests include design and modeling of Radio frequency Integrated Circuits and compact and behavioral modeling of nanotechnology components. Mariam Boughariou was born in Sfax-Tunisia in 1983. She received The Engineering Degree in 2007, from the National Engineering School of Sfax (ENIS)-Tunisia. Since 2007, she is working in TELecom NETworks Engineering Society (TELNET) as a design engineer in the Analogue and Digital Microelectronic Team. She is also a Master student with the LETI Laboratory-ENIS. Her current research focuses on the design and optimization of Radio Frequency (RF) circuits. Meriam Ben Amor was born in Sfax, Tunisia in 1981. She received the Electrical Engineering Diploma then the Master degree in electronics from the National School of Engineering of Sfax “ENIS”, respectively, in 2004 and 2005. She joints the Electronic and Information Technology Laboratory of Sfax “LETI” since 2004 and he has been a PhD student at the National School of Engineering of Sfax “ENIS” from 2005. She joints the two Research Group: Electronics and Communication group (EleCom), ENIS, Tunisia and the Circuits, Instrumentation and Electronic Modelling group (ECIME), ENSEA, France since 2006. Her current research interests are on analogue RF CMOS integrated circuits design for communication systems. She is actually an assistant Professor at the National School of Engineers of Gabès. Mohamed Mabrouk (M’89), was born in 1961 in Aouadna, Menzel-Chaker, Sfax, Tunisia. He received the DEA and PhD Thesis degrees in OOM (Optique Optoélectronique et Microondes) from LEMO-ENSERG-INPG (Grenoble-France) in 1988 and 1991 respectively. His doctoral research concerned RF and Microwave Test and Measurements using TRL calibration for MMIC characterization between 2 and 18 GHz. From 1995-1998, he worked for Teradyne (based in Paris office) as RF/Microwave Applications Engineer, where he developed several ATE turn-key RF test solutions and dedicated trainings for European Semiconductors manufacturers. Since 1999, he is Assistant-Professor at ISETCOM of Tunis, Tunisia. He is currently teaching RF and Microwave devices, Transceiver equipments and RF/ Microwave Measurements. He heads Tunable and Reconfigurable RF Devices and Integration Team, CIRTA’COM Research Laboratory (SUPCOM of Tunis). His current research interests include RF/Microwave non-linearities measurements, UWB Filters and integrated printed antennas characterization and reconfigurable RF devices. Mohd Tafir Mustaffa was born in Kedah, Malaysia in 1977. He received his first degree (B.Eng.) in electrical and electronic engineering from Universiti Sains Malaysia (USM), Penang in 2000. From May to October 2000, he worked as an engineer at Data Acquisition System Sdn. Bhd. From November 2000 until July 2004 he joined USM as a tutor. After that, he got a scholarship from USM to pursue his study starting July 2004 and was awarded a master degree (M.Eng.Sc) in computer and microelectronic engineering from Victoria University, Australia a year later. From August 2005, he continued his study at the same university and was officially completed his PhD in electrical engineering specializing in radio frequency integrated circuit (RFIC) in September 2009. He is now a lecturer at the School of Electrical and Electronic Engineering, USM, Engineering Campus, Nibong Tebal, Penang, Malaysia. He is also a member of IEEE since 2007. 360

About the Contributors

Mourad Fakhfakh was born in Sfax-Tunisia in 1969. He received the engineering and the PhD degrees from the national engineering school of Sfax Tunisia in 1996 and 2006 respectively. From 1998 to 2004 he worked in the Tunisian National Society of Electricity and Gas (STEG) as a department head. In September 2004, he joined the higher institute of electronics and communications (ISECS) where he is working as an assistant professor. Since 2002 he has been with the electronics and information technology laboratory (LETI/ENIS) where he is currently a researcher. His research interests include symbolic analysis techniques, analog design automation, and optimization techniques. Norlaili Mohd Noh had received her B.Eng (Electrical) from Universiti Teknologi Malaysia (UTM), MSc (Electrical & Electronic) and PhD (Electrical & Electronic) from Universiti Sains Malaysia (USM) in 1987, 1995 and 2009, respectively. She was a tutor with USM from 1988 to 1995 and a lecturer with the same university since 1995. She has teaching experience in courses like Electronic Devices, Analog Circuits, Circuit Theory, Electronic and Analog laboratories, Introduction to IC Design and had supervised more than 60 undergraduate final year projects. She has written 8 teaching modules throughout her teaching career. Her areas of expertise and professional interest are in CMOS RFIC front-end design (specifically in LNA design) and analog CMOS integrated circuit design (especially in amplifiers, biasing circuitries and buffer designs). Her PhD work was on the development of inductively-degenerated LNA for W-CDMA application utilizing 0.18 µm RFCMOS technology. She has published 18 international conference papers, 9 regional and local journal papers. Sébastien Quintanel received the Ph.D.degree in electronics from the University of Limoges, France in 2002. Since 2003 he is an assistant professor at Ecole Nationale Supérieure de l’Electronique et de ses Applications (ENSEA) in Cergy, France and is doing his research at the ETIS laboratory (Systems and information Processing researches). ETIS is a CNRS research lab (UMR CNRS 8051) located at Cergy-Pontoise University and ENSEA. His research activities concern principally the design and characterization of low noise devices for microwave and millimeter-wave applications. Wan Yeen Ng graduated from school of electrical and electronic engineering, Universiti Sains Malaysia, Malaysia. Now she is working in Malaysia as an engineer. Xhiang Rhung Ng graduated from school of electrical and electronic engineering, Universiti Sains Malaysia, Malaysia. Now she is working in Malaysia as an engineer.

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Index

Symbols 1-dB Compression Point (P1dB) 114, 118, 134, 138, 140, 143, 145, 153-154, 161-162, 177, 181, 197, 201-202, 205, 230, 232-233, 235, 263, 276 3G systems 1, 3-5 3rd Generation Partnership Project (3GPP) 2-4, 22

A Accessories Networks (AN) 4, 6-7, 10-13, 15, 2225, 27, 29, 35, 40, 42-43, 45, 48-50, 52-57, 5960, 62-64, 66-68, 70, 73-75, 78-79, 81, 85-87, 90, 92-93, 95, 97, 100, 102-103, 105, 107-108, 110-112, 116-120, 122-124, 129, 138, 140, 154-155, 157-158, 160-161, 163, 180, 184, 186-191, 193-194, 197, 199, 201, 205-207, 209-210, 215, 217-220, 223, 242, 246-249, 254-255, 260, 263, 265, 271, 287, 295, 298, 309, 312-313, 317, 319, 322-323, 325, 327, 329, 334-335, 339, 341, 343-345 ADS software 100, 263 Advanced Design System (ADS) 4-5, 69, 82, 8485, 100, 106, 132-133, 154, 157, 167, 183, 189, 192, 194, 199, 203, 205-206, 215, 233, 253, 263, 274, 276-277, 282, 288, 329 Aluminum Gallium Arsenide (AlGaAs) 108, 184, 197, 203 analogue circuit design 75 Ant Colony Optimization (ACO) 77 Automated Test Equipments (ATE) 334, 338, 340, 343 automotive radar 205-206 automotive radar transmitter 205

B bandpass filter 159

bandwidth 3, 6, 30-31, 51, 53-57, 59, 67, 105, 116, 118, 120, 159, 166, 186-187, 190, 218, 220, 241, 244-245, 248, 250, 252-254, 263, 265, 278, 292-293, 319 bandwidth performance 57 bench characterization 343 biasing network 218, 220, 224 Bias Network (BN) 72, 118-119, 122, 171, 217, 262, 274 bias voltage 40, 43, 170, 172, 237 Bit Error Rate (BER) 4, 162 Bottom Series QVCO (BS-QVCO) 89-91, 94, 9697, 100-102

C Carrier to Noise Ratio (CNR) 4 cascade topology 108, 116, 131, 171, 173 CG amplifier 26, 30 channel blockers 158 Classical Noise Matching (CNM) 30-31 close-loop gain 126, 129 Coates flow-graph technique 69-70 Common-Drain (CD) 30, 40, 43, 56-57, 124, 170, 262, 274, 288, 309, 321 common-gate input 55 Continuous Wave (CW) 107, 325 Coplanar Waveguide (CPW) 48-49, 60-64, 67 CPW line 48-49, 60-63, 67 CPW transmission line 48-49, 61, 63 CS cascode 44 Current-Reuse (CR) 24-25, 38, 40, 42, 44, 56 current reuse topology 56-57, 67

D DC blocking capacitors 218, 220 design methodology 105-106, 116, 206, 210, 217, 222, 240, 265, 327 Design Rules Check (DRC) 133, 205, 216

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Index

Device Under Test (DUT) 334-336, 338-341, 343 Direct Broadcast Satellite (DSB) 205-206 Direct Conversion Receiver (DCR) 6-8, 10, 21, 50-51 directed graph approach 74

E electronic amplifier 157 Enhanced-GSM (EGSM) 6, 21 European Telecommunications Standards Institute (ETSI) 2-4, 21 evolutionary algorithms 77, 243 Evolutionary Computation (EC) 77

F feedback topology 108, 123, 126, 128-129, 164165, 188, 194, 198, 220, 255 Field Effect Transistor (FET) 46, 108, 117, 155, 205-209, 238, 324, 331 Figure of Merit (FOM) 102, 265, 292-293, 328 Folded-Cascode (FC) 24-25, 40, 42-44

G GaAs PHEMT technology 106, 132-133, 157, 183, 185-186, 189-194, 198, 201-202, 205, 233 GaAs technology 187, 197, 271, 325, 327 Gallium Arsenide (GaAs) 105-109, 120, 132-133, 141, 154-155, 157, 183-187, 189-195, 197-199, 201-207, 210, 233, 237-238, 270-271, 305, 325, 327, 329-332, 344 Genetic Algorithms (GA) 77, 86 Global Positioning System (GPS) 6-7, 9 graphic optimization strategy 90

H heterodyne receiver 6, 49-50 Heterojunction FETs (HFETs) 108 Heterostructure FETs 108 High Electron Mobility Transistor (HEMT) 105106, 108, 120, 154-155, 164, 166, 186, 204, 270 Homodyne Receiver 49-51

I IF frequency 49 impedance load 25, 44 Indium Gallium Arsenide (InGaAs) 108, 184, 197, 203, 237

Inductance-Capacitance (LC) 42, 55, 57, 81, 89-90, 93, 102-103, 160, 267, 283, 297, 312, 328, 330 Inductively-Degenerated Common-Source (IDCS) 1, 12, 14, 20, 24 Input IP3 (IIP3) 4-5, 43, 66-67, 176-177, 180, 242 Input Matching Network (IMN) 57, 119, 124-125, 168, 194, 198, 217, 226-227 Input Third Order Interception Point (IIP3) 4-5, 43, 66-67, 177, 242 Insertion Loss (IL) 205-207, 209-211, 213, 215216, 233-234, 237, 267, 333-337 Intermediate Frequency (IF) 5-6, 25-26, 29-30, 33, 35-36, 40, 42-43, 49-51, 54, 56, 59, 62-63, 72, 78, 92, 98, 108, 114, 116-118, 129, 155, 160-161, 163-164, 187, 189-191, 208-210, 232, 241, 247-248, 251, 254, 257, 259-260, 268, 285, 287, 312, 315-317, 319, 335-336, 340, 343 InterModulation Products 114-115, 333, 335, 340, 342

L large-signal optimization 105-106, 116, 120 LC-ladder filter 55 LC-tank 89-91 load-pull 155, 185, 191-193 load-pull technique 185, 191 Low Noise Amplifier (LNA) 1-2, 4-5, 9-25, 27-31, 33, 35-36, 38, 40, 42-46, 48-50, 52-60, 62-64, 66-70, 79, 81-82, 85-86, 88, 105, 157-160, 164, 175, 177, 182-184, 205-206, 217-218, 220, 230, 232-233, 235-237, 240-244, 246, 253, 262-263, 271, 274-277, 288, 290-291, 307-310, 319-321, 327-335, 338, 340-342, 344

M measurement random errors 336 measurement systematic errors 336 Medium Power Amplifier (MPA) 106, 124, 132, 136-147, 152-155, 185-206, 222-230, 232-235, 237, 240-241, 253, 263-264, 271, 276, 278279, 288, 290-292, 309-311, 328 Metal-Insulator-Metal (MIM) 108, 110, 155, 184, 307, 309 metropolis algorithm 78 Millimeter Wave Integrated Circuit (MMWIC) 106, 108, 205 MMIC LNA design 157 MMIC power amplifiers 105-106 Monolithic Microwave Integrated Circuits (MMIC) 105-111, 116, 120, 132, 141, 154-155, 157,

363

Index

184, 203, 205-206, 218, 237-238, 240-242, 244, 250, 252, 327, 329-330, 332-333, 344 multiband LNA 11, 48, 52-53, 307, 321 multiband receiver 48, 52-53 Multi-Channel Multipoint Distribution Service (MMDS) 106 multi-standard multi-band LNA 1-2, 12-13, 16, 18, 20 Noise Figure (NF) 4-5, 11-14, 20, 24-27, 30, 33, 35-36, 38, 40, 44, 48, 51-55, 57-61, 63-64, 66, 70, 81-82, 85, 87, 120, 123, 157, 159-164, 174-175, 177-178, 180-182, 186, 205, 217-218, 220, 230, 233, 235, 241-244, 250, 253-254, 260, 262-263, 265, 270, 278, 282, 293, 295, 319, 328, 333-335, 338, 340-341, 343-344

N Normal Boundary Intersection (NBI) 244 NP-hard optimization problems 75 Number of Finger (NOF) 121, 211, 218, 274, 288

O Open-Short-Load (OSL) 336 Orthogonal Frequency Division Multiple Access (OFDMA) 51 oscillators 49, 89-90, 100-101, 103, 265-269, 297, 299-300, 302, 328 OSLT calibration 336 output buffer 42-44, 287, 302 Output Matching Network (OMN) 119, 126-127, 170, 192, 194, 198, 217, 224, 228-229

P Parallel QVCO (P-QVCO) 89-91, 94, 99-102 Parasitic-Aware-Core-Base (PACB) 250, 271, 328 Particle Swarm Optimization (PSO) 77, 87 phase noise 89-92, 95, 97-98, 100-103, 265 Power-Added Efficiency (PAE) 105, 113, 117-118, 134, 138, 140, 143, 145, 153-154, 185, 187, 192-194, 197, 201-203, 205, 230, 232-233, 238 power amplifier design 105-108, 113, 116, 118-120, 123, 186-187, 191, 194, 237, 271 Power Amplifiers (PA) 105-108, 112-115, 118, 156, 185-186, 188, 192, 197-198, 201-205, 224, 229, 240-241, 263, 271, 276, 310, 322-323, 327, 332 Power-Constrained Noise Optimization (PCNO) 30, 35

364

Power-Constrained Simultaneous Noise and Input Matching (PCSNIM) 24-25, 30, 36, 38, 40, 42-44, 310, 321-322 propagation delay 258 Pseudomorphic High Electron Mobility Transistors (PHEMT) 105-106, 108, 120, 124, 132-133, 141, 154-155, 157, 183-186, 189-195, 198-199, 201-205, 210-211, 213, 218, 233, 237, 240, 253, 270, 274, 278, 304-305, 330

Q quadrature generation 90 quadrature oscillator 90, 94, 100-102 quadrature signals 90, 102 Quadrature Voltage Controlled Oscillators (QVCOs) 89-90 QVCO circuit 90

R Radio Frequency Integrated Circuit (RFIC) 1, 21, 68, 87, 184, 204, 237-238, 240-241, 250, 252, 327, 331-332, 334 Radio Frequency (RF) 1-8, 10, 16, 20-22, 26, 28, 45-46, 48-49, 51-53, 55-57, 66, 68, 86-87, 90, 103, 105-108, 110, 112, 114-117, 119, 123-124, 155-157, 159-160, 162, 164, 171, 184, 186, 188, 203-206, 208, 210-211, 215, 217-220, 223, 232, 237-238, 240-243, 252, 254, 256, 260, 263-264, 267, 271, 274, 278, 288, 310, 316-317, 324, 327, 329, 331-336, 338-341, 343-345 RC feedback 123, 185, 187-190, 201, 263-264, 278, 281 receiver path 49, 215 reconfigurability 1, 7-8, 10, 12 repeatability 335, 338-339, 343 resistive shunt feedback 55 resistive termination 54-55 return loss 1, 64, 105, 133, 137-139, 142, 144, 154, 175-177, 179, 182, 192, 196-197, 199-200, 202, 210, 215-216, 233-234, 236, 244-245, 261, 333, 335, 340-341 RF filters 2, 10 RF front-end design 210 RF receiver system 2, 6 RF signal loss 159 ring oscillator 90 Rollet’s stability factor 187, 189-191

Index

S scattering parameters 69-70, 85, 244, 343, 345 series-shunt SPDT switch 214, 216, 234 shunt mounted transistors 213 Silicon Germanium (SiGe) 11, 45, 156, 204, 246, 332 simple transistor 234 Simulated Annealing (SA) 69-70, 75, 77-80, 82-83, 85, 87, 243 Simultaneous Noise and Input Matching (SNIM) 17, 24, 30, 33-36, 38, 42, 44 Single Pole Double Throw (SPDT) 205-208, 210, 214-216, 230, 232-235, 237, 324 single series SPDT switch 234 single-stage MPA 185, 189-190, 192, 194-197, 202 small-signal design 105-106, 116, 118 Small-Signal Gain (S21) 1, 48, 66, 71, 82-84, 105, 114, 133, 142, 144, 154, 160, 196-197, 200, 202, 205, 246-247, 257-258, 261, 265, 274, 277-278, 281, 288, 293-295, 305, 307, 309, 336-337, 340-341 SPDT switch 205-208, 214-216, 230, 232-235 spiral inductor 49, 103, 110, 183, 307, 309 startup constraint 98 state device impedance 208 switch isolation 213 symbolic analysis 69, 86-88 System-on-Chip (SoC) 243

T Tabu Search (TS) 21, 77 tank amplitude 89, 92, 95, 97-102 Test and Measurement (T&M) 333, 335 Third-Order Intercept Point (IP3) 4, 64, 161-162, 176, 180 Titanium Tungstosilicate (TiWSi) 109

transconductance 15, 17-18, 24-25, 30, 38-40, 44, 54-55, 57, 59, 93-94, 115, 120, 221, 245, 263, 271, 315-316 tuning range constraint 98 two-stage MPA 142, 145, 154, 185, 189, 198, 201

U Unit Gate Width (UGW) 120, 211-213, 218, 274, 280, 288 Universal Cellular Engineering (UCE) 1, 3-4, 23 Universal Telecommunication System (UMTS) 1, 3, 6-11, 21, 23, 81

V Variable Signal Generator (VSG) 240, 265-267, 269, 285-287, 294, 298, 302-303, 305, 328 Voltage Controlled Oscillator (VCO) 89-90, 102103, 240-241, 309, 312-316, 327, 330-331

W wide band LNA 20, 48-49, 53-56, 59, 62, 64, 66-67 Wide Code Division Multiple Access (WCDMA) 1, 3-4, 8-9, 11-12, 23, 45-46, 330 wireless application 105, 154, 240, 328 wireless communication systems 48, 51, 340 Wireless Information Networking (WIN) 132-133, 157, 172, 175-176, 180, 183, 216, 218 Wireless LAN applications 105, 155, 203-204, 237 Wireless Local Area Network (WLAN) 7, 9, 12, 106-107, 186, 209 Wireless Local Loop (WLL) 106, 202 Worldwide Interoperability for Microwave Access (WiMAX) 48-49, 51-52, 55, 66, 105-107, 155, 202, 204, 237, 334

Z zero IF receiver 49

365