3rd International Symposium on Quality Electronic Design: Proceedings 2002 March 18-21, 2002, San Jose, California

Trading off Reliability and Power-Consumption in Ultra-Low Power Systems AtulMaheshwari Wayne Burleson Russell T...

Author: IEEE Computer Society

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Trading off Reliability and Power-Consumption in Ultra-Low Power Systems AtulMaheshwari Wayne Burleson Russell Tessier !"#%$'&(#) +*, .-/+ /.01/2# 3/546798:#33;<>=,*?3;5!3@"AB= 3!@C8DAFE$*

Abstract

&O /!#O34X3 ;3YZ[<\ I ]^[ 3@$_`P //# # 3@UNa# I P]#) +*, ; 3+$6/=; b; >#!c-.$L-<!3\=#2#bdDP $;3e-%>$f%#YZ4];# g MZ!P/Z/54hP*,B#i3]; D*,Z5 MI #N Na; h#3*,) +5!#j$*kdlZ/b/ >$mP ; 4lZ ;^Von%=?p3 g>q; + M;3g# M=?/ ;5*, M;@\WM-!:#%$r/ M*,/92Xs +I + M^= ;3hdtQ=?p3k5 M$<>u)Vwv1#*,Zx #W; M+h >=,!y*3 #BQ= z# M=?/ ;5*, M{2#;)#|P:P M^$?e4};#33 _$k/ 35 !s xd) M#` M$#*,+$<#%;4V~03/.-f#mMq?U %'7 #*, 3!/%# 46+${s M4]Na93M= #NmQ= ( ;) M# M;I $#*,%$#%;4rp3DP3\3*,/d$;# 6Q= ;3g*,Z5 M#I N #Na g#%$ #N6 ; Q; ]+34X3dY3`#3`/#3*,;3`H<E m33 #Na /=#m#m# Mz M$#*,%$#Tcd=?!y*^Vm&O/ M*,/\ >=,!y*3 #/N Na; I

>;Z!LVAo;Q= ^$M-4mp3k$<;2#> $PX3$~#NCI 2X1;*,ZB3/b*,#5!#*?3/.-k C#&`@N1=?!=|/#NO3r$<;I d/$/ M;*,/Y]^$i3\; :P>/=: #Na '> 3*,) +5!#|#%$

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1. Introduction `>e>W M, > b > ] W ¡ ¡ W > W¢ ¡ ;£d ¢L h¤ ;¥T¦ M WW M >~M§ ] ¨ ¦ ¨ > £ ¨ >§B ¡ © > © M Wª¦T ¦ M£ MLMW L«D¬© ]M:M§ ]M ¦ MM z ¨ M§k>§ ! ;D>§ { ? M§ M, > ¦ >> ¦Th> ¡W ; '>L§ M§;W> © e '© >§ , ML c § ©W ¦T].>ML] W' ¨ £ ¡ ¨ «B® cM§ > ] MW]sM§ UMMp M§ M, > ¨ > M§ © !© £5M L ;xML§ W¯ © >z © MDM ¦ Q© MW £ « °r±c²9>L§ B M> C > W > M© M ;W> © e ¨ M§9§ § ¡ ¨ M© ¡ MW B9 ¨ LM£ ¦ e <«C³ § a¡¡ © (´ £5¦ a> £5MW]U; © > (` ; ¡ 9> ©,g!© M£> cM^§ p¯ © \ µ< Lµ W W©T > M{M§{M L¶¦+; ¨ ¡ ¨ Lx; £ © ¡ MW ' > ¦ C], M « ³ < MW !© `M ; § ] a W¢ ³ > ¡ \°' £ © p 1·U ,© T b¸³ °:·)¹ ¡ >#µ. § § ML( ?!© M£ M L ; ¨ § ) ¡ L <M ; aM§\ ` ]>M§ ¨ 9MW] M§ > Y¡ ¨ ` M© ¡ > « °' C M§ ¦+#µ`] MW M, > C >M W MWµ Wc ¨

¡ > ;)¦ © M ¡ ¨ aMMp T § ;)]MWµ M M§ ©, M§B ¡ U '¡ ¨ U M© ¡ MW ',© 9M ;< ¡ > "!© M£> « ³ §UML C +¡T¡ ( < Wª bC W ¨ Lº ²?^£ MW }»: ©TM ¨ p]W ¡ Lb > ; © > ¨ § p§ ¨ LM'; LM <M§ x ©T,« ²?L;MW m¼k £ ©TM M§ g];M>p Y ];>§ <r©T Mz] M© M !© M£> Y¡ ¨ « ²?^MW b´c ©TM ];>§ W ¡ M#µ? M§ ); © M ¦ ] > © £ {¸! >§ M^ © M Lµ ¹ ¦ > < B <b;W£ © e9¦ ,¢ b¸ © e Lµ ¹ «B½ W ²?^> f¾D ©TM ]9; W© W T6Q© © M ¨ >¢ «

2. Counters ¿ M§ s L> ¨ ©> M§ \ ¡ ] > "À £ {rÁ X ; © > ¨ § W§ ¨ >Y > g )M§ ©,<«"½T© ;>L> M^§ p¯ © 1M§ ; © M M p ©> «À 'kÁ X © > \ M © W M§ U¡T¡ )¦ © UM§ > ]cM^§ p¯ © ¦T;?M M ] ? ;W> © e « ` © ML ¨ LMa ¢ bO ; b£ ¡ <M§ \ ©,{ >§ ' > M ¡ ) M§ M? ML X ¦T © }<Y MWbL] <r M M > < M§ g¡ M#µ? c ¨ e¶%> MB ; C ; © M «

2.1. Binary Counter ³ § À © ML9 >§ ¡ ] Y;b£ ] W9© ; © > «"Á © M gÂeÃÄ?¡ M ¡ B >L§ W¯ © C ¢. M§ À ; © M !© L © > «1®t¡ > ¡ M M§ ³kÅ ¡ £ Å ¡ ¨ 1© c < ;M^> >> «½ © > Ã § ¨ >§ \ © e ¡ ] MW Y³tÅ ¡ £ Å ¡ ¦ ; © ML ¨ e>§ !© ;>L> { p « ³`?¡ p WW °r±c² À © ML t >|W ¡ ;£ ] M mx § ¨ ½ © > » M§]M§ m© h³ Å ¡ £ Å ¡« ²? ;>§ ¡ ] > h© 9'¬ £ Å ¡kÅ ¡ ¸ < cp >§+¹ b ³ £ Å ¡bÅ ¡ M§ W >M§ ¡ M ¡ kÂÃ;Ä ¦+ >L; W6¡¡ W M]>§ ; © M «CÆ ¨ £ µ< g ML M §]9 ¦T © ¨ § LMM§ ¡ M >§ f ¦ Tp:¸!ÇBÈ]É ÇBÈYÊ}««W«ËÇYÈYÌ ¹x p M

Proceedings of the International Symposium on Quality Electronic Design (ISQED’02) 0-7695-1561-4/02 $17.00 © 2002 IEEE

PARITY

ENABLE

T

Q

T

TFF

Q

T

TFF

Q

T

TFF

Q TFF

CLOCK

a) Binary Counter using T−Flip Flop T1 T2 T3 T4

PREDICTED PARITY D

Q1 Q2 Q3 Q4

Q

Q’

CLOCK

b) Parity prediction logic

½ <© M Ã<º Binary counter with fault detection using T-Flip flop § ;>§ aM§ ¡ >e M§ ;? M ¨ W § s « ¨ Æ ;r M M§ É Ê}««W« Ì| W ¥ © > Ã<¸ ¦T¹ <psÇBÈbÉ ÇBÈYÊb«W««(ÇYÈYÌ ¦T © M ML; ]!© « ¿ ¦T L >§ ½ © M Ã'½ © > » M W] p 9W ¡ ] MW M§ À ; © MLB; ; ¡ s>§ 9]] ] « M < >x; T >§ ¡ ] > z § ¨ f½ <© M »] M§ c ©,'< )¡ ¡© W UW ¡ Lb > '{p ¢< ) < M ;< ¡T > À ; © ML ¨ M§ Á X ; © > «

] Á X b © ML § < ¦TL f¡ > ¡ > > µ ¡ ¨ L >§ b M> 1¡ >§: Y¦+ z¡ M, > < BÂ »XÄd« >¢:§ ¦+ f bM ¡ >#µB>§ µ sÁ X ; M M >§ {; >;?b ¦ x§ M§ M Mx 6 § ; M ,© > B ¨ >§ £ MWµ?e ¦ x ¼ £ ¾ ,© > Y <M T¡ > ,L © MW x© £ rfÁ X ; g; © > Â ¼#Ä5«kÆ ¨ µ< W ¡ ] M Á X ; © M ] x ¡ < kÀ ; © ML L«x®¤ e¥T ] © 9 Wb M^¯ © > M M>] >§ ;? >] >§ ; © > «³ § \ pY ¹ . > ) ¡: ©M©W W k mÃ ¸ £5¦ec; © > : ;£ ¡ W M§ {¦ >§ ¡ MLµ? ©] M >§ W ;< ¡ L] L« ®) M§ D p ;< ¡ ? ] §<g © ¡ ¢? M§ Á X ; © >B]<M ¡ ¨ L9§ © «g®) § ¨ ½ © M ¼ r ] M tÁ X ; © M Â ´XÄ ¦+ © >kM ,© ;DM§ ] © ] \ p6>L¯ © WM ¨ M§ © ] §. M M§ ¨ >§ ;MWµ. «C¬ ;>LM£ ]!© 'Á X ; © > µL M6 ¨ M§{Lµ >)§ s>§ ¡ M § ] (¢< ¡T M « ® ;W> © e ¡ ] > >§ Á X © > § ¨ {½ © > ´« 4 − bit Gray counter

overflow

overflow

4 − bit Gray counter

.....

4 − bit Gray counter

overflow

a) Segmented Gray counter using 4−bit Gray counters

ENABLE

0

0

0

0

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0

0

0

0

0

0

0

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0

0

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..... EN 0

EN 1

EN 2

EN 3 0

0

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CLOCK

b) Output of a Segmented Gray counter

DFF

DFF

BIT 0

DFF

BIT 1

½ © > ¼ º Segmented Gray counter

DFF

BIT 2

BIT 3

½ © > »,º Binary counter using a D-Flip flop

2.2. Gray counter

] £ À ; © > M c © MWµ W µ< g¡ ¨ \ ;W ;cM§> >c © M ¡ 9M MW ¨ § : ¨ e§,£ M< >9MxM§ ;? «U³ § Á X ; © >) ¦T ¨ M£ ¡ ¨ CM§ LMa M e> Å ¡ £ Å ¡ ¨ § h ¨ >§ ' > L«x³ § M ,© ;MW h ¨ e§,£ x >µ? 'M µ< b ¥T ] © U "¡ ¨ L £ M§ © §f >>] > Wb X § µ<]<MM MW L«

3. Fault model and fault sensitivity analysis methodology ½T© ¦Tc¦ > <,W p> ¥ > ; #%;T > !© Y M ©T©W ©T 5 M#3! !© L « > M § 6 ; ,© ?©,! © > { ¨ § ]> !© >Y © >§ B¥ W« · s <)> !© £ W© ' MW M M ¢ l¡ ¨ ]> « ¿ § < ¦TL k § ¨ M§ M, > ! W© > 9,© bM M T W !© rÂ ¾ Äd« Æ ; 6M§ D ©T, ¨ M ; LM > !© « ²,µL C!© Y] WB 9> W !© § µ¦+ > ¡ ¡ tÂ Äd«]½ c>§ ¡ © ¡ ] M§ 9 © ¨ M © >§ kb c¡ M M ËÂ XÄ ¨ § p§|] p{?

Proceedings of the International Symposium on Quality Electronic Design (ISQED’02) 0-7695-1561-4/02 $17.00 © 2002 IEEE

³ § ?© ¦TL{ £ ¡T MMp § eMM m © e{ { £ >L ¡ M ¡ <> MM§ ;MWµ > >§ \ © e ¸ £ ¡ >W §e ? x;> M ML{§ D >MW e § \ : >µ< > 'ÂÃ #Ä ¹ «)Æ ; >6;< ¡T > e¶%M£ \ ¡ ] MW T M§ b; © > MWµ > M§ ; © ML § ©W ¦+ ¢< M © «"Æ ¨ ¥ ¹ ] ¨ ];>Mp9 g½© C© L ¦ z¸

BIT0 BIT0 BIT1 BIT1 . . . . BIT3

Logic to generate the bit for next state Similar for other bits

, 43S 43S 03254UT > WVXZY\[] ^ fb M© > 03254 _4 3S z ;> ¡ M } ;]

CLOCK

DFF

DFF

BIT 0

DFF

BIT 1

³ © £ M W > M > , § M W µ p ¨ T © ¡ © W, «s³ § #µL >. %Å ¨ U § M ¨ ' ½ < © ¾ «

DFF

BIT 2

BIT 3

½ © > ´º Implementation of a Gray counter M W M Wµ ]

INPUTS

] ® §

¨ § p§b> M © ; L;MW § s ;£ ¹ O ¸ « « ³ § sM W a ] ¦ 9 ; > ^ © ¡ > © >M Wµ ¦ rº

T « >§ x!© {] ch!© e>µ? W, ¦+ DMh;< ¡ >x ¨ z ?¡ ; © MbW ¡ £ MW L« ·UL; ¨ >¢ Â #Ä § \ § ¨ M§ )>§ !© e>µ? gW, s £ ¡T MMp B T,© ; M T W ¦+ ¡ >b D W6 c >§ ² ¿ © L« ]M>W' W >§ M<¦ ¦ e c½T © M ¸ ¹ ¦+ {¡ M ¡ kÂ Ä5«(³ § s Wµ ¦

+

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+

Ì

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03254 6 8 7 *Ç ; =< É:9 § > >/?!A >§ > Ç

M§

B Ì >@?!A C 7 É > ?!A 9 « Ç ; s µ<

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D IHKJLHM

Ì ¨ § > M§ ?© Y¦+" M L¸5» ¨ § p§z>§ W ©W MW ¨ <¡ >] ^> t µ< p ; T > l MW]6 ¨ § p§ !© ¨ > © ;<bc O!© U L;MW ; ¡ >]

PQ RO

103254

03254

J

¸!¼ ¹

£d¦ eC; © ML¹ < M§ ?© ¦TL M§ .© Y¦+ L> «rÇ >§ Wµ ¦

M§9 ^> M !© © ¡ © >§ ¨

1. Create a list of nodes

SPICE wirelist

Ì ¸ ¹ ¸ !#" $%&!(' ¹ ¸7Ã ¹ ¨ § > >§ ] , © w © >> *) É M§ ; L;MW MW]r; < © ;MW | Ê >§ zW > ¢ ) ¦ § ] sMWb;

¸5¾ ¹

> M© ¸Q´ ¹

2. Run SPICE simulations with fault at one node

Inputs (States)

OUTPUTS RELIABILITY

3. Repeat step 2 for various charge generated , inputs (states), time instances

Charge Generated Time instance of fault

( POF, FV ) POWER

4. Compare the outputs to detect errors.

½ <© > ¾,º Tool flow for measuring Reliability and Power

4. Improving fault tolerance of counters

`

,§ © MWµ © W MW s § ¨ M§ \M? TÅ ¨ ¸!½ £ > © ¾ ¹ ¨ LM ¡ >] ]© M§ ¦+#µs] MW ]!© e>µ? rW, bM§ hfÃ«i» °r±c² ¡ M, >« > § M § B M L L M c ; ®UW © LM x < ] £ ¨ > § W ¦ M !© Tr ¡ M g´ £d¦ B; © > > \ # µ > ? ² L µ « L;MW g Lµ p ¨ LM p b; £ ¨ > « ², © W MW > M© >§ {; © > ¨ M§ © ? ¡ MWbWª MW § ¨ ¦ Ã«

a

` © M À T Á X

± ½ «Ã «

b,

½ ^Ã » ?«

+ «

¨ « <¾» « ¼

³" ¦ Ãº Comparison of counter without any optimization ³ ¨ ¡ ¡ M § ¨ >s; T > Y CW ¡ >#µ. \!© M L ;k > § ; © M «½ :]M§ µ< µ £ ;< ¡ > > , © M§ 6 © >cM{ ¢<bM§ L

Proceedings of the International Symposium on Quality Electronic Design (ISQED’02) 0-7695-1561-4/02 $17.00 © 2002 IEEE

!© £5M L 1 « ³ § L ];>§ ?¢ O C> <]\ >§ 9¦ , ¢ > ¢ \M§B; © > !© M£>

«

RESET Error Detection Circuit

Counter data

Counter

4.1. Incorporating redundancy in the counters ¿ ~ L B¡ M d¸! M ¹D{> ¡ < 5¸ MW]^¹{> ,© £ ¡ ¡ W M ;W> © e{>t ¢fM§ L !© M£ M L «F® > M ,© ¦+ ¡ ¡ W M; © £ ML | µL t W ¡ > B¬)©T °' ,© p D·U ,© £ ¸!¬ °:·)¹ ¸½ <© M ¹f ³ > ¡ °' ,© p ·U ,© £ ¸!³ °:·¹ ¨ § > > © : © ML { M >§ ¥ © ¡ © a M§ ) >e µ> M§ ; © £ ML L« r '? ?¡ > M ,© £ ;> < C¡ ¨ `; T© ¡ > 6 < e¥+ {¸ ¦ ]9! ;M<a » ¼ ¹ «

ERROR Counter clock Counter load

OUT1

Counter LOAD DATA

OUT

with enable

Correct Data DATA

½ <© M ,º Architecture of time redundant counter ` © ML ® > · © À ³ WbB·U ,© T À ® M ·U ,© T ³ ]B· ,©

ERROR

CLOCK

2:1 MUX

Error Detection Circuit

2−1 MUX

Control Logic

CLOCK

CLOCK RESET

OUT Regi− ster

LOAD

³a?¡ T Á X Á X

¨ «WÃÃ^»¼ « »<» « « »¼

` © > ` © ML ` © ML ` © M

³" ¦ »,º Power comparison of area and time redundant counters

OUT2

Redundant Counter

4.2. Circuit-level fault tolerance ½ <© M

º

Architecture of area redundant (DMR)

counter ¡ > ¡ ]Mz ¡ < M 5/]I

M$#*,%$+4 >§ ; © M L«o³ § k¡ ¡ > § W]e § ¨ M}#µ>§ Mz> © ; h¡ ¨ ]; M© ¡ MW « ¿ © /;I

M$#*,%$#T >L§ W¯ © LM Y © ¡ © b >L ¡ © > 'g ML ¡ M>L#µ >¤> W !© « ½ © > WW© > M © `W ¡ ] MW >§ /;I

M$#*,%$#T ML§ W¯ © « ¬© > <M ¡ L MW >§ ; © Ma © ¡ © ` a M<M x ¦ > ML « ¿ LM> >§ ¡ MLµ.W ©TW £ M<M >M^µ W© ( < >M§ b; © M «³ § Y © ML) >§ : µ< ' ,¢DM M^;< ¡© M>§ ? > «O³ § < MW § ¨ >sM£ ¯ © > W© 9 ¦ M > © M ¡ ;, ; >M T W <6T ,¢ <p« ¨ a > µ DLM>B>L#µL f p ©T >> § ¦+ D ML;M «(³ § © >§ >L§ W¯ © \ s¡ ¡ > ¡ > M © M £ ¨ ¡ ¨ D ¨ ¡ L <M ; , M L« ½ !© M T MW]t> © rM^§,£ p ¯ © c ©M z ¦+#µB> M© \ Ã > ¦ «c³ § ¡ ¨ s; M© ] ¦ M§ W ¡ L] MW § ¨ ¦ » «

® © >(; c C bL] ] )¸/Å ¡ £ Å ¡ ¹ ¨ § p§D§ p >§ 9 © >> M\ >§ 9; © > p ¨ § p§ ;MLM] >§ . Ms¦ < >§ ¡ >;£ µ? © > « ²? Å ¡ £ Å ¡ >¦ ¦ c Lb M§ >gb<M e>µ<6>z> M§ M§ W < M « Æ ; ? MM ¡ gM}M < ; © MD; ¡ § © p{ M M<F>§ Å ¡ £ Å ¡«`®j³ T W (© p ³ £ § ¸!³ `³ ¹ ¡ M ¡ ÂeÃ<ÃÄ ¦+ ©T M W ¡ M#µ<`>§ !© aM ;s M§ Å ¡ £ Å ¡ § ; M§b © ML « ·U;W> © e\§ W¡ ¥ >> © )M§§ § >L¯ © > W L¸½ © M <¹ « ²?LµL ·Ukµ © ¨ LM § © m¸ { > ¾ £ » ¾ ¶T£ ¼ ¶a¹M xM§ ;¶%L;` ³ a³ ]!© £5M L ; ]¡ ¨ ¸!³" ¦ ¼ ¹ « ·U M© 6 § ¨ M§ ¨ e>§ ;> < { M ¡ e M§D> ¦ M§ g; © Mb ;> < B M§g M k¡ ¨ L ¸½ © M zmÃ ¹ «k³ § < MLM M ¦ e § ¨ LµL M © > ¦+ © Ã § 6?Q© >§ s> ; M )> M© e> ¡ ¨ U; « ®) >§ rM^§ p¯ © ¨ § p§j] §. ¡ >#µ. W ¡ >#µ;£ ] B z!© M£> M{ ;> < M§ Wª] M £ M< rÂeÃX»^Ä5« ¿ ;> < >§ Wª: M§ zM M<6>;£ ,© >§ e © b >§ ¶ ; ]µ b M§

Proceedings of the International Symposium on Quality Electronic Design (ISQED’02) 0-7695-1561-4/02 $17.00 © 2002 IEEE

.

.

.

+

0.075

Clk

0.07

Clk

Power consumed (in mW)

R,C

Clk R,C

Binary Counter Gray Counter

0.065 0.06 0.055 0.05 0.045 0.04 0.035

Clk

½ <© M

º Transient Pulse Tolerant Latch (TPTL)

± ½ «Ã «ÃX¾» «Ã ¼ «Ã « « » « .¾¼ « .¾»

b,

½ ^Ã » ?« Ã « ¼ « ,Ã« « #´« ´« »,«

+

+

+

¨ « <¾<» « <¾ « ¾ « ¼ « ¼ « ´<´ « <¾ Ã « Ã

³1 ¦ ¼º Comparison of counters using various resistance values

10 Resistance (in K−ohms)

15

20

Binary Counter Gray Counter 120 110 100 90 80 70

0

5

10 Resistance (in K−ohms)

15

>

M » 6«

` © M > À T » ´ > Á X » ´

± ½ «Ã «ÃL´ « « ´ « « .¾¾ « .» « Ã^¾

\+

b,

½ XÃ » ?« Ã<ÃÃ« ´«i» ¼<¼ « « « ¼ ¼ «i» » Ã« ¼

+

+

¨ « <¾<» « « » « « ¼ « <¾<¾ « » «

%+

³" ¦ ´º

Comparison of counters using various transistor sizes

·U M© B § ¨ >§ 9>§ > ¦ M§ D; © >9 £ ;> < ¨ M§B M ( M§ Wª( M§ `M T > . M§ b; ) M g¡ ¨ L ¸!½ © > YÃÃBhÃ^» ¹ «U® < e¥+ < M ¦ e <¦ >µ z M§ ªL M§\MMp T Lµ.p; M « ¿ M§ Wª Lµ?W Q© MM§ L M M ¦ e ¨ ¡ >#µY¦ © ce\b §. ;W C>9 M M§ ªLs M§ Lµ?W (¦T ¡ ¨ Ox ¦+ h M k W]e «:® ªL {! >Y ¦+ MM£ ] ¦ >§ ¡ ¨ B¦ ©T, YM§ , ML ¸ M§B;W> © e¹ «

130

Fault Vulnerability

5

½ <© > Ã º Effect of resistance on power

` © > M < À ¾ § Ã § » ¢§ <M Á X ¾ § Ã § » ¢§

60

0

20

+

½ © M º Effect of resistance on reliability M W M§ © ¡ >#µ M ¦ e <« ± Wr L> § § W T MWµ z § ©W ¦+}> ªL M| ¡ >#µ M§ !© M£> ¨ e>§ © \ ;> < >§ > x < ¥ £ <« `MMp T ¨ > Wª ¦ B! > 1» £ M§ L]¶+^ }!© £5M L ; l¡ ¨ ¨ b © W ¸!³" ¦ ´ ¹ «b³ § >L§ W¯ © ]> M© > fk > x¡ T

5. Conclusions and Future work ½ M<w>§ ¨ <M¢ ¨ ; W© ]M§ µ > ¨ £ ¡ ¨ L !© £5M ; < >L§ p¯ © s M f¸!½ © > Ã^¼ ¹ ] <© 6m #µ< ;£ < M^§ p¯ © a M>L¯ © W> M M M ¦+>§x¦ L>µ< © L ©MW«:® Y>§ >§e>L © > Lµ 5/]D M$#*,TI $+4 § © p ¦+h ¡ ¨ §>µL ¡ M W¦ f>mb£ ¡ >#µYM§ !© £5M L ; >§ , ML « ¿ ¨ \ § ¨ M§ \MWbb> ,© T U>L§ p¯ © T:© ¡ M© ] 6© ¡

Proceedings of the International Symposium on Quality Electronic Design (ISQED’02) 0-7695-1561-4/02 $17.00 © 2002 IEEE

© W MW ¨ W § ¡ ¢? M§ 'TW? 6 ¦ p ;W> © e «k³ ¡ > >§ ©T,f bb L T]Q© © M)ML§ M§ LM `9 M µ< ¡]!© ] p` W M M^§ «O®Up ? M§ © M £ ¨ ¡ ¨ M, > ; x!© M£ MWµ\b, £ < ;W © ]T § ;g] ¡ M bM ¡ > W] p © W ]e, £ ;W> © e «

140 Binary Counter Gray Counter

Fault Vulerability

120

100

80

60

³ § ¨ >¢ ¨ ©¡ ¡ <> Acknowledgment: ¡ U¦ ²?§ ¡ `< ¡ > «

40

20

1

2

3 4 Size (time original size)

5

6

6. References

½ <© > Ã<Ãº Effect of sizing on reliability

[1] Karaolis E., Nikolaidis MS., ((Goutis TdC.E., +“Fault !+Secure &(#^;;Binary

>;%> Counter #'Design,” M!;3@&Oin/ M*,/!3Y#%$+4X3dY3 , 1999, pp. 16591662.

0.1 Binary Counter Gray Counter

Power Consumed (in mW)

0.09

[2] Su C. L., Tsui C. Y. and Despain A. “Saving M^power >$#/?in -#3:the 7 control path Ma(t ;3e-of:embedded #%$:n;3(processors,” 7&CU %*,din 3 , 1994, pp. 24-31.

0.08 0.07

0.05

0.04 0.03

1

2

3 4 Size (times original size)

5

6

[6] Iyer R. and Rosetti D., load of CPU >L“A statistical $#/.-3Y7 vcnadependency &" errors at SLAC,” in , 1982.

0.085

6X Size

0.08

Binary Counter Gray Counter

6X Size

0.075

[7] Messenger G. C., “Collection charge junction M(a n of

M 3!on 9*3h # # nodes from ion tracks,” in %!+ , 1982, pp. 2024-2031.

0.07

10K Res

0.065 0.06 0.055

10K Res

[8] Laguna G. and Treece R. “VLSI M^>modeling $/.-3cand >((design ; ;for

I radiation environments,” in +!+&CL; M+6&(#) +*, ; Bb3e- , 1986, pp. 380-384.

Normal

0.05 0.045

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[4] Hakenes R. and Manoli Y., “A segmented Gray code Y 0 86 #for & lowpower microcontroller address buses,” in &(#^;; M+ , 1999, pp. 240-243. [5] Ball H. and Hardy F., “Effects and M^detection >$/.-& 3bof s 7\ &1intermitv@ tent failures in digital systems,” in A)v">`k#^;; >;%> , 1969, pp. 329-335.

½ © > Ã^»,º Effect of sizing on power

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[3] Mehta H., Owens R. M. and

M^>Irwin $/.-M. 3{7J.6“Some Teq <Q^=m [issues s Min Gray code T4#) addressing,” X3/*, "?in , 1996, pp. 178-181.

0.06

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[9] Singh M., Rachala R., and Koren I., “Transient Fault Sensitivity Analysis Converters (ADCs),” in Ma(| A' T# M*[##3Mof = Analog-to-Digital } "? , Apr. 2001, pp. 140145.

[10] Kang S. and Chu D., “CMOSMa circuit preven( design Td +for !the +# &(I tion of single event upset,” in ; M;%}&(#) +*, ; )b;3e- , 1986, pp. 385-388. [11] Cha H., and Patel J.H., “A Logic-Level s ML$#/?-#Model 37cMfor (( -Particle ; ; I Hits in CMOS Circuits,” in +!+`&(#^;; >;%>&CU %*,d \b;3e- , Oct 1993, pp. 538–542. [12] Singh M., and Koren I., “Reliability Enhancement >(( Td of+Analog!+# to-Digital Converters (ADCs),” in T4#) X3/*, 6;;s#+$v*,Z\nT O#? M#%9/

Proceedings of the International Symposium on Quality Electronic Design (ISQED’02) 0-7695-1561-4/02 $17.00 © 2002 IEEE

T4X3 ;3

, Oct. 2001.

Scientific American (March 2002)

Scientific American (March 2002)

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Mathematical Foundations of Computer Science 2002: 27th International Symposium, MFCS 2002, Warsaw, Poland, August 26-30, 2002. Proceedings

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Problems on algorithms (2002)

Problems on algorithms (2002)

Privacy Enhancing Technologies: Second International Workshop, Pet 2002, San Francisco, Ca, Usa, April 2002 : Revised Papers

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