$EMYSTIFYING#HIPMAKING
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$EMYSTIFYING#HIPMAKING
BY2ICHARD&9ANDA -ICHAEL(EYNE...
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$EMYSTIFYING #HIPMAKING
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$EMYSTIFYING #HIPMAKING
BY 2ICHARD & 9ANDA -ICHAEL (EYNES AND !NNE + -ILLER
.EWNES IS AN IMPRINT OF %LSEVIER #ORPORATE $RIVE 3UITE "URLINGTON -! 53! ,INACRE (OUSE *ORDAN (ILL /XFORD /8 $0 5+ #OPYRIGHT Ú %LSEVIER )NC !LL RIGHTS RESERVED .O PART OF THIS PUBLICATION MAY BE REPRODUCED STORED IN A RETRIEVAL SYSTEM OR TRANSMITTED IN ANY FORM OR BY ANY MEANS ELECTRONIC MECHANICAL PHOTOCOPYING RECORDING OR OTHERWISE WITHOUT THE PRIOR WRITTEN PERMISSION OF THE PUBLISHER 0ERMISSIONS MAY BE SOUGHT DIRECTLY FROM %LSEVIERS 3CIENCE 4ECHNOLOGY 2IGHTS $EPARTMENT IN /XFORD 5+ PHONE FAX E MAIL PERMISSIONS ELSEVIERCOMUK 9OU MAY ALSO COMPLETE YOUR REQUEST ON LINE VIA THE %LSEVIER HOMEPAGE HTTPELSEVIERCOM BY SELECTING h#USTOMER 3UPPORTv AND THEN h/BTAINING 0ERMISSIONSv 2ECOGNIZING THE IMPORTANCE OF PRESERVING WHAT HAS BEEN WRITTEN %LSEVIER PRINTS ITS BOOKS ON ACID FREE PAPER WHENEVER POSSIBLE ,IBRARY OF #ONGRESS #ATALOGING IN 0UBLICATION $ATA !PPLICATION SUBMITTED "RITISH ,IBRARY #ATALOGUING IN 0UBLICATION $ATA ! CATALOGUE RECORD FOR THIS BOOK IS AVAILABLE FROM THE "RITISH ,IBRARY )3". &OR INFORMATION ON ALL .EWNES PUBLICATIONS VISIT OUR 7EB SITE AT WWWBOOKSELSEVIERCOM 0RINTED IN THE 5NITED 3TATES OF !MERICA
Contents Foreword
........................................................................................................... xi... ............................................................................................. xiii
Acknowledgments
.............................................................................................. .................................................................................. . . Chapter 1: IC Fabrication Overview....................................................................... Section 1 : Introduction ...........................................................................................
About the Authors What’s on the CD-ROM?
1.1 Integrated Circuits .............................................................. 1.2 The Semiconductor Industry ...................... Section 2: Support Technologies
............................... ...............................
.............................................................................
xv
..
XVII
1 3
3 6 7
2.1 Crystal Growth and Wafer Preparation ......................................... . . 2.2 Contamination Control ...................................................... ............................... 8 2.3 Circuit Design and Mask Making .............. ............................. 10 2.4 Process Diagnostics and Metrology ...................................................................... 12 Section 3: Integrated Circuit Fabrication
...............................................................
3.1 Layering ................................................................................................................ 3.2 Patterning .............................................................................................................. 3.3 Doping .................................................................................................................. 3.4 Process Control and In-line Monitoring ............................................................... Section 4: Test and Assembly
................................................................................
4.1 Electrical Tests ..................................................................................................... 4.2 Die Separation ....................................................................................................... 4.3 Die Attach and Wire Bonding ............................................................................... 4.4 Encapsulation ........................................................................................................ 4.5 Final Test ............................................................................................................... Section 5: Summary .............................................................................................. Chapter 2: Support Technologies .........................................................................
......................................................................................... .........................................................................
Section 1 : Introduction . . Section 2: Contamination Control
2.1 Why Control Contamination? ............................................ ............................. ........................................... 2.2 Contamination Sources ..............................
V
13
13 18 21 22 25
25 25 25 26 26 27
29 31 33
33 35
Contents
2.3 The Cleanroom .................. ....................................................... Section 3: Crystal Growth and Preparation ...................................................... ......................................... ion .................................... ......................................... 3.3 Czochralski Silicon Growth ...................................................... 3.4 Shaping, Grinding. Cutting Polishing ......................... 3.5 Final Inspection and Shipping ............................... ......................................... Section 4: Circuit Design 4.1 Introduction ........................ ....................................................... 4.2 Product Definition and Ne duct Plan ......................... ......................................... 4.3 The Design Team ...................................................
.............................
.............................................
.....................................
4.4 The Design Process ................................................ ......................................... 4.5 Design Verification and Tapeout ........................................................................... Section 5: Photomask and Reticle Preparation...................................................... 5.1 Introduction ........................................................................................................... 5.2 Reticle Substrate Preparation ................................................................................ 5.3 Pattern Transfer ..................................................................................................... 5.4 Inspection and Defect Repair ................................................................................
................................................................................... ......................................................................................... .................................................................................... ..................................................................................
Chapter 3: Forming Wells
Section 1 : Introduction Section 2: Initial Oxidation Section 3: Photolithography 3.1 Introduction ........................ ....................................................... 3.2 Coat (Spin) ............. ...................................................... ............................. 3.3 Exposure (Step) ...................................................... ......................................... 3.4 Develop ..................................................... ..................................................... 3.5 After Develop Inspect (ADI) .......................................................... Section 4: Ion Implantation
................................................................................... Chapter 4: Isolate Active Areas (Shallow Trench Isolation) ..................................... Section 1: Introduction to Shallow Trench Isolation............................................... Section 2: Pad Oxide Growth ................................................................................ Section 3: Silicon Nitride Deposition ................................................................... Section 4: Photolithography for Photo/Etch........................................................ Section 5: Hard Mask Formation Using Plasma Etch ...........................................
41 42
47 49 53 55 57 59 59 59 60 61 63 65 71 79
a3 a4 87
93 95 99 101 105 107 5.1 Hard Mask Overview .......................................................................................... 107 109 5.2 Plasma Etch Overview ........................................................................................ 5.3 Etch Chemistry: Silicon Dioxide and Silicon Nitride ......................................... 114 Section 6: Form Trenches in Silicon with Plasma Etch.......................................... 119 Section 7: Fill Trenches with Silicon Dioxide ........................................................ 121 Section 8: Chemical Mechanical Polishing (CMP) to Remove Excess Dioxide .......123
vi
Contents Section 9:W e t Etch Removal o f Silicon N i t r i d e and Pad Oxide
............................ Chapter 5: Building the Transistors.................................................................... Section 1 : Introduction ....................................................................................... Section 2:Thin Film Formation ...........................................................................
......................................... 2.1 Gate Dielectric Oxidation .. 2.2 Polycrystalline Silicon (Poly) Deposition .................................................. 2.3 Nitride Cap Deposition ...................................................... Section 3: Poly Gate Formation........................................................................... ......................................... 3.1 Photoresist Patterning ........ 3.2 Plasma Etch .........................................................................................................
127 129 131 137 137
143 143 144 Section 4: Source/Drain Formation ..................................................................... 147 4.1 Introduction ......................................................................................................... 147 4.2 Shallow Implant .................................................................................................. 149 4.3 Spacer Formation ................................................................................................ 149 4.4 High-Dose Implant ............................................................................................. 151 4.5 Anneal ................................................................................................................. 151 .. Section 5: Salicide Formation .............................................................................. 153 5.1 Sputter Cobalt .................................................................................................... 155 5.2 RTP Reaction Forming Silicide .......................................................................... 155 5.3 Strip Residual Cobalt .......................................................................................... 156 156 5.4 Anneal the Silicide ..............................................................................................
.................................................................. ....................................................................................... ............................................................
Chapter 6: First Level Metallization Section 1 : Introduction Section 2: N i t r i d e and Oxide Depositions . . .. 2.1 Nitride Deposition .............................................................. ......................................... 2.2 Oxide Deposition ........................... Section 3: C M P Planarization Section 4:Photo/Etch for Contact Holes 4.1 Contact Hole Photolithography ......................................... ......................................... 4.2 Contact Etch ................................... Section 5:Tungsten Plug Process 5.1 Deposit Ti/TiN Barrier/Glue Layers ..........................................................
................
........................................................ ............................................................
164 167 169
........................................................
170 173
..........
5.2 Tungsten CVD .................................................................................................... 5.3 Tungsten CMP .................................................................................................... Section 6 : Low-lc Dielectric Process
157 159 163
.....................................................................
6.1 Deposit Low-k Dielectric Film ........................................................................... 6.2 Trench Photolithography and Etch ..................................................................... Section 7: Copper First Level Interconnection Process ......................................... 7.1 TdTaN Barrier Layer Deposition ....................................................................... 7.2 Sputter Copper (Cu) ............................................................................................
vii
174 176 177 177 180 183 183 185
Contents
7.3 Electroplate Copper (Cu) ......................................... ........................... 7.4 Copper CMP .......................................................................................................
........................... Section 1 : Introduction ....................................................................................... Section 2: Deposit Barrier Layer and lntermetal Dielectric ................................... Section 3: Dual Damascene Process ....................................................................
Chapter 8: Multilevel M e t a l Interconnects and Dual Damascene
3.1 Introduction ......................................................................................................... 3.2 Via Photo/Etch .................................................................................................... 3.3 Trench Photo/Etch ............................................................................................... 3.4 Deposit Barrier Layers ........................................................................................ 3.5 Sputter Copper .................................................................................................... 3.6 Electroplate Copper ............................................................................................ 3.7 CMP to Remove Excess Copper ......................................................................... 3.8 Deposit S i c Barrier Layer .................................................................................. 3.9 Build Additional Layers ......................................................................................
............................................................................ ....................................................................
Section 4: Form Bonding Pads Section 5: Final Passivation Process
185 186
i89 191 195 197
197 198 199 200 200 200 201 202 202 203 205
5.1 Deposit Final Passivation .................................................................................... 205 5.2 Photo/Etch for Bonding Pads .............................................................................. 205 Chapter 8: Test and Assembly
...........................................................................
....................................................................................... ......................................................................
Section 1 : Introduction Section 2: Wafer and Chip Testing
2.1 In-line Parametric Test ........................................................................................ 2.2 Wafer Sort (Probe) .............................................................................................. 2.3 Final Functional Test ...........................................................................................
.....................................................................
Section 3: Assembly and Packaging
3.1 Die Separation ..................................................................................................... 3.2 Die Attach and Bond Pad Connection ................................................................ 3.3 Encapsulation ......................................................................................................
207 209 211
211 212 213 215
215 216 218
........................................................................... Introduction ....................................................................................................... Section 1 : Atoms and Molecules .........................................................................
219
1.1 The Atom ............................................................................................................ 1.2 Molecules ............................................................................................................ 1.3 Organic Molecules ..............................................................................................
223 226 227
Appendix A: Science Overview
Section 2: Gases
.................................................................................................
2.1 Facts about Gases ................................................................................................ 2.2 Ions ...................................................................................................................... 2.3 Plasma ................................................................................................................. 2.4 Free Radicals .......................................................................................................
...
Vlll
221 223
229
229 230 230 231
Contents
2.5 Excited States ...................................................................................................... Section 3: Chemistry
...........................................................................................
...............................................................
3.3 Plasma Etch Chemistry ....................................................................................... Section 4: Solids
.................................................................................................
231 233
233 235 237
4.1 Conductors and Insulators . 4.2 Semiconductors .................. ........................................................................... 238 4.3 pn Junctions ........................................................................................................ 239
...............................................
241
5.1 Electric Charges and Fields 5.2 Electric Current ................................................................................................... 5.3 Magnetic Field ....................................................................................................
242 243
Section 5: Electricity, Electric and Magnetic Fields
Appendix B: Plasma Etch Supplement to Chapter 4 .............................................
......................................................................... .....................................................
Section 1 : Plasma Etcher Theory Section 2: Plasma Etch Process Requirements
Bibliography
....................................................................................................
Index ..............................................................................................................
245 247 249
251 253
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&OREWORD
7ELCOME 4HIS IS THE STORY OF HOW THE VAST MAJORITY OF INTEGRATED CIRCUITS ARE MADECALL THEM hCOMPUTER CHIPS v IF YOU LIKE ALTHOUGH A HOST OF OTHER ELECTRONIC COMPONENTS ARE MADE IN MUCH THE SAME WAY %VERYONE WHO IS CURIOUS ABOUT HOW SUCH TINY YET POWERFUL DEVICES ARE MADE WILL ENJOY THE STORY 4HIS BOOK WILL ALSO SERVE AS A VALUABLE UPDATE TO THOSE WHO MAY BE UNAWARE OF HOW DRASTICALLY THE STATE OF THE ART PROCESSES HAVE CHANGED IN RECENT YEARS 4HE MOST GLAMOROUS AND EXPENSIVE PART OF THE CHIPMAKING PROCESS IS THE FOCUS OF THIS BOOK ! CHIP WILL BE BUILT EACH STEP IS DESCRIBED IN ORDER UNTIL THE WHOLE CHIP IS COMPLETED FROM THE DESIGN PHASE TO GROWING THE SILICON INGOTS TO THE lNAL TESTING OF THE PACKAGED PART 4HE BUILDING OF A CHIP IS A FASCINATING PROCESS THAT WILL CERTAINLY IMPRESS AND ASTONISH EVERYONE WHO IS NEW TO THE STORY OR WHO IS OUT OF TOUCH WITH CURRENT PROCEDURES 2EAD ON
XI
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!CKNOWLEDGMENTS
4HE AUTHORS ARE VERY GRATEFUL TO THESE WONDERFUL FOLKS WHO HELPED MAKE THIS PROJECT A SUCCESS +ATY 9ANDA AND 2OBERT ,AIN OF 4 2AM 2OD 'ROSS AT 3TUDIO $AVID #RAVEN OF ,AM 2ESEARCH #ORPORATION 0ATTY #IMLOV :AHARES h!NOTHER !RTIST v AND +AREN -OORE AND THE ANALYSTS AT 6,3) 2ESEARCH
XIII
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!BOUT THE !UTHORS
2ICHARD & 9ANDA 2ICK 9ANDA IS A SENIOR INDUSTRY INSTRUCTOR WITH EXTENSIVE EXPERIENCE IN DEVELOPING AND DELIVERING SEMICONDUCTOR RELATED COURSES (E SERVED AS MANAGER AS THE 0ROCESS 4RAIN ING $EPARTMENT AT ,!- 2ESEARCH WHERE HE DEVELOPED THE DEPARTMENT CURRICULUM AND SERVED AS SENIOR TECHNICAL INSTRUCTOR !S FOUNDER OF 3EMICONDUCTOR 4ECHNOLOGY 4RAINING #ORP HE DEVELOPED SPECIALIZED INDUSTRY TRAINING COURSES %ARLIER IN HIS CAREER -R 9ANDA WAS SENIOR PROCESS ENGINEER AT !DVANCED -ICRO $EVICES #YPRESS 3EMICONDUCTOR AND ).-/3 #ORPORATION (E ALSO HELD THE POSITION OF SENIOR PROCESS ENGINEER AT ,AM 2ESEARCH AND -ATRIX )NTEGRATED 3YSTEMS -R 9ANDA HOLDS A "! IN 0HYSICS AND HAS COMPLETED NUMEROUS POST GRADUATE TECHNICAL COURSES -ICHAEL 32 (EYNES 0H $ $R (EYNES IS SENIOR ENGINEERSCIENTIST WITH BROAD SEMICONDUCTOR INDUSTRY EXPERIENCE PRIMARILY IN WAFER FABRICATION 3INCE $R (EYNES HAS BEEN DEVELOPING AND DELIVERING SEMICONDUCTOR RELATED COURSES (E WAS A SENIOR TECHNICAL INSTRUCTOR AT ,!- 2ESEARCH (E HAS WORKED EXTENSIVELY WITH 3EMICONDUCTOR 3ERVICES AS AN INSTRUCTOR AND COURSE DEVELOPER (E ALSO IN WRITES SCRIPTS FOR TRAINING VIDEOS IN THE AREA OF SEMICONDUCTOR MANUFACTURING AS WELL AS REVIEWS AND ADVISES ON CONTENT OF TECHNI CAL ARTICLES (IS INDUSTRY EXPERIENCE INCLUDES MANAGEMENT OF ENGINEERING GROUPS AND SMALL WAFER FABRICATION OPERATIONS $R (EYNES HOLDS A 0H$ IN 0HYSICAL #HEMISTRY !NNE + -ILLER !NNE -ILLER HAS BEEN MANAGING 3EMICONDUCTOR 3ERVICES SINCE 3HE IS RESPON SIBLE FOR TRAINING PRODUCT DEVELOPMENT AND ALSO PROVIDES TECHNICAL MARKETING SERVICES
XV
!BOUT THE !UTHORS TO SEMICONDUCTOR RELATED lRMS -S -ILLER HAD BEEN THE PRODUCT MARKETING MANAGER OF THE 7AFER )NSPECTION $IVISION OF +,! )NSTRUMENTS #ORPORATION "EFORE THAT SHE WAS THE PRODUCT MANAGER FOR THE 3EMICONDUCTOR %QUIPMENT $IVISION OF #AMBRIDGE )NSTRUMENTS !S ONE OF THE PIONEERS IN THE DEVELOPMENT OF PELLICLES -S -ILLER FOUNDED -ICROPEL A SUBSIDIARY OF %+# 4ECHNOLOGY /THER EXPERIENCE WAS GAINED AS A PROCESS ENGINEER AT )NTEL #ORPORATION AND PRODUCT DEVELOPMENT MANAGER AT *!3#/ #HEMICAL #ORPORATION "EFORE ENTERING THE SEMICONDUCTOR INDUSTRY -S -ILLER WAS A LECTURER IN THE #HEMISTRY $EPARTMENT AT 3AN *OSE 3TATE 5NIVERSITY 3HE HAS AN EXECUTIVE -"! FROM 3TANFORD 5NIVERSITY HOLDS A JUNIOR COLLEGE TEACHING CREDENTIAL IN INDUSTRIAL TECHNOLOGY SEVENTY POST GRADUATE UNITS IN "USINESS AND #HEMISTRY AND A "3 DEGREE IN #HEMISTRY -S -ILLER HAS BEEN A MEMBER OF h7HOS 7HO IN THE 7ESTv FOR MANY YEARS
XVI
7HATS ON THE #$ 2/-
4HE #$ CONTAINS LIVE FOOTAGE FROM LEADING CHIP MANUFACTURING FACILITIES )T IS THE PREVIEW FOR h-AKING THE -ICROCHIP!T THE ,IMITS )))v VIDEO TRAINING COURSE PRODUCED BY 3EMICONDUCTOR 3ERVICES IN 4HE VIDEO REmECTS CURRENT INTEGRATED MANUFACTURING TECHNOLOGY AND INCLUDES TOPICS SUCH AS SHALLOW TRENCH ISOLATION CHEM ICAL MECHANICAL PLANARIZATION LOW AND HIGH K DIELECTRICS AND THE DUAL DAMASCENE COPPER DEPOSITION PROCESS -ANY OF THE IMAGES USED IN $EMYSTIFYING #HIPMAKING ARE ALSO IN THE VIDEO )T IS POSSIBLE FOR READERS TO RENT OR PURCHASE THE VIDEO TRAINING COURSE FROM 3EMICONDUCTOR 3ERVICES AT WWWSEMICONDUCTORSERVICESCOM OR VIEW IT AT WWW3EMI:ONECOM
XVII
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#(!04%2
)# &ABRICATION /VERVIEW
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3%#4)/.
)NTRODUCTION #HAPTER CONTAINS A BRIEF SYNOPSIS OF THE DETAILED DISCUSSION TO COME )T SERVES AS AN ORIENTATION AND REFERENCE TO GIVE THE READER A SENSE OF THE BIG PICTURE AND HOW MUCH GOES INTO THE MAKING OF A hCHIPv
&IGURE %XAMPLE OF AN )NTEGRATED #IRCUIT -ICROPROCESSOR
)NTEGRATED #IRCUITS !N INTEGRATED CIRCUIT )# IS A MINIATURIZED ELECTRONIC DEVICE MADE BY COMBINING DISCRETE ELECTRONIC COMPONENTS INTO A SINGLE DEVICE ALL MANUFACTURED AS A WHOLE 4HE )# MAY CONTAIN MILLIONS OF TRANSISTORS DIODES RESISTORS CAPACITORS AND OTHER COMPO NENTS INTEGRATED INTO A SINGLE CHIP
#HAPTER )# &ABRICATION /VERVIEW 4ODAY THE TERM hCHIPv IS OFTEN THE FAVORITE NAME GIVEN TO )#S AND WILL BE USED EXTENSIVELY THROUGHOUT THIS DISCUSSION 4HE )# WAS ORIGINALLY CALLED THE MONOLITHIC INTEGRATED CIRCUIT h-ONOLITHICv MEANS hSINGLE STONE v REFERRING TO THE FACT THAT THE ENTIRE CIRCUIT IS BUILT ONAND INA SINGLE PIECE OF hSTONE v THE SEMICONDUCTING MATERIAL )N 2OBERT .OYCE ONE OF THE FOUNDERS OF )NTEL THEN AT &AIRCHILD 3EMICONDUC TOR AND *ACK +ILBY OF 4EXAS )NSTRUMENTS WERE JOINTLY AWARDED THE PATENT FOR THE )# EVEN THOUGH THEY DID THE WORK SEPARATELY AND AT DIFFERENT COMPANIES .OYCE BUILT HIS DEVICE ON SILICON AND +ILBY BUILT HIS ON GERMANIUM 4HE IMPORTANT DIFFERENCE IN THE TWO APPROACHES TO MAKING THE lRST )# WAS IN THE WAY THEY WERE WIRED TOGETHER +ILBY USED THERMO COMPRESSION WIRE BONDING TO CONNECT THE COMPONENTS .OYCE USED A PATTERNING PROCESS AND FORMED THE WIRES BY ETCHING A THIN ALUMINUM lLM ON THE SURFACE OF THE WAFER .OYCES TECHNIQUE BECAME THE STANDARD METHOD
&IGURE A +ILBYS &IRST )#
&IGURE B #OMMERCIAL 6ERSION OF 4) )#
&IGURE C &IRST )# 5SING 4HIN &ILM 7IRING .OYCE&AIRCHILD 3EMICONDUCTOR
)NTRODUCTION 3ILICON 3I THE SECOND MOST ABUNDANT ELEMENT ON EARTH IS THE MOST FAMILIAR SEMICONDUCTOR MATERIAL AS WELL AS THE MOST WIDELY USED 3ILICON TECHNOLOGY IS THE SUBJECT OF THIS BOOK 4HE VAST MAJORITY OF ALL THE )#S PRODUCED IN THE WORLD TODAY ARE MADE USING SILICON 'ERMANIUM 'E IS ANOTHER FAMILIAR SEMICONDUCTOR 4HE lRST TRANSISTOR WAS MADE OF GERMANIUM AND IT WAS THE PRINCIPLE MATERIAL USED FOR THE lRST DECADE OF THE INDUS TRY )T IS STILL IS OF INTEREST TODAY 3ILICON AND GERMANIUM ARE ELEMENTS BUT MANY SEMICONDUCTING MATERIALS ARE CHEMICAL COMPOUNDS FORMED BETWEEN TWO OR MORE CHEMICAL ELEMENTS .OT SURPRISINGLY THEY ARE CALLED COMPOUND SEMICONDUCTORS 'ALLIUM ARSENIDE 'A!S GALLIUM NITRIDE 'A. AND INDIUM PHOSPHIDE )N0 ARE EXAMPLES OF COMPOUND SEMI CONDUCTORS !LTHOUGH THEY ARE NOT AS WELL RECOGNIZED THEY PLAY A LARGE ROLE IN SEVERAL APPLICATIONS SUCH AS HIGH FREQUENCY DEVICES USED IN CELL PHONES AND IN OPTOELECTRON ICS MOST NOTABLY IN lBER OPTICS APPLICATIONS TELECOMMUNICATIONS APPLICATIONS USING GLASS lBERS INSTEAD OF COPPER WIRES #OMPOUND SEMICONDUCTORS ARE ALSO FOUND IN APPLICATIONS SUCH AS LIGHT EMITTING DIODES ,%$S WHICH ARE USED FOR TRAFlC LIGHTS THEY SAVE ENERGY AND REDUCE MAINTENANCE COSTS AS WELL AS PRODUCING MORE INTENSE LIGHT 3EMICONDUCTOR MATERIALS MAKE THE MAGIC HAPPEN FOR )#S 0URE SEMICONDUCTORS ARE NOT VERY GOOD CONDUCTORS OF ELECTRICITY (OWEVER THEY HAVE A QUITE HANDY PROPER TY THAT ALLOWS THEM TO BECOME RELATIVELY GOOD CONDUCTORS IF SPECIAL IMPURITIES CALLED DOPANTS ARE ADDED $OPED SEMICONDUCTORS POSSESS EITHER AN EXCESS OF MOBILE NEGA TIVE CHARGES N TYPE OR AN EXCESS OF APPARENTLY MOBILE POSITIVE CHARGES P TYPE DEPENDING ON THE TYPE OF DOPANT CHEMICAL THAT IS ADDED 4HE MOBILE CHARGES IN N TYPE MATERIAL ARE ELECTRONS 4HE MOBILE CHARGE IN A P TYPE CONDUCTOR IS CALLED A HOLE AND IT IS TREATED AS THOUGH IT WERE AN ACTUAL POSITIVE CHARGE CARRIER 4HE PHYSICS OF SEMICON DUCTOR DEVICES IS VERY INTERESTING AND THE READER WILL lND SOME GOOD SUGGESTIONS FOR FURTHER READING IN THE "IBLIOGRAPHY
#HAPTER )# &ABRICATION /VERVIEW
&IGURE 3EMICONDUCTOR )NDUSTRY 2EVENUE WITH #HIP &EATURE 3IZES
!LMOST ALL OF THE DEVICES MADE FROM SEMICONDUCTORS INCORPORATE ADJACENT N TYPE AND P TYPE REGIONS IN A VARIETY OF WAYS 4HE IMPORTANCE OF PUTTING THESE TWO OPPO SITELY DOPED REGIONS RIGHT NEXT TO EACH OTHER IS DISCUSSED EXTENSIVELY THROUGHOUT THE BOOK )N SHORT DIODES TRANSISTORS OF VARIOUS TYPES AND OTHER ELECTRICAL COMPONENTS ARE MADE IN THIS WAY
4HE 3EMICONDUCTOR )NDUSTRY 4HE SEMICONDUCTOR INDUSTRY BEGAN IN AT "ELL ,ABORATORIES IN -URRAY (ILL .* WITH THE INVENTION OF THE lRST TRANSISTOR !T THE TIME OF THIS WRITING THE INDUSTRY HAS GROWN TO GLOBAL PROPORTIONS WITH ANNUAL CHIP SALES EXCEEDING BILLION 4HE SEG MENT OF THE INDUSTRY THAT MAKES PROCESSING EQUIPMENT USED TO MANUFACTURE )#S IS ABOUT BILLION IN ANNUAL SALES 0RODUCTS INCLUDE )#S DIODES RECTIlERS AND TRANSISTORS MADE FROM SEMICONDUCTOR MATERIALS )#S ARE NOW FOUND IN TOASTERS LAMPS AUTOMOBILES AND MOST EVERY ELECTRICAL DEVICE /F COURSE COMPUTERS OFlCE EQUIPMENT COMMUNICATIONS DEFENSE AEROSPACE INDUSTRIAL CONTROL AND CONSUMER ELECTRONICS INDUSTRIES ARE DEPENDENT UPON THE SEMI CONDUCTOR INDUSTRY ,IGHT EMITTING DIODES ,%$S LASERS PHOTOVOLTAIC SOLAR CELLS MEASUREMENT AND SENSING DEVICES ARE ALSO PART OF THE SEMICONDUCTOR INDUSTRY
3%#4)/.
3UPPORT 4ECHNOLOGIES 4HE FOCUS OF THIS BOOK IS THE STORY OF HOW )#S ARE PRODUCED USING THE PRINCIPAL TECH NOLOGY EMPLOYED TODAY #-/3 (OWEVER THE COMPLEXITY OF THIS TECHNOLOGY REQUIRES THE SUPPORT OF OTHER EQUALLY SOPHISTICATED TECHNOLOGIES 4HE STORY WOULD NOT BE COM PLETE WITHOUT INCLUDING A DISCUSSION OF THESE FASCINATING TOPICS
#RYSTAL 'ROWTH AND 7AFER 0REPARATION 3INGLE CRYSTAL SILICON IS THE MATERIAL MOST COMMONLY USED IN THE FABRICATION OF INTE GRATED CIRCUITS 4HE SILICON IS PURIlED FROM A SURPRISINGLY FAMILIAR STARTING MATERIAL SAND -ANY SAND DEPOSITS ARE PRIMARILY SILICON DIOXIDE 4HE PREFERRED TYPES OF SAND CONTAIN VERY LOW LEVELS OF IMPURITIES 4HIS STARTING MATERIAL IS FURTHER PURIlED AND CHUNKS OF VERY PURE POLYCRYSTALLINE SILICON ARE EXTRACTED .EXT THE SILICON IS MELTED IN A LARGE QUARTZ GLASS CRUCIBLE 4HE FURNACE MUST REACH A TEMPERATURE OF AT LEAST # WHITE HEAT THE MELTING POINT OF SILICON ! SEED CRYSTAL IN THE FORM OF A SHORT ROD ABOUT THE SIZE OF A PENCIL WITH THE DESIRED ATOMIC ARRANGEMENT IS LOWERED TO TOUCH THE TOP OF THE MELT 3ILICON ATOMS ATTACH TO THE SEED CRYSTAL SLOWLY FREEZE AND PRECISELY REPLICATE THE ATOMIC ARRANGEMENT IN THE SEED 4HE RESULTING INGOT IS GRADUALLY PULLED UP AND OUT OF THE LIQUID MELT 4HE INGOT WILL OFTEN BE MM IN DIAMETER AND ONE OR TWO METERS LONG
#HAPTER )# &ABRICATION /VERVIEW
&IGURE 3ILICON )NGOT "EING 0ULLED FROM -ELT
4HE SILICON INGOT IS MACHINED ON SPECIAL TOOLS THAT PRODUCE A MORE PRECISELY SHAPED CYLINDER OF THE PROPER DIAMETER 4HEN THE INGOT IS CUT INTO THIN WAFERS USING A DIAMOND SAW 4HE WAFERS ARE POLISHED TO A MIRROR lNISH USING METHODS THAT MINIMIZE THE DAMAGE DONE TO THE CRYSTAL STRUCTURE AT THE SURFACE -OST SEMICONDUCTOR DEVICES USE ONLY A VERY SHALLOW LAYER OF THE SILICON AT THE WAFER SURFACE MAINTAINING GOOD CRYSTAL PROPERTIES IS IMPORTANT TO THEIR PERFORMANCE
#ONTAMINATION #ONTROL )NTEGRATED CIRCUITS MUST BE MANUFACTURED IN A CAREFULLY CONTROLLED ENVIRONMENT 4HE DEVICES ARE SO SMALL THAT EVEN A BACTERIUM CONTAMINATING THE SURFACE OF THE CHIP WOULD LIKELY CAUSE IT TO FAIL $UST PARTICLES MUCH SMALLER THAN THE EYE CAN SEE WILL PRODUCE hKILLERv DEFECTS 0ARTICLES CAN RESULT IN DEFECTS IN THE TINY PATTERNS FORMED IN BUILDING THE DEVICE STRUCTURES 0ARTICLES COULD ALSO BE A SOURCE OF TRACE CHEMICAL CON TAMINATION THAT MAY DAMAGE THE PRODUCT )#S ARE MADE IN CLEANROOMS OFTEN CALLED THE FABRICATION AREA OR FAB FOR SHORT #ONTAMINATION LEVELS ARE CLASSIlED IN TERMS OF THE NUMBER OF PARTICLES FOUND IN A CUBIC FOOT OF AIR THAT ARE MM OR MORE IN DIAMETER 4HE MM STANDS FOR MICROMETER OR MICRON FOR SHORT A UNIT OF MEASURE THAT IS ONE ONE THOUSANDTH OF A MILLIMETER IN LENGTH 4HE #LASS CLEANROOM COMMON TO THE INDUSTRY TODAY WILL ONLY HAVE ONE OF THOSE PARTICLES IN EACH CUBIC FOOT OF AIR #LASS AND #LASS CLEANROOMS ARE ALSO USEFUL FOR LESS DEMANDING TECHNOLOGIES
3UPPORT 4ECHNOLOGIES
&IGURE 4ABLE OF #LEANROOM #LASSES
&IGURE #LASS #LEANROOM
4HE CLEANLINESS IS MAINTAINED BY THE USE OF HIGH EFlCIENCY PARTICLE ATTENUATION (%0! lLTERS 5LTRA LOW PARTICLE ATTENUATION 5,0! lLTERS ARE ALSO USED 4HESE lLTERS ARE POSITIONED IN THE CEILING OF THE CLEANROOM OR IN THE CEILINGS OF SPECIAL ENVI RONMENTAL CHAMBERS THAT MUST BE KEPT CONTAMINATION FREE 4HE AIR MOVES DOWNWARD FROM THE lLTERS PRODUCING A LAMINAR mOW PATTERN THAT WILL CARRY ANY STRAY PARTICLES DOWNWARD THROUGH THE RETURN VENTS IN OR NEAR THE mOOR 4HE CLEANROOM SUIT OR hBUNNY SUITv IS CRITICAL TO KEEPING THE ENVIRONMENT CLEAN )T IS A COVERALL MADE OF NONPARTICULATING MATERIAL 4HE PEOPLE WORKING IN THE CLEANROOM ARE A MAJOR SOURCE OF PARTICLES SO A COMPLETE COVERALL MUST BE WORN %VEN MAKEUP IS FORBIDDEN BECAUSE IT PRODUCES A CONTINUOUS CLOUD OF PARTICLES EMITTED BY THE PERSON WEARING IT
#HAPTER )# &ABRICATION /VERVIEW 4HE WAFERS UPON WHICH THE CHIPS ARE MADE ARE KEPT IN CLOSED CONTAINERS DURING MOVEMENT BETWEEN MANUFACTURING STATIONS 4HE WAFERS ARE HELD IN SLOTTED CASSETTES CALLED BOATS WHICH KEEP THEM FROM TOUCHING EACH OTHER !UTOMATED ROBOTIC HAN DLERS ARE POPULAR TO MOVE WAFERS THROUGH THE FAB %ACH TOOL AND INSPECTION STATION IS EQUIPPED WITH VACUUM TRANSFER ARMS OR WANDS FOR HANDLING INDIVIDUAL WAFERS 4HE FRONT OF THE WAFER MUST NEVER BE TOUCHED EXCEPT FOR PROCESSING
#IRCUIT $ESIGN AND -ASK -AKING #HIP DESIGN BEGINS WITH A SCHEMATIC DIAGRAM OF THE DESIRED CIRCUIT 4HE SCHEMATIC IS TRANSLATED INTO A PICTURE OR hLAYOUTv OF THE ACTUAL CHIP DRAWN ON A COMPUTER AIDED DESIGN #!$ TOOL 4HE CHIP IS MANUFACTURED IN LAYERS THE OVERALL LAYOUT IS PAR TITIONED APPROPRIATELY BY THE DESIGN SOFTWARE %ACH LAYER IS A PATTERN THAT MUST BE REPRODUCED ON THE WAFER 4HESE PATTERNED LAYERS WHEN STACKED UP BECOME THE ELEC TRONIC COMPONENTS OF THE CHIP ALL WIRED TOGETHER 4HE INDIVIDUAL LAYER PATTERNS ARE TRANSFERRED TO THE CHIP USING A PHOTOLITHOGRAPHIC TECHNIQUE ! TEMPLATE CALLED A PHOTOMASK IS MADE FOR EACH LAYER 4HE PHOTOMASK IS A PICTURE OR PATTERN ETCHED IN CHROME ON A QUARTZ GLASS PLATE THAT ALLOWS LIGHT THROUGH IN SOME AREAS AND BLOCKS THE LIGHT ELSEWHERE !NOTHER FORM OF THE PATTERNED PLATE IS CALLED A RETICLE 7HEN LIGHT IS PROJECTED THROUGH THE PHOTOMASK OR RETICLE AND ONTO A PHOTOSENSITIVE MATERIAL CALLED PHOTORESIST RESIST COATING THE WAFER THE PATTERN FROM THE RETICLE WILL APPEAR IN THE PHOTOSENSITIVE MATERIAL AFTER TREATMENT WITH A DEVELOPER SOLUTION SEE 3ECTION %XPOSURE AND 3ECTION $EVELOP )N EFFECT THE PHO TORESIST COATED WAFER ACTS LIKE THE lLM IN A CAMERA 4HE RETICLES AND PHOTOMASKS ARE THEMSELVES MADE USING A SIMILAR PROCESS 4HE MASK MAKING COMPANY RECEIVES A COMPUTER lLE CONTAINING THE DESIGN FOR EACH PHO TOMASK OR RETICLE ! BLANK CHROME COATED QUARTZ PLATE IS COVERED WITH PHOTORESIST 4HEN THE PLATE IS PROCESSED IN A COMPUTER CONTROLLED ELECTRON BEAM E BEAM TOOL OR A LASER PATTERN GENERATOR THAT REPRODUCES THE DESIRED PATTERN IN THE PHOTORESIST $EVEL OPER SOLUTION REMOVES THE UNWANTED RESIST 4HE REMAINING RESIST SERVES AS THE TEMPLATE RESIST MASK FOR A WET ETCHING PROCESS TO REMOVE THE EXPOSED CHROME 7HEN THE PAT TERN IS REPRODUCED IN THE CHROME THE RESIST MASK CAN BE STRIPPED OFF AND THE CHROME MASK OR RETICLE IS COMPLETE 3TATE OF THE ART CHIPS REQUIRE TWENTY TO THIRTY SUCH MASKS 0HOTOMASKS ARE SOMETIMES CALLED MASKS FOR SHORT SO IT CAN BECOME CONFUSING #HAPTERS AND WILL CLARIFY THE TERMINOLOGY AND ELABORATE ON HOW THE VARIOUS MASKS ARE USED
3UPPORT 4ECHNOLOGIES
&IGURE %XPOSING A 7AFER 5SING 0HOTOMASK
&IGURE %XPOSING 7AFER 5SING A 2ETICLE
#HAPTER )# &ABRICATION /VERVIEW
0ROCESS $IAGNOSTICS AND -ETROLOGY 3TRICT DIMENSIONAL CONTROL IS CRITICAL TO PRODUCING STATE OF THE ART )#S -ANY OF THE DEVICES AVAILABLE TODAY TO MEASURE lLM THICKNESSES AND LINE WIDTHS ON THE CHIPS DID NOT EXIST EARLY IN THE HISTORY OF THE INDUSTRY )T IS NO EASY MATTER TO MEASURE THESE TINY DIMENSIONS 2$ WORK IS UNDERWAY FOR NM TECHNOLOGY THAT IS A CONDUCTING hWIREv ON THE CHIP THAT IS NM WIDE 4HE DIAMETER OF A HAIR IS TO NM #HAPTER 3ECTION HAS THE lRST OF SEVERAL HELPFUL HINTS FOUND THROUGHOUT THE BOOK REGARDING THE UNITS OF MEASURE COMMON TO THE INDUSTRY (ERE NM STANDS FOR NANOME TER OR ONE BILLIONTH OF A METER !FTER EACH CRITICAL MANUFACTURING STEP THE WAFERS ARE OFTEN INSPECTED $EFECTS CONTAMINATION PROCESSING OR OPERATOR ERRORS AND METROLOGY AND THE MEASUREMENT OF CRITICAL DIMENSIONS #$S AND lLM THICKNESSES ARE SOME OF THE ITEMS THAT ARE CHECKED AT EACH INSPECTION !UTOMATED INSPECTION STATIONS DO MUCH OF THE WORK TODAY 4HE DIMENSIONS OF FEATURES ON TODAYS CHIPS ARE SO SMALL THAT EVEN THE SOPHISTI CATED INSPECTION AND MEASUREMENT TOOLS DEVELOPED IN THE LAST TWENTY YEARS HAVE BEEN RENDERED AT LEAST PARTIALLY USELESS 3CANNING ELECTRON MICROSCOPES 3%- ARE REQUIRED TO SEE THE SMALLEST FEATURES BEING PRODUCED TODAY 3OME lLMS ARE SO THIN THAT EVEN CLASSICAL THIN lLM MEASURING INSTRUMENTS LIKE THE ELLIPSOMETER CAN BE INACCURATE "ROAD SPECTRUM REmECTROMETRY IS STILL USEFUL FOR lLM THICKNESSES BUT SOPHISTICATED NEW TECHNOLOGIES USING ELLIPSOMETRY ARE IMPROVING MONITORING AND MEASUREMENTS .EW 3%- TECHNOLOGY IS AUTOMATED AND MAKES THE SMALLEST MEASUREMENTS IN THE FAB
3%#4)/.
)NTEGRATED #IRCUIT &ABRICATION 4HE STORY OF BUILDING )#S BEGINS NOW
,AYERING 3EMICONDUCTOR DEVICES ARE BUILT IN LAYERS 7HILE MUCH OF THE CRITICAL ELECTRICAL ACTION OCCURS IN THE SILICON WAFER SUBSTRATE A GREAT DEAL OF THE CHIP BUILDING PROCESS INVOLVES THE LAYERING OF THIN lLMS OF VARIOUS SORTS ON THE SUBSTRATE 3INCE CHIPS ARE ELECTRICAL DEVICES IT IS NOT SURPRISING THAT LAYERS OF ELECTRICAL CONDUCTORS ARE SEPA RATED FROM EACH OTHER BY LAYERS OF ELECTRICAL INSULATORS 4HERE IS A LITTLE MORE INVOLVED IN BUILDING THE WHOLE DEVICE AS WILL BE SEEN LATER BUT THAT IS THE GENERAL THEME OF LAYERING 4HIN lLM DEPOSITION IS THE GENERAL NAME FOR THE TECHNOLOGY OF ADDING LAYERS OF VARIOUS MATERIALS TO THE WAFER ,AYERS ARE ALSO FORMED BY TECHNOLOGIES CALLED OXIDA TION AND EPITAXY )NSULATORS $IELECTRICS 3ILICON DIOXIDE OXIDE FOR SHORT THE PRINCIPLE COMPONENT OF GLASS IS THE MOST WIDELY USED INSULATOR IN THE INDUSTRY /THER CHEMICALS ARE SOMETIMES ADDED TO OXIDE TO MODIFY ITS PHYSICAL CHARACTERISTICS )NSULATORS ARE PART OF A MORE GENERAL CLASS OF MATERIALS CALLED DIELECTRICS $IELEC TRICS AS A CLASS OF MATERIALS HAVE A VARIETY OF PROPERTIES THAT HELP MAKE THE CHIP WORK BETTER 4HE TEXT DISCUSSES SEVERAL USES FOR THESE MATERIALS BESIDES THOSE OF ELECTRICAL IMPORTANCE
#HAPTER )# &ABRICATION /VERVIEW 4O IMPROVE CHIP SPEED SPECIAL DIELECTRICS ARE BEING DEVELOPED TO REPLACE THE OXIDE IN SOME AREAS OF THE CHIP 4HESE NEW MATERIALS ARE CALLED LOW K AND HIGH K DIELECTRICS 4HEIR USE IS DISCUSSED LATER IN THE TEXT %ARLY IN THE WAFER FABRICATION PROCESS HIGH TEMPERATURE PROCEDURES CAN BE USED 3IMPLY HEATING THE SILICON WAFER IN AN OXYGEN ATMOSPHERE ACTUALLY GROWS A COATING OF THERMAL OXIDE ALL OVER THE WAFER SOME OF THE SILICON IS CONSUMED BY REACTING WITH THE OXYGEN TO FORM SILICON DIOXIDE 4YPICALLY A TEMPERATURE OF TO # IS NEEDED FOR THE OXIDATION REACTION TO PROCEED 4HE DEVICES BEING MADE ON THE WAFER CANNOT WITHSTAND THAT HIGH OF A TEMPERATURE LATER ON IN THE PROCESS SO LOWER TEMPERATURE OP TIONS MUST BE USED #HEMICAL VAPOR DEPOSITION #6$ IS ONE OF THE PROCESSES OF DEPOSITING A lLM ON THE WAFER SURFACE 4HE TEMPERATURE CAN BE MUCH LOWER THAN THAT NEEDED FOR THERMAL OXIDATION !S ANOTHER EXAMPLE SOME LOW K DIELECTRICS ARE APPLIED IN LIQUID FORM USING A SPINNING CHUCK TO HOLD THE WAFER DEPOSITION IS FOLLOWED BY A CURING PROCESS AT TO # /THER METHODS OF LOW TEMPERATURE DEPOSITIONS ARE DISCUSSED IN THE TEXT
&IGURE #HEMICAL 6APOR $EPOSITION #6$
)NTEGRATED #IRCUIT &ABRICATION 3EMICONDUCTORS 3ILICON TECHNOLOGY IS THE TOPIC OF DISCUSSION FOR THIS BOOK 3ILICON IS USED IN TWO FORMS SINGLE CRYSTAL AND POLYCRYSTALLINE POLY 4HE THIRD FORM OF SILICON AMORPHOUS SILICON IS NOT TYPICALLY USED TO MAKE #-/3 DEVICES AND SO IT WILL NOT BE DISCUSSED IN THIS TEXT 4HE WAFER IS SINGLE CRYSTAL SILICON 4HE PRODUCTION OF THE SILICON INGOT AND THE WA FERS WAS DISCUSSED IN 3ECTION 3OME CHIP DESIGNS REQUIRE THAT THE DEVICE BE BUILT IN A THIN LAYER OF SINGLE CRYSTAL SILICON THAT IS GROWN ON TOP OF THE STARTING WAFER 4HAT TYPE OF lLM IS CALLED EPITAXIAL SILICON EPI AND IT IS GROWN IN AN EPITAXIAL REACTOR AT A HIGH TEMPERATURE 4HE EPI lLM IS AN EXTENSION OF THE UNDERLYING SILICON CRYSTAL 3ILICON CAN ALSO BE DEPOSITED ON THE WAFER USUALLY ON TOP OF A lLM OF SILICON DIOXIDE 0OLYCRYSTALLINE SILICON POLY FORMS AT TEMPERATURES ABOVE ABOUT # )T IS COMPOSED OF GRAINS OF SINGLE CRYSTAL SILICON ALL STUCK TOGETHER !T LOWER DEPOSITION TEMPERATURES THE CRYSTAL REGULARITY IS LOST AND THE SILICON BECOMES AMORPHOUS 3ILICON IN AN )# ALMOST ALWAYS NEEDS TO CONDUCT FAIRLY WELL SO IT WILL BE DOPED TO IMPROVE ITS CONDUCTIVITY $OPING IS DISCUSSED IN 3ECTION #ONDUCTORS #ONNECTING THE INDIVIDUAL ELECTRICAL COMPONENTS ON THE CHIP TOGETHER TO FORM A CIRCUIT IS DONE MOSTLY WITH METALS NOTABLY ALUMINUM COPPER AND TUNGSTEN BUT DOPED POLY AND SILICIDES ARE USED FOR SOME CONNECTIONS 3ILICIDES ARE CHEMICAL COMPOUNDS THAT CAN BE MADE BY REACTING SILICON AND CERTAIN METALS 4HESE SILICIDES CONDUCT QUITE WELL AND CAN WITHSTAND RELATIVELY HIGH PROCESS TEMPERATURES 0HYSICAL VAPOR DEPOSITION 06$ IS OFTEN THE METHOD FOR DEPOSITING METAL ON THE WAFER 4HE 06$ TOOL USES LARGE IONS ATTRACTED TO A TARGET BY AN ELECTRIC lELD 4HE TARGET IS MADE OF THE MATERIAL TO BE DEPOSITED ON THE WAFER 4HE BOMBARDING IONS EJECT ATOMS FROM THE TARGET 4HE ATOMS mY OFF THE TARGET SPUTTERING AND FORM A COATING ON THE WAFER /F COURSE THIS hBLANKETv COATING WILL HAVE TO BE FORMED INTO CONDUCTING WIRES IF USED FOR INTERCONNECTIONS AS DISCUSSED IN 3ECTION
#HAPTER )# &ABRICATION /VERVIEW
&IGURE 0HYSICAL 6APOR $EPOSITION 06$
! POPULAR METHOD OF DEPOSITING COPPER IS ELECTROPLATING ALSO CALLED ELECTRO CHEMICAL DEPOSITION %#$ 4HE WAFER IS IMMERSED IN A CHEMICAL SOLUTION CONTAINING COPPER SULPHATE ! COPPER PLATE IS ALSO IMMERSED IN THE SOLUTION AND WHEN AN ELEC TRIC CURRENT IS PASSED THROUGH THE SOLUTION BETWEEN THIS PLATE AND THE WAFER COPPER IS DEPOSITED ON THE WAFER
&IGURE %LECTROCHEMICAL $EPOSITION %#$
)NTEGRATED #IRCUIT &ABRICATION "ECAUSE OF THE DENSITY OF COMPONENTS ON THE )# MANY CRISSCROSSING LAYERS OF METAL INTERCONNECTS ARE NEEDED %ACH NEW LAYER IS INSULATED FROM THE PREVIOUS UNDER LYING ONE BY USING A DIELECTRIC MATERIAL (OLES ARE CUT IN THE DIELECTRIC AND lLLED WITH METAL TO MAKE THE ELECTRICAL CONNECTIONS BETWEEN LAYERS %IGHT LAYERS OF METAL ARE COMMON TODAY AND THE NUMBER IS INCREASING #HEMICAL -ECHANICAL 0OLISHING #HEMICAL MECHANICAL POLISHING #-0 WAS MENTIONED EARLIER AS THE METHOD USED TO POLISH NEWLY PRODUCED STARTING WAFERS )T ALSO HAS OTHER USES IN MAKING )#S 4HE OPTICAL TOOLS DISCUSSED IN 3ECTION USED TO TRANSFER THE PATTERN FROM THE RETICLE TO THE WAFER ARE CAPABLE OF PRINTING VERY TINY FEATURES ON THE WAFER "UT THE WAFER BECOMES TOO BUMPY RATHER EARLY IN THE PROCESS FOR GOOD PATTERN TRANSFER THE OPTICAL TOOL CANNOT FOCUS ON ALL POINTS ON THE WAFER 4HE WAFER MUST BE PLANARIZED FOR BEST RESULTS #-0 IS THE BEST TECHNOLOGY AVAILABLE FOR PLANARIZING THE SURFACE OF THE WAFER .EW PROCESSING METHODS AND THE USE OF COPPER HAVE ALSO REQUIRED THE USE OF #-0 4HE DUAL DAMASCENE PROCESS DISCUSSED IN THE TEXT REQUIRES THAT THE COPPER BE REMOVED BY POLISHING 4HE SHALLOW TRENCH ISOLATION TECHNOLOGY ALSO MUST USE #-0 TO REMOVE EXCESS OXIDE 3EVERAL EXAMPLES WILL BE DISCUSSED
&IGURE #HEMICAL -ECHANICAL 0OLISHING #-0
#HAPTER )# &ABRICATION /VERVIEW
0ATTERNING 4HE PATTERNING PROCESS TRANSFERS THE PATTERN FROM THE RETICLE OR PHOTOMASK TO THE WAFER USING PHOTOLITHOGRAPHIC TECHNOLOGY ! PHOTORESIST TEMPLATE ALSO COMMONLY CALLED A MASK JUST TO CONFUSE EVERYONE IS PRODUCED ON THE WAFER SURFACE THAT IS A DUPLICATE OF THE PATTERN ON THE RETICLE /NE OF TWO FUNCTIONS IS PERFORMED BY THIS TEM PLATE IT IS USED TO PROTECT PARTS OF THE WAFER FROM CHEMICAL ATTACK DURING AN ETCHING PROCESS OR TO BLOCK THE IMPLANTATION OF DOPANTS FROM THE COVERED AREAS 4HE USE OF PHOTOLITHOGRAPHIC TECHNIQUES IS ALSO DISCUSSED IN 3ECTION 0HOTORESIST #OAT 0HOTORESIST RESIST IS A LIGHT SENSITIVE PLASTIC MATERIAL THAT IS lRST DISPENSED IN THE FORM OF A SOLUTION 4HE WAFER IS POSITIONED ON A HOLDER OR hCHUCKv THAT HOLDS IT IN PLACE WITH A VACUUM WHILE THE CHUCK SPINS 4HE RESIST IS APPLIED TO THE WAFER BY DISPENSING A SMALL AMOUNT OF THE THICK STICKY LIQUID ONTO THE CENTER OF THE WAFER 4HE SPINNING THROWS OFF EXCESS RESIST AND HELPS TO DETERMINE THE THICKNESS OF THE RESIST lLM A HIGHER SPIN SPEED WILL DRIVE OFF MORE RESIST AND LEAVE A THINNER lLM BEHIND /THER FACTORS SUCH AS THE VISCOSITY OF THE RESIST CONTRIBUTE STRONGLY TO THE lLM THICKNESS ! SOFT BAKE AT ABOUT # DRIVES OFF MOST OF THE SOLVENT 4HE RESIST IS STABILIZED SOLIDIlED BY THE BAKE AND THE PHOTOSENSITIVITY AND SOLUBILITY IN DEVELOPER SOLUTION ARE INmUENCED TOO
&IGURE 0HOTORESIST $ISPENSE
)NTEGRATED #IRCUIT &ABRICATION %XPOSURE -OST EXPOSURE OPERATIONS ARE DONE IN A STEPPER 4HIS TOOL HOLDS THE RETICLE AND PROJ ECTS LIGHT THROUGH IT 4HE RESIST IS SENSITIVE TO ULTRAVIOLET 56 LIGHT 4HE AREAS EXPOSED TO 56 WILL DISSOLVE IN THE DEVELOPER SOLUTION 4HE UNEXPOSED AREAS ARE LEFT BEHIND AND FORM A TEMPLATE OR MASK ON THE WAFER 4HE NAME hSTEPPERv IS SHORT FOR THE FORMAL NAME OF THE TECHNOLOGY STEP AND RE PEAT REDUCTION PROJECTION PRINTING 3TEP AND SCAN IS ALSO A COMMON TECHNOLOGY FOUND IN THE FAB TODAY 4HE IMAGE ON THE RETICLE IS REDUCED IN SIZE BY LENSES -OST REDUCTION SYSTEMS IN USE TODAY ARE ¾THAT IS THEY REDUCE THE IMAGE TO OF ITS ORIGINAL SIZE ON THE RETICLE 4HE STEP AND REPEAT OR STEP AND SCAN DESCRIBES HOW THE TOOL EXPOSES THE WAFER 3INCE THE IMAGE IS REDUCED IN SIZE ONLY A SMALL PORTION OF THE WAFER CAN BE EXPOSED AT A TIME 4HE WAFER MUST BE MOVED OR STEPPED AFTER EACH EXPOSURE 4HE WAFER IS EXPOSED hSTEP WISEv UNTIL THE PATTERN HAS BEEN TRANSFERRED TO THE WHOLE USABLE SURFACE
&IGURE 0HOTORESIST %XPOSURE 5SING 3TEPPER
$EVELOP 4HE EXPOSED WAFER IS POSITIONED ON ANOTHER SPINNING VACUUM CHUCK BUT THIS TIME A DEVELOPER SOLUTION IS SPRAYED ON IT 4HE EXPOSED RESIST DISSOLVES LEAVING THE RESIST TEMPLATE MASK BEHIND
#HAPTER )# &ABRICATION /VERVIEW 0ATTERN )NSPECTION )F AN ERROR IN PROCESSING HAS CREATED ANY IMPERFECTIONS IN THE PHOTORESIST IMAGE IT CAN BE STRIPPED OFF AND REWORKED .OW IS THE TIME TO lND ANY PROBLEMS BECAUSE THE NEXT PROCESSING STEPS WILL PERMANENTLY TRANSFER THE PATTERN TO THE WAFER )MPERFECTIONS COULD RESULT IN SCRAPPING MANY WAFERS !UTOMATED INSPECTION TOOLS CHECK THE PATTERN FOR DEFECTS AND MEASURE IMPORTANT FEATURE SIZES CALLED CRITICAL DIMENSIONS TO MONITOR THE QUALITY OF THE PRODUCT %TCH -OST OF THE MASKING STEPS ARE FOLLOWED BY AN ETCHING STEP 0LASMA ETCH IS THE DOMI NANT TECHNOLOGY FOR PERMANENTLY TRANSFERRING THE RESIST MASK INTO THE lLM OR lLMS BELOW 4HE WAFER ENTERS AN EVACUATED CHAMBER ! GAS IS INTRODUCED AND ELECTRICALLY CHARGED IONIZED TO CHANGE IT INTO A PLASMA 4HE PLASMA IS HIGHLY REACTIVE AND ALLOWS BETTER CONTROL OF THE FEATURE SHAPES AND DIMENSIONS THAN THE WET ETCH METHOD 0LASMA %TCHERS 4ECHNICALLY PLASMA ETCH REACTORS ONLY MAKE A SMALL AMOUNT OF THE INJECTED GAS INTO A PLASMA 4YPICALLY LESS THAN OF THE GAS PARTICLES ARE IONIZED AT ANY ONE TIME (OWEVER AS DISCUSSED IN #HAPTER THAT IS ALL THAT IS NEEDED TO GET THE JOB DONE
&IGURE 0LASMA %TCH
)NTEGRATED #IRCUIT &ABRICATION )MPLANT 3OME STEPS IN THE PROCESS USE THE RESIST MASK AS A PROTECTIVE TEMPLATE TO PERMIT DOPANT SPECIES TO ENTER ONLY SELECTED AREAS 4HIS IMPLANT MASK IS NEEDED WHEN AN IMPLANTER IS USED TO DOPE THE WAFER !N IMPLANTER IS A PARTICLE BEAM MACHINE THAT AC CELERATES DOPANT IONS AND DRIVES THEM INTO THE WAFER )T IS ALSO COMMON TO ETCH THE REQUIRED IMPLANT MASKING TEMPLATE INTO A PROTEC TIVE lLM OFTEN A DIELECTRIC THAT IS DEPOSITED ON TOP OF THE MATERIAL TO BE DOPED )N THIS CASE THE PROCESS LOOKS JUST LIKE ANY OTHER PHOTOETCH STEP WITH THE WAFER GOING TO IMPLANT AFTER THE ETCH SEQUENCE 3ECTION WILL COVER MORE ON DOPING 0HOTORESIST 3TRIP 7HEN THE RESIST MASK IS NO LONGER NEEDED IT IS REMOVED OFTEN BY ETCHING IT OFF IN AN OXYGEN PLASMA THE RESIST IS SIMPLY BURNED OFF OR THROUGH THE USE OF A LIQUID STRIPPER %TCH )NSPECT 4HE FEATURES THAT WERE JUST PRODUCED ON THE WAFER ARE INSPECTED AND CRITICAL DIMEN SIONS MEASURED $EFECTS FOUND AT THIS POINT OFTEN REQUIRE THE AFFECTED WAFERS TO BE SCRAPPED 4HE WAFER IS NOW READY TO HAVE ANOTHER THIN lLM DEPOSITED SO IT CAN RETURN TO PAT TERNING FOR THE COMPLETION OF ANOTHER LAYER 4HE WAFER LOOPS THROUGH THESE STEPS UNTIL THE DEVICE IS COMPLETE
$OPING $OPANTS ARE INTRODUCED TO ALTER THE ELECTRICAL CONDUCTIVITY OF THE DOPED REGION 4HEY CAN BE ADDED TO THE WAFER IN A VARIETY OF WAYS 4HE DOPANT IS ADDED TO THE SILICON MELT AT CRYSTAL GROWTH SO THE SILICON INGOT IS EITHER N OR P TYPE 4HE CHEMISTRY USED TO PRODUCE EPITAXIAL SILICON WILL USUALLY INCLUDE DOPANT SPECIES 4HE WAFER CAN BE DOPED SIMPLY BY PUTTING IT IN A FURNACE AND INTRODUCING THE DOPANT IN GAS FORM 4ODAY ALMOST ALL OF THE DOPING OF STATE OF THE ART )#S IS DONE BY IMPLANTING THE DOPANT USING A PARTICLE BEAM MACHINE CALLED AN ION IMPLANTER !S MENTIONED ABOVE THE IMPLANTER ACCELERATES IONS DOWN A LONG TUBE AND DRIVES THEM INTO THE WAFER 4HE
#HAPTER )# &ABRICATION /VERVIEW DOPANT ENTERS THE WAFER WHEREVER THE IMPLANT MASK HAS AN OPENING 4HIS METHOD AL LOWS GREAT PRECISION IN THE PLACEMENT OF DOPANT AS WELL AS ITS CONCENTRATION OR hDOSEv )T IS THE DOPED REGIONS THAT FORM CRITICAL SECTIONS OF -/3 TRANSISTORS THAT WILL BE DIS CUSSED IN DETAIL IN THE TEXT
&IGURE )ON )MPLANTATION $OPING
0ROCESS #ONTROL AND )N LINE -ONITORING 0RODUCTION LINES MUST BE CONSTANTLY MONITORED IN AN ATTEMPT TO PREVENT COSTLY MISPRO CESSING 3TATISTICAL PROCESS CONTROL 30# IS THE BEST METHOD FOR REAL TIME MONITORING OF A MANUFACTURING LINE 30# CHARTS ARE UPDATED CONTINUALLY AS EACH INSPECTION IS COMPLETED 4HE CHART PROVIDES SIGNALS OF A DRIFTING PROCESS AND OFTEN PREVENTS EXPEN SIVE PRODUCTION ERRORS
)NTEGRATED #IRCUIT &ABRICATION
+,! 4ENCOR
&IGURE 3TATISTICAL 0ROCESS #ONTROL #HART
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4EST AND !SSEMBLY 4HE COMPLETED WAFERS ARE READY TO BECOME INDIVIDUAL PACKAGED PARTS IF THEY PASS ELECTRICAL TESTS
%LECTRICAL 4ESTS 4WO TYPES OF ELECTRICAL TESTS ARE DONE WHILE THE WAFERS ARE STILL WHOLE &IRST SEVERAL DOZEN BASIC MEASUREMENTS CALLED PARAMETRIC TESTS ARE MADE ON INDIVIDUAL TRANSISTORS AND OTHER TEST STRUCTURES IN TEST PATTERNS ON THE WAFERS 4HIS IS THE lRST CHECK ON PROPER FABRICATION 4HE SECOND TEST IS A CIRCUIT FUNCTION TEST %ACH CHIP IS TESTED WITH A PROBE THAT HAS MANY TINY ELECTRODES ! COMPUTERIZED SYSTEM PERFORMS MANY TESTS ON THE CHIP AND COLLECTS STATISTICAL DATA ON THE PRODUCT 4HE TEST SYSTEM KEEPS A MAP OF PASSED AND FAILED DIE ON EVERY WAFER &AILED DIE ARE OFTEN MARKED WITH AN INK DOT OR hINKED OUTv
$IE 3EPARATION 4HE CHIPS ARE ALSO CALLED DIE DISCUSSED IN #HAPTER 4HE TESTED WAFERS ARE hDICEDv BY PUTTING EACH WAFER ON AN ADHESIVE HOLDER AND CUTTING THE CHIPS APART WITH A DIAMOND SAW
$IE !TTACH AND 7IRE "ONDING 4HE GOOD DIE ARE REMOVED FROM THE ADHESIVE AND ATTACHED TO A CHIP PACKAGE 4HE DUAL INLINE PACKAGE IS THE MOST COMMON AND CONTAINS A LEAD FRAME TO WHICH THE CHIP IS AT TACHED 4HE LEAD FRAME IS A MOUNTING THAT HAS THE APPROPRIATE NUMBER AND CONlGURATION OF CONTACTS OR hLEADSv TO ATTACH TO OTHER ELECTRICAL DEVICES CIRCUIT BOARDS AND THE LIKE
#HAPTER )# &ABRICATION /VERVIEW 4HE CHIP ITSELF IS ATTACHED TO THE LEAD FRAME USING SPECIAL SOLDER SUCH AS GOLD GERMANIUM ALLOY OR EPOXY 4HEN THE TINY GOLD OR ALUMINUM WIRES THAT CONNECT TO THE BONDING PADS ON THE CHIP ARE ATTACHED USING SPECIAL TECHNIQUES THAT DO NOT DAMAGE THE PADS
%NCAPSULATION %NCAPSULATION IS THE PROCESS OF PUTTING THE CHIPS INTO PROTECTIVE PACKAGES -ANY PACK AGES ARE AVAILABLE FOR CHIPS 4HE INTENDED USE OF THE PART IS KEY IN DECIDING HOW TO ENCAPSULATE IT -ILITARY HARDWARE IS EXPOSED TO HARSH ENVIRONMENTS SO TOUGH PACKAG ING IS USED 3IMPLE PLASTIC PACKAGES SUCH AS THE DUAL INLINE PACKAGE SUFlCE FOR MANY CHIPS -ETAL CERAMIC AND COMPOSITE PACKAGING MATERIAL ARE ALL USED
&INAL 4EST 4HE PACKAGED PARTS RECEIVE A FUNCTIONAL TEST SIMILAR TO THAT GIVEN EARLIER TO THE DIE ON THE WAFERS BUT IT IS USUALLY MORE EXTENSIVE SINCE MANY PRODUCTS CANNOT BE TESTED AT FULL SPEED OR POWER UNTIL lNAL ASSEMBLY IS COMPLETE 4HE PARTS ARE NOW READY FOR SHIPPING TO STORES OR CUSTOMERS
3%#4)/.
3UMMARY #HAPTER SUMMARIZED THE COMPONENTS OF )# PRODUCTION #HAPTER BEGINS THE STORY OF BUILDING A CHIP FROM THE GROUND UP )N #HAPTERS THROUGH THE READER WILL ACTU ALLY BUILD A CHIP lGURATIVELY SPEAKING TAKING THE WAFERS THROUGH THE ENTIRE PROCESS WATCHING EACH COMPONENT OF THE CHIP COME TOGETHER
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#(!04%2
3UPPORT 4ECHNOLOGIES
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)NTRODUCTION )N #HAPTER YOU WILL LEARN v 7HAT ARE SUPPORT TECHNOLOGIES v (OW THE MANUFACTURING ENVIRONMENT IS KEPT CLEAN v (OW SILICON WAFERS ARE MADE v (OW AN INTEGRATED CIRCUIT IS DESIGNED v (OW THE CHIP DESIGN IS TRANSFERRED TO THE MANUFACTURING LINE $ElNITION 3UPPORT 4ECHNOLOGIES ARE THE ANCILLARY OR SUPPORT OPERATIONS THAT ARE CRITI CAL TO THE INTEGRATED CIRCUIT MANUFACTURING PROCESS #HAPTER 3ELECTION OF 4OPICS 4O SIMPLIFY THE ORGANIZATION OF THIS TEXT SOME TOPICS ARE INCLUDED IN THE SUPPORT TECHNOLOGIES CHAPTER EVEN THOUGH THEY ARE NOT TECHNICALLY PROVIDING SUPPORT TO THE MANUFACTURING PROCESS BUT ARE RATHER A PRINCIPAL PART OF IT 4HE REASON FOR THAT CHOICE IS TO REINFORCE THE FOCUS OF THIS BOOK WHICH IS THE ACTUAL FABRICATION OF THE INTEGRATED CIRCUITS 3O EVEN THOUGH THE CHIP COULD NEVER BE MANUFACTURED WITHOUT lRST BEING DESIGNED THE DISCUSSION OF THE DESIGN PROCESS IS FOUND IN #HAPTER
4HE PRINCIPAL SUPPORT TECHNOLOGIES TO BE ADDRESSED ARE AS FOLLOWS #ONTAMINATION CONTROL 3ILICON WAFER MANUFACTURING #IRCUIT DESIGN 0HOTOMASKRETICLE MANUFACTURING
#HAPTER 3UPPORT 4ECHNOLOGIES #ONTAMINATION CONTROL WILL BEGIN THE DISCUSSION OF THIS CHAPTER 4HE CHIPMAK ING ENVIRONMENT IS SO SENSITIVE TO CONTAMINATION THAT EVEN THE MACHINERY USED IN THE PROCESS MUST MANUFACTURED IN A CLEANROOM 4HE WAFERS THAT ARE MANUFACTURED FROM SILICON INGOTS MUST BE EXTREMELY CLEAN BEFORE THEY CAN ENTER THE CLEANROOM %VEN THE CHEMICALS USED IN THE PROCESS MUST BE OF THE HIGHEST POSSIBLE PURITY AND BE NEARLY FREE OF PARTICLES -ANUFACTURING THE WAFERS IS A HIGHLY SOPHISTICATED PROCESS 3TATE OF THE ART FABS USE MM INCH DIAMETER WAFERSAS BIG AS A DINNER PLATE 4HE INGOTS OF SILICON PRODUCED TODAY ARE OFTEN ONE METER LONG AND WEIGH CLOSE TO KG POUNDS )# DESIGN IS THE ONLY OPERATION DISCUSSED HERE THAT DOES NOT NEED TO BE DONE IN A CLEANROOM "UT THE PHOTOMASKS PRODUCED FROM THE DESIGN ARE MADE IN AN ULTRA CLEAN ENVIRONMENT !NOTHER TOPIC OF IMPORTANCE TO THE BUILDING OF )#S IS PROCESS DIAGNOSTICS INTRODUCED IN #HAPTER #RITICAL DIMENSION MEASUREMENTS lLM THICKNESSES DEFECT IDENTIlCATION PARTICLE COUNTING AND OTHER MEASUREMENTS ARE INDISPENSABLE TO THE PROCESS 4HERE ARE MANY MANY TECHNOLOGIES THAT ARE PUT TO WORK TO DO THE JOBSO MANY IN FACT THAT TO DO JUSTICE TO THE TOPIC WOULD LEAD THE DISCUSSION FAR AWAY FROM THE FOCUS OF THIS BOOK 4HE READER IS INVITED TO READ ABOUT METROLOGY SEPARATELY 4HE BIBLIOGRAPHY CONTAINS MANY HELPFUL REFERENCES THAT WILL SERVE AS A STARTING POINT
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#ONTAMINATION #ONTROL 7HY #ONTROL #ONTAMINATION /NE OF THE MOST AMAZING THINGS ABOUT STATE OF THE ART )#S IS HOW SMALL THE FEATURES ARE ON THE CHIP &EATURES INCLUDE CONDUCTING LINES HOLES MADE IN INSULATORS AND OTHER STRUCTURES THAT ARE EASILY IDENTIlABLE UNDER A MICROSCOPE )T IS BECOMING VERY DIFl CULT TO MAKE MEANINGFUL SIZE COMPARISONS 4HE PREFERRED EXAMPLE THAT HAS BEEN USED FOR YEARS IS THE DIAMETER OF A HUMAN HAIR 4YPICALLY A lNE HAIR IS ABOUT MICRONS MICROMETERS IN DIAMETER AND A COARSE HAIR WILL BE ABOUT MICRONS IN DIAMETER 7HEN THE CONDUCTING WIRES OR OTHER FEATURES ON THE CHIP WERE ONE MICRON WIDE OR EVEN ONE HALF MICRON WIDE ONE COULD STILL GET ORIENTED 4HE FEATURE SIZES IN THE CHIPS ARE DROPPING BELOW ONE TENTH OF A MICRON /PTICAL MICROSCOPES ARE HEAVILY RELIED UPON IN THE FAB BUT WHEN FEATURE SIZES DROP MUCH
&IGURE 7AFER EXPOSED TO !IR /UTSIDE #LEANROOM
#HAPTER 3UPPORT 4ECHNOLOGIES BELOW ONE MICRON THEIR USEFULNESS IS LIMITED 3O THE SMALLEST FEATURES ON THE CHIP ARE EFFECTIVELY INVISIBLE TO AN OPTICAL MICROSCOPE 4HE SCANNING ELECTRON MICROSCOPE 3%- IS QUITE COMMON BECAUSE IT IS INDISPENSABLE IN TODAYS MANUFACTURING ENVIRON MENT ! 3%- IS NEEDED TO ACTUALLY SEE THE SMALLEST FEATURES ON THE CHIP (ERE IS AN EXAMPLE NM TECHNOLOGY CAN lT MILLION TRANSISTORS IN THE SPACE THAT IS ROUGHLY THE SIZE OF THE TIP OF A BALLPOINT PEN )T SEEMS THAT TECHNOLOGY HAS EXCEEDED THE ABILITY TO CONNECT IT TO THE hREALv WORLD 4INY $IMENSIONS )T IS BECOMING VERY DIFlCULT TO RELATE THE FEATURE SIZES ON A CHIP TO EVERYDAY EX PERIENCE ! HUMAN EGG IS MICRONS ACROSSHUGE COMPARED TO A FEATURE ON A STATE OF THE ART CHIP %VEN A SPERM IS COMPARATIVELY LARGE ABOUT MICRONS IN DIAMETER AT THE HEAD ! TYPICAL BACTERIUM IS MICRONS IN DIAMETER 4HATS STILL AWFULLY LARGE BUT GETTING CLOSE 3HIFTING TO VIRUS SIZED DIMENSIONS IN THE FEW NANOMETERS RANGE THS OF A MICRON CLEARLY DEFEATS THE PURPOSE SUCH SMALL THINGS ARE FAR REMOVED FROM THE REALM OF OUR EVERYDAY EXPERIENCE
7HY ARE THESE TINY FEATURES ON THE CHIP SO VULNERABLE TO CONTAMINANTS 3IMPLE PARTICLES OF DIRT THAT ARE SMALLER THAN THE SMALLEST FEATURE ON THE CHIP WILL CAUSE TROUBLE 4HEY CAN CAUSE A PORTION OF THE CHIP TO MALFUNCTION BY CAUSING THE FEATURE TO BE MISSHAPEN AND THEREFORE NOT FUNCTION AS NEEDED 3OME TYPES OF PARTICLES WILL BLOCK THE FORMATION OF PATTERNS ON THE WAFER BY INTERFERING WITH THE PHOTOLITHOGRAPHY PROCESS STILL OTHER PARTICLES CAN CAUSE A CONDUCTING PATH TO FORM BETWEEN CONDUCTING LINES ON THE CHIP SHORTING THEM OUT 4HE FOLLOWING ILLUSTRATION SHOWS AN EXAMPLE OF DAMAGED AREAS ON A CHIP
&IGURE 0ATTERN $EFECT 3EMICONDUCTOR 0ICTURE $ICTIONARYSEE "IBLIOGRAPHY
#ONTAMINATION #ONTROL #HEMICAL CONTAMINANTS THAT CORRODE METAL STRUCTURES OR DISSOLVE THIN lLM MATERIALS ARE A CONSTANT HAZARD 4HESE CHEMICALS ARE OFTEN THE VERY ONES USED IN THE MANUFACTURING PROCESS %VEN SMALLER CONTAMINANTS ARE DANGEROUS -OBILE ION CONTAMINANTS ARE IONS OF METALS THAT CAN MIGRATE TO THE HEART OF ELECTRICAL DEVICES SUCH AS TRANSISTORS AND WILL DAMAGE OR DESTROY THEM 7ITH CRITICAL DIMENSIONS ON )#S AS SMALL AS THEY ARE TODAY WAFERS MUST BE KEPT IN A CONTAMINATION FREE ENVIRONMENT THROUGHOUT MANUFACTURING
#ONTAMINATION 3OURCES &OR MANY YEARS THE PEOPLE WORKING IN THE FAB WERE IDENTIlED AS THE PRINCIPLE SOURCE OF PARTICULATE CONTAMINATION IN THE CLEANROOM %VERYONE CONTINUALLY SHEDS MICRO SCOPIC PARTICLES OF DRY DEAD SKIN AND HAIR $UST AND DIRT IS ALSO CARRIED ON CLOTHES AND IN HAIR -AKEUP IS ESPECIALLY DANGEROUS BECAUSE IT NOT ONLY ADDS TO THE PARTICULATE SHEDDING IT ALSO CONTAINS CHEMICAL CONTAMINANTS THAT WILL RUIN THE CHIPS -AKEUP HAS BEEN FORBIDDEN INSIDE THE FAB SINCE THE MID S 4HE MACHINERY USED TO MAKE THE CHIPS IS THE MAIN PARTICLE SOURCE IN STATE OF THE ART FABS TODAY -AINTENANCE PROCEDURES ARE CRITICAL TO KEEPING THE TOOLS FREE FROM CONTAMINATION -ECHANICAL DEVICES WITH MOVING PARTS SUFFER WEAR LUBRICANTS OUTGAS CHEMICAL VAPORS CONDENSE ON THE INTERIOR WALLS OF THE CHAMBERS AND LOADLOCKS AND CAN BUILD UP UNTIL THEY mAKE OFF AND DROP ON THE WAFERS 3IGNIlCANT IMPROVEMENTS CONTINUE TO BE MADE IN PROCESSING TOOLS &OR EXAMPLE SELF CLEANING PROCESSING CHAMBERS ARE OFFERED FOR SOME TYPES OF REACTORS )N OTHER CASES QUICK CHANGE REPLACEMENT CHAMBERS AND LINERS ARE AVAILABLE &ABRICATION WILL ALWAYS BE A PART OF THE DISCUSSION OF CONTAMINATION 4HE PRO CESS PRODUCES PARTICULATES AND CHEMICAL CONTAMINANTS &OR EXAMPLE CHEMICAL VAPOR DEPOSITION #6$ AND OTHER THIN lLM DEPOSITION PROCESSES WILL OFTEN DEPOSIT lLMS ON THE INTERIOR WALLS OF THE REACTOR AS WELL AS ON THE WAFER )F ALLOWED TO BUILD UP THESE MATERIALS OFTEN BREAK AWAY AND FALL ON THE WAFER AND THEN AN UNWANTED PARTICLE COULD BE INCORPORATED INTO A NEWLY DEPOSITED lLM #HEMICAL MECHANICAL POLISHING #-0 IS A GOOD EXAMPLE OF A PROCESSING OPERATION THAT CREATES PARTICLES #-0 USES TINY ABRASIVE PARTICLES THAT ARE DELIVERED TO THE WAFER SURFACE IN A LIQUID SLURRY 4HE ABRASIVE GRINDS OFF TINY PARTICLES FROM THE WAFER SURFACE !LL OF THESE PARTICLES MUST BE REMOVED AT THE END OF THE PROCESSING STEP OR THE WAFER COULD BE RUINED
#HAPTER 3UPPORT 4ECHNOLOGIES 0ROCESSING CHEMICALS ARE AN IMPORTANT CONSIDERATION 2ESIDUES LEFT BEHIND BY PROCESSING LIQUIDS AND GASES MAY LATER CAUSE DAMAGE SUCH AS CORROSION OF INTERCON NECTING METAL WIRES ON THE WAFER #LEARLY ALL UNWANTED CHEMICALS MUST BE REMOVED FROM THE WAFER AFTER PROCESSING $EIONIZED WATER $) WATER MUST BE USED AT ALL STAGES OF MANUFACTURE 4HE IONS SEE !PPENDIX ! 3CIENCE /VERVIEW IN TAP WATER WOULD TRANSFER TO THE CHIPS AND RUIN THE ELECTRICAL DEVICES ON IT
4HE #LEANROOM 4HE FABRICATION FAB AREA WHERE CHIPS ARE MANUFACTURED IS CALLED A CLEANROOM 4HE CLEANROOM ACCOMPLISHES A LARGE PART OF THE TASK OF KEEPING THE WAFERS FREE OF CONTAMINATION #LEANROOMS ARE CLASSIlED ACCORDING TO THE NUMBER OF MICRON OR LARGER PARTICLES THAT ARE PRESENT IN A CUBIC FOOT OF AIR 3TATE OF THE ART FABS ARE #LASS CLEAN ROOMS 4HAT IS THEY HAVE ONLY ONE PARTICLE THAT IS MICRONS OR LARGER IN EACH CUBIC FOOT OF AIR IN THE FAB #LASS AND #LASS CLEANROOMS ARE USED FOR LESS DEMANDING PROCESSES
&IGURE )NSIDE THE #LEANROOM )NTEL
#ONTAMINATION #ONTROL 4HE CLEANLINESS OF THE FAB IS MAINTAINED BY (%0! OR 5,0! lLTERS 4HE CLEANROOM IS DESIGNED TO CIRCULATE THE AIR IN SUCH A WAY AS TO OPTIMALLY CARRY AWAY ANY AIR BORNE PARTICLES 4HE AIRmOW LEAVES THE (%0! lLTERS IN THE CEILING AND TRAVELS STRAIGHT DOWNWARD TO THE mOOR IN A LAMINAR FASHION 4HE VERTICAL LAMINAR mOW 6,& PREVENTS PARTICLES FROM BEING SCATTERED SIDEWAYS AND ENSURES THAT THEY ARE CARRIED AWAY ! TYPI CAL CIRCULATION PATH IS SHOWN IN &IGURE
&IGURE ,AMINAR &LOW !IR 0ATTERN
!IR COMING INTO THE FABRICATION AREA FROM OUTSIDE GOES THROUGH A PROCESSING PLANT TO lLTER IT AND TO SET THE TEMPERATURE AND HUMIDITY LEVELS TO MATCH THE AIR REQUIRE MENTS INSIDE )T WAS NOT UNHEARD OF IN YEARS PAST FOR A SUDDEN CHANGE IN THE WEATHER TO CAUSE SOME PROCESSING PROBLEMS IN THE FAB BECAUSE THE MACHINERY CONTROLLING THE ENVIRONMENT COULD NOT REACT FAST ENOUGH AND WOULD BECOME TEMPORARILY OVERLOADED 3TATE OF THE ART FABS BUILT TODAY ARE OVER ENGINEERED TO COMPENSATE FOR THAT EVENTUALITY 4HE CLEANROOM COVERALL FONDLY KNOWN AS THE hBUNNY SUIT v HAS EVOLVED OVER THE YEARS TO RESEMBLE A SPACE SUIT 4ODAYS SUITS ARE MADE OF SPACE AGE MATERIALS SUCH AS $UPONTS +EVLAR® AND ARE EQUIPPED WITH lLTERS AND FANS TO DRAW AIR THROUGH THE SUIT BUT NOT LET ANY PARTICLES GET OUT 'OWNING PROCEDURES ARE A CRITICAL PART OF THE TRAINING FOR EVERYONE ENTERING THE FAB 4HE GOWNING ROOM AND GOWNING PROCEDURE ALLOWS A PERSON TO hGOWN UPv WITHOUT
#HAPTER 3UPPORT 4ECHNOLOGIES TRANSFERRING TOO MANY PARTICLES TO THE OUTSIDE OF THE BUNNY SUIT %VERYONE ENTERING THE FAB MUST THEN PASS THROUGH AN AIR SHOWER WHICH IS A SMALL ROOM WITH AIR VENTS BLOW ING AIR FROM ALL ANGLES IN AN ATTEMPT TO REMOVE ALL LOOSE PARTICLES FROM THE OUTSIDE OF THE SUITS (ISTORICALLY THE FABRICATION AREA HAS BEEN LAID OUT IN BAYS BRANCHING FROM A CEN TRAL SPINE 4ODAY THERE ARE NEW LAYOUTS BEING INTRODUCED THAT CONSIST OF A LARGE WORK AREA FOR EACH MAJOR PROCESS STEP 4HE NEWER MULTIFUNCTION PROCESSING TOOL DESIGNS OR CLUSTER TOOLS DISCUSSED IN LATER CHAPTERS FACILITATE THIS INNOVATION 7AFERS ARE ALWAYS HELD IN CASSETTES AND THE CASSETTES ARE PLACED IN CARRYING BOXES 3TATE OF THE ART CLEANROOMS MOVE THE WAFERS FROM ONE AREA TO ANOTHER WITHIN THE FAB USING TRANSPORT SYSTEMS CALLED AUTOMATED MATERIAL HANDLING SYSTEMS !-(3 3OME LIKE THE MONORAIL LOOP TRANSPORT SYSTEM ARE POSITIONED NEAR THE CEILING AND ARE LOADED BY PLACING THE CARRYING BOXES IN AN ELEVATOR THAT AUTOMATICALLY PLACES THE BOX ON A hCARv 4HE CARS TRAVEL ON TRACKS ALONG THE WALLS OVERHEAD /THER TRANSPORTERS ARE CLOSER TO TABLETOP LEVEL SUCH AS THE AUTOMATIC GUIDED VEHICLE SYSTEM
&IGURE &AB ,AYOUT"ALLROOM $ESIGN
#ONTAMINATION #ONTROL -INIMIZING WAFER HANDLING BY HUMANS IS IMPORTANT &ABS CAN BE HIGHLY AUTOMAT ED SUCH THAT ONLY A FEW PEOPLE ARE EVER NEEDED TO MOVE A BOX OF WAFERS 0ROCESSING EQUIPMENT IS MANUFACTURED IN CLUSTERED CONlGURATIONS WHEN POSSIBLE THE WAFERS ARE PUT UNDER VACUUM AND KEPT THERE AS LONG AS POSSIBLE THUS REMOVING THE RISK OF ATMO SPHERIC CONTAMINATION 2ECORDKEEPING NOTE TAKING LOT TRACKING AND OTHER PAPER INTENSIVE ACTIVITIES HAVE ALWAYS BEEN A PROBLEM IN THE CLEANROOM 0APER SHEDS A LARGE AMOUNT OF PARTICLES AND CANNOT BE USED IN THE CLEANROOM 0ENCILS AND PENS ALSO PRODUCE PARTICLES ,INT FREE PAPER WAS DEVELOPED FROM POLYMER lBERS AND IT HELPED SOLVE THE PROBLEM AS DID SPECIAL CLEANROOM PENS 4ODAYS FABS WILL NOT TOLERATE EVEN THE VERY LOW LEVELS OF PARTICLES PRODUCED BY THE LINT FREE PAPER #OMPUTER TERMINALS SPACED EVERY lVE OR TEN FEET APART THROUGHOUT THE FACILITY HAVE REPLACED WRITING IMPLEMENTS AND PAPER 3OME FABS HAVE ACHIEVED LOW PARTICULATE LEVELS WITHOUT MAKING THE ENTIRE FACIL ITY INTO A #LASS ROOM )T IS POSSIBLE TO USE MINI ENVIRONMENTS THAT SURROUND EACH PROCESSING TOOL AND PROTECTIVE BOXES TO TRANSPORT THE WAFERS 4HE INDUSTRY USES A STANDARD MECHANICAL INTERFACE 3-)& TO ENSURE COMPATIBILITY WITH BOXES LOADING SYSTEMS AND PROCESSING TOOLS )N THESE FABS THE ONLY AREAS THAT REQUIRE STRICT GOWNING PROCEDURES ARE SMALL ROOMS WHERE WAFER INSPECTIONS ARE DONE BY FAB PERSONNEL RATHER THAN AUTOMATED INSPECTION TOOLS /F COURSE SOME CLEANROOM PROCEDURES ARE STILL NEC ESSARY FOR THE AREAS WITH HIGHER PARTICULATE CLASSIlCATIONS -ANY OTHER ISSUES SUCH AS CHEMICAL PURITY POINT OF USE lLTERS FOR GASES PRODUC TION OF DEIONIZED WATER AND THE ELIMINATION OF STATIC ELECTRIC CHARGE ARE A FEW OF THE TOPICS THAT ARE BEYOND THE SCOPE OF THIS DISCUSSION 4HE READER WILL lND REFERENCES IN THE BIBLIOGRAPHY THAT WILL LEAD TO FURTHER READING ABOUT CLEANROOM TECHNOLOGY
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#RYSTAL 'ROWTH AND 7AFER 0REPARATION )NTRODUCTION 3EVERAL DIFFERENT SEMICONDUCTING MATERIALS ARE USED FOR ELECTRONIC DEVICE APPLICATIONS #HAPTER MENTIONS THE MOST PROMINENT ELEMENTAL AND COMPOUND SEMICONDUCTORS FAVORED FOR PRODUCTION "ECAUSE SILICON TECHNOLOGY REPRESENTS THE VAST MAJORITY OF COMMERCIAL )# FABRICATION IT IS THE FOCUS OF THIS SECTION )N THIS SECTION THE PURIlCATION OF SILICON SINGLE CRYSTAL SILICON GROWTH AND WAFER MANUFACTURING IS DESCRIBED 4HE FOLLOWING TECHNIQUES ARE THE ONES THAT DOMINATE THE INDUSTRY TODAY
&IGURE 3ILICON )NGOT "EING 0ULLED FROM -ELT
#HAPTER 3UPPORT 4ECHNOLOGIES 0ROCESS &LOW 3ILICON 0URIlCATION -ETALLURGICAL 'RADE 3ILICON %LECTRONICS 'RADE 3ILICON #ZOCHRALSKI #: #RYSTAL 'ROWTH $OPING )NGOT 3HAPING .OTCH 'RINDING
3AWING 7AFERS ,APPING AND 'RINDING %DGE 'RINDING AND 3MOOTHING #HEMICAL %TCH
#HEMICAL -ECHANICAL 0OLISHING 7ET #LEAN ,ASER )NSPECT 3HIP TO #USTOMER 4HIS PROCESS mOW LOOKS QUITE DETAILED BUT THE DISCUSSION WILL SUMMARIZE EACH POINT BRIEmY AND EMPHASIZE THE PURPOSE OF THE MOST IMPORTANT STEPS $ElNITION ! 3UBSTRATE IS A FOUNDATION OR BASIS )T IS ANOTHER NAME FOR THE SILICON WAFER 4HE INTEGRATED CIRCUIT IS BUILT PARTLY WITHIN AND PARTLY UPON THE SEMICON DUCTOR SUBSTRATE
3ILICON 0URIlCATION 4HE PRODUCTION OF SINGLE CRYSTAL SILICON WAFERS WITH THE CHEMICAL CONSISTENCY AND CRYSTALLINE STRUCTURAL PROPERTIES REQUIRED TO MAKE )#S REQUIRES THAT THE SILICON BE RElNED TO AN UNPRECEDENTED LEVEL OF PURITY 4HE INGOT MUST BE MADE FROM SILICON THAT HAS IMPURITIES IN THE PARTS PER BILLION ATOMS PPBA RANGE 3ILICON OF THIS PURITY IS CALLED ELECTRONICS GRADE SILICON %'3 AND IS ONE OF THE PUREST MATERIALS EVER MADE )T IS PURE
#RYSTAL 'ROWTH AND 7AFER 0REPARATION #HEMICAL 0URITY -ATERIAL WITH A PURITY IN THE PARTS PER BILLION ATOMS PPBA RANGE STILL CONTAINS IMPURITIES AT LEVELS OF TEN MILLION MILLION ATOMS PER CUBIC CENTIMETER OF SILICON CM %VEN THOUGH THIS SILICON IS THE PUREST MATERIAL COMMONLY PRODUCED IN THE WORLD TODAY IT IS STILL FAR FROM PERFECT -ANY STRATEGIES ARE EMPLOYED IN THE DESIGN AND MANUFACTURING PROCESS TO COMPENSATE FOR THE INABILITY TO REMOVE OF ALL IMPURITIES FROM THESE MATERIALS )T SEEMS AMAZING THAT )#S WORK AT ALL BUT THE SOPHISTICATED TRICKS OF THE TRADE ARE EVEN MORE AMAZING -ANY OF THESE SECRETS WILL BE REVEALED IN THE DISCUSSIONS TO FOLLOW
4HE STARTING MATERIAL IS A TYPE OF SAND CALLED SILICA WHICH IS MADE OF SILICON DIOX IDE WITH VERY LOW IMPURITY LEVELS 3ILICA IS ACTUALLY ANOTHER NAME FOR SILICON DIOXIDE 4HE SILICA IS REACTED WITH CARBON PRODUCING METALLURGICAL GRADE SILICON -'3 AT A PURITY LEVEL OF ABOUT )MPROVING THE PURITY OF THE SILICON IS NO EASY TASK AS PROVEN BY THE COMPLICATED PROCESSING STEPS TO FOLLOW 4HE SOLID -'3 IS CONVERTED TO A LIQUID CHEMICAL CALLED TRICHLOROSILANE 3I(#L )N THIS FORM IT CAN MORE EASILY BE PURIlED IT IS RElNED IN A VERY INVOLVED DISTILLATION PROCESS THAT IS BEYOND THE SCOPE OF THIS TEXT 4HE PURIlED TRICHLOROSILANE IS THEN REACTED WITH HYDROGEN IN A CHEMICAL VAPOR DEPOSITION #6$ REACTOR THAT EXTRACTS THE HIGHLY PURIlED SOLID ELECTRONICS GRADE SILICON #6$ IS DIS CUSSED AT LENGTH LATER IN THE BOOK 4HE %'3 JUST PRODUCED IS POLYCRYSTALLINE IN STRUCTURE )#S MUST BE BUILT ON SINGLE CRYSTAL SILICON 4HE NEXT STEP PRODUCES SINGLE CRYSTAL SILICON
#ZOCHRALSKI 3ILICON 'ROWTH 4HE #ZOCHRALSKI #: METHOD OF SILICON GROWTH IS NAMED AFTER THE MAN WHO INVENTED IT *AN #ZOCHRALSKI .EARLY ALL OF THE SEMICONDUCTOR MANUFACTURING INDUSTRYS SILICON WAFERS ARE CUT FROM SINGLE CRYSTALS GROWN USING THIS METHOD )N THE #: METHOD A SINGLE CRYSTAL OF SILICON IS GROWN FROM SILICON MELTED IN A QUARTZ GLASS CRUCIBLE 4HIS INGOT OF SILICON IS QUITE LARGE AND IS PRODUCED IN A TWO STORY HIGH FURNACE 3TATE OF THE ART FABS USE MM DIAMETER WAFERS ABOUT INCHES SO THE INGOT CAN BE QUITE LARGE 4HE PROCESS BEGINS WITH A QUARTZ GLASS CRUCIBLE lLLED WITH CHUNKS OF POLYCRYS TALLINE SILICON 4HE CRUCIBLE IS HEATED IN THE CRYSTAL GROWER UNTIL THE SILICON MELTS ! TEMPERATURE OF ABOUT # WHITE HEAT MUST BE REACHED TO MELT THE SILICON ! SEED
#HAPTER 3UPPORT 4ECHNOLOGIES
&IGURE 3ILICON )NGOT
CRYSTAL HAVING THE DESIRED CRYSTAL ORIENTATION IS THEN LOWERED UNTIL IT TOUCHES THE TOP OF THE MELT -ANY SUBTLETIES EXIST IN THE SUCCESSFUL PRODUCTION OF AN INGOT INCLUDING THE ROTATION OF THE MELT AND THE SEED IN OPPOSITE DIRECTIONS 4HE SEED CRYSTAL ACTS AS A TEM PLATE PROVIDING THE STRUCTURAL PATTERN FOR THE CRYSTAL 4HE MOLTEN SILICON FREEZES ONTO THE SEED AS IT IS WITHDRAWN 4HE ENTIRE INGOT IS A SINGLE CRYSTAL OF SILICON MATCHING THE ATOMIC ARRANGEMENT OF THE SEED CRYSTAL 4HE PROCESS TAKES MORE THAN AN HOUR FOR EACH INCH OF INGOT LENGTH #RYSTAL /RIENTATION %VERY CRYSTAL CAN BE DESCRIBED AS A REGULAR ARRANGEMENT OF MANY UNIT CELLS 4HE UNIT CELL IS THE SMALLEST UNIT OF A CRYSTAL THAT STILL DEMONSTRATES THE REGULAR STRUCTURE OF ATOMS FOUND THROUGHOUT THE CRYSTAL 3OME UNIT CELLS AND THEREFORE SINGLE CRYSTALS LOOK THE SAME WHEN VIEWED ALONG ANY PRINCIPAL AXIS 3ILICON HOWEVER DOES NOT 4HE ORIENTATION OF THE SILICON CRYSTAL IS SELECTED BASED UPON THE ELECTRICAL CHARACTERISTICS DESIRED IN THE CHIP ! SYSTEM OF ORTHOGONAL AXES IS USED TO DESIGNATE THE CRYSTAL ORIENTATION 4HE BIBLIOGRAPHY INCLUDES SEVERAL TEXTS WITH A MORE COMPLETE EXPLANATION OF THIS CHARACTERISTIC OF A CRYSTAL AND THE NOTATIONAL SYSTEM USED FOR EACH ORIENTATION &OR EXAMPLE A SPECIlC TYPE OF )# IS MANUFACTURED ON ;= SILICON BECAUSE IT ETCHES FASTER IN THE DIRECTION OF THAT PLANE IN CERTAIN ETCH SOLUTIONS BUT MORE SLOWLY ALONG THE OTHER TWO AXES !S A RESULT A PRECISELY SHAPED TRENCH
#RYSTAL 'ROWTH AND 7AFER 0REPARATION CAN EASILY BE ETCHED INTO THE SILICON FORMING AN IMPORTANT STRUCTURE NEEDED TO MAKE THE CHIP
&IGURE %XAMPLE OF A 5NIT #ELL 3IMPLE #UBIC
4HE VAST MAJORITY OF SILICON PRODUCED FOR CHIP MANUFACTURING IS DOPED IN THE MELT #RYSTALS ARE GROWN WITH A WIDE RANGE OF DOPING LEVELS ! CHIPMAKERS CHOICE OF DOPING LEVEL AND SPECIES IS DICTATED BY THE NATURE OF THE PRODUCT TO BE FABRICATED 4HE STARTING WAFERS NEEDED TO FABRICATE HIGH VOLTAGE RECTIlER CHIPS ARE MUCH DIFFERENT FROM THOSE NEEDED FOR A #-/3 )# #-/3 CHIPMAKERS CHOOSE DOPING LEVELS IN STARTING SILI CON CORRESPONDING TO THEIR PROCESS DESIGN AND ELECTRICAL PARAMETER GOALS 4HE ROLE THAT THE DOPED SUBSTRATE SILICON PLAYS IN THE DEVICE BEING MANUFACTURED AS WELL AS DOPING OTHER lLMS USED IN THE PROCESS WILL BE DISCUSSED IN THE COMING CHAPTERS 4HE TOPIC OF SEMICONDUCTOR DOPING IS ALSO DISCUSSED IN !PPENDIX ! 3CIENCE /VERVIEW !NOTHER IMPURITY OXYGEN IS UNINTENTIONALLY INCORPORATED INTO THE SILICON 4HE QUARTZ GLASS CRUCIBLE IS MADE OF HIGH PURITY SILICON DIOXIDE 3OME OF THE CRUCIBLE REACTS WITH THE SILICON IN THE MELT ADDING A SMALL AMOUNT OF OXYGEN TO THE SINGLE CRYSTAL 4HE OXYGEN DISSOLVES IN THE SILICON A SOLID SOLUTION AND WILL PRECIPITATE OUT AND REACT WITH THE SILICON DURING SOME OF THE HIGH TEMPERATURE PROCESSING STEPS FORMING SILICON DIOXIDE OXIDE )T TURNS OUT THAT THE OXIDE IS A BIG HELP IN CONTROLLING CONTAMINATION 4HE SILICON DIOXIDE TENDS TO CLUMP UP FORMING DISLOCATIONS IN THE SILICON CRYSTAL 4HESE IMPERFECTIONS ARE GETTERING SITES SEE !PPENDIX ! THAT WILL TRAP AND HOLD SOME TYPES OF CONTAMINANTS
#HAPTER 3UPPORT 4ECHNOLOGIES
3HAPING 'RINDING #UTTING AND 0OLISHING 4HE INGOT COMES OUT OF THE MELT AS AN IRREGULARLY SHAPED CYLINDER WITH POINTED ENDS 4HE TEARDROP SHAPED ENDS ARE CUT OFF AND THE INGOT IS PUT INTO A SPECIAL MACHINE THAT GRINDS IT INTO A SMOOTH SIDED CYLINDER OF THE DESIRED DIAMETER .ATURALLY THE SILICON IS HARD SO DIAMOND TIPPED CUTTERS AND GRINDERS MUST BE USED FOR MUCH OF THIS WORK 3INCE A ROUND WAFER WILL OFFER NO FEATURE FOR ORIENTATION OF THE WAFER ON A WAFER HANDLING TOOL A NOTCH IS MACHINED ALONG THE LENGTH OF THE INGOT )T WILL SOON BECOME CLEAR JUST HOW IMPORTANT IT IS TO KNOW WHICH WAY IS hUPv ON THE WAFER AT EVERY STAGE OF CHIP MANUFACTURING /NE OR MORE mAT SIDES WERE MACHINED ON THE INGOT EARLIER IN THE HISTORY OF THE INDUSTRY BUT NOW A SMALL NOTCH IS CUT ON EVERY WAFER WHICH CONSUMES LESS OF THE HIGHLY VALUABLE hREAL ESTATEv ON THE WAFER SURFACE /BVIOUSLY MANUFACTURERS WANT TO PRODUCE AS MANY CHIPS PER WAFER AS POSSIBLE .EXT THE WAFERS ARE MADE BY SAWING THE INGOT WITH SPECIAL ABRASIVE COATED WIRES 3TAINLESS STEEL BLADES WITH DIAMOND EDGES ARE OFTEN USED FOR CUTTING WAFERS SMALLER THAN MM 4HE WAFER SURFACES ARE FAIRLY ROUGH AT THIS POINT 4HEY MOVE TO THE LAPPING AND GRINDING TOOL WHERE THEY ARE FURTHER PROCESSED UNTIL THEY SATISFY A STRICT THICKNESS SPECIlCATION 4HE LAPPING AND GRINDING TOOL ACCOMPLISHES THIS THROUGH THE USE OF TWO COUNTER ROTATING PLATES AND A SLURRY WITH AN ABRASIVE IN IT 4HE WAFERS ARE PLACED BETWEEN THE TWO PLATES AND THE SLURRY REMOVES THE EXCESS SILICON 7AFER EDGES ARE AN IMPORTANT ASPECT OF WAFER PRODUCTION )F THE EDGES OF THE WAFERS ARE ROUGH THEY SHED TINY PARTICLES OF SILICON THAT CAN DAMAGE OR RUIN THE CHIPS #RYSTAL DEFECTS ARE ALSO AN ISSUE IF THE SURFACE OF THE WAFER EDGE IS NOT WELL POLISHED SO THE EDGES OF THE WAFERS ARE ROUNDED WITH A GRINDING TOOL AND THEN HIGHLY POLISHED 4HE WAFER SHAPING PROCESSES USED UP TO THIS POINT HAVE BROUGHT THE WAFER TO AN INTERMEDIATE STAGE AS FAR AS GENERAL SIZE AND SHAPE .EXT SURFACE DAMAGE AND CONTAM INATION MUST BE REMOVED 4HE lRST STEP IN THIS PHASE OF THE PROCESS IS A WET CHEMICAL ETCH USING A COMBINATION OF ACIDS USUALLY INCLUDING HYDROmUORIC ACID AND NITRIC ACID #ONTAMINANTS FROM THE PROCESSING TOOLS AND PARTICLES FROM LAPPING GRIND ING AND POLISHING ARE REMOVED &IGURE 3ILICON )NGOT 'ROUND AND 3LICED INTO 7AFERS
#RYSTAL 'ROWTH AND 7AFER 0REPARATION #HEMICAL MECHANICAL POLISHING #-0 IS A MAJOR PART OF CHIPMAKING TODAY AND APPLICATIONS APPEAR OFTEN IN THE COMING CHAPTERS (OWEVER THE lRST APPLICATION OF #-0 IN THE INDUSTRY WAS POLISHING WAFERS )T IS AT THIS POINT THAT THE SIDE OF THE WAFER ON WHICH THE DEVICES WILL BE BUILT IS BROUGHT TO A HIGHLY POLISHED lNISH 7HY SHOULD A HIGH SHINE HAVE ANY EFFECT ON MAKING THE )#S 4HE SURFACE ROUGH NESS MUST BE DIMENSIONALLY SMALLER THAN THE SIZE OF THE FEATURES BEING PRODUCED ON THE WAFER 4HE ELECTRONIC COMPONENTS OF THE CHIP ARE PARTLY BUILT INTO A VERY THIN POR TION OF THE UPPER SURFACE OF THE WAFER 4HERE IS ALWAYS A HIGH LIKELIHOOD OF DEFECTS ON THE SURFACE OF A CRYSTALRIGHT WHERE THE DEVICES WILL BE BUILT )N ORDER TO MINIMIZE THE NUMBER AND SEVERITY OF CRYSTAL DEFECTS THE SURFACE IS MADE AS PERFECT AS IS HUMAN LY POSSIBLE #-0 STRONGLY RESEMBLES THE LAPPING AND GRINDING PROCESS DISCUSSED EARLIER 4HE #-0 SLURRY IS SPECIlCALLY DESIGNED FOR THIS lNE POLISHING PROCESS AND USES CAREFULLY SELECTED ABRASIVES AND LIQUID COMPONENTS 4HE LIQUIDS IN SLURRIES MAY CONTAIN ACIDS OXIDIZERS OR BASES IN A PROPRIETARY MIXTURE 4HE POLISHING PAD IS ALSO A SPECIALLY DESIGNED MATERIAL 4HE POST #-0 CLEAN IS VERY IMPORTANT 4HE PROCESS OF POLISHING A SURFACE REMOVES VERY TINY PARTICLES OF THE SURFACE MATERIAL 4HE SLURRY CONTAINS TINY PARTICLES AND THEY MUST BE REMOVED OR THE CHIPS WILL BE DAMAGED 4HE CHEMICAL CONTAMINANTS FROM THE SLURRY MUST ALSO BE REMOVED
&INAL )NSPECTION AND 3HIPPING ! LASER INSPECTION IS DONE PRIOR TO SHIPPING THE lNISHED WAFERS 3PECIAL MACHINES USE LASERS TO INSPECT THE SURFACE OF THE WAFERS FOR ALL TYPES OF DEFECTS 4HESE AUTOMATED TOOLS IDENTIFY DEFECTS QUICKLY AND ACCURATELY &LATNESS BOWING RESISTIVITY PHYSICAL MEASUREMENT AND MANY OTHER SPECIlCATIONS ARE CHECKED BY AUTOMATED TOOLS 7AFER &LATNESS 7AFERS SATISFY SOME OF THE TIGHTEST SPECIlCATIONS KNOWN TO MAN )F AN AIRPORT RUNWAY WAS AS mAT AS A WAFER ITS SURFACE WOULD VARY BY ONE INCH OR LESS PER MILE
7HEN THE WAFERS PASS lNAL INSPECTION THEY ARE PLACED IN CASSETTES WRAPPED IN LAYERS OF PLASTIC AND SHIPPED TO THE CUSTOMER
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3%#4)/.
#IRCUIT $ESIGN )NTRODUCTION 4HE INTEGRATED CIRCUIT )# IS SIMPLY A LOT OF DISCRETE ELECTRONIC DEVICES LIKE TRANSISTORS DIODES RESISTORS AND CAPACITORS THAT ARE ALL BUILT ON A SINGLE PIECE OF SEMI CONDUCTOR MATERIAL AND WIRED TOGETHER THESE DEVICES ARE hINTEGRATEDv INTO A SINGLE CHIP 4HE PROCESS OF DESIGNING AN )# IS QUITE COMPLEX 4ODAYS CHIPS MAY CONTAIN WELL OVER ONE BILLION OF THESE DISCRETE DEVICES 4O CALL THE DESIGN PROCESS hNONTRIVIALv IS SOMETHING OF AN UNDERSTATEMENT )T IS A HIGHLY SOPHISTICATED PROCEDURE UTILIZING SOME OF THE MOST ADVANCED SOFTWARE TOOLS EVER DEVISED #OMPARATIVELY SIMPLE )#S CAN BE DESIGNED IN SEVERAL MONTHS ! PRODUCT LIKE THE RADIO FREQUENCY IDENTIlCATION 2&)$ CHIP THAT PERFORMS ONLY ONE SIMPLE FUNCTION IS AN EXAMPLE -ICROPROCESSORS ARE A VERY DIFFERENT STORY THEY TAKE YEARS TO DESIGN -ICROPROCESSORS ARE COMPLEX CHIPS THAT PERFORM MANY DIFFERENT FUNCTIONS ON THE SAME CHIP )T TAKES SEVERAL SPECIALIZED DESIGN GROUPS TO GET THE JOB DONE 2IGOROUS VERIlCA TION OF FUNCTIONALITY ALONE TAKES MONTHS -INIATURIZATION IS THE NAME OF THE GAME IN CHIPMAKING 0LANNING THE SHRINKAGE OF THE SIZE OF THE PART ADDS TO THE DESIGN TIME $ESIGNERS MUST COORDINATE WITH MANUFAC TURING TO ENSURE THAT IT IS POSSIBLE TO MAKE THE CHIP THAT THEY HAVE DESIGNED 4HE SPACE PROGRAM DROVE THE EARLY DEVELOPMENT OF THE INDUSTRY .OW -OORES ,AW IS MISTAKEN FOR A LAW OF NATURE BECAUSE IT HAS PROVEN TO BE SO RELIABLE
#HAPTER 3UPPORT 4ECHNOLOGIES -OORES ,AW -OORES ,AW IS NAMED AFTER 'ORDON -OORE ONE OF THE FOUNDERS OF )NTEL )N THE MID SEVENTIES HE OBSERVED THAT MANUFACTURERS OF COMPUTER MEMORY CHIPS WERE ABLE TO DOUBLE THE NUMBER OF TRANSISTORS IN THEIR PRODUCTS EVERY EIGHTEEN MONTHS !CTUALLY HIS lRST APPROXIMATION WAS TWELVE MONTHS BUT HE SOON MODIlED IT TO THE EIGHTEEN MONTH lGURE THAT HAS BEEN USED EVER SINCE 4HE CORRESPONDING EXPONENTIAL RISE IN CHIP PERFORMANCE IS LARGELY RESPONSIBLE FOR THE GROWTH IN COMPUTER PERFORMANCE WITHOUT A CORRESPONDING INCREASE IN PRICE -OORES OBSERVATION HAS PROVEN TO BE INCREDIBLY ACCURATE AND NO ONE WAS MORE SURPRISED THAN -OORE HIMSELF -ANY PEOPLE EXPECT TO REACH THE END OF ITS VALIDITY ANY DAY NOW BUT THE INNOVATORS IN THE INDUSTRY CONTINUE TO PRODUCE EVER MORE COMPLEX )#S WITH MORE AND MORE TRANSISTORS AT THAT AMAZ INGLY CONSISTENT RATE
3EVERAL KINDS OF COMPANIES DESIGN )#S )NDEPENDENT DESIGN lRMS ARE PROBABLY THE MOST NUMEROUS TODAY 4HESE COMPANIES DO ONLY THE DESIGN PROCESS AND CONTRACT OUT TO A FOUNDRY FOR THE PRODUCTION OF THE CHIP 3OME VERY LARGE lRMS SUCH AS !LTERA AND 8ILINX ARE SO CALLED FABLESS COMPANIES &ABLESS DESIGN HOUSES USE $ESIGN 2ULE 3ETS GENERALIZED INSTRUCTIONS GUIDELINES AND RESTRICTIONS ON THE )# DESIGN AS PROVIDED BY A PARTICULAR FOUNDRY OR A GROUP OF FOUNDRIES 4HESE DESIGN RULES TELL THE DESIGNERS EXACTLY WHAT THE MANUFACTURING CAPABILITIES ARE FOR THE FOUNDRY SO THAT THEY DO NOT DESIGN A CHIP THAT CANNOT BE PRODUCED BY THAT FAB &OUNDRIES ARE BECOMING THE BACKBONE OF SEMICONDUCTOR MANUFACTURING 4HE FOUNDRY MANUFACTURES CHIPS DESIGNED BY OTHER lRMS 43-# AND 5-# IN 4AIWAN ARE EXAMPLES OF lRMS THAT DO ONLY FOUNDRY WORK -OTOROLA )"- AND 3AMSUNG ARE A FEW WELL KNOWN MANUFACTURERS THAT DO FOUNDRY WORK FOR THE INDEPENDENT DESIGN HOUSES AS WELL AS MAKING CHIPS DESIGNED IN HOUSE 4HE INDEPENDENT DEVICE MANUFACTURER )$- IS THE lRM THAT ONLY MAKES CHIPS IN ITS FAB THAT ARE DESIGNED BY ITS OWN ENGINEERS 7HILE THESE TYPES OF COMPANIES ONCE DOMINATED THE CHIP MAKING BUSINESS )$-S ARE BECOMING RARE TODAY BECAUSE OF THE HIGH COST OF BUILDING A NEW FAB -OST lRMS WITH A MANUFACTURING FACILITY WILL ENTER TAIN OFFERS TO DO FOUNDRY WORK
0RODUCT $ElNITION AND .EW 0RODUCT 0LAN $ElNITION ! 3CHEMATIC IS A SYMBOLIC REPRESENTATION OF AN ELECTRICAL CIRCUIT 4HE DRAWING MAY INCLUDE ONE OR MORE TRANSISTORS CAPACITORS DIODES POWER SUPPLIES OR OTHER ELECTRICAL COMPONENTS ALL WIRED TOGETHER
#IRCUIT $ESIGN $ElNITION $ESIGN 2ULES ARE A SET OF SPECIlCATIONS THAT DESCRIBE IN DETAIL THE SIZE OF THE CHIP THE SIZE OF THE FEATURES ON THE CHIP THE SPACING OF FEATURES AND COMPO NENTS ELECTRICAL PARAMETERS AND THE STEPS TO BE FOLLOWED IN THE DESIGN PROCESS TO ENSURE THAT IT RUNS SMOOTHLY AND THAT ALL CHECKS AND VERIlCATIONS ARE PERFORMED 4HERE ARE THOUSANDS OF DIFFERENT )#S MADE TODAY BUT THE NEED FOR NEW CHIPS WITH BETTER OR UNIQUE DESIGNS IS AS STRONG AS EVER )T ONLY TAKES A GOOD IDEA TO START A NEW CHIP DESIGN COMPANY ! GOOD IDEA WITH A GOOD BUSINESS PLAN WILL ATTRACT THE NEEDED VENTURE CAPITAL -ANY OF THESE STARTUPS ARE FOUND IN h3ILICON 6ALLEYv AND OTHER INNO VATION CENTERS AROUND THE WORLD &REQUENTLY THE NEW CHIP DESIGNS ARE MOTIVATED BY A CUSTOMER NEED ! CHIP DESIGN COMPANYS MARKETING AND SALES FORCE WILL BRING REQUESTS FOR A NEW PRODUCT FROM THE CUSTOMER !LSO COMMON ARE INNOVATIONS WITHIN AN IN HOUSE DESIGN GROUP THAT CAN ADD A NEW LINE TO AN EXISTING ONE OR EVEN DEVELOP A NEW PART WITH A PERCEIVED NEED /THER INNOVATIONS ARE THE RESULT OF RESEARCH OR 2$ WORK THAT DEVELOPS A NEW TECHNOLOGY TO BE USED FOR MAKING )#S .O MATTER HOW GREAT THE IDEA FOR A STARTUP OR NEW CHIP DESIGN ELECTRICAL ENGINEERS AND PRODUCT DESIGNERS MUST BE INTERESTED IN USING THE NEW PART IN THEIR END PRODUCTS )N OTHER WORDS THERE MUST BE A MARKET FOR THE NEW PRODUCT !PPLICABILITY AVAILABILITY AND RELIABILITY MUST BE PROVEN FOR EVERY NEW CHIP ENTERING THE MARKET 4HE PROCESS OF DESIGNING A SEMICONDUCTOR CHIP STARTS WITH THE 0RODUCT $ElNITION 7ITH A CLEARLY DElNED PRODUCT CONCEPT A .EW 0RODUCT 0LAN .00 IS CREATED BY A GROUP OF KEY PLAYERS )T IS THE MASTER PLAN FOR THE CHIP 4HE .00 OFTEN ORIGINATES WITH MARKETING AND MAY BE ADJUSTED BY DESIGNERS IF THE SPECIlCATION CANNOT BE MET $ElNITION 4HE .EW 0RODUCT 0LAN .00 IS THE MASTER PLAN FOR THE CHIP )T CONTAINS REQUIREMENTS FROM MAR KETING BUSINESS RELIABILITY TECHNOLOGY OPERATIONS FABRICATION AND ENGINEERING CHIP DESIGN 4HIS INFORMATION mOWS TO BLOCK PLANS CHIP PLANNING AND ALL OTHER DOWNSTREAM CHIP DESIGNING ACTIVITIES &OR EXAMPLE THE MARKETING DEPARTMENT CONTINUALLY INTERFACES WITH CUSTOMERS 4HEY KEEP THEIR lNGERS ON THE PULSE OF THE MARKET TO DETERMINE WHEN THE NEED FOR A NEW PRODUCT APPEARS $O OUR CUSTOMERS NEED ANALOG CHIPS FOR STEREOS $O THEY NEED MEMORY CHIPS TO STORE INFORMATION IN THEIR PRODUCT $O THEY NEED A MICROCONTROLLER THAT CAN
3OME TOPICS IN THE .00 ARCHITECTURE DENSITY SPEED VOLTAGE POWER CONSUMPTION PACKAGE SUPPORT DIE SIZE ESTIMATE BONDING OPTIONS BUSINESS OPPORTUNITIES STAFlNG REQUIREMENTS ESTIMATED SCHEDULE COST ANALYSIS DEFECT DENSITY REQUIREMENTS
#HAPTER 3UPPORT 4ECHNOLOGIES BE PROGRAMMED THROUGH SOFTWARE 7HAT IF THE MILITARY NEEDS A CHIP THAT WILL WORK IN SPACE ON A SATELLITE "ASED ON ITS MARKET ANALYSIS THE MARKETING DEPARTMENT THEN CREATES A PRODUCT DElNITION A CHIP DESIGN THAT WILL lLL A PERCEIVED NEED AND THERE FORE WILL SELL WELL -ARKETING ENGINEERS WILL THEN WORK WITH THE DESIGN ENGINEERS TO PRODUCE THE NEW PRODUCT PLAN 0ERHAPS MARKETING RECEIVES A REQUEST FOR A NEW CHIP FROM A CUSTOMER 3INCE THE CHIP MUST INTERFACE WITH OTHER DEVICES IN THE CUSTOMERS END PRODUCT THE CUSTOMERS REQUIREMENTS WILL BE INTEGRAL TO THE CREATION OF THE .00 .EW PRODUCT PLANS ARE BY NECESSITY mEXIBLE 2EGULAR MEETINGS OF ALL INTERESTED PARTIES ARE HELD TO REVIEW THE PROGRESS OF THE DESIGN AND TO DISCUSS THE INEVITABLE PROB LEMS AND REVISIONS $ESIGN MARKETING AND CUSTOMER REPRESENTATIVES ALL PARTICIPATE AS APPROPRIATE !FTER THE NEW PRODUCT PLAN HAS BEEN DECIDED UPON THE CHIP SPECIlCATIONS CAN BE WRITTEN 4HESE SPECIlCATIONS ARE OFlCIAL DOCUMENTS WRITTEN BY THE DESIGN AND LOGIC ENGINEERS OF A DESIGN TEAM -ANY OF THESE PARTICULARS COME DIRECTLY FROM THE .00 4HEY DETAIL THE PARAMETERS OF MANY INTRICATE CIRCUIT CHARACTERISTICS SUCH AS VOLTAGES CURRENT REQUIREMENTS POWER CONSUMPTION GAIN AND SPEED 4HIS IN TURN BECOMES THE BASIS FOR THE DESIGN OF THE CIRCUIT SCHEMATICS AS WELL AS SELECTION OF A FOUNDRYS TECHNOLOGY
&IGURE %XAMPLE OF A 3CHEMATIC
#IRCUIT $ESIGN -ILITARY PRODUCTS ARE MORE DIFlCULT TO DESIGN BECAUSE THE )#S MUST WORK UN DER A BROADER RANGE OF TEMPERATURE AND ENVIRONMENTAL CONDITIONS THAN COMMERCIAL PRODUCTS 4HE hMIL SPEC v AS IT IS KNOWN REQUIRES THE CHIPS TO STAND UP TO EXTENSIVE RELIABILITY TESTINGRIGOROUS THERMAL SHOCK TESTS PHYSICAL SHOCKS AND SOMETIMES EVEN RADIATION EXPOSURES THAT COULD COME FROM NUCLEAR WEAPONS 4HEY ARE ALSO MORE COSTLY TO PRODUCE BECAUSE THE GOVERNMENT REQUIRES MORE PAPERWORK AND MORE STRINGENT PRO CESS CONTROLS 4HERE ARE THREE BASIC TYPES OF DESIGN SPECIlCATIONS #USTOMER $ESIGN 3PECIlCATIONS INCLUDE ALL OF THE REQUIREMENTS FROM THE CUSTOMERS SIDE 7HAT ARE THE INPUTOUTPUT VOLTAGES !RE THERE FREQUENCY LIMITATIONS 7HAT TYPE OF SIGNAL IS BEING PROCESSED (OW WILL THE CHIP INTERFACE WITH THE EXISTING PRODUCT 7HAT PACKAGE BEST SUITS THE CUSTOMERS END PRODUCT &OR EXAMPLE COMMODITY PRODUCTS SUCH AS MEMORY CHIPS OR ANALOG TO DIGITAL CHIPS HAVE A RANGE OF STANDARD PACKAGES FOR CUSTOMERS TO CHOOSE FROM 0ROCEDURAL $ESIGN 3PECIlCATIONS SPECIFY THE PROCEDURES TO BE FOLLOWED DUR ING THE DESIGN PROCESS !RE CROSS FUNCTIONAL GROUPS TO BE USED 7ILL TEAMS OF ENGINEERS WORK ON SEPARATE SEGMENTS OF THE CHIP OR WILL A SINGLE ENGINEER BE RESPONSIBLE FOR EACH SECTION (OW WILL EACH PIECE OF THE DESIGN BE PASSED ON UPON COMPLETION 0ROCEDURAL DESIGN SPECS ALSO LET THE TEAM KNOW WHEN A STEP IN THE PROCEDURE IS DONE CORRECTLY 4HESE SPECIlCATIONS CAN BE EXTREMELY DE TAILED AND ENUMERATE HOW MANY TIMES A SCHEMATIC OR DRAWING CAN BE REVISED OR IF THE AUTHORS NAME MUST BE ON THE DOCUMENT 4HESE TYPES OF SPECIlCATIONS ARE REQUIRED WHEN A LARGE TEAM OF ENGINEERS ARE WORKING ON A COMPLEX DESIGN $IMENSION $ESIGN 3PECIlCATIONS ENUMERATE THE SIZES OF THE CHIP AND ALL THE COMPONENTS ON THE CHIPTHE CRITICAL DIMENSIONS OF THE TRANSISTORS THE SIZE OF THE MEMORY BLOCKS THE SIZE OF THE CHIP ITSELF THE WIDTH OF CONDUCTING METAL LINES AND SO FORTH 4HEY ARE COMMONLY KNOWN AS DESIGN RULES 4HE DIMENSIONS OF THE CHIP AND ITS COMPONENTS OFTEN MUST BE ADJUSTED DURING DESIGN BUT ANY LARGE DEPARTURES FROM THE ORIGINAL PLAN CAN STRONGLY AFFECT THE VALUE OF THE CHIP TO THE END USER
4HE $ESIGN 4EAM ! LOT OF TERMINOLOGY IS INCLUDED IN THIS SECTION THAT GOES BEYOND THE FAMILIAR AND IS OFFERED AS A hTEASERv TO ENCOURAGE THE READER TO EXPLORE THE lELD IN MORE DEPTH -ANY DIFFERENT TYPES OF ENGINEERS ARE NEEDED FOR THE DESIGN TEAM
#HAPTER 3UPPORT 4ECHNOLOGIES 4HE MOST WELL KNOWN ENGINEER IS THE DESIGN ENGINEER 4HIS SPECIALIST HOLDS AN ELECTRICAL ENGINEERING DEGREE COUPLED WITH THE EXPERTISE AND CREATIVITY TO DEVISE NEW WAYS TO MAKE CIRCUITS WORK 4HE DESIGN ENGINEER UTILIZES HIS OR HER SKILLS TO CREATE A SCHEMATIC THAT WILL NOT ONLY PERFORM A SPECIlC FUNCTION BUT DO SO IN A UNIQUE WAY #REATING A UNIQUE DESIGN MAKES IT ELIGIBLE FOR A PATENT THEREBY PROTECTING THE COMPANYS INTELLECTUAL PROPERTY /VER THE YEARS DESIGN ENGINEERS HAVE TRANSITIONED FROM USING PAPER AND PENCIL TO DRAW SCHEMATICS TO USING SOPHISTICATED SOFTWARE THAT MODELS THE lNAL BEHAVIOR OF THE CIRCUIT IMMEDIATELY AFTER IT IS DRAWN 4HE SCHEMATIC BECOMES THE BASIS FOR MANY OF THE DESIGN PROCESS TASKS CIRCUIT SIMULATION AND FUNC TIONALITY TESTING THE BLUEPRINT AND INSTRUCTION SET FOR THE LAYOUT ENGINEER AND THE BASIS FOR THE DOCUMENTATION THAT MUST ACCOMPANY EVERY NEW ELECTRONIC DEVICE 4HE LAYOUT ENGINEER OR LAYOUT DESIGNER DOES THE ARTWORK THAT TURNS THE SCHEMATIC INTO A DRAWING OF WHAT THE ENTIRE CIRCUIT WILL ACTUALLY LOOK LIKE ON THE CHIP 4HE LAYOUT ENGINEER IS RESPONSIBLE FOR PLANNING THE SHAPE OF FUNCTIONAL BLOCKS CIRCUIT DESIGNS ARE CREATED IN SMALLER CHUNKS AND LATER ASSEMBLED INTO THE lNISHED )# 4HE LAYOUT GROUP PLANS THE WIRING LOCATIONS TRANSISTOR CONNECTIONS AND CONDUCTS VERIlCATION OF THE DESIGN RULES AND CONNECTIONS 4HESE CIRCUIT DIAGRAMS ARE CONVERTED INTO LAYERS BY THE DESIGN SOFTWARE )NTE GRATED CIRCUITS ARE BUILT ONE LAYER AT A TIME SO EACH LAYER IS UNIQUELY IDENTIlED IN THE DRAWING PROGRAM SO IT CAN BE VIEWED INDIVIDUALLY ,ATER THESE LAYERS ARE MADE INTO PHOTOMASKS THAT ARE REPRODUCED ON THE WAFER SEE 3ECTION 4HE LOGIC ENGINEER LOOKS AT THE )# FROM A GLOBAL VIEWPOINT (E OR SHE USES SOFT WARE PROGRAMMING LANGUAGES SUCH AS 6($, A HARDWARE DESCRIPTION LANGUAGE ($, THE h6v IS JUST PART OF THE PRODUCT NAME OR 6ERILOG TO CREATE LOGIC OR FUNCTIONAL CODE OR LOGIC DESCRIPTIONS 4HESE LOGIC DIAGRAMS PARTITION AN OVERALL DESIGN INTO FUNCTIONAL PARTS WHICH CAN THEN BE USED BY A CIRCUIT DESIGNER TO CREATE THE DETAILED DESIGN FOR THAT FUNCTION 3YNTHESIZED LAYOUT IS CREATED BY COMPUTER AIDED DESIGN TOOLS ! METHOD CALLED STANDARD CELL PLACE AND ROUTE USES COMPUTER PROGRAMS TO MAKE THE REQUIRED CONNECTIONS 3OFTWARE ENGINEERS ARE NEEDED FOR CHIPS THAT MUST BE PROGRAMMED TO COMMU NICATE WITH OTHER DEVICES 4HE MOST FAMILIAR CHIPS OF THIS SORT ARE MICROPROCESSORS 4HEIR mAWS AND SOFTWARE BUGS ARE WIDELY REPORTED IN THE NEWS #HIPS USED FOR COM PUTER APPLICATIONS ARE AN EXAMPLE OF CHIPS THAT MUST BE PROGRAMMED AFTER THEY ARE MANUFACTURED
#IRCUIT $ESIGN !PPLICATIONS ENGINEERS PUT THE CHIPS TO WORK IN NEW APPLICATIONS OR SHOW HOW THEY CAN BE BETTER USED IN EXISTING APPLICATIONS #USTOMERS OFTEN GET A LOT OF HELP IN OPTIMIZING THE USE OF THE PRODUCT FROM THESE FOLKS 4ECHNOLOGY TRANSFER ENGINEERS OR A TECHNOLOGY GROUP WILL INTERFACE WITH THE MANUFACTURING ENGINEERS AND PROCESS ENGINEERS WHO WILL BE PRODUCING THE CHIPS 4HE TECHNOLOGY GROUP CAN ENCOMPASS A WIDE RANGE OF RESPONSIBILITIES FROM RESEARCH INTO NEW MANUFACTURING PROCESSES TO RELIABILITY STANDARDS FOR EXISTING PROCESSES 4HE MODELING ENGINEER IS RESPONSIBLE FOR CREATING MATHEMATICAL MODELS AND SOFTWARE THAT MIMICS THE WAY A CERTAIN TYPE OF TRANSISTOR OR DISCRETE DEVICE WILL WORK 4HEY USE DATA THAT IS FED BACK FROM THE MANUFACTURING ENVIRONMENT 4ECHNOL OGY ENGINEERS AS WELL AS BY DESIGN ENGINEERS WILL USE THEIR PRODUCT ESPECIALLY IF THE MANUFACTURING TECHNOLOGY IS NEW OR UNIQUE !RCHITECTURAL ENGINEERING IS THE DOMAIN OF HIGHLY EXPERIENCED ENGINEERS WHO KNOW HOW TO PARTITION AND hmOOR PLANv THE hGUTSv OF THE SEMICONDUCTOR CHIP ,ARGE COMPLICATED INTEGRATED CIRCUITS REQUIRE MANY REVISIONS OF THE INITIAL mOOR PLAN 3OME TIMES AN ENGINEER WILL HAVE TO COMPLETELY CHANGE THE PARTITIONING IN ORDER TO lX A PROBLEM SUCH AS SPEED USUALLY TOO SLOW OR POWER USES TOO MUCH 4HE UNSUNG HERO OF THE DESIGN TEAM IS THE #!$ ENGINEER 4HIS ENGINEER IS RESPON SIBLE FOR INSTALLING AND SUPPORTING DESIGN SOFTWARE FOR ALL THE TYPES OF ENGINEERS ON THE TEAM AS WELL AS WRITING PROGRAMS TO HELP ALL THE TEAM MEMBERS DO THEIR JOBS MORE EFlCIENTLY 4HIS TEAM MEMBER CAN ALSO BE RESPONSIBLE FOR EVALUATING AND NEGOTIATING THE PRICING OF DESIGN AND VERIlCATION SOFTWARE )N SMALL COMPANIES THE #!$ ENGINEER lNISHES THE INTEGRATED CIRCUIT DESIGN PROCESS AND PERFORMS THE lNAL STEP CALLED TAPEOUT #ROSS FUNCTIONAL TEAMS COMBINE SEVERAL DIFFERENT TYPES OF ENGINEERS TO PRODUCE A COMPLETE DESIGN ON A SECTION OF THE DESIGN OR OF THE ENTIRE CHIP &UNCTIONAL TEAMS ARE USUALLY COMPRISED OF ONLY ONE TYPE OF ENGINEER )N THIS CASE THE NEW PRODUCT PLAN WILL HAVE A PROCEDURE DElNED THAT DIVIDES THE DESIGN WORK INTO DISTINCT SEGMENTS THAT ARE INTEGRATED LATER
4HE $ESIGN 0ROCESS $ESIGN ENGINEERS USE SOFTWARE PRODUCTS WITH NAMES LIKE 24, AND 6ERILOG TO DRAW SCHEMATICS 4HE IDEA STILL COMES FROM THE CREATIVITY OF THE ENGINEER (OWEVER TODAYS SOPHISTICATED SOFTWARE ALLOWS THE DESIGNER TO QUICKLY CHECK HIS OR HER WORK USING SIMULATIONS
#HAPTER 3UPPORT 4ECHNOLOGIES
&IGURE %XAMPLE OF A ,AYOUT
3IMULATIONS ARE RUN REPEATEDLY THROUGHOUT THE DESIGN PROCESS TO ENSURE THAT THE DESIGNS WILL WORK THAT EACH PART OF THE CHIP WILL INTERFACE CORRECTLY TO CHECK DESIGN RULES AND SO FORTH 3OFTWARE PRODUCTS LIKE 6($, ARE USED FOR THESE SIMULATIONS !T THE START OF THE DESIGN PROCESS MANY ENGINEERS AND OTHER CONTRIBUTORS ARE NEEDED TO SPEED THINGS ALONG 4HE MORE PEOPLE THE BETTER DURING THE EARLY STAGES OF DEVELOPMENT ,ATER ON HOWEVER FEWER PEOPLE ARE NEEDED BECAUSE THE TASKS ARE MORE SPECIALIZED 6ERIlCATIONS BEGIN TO DOMINATE THE WORK AND THE ABILITY OF THE LAYOUT GROUP TO MAKE CORRECTIONS IN THE ARTWORK BECOMES MORE IMPORTANT SO EXTRA HELP DOES MORE HARM THAN GOOD AT THE END OF THE PROCESS #HIPS ARE DESIGNED AS A WHOLE ENTITY 4HE SCHEMATIC IS ONLY A SYMBOLIC REPRE SENTATION OF ACTUAL ELECTRICAL COMPONENTS 4HE LAYOUT ENGINEER DRAWS A PICTURE OF THE ACTUAL lNISHED DEVICE AS SEEN FROM THE TOP !LTHOUGH THE CHIPS ARE MANUFACTURED IN LAYERS THE DESIGN OF THE CHIP IS NOT DONE THAT WAY 4HE CHIP LAYOUT IS BROKEN APART INTO LAYERS BY THE DESIGN SOFTWARE WHEN THE DESIGN IS COMPLETE
#IRCUIT $ESIGN
$ESIGN 6ERIlCATION AND 4APEOUT )T MAY SOUND AS IF THE DESIGN PROCESS GOES RELATIVELY SMOOTHLY FROM START TO lNISH .OTHING COULD BE FURTHER FROM THE TRUTH $OZENS OF THINGS CAN HAPPEN TO CAUSE ERRORS THAT WILL REQUIRE CHANGES CORRECTIONS AND REWORK OF THE DESIGN %VEN SIMPLE CHIPS ARE OFTEN DESIGNED IN BLOCKS THAT ARE LATER WIRED TOGETHER )F THE ELECTRICAL PARAMETERS DO NOT MATCH EXACTLY ONE OR ALL BLOCKS MUST BE REWORKED 3IMULATIONS REVEAL HOW FAST A DESIGN WILL PROCESS SIGNALS )F THE DESIGN IS DISCOVERED TO BE TOO SLOW TO PROCESS SIGNALS IT MUST BE REDESIGNED $ESIGN RULES SPECIFY SUCH PARTICULARS AS lLM THICK NESSES AND CONDUCTING LINE WIDTHS )T MAY BE DISCOVERED THAT THE DESIGN RULES WERE TOO AGGRESSIVE AND THE CHIP WILL NOT BE RELIABLE BECAUSE OF MANUFACTURING LIMITATIONS 4HE POSSIBILITIES FOR BOTTLENECKS ARE ENDLESS $ESIGN VERIlCATION IS DONE AS OFTEN AS IS NECESSARY TO CATCH ALL ERRORS AND lX THEM 4HE NEW PRODUCT PLAN WILL ALLOW MANY CHECKS AND TESTS SO THAT ERRORS ARE FOUND AS EARLY AS POSSIBLE IN THE DESIGN PROCESS 6ERIlCATION IS DONE WITH HIGHLY SPECIALIZED AND EXPENSIVE SOFTWARE /RIGINALLY VERIlCATION WAS DONE BY HAVING THE DESIGN PRINTED OUT ON PAPER AND THE DESIGN ENGINEER AND LAYOUT DESIGNER WOULD USE COLORED PENCILS TO DOUBLE CHECK THE ACCURACY OF CONNECTIONS BY DRAWING OVER EACH CONNECTION 4O DAYS )#S ARE TOO COMPLEX FOR SUCH A SIMPLISTIC METHOD 3IMULATIONS OF HOW THE CIRCUIT WILL OPERATE ARE RUN ON THE lNISHED CIRCUIT AND DURING THE DESIGN OF THE CHIP 3IMULATIONS ARE RUN ON SMALL SEGMENTS OF THE DESIGN AS WELL AS THE WHOLE CHIP DESIGN TO ENSURE THAT EACH PART NO MATTER HOW SMALL WILL FUNC TION AS INTENDED -ANY TIMES THE LAYOUT WILL BE CHANGED DUE TO A SIMULATION CATCHING A hBUGv OR ERROR IN THE DESIGN ,AYOUT 6ERSUS 3CHEMATIC ,63 IS ONE OF THE MOST IMPORTANT TESTS )T IS DONE TO SEE IF THE LAYOUT ARTWORK MATCHES THE SCHEMATIC AND THAT THE CONNECTIVITY OF ALL THE WIRING IS CORRECT $ESIGN 2ULE #HECKS $2# VERIFY THAT THE DRAWING CONFORMS TO THE DIMENSIONS AND OBJECT SPACING SPECIlED IN THE DESIGN RULES 4HIS CHECK IS DONE FOR EACH PORTION OF THE )# AS WELL AS FOR THE lNISHED DRAWING 0HASE 3HIFT -ASK #HECK IS ANOTHER TEST TO ENSURE THE lLE THAT IS SENT TO THE MASK MAKING VENDOR IS DRAWN FOR A SPECIAL TYPE OF MASK THE PHASE SHIFT MASK )N PARTICULAR POLY GATE DIMENSIONS SEE #HAPTER ARE NOW SO SMALL THAT SPECIAL MULTIPLE OPENINGS IN THE PHOTOMASK ARE NEEDED TO CONTROL THE PHASE OF THE 56 LIGHT SHINING THROUGH THE PHOTOMASK SEE 3ECTION 4HIS IS A NEW STEP IN THE VERIlCATION PROCESS
#HAPTER 3UPPORT 4ECHNOLOGIES $ElNITION 4APEOUT IS THE PROCESS OF TURNING THE LAYOUT CHIP ARTWORK INTO SEPARATE LAYERS THAT WILL BE MADE INTO PHOTOMASKS SEE 3ECTION 4HE TERM COMES FROM THE PROCEDURE USED EARLY IN THE HISTORY OF THE INDUSTRY WHEN THE lNAL STEP IN THE DESIGN PROCESS WAS TO DOWNLOAD THE LAYERS ONTO REEL TO REEL TAPES 4HE TAPES WOULD THEN BE DELIVERED TO THE MASK MAKER 4ODAY TAPEOUT ESSENTIALLY CONSISTS OF SENDING AN ENCRYPTED lLE OF THE FULLY VERIlED )# USING lLE TRANSFER PROTOCOL &40 TO THE MASK VENDOR
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0HOTOMASK AND 2ETICLE 0REPARATION )NTRODUCTION 4HE )# DESIGN TEAM HAS TAPED OUT THE DESIGN OF A NEW PRODUCT (OW IS THE ARTWORK TRANSFERRED TO THE WAFER SURFACE ! PHOTOLITHOGRAPHY PROCESS IS USED FOR THAT PURPOSE %ACH LAYER NEEDED TO BUILD THE CHIP REQUIRES A PATTERNED QUARTZ GLASS PLATE EITHER A PHOTOMASK OR A RETICLE 4HESE PHOTOMASKS OR RETICLES ARE USED BY PHOTOLITHOGRAPHIC IMAGING TOOLS THAT ARE A LARGE PART OF THE STORY FOUND IN LATER CHAPTERS 4HE PRODUCTION OF THE PHOTOMASKS AND RETICLES IS DISCUSSED IN THIS SECTION )N TERESTINGLY THE PROCESS MOST OFTEN USED TO MAKE THE RETICLES AND PHOTOMASKS IS AN ELECTRON BEAM LITHOGRAPHIC PROCESS THAT IS NEARLY THE SAME AS THE PHOTOLITHOGRAPHY USED IN THE FAB $ElNITION 0HOTOLITHOGRAPHY IS ANY PRINTING PROCESS THAT USES PHOTOGRAPHIC TECH NOLOGY %LECTRON "EAM ,ITHOGRAPHY SIMPLY SUBSTITUTES ELECTRONS FOR PHOTONS 0HOTOLITHOGRAPHY IS THE METHOD USED FOR PATTERN TRANSFER THROUGHOUT THE )# MANU FACTURING PROCESS $ElNITION ! 0HOTOMASK IS A GLASS PLATE WITH A CHROME PATTERN THAT CAN BE TRANSFERRED TO THE WAFER IN A SINGLE EXPOSURE
2ETICLE 3UBSTRATE 0REPARATION 4HIS ACCOUNT OF CHIPMAKING IS FOCUSED ON STATE OF THE ART PROCESSES )N THIS CASE RETICLES ARE USED EXCLUSIVELY SO THERE WILL NOT BE A SEPARATE DISCUSSION OF MASK MAK ING ALTHOUGH THE TECHNIQUES ARE ESSENTIALLY THE SAME $ElNITION ! 2ETICLE IS A GLASS PLATE WITH A CHROME PATTERN THAT IS USED IN A STEP AND REPEAT OR STEP AND SCAN EXPOSURE TOOL SEE #HAPTER )T CONTAINS THE PATTERN OF
#HAPTER 3UPPORT 4ECHNOLOGIES ONLY A SMALL PORTION OF THE WAFER -ULTIPLE EXPOSURES ARE REQUIRED TO TRANSFER THE PATTERN TO THE ENTIRE WAFER 4HESE TOOLS HAVE REPLACED THOSE USING PHOTOMASKS BECAUSE THE IMAGE ON THE RETICLE CAN BE OPTICALLY REDUCED PRODUCING A SMALLER SIZED IMAGE $ElNITION 4HE 1UARTZ 'LASS DISCUSSED HERE IS FUSED SILICA A HIGH PURITY FORM OF SILICON DIOXIDE 3I/ 4HE RETICLE IS MADE BY PATTERNING A CHROME COATED SUBSTRATE OF QUARTZ GLASS PLATE 4HE GLASS MUST BE DEFECT FREE EXTREMELY mAT AND HIGHLY POLISHED "UT MORE IMPOR TANT IT MUST BE TRANSPARENT TO THE ULTRAVIOLET LIGHT WAVELENGTHS USED TO EXPOSE THE PHOTORESIST !LL OF THESE REQUIREMENTS ARE WELL SATISlED BY QUARTZ GLASS ! THIN LAYER OF CHROMIUM COATS THE PLATE ON ONE SIDE ! GLUE LAYER IS OFTEN NEEDED TO ENSURE THAT THE CHROME STICKS TO THE GLASS AND AN ANTIREmECTIVE COATING IS NEEDED ON TOP 4HE TOTAL THICKNESS OF THESE lLMS IS ONLY ABOUT NM
0ATTERN 4RANSFER $ElNITION 0HOTORESIST 2ESIST IS A LIGHT SENSITIVE OR E BEAM SENSITIVE PLASTIC MATERIAL )TS FUNCTION IS SIMILAR TO THAT OF THE lLM IN A CAMERA A LIKENESS THAT WILL BECOME CLEAR IN THE NEXT FEW PARAGRAPHS 4HE CHROME IS COATED WITH A THIN LAYER OF PHOTORESIST 4HE RESIST IS SENSITIVE TO EX POSURE TO EITHER AN ELECTRON BEAM OR A LASER -OST ULTRA LARGE SCALE INTEGRATION 5,3) RETICLES ARE PRODUCED USING AN ELECTRON BEAM IN A DIRECT WRITE ELECTRON BEAM SYSTEM .OW IT IS TIME TO UTILIZE THE DIGITAL CODE PROVIDED BY THE DESIGN GROUP 4HAT CODE IS LOADED INTO THE COMPUTER THAT CONTROLS THE DIRECT WRITE TOOL 4HE LAYOUT ARTWORK IS REPRODUCED IN THE RESIST BY THE TOOL THE E BEAM IS SCANNED BACK AND FORTH ACROSS THE RESIST AND THE PLATEN ON WHICH THE GLASS PLATE IS MOUNTED MOVES UP AND DOWN 4HIS INTRICATE CONTROL SCHEME TRANSFERS THE IMAGE INTO THE RESIST %XPOSURE TO THE E BEAM OR LASER ENERGY CAUSES A CHEMICAL CHANGE IN THE PHOTORESIST 4HE PATTERN IS INVISIBLE IMMEDIATELY AFTER EXPOSURE TO THE E BEAM ! DEVELOPER SOLUTION IS NEEDED TO DISSOLVE THE EXPOSED RESIST LEAVING BEHIND THE DESIRED PATTERN IN THE RESIST .OW THE CHROME IS COVERED WITH A TEMPLATE THAT WILL ALLOW THE PATTERN TO BE TRANSFERRED TO IT 4HE NEXT STEP IS TO ETCH THE PATTERN INTO THE CHROME !N ACID IS USED THAT DOES NOT ATTACK THE RESIST BUT EASILY REMOVES THE EXPOSED CHROME ! THOROUGH RINSE IS REQUIRED AFTER ETCH FOLLOWED BY A PHOTORESIST STRIP PROCESS TO REMOVE THE TEMPLATE 4HE RETICLE IS NOW COMPLETE
0HOTOMASK AND 2ETICLE 0REPARATION
)NSPECTION AND $EFECT 2EPAIR 4HE RETICLE MUST BE FREE FROM ALL DEFECTS THAT WOULD DEGRADE ITS PERFORMANCE BEFORE IT IS SHIPPED TO THE END USER )F THERE IS THE SMALLEST IMPERFECTION IN THE PATTERN IT WILL BE PRINTED ON THE WAFER AND EVERY WAFER WILL HAVE MANY DEFECTS AS MANY AS THE NUMBER OF EXPOSURES NEEDED TO PRINT THE ENTIRE WAFER 4HIS TYPE OF DEFECT IS CALLED A REPEATING DEFECT AND IT CAN DEVASTATE MANUFACTURING YIELD 0ARTICLES ON THE RETICLE ARE ONE TYPE OF REPEATING DEFECT 0ARTICLES ARE NOT THE ONLY POSSIBLE DEFECT 0INHOLES THAT ARE LARGE ENOUGH TO AL LOW LIGHT TO LEAK THROUGH CAN BE ACCIDENTALLY ETCHED INTO THE CHROME ,UCKILY THESE DEFECTS ARE EASILY REPAIRED 4HERE ARE A VARIETY OF OTHER TYPES OF DEFECTS THAT GO BEYOND THE SCOPE OF THIS DISCUSSION !LUMINUM ALLOY &RAME
-EMBRANE
5PPER 0ELLICLE
1UARTZ GLASS 2ETICLE
,OWER 0ELLICLE #HROME 0ATTERN
&IGURE 2ETICLE WITH 0ELLICLE
!FTER ENSURING THAT THE RETICLES ARE DEFECT FREE PELLICLES ARE INSTALLED 4HE PEL LICLE IS A TRANSPARENT PLASTIC MEMBRANE STRETCHED ACROSS A RECTANGULAR FRAME THAT IS LARGER THAN THE PATTERN ON THE RETICLE 4HE FRAME SURROUNDS THE CHROME PATTERN AND IS ATTACHED TO THE GLASS SUBSTRATE 4HE PELLICLE KEEPS DUST AND DIRT AWAY FROM THE SURFACE OF THE RETICLE 7HAT ABOUT DIRT ON THE PELLICLE 4HE THICKNESS OF THE SUPPORTING FRAME HOLDS ANY PARTICLES A DISTANCE AWAY FROM THE RETICLE SUCH THAT THEY ARE OUT OF FOCUS AND THEREFORE ARE NOT REPRODUCED ON THE WAFER SURFACE .OW THAT THE PELLICLES ARE INSTALLED THE RETICLES CAN BE SHIPPED TO THE CUSTOMER AND MANUFACTURING OF THE NEW )#S CAN BEGIN
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#(!04%2
&ORMING 7ELLS
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)NTRODUCTION )N THIS CHAPTER YOU WILL LEARN v 7HAT ARE WELLS v (OW WELLS ARE FORMED IN THE WAFER v 'LASS MAKING THERMAL OXIDATION OF SILICON v 0HOTOLITHOGRAPHY PATTERNING v !DDING DOPANTS TO THE WAFER ION IMPLANTATION "EFORE WE COMMENCE OUR DISCUSSION OF THE PARTICULARS OF MAKING A CHIP A CLARI lCATION IS IN ORDER ! SO CALLED PROCESS mOW IS A RECIPE SOMETHING LIKE MAKING A SANDWICH /UR DISCUSSION IS A GENERALIZED #-/3 0ROCESS &LOW THAT CONTAINS ALL OF THE REQUIRED COMPONENTS OF THE PROCESS ! GOOD DEAL OF VARIATION IN THE ORDER OF STEPS EXISTS AS DOES THE ADDITION OR SUBTRACTION OF SOME STEPS IT ALL DEPENDS STRONGLY UPON THE DESIGN OF THE CHIP THAT IS BEING BUILT 3O IF YOU GO TO WORK AND lND THAT YOUR PRO CESS PUTS THE LETTUCE ON TOP OF THE CUCUMBERS RATHER THAN THE OTHER WAY AROUND DONT BE SURPRISED 4HE DISCUSSION CENTERS ON CHIPS THAT ARE USED IN COMPUTERS AND SIMILAR SYSTEMS 4HE TRANSISTORS MAKING UP MOST OF THE CHIP AND THE CHIPS THEMSELVES HAVE A HUGE VARIETY OF OTHER USES IN ELECTRICAL AND ELECTRONIC CIRCUITS THAT WILL NOT BE DISCUSSED 4HE COMPUTER APPLICATION IS A GOOD EXAMPLE TO USE BECAUSE IT IS EASY TO UNDERSTAND THE TRANSISTORS PRIMARY FUNCTION AS QUITE SIMPLY A SWITCH
#HAPTER &ORMING 7ELLS (OW A #OMPUTER 7ORKS (IGHLY 3IMPLIlED 6ERSION ! COMPUTER PERFORMS BILLIONS OF OPERATIONS PER SECOND USING BINARY MATH "INARY HAVING TWO PARTS MATH USES ONLY A ZERO AND A ONE IT IS CALLED BASE BUT AS YOU CAN SEE THE lGURE hv IS NOT ACTUALLY USED !LL LETTERS AND NUMBERS ARE COMPOSED OF COMBINATIONS OF ZEROS AND ONES 4HE EARLIEST COM PUTERS USED VARIOUS TYPES OF SWITCHES TO REPRESENT THE ZEROS AND ONES IF THE SWITCH WAS OFF IT COULD REPRESENT A ZERO AND THEN IF THE SWITCH WAS TURNED ON IT REPRESENTED A ONE )N MODERN COMPUTERS THE SWITCHES ARE TINY TRANSISTORS USUALLY THE lELD EFFECT TRANSISTORS &%4 THAT ARE DESCRIBED IN THIS BOOK 9ES MOST OF THE TRANSISTORS IN A COMPUTER ARE SIMPLY SWITCHES /H AND WHAT EXACTLY ARE THE hBILLIONS OF OPERATIONSv BEING PERFORMED EACH SECOND )T MERELY MEANS SWITCHING THE SWITCHES ON AND OFF /NE OPERATION IS SWITCHING A SWITCH OR GROUP OF SWITCHES DEPENDING ON THE CIRCUIT DESIGN FROM OFF TO ON OR VICE VERSA
N 7ELL
P 7ELL
&IGURE #ROSS 3ECTION OF #-/3 7ELL 3TRUCTURE
4HE COMPLEMENTARY METAL OXIDE SEMICONDUCTOR #-/3 TECHNOLOGY USES BOTH N CHANNEL AND P CHANNEL TRANSISTORS ON THE SAME CHIP 4HE NEED TO PRODUCE BOTH TYPES OF TRANSISTOR WITHIN THE SAME CHIP COMPLICATES THE MANUFACTURING PROCESS CONSIDER ABLY )T REQUIRES THAT A LOCALIZED AND VERY THIN LAYER AT THE SURFACE OF THE SILICON WAFER BE DOPED WITH IMPURITIES TO ADJUST THE ELECTRICAL PROPERTIES OF THE SILICON TO MATCH THE TYPE OF TRANSISTOR BEING CONSTRUCTED AT THAT SITE ! PROCESS WAS DEVELOPED TO PRODUCE BOTH N AND P TYPE DOPED REGIONS IN THE APPROPRIATE SPOTS CALLED THE WELLS $ElNITION ! WELL IS A CAREFULLY DElNED AREA IN THE SURFACE OF THE SILICON WAFER THAT IS DOPED WITH EITHER N TYPE OR P TYPE IMPURITIES 4HE DEPTH OF THESE DOPED REGIONS MAY BE AS LITTLE AS A FRACTION OF A MICRON MICROMETER IN TODAYS CHIPS 4HERE IS A GOOD DEAL OF VARIATION AND SOME CHIPS HAVE WELLS THAT ARE SEVERAL MICRONS DEEP &IGURE SHOWS THE STRUCTURE THAT WE WILL DISCUSS IN THIS CHAPTER 4HE PURPOSE OF THIS PROCESS IS TO CREATE REGIONS OF N AND P TYPE SILICON WITHIN THE WAFER SURFACE
)NTRODUCTION 3ILICON ON )NSULATOR 3/) 4HE CHIPMAKING INDUSTRY IS DYNAMIC )T NEVER STOPS IMPROVING ITSELF 4HIS BOOK IS A SNAPSHOT OF THE MOST CURRENT TECHNOLOGY IN USE AT THE PRESENT TIME BUT MORE INNOVATIONS ARE CONSTANTLY BEING INTRODUCED 3ILICON ON INSULATOR 3/) IS ONE OF THEM 3/) IS A TECHNIQUE THAT PUTS A LAYER OF INSULATING SILICON DIOXIDE VERY CLOSELY UNDER THE TRANSISTORS 4HIS DESIGN MORE EFFECTIVELY ISOLATES EACH TRANSISTOR ELECTRICALLY INCREASING THE CHIPS SPEED REDUCING LEAKAGE CURRENTS AND IM PROVING THE CHIPS RESISTANCE TO IONIZING RADIATION 3/) HAS BEEN USED IN A SMALL NICHE OF THE INDUSTRY FOR YEARS BUT NOW IT IS MOVING INTO THE MAINSTREAM 4HE REASON IS THAT THE LIMITS OF SILICON TECHNOLOGY ARE BEING REACHED )NNOVATION IS NEEDED TO PUSH EXISTING SILICON TECHNOLOGY BEYOND ITS CURRENT PERFORMANCE LEVELS
4HE TERM hWELLv IS A BIT MISLEADING 4HE WELLS ARE OFTEN MUCH BIGGER AROUND THAN THEY ARE DEEP SO IT DOESNT SOUND LIKE MUCH OF A WELL (OWEVER IF YOU THINK OF IT AS A REGION THAT IS DEEP COMPARED TO THE TRANSISTOR STRUCTURES IN ITS UPPER PORTIONS THEN PER HAPS IT MAKES MORE SENSE 4HE LARGE SURFACE AREA OF THE WELL IS NEEDED BECAUSE OFTEN A LARGE NUMBER OF TRANSISTORS ARE MADE IN EACH WELL 4HE WELLS ARE CREATED BY ADDING DOPANTS TO THE SILICON WAFER IN PRECISELY DElNED AREAS )N THIS CHAPTER WE WILL DISCUSS THE METHOD USED TO MAKE SURE THAT THE DOPANT ONLY GOES WHERE IT IS NEEDED AS WELL AS THE RELATED TECHNOLOGIES THAT HELP MAKE IT ALL COME TOGETHER 4HE N AND P TYPE WELLS FORM THE REGIONS WHERE P AND N CHANNEL TRANSISTORS WILL BE BUILT 9ES THE N CHANNEL TRANSISTOR IS BUILT IN THE P WELL AND VICE VERSA )F THAT SEEMS CONFUSING DONT WORRY !S THE TRANSISTOR IS BUILT THE FUNCTION OF EACH OF ITS PARTS WILL BECOME VERY CLEAR #-/3 $EVICES $YNAMIC RANDOM ACCESS MEMORY $2!- CHIPS NEED ONE TRANSISTOR AND ONE CAPACITOR FOR EACH BIT OF DATA IN MEMORY STORAGE -ANY STATIC RANDOM ACCESS MEMORY 32!- CHIPS USE SIX TRANSISTORS TO MAKE A MEMORY BIT OBVIOUSLY THE 32!- FUNCTIONS QUITE DIFFERENTLY THAN A $2!- %ACH HAS AN IMPORTANT ROLE IN COMPUTER OPERATION !NOTHER EXAMPLE OF A DIGITAL CIRCUIT ELEMENT THAT BENElTS FROM #-/3 TECHNOL OGY IS THE INVERTER ! #-/3 INVERTER CONSISTS OF TWO TRANSISTORS ONE N CHANNEL
#HAPTER &ORMING 7ELLS AND ONE P CHANNEL )N AN INVERTER A LOW VOLTAGE INPUT IS CHANGED TO A HIGH VOLTAGE OUTPUT OR VICE VERSA ! HIGH VOLTAGE OFTEN REPRESENTS A hv AND A LOW VOLTAGE REPRESENTS A hv IN LOGIC CIRCUITS .OTE THAT hLOW VOLTAGEv MEANS NEAR ZERO AND hHIGH VOLTAGEv MEANS NEAR TO THE SUPPLY VOLTAGE IN THE CIRCUIT WHICH IS IN CURRENT ADVANCED DIGITAL CHIPS ABOUT ONE VOLTNOT EXACTLY WHAT ONE WOULD EXPECT TO BE CALLED A HIGH VOLTAGE IS IT
$ElNITION /NE "IT OF DATA IN MEMORY IS A ZERO OR A ONE 4HIS TERM IS USED IN MEMORY CHIPS $ElNITION /NE "YTE IS THE COMPUTER TERM FOR EIGHT BITS "YTES ARE COMBINED TO MAKE CHARACTERS OR hWORDSv IN A PROGRAMMING LANGUAGE 4ERMINOLOGY 4IP -ICRON -ICROMETER 4HE METRIC SYSTEM IS USED FOR MEASURING DIMENSIONS ON CHIPS 4HE MICROMETER ONE MILLIONTH OF A METER ¾ n METERS OR OF A MILLIMETER IS VERY USEFUL FOR DESCRIBING STRUCTURE SIZES ON A CHIP 4HE PRACTICE OF SHORTENING THE TERM TO hMICRONv HAS EVOLVED OVER THE YEARS AND IS INTERCHANGEABLE WITH THE MORE FORMAL VERSION 3INCE THE DIMENSIONS HAVE BECOME SO SMALL ON STATE OF THE ART PARTS IT IS VERY COMMON TODAY TO SEE THE NANOMETER USED FOR LENGTH MEASUREMENTS IN ADDITION TO THE MICRON 4HE NANOMETER IS ¾ n METERS ONE BILLIONTH OF A METER OR OF A MICRON IN LENGTH 3URPRISINGLY THERE IS NO INDUSTRY SLANG FOR hNANOMETERv 4ODAY THE FAMILIAR TERM hNANOTECHNOLOGYv IS BROADLY APPLIED TO ANY TECHNOLOGY DEALING WITH MICROSCOPIC DIMENSIONS NOT NECES SARILY OF THE NANOMETER SCALE ^ -ICRON
TRANSISTORS END TO END IN MM (ALF A BILLION ON A SMALL 53 STAMP
)F DRAWN TO SCALE THIS WAFER THICKNESS WOULD BE ABOUT FEET OR ^ METERS
2OUGHLY TRANSISTORS END TO END $IAMETER OF A U HAIR
&IGURE 2ELATIVE 3IZE OF )# $EVICE &EATURES
)NTRODUCTION ! HELPFUL PERSPECTIVE IS PROVIDED BY THE DIAMETER OF A TYPICAL HUMAN HAIR ! THICK HAIR FROM A PERSONS HEAD IS ABOUT MICRONS IN DIAMETER ! lNE HAIR CAN BE AS THIN AS MICRONS !S YOU WILL SEE MANY OF THE FEATURES THAT ARE FORMED ON A CHIP ARE ABOUT ONE ONE THOUSANDTH OF THE DIAMETER OF A HAIR 4ERMINOLOGY 4IP 0RODUCT 7AFERS 4HROUGHOUT OUR DISCUSSION THE WORD hPRODUCTv WILL OFTEN BE USED TO REFER TO THE WAFERS MOVING THROUGH THE MANU FACTURING LINE )T IS STANDARD PRACTICE IN MANUFACTURING TO REFER TO WHATEVER IT IS THAT IS BEING MADE AS hPRODUCTv /F COURSE THE CHIPS THEMSELVES ARE THE lNAL PRODUCT SO IT IS /+ TO USE THE TERM FOR THEM AS WELL
0ROCESS &LOW FOR 7ELL &ORMATION 'ROW SILICON DIOXIDE ON THE WAFER SURFACE #REATE A MASK OR TEMPLATE TO DElNE THE AREAS TO BE DOPED !DD THE DOPANT SPECIES BY IMPLANTATION USING A PARTICLE BEAM MACHINE 2EMOVE THE MASKING MATERIAL (EAT THE WAFER TO PROPERLY DISTRIBUTE THE DOPANT AND REPAIR ANY DAMAGE TO THE SILICON CRYSTAL LATTICE !FTER THE WELLS ARE CREATED THE WAFER IS READY FOR THE NEXT STEP SHALLOW TRENCH ISOLA TION DISCUSSED IN #HAPTER .OTE THAT SOME PROCESSES FORM THE ISOLATING TRENCHES BEFORE CREATING THE WELLS )F THERE IS ANY ADVANTAGE TO REVERSING THE ORDER OF THESE TWO STEPS IT WILL BE FOUND IN THE DESIGN OF THE PROCESS !T ANY RATE IT DOES NOT CHANGE EITHER OF THE STEPS TO ANY SIGNIlCANT DEGREE IF THEY ARE REVERSED SO OUR DISCUSSION IS NOT AFFECTED
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)NITIAL /XIDATION 4HE BEAUTIFULLY POLISHED NEWLY MANUFACTURED BLANK WAFERS ENTER THE FAB #AREFUL PROCEDURES ARE FOLLOWED TO ENSURE THAT MINIMUM CONTAMINANTS ENTER THE FAB WITH THE WAFERS 3OMETIMES THESE WAFERS ARE CLEANED PRIOR TO USE IN A SPECIAL WET CLEAN TOOL BUT OFTEN THE WAFERS ARE KNOWN TO BE IN AN OPTIMUM STATE THAT IS ALMOST FREE OF CONTAMINATION SO THE EXTRA STEP IS NOT NECESSARY )N FACT IT IS POSSIBLE THAT AN EXTRA CLEANING RISKS ADDING CONTAMINANTS
&IGURE 3ILICON 7AFERS IN #ARRIER #ASSETTE #ONTAMINATION ,EVELS )T IS COMMON PRACTICE TO USE TERMS SUCH AS hCONTAMINATION FREE ENVIRONMENTv !S WILL BE POINTED OUT IN THIS DISCUSSION THERE ARE ALWAYS CONTAMINANTS AND IMPURITIES PRESENT IN TRACE AMOUNTS /NE OF THE GREATEST CHALLENGES IN CHIP MAKING IS TO EMPLOY DESIGNS AND MANUFACTURING STRATEGIES THAT MINIMIZE THE EFFECTS OF THE NATURAL LEVELS OF IMPURITIES THAT ARE ALWAYS PRESENT
#HAPTER &ORMING 7ELLS $ElNITION $IELECTRIC IS THE NAME OF A SUBSTANCE THAT STRONGLY RESISTS THE mOW OF ELEC TRICAL CURRENT AN INSULATOR 3ILICON DIOXIDE IS A MEMBER OF THIS FAMILY OF MATERIALS $ElNITION 4HERMAL /XIDE IS SILICON DIOXIDE 3I/ PRODUCED BY THE THERMAL OXIDA TION OF SILICON 0URPOSE 4HERMAL OXIDE IS A DIELECTRIC lLM AN ELECTRICAL INSULATOR )T IS USED IN CHIP STRUCTURES THAT INSULATE CONDUCTORS MASK IMPLANTS AND ETCHES AND PERFORMS OTHER PROTECTIVE FUNCTIONS $ISCUSSION 4HE MATERIAL PROPERTIES OF THERMAL OXIDE ARE EXTREMELY UNIFORM CHEMICALLY CONSISTENT AND REPRODUCIBLE 4HIS HIGH QUALITY lLM PERFORMS CRITICAL FUNCTIONS ON THE CHIP AND WILL BE DISCUSSED LATER ! SILICON DIOXIDE lLM CALLED NATIVE OXIDE WILL FORM NATURALLY ON SILICON WHEN IT IS EXPOSED TO THE AIR BUT IN THAT CASE ONLY A VERY THIN NONUNIFORM LAYER FORMS 4HE THER MAL OXIDATION PROCESS PRODUCES A VERY UNIFORM lLM WITH THE PRECISELY CONTROLLABLE THICKNESS AND MATERIAL PROPERTIES NEEDED IN CHIP FABRICATION TECHNOLOGY 4HE "ASIC #HEMICAL 2EACTION 3I / m 3I/ SILICON AND OXYGEN FORM SILICON DIOXIDE 7HAT #OLOR IS THE 7AFER /NE OF THE INTERESTING THINGS ABOUT THE THIN lLMS ON THE WAFER IS THEIR COLOR VARIATION -ANY OF THE lLMS DEPOSITED ON THE WAFER ARE TRANSPARENT $IFFER ENT THICKNESSES OF lLMS AND STACKED lLMS CAUSE THE WAFER TO CHANGE COLOR THROUGHOUT THE PROCESS 0HOTORESIST CAN PRODUCE A BEAUTIFUL RAINBOW OF COLOR UNFORTUNATELY IN THIS CASE IT IS USUALLY A SIGNAL THAT SOMETHING HAS GONE WRONG )N THE EARLY YEARS OF THE INDUSTRY THE MACHINES NEEDED TO MEASURE ALL OF THE VARIETIES OF lLM THICKNESSES REQUIRED FOR CHIPMAKING HAD NOT YET BEEN INVENTED 3O THE lLM THICKNESS WAS CHECKED AFTER OXIDATION OR DEPOSITION BY HOLDING THE WAFER UP TO A COLOR CHART HANGING ON THE WALL CLOSE TO THE TOOL 4HE OPERATOR HAD TO BE ABLE TO COMPARE THE WAFER COLOR TO THE EXAMPLES SHOWN ON THE CHART TO DETERMINE THE lLM THICKNESS 3OME OF THE TEXTS FOUND IN THE BIBLIOGRAPHY CONTAIN A TABLE LISTING THE COLORS OF VARIOUS lLMS BASED ON THEIR THICKNESS
)NITIAL /XIDATION ! &AMILIAR %XAMPLE 2UST IS THE PRODUCT OF A CHEMICAL REACTION )RON OXIDIZES OR hRUSTSv IN THE PRESENCE OF OXYGEN AND MOISTURE LEAVING A COATING OF IRON OXIDE &E/ ON THE SURFACE OF THE IRON 3IMILARLY THE PROCESS OF OXIDIZING THE SILICON WAFER LEAVES A COATING OF 3I/ COVERING THE WAFER 7HEN CHARCOAL IS BURNED AN OXIDATION REACTION IS TAKING PLACE TOO 4HE FUEL IS PRIMARILY COMPOSED OF CARBON WHICH REACTS WITH OXYGEN IN THE AIR TO FORM GASEOUS OXIDES CARBON MONOXIDE #/ AND CARBON DIOXIDE #/ 4HE REACTION IS EXOTHERMIC IT GIVES OFF HEAT ALLOWING THE PRODUCTION OF ESSENTIAL HAMBURGERS AND HOT DOGS
)T IS INTERESTING TO NOTE THAT THE EASE WITH WHICH A SILICON DIOXIDE lLM CAN BE FORMED ON SILICON AS WELL AS ITS ELECTRICAL PROPERTIES AND STABILITY WERE IMPORTANT FACTORS IN THE RAPID TRANSITION FROM GERMANIUM TO SILICON IN THE EARLY YEARS OF THE SEMICONDUCTOR INDUSTRY /XIDE ALSO HAS OTHER ADVANTAGEOUS PROPERTIES LIKE THE ABILITY TO BLOCK THE IMPLANTATION OF DOPANTS WHICH WILL BE DISCUSSED LATER 3ILICON DIOXIDE IS ACTUALLY A VERY FAMILIAR SUBSTANCE IT IS THE PRINCIPAL COMPO NENT OF GLASS AND SEVERAL OTHER ITEMS MENTIONED IN THE NEXT SIDEBAR "OTH hOXIDEv AND hGLASSv ARE INDUSTRY SLANG TERMS FOR SILICON DIOXIDE !NOTHER &AMILIAR %XAMPLE 3AND IS PERHAPS THE MOST FAMILIAR EXAMPLE OF NATURALLY OCCURRING SILICON DIOX IDE -UCH OF THE SAND IN THE WORLD IS PRINCIPALLY COMPOSED OF SILICON DIOXIDE SOME OF QUITE HIGH PURITY !NOTHER COMMON NATURALLY OCCURRING FORM OF 3I/ IS QUARTZ A SINGLE CRYSTAL FORM !N IMPORTANT INDUSTRIAL PRODUCT IS hQUARTZ GLASS v SOMETIMES MADE BY MELTING HIGH PURITY QUARTZ CRYSTALS BUT ALSO CAN BE PRODUCED TODAY FROM MELTING VERY HIGH PURITY SYNTHETIC SILICON DIOXIDE 1UARTZ GLASS IS WIDELY USED IN HIGH TEMPERATURE ENVIRONMENTS INCLUDING MANY APPLICATIONS IN THE SEMICONDUCTOR INDUSTRY 4HE THERMAL OXIDE lLM GROWN ON SILICON WAFERS IS CHEMICALLY SIMILAR TO QUARTZ GLASS 3EVERAL GEMSTONES SUCH AS OPAL AND AMETHYST ARE ALSO FORMS OF SILICON DIOX IDE #OMMON BOTTLE AND WINDOW GLASSES ARE ABOUT SILICON DIOXIDE
$IELECTRIC MATERIALS ARE THE COMPLEMENT TO CONDUCTING MATERIALS THAT ALLOW THE CREATION OF ELECTRICAL COMPONENTS IN THE CIRCUIT 3EVERAL DIELECTRIC MATERIALS ARE NEEDED TO MAKE CHIPS AND EACH WILL BE EXPLAINED AS IT IS ENCOUNTERED
#HAPTER &ORMING 7ELLS 4HE CRITICAL VALUE OF OXIDE IS THAT IT IS A HARD STABLE DIELECTRIC 3INCE ELECTRICAL CIRCUITS ARE BEING BUILT ON THE CHIP IT WILL CERTAINLY BE NECESSARY TO SEPARATE CONDUCT ING MATERIALS FROM EACH OTHER WITH AN INSULATOR TO AVOID AN ELECTRICAL SHORT 2ECALL THAT THE CHIP IS BUILT IN LAYERS AND INSULATING LAYERS SEPARATE CONDUCTING LAYERS AS REQUIRED BY ANY ELECTRICAL CIRCUIT $IELECTRICS ALSO FORM THE SEPARATING MEDIUM BETWEEN THE PLATES OF A CAPACITOR AND PLAY A CRITICAL ROLE IN THE FUNCTION OF THE TRANSISTORS AND OTHER COMPONENTS ON THE CHIP 4HE ELECTRICAL PROPERTIES OF OXIDE ARE IMPORTANT BUT IT HAS OTHER USES TOO )T MAY SERVE AS AN IMPLANT MASK BLOCKING THE PATH OF DOPANT PARTICLES THAT ARE SHOT AT THE WAFER IN AN ION IMPLANTER DISCUSSED LATER IN THIS CHAPTER !NOTHER IMPORTANT USE IS AS AN ETCH MASK PROTECTING PORTIONS OF A lLM FROM ATTACK BY ETCHANT CHEMICALS 7HAT FUNCTION IS THE OXIDE COATING PERFORMING AT THIS POINT IN THE PROCESS $ElNITION 4HE !CTIVE !REA IS THE REGION ON THE SURFACE OF THE WAFER WHERE THE TRAN SISTORSTHE hACTIVE DEVICESvWILL BE BUILT )T MUST BE KEPT AS FREE AS POSSIBLE FROM CONTAMINATION AND DAMAGE +EY 0OINT 4HE INITIAL OXIDE IS A PROTECTIVE COATING !LTHOUGH THE lLM COVERS THE WHOLE CHIP THE FOCUS OF ITS USE IS IN THE hACTIVE AREAv $ElNITION 3ACRIlCIAL /XIDE IS THE COMMON NAME FOR A THERMAL OXIDE THAT WILL BE REMOVED LATER IN THE PROCESS 3ACRIlCIAL OXIDES ARE USED AS PROTECTIVE LAYERS OR OCCASIONALLY TO REMOVE CONTAMINANTS FROM THE SILICON SURFACE 4HE INITIAL OXIDA TION STEP PRODUCES A SACRIlCIAL OXIDE THAT IS ETCHED OFF AFTER THE WELLS HAVE BEEN FORMED 4HE INITIAL OXIDE ALSO INmUENCES THE AMOUNT OF DOPANT ENTERING THE WAFER FROM THE IMPLANTER 4HE THICKNESS IS CAREFULLY CONTROLLED SO THAT THE DEGREE OF SCREENING IS PREDICTABLE AND UNIFORM !NOTHER IMPORTANT FUNCTION OF THE INITIAL OXIDE IS TO PREVENT hKNOCK ONv OF SURFACE CONTAMINANTS AN EFFECT WHERE THE IMPACTING IONS FROM THE IMPLANTER PUSH UNWANTED IMPURITIES INTO THE SILICON CRYSTAL WHERE THEY CAN MOVE AROUND AND DAMAGE THE TRANSISTORS 4HE )MPLANTER &OR CLARIlCATION IT SHOULD BE MENTIONED THAT THE IMPLANTER IS A PARTICLE ACCELERATOR THAT SHOOTS CHARGED PARTICLES AT THE WAFER DRIVING THEM INTO THE SURFACE 4HE DETAILS OF IMPLANTATION WILL BE DISCUSSED IN 3ECTION
)NITIAL /XIDATION 4HE /XIDATION 0ROCESS $ElNITION 4HERMAL /XIDATION OF 3ILICON IS THE HIGH TEMPERATURE REACTION OF THE SILICON WAFER WITH OXYGEN WATER VAPOR ANDOR NITROGEN OXIDES 4HIS IS USUALLY THE lRST OPERATION TO BE PERFORMED ON THE WAFERS IN THE FAB 0URPOSE 4O FORM THERMAL OXIDE SILICON DIOXIDE PRODUCED BY DIRECT OXIDATION OF SILICON AT HIGH TEMPERATURE 0ROCESS GASES FLOW DOWN OVER WAFERS
&IGURE /XIDATION &URNACE 6ERTICAL 4UBE &URNACE
%LECTRICALLY HEATED FURNACE
1UARTZ GLASS TUBE
7AFER CARRIER RAISED INTO FURNACE
1UARTZ 'LASS CHAMBER
&IGURE 2APID 4HERMAL 0ROCESSOR 0ROCESS 'ASES
7AFER
"ANKS OF HIGH INTENSITY LAMPS
$ISCUSSION 4HIS OXIDE MAY HAVE OTHER NAMES SUCH AS SACRIlCIAL OXIDE OR PAD OXIDE AND CAN DO SEVERAL THINGS DEPENDING UPON THE PROCESS 3OME OF THE SPECIlCS WILL BE DISCUSSED IN THIS AND SUBSEQUENT SECTIONS
#HAPTER &ORMING 7ELLS )NITIAL /XIDATION 0ROCESS &LOW &URNACE OXIDATION )NSPECTION ! WET CLEAN PRECEDES MOST lLM GROWTHS OR DEPOSITION STEPS 5SING VARIOUS COMBINATIONS OF ACIDS BASES OXIDIZERS AND $) WATER SURFACE CONTAMINANTS ARE REMOVED 4HE TEMPERATURE IS VERY HIGH DURING THE MAJORITY OF THE OXIDATION OR OTHER lLM DEPOSITION OPERATIONS UNWANTED CHEMICAL IMPURITIES CAN MOVE AROUND IN THE WAFER TO POINTS WHERE THEY WOULD RUIN MANY TRANSISTORS 4HE PHENOMENON IS CALLED DIFFUSION WHICH IS THE ENERGETIC VIBRATION OF THE ATOMS IN THE CRYSTAL AS WELL AS THE EXPANDED DIMENSIONS OF THE CRYSTAL AT HIGH TEMPERATURE CREATE AN ENVIRONMENT WHERE STRAY ATOMS WILL BE MOVED AROUND IN THE CRYSTAL LATTICE
$ISCUSSION 4HERMAL OXIDATION IN A TUBE FURNACE IS DONE BY PLACING THE WAFERS IN THE FURNACE WHILE IT IS mUSHED WITH GAS OFTEN NITROGEN TO DISPLACE THE AIR 4HEN OXYGEN OR WATER VAPOR IS INTRODUCED WHILE HEATING THE WAFERS TO TYPICALLY SOMEWHERE IN THE RANGE OF # TO # DEPENDING ON THE PROCESS REQUIREMENTS ! FURNACE OXIDATION REQUIRES THAT THE WAFERS BE PLACED IN SPECIAL TEMPERATURE RESISTANT HOLDERS CALLED BOATS WHICH ARE SLOWLY INSERTED INTO THE FURNACE "ATCHES OF OR MORE WAFERS ARE PROCESSED AT THE SAME TIME 4HE FURNACE IS HEATED BY ELECTRICAL RESISTANCE HEATERS 4HE SLOW HEATING AND COOLING OF THE WAFERS TEMPERATURE RAMPING IS CRITICAL TO THE PROCESS TO AVOID THERMAL SHOCK WHICH WOULD WARP THE WAFERS AND DAMAGE THE CRYSTAL STRUCTURE 3OME PROCESSING CYCLES ARE QUITE LONG AND OFTEN WAFERS AT OPPOSITE ENDS OF THE FURNACE DIS PLAY SOME VARIATION IN lLM CHARACTERISTICS !NOTHER TYPE OF HIGH TEMPERATURE TOOL IS CALLED A RAPID THERMAL PROCESSOR 240 4HE 240 IS A hSINGLE WAFERv SYSTEM MEANING THAT IT PROCESSES ONLY ONE WAFER AT A TIME 4HE WAFER IS RAPIDLY HEATED WITH HIGH INTENSITY LAMPS 4HE PROCESS GASES IN THIS CASE OXYGEN OR WATER VAPOR ARE INTRODUCED WHEN THE WAFER REACHES THE PRESCRIBED TEMPERATURE !FTER THE lLM IS GROWN THE LAMPS ARE EXTINGUISHED AND THE PROCESS GASES ARE TURNED OFF 7ATER COOLED WAFER PLATENS OR A mOOD OF NITROGEN GAS MAY BE USED TO HELP RAPIDLY CARRY HEAT AWAY FROM THE WAFER ! TYPICAL 240 SYSTEM WILL HEAT THE WAFER TO # AND COOL IT BACK DOWN TO ROOM TEMPERATURE IN LESS THAN ONE MINUTE 4HE ISSUE OF THROUGHPUT IS VERY IMPORTANT IN THE MANUFACTURING ENVIRONMENT ! LARGE NUMBER OF WAFERS MUST BE PROCESSED IN A GIVEN AMOUNT OF TIME IN ORDER TO
)NITIAL /XIDATION MINIMIZE COSTS 4HE COMPETITION BETWEEN BATCH PROCESSORS AND SINGLE WAFER PROCES SORS HAS ALWAYS BEEN lERCE NOT ONLY BECAUSE OF THROUGHPUT BUT ALSO THE MANY OTHER IMPORTANT PROCESS SPECIlCATIONS !N INTERESTING VARIETY OF BOTH OF THESE TYPES OF PROCESSOR AS WELL AS SOME INNOVATIVE CROSS BREEDS THAT COMBINE ASPECTS OF BOTH ARE FOUND IN FABS TODAY 4HERMAL "UDGET 4HERMAL BUDGET IS THE TERM THAT REFERS TO THE AMOUNT OF HEAT ENERGY THAT THE WAFER WILL TOLERATE DURING THE ENTIRE PROCESS 4HE DEVICES BEING BUILT ON THE WAFER WILL NOT TOLERATE HIGH TEMPERATURES LATER IN THE PROCESS &OR EXAMPLE WHEN METAL IS DEPOSITED ON THE WAFER LATER IN THE PROCESS THAT METAL WILL DEFORM OR REACT WITH ITS SURROUNDING MATERIALS AT ONLY A FEW HUNDRED DEGREES #ELSIUS 4HERMAL OXIDE IS GROWN AT ABOUT # #LEARLY IT WILL NOT BE POS SIBLE TO GROW AN OXIDE ON THE WAFER AFTER METAL HAS BEEN DEPOSITED WITHOUT RUINING THE DEVICES 4EMPERATURE LIMITATIONS WILL BE POINTED OUT THROUGHOUT OUR DISCUSSION
)NSPECTION $URING THE INSPECTION PHASE OF THE PROCESS MEASUREMENTS ARE MADE TO SEE THAT THE lLM THICKNESS IS CORRECT ACCORDING TO THE DESIGN SPECIlCATIONS FOR THE CHIP 4HE TERM hIN SPEC v IS INDUSTRY SLANG FOR A PROPERLY DONE PROCESSING STEP 4HE DEPOSITION STEPS REQUIRE VERY CLOSE ADHERENCE TO lLM THICKNESS AND CROSS WAFER THICKNESS UNIFORMITY SPECIlCATIONS !N EXAMPLE OF THE INITIAL OXIDE THICKNESS USED FOR SOME STATE OF THE ART #-/3 DEVICES IS NANOMETERS WHICH MAY ALSO BE EXPRESSED AS !NGSTROMS $ElNITION /NE !NGSTROM ª ALSO CALLED THE !NGSTROM UNIT IS ¾ n METERS IN LENGTH ONE TEN BILLIONTH OF A METER OR ONE TEN THOUSANDTH OF A MICRON )T MAY ALSO BE EXPRESSED AS ONE TENTH OF A NANOMETER 2ECALL THAT A NANOMETER IS ¾ n METERS OR ONE BILLIONTH OF A METER 4HE !NGSTROM 5NIT 4HE !NGSTROM UNIT IS NAMED AFTER !NDERS * !NGSTRM A 3WEDISH PHYSICIST !T lRST GLANCE IT SEEMS TO BE A CUMBERSOME AND ANNOYING UNIT OF MEASURE BECAUSE IT IS INCONSISTENT WITH THE STANDARDIZED UNITS OF MEASURE LIKE THE MICRON AND NANOMETER ALL OF WHICH ARE SPACED THREE ORDERS OF MAGNITUDE APARTTHAT IS THE NEXT SMALLER UNIT IS TH OF THE LARGER ONE DIVIDE THE MILLIMETER INTO PARTS AND EACH ONE IS A MICRON IN LENGTH
#HAPTER &ORMING 7ELLS (OWEVER THE !NGSTROM UNIT HAS SPECIAL PHYSICAL MEANING THE RADII OF ALL ATOMS ARE APPROXIMATELY ONE OR TWO !NGSTROM UNITS !CCORDING TO THE 3AR GENT 7ELSH 0ERIODIC 4ABLE THE LARGEST ATOMIC RADIUS IS &RANCIUM AT ª THE SMALLEST IS .EON AT ª )T IS ESPECIALLY MEANINGFUL FOR CHIPMAKING SINCE THE lLMS DEPOSITED ON THE WAFER ARE EXTREMELY THIN 4HIS FACT IS ILLUSTRATED IN THE DISCUSSION OF THE 'ATE $IELECTRIC lLM FOUND IN #HAPTER
)MPORTANT &ILM #HARACTERISTICS 4HICKNESS 4HE EXACT OXIDE lLM THICKNESS IS SPECIlED SO THAT THE IMPLANTATION SCREENING EFFECT OF THE OXIDE IS CONSISTENT FROM WAFER TO WAFER AND BATCH TO BATCH WHILE STILL PROVIDING ENOUGH PROTECTION TO THE UNDERLYING SILICON 5NIFORMITY 4HE WAFER WILL HAVE MANY INDIVIDUAL CHIPS ON IT AND THE GOAL IS FOR EACH ONE TO OPERATE IDENTICALLY &OR THAT TO HAPPEN THE CROSS WAFER lLM THICKNESS MUST BE KEPT WITHIN TIGHT LIMITS !S THE READER MIGHT EXPECT A LARGE NUMBER OF PRODUCT WAFERS IS NOT COMMIT TED TO A PROCESSING TOOL WITHOUT DOUBLE CHECKING THAT IT IS WORKING PROPERLY 4HESE TESTS ARE PERFORMED ON A TIMETABLE THAT VARIES FROM FAB TO FAB BUT MONITORING THE TOOLS IS A NECESSITY 3OME OF THE COMMON NAMES FOR THESE WAFERS ARE TEST WAFERS PILOT WAFERS OR MONITOR WAFERS )T IS NOT NECESSARY FOR THIS DISCUSSION TO INCLUDE THE PROCEDURES INVOLVED WITH THESE WAFERS 3UFlCE TO SAY THAT THEY ARE PROCESSED IN THE STANDARD MANNER INSPECTED MEASURED AND IF ALL IS WELL THEN LARGE BATCHES OF PRODUCT ARE COMMITTED TO THE TOOL
3%#4)/.
0HOTOLITHOGRAPHY )NTRODUCTION $ElNITION ,ITHOGRAPHY IS A PRINTING PROCESS $ElNITION 0HOTOLITHOGRAPHY IS A PRINTING PROCESS THAT USES PHOTOGRAPHIC TECHNIQUES TO TRANSFER A PATTERN FROM A PHOTOMASK OR RETICLE TO A COATING OF PHOTOSENSITIVE MATERIAL CALLED PHOTORESIST ON THE WAFER SURFACE $ElNITION 0HOTORESIST RESIST IS A LIGHT SENSITIVE PLASTIC MATERIAL THAT IS DISSOLVED IN A SOLVENT TO FORM A SOLUTION 4HE RESIST IS DISPENSED ONTO THE WAFER IN THE FORM OF A LIQUID THEN STABILIZED SOLIDIlED BY A BAKING STEP THAT ALSO AFFECTS THE PHOTOSEN SITIVITY AND SOLUBILITY IN DEVELOPER SOLUTION AS DESCRIBED LATER IN THIS SECTION -OST PHOTORESIST IS SENSITIVE TO ULTRAVIOLET LIGHT +EY 0OINT 4HE PROCESS OF WAFER PATTERNING IS NOW UNDER WAY "EFORE GETTING INTO THE DETAILS OF THE PATTERNING PROCESS TAKE A LOOK AT &IGURE
&IGURE 0ATTERNED 7AFER
#HAPTER &ORMING 7ELLS 4O THE NAKED EYE THE PATTERNED WAFER LOOKS LIKE A BUNCH OF SMALL SQUARES OR RECTANGLES (OWEVER WHEN LOOKING UNDER MAGNIlCATION THE REAL DETAILS BECOME VIS IBLE 4HE PATTERN THAT IS TRANSFERRED TO THE WAFER IS FOUND ON THE RETICLE 2ECALL THAT THE RETICLE MAY HAVE THE PATTERN FOR ONE DIE OR MANY DIE DEPENDING ON THEIR SIZE AND THE SIZE OF THE EXPOSURE lELD OF THE IMAGING TOOL STEPPER 4HE TERMS hDIEv AND hCHIPv ARE USED INTERCHANGEABLY THROUGHOUT THIS DISCUSSION /NE RETICLE IS REQUIRED FOR EACH LAYER THAT NEEDS A MASK FOR IMPLANTING OR ETCHING 4HE PATTERN FOR MOST LAYERS APPEARS TO BE AN UNCOMPLICATED SET OF SQUARES LINES AND RECTANGLES ON THE RETICLE )T IS IMPRES SIVE THAT THESE SIMPLE BITS COMBINE TO MAKE SUCH A SOPHISTICATED DEVICE $IE VS $ICE 4HE PLURAL OF hDIEv IS hDICEv SEE ANY DICTIONARY (OWEVER USAGE IN THE INDUSTRY HAS EVOLVED AWAY FROM USE OF THE PLURAL FORM AND hDIEv IS COMMONLY USED FOR BOTH SINGULAR AND PLURAL
4HE COMPARATIVELY WIDE SPACES BETWEEN EACH DIE ARE CALLED SCRIBE LINES OR STREETS 4HESE SPACES MUST BE RATHER WIDE BECAUSE THE DIE ARE CUT APART WITH A DIAMOND SAW 4HE BLADE IS MADE AS THIN AS POSSIBLE BUT IT IS STILL GIGANTIC COMPARED TO THE FEATURES ON THE CHIP SEE #HAPTER 0HOTOLITHOGRAPHY 0ROCESS &LOW
#OAT 3PIN A 3URFACE 0REPARATION I 6ACUUM DEHYDRATION BAKE II (-$3 HEXAMETHYLDISILAZANE APPLICATION B 3PIN RESIST APPLICATION C 3OFT BAKE
%XPOSE 3TEP $EVELOP A !PPLY DEVELOPER SOLUTION B 0OST DEVELOP RINSE !FTER $EVELOP )NSPECTION !$)
0HOTOLITHOGRAPHY 5LTRA 6IOLET ,IGHT
'LASS PLATE #HROME PATTERN 0HOTORESIST
%XPOSURE
3ILICON $IOXIDE 3ILICON 7AFER
$EVELOPMENT
%TCH
3TRIP 2ESIST
&IGURE 4HE 7AFER 0ATTERNING 0ROCESS 4HE 9ELLOW 2OOM .OW WE ENTER THE YELLOW ROOM 3INCE PHOTORESIST IS SENSITIVE TO ULTRAVIOLET 56 LIGHT THE AREA OF THE FAB WHERE IT IS PROCESSED MUST BE FREE OF 56 6ISIBLE OR WHITE LIGHT THAT WE ARE ALL FAMILIAR WITH CONTAINS 56 AT THE HIGH FREQUENCY END THE BLUE END OF THE SPECTRUM SO IT CANNOT BE USED TO ILLUMINATE THE PHOTOLITHOGRAPHY PROCESSING AREA #UTTING OFF THE UPPER END OF THE SPECTRUM CHANGES THE COLOR OF THE LIGHT AND MAKES EVERYTHING LOOK YELLOW 7HAT WOULD HAPPEN IF WHITE LIGHT GOT INTO THE PHOTO AREA .O ONE WOULD KNOW THERE WAS A PROBLEM UNTIL THE WAFERS WERE PUT INTO THE DEVELOPER SOLU TION !LL OF THE RESIST WOULD DISSOLVE IN THE DEVELOPER LEAVING NO PATTERN ON THE WAFER 7HY DOES THAT HAPPEN 2EAD ON
$ElNITION !N )MPLANT -ASK IS A PATTERN CREATED IN PHOTORESIST OR OTHER MASKING MATERIAL 0URPOSE !N IMPLANT MASK ALLOWS THE INTRODUCTION OF DOPANTS FROM AN IMPLANTER TO ENTER ONLY THE SPECIlED AREAS OF THE WAFER 4HE RESIST FORMS A COMPARATIVELY THICK LAYER OF PLASTIC THAT ABSORBS THE SPEEDING IONS OR NEUTRALS SO THAT THEY ARE UNABLE TO REACH THE SURFACE OF THE SILICON $OPANTS ARE USED TO CREATE THE TRANSISTORS AND SOME OF THE ELECTRICAL COMPONENTS OF THE CHIP 4HE DOPANTS MUST BE PLACED PRECISELY IN THE CORRECT AREAS FOR THE COM PONENTS TO WORK
#HAPTER &ORMING 7ELLS
#OAT 3PIN 3URFACE 0REPARATION 7HEN THE WAFERS ARRIVE AT PHOTOLITHOGRAPHY PHOTO THEY ENTER A LOW PRESSURE BAKE OVEN AND ARE TREATED TO A hSAUNAv OF HOT DRY NITROGEN GAS TO DRIVE OFF ANY MOISTURE 4HEN HEXAMETHYLDISILAZANE (-$3 IS DISPENSED INTO THE CHAMBER IN VAPOR FORM WHERE IT COATS THE WAFERS 4HE (-$3 FORMS AN IMPORTANT hGLUE LAYERv THAT ENSURES THE PHOTORESIST WILL STICK TO THE WAFERS 3URFACE PREPARATION IS ALWAYS A MAJOR ISSUE IN CHIPMAKING 7E WOULD BE IN REAL TROUBLE IF THE LAYERS DIDNT STICK TO EACH OTHER 2ESIST !PPLICATION 4HE PROCESS OF COATING THE TOP OF THE WAFER WITH PHOTORESIST IS SOMETIMES CALLED SPIN SIMPLY BECAUSE THE TOOL THAT PUTS ON THE RESIST SPINS THE WAFER AROUND 4HE TOOL HOLDS THE WAFER ON A SPINNING VACUUM CHUCK 4HE RESIST IS DISPENSED ONTO THE CENTER OF THE WAFER THROUGH A TUBE AND IS IMMEDIATELY mUNG OFF SIDEWAYS BECAUSE THE WAFER IS SPINNING AT A RATHER HIGH SPEED "ELIEVE IT OR NOT THAT IS THE IDEA 4HE SPIN SPEED IS THE PRINCIPLE DETERMINANT OF THE THICKNESS OF THE RESIST THAT IS LEFT ON THE WAFER RESIST VIS COSITY IS ALSO AN IMPORTANT THICKNESS FACTOR IT IS OFTEN THE THICKNESS OF PANCAKE SYRUP OR ENGINE OIL &IGURE SHOWS A SPINNER
&IGURE 0HOTORESIST #OATER 3PINNER
3OFT "AKE !FTER THE RESIST IS APPLIED TO THE WAFER SPIN IT GOES TO A HOTPLATE FOR A hSOFT BAKEv AT ABOUT # -OST OF THE SOLVENT IS DRIVEN OFF LEAVING A STICKY SEMISOLID THAT SERVES AS A KIND OF PHOTOGRAPHIC lLM 4HEN THE WAFER MOVES TO THE STEPPER FOR EXPOSURE
0HOTOLITHOGRAPHY
%XPOSURE 3TEP $ElNITION %XPOSURE IS THE PROCESS OF SHINING ULTRAVIOLET LIGHT ONTO THE WAFER 4HE WAFER IS EXPOSED TO ULTRAVIOLET LIGHT JUST AS THE lLM IN A CAMERA IS EXPOSED TO VIS IBLE LIGHT 4HE STEPPER IS AN INCREDIBLY SOPHISTICATED DEVICE 4HE NAME hSTEPPERv COMES FROM THE WAY THE MACHINE PERFORMS ITS JOB OF EXPOSING THE WAFER TO 56 LIGHT ! SQUARE OR RECTANGULAR REGION OF A FEW SQUARE CENTIMETERS IS EXPOSED AT A TIME 4HE STEPPER PHYSICALLY MOVES OR hSTEPSv THE WAFER IN PREPARATION FOR THE NEXT EXPOSURE 7ATCHING THE MACHINE IN ACTION IS FUN 4HE WAFER IS POSITIONED FOR THE lRST EXPOSURE THE SHUTTER OPENS FOR A SECOND OR LESS ALLOWING THE 56 LIGHT TO SHINE ON THE WAFER 4HEN THE WAFER IS SUDDENLY MOVED A SHORT DISTANCE FOLLOWED BY ANOTHER mASH OF LIGHT 4HE PROCESS CONTINUES STEP BY STEP BACK AND FORTH ACROSS THE WAFER UNTIL THE ENTIRE SURFACE IS EXPOSED 4HERE CAN BE A HUNDRED OR MORE STEPS NEEDED TO EXPOSE AN ENTIRE WAFER 7HAT IS TRULY AMAZING ABOUT THE STEPPER IS THE EXTREME PRECISION WITH WHICH IT MOVES THE WAFER FOR EACH EXPOSURE 2EMEMBER THAT EACH LAYER REQUIRED TO MAKE A CHIP MUST BE PLACED EXACTLY ON TOP OF THE LAST LAYER OR EVERYTHING WILL BE JUMBLED UP AND THE DEVICES WILL NOT WORK 4HE TOLERANCE FOR ALIGNMENT OF THE WAFER IS MEASURED IN NANOMETERS FOR TODAYS DEVICES REQUIRING THE USE OF LASERS TO DETERMINE THE POSITION OF THE VACUUM CHUCK ASSEMBLY THAT HOLDS THE WAFER )N MORE FAMILIAR TERMS THE STEPPER POSITIONS THE WAFER WITH A TOLERANCE OF CLOSER THAN OF THE THICKNESS OF A HAIR 4HATS PRECISION 4HE STEPPER IS ESSENTIALLY TAKING A PICTURE OF THE RETICLE 4HE lLM IN WHICH THE PICTURE WILL BE DEVELOPED IS THE PHOTORESIST ON TOP OF THE WAFER
&IGURE 2ETICLE 0ROJECTED ONTO 7AFER
#HAPTER &ORMING 7ELLS $ElNITION 4HE %XPOSURE &IELD OR SIMPLY THE lELD IS THE AREA ON THE WAFER SURFACE THAT IS EXPOSED TO 56 LIGHT AT EACH EXPOSURE 4HE MAJORITY OF STEPPERS IN TODAYS STATE OF THE ART FABS USE A SCANNING TECHNIQUE THAT SWEEPS THE LIGHT QUICKLY ACROSS THE lELD 4HESE TOOLS ARE CALLED hSCANNERSv AND USE A STEP AND SCAN TECHNIQUE 4HE TERM hmASHv IS ANOTHER SLANG TERM FOR THE EXPOSURE lELD THAT APPLIES TO STEPPERS THAT EXPOSE THE ENTIRE AREA OF INTEREST AS IF A CAMERA SHUTTER OPENED AND CLOSED 4HIS STEPPER TECHNOLOGY DOMINATED THE INDUSTRY FOR MANY YEARS AND IS STILL IN USE TODAY 56 3OURCE
2ETICLE 8 2EDUCTION ,ENS
&IGURE 3TEPPER 0RINTS )MAGE IN 2ESIST
$EVELOP $ElNITION $EIONIZED 7ATER $) 7ATER IS WATER THAT HAS BEEN PROCESSED TO REMOVE IMPURITIES ESPECIALLY THOSE IN AN IONIZED STATE SUCH AS SODIUM .A AND CALCIUM #A 7HEN WATER IS NEEDED ONLY $) WATER IS PURE ENOUGH TO BE USED IN THE CHIP MANUFACTURING PROCESS $EVELOPING THE PATTERN IN THE RESIST IS VERY MUCH LIKE DEVELOPING THE lLM FROM A CAMERA %XPOSURE TO 56 LIGHT CHEMICALLY CHANGES THE RESIST ,IQUID DEVELOPER SOLU TION IS DISPENSED ON THE RESIST IT DISSOLVES AWAY ONLY THE AREAS OF RESIST THAT WERE EXPOSED TO 56 LIGHT 4HEN A THOROUGH RINSE WITH $) WATER REMOVES ANY LEFTOVER CHEMICALS AND LEAVES A PRECISE PATTERN BEHIND $EVELOPMENT TAKES PLACE IN ANOTHER TOOL THAT SPINS THE WAFER ON A VACUUM CHUCK TO IMPROVE THE CONSISTENCY OF CHEMICAL DISTRIBUTION
0HOTOLITHOGRAPHY )N THIS CASE THE REMAINING RESIST IS THE PROTECTIVE MASK THAT BLOCKS THE IMPLANT /NLY THE OPEN AREAS IN THE RESIST WILL RECEIVE DOPANT
!FTER $EVELOP )NSPECT !$) 4HE ENTIRE MANUFACTURING PROCESS IS INTERSPERSED WITH INSPECTIONS OF THE WAFERS TO CHECK CRITICAL DIMENSIONS AND TO CATCH DEFECTS BEFORE THEY RUIN THE PRODUCT 4HIS IS THE ONLY TIME THAT INSPECTIONS WILL BE DISCUSSED UNLESS THERE IS SOME SPECIAL INSIGHT TO BE GAINED INTO THE CHIP OR MANUFACTURING PROCESS 4HE AFTER DEVELOP INSPECTION !$) INCLUDES A VISUAL INSPECTION OF A SAMPLE OF WAFERS UNDER THE MICROSCOPE MEASUREMENTS OF THE FEATURE SIZES CREATED IN THE RESIST SCANNING ELECTRON MICROSCOPE 3%- INSPECTIONS MEASUREMENTS AND CHECKS FOR PARTICULATE CONTAMINATION 4HERE ARE EVEN 3%- CROSS SECTIONS DONE INFREQUENTLY THAT REQUIRE BREAKING A WAFER -OST OF THE INSPECTIONS AND MEASUREMENTS ARE DONE BY AUTOMATED TOOLS THAT CAN RECOGNIZE THE PATTERN IN THE WAFER GO RIGHT TO THE PRO GRAMMED SPOT FOR THE INSPECTION COMPARE PATTERNS TO lND DEFECTS AND CONTAMINATION AND MANY OTHER JOBS THAT FORMERLY REQUIRED AN OPERATOR TO HANDLE THE WAFERS SEE #HAPTERS AND !N EXAMPLE OF A COMPLETED PHOTORESIST PATTERN IS SHOWN IN &IGURE
&IGURE 3CANNING %LECTRON -ICROGRAPH 3%- OF $EVELOPED 0HOTORESIST )MAGE .IKON
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)ON )MPLANTATION )MPLANT 0ROCESS &LOW -ASK FOR N TYPE IMPLANT )MPLANT N TYPE DOPANTS 2EMOVE MASK 7ELL $IFFUSION SOMETIMES DONE ONLY ONCE AT THE END 2EMASK FOR P TYPE IMPLANT )MPLANT P TYPE DOPANTS 2EMOVE MASK 7ELL $IFFUSION 4HE PROCESS mOW FOR 7ELL )MPLANT SHOWS THAT IT IS A TWO PART OPERATION 3INCE #-/3 PARTS COM BINE N TYPE AND P TYPE DEVICES AS EXPLAINED EAR LIER TWO DIFFERENT IMPLANTS AND MASKS MUST BE USED SEE &IGURE )MPLANT /VERVIEW
0HOTORESIST MASKED N 4YPE IMPLANT
0HOTORESIST
(IGH TEMPERATURE DIFFUSION OF IMPLANT
2EPEAT WITH P WELL MASK AND IMPLANT
N 7ELL
P 7ELL
N 7ELL
&IGURE 3EQUENCE OF 3TEPS FOR 7ELL $OPING
4HE IMPLANTING PROCESS IS VERY STRAIGHTFORWARD )T SIMPLY INVOLVES SHOOTING IONS AT THE WAFER SO THAT THEY EMBED
#HAPTER &ORMING 7ELLS -AGNETIC FIELD
7AFER
0OSITIVE IONS PULLED FROM ION SOURCE BY A NEGATIVE VOLTAGE
(IGH NEGATIVE VOLTAGE ACCELERATES IONS ! FEW HUNDRED VOLTS TO MILLIONS OF VOLTS ARE USED
)ONS PRODUCED IN PLASMA
4HE MAGNETIC FIELD FILTERS OUT UNWANTED IONS /NLY THE SPECIES WITH THE CORRECT CHARGEMASS RATIO ARE STEERED PRECISELY AROUND THE TURN
&IGURE 3CHEMATIC OF )ON )MPLANTER
THEMSELVES IN IT 4HE TECHNOLOGY ALLOWS VERY PRECISE AMOUNTS OF DOPANT TO BE ADDED TO THE WAFER AS WELL AS A GOOD DEAL OF CONTROL OF THE DEPTH THAT THE IONS OR ATOMS TRAVEL INTO THE WAFER 'ENERALLY CHARGE ACCUMULATION ON THE WAFER SURFACE IS UNACCEPTABLE SINCE IT MAY DAMAGE THE WAFER SO NEUTRAL ATOMS ARE IMPLANTED RATHER THAN THOSE WITH A CHARGE ON THEM 4HE IONS PASS THROUGH A REGION AT THE END OF THEIR RUN THROUGH THE IMPLANTER WHERE THERE ARE MANY ELECTRONS AVAILABLE 4HE POSITIVE IONS GRAB AN ELECTRON REPLAC ING THEIR MISSING ONE OPPOSITE CHARGES ATTRACT AND BECOME A NEUTRAL ATOM 4HE ATOMS MOMENTUM CARRIES IT FORWARD AND INTO THE WAFER SURFACE 4HE IMPLANTED SPECIES TRAVEL A VERY SHORT AVERAGE DISTANCE INTO THE SILICON USUALLY ONLY A FRACTION OF A MICRON )N ADDITION TO CONTROLLING THE AREAS WHERE THE DOPANT ATOMS ENTER THE WAFER SURFACE WITH THE PHOTORESIST PATTERNS THE DEPTH OF PENETRATION OF THE ATOMS MUST BE CONTROLLED 4HE ACCELERATION VOLTAGE USED IN THE IMPLANTER CONTROLS THIS DEPTH WHICH ALSO DEPENDS ON THE SIZE OF THE ATOM BEING IMPLANTED &OR THE SAME DEPTH A HIGHER ACCELERATION VOLTAGE MUST BE CHOSEN FOR A LARGE ATOM THAN FOR A SMALL ONE
)ON )MPLANTATION #HANNELING 3INCE THE CRYSTAL PLANES OF THE SILICON ARE ALIGNED WITH THE SURFACE OF THE WAFER THE WAFER IS ANGLED n TO AVOID CHANNELING WHERE THE ACCELERATED ION OR ATOM FOLLOWS A MAJOR CRYSTALLOGRAPHIC AXIS SLIPPING BETWEEN ATOMS OF 3I AND MOVING DEEP INTO THE WAFER #ONTROL OF THE DEPTH OF IMPLANT RELIES PARTLY UPON THE IMPLANTED SPECIES COLLIDING WITH SILICON ATOMS "Y WAY OF COMPARISON ORCHARDS BEAR A STRONG RESEMBLANCE TO CRYSTALS $RIV ING DOWN THE ROAD NEXT TO AN ORCHARD IS A GOOD WAY OF IMAGINING WHAT THE IMPLANTED ATOMS MIGHT SEE WHEN APPROACHING THE SILICON WAFER )F COMING FROM AN ANGLE THAT IS OFF AXIS THE TREES LOOK LIKE A JUMBLE OF RANDOM ARRANGE MENT (OWEVER WHEN THE SPACES BETWEEN THE ROWS OF TREES APPEAR YOU CAN SEE CLEAR ACROSS THE ORCHARD 4HE CRYSTAL IS LIKE THE ORCHARD AND THE SPACES BETWEEN ROWS OF ATOMS ARE THE MAJOR CRYSTALLOGRAPHIC AXES )T IS EASY TO SEE WHY CHANNELING ATOMS TRAVEL SO FAR
5NIFORM COVERAGE OF THE WAFER SURFACE IS ANOTHER KEY CONCERN $IFFERENT IMPLANTER MANUFACTURERS CONTROL DOPANT DISTRIBUTION IN A VARIETY OF WAYS &IGURE SHOWS ONE EXAMPLE A TOOL THAT HOLDS A NUMBER OF WAFERS AROUND THE CIRCUMFERENCE OF A LARGE CARTWHEEL SHAPED ASSEMBLY $URING PROCESSING THE CARTWHEEL ROTATES AT A HIGH SPEED PASSING THE WAFERS IN FRONT OF AN OPENING THAT EXPOSES A VERY SMALL PART OF THE WAFER AT A TIME TO THE IMPLANTER BEAM 4HIS MOTION PROVIDES VERTICAL SCANNING THE BEAM IS SCANNED HORIZONTALLY 4HE ENTIRE WAFER IS IMPLANTED A LITTLE AT A TIME SO THE DOSE CAN BE CAREFULLY METERED AND THE TEMPERATURE CAN BE KEPT UNDER CONTROL (IGH DOSE HIGH ENERGY IMPLANTS CAN OVERHEAT THE WAFER AND DAMAGE THE RESIST MASK &IGURE )ON )MPLANTER 0LATEN !PPLIED -ATERIALS
#HAPTER &ORMING 7ELLS #RYSTAL $AMAGE 2EPAIR AND $OPANT $IFFUSION !S MIGHT BE IMAGINED THE BOMBARDMENT OF THE WAFER DAMAGES THE SILICON CRYSTAL LATTICE 4HE SILICON ATOMS ARE KNOCKED OUT OF PLACE AND THE ORDERLY BONDS ARE BROKEN )N HIGH ENERGY HIGH DOSE IMPLANTS THE CRYSTAL STRUCTURE AT THE SURFACE OF THE WAFER IS COMPLETELY LOST IT IS SAID TO BECOME hAMORPHIZEDv )N ADDITION THERE ARE NOW MANY DOPANT ATOMS ADDED TO THE MIX
&IGURE 3ILICON #RYSTAL WITH $OPANT !TOMS AS )MPLANTED
4HE DESIRED RESULT OF THE DOPING OPERATION IS TO REPLACE SOME OF THE SILICON ATOMS WITH DOPANT ATOMS SEE #HAPTER WHILE MAINTAINING THE UNIFORM CRYSTAL STRUCTURE 4HE CHIP WILL NOT WORK IF THE CRYSTAL IS NOT REPAIRED WITH THOSE SUBSTITUTIONS INCLUDED ,UCKILY THE CRYSTAL CAN BE REASSEMBLED TO MATCH THE CRYSTAL STRUCTURE OF THE BULK OF THE SILICON WAFER BY HEATING IT TO A TEMPERATURE THAT IS WELL BELOW THE MELTING POINT OF SILICON THE MELTING POINT OF SILICON IS #THATS HOT 4HE LATTICE CAN BE RESTORED AT A TEMPERATURE OF # TO # IN A SHORT TIME 4HIS HEATING OPERATION IS CALLED ANNEALING 4HE ANNEALING OPERATION REPAIRS THE DAMAGED CRYSTAL )T ALSO CAUSES THE DOPANT ATOMS TO MOVE A KNOWN DISTANCE THROUGH THE SILICON 4HIS NATURAL MOVEMENT OR DIFFU SION RESULTS IN DISTRIBUTION OF THE DOPANT THROUGH A WIDER AREA THAN IS ALLOWED BY THE IMPLANT ALONE 4HE VIBRATION OF THE ATOMS IN THE SOLID AT A GIVEN TEMPERATURE MOVES THE DOPANT SLOWLY THROUGH THE SILICON IN A VERY CONTROLLED MANNER PERMITTING THE EX ACT DIMENSIONS OF THE CONDUCTIVE REGION TO BE DElNED 7HEN THE DOPANT ATOMS ARE IN PLACE AND THE CRYSTAL STRUCTURE IS RESTORED THE ELEC TRICAL PROPERTIES OF THE SILICON HAVE BEEN ALTERED !T THAT POINT THE DOPANT IS SAID TO BE hACTIVATEDv -ORE FORMALLY hACTIVATION IN THE HOST LATTICEv HAS BEEN ACCOMPLISHED AS A
)ON )MPLANTATION RESULT OF THE ANNEALING .OW THE REGIONS OF IMPLANTED SILICON ARE MORE CONDUCTIVE THAN THE STARTING WAFER AND IT IS EITHER N TYPE OR P TYPE DEPENDING UPON THE DOPANT USED )N THE PARTICULAR CASE OF THE WELL PROCESS HIGHER TEMPERATURES ARE USED AND APPLIED FOR A FAIRLY LONG TIME BECAUSE THE DOPANT ATOMS MUST DIFFUSE RELATIVELY LONG DISTANCES TO FORM THE WELL 4HIS STEP IS OFTEN CALLED A WELL DIFFUSION OR A WELL DRIVE IN RATHER THAN AN ANNEAL )N LATER STEPS DIFFUSION DISTANCES MUST BE KEPT SHORT AND LOW TEMPERATURE ANNEALING AS DISCUSSED ABOVE IS NEEDED )F THE IMPLANT IS SHALLOW WITH THE HIGHEST CONCENTRATION OF ATOMS NEAR THE SURFACE OF THE WAFER THE ANNEAL WILL MOVE THE ATOMS DOWNWARD 4HAT TYPE OF WELL WILL HAVE A HIGH CONCENTRATION OF DOPANT AT THE SURFACE AND A DECREASING CONCENTRATION OF DOPANT MOVING DOWN INTO THE WAFER ! SECOND DOPING STRATEGY USES A DEEP IMPLANT 4HE IMPLANTED ATOMS ARE DRIVEN DEEPLY INTO THE WAFER LEAVING A REGION ABOVE THAT IS ESSENTIALLY UNDOPED )N THIS CASE THE ANNEALING MOVES MANY OF THE DOPANT ATOMS UPWARD TOWARD THE WAFER SURFACE 4HIS FORMS A hRETROGRADEv WELL IN WHICH THE CONCENTRA TION OF DOPANT INCREASES MOVING DOWN FROM THE SURFACE THE OPPOSITE OF THE SHALLOW IMPLANT WELL 4HERE IS AN ADVANTAGE OFFERED BY THE RETROGRADE WELL LESS CHANCE OF hLATCH UP v A CONDITION THAT MAY OCCUR DURING OPERATION THAT CAUSES A LOCAL HIGH CURRENT mOW THAT MAY DAMAGE OR DESTROY THE CHIP
.OTE 3CHEMATIC REPRESENTATION ONLY 2ATIO OF DOPANT ATOMS TO SILICON ATOMS ACTUALLY MUCH SMALLER THAN SHOWN
&IGURE $OPANT $ISTRIBUTION AFTER !NNEAL
#HAPTER &ORMING 7ELLS 3ILICON SURFACE
3ILICON SURFACE
(EAVIER DOPING NEAR SURFACE
(EAVIER DOPING AT BOTTOM OF WELL
&IGURE $OPING 0ROlLES IN 7ELLS
0ROCESS .OTES 4HE DOPANT SPECIES MOST COMMONLY USED TO CREATE N TYPE WELLS IS PHOSPHOROUS 4HE MAJOR P TYPE DOPANT IS BORON )T IS NOT SURPRISING THAT SOME IMPLANTS INVOLVE A LARGE AMOUNT OF ENERGY TRANS FER TO THE WAFER WHICH RAISES THE WAFER TEMPERATURE 4HE PRINCIPLE ISSUE WITH WAFER HEATING IS DAMAGE TO THE PHOTORESIST MASK )F RESIST IS EXPOSED TO TEMPERATURES ABOVE LEVELS SPECIlED BY THE MANUFACTURER IT SUFFERS PROGRESSIVE DAMAGE IT WILL MELT OR hmOW v AS THE TEMPERATURE RISES THEN HARDEN OR hRETICULATEv AND EVENTUALLY AT A HIGH ENOUGH TEMPERATURE WILL BURN 4HERE IS ALSO SOME DAMAGE TO THE CHEMICAL STRUCTURE OF THE RESIST BECAUSE OF THE BOMBARDMENT FROM THE IMPLANTER $AMAGED RESIST IS HARD TO REMOVE FROM THE WAFER IF CONDITIONS BECOME TOO EXTREME THE MASK WILL BECOME DISTORTED AND DEFORMED AND THE PARTS WILL BE RUINED -INIMIZING RESIST DAMAGE IS AN IMPORTANT PROCESS CONTROL ISSUE !LTHOUGH WELL IMPLANT DOES NOT GENERALLY PRODUCE ENOUGH HEATING TO DAMAGE THE RESIST LATER IMPLANTATION STEPS SUCH AS THE SOURCEDRAIN IMPLANT DISCUSSED IN THE NEXT CHAPTER REQUIRE SPECIAL PROCEDURES TO REDUCE THE RISK TO THE RESIST MASK )T IS OFTEN NECESSARY TO USE BOTH A PLASMA ETCH OPERATION CALLED ASHING AND A WET CHEMICAL STRIPPING SOLUTION AFTER IMPLANT TO REMOVE THE RESIST N 7ELL
P 7ELL
&IGURE #ROSS 3ECTION OF #-/3 7ELL 3TRUCTURE
.OW THAT THE WELLS HAVE BEEN FORMED THE WAFERS ARE READY TO MOVE TO THE NEXT OPERATION SHALLOW TRENCH ISOLATION 34) 4HE TRENCHES WILL ELECTRICALLY ISOLATE EVERY TRANSISTOR FROM ITS NEIGHBORS SO THAT NO ELECTRICAL INTERACTIONS OCCUR THAT WOULD RUIN THE CIRCUITS
#(!04%2
)SOLATE !CTIVE !REAS 3HALLOW 4RENCH )SOLATION
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)NTRODUCTION TO 3HALLOW 4RENCH )SOLATION )N THIS CHAPTER YOU WILL LEARN v (OW TRANSISTORS ARE ELECTRICALLY ISOLATED IN THE CHIP v (OW SILICON NITRIDE IS DEPOSITED v 3OME OF THE DETAILS OF PLASMA ETCHING v 3OME OF THE DETAILS OF CHEMICAL MECHANICAL POLISHING 4RENCH &ILLED WITH )NSULATING -ATERIAL
&IGURE 3HALLOW 4RENCH )SOLATION
&IGURE 3HALLOW 4RENCH )SOLATION #ROSS 3ECTION
#HAPTER )SOLATE !CTIVE !REAS 3HALLOW 4RENCH )SOLATION $ElNITION ! 3HALLOW 4RENCH IS A SORT OF MOAT THAT IS DUG AROUND EVERY TRANSISTOR ON THE CHIP 4HE DIMENSIONS OF THE TRENCHES WILL VARY SOMEWHAT BASED UPON THE DESIGN OF THE CHIP 7HY ARE THE TRENCHES CALLED SHALLOW #OMPARED TO THE DEPTH THAT THE TRANSISTOR GOES INTO THE WAFER THEY ARE PRETTY DEEP AS WILL BE ILLUSTRATED SHORTLY 4HE REASON FOR THE TERMINOLOGY IS THAT THERE ARE TRENCH STRUCTURES SOMETIMES USED FOR OTHER PURPOSES SUCH AS CAPACITORS FOR $2!-S THAT ARE QUITE A LOT DEEPER 3O THE TERM SIMPLY REmECTS A GENERALIZED COMPARISON OF SIMILAR CHIP STRUCTURES 0URPOSE 3HALLOW 4RENCH )SOLATION 34) IS A TECHNIQUE FOR ELECTRICALLY ISOLATING EACH TRANSISTOR 4RENCHES ARE FORMED AROUND EACH TRANSISTOR ON THE CHIP 4HE TRENCHES ARE lLLED WITH SILICON DIOXIDE AN ELECTRICAL INSULATOR WHICH PREVENTS MOST UN WANTED ELECTRICAL CURRENT FROM mOWING BETWEEN ADJACENT TRANSISTORS $ISCUSSION 7HY DO ADJACENT TRANSISTORS NEED TO BE ELECTRICALLY ISOLATED "ECAUSE THEY ARE ELEC TRICAL DEVICES AND WILL COMMUNICATE WITH EACH OTHER IN UNWANTED WAYS LIKE SHORTS LATCH UP AND CROSS TALK 4HESE PROBLEMS WILL RUIN THE CHIP 3OME EXAMPLES WILL BE DISCUSSED LATER IN THE CHAPTER #ANT THE TRANSISTORS JUST BE KEPT SEPARATED 2ECALL FROM #HAPTERS THAT THE SILICON WAFER WHICH IS PART OF THE CHIP IS DOPED TO MAKE IT CONDUCTIVE 3INCE THE TRANSISTORS ARE BUILT MOSTLY DOWN INTO THE WAFER THEY WOULD NEED TO BE SEPARATED BY A RATHER LONG DISTANCE TO REDUCE THE CURRENT mOW BETWEEN THEM "UT THE TRANSISTORS MUST BE PACKED TIGHTLY TOGETHER IN ORDER TO lT MANY MILLIONS OF THEM ON A SINGLE CHIP SO WIDE SEPARATION OF THE TRANSISTORS IS NOT AN OPTION (OW GOOD IS THE ISOLATION PROVIDED BY A TRENCH 3HOULDNT THE TRANSISTOR BE COM PLETELY SURROUNDED BY INSULATION LIKE ANY OTHER ELECTRICAL DEVICE )N OTHER WORDS WONT THE ELECTRICITY mOW UNDER THE TRENCH 4HE INSULATION DOES NOT HAVE TO GO UNDERNEATH THE TRANSISTORS 4HE ISOLATION UNDER THE TRANSISTORS IS TAKEN CARE OF BY THE PRESENCE OF P N JUNCTIONS 7HEN THE CHIP IS OPERATING NORMALLY THOSE P N JUNCTIONS ACT LIKE INSULATING LAYERS 2EVIEW P N JUNC TIONS IN !PPENDIX ! TO SEE HOW CURRENT MAY mOW THROUGH THESE JUNCTIONS AND HOW IT IS INHIBITED FROM mOWING (OWEVER AS YOU MIGHT SUSPECT THERE IS A VERY WEAK CONNECTION BETWEEN THE ADJACENT TRANSISTORS THAT IS FELT UNDERNEATH THE TRENCH 4HERE ARE MECHANISMS THAT CAN
)NTRODUCTION TO 3HALLOW 4RENCH )SOLATION RESULT IN UNWANTED CURRENT mOW WHICH CAN CAUSE FAULTY OPERATION OR EVEN CHIP DESTRUC TION 0ROPER CHIP DESIGN AND CONSTRUCTION MINIMIZES THAT RISK 3HALLOW 4RENCH )SOLATION 0ROCESS &LOW 'ROW 0AD /XIDE $EPOSIT 3ILICON .ITRIDE 0HOTOLITHOGRAPHY 0ATTERNING &ORM THE (ARD -ASK 4RANSFER 0ATTERN TO $IELECTRIC &ILMS WITH 0LASMA %TCH A 3ILICON .ITRIDE %TCH B 0AD /XIDE %TCH %TCH 4RENCH IN 3ILICON 3UBSTRATE
&ILL 4RENCH WITH 3ILICON $IOXIDE A 'ROW 4HERMAL /XIDE ,INER B $EPOSIT #6$ /XIDE &ILL 2EMOVE EXCESS OXIDE WITH CHEMICAL MECHANICAL POLISHING #-0
2EMOVE REMAINING NITRIDE AND OXIDE WITH WET CHEMICAL ETCH $ISCUSSION 3HALLOW TRENCH ISOLATION 34) IS A VERY COMPREHENSIVE PROCESS )T INCLUDES A MAJORITY OF THE OPERATIONS FOUND IN THE FAB THERMAL OXIDATION THIN lLM DEPOSITION PHOTOLI THOGRAPHY PLASMA ETCH AND #-0 34) IS ESPECIALLY INTERESTING BECAUSE IN THE PROCESS OF BUILDING THE TRENCH STRUCTURES THE INTERRELATIONSHIP OF THESE FAB PROCEDURES IS CLEARLY ILLUSTRATED 4HE SPECIAL REQUIREMENTS OF 34) ARE OUTLINED BELOW %ACH ELEMENT OF THE +EY 0OINTS WILL BE EXPLAINED IN DETAIL IN LATER SECTIONS +EY 0OINTS IN THE 34) 0ROCESS #HEMICAL MECHANICAL POLISHING #-0 MUST BE USED TO REMOVE EXCESS OXIDE AFTER TRENCH lLL LEAVING A NEARLY mAT SURFACE ON THE WAFER 3ILICON TRENCH ETCH USES AN INORGANIC SIDEWALL PROTECTIVE COATING CALLED PASSIV ATION TO CONTROL THE SHAPE OF THE TRENCH 4HE MORE COMMON ORGANIC PASSIVATION COULD LEAVE CONTAMINATION BEHIND SO NO CARBON SOURCE IS USED AT THAT STAGE
#HAPTER )SOLATE !CTIVE !REAS 3HALLOW 4RENCH )SOLATION ! HARD MASK FOR THE TRENCH ETCH MUST BE USED IN PLACE OF THE PHOTORESIST MASK TO ELIMINATE ORGANICS AND PROVIDE GOOD TRENCH EDGE DElNITION 4HE DIELECTRICS SILICON NITRIDE AND PAD OXIDE ARE GOOD HARD MASKING MATERIALS 4HE RESIST IS USED AS THE MASK FOR THE HARD MASK ETCH BUT MUST BE REMOVED BEFORE THE TRENCHES ARE ETCHED !NTI REmECTIVE COATINGS ARE INCLUDED IN THE PROCESS TO AID PHOTOLITHOGRAPHY BUT ARE NOT ILLUSTRATED IN THE lGURES
3%#4)/.
0AD /XIDE 'ROWTH $ElNITION 0AD /XIDE IS THERMAL OXIDE GROWN ON TOP OF THE SILICON WAFER )T IS TYPI CALLY ABOUT !NGSTROMS THICK )T FORMS A PROTECTIVE PAD BETWEEN THE NEXT LAYER SILICON NITRIDE AND THE UNDERLYING SILICON WAFER SURFACE 0URPOSE 4HE PAD OXIDE PREVENTS DAMAGE TO THE SILICON SURFACE THAT WOULD HAPPEN IF SILICON NITRIDE WERE DEPOSITED DIRECTLY ON THE SILICON $ISCUSSION 3ILICON NITRIDE EXPANDS AT A DIFFERENT RATE THAN THE SILICON WAFER 4HE PAD OXIDE ALLOWS THE NITRIDE TO mOAT ABOVE THE SILICON SO THAT THE NITRIDE APPLIES LITTLE MECHANICAL STRESS TO THE SILICON SURFACE DURING THE THERMAL CYCLING NEEDED FOR THE PROCESS 4HE AREA UNDERNEATH THE SILICON NITRIDE IS WHERE THE TRANSISTORS ARE TO BE BUILT AS MENTIONED IN #HAPTER IT IS THE !CTIVE !REA WHERE THE !CTIVE $EVICES TRANSISTORS ARE LOCATED 4HE SILICON CRYSTAL STRUCTURE IS IMPORTANT TO THE PROPER FUNCTIONING OF THE TRANSISTOR AND MUST BE KEPT IN GOOD CONDITION 4HE PAD OXIDE IS THERMAL OXIDE JUST LIKE THE SACRIlCIAL OXIDE DISCUSSED IN #HAPTER )N FACT THE THICKNESS IS ABOUT THE SAME IN BOTH CASES ABOUT !NGSTROMS
&IGURE 0AD /XIDE #ROSS 3ECTION
#HAPTER )SOLATE !CTIVE !REAS 3HALLOW 4RENCH )SOLATION 0LEASE FEEL FREE TO REFRESH YOUR MEMORY BY RETURNING TO #HAPTER TO READ THE DIS CUSSION OF THERMAL OXIDATION
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3ILICON .ITRIDE $EPOSITION $ElNITION 3ILICON .ITRIDE .ITRIDE IS A HARD DIELECTRIC lLM 0URPOSE )N THIS APPLICATION THE SILICON NITRIDE IS USED AS AN ETCH MASK TO BLOCK THE ETCHING CHEMICALS FROM ATTACKING MASKED OFF AREAS ON THE WAFER SURFACE 4HIS IS THE JOB OF A hHARD MASKv AS DISCUSSED IN THE NEXT SECTION )T ALSO HELPS TO PROTECT THE ACTIVE AREAS FROM PHYSICAL DAMAGE THAT MIGHT BE CAUSED BY THE #-0 TOOL AS DISCUSSED IN 3ECTION ALTHOUGH THAT IS OF SECONDARY IMPORTANCE TO THE PRIMARY FUNCTION OF THE lLM
7HY NOT JUST USE PHOTORESIST AS THE ETCH MASK 4HAT QUESTION IS ANSWERED IN SOME DETAIL IN 3ECTION (ARD -ASK &ORMATION
$ElNITION #HEMICAL 6APOR $EPOSITION #6$ IS THE PROCESS OF DEPOSITING A THIN lLM ON THE WAFER BY EXPOSING IT TO GASEOUS CHEMICALS SAID TO BE IN THE hVAPOR PHASEv WHICH REACT WITH ONE ANOTHER TO FORM THE DESIRED LAYER MATERIAL $ElNITION ,OW 0RESSURE #6$ ,0#6$ DEPOSITS A lLM IN A LOW PRESSURE ENVIRON MENT TYPICALLY TO 4ORR AROUND ONE THOUSANDTH OF ATMOSPHERIC PRESSURE AT TEMPERATURES RANGING FROM TO # 4HE ,0#6$ REACTOR RELIES SOLELY ON THERMAL ENERGY TO INITIATE THE CHEMICAL REACTION THAT RESULTS IN DEPOSITION 5NITS OF PRESSURE ARE DISCUSSED LATER IN THIS CHAPTER AND IN !PPENDIX ! 3CIENCE /VERVIEW $ElNITION 0LASMA %NHANCED #6$ 0%#6$ IS DEPOSITION CARRIED OUT IN A PLASMA REACTOR 4HE ENERGY OF THE PLASMA IS USED TO ASSIST THE CHEMICAL REACTION WHICH WILL THEN PROCEED AT A LOWER TEMPERATURE THAN IN ,0#6$ 7AFER TEMPERATURES IN THE RANGE OF n# ARE USED FOR 0%#6$
#HAPTER )SOLATE !CTIVE !REAS 3HALLOW 4RENCH )SOLATION #HEMICAL 2EACTION 3I(#LGAS .(GAS m 3I.SOLID .(#LGAS (GAS 4HE ABOVE CHEMICAL REACTION INVOLVES THE MOST COMMONLY USED CHEMICALS FOR THE ,0 #6$ SILICON NITRIDE DEPOSITION PROCESS $ICHLOROSILANE REACTS WITH AMMONIA TO GIVE SILICON NITRIDE AMMONIUM CHLORIDE AND HYDROGEN !MMONIUM CHLORIDE IS A SOLID AT ROOM TEMPERATURE BUT IS A VAPOR AT THE TEMPERATURE OF THE REACTOR $ISCUSSION 4HIS NITRIDE lLM WILL BE ABOUT !NGSTROMS THICK 3ILICON NITRIDE IS LIKE A NUMBER OF THE MATERIALS USED IN CHIPMAKING IN THAT ITS CHEMICAL COMPOSITION CAN VARY BUT IT WILL STILL FUNCTION EFFECTIVELY 4HE RATIO OF SILICON TO NITROGEN VARIES AND IT CAN CONTAIN A SUBSTANTIAL AMOUNT OF HYDROGEN DEPENDING ON THE WAY IT IS DEPOSITED 4HE SILICON NITRIDE lLM FOR THE 34) PROCESS IS DEPOSITED WITH OUT USING A PLASMA WITH THE WAFERS AT A HIGH TEMPERATURE OF ABOUT # AND HAS A COMPOSITION CLOSE TO THE THEORETICAL FORMULA OF 3I. )N OTHER APPLICATIONS LATER IN THE WAFER FABRICATION CYCLE A TEMPERATURE OF # WOULD DAMAGE THE DEVICES SO PLASMA ENHANCED #6$ 0%#6$ IS USED TO PROVIDE A LOWER TEMPERATURE PROCESS USUALLY IN THE NEIGHBORHOOD OF # OR BELOW -ANY #6$ PROCESSES DEPEND SIMPLY ON HEATING THE WAFERS TO A HIGH ENOUGH TEM PERATURE FOR THE DEPOSITION REACTIONS BETWEEN THE GASES TO OCCUR ON THE WAFER SURFACE BUT IN CASES WHERE DEVICE DAMAGE IS AN ISSUE ANOTHER APPROACH IS NEEDED 5SING THE ELECTRICAL ENERGY OF A PLASMA CAN HELP THE REACTIONS ALONG SO THAT DEPOSITION WILL PRO CEED AT LOWER WAFER TEMPERATURES ! PLASMA NITRIDE MAY HAVE A HYDROGEN CONTENT OF OR MORE AND WILL HAVE PROPERTIES THAT DIFFER FROM THOSE OF THE HIGH TEMPERATURE MATERIAL &OR EXAMPLE IT WILL HAVE DIFFERENT OPTICAL PROPERTIES AND DISSOLVE MUCH MORE RAPIDLY IN HYDROmUORIC ACID SOLUTIONS )N MOST #6$ APPLICATIONS THE lLM COVERS ALL KINDS OF STRUCTURAL FEATURES ALREADY FORMED ON THE WAFER !N IMPORTANT FACTOR IN ALL THIN lLM DEPOSITION PROCESSES IS HOW WELL THE lLM CONFORMS TO THE WAFER SURFACE )N PARTICULAR IT CAN BE DIFlCULT TO lLL SMALL HOLES AND VERY NARROW TRENCHES !LSO lLMS DEPOSITED BY VARIOUS TECHNIQUES ARE CONFORMAL TO VARYING DEGREES &ILMS DEPOSITED BY PHYSICAL VAPOR DEPOSITION SPUT TERING HAVE DIFFERENT CONFORMALITY CHARACTERISTICS FROM THOSE OF #6$ lLMS AND THE CONFORMALITY OF #6$ lLMS VARIES WITH THE CHEMISTRY USED
3ILICON .ITRIDE $EPOSITION /XIDE 3ILICON
!LUMINUM 3PUTTER
/XIDE ,0#6$
'OOD CONFORMALITY 4UNGSTEN #6$
&IGURE #6$ #ONFORMALITY AND &ILL #HARACTERISTICS
3ILICON NITRIDE HAS A NUMBER OF USES AND IT WILL APPEAR OFTEN IN THE CHIPMAKING PROCESS 3ILICON NITRIDE
&IGURE .ITRIDE ON 0AD /XIDE #ROSS 3ECTION
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0HOTOLITHOGRAPHY FOR 0HOTO%TCH 4HIS SECTION BEGINS THE DISCUSSION OF A NEW APPLICATION FOR PHOTOETCHTHE FORMA TION OF A HARD MASK 3OME PHOTOLITHOGRAPHY POINTS ARE REITERATED IN THIS SECTION FROM #HAPTER TO HELP KEEP THE DISCUSSION IN CONTEXT $ElNITION 0HOTOLITHOGRAPHY IS THE PROCESS OF TRANSFERRING A PATTERN FROM THE RETICLE TO THE PHOTORESIST WHICH WILL THEN ACT AS A MASK OR TEMPLATE 4HIS TIME THE PAT TERN IN THE RESIST WILL BE ETCHED INTO THE UNDERLYING lLM COMPLETING THE PATTERN TRANSFER $ElNITION 0HOTORESIST RESIST IS A PLASTIC MATERIAL THAT IS SENSITIVE TO ULTRAVIOLET 56 LIGHT 0URPOSE 4HE PHOTORESIST ACTS AS A TEMPLATE A PROTECTIVE MASK THAT WILL ONLY ALLOW THE UNDERLYING lLM TO BE ETCHED AWAY FROM AREAS NOT COVERED WITH RESIST 7HEN USED THIS WAY IT IS CALLED AN ETCH MASK 2ECALL THAT THE PHOTOLITHOGRAPHY PROCESS IN #HAPTER PRODUCED PATTERNED RESIST THAT SERVED AS AN IMPLANT MASK )N 34) THE RESIST IS USED TO PATTERN THE NITRIDE AND OXIDE LAYERS 4HIS IS AN INTEREST ING COMBINATION PROCESS THAT IS USED TO PRODUCE SOMETHING CALLED A HARD MASK WHICH IS DISCUSSED IN THE NEXT SECTION 0HOTOLITHOGRAPHY 0ROCESS &LOW 4HE PROCESS mOW WAS COVERED IN #HAPTER 4HERE ARE NO CHANGES IN THAT DISCUSSION FOR THIS APPLICATION (ERE IT IS AGAIN FOR REFERENCE
#HAPTER )SOLATE !CTIVE !REAS 3HALLOW 4RENCH )SOLATION
#OAT 3PIN A 3URFACE 0REPARATION I 6ACUUM DEHYDRATION BAKE II (-$3 HEXAMETHYLDISILAZANE APPLICATION B 3PIN RESIST APPLICATION C 3OFT BAKE
%XPOSE 3TEP $EVELOP A !PPLY DEVELOPER SOLUTION B 0OST DEVELOP RINSE !FTER $EVELOP )NSPECTION !$)
&IGURE 2ESIST 0ATTERN FOR 4RENCH %TCH
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(ARD -ASK &ORMATION 5SING 0LASMA %TCH (ARD -ASK /VERVIEW $ElNITION ! (ARD -ASK IS A MASK MOST COMMONLY MADE OUT OF EITHER SILICON NITRIDE SILICON DIOXIDE OR BOTH 0URPOSE OF (ARD -ASK ! HARD MASK IS OFTEN USED AS AN ETCH MASK AND SOMETIMES AS AN IMPLANT MASK )N THIS CASE THE MASK PROTECTS THE UNDERLYING SURFACE FROM ATTACK BY THE ETCHANT CHEMICALS AND ONLY EXPOSED SURFACES ARE ETCHED AWAY 4HE HARD MASK SUBSTITUTES FOR PHOTORESIST IN INSTANCES WHERE THE RESIST IS UNABLE TO DO THE JOB REQUIRED BY THE PROCESS $ISCUSSION 7HY IS THE RESIST UNABLE TO DO THE MASKING JOB FOR ETCHING THE SILICON TRENCHES -OST OF THE TIME THE PHOTORESIST IS PERFECTLY ADEQUATE TO USE AS AN ETCH OR IMPLANT MASKIN FACT IT IS USED AS THE ETCH MASK TO ETCH THE HARD MASK "UT IN A FEW CASES THERE ARE REQUIREMENTS IN THE PROCESS THAT MAKE IT INADVISABLE TO USE RESIST 4RENCH ETCH IS ONE OF THOSE CASES 4HE PROBLEM WITH USING PHOTORESIST AS THE ETCH MASK FOR TRENCH ETCH IS TWO FOLD 4HE RESIST WILL BE ETCHED AWAY BEFORE THE TRENCHES ARE COMPLETED 4HE TRENCHES WILL BE COATED WITH ORGANIC CARBON BASED CHEMICAL DEPOSITS THAT COULD CONTAMINATE THE DEVICES 4HE CHEMISTRY OF TRENCH ETCH WILL BE DISCUSSED IN MORE DETAIL LATER BUT HERE IS AN OVERVIEW OF THE MAJOR ISSUES
#HAPTER )SOLATE !CTIVE !REAS 3HALLOW 4RENCH )SOLATION "RIEmY CHLORINE IS THE PRINCIPLE REACTANT USED TO ETCH THE SILICON TRENCHES 4HE CHLORINE ATTACKS THE RESIST MASK AND ETCHES IT AWAY RATHER RAPIDLY &OR MOST APPLICA TIONS A THICK ENOUGH RESIST COATING IS USED SO THAT THE WHOLE MASK IS NOT DESTROYED BEFORE THE FEATURE IS FORMED "UT IN THIS CASE THE TRENCHES ARE QUITE LARGE COMPARED TO MOST FEATURES ON THE CHIP A LONG ETCH TIME IS NEEDED TO FORM THE TRENCH BECAUSE SUCH A LARGE AMOUNT OF SILICON MUST BE REMOVED 4HE CHLORINE ATTACK IS AGGRESSIVE ENOUGH SO THAT ALL THE RESIST WOULD BE ETCHED OFF LONG BEFORE THE TRENCHES WERE lNISHED /F COURSE WHEN THE TEMPLATE MASK THAT IS TO BE REPRODUCED ON THE WAFER IS DESTROYED THE FEATURE IS ALSO RUINED 3O A TOUGHER MASKING MATERIAL MUST BE USED )T SHOULD NOT BE OVERLOOKED THAT ALTHOUGH THE RESIST IS ATTACKED BY THE ETCH CHEMI CALS SOME OF THE CARBON CONTAINING PRODUCTS ARE RE DEPOSITED ON THE WAFER 4HE AMOUNT OF RE DEPOSITION IS QUITE SMALL BUT IT IS ENOUGH TO LEAVE SIGNIlCANT AMOUNTS OF TRACE CHEMICALS THAT POSE A POTENTIAL CONTAMINATION HAZARD THAT WILL BE DISCUSSED LATER IN THIS SECTION 3ILICON NITRIDE IS A VERY TOUGH MATERIAL AND STANDS UP WELL TO THE CHLORINE CHEMIS TRY 4HE PAD OXIDE UNDERNEATH THE NITRIDE IS ALSO A TOUGH DIELECTRIC AND LIKEWISE ETCHES VERY SLOWLY IN CHLORINE CHEMISTRY ALTHOUGH ITS FUNCTION IS PRIMARILY TO SEPARATE THE NITRIDE AND SILICON AS DISCUSSED EARLIER /F COURSE THE HARD MASK MUST BE FORMED IN THE NITRIDE AND OXIDE lLMS USING PLASMA ETCH SO A MASK IS NECESSARY FOR THAT PART OF THE OPERATION 0HOTORESIST WORKS VERY WELL FOR THIS MASKING OPERATION !NY REMAINING RESIST IS REMOVED BEFORE PRO GRESSING TO THE TRENCH ETCH 4HERE IS ANOTHER ISSUE REGARDING CHEMICAL CONTAMINATION .ITRIDE AND OXIDE ETCH RECIPES USUALLY HAVE A CHEMICAL COMPONENT CONTAINING CARBON AND WHEN COMBINED WITH SOME MINOR RESIST EROSION RECALL THAT RESIST IS MOSTLY CARBON FORMS AN ORGANIC PROTECTIVE LAYER CALLED PASSIVATION $ISCUSSED LATER IN THIS CHAPTER THESE DEPOSITS ARE IMPORTANT TO HELP CONTROL THE ETCH AND ALLOWING THE PRODUCTION OF VERTICAL SIDEWALL PROlLES SO CRITICAL TO THE DEVICE 4HERE IS SOME CONCERN THAT IF ANY RESIDUAL ORGANIC PASSIVATION IS LEFT ON THE SIDE WALLS OF THE TRENCHES THAT LATER IN THE PROCESS IT COULD OVERHEAT ENOUGH TO HARDEN OR BURN 4HAT RESIDUE COULD NOT BE REMOVED IN THE SUCCEEDING WAFER CLEANING STEPS AND SO BECOMES A CONTAMINANT THAT COULD ENDANGER THE FUNCTIONING OF THE DEVICE 4HERE FORE ALL OF THE RESIST AND MOST OF THE ORGANIC DEPOSITS ARE REMOVED FROM THE WAFER PRIOR TO ETCHING THE TRENCHES (OW THEN ARE THE TRENCH SIDEWALLS PASSIVATED 2EAD ON
(ARD -ASK &ORMATION 5SING 0LASMA %TCH
0LASMA %TCH /VERVIEW
2& 3OURCE %LECTRODES
7AFER
&IGURE 4YPICAL 0LASMA %TCH 2EACTOR
$ElNITION 0LASMA %TCH IS THE USE OF A PLASMA GENERATED WITH SUITABLE GASES TO CHEMICALLY REMOVE MATERIAL FROM THE WAFER SURFACE 0URPOSE OF 0LASMA %TCH 4HE PURPOSE OF PLASMA ETCH IS TO REPRODUCE THE ETCH MASK IN THE lLMS ON THE SURFACE OF THE WAFER OR TO CHEMICALLY REMOVE MATERIAL FROM THE WAFER SURFACE IN A LESS SPECIlC WAY 4HE MASK PATTERN MAY BE TRANSFERRED TO A lLM OR STACK OF lLMS THAT HAVE BEEN DEPOSITED ON THE WAFER OR ETCHED INTO THE SILICON WAFER ITSELF &OR MANY CRITICAL MANUFACTURING STEPS THE ETCH PROCESS MUST ALSO BE ABLE TO SHAPE THE FEATURE BEING PRODUCED ON THE WAFER SURFACE IN A SPECI lED WAY
0LASMA ETCH IS ALSO USED TO CHEMICALLY REMOVE lLMS THAT COMPLETELY COVER THE WA FER -OST OF OUR DISCUSSION WILL CENTER ON THE MOST CRITICAL APPLICATIONS OF PLASMA ETCH WHICH RESULTS IN PROPERLY SHAPED FEATURES PRODUCED ON THE WAFER
4HE PLASMA ETCH PROCESS INCLUDES BOTH THE CHEMICAL REMOVAL OF MATERIAL AND THE DEPOSITION OF A THIN COATING OF MATERIAL TO PROTECT SELECTED AREAS AND ASSIST IN CRE ATING THE DESIRED FEATURES ON THE WAFER 0HYSICAL BOMBARDMENT OF THE WAFER WITH ACCELERATED IONS IS OFTEN UTILIZED TO ASSIST IN THE PROCESS ALTHOUGH THERE ARE SEVERAL PLASMA ETCH OPERATIONS THAT DO NOT REQUIRE BOMBARDMENT
3INCE PLASMA ETCH USES GASES RATHER THAN WET CHEMICALS IT IS OFTEN REFERRED TO AS hDRY ETCHINGv
$ElNITION 7ET %TCH IS THE USE OF LIQUID ETCHANTS TO REMOVE MATERIAL FROM THE WAFER SURFACE 7ET ETCHANTS PRODUCE AN ISOTROPIC SIDEWALL PROlLE
#HAPTER )SOLATE !CTIVE !REAS 3HALLOW 4RENCH )SOLATION )SOTROPIC 0ROFILE
!NISOTROPIC 0ROFILE
&IGURE )SOTROPIC AND !NISOTROPIC %TCH 0ROlLES (ISTORICAL 0ERSPECTIVE ON %TCH &OR ABOUT THE lRST TWENTY YEARS OF THE SEMICONDUCTOR INDUSTRY WHICH STARTED AROUND ESSENTIALLY ALL ETCH PROCESSES USED IN DEVICE FABRICATION WERE WET USING A WIDE VARIETY OF CHEMICAL SOLUTIONS 4HEN PLASMA ETCHES WERE DEVELOPED lRST TO ETCH MATERIALS THAT WERE DIFlCULT TO WET ETCH AND LATER TO ETCH VERY SMALL DEVICE FEATURES THAT COULD NOT BE FORMED PROPERLY WITH WET ETCHING )N CURRENT TECHNOLOGY ALMOST ALL THE ETCHES USED ARE PLASMA PROCESSES !S YOU WILL SEE IN A MOMENT THE TOPIC OF PLASMA ETCH IS QUITE BROAD 4O GET A GOOD PICTURE OF THE ENTIRE PROCESS REQUIRES A DISCUSSION OF SEVERAL DIFFERENT TECHNOLOGIES SOME INTERESTING PHYSICS AND CHEMISTRY AND A LITTLE HISTORY OF WHY AND HOW THE TECHNOLOGY DEVELOPED -ORE INFORMATION CAN BE FOUND IN !PPENDIX " 0LASMA %TCH 3UPPLEMENT TO #HAPTER BUT DO NOT HESITATE TO DO SOME ADDITIONAL READING ON PLASMA ETCH 3EVERAL GOOD BOOKS ARE REFERENCED IN THE "IBLIOGRAPHY
$ElNITION 0LASMA IS AN ELECTRICALLY CHARGED GAS 4HE ATOMS ANDOR MOLECULES OF GAS ARE MADE INTO IONS SEE !PPENDIX ! BY THE PROCESSING TOOL 4HE ETCH REACTOR PRODUCES ABOUT OR LESS OF CHARGED PARTICLES MIXED WITH A NEUTRAL GASJUST RIGHT FOR THE PROCESS REQUIREMENTS 4HE PLASMA PRODUCED BY PROCESS ING TOOLS IS REFERRED TO AS A hPARTIALLY IONIZED GASv 4HIS DISTINCTION IS MADE BECAUSE TECHNICALLY SPEAKING A PLASMA IS MADE ONLY OF IONIZED GAS PARTICLES )T IS MUCH EASIER TO USE A MORE RELAXED DElNITION WHEN DISCUSSING PLASMA PROCESSING
(ARD -ASK &ORMATION 5SING 0LASMA %TCH #ASCADE %FFECT 4HE CASCADE EFFECT IS THE TERM FOR THE AVALANCHE OF COLLISIONS BETWEEN ELEC TRONS IN A PLASMA REACTOR &IRST ONE STRAY ELECTRON COLLIDES WITH ANOTHER THAT IS BOUND TO A MOLECULE KNOCKING IT OFF AND THEREBY PRODUCING AN ION .OW THERE ARE TWO ELECTRONS BEING ACCELERATED BY THE REACTOR TOWARD OTHER MOLECULES 7HEN THEY BOTH KNOCK OFF ANOTHER ELECTRON FOUR FREE ELECTRONS EXISTTHEN EIGHT THEN SIXTEENYOU GET THE PICTURE
$ElNITION 0ASSIVATION IS A CHEMICAL COATING PRODUCED IN THE ETCH REACTOR THAT IS DEPOSITED ON THE WAFER -ANY PLASMA ETCH RECIPES INCLUDE A CHEMICAL COMBINA TION THAT PRODUCES THIS MATERIAL 4HE COATING hPASSIVATESv OR PROTECTS SOME WAFER SURFACES FROM ATTACK BY THE ETCHANT CHEMICALS AND CAN OFFER SOME PROTECTION FROM BOMBARDMENT TOO
3OMETIMES THE TERM hSIDEWALL PASSIVATIONv IS USED SINCE THE PROTECTION OF THE FEATURES SIDEWALLS FROM CHEMICAL ATTACK IS SO IMPORTANT TO FORMING THE ELECTRICAL DEVICES ON THE CHIP )T IS IMPORTANT TO REMEMBER THAT THE PASSIVATION DOES MUCH MORE THAN THAT AS WILL BE DISCUSSED LATER IN THIS SECTION
$ElNITION 0HOTORESIST 3TRIPPING OR h!SHINGv IS THE REMOVAL OF PHOTORESIST FROM THE WAFER SURFACE USING A PLASMA !SHING IS ACTUALLY THE ETCHING OF PHOTORESIST UNLIKE LIQUID WET RESIST STRIP WHICH IS DONE IN A BATH OF LIQUID CHEMICALS 4HE PRINCIPAL GAS USED FOR THIS ETCH IS OXYGEN WHICH IS USED TO OXIDIZE OR hBURNv THE RESIST OFF OF THE WAFER HENCE THE NAME (OWEVER IT IS SOMEWHAT MISLEADING BECAUSE NO ACTUAL ASH IS FORMED THE REACTION PRODUCTS ARE GASES AND SO CAN BE REMOVED BY THE VACUUM SYSTEM
/THER TRACE GASES MAY BE ADDED TO ENHANCE THE PROCESS
0URPOSE OF 0HOTORESIST !SHING 2ESIST ASHING IS NEEDED TO REMOVE THE REMAINING RESIST MASK AFTER A PROCESSING OPERATION LIKE PLASMA ETCH OR ANY OTHER SITUATION REQUIRING THE REMOVAL OF RESIST FROM THE WAFER 4HE OXYGEN PLASMA IS GOOD AT RE MOVING ANY OTHER ORGANICS THAT WERE DEPOSITED ON THE WAFER DURING PROCESSING AN IMPORTANT WAFER CLEANING ISSUE
#HAPTER )SOLATE !CTIVE !REAS 3HALLOW 4RENCH )SOLATION $ISCUSSION 4HE USE OF PLASMA ETCH IS REQUIRED FOR MAKING TODAYS CHIPS (ERE ARE SOME OF THE ADVANTAGES OF PLASMA ETCH 0LASMAS MAKE HIGHLY REACTIVE CHEMICAL SPECIES !NISOTROPIC DIRECTIONAL ETCH CAPABILITYVERTICAL SIDEWALLS ARE REQUIRED )ON BOMBARDMENT IS AVAILABLE TO SPEED UP CHEMICAL REACTIONS AND HELP TO SHAPE FEATURES #AN DEPOSIT A SURFACE PASSIVATION lLM THAT ENHANCES SEVERAL ASPECTS OF THE ETCH &ORMATION OF TINY FEATURESLIQUIDS MAY NOT ENTER MICROSCOPIC OPENINGS AND THEREFORE ARE NOT RELIABLE FOR PRODUCING THE SMALLEST FEATURES 5SES A MUCH LOWER QUANTITY OF CHEMICALS THAN WET ETCH AND THE EFmUENT OR WASTE CHEMICAL IS EASIER TO DEAL WITH MORE ENVIRONMENTALLY FRIENDLY 0ROCESS &LOW FOR 34) 0LASMA %TCH %TCH SILICON NITRIDE %TCH PAD OXIDE 2EMOVE REMAINING RESIST USING AN OXYGEN PLASMA %TCH TRENCH IN SILICON DISCUSSED IN THE NEXT SECTION 7ET CLEAN TO REMOVE INORGANIC PASSIVATION %TCHING 'LASS !NYONE TAKING AN ART CLASS ON ETCHING GLASS WILL BE VERY FAMILIAR WITH THE BASICS OF THIS PROCESS )N THE ART CLASS THE PLATE OF GLASS TO BE ETCHED IS COATED WITH WAX 4HEN THE ARTIST SCRATCHES OFF THE WAX IN THE SPOTS WHERE IT IS DESIRED TO ETCH THE GLASS !N ACID IS POURED ONTO THE GLASS AND AFTER A SPECIlED TIME THE ACID IS RINSED OFF 4HEN THE WAX CAN BE REMOVEDAND VOILA ! BEAUTIFUL WORK OF ART HAS BEEN CREATED 4HE lRST CHIPS TO COME OUT IN THE S WERE MADE IN SOMEWHAT THE SAME WAY 0HOTORESIST WAS PREVIOUSLY USED ONLY IN THE 0# BOARD INDUSTRY AND TO SOME EXTENT IN MAKING DISCRETE TRANSISTORS (OWEVER ITS USE WAS ADOPTED EARLY ON IN )# MANUFACTURING AND APPLIED TO THE WET ETCHING PROCESSES USED AT THAT TIME 0LASMA PROCESSING WAS INTRODUCED LATER AND PHOTOLITHOGRAPHY GREW EVER MORE SOPHISTICATED
(ARD -ASK &ORMATION 5SING 0LASMA %TCH #HEMICAL 2EACTIONS 4HE EASE WITH WHICH A CHEMICAL REACTION TAKES PLACE DEPENDS A LOT UPON THE STRENGTH OF THE BONDS HOLDING THE REACTANTS TOGETHER &OR EXAMPLE THE STRENGTH OF THE CHEMICAL BONDS HOLDING THE SILICON TO THE OXYGEN IN SILICON DIOXIDE IS MORE THAN DOUBLE THE STRENGTH OF THE BOND HOLDING THE SILICON ATOMS TO EACH OTHER IN SINGLE CRYSTAL SILICON .EEDLESS TO SAY SILICON DIOXIDE ETCHES MUCH MORE SLOWLY THAN SILICON IN A GIVEN SET OF CONDITIONS )N THIS SECTION THE METHODS USED TO INCREASE THE ETCH RATE OF SILICON DIOXIDE ARE DISCUSSED
(ARD -ASK %TCH 3TRATEGY (ERE IS A CONDENSED SUMMARY OF THE STRATEGY EMPLOYED TO ETCH DIELECTRICS THAT ARE DISCUSSED IN THIS SECTION 5SE HIGHLY REACTIVE CHEMICALS !DD ENERGY THROUGH ION BOMBARDMENT TO INCREASE RATE OF REACTION 0ASSIVATE WITH ORGANICS TO AID SELECTIVITY AND TO HELP CONTROL FEATURE SHAPE 3PUTTER OFF ORGANIC PASSIVATION FROM HORIZONTAL SURFACES WITH ACCELERATED IONS TO ALLOW REACTANT ACCESS TO REACTION SITES ON THE MATERIAL BELOW 3I/ #& #(& m 3I& #/ 0ASSIVATING 0OLYMER #OATING
!R 3I&
2ESIST
&
.ITRIDE
#&
#&
&
/XIDE 3ILICON
&IGURE #HEMICAL 3OUP IN A 0LASMA
&IGURE IS AN ATTEMPT TO SUMMARIZE ALL OF THE MAJOR ACTIVITIES GOING ON AT THE WAFER SURFACE -ORE IS ADDED TO THIS DISCUSSION AT THE END OF THE SECTION 4HE LARGE POSITIVE ARGON IONS ARE SHOWN BOMBARDING THE SURFACE ADSORBED CHEMICALS ARE READY TO REACT WHEN ENOUGH ENERGY IS ADDED BY THE BOMBARDMENT 4HE ORGANIC PASSIVANT IS
#HAPTER )SOLATE !CTIVE !REAS 3HALLOW 4RENCH )SOLATION SPUTTERED OFF BY THE ARGON IONS 4HE VOLATILE PRODUCTS OF REACTION ARE SHOWN LEAVING THE SURFACE AND BEING PUMPED OUT OF THE REACTOR 4HE DYNAMIC BALANCE ACHIEVED IN PLASMA ETCH IS TRULY IMPRESSIVE
%TCH #HEMISTRY 3ILICON $IOXIDE AND 3ILICON .ITRIDE )T HAS ALREADY BEEN POINTED OUT THAT THE STRONG BONDS HOLDING OXIDE TOGETHER ARE HARD TO BREAK 4HE SAME GOES FOR NITRIDE 4HE LOW REACTIVITY OF THE lLMS MEANS THEY WILL HAVE A SLOW ETCH RATE ! HIGHLY REACTIVE ETCHANT IS REQUIRED TO BOOST RATE AND INCREASE THROUGHPUT /XIDE AND NITRIDE ARE ETCHED WITH mUORINE & CHEMISTRY &LUORINE IS PART OF 'ROUP 6)) ON THE 0ERIODIC 4ABLE RIGHT NEXT TO THE .OBLE 'ASES 4HE ELEMENTS IN THAT GROUP ARE HIGHLY REACTIVE )N FACT mUORINE AT THE TOP OF THE LIST IS ONE OF THE MOST REACTIVE SUBSTANCES IN THE UNIVERSE )T IS THAT PROPERTY THAT MAKES mUORINE SO USEFUL IN ETCHING THESE TWO SILICON COMPOUNDS &LUORINE WILL PRODUCE THE FASTEST ETCH RATE POSSIBLE ! 4YPICAL /XIDE %TCH #HEMICAL 2EACTION 0LASMA ETCH REACTIONS ARE OFTEN QUITE COMPLICATED WITH A NUMBER OF STEPS INVOLVED &OLLOWING IS A SIMPLIlED EXAMPLE FOR OXIDE ETCH
3I/ #& m 3I&G #/G #/G
+EY 0OINT 4HE PLASMA ETCH CHEMICAL REACTION MUST HAVE VOLATILE PRODUCTS OR THE REACTANT WILL BE BLOCKED FROM THE REACTION SITES BY A LAYER OF SOLID MATERIAL STOP PING THE ETCH REACTION &OR EXAMPLE A mUORINE PLASMA DOES NOT WORK FOR ETCHING ALUMINUM BECAUSE UNLIKE SILICON TETRAmUORIDE ALUMINUM mUORIDE IS NOT VOLATILE )N THE PLASMA 2ADICAL #&
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INDICATES %XCITED 3TATE
&IGURE #& "REAKDOWN IN THE 0LASMA
(ARD -ASK &ORMATION 5SING 0LASMA %TCH -ANY CHEMICALS MAY BE COMBINED TO ETCH SILICON COMPOUNDS 4HESE COMPLICATED ETCH RECIPES HAVE BEEN DEVELOPED TO PRODUCE DIFlCULT FEATURE SHAPES ! VERY IMPOR TANT FACTOR IS THE CONTROL OF REACTION PRODUCTS THAT COAT THE WAFER AND ACT AS PASSIVANTS 4HESE COMPOUNDS HELP TO CONTROL THE SHAPE OF THE FEATURES BEING CREATED ON THE WAFER AS WELL AS ENHANCING THE SELECTIVITY TO UNDERLYING LAYERS $ElNITION ! 2ADICAL IS A GROUP OF TWO OR MORE ATOMS THAT TEND TO ENTER INTO CHEMI CAL COMBINATIONS AS A UNIT 4HE &REE 2ADICAL IS A FORM OF RADICAL THAT HAS ONE OR MORE UNPAIRED FREE ELECTRONS SO IT IS VERY REACTIVE 2ADICALS OFTEN FORM IN A PLASMA 7HEN mUOROCARBON COMPOUNDS ARE BROKEN DOWN IN A PLASMA ONE IMPORTANT PRODUCT IS THE #& RADICAL 4HIS RADICAL HAS TWO UNSATISlED CHEMICAL BONDS SO IT HAS A STRONG TENDENCY TO JOIN MANY OTHER SUCH RADICALS AND FORM CHAINS CALLED POLYMERS 4HIS KIND OF REACTION IS THE BASIS OF THE PLASTICS INDUSTRY 4HE POLYMER POLYTETRAmUOROETHYLENE CHAINS OF THOSE #& RADICALS MENTIONED PREVIOUSLY IS ONE OF THE TYPES OF POLYMER THAT FORM IN OXIDE ETCH PLASMAS )T IS A FORM OF 4EmON® AND IT IS VERY RESISTANT TO CHEMICAL ATTACK 4HE POLYMERS FORMED IN ETCH PLASMA MAY NOT BE QUITE AS TIDY IN CHEMICAL COMPOSITION AS THIS BUT THEY ARE STILL EFFECTIVE PASSIVANTS 4HE POPULAR PARALLEL PLATE REACTOR &IGURE HAS BEEN CHOSEN TO ILLUSTRATE HOW AN ETCHER ACCOMPLISHES THE OBJECTIVES REQUIRED BY THE PROCESS 0OWER 3UPPLY 0OSITIVE )ONS
6
0LASMA
0OSITIVE IONS ATTRACTED TO NEGATIVE VOLTAGE AT LOWER ELECTRODE
&IGURE 4HE 0LASMA IN A 0ARALLEL 0LATE 2EACTOR
4HE ETCH REACTOR OPERATES AT A LOW PRESSURE 3TANDARD ATMOSPHERIC PRESSURE IS 4ORR PSI %TCH REACTORS OPERATE AT PRESSURES MUCH LOWER THAN THAT USUALLY IN THE MILLITORR RANGE THOUSANDTHS OF A 4ORR 4HAT MAY SOUND LIKE A QUITE LOW PRESSURE
#HAPTER )SOLATE !CTIVE !REAS 3HALLOW 4RENCH )SOLATION BUT AT ONE 4ORR THERE ARE STILL ABOUT ¾ ATOMS OR MOLECULES OF GAS IN A CUBIC CENTIMETER 4HATS OVER A MILLION BILLION PARTICLES OF GAS #LEARLY THERE IS STILL PLENTY OF GAS AVAILABLE TO MAKE THE CHEMICAL REACTION GO %VANGELISTA 4ORRICELLI 4HE FAVORITE UNIT OF PRESSURE USED BY THE SEMICONDUCTOR INDUSTRY IS THE 4ORR 4HE NAME OF THAT UNIT OF PRESSURE HONORS %VANGELISTA 4ORRICELLI WHO INVENTED THE BAROMETER 4ORRICELLI lLLED A LONG GLASS TUBE THAT WAS SEALED AT ONE END WITH MERCURY 4HEN WITH HIS THUMB OVER THE OPEN END OF THE TUBE HE UPENDED IT AND IMMERSED THE OPEN END IN A BOWL OF MERCURY (G 4HE MERCURY DROPPED AWAY FROM THE SEALED END A SHORT WAY AND FELL NO FURTHER 4HE COLUMN OF MERCURY STOOD IN TODAYS UNITS ABOUT MILLIMETERS HIGH 4HE COLUMN HEIGHT VARIED SLIGHTLY FROM DAY TO DAY BUT THE AVERAGE REMAINED MM 4ODAY THE ACCEPTED VALUE OF STANDARD ATMOSPHERIC PRESSURE AT SEA LEVEL IS MM OF (G OR 4ORR )T IS ANOTHER ONE OF HISTORYS SURPRISING CONNECTIONS IS THAT 3IGNOR 4ORRICELLI WAS 'ALILEOS SECRETARY
-ERCURY COLUMN HEIGHT ^ CM
-ERCURY
&IGURE 4ORRICELLIS "AROMETER
(ARD -ASK &ORMATION 5SING 0LASMA %TCH ! CONTROLLED AMOUNT OF THE DESIRED GAS IS ALLOWED TO mOW INTO THE CHAMBER ! SPECIAL SET OF VACUUM PUMPS CONTINUALLY REMOVES THE GAS FROM THE CHAMBER 2ECALL THAT THE PRODUCTS OF REACTION MUST BE VOLATILE FOR THE ETCH TO PROCEED SO THEY ARE BEING CONTINUALLY PUMPED OUT OF THE REACTOR !S SHOWN IN &IGURE THE WAFER SITS ON ONE ELECTRODE 7HEN THE POWER IS TURNED ON AN ELECTRIC lELD FORMS BETWEEN TWO ELECTRODES 4HE IONS FORMED IN THE PLASMA ARE ACCELERATED TOWARD THE WAFER PROVIDING THE BOMBARDMENT ENERGY TO DRIVE THE ETCH REACTION VERTICALLY DOWNWARDS +EY 0OINT 4HE DIFFUSION OF GAS MOLECULES WITHIN THE REACTION CHAMBER IS THE PRIMARY WAY THAT GAS REACTANT REACHES THE WAFER SURFACE &IGURE ATTEMPTS TO ILLUSTRATE THE hCHEMICAL SOUPv INSIDE THE ETCH REACTOR EVERYTHING IS HAPPENING AT ONCE v !DSORBED REACTANTS ETCH THE OXIDE v "OMBARDING ARGON !R IONS ADD ENERGY TO SPEED THE RATE OF REACTION v $EPOSITION OF POLYMERS FOR PASSIVATION OF SIDEWALLS AND IMPROVED SELECTIVITY VERTICAL SIDEWALLS ARE CRITICAL TO THIS ETCH v "OMBARDMENT PHYSICALLY KNOCKS OFF SPUTTERS THE DEPOSITED PASSIVATION FROM HORIZONTAL SURFACES EXPOSING THEM TO REACTANT v 3PUTTERING OF EXPOSED lLM IS MINOR BUT EXISTS IN SOME ETCHES 4HE REMAINING PHOTORESIST IS REMOVED BY THE PLASMA ETCHER PRIOR TO PROCEEDING TO THE NEXT STEP ETCHING THE TRENCHES 0HOTORESIST ETCHING OR hASHINGv WAS DElNED EARLIER IN THIS SECTION
&IGURE 4HE #OMPLETED (ARD -ASK
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&ORM 4RENCHES IN 3ILICON WITH 0LASMA %TCH $ElNITION 4RENCH %TCH IS THE PROCESS OF ETCHING TRENCHES IN THE SILICON SUBSTRATE 0URPOSE OF 4RENCH %TCH 4HE TRENCHES ARE SHAPED TO EXACTING SPECIlCATIONS SO THAT WHEN lLLED WITH INSULATING OXIDE THEY WILL PROVIDE A SUFlCIENT BARRIER TO CURRENT mOW BETWEEN TRANSISTORS $ISCUSSION 3ILICON ETCH IS DONE WITH CHLORINE AND BROMINE 4HE TRENCHES ARE ETCHED PRIMARILY WITH CHLORINE "ROMINE ENTERS THE PROCESS IN LATER STEPS WHEN ADDITIONAL RIGOROUS REQUIREMENTS LIMIT THE USE OF THE MORE AGGRESSIVE CHLORINE 4HE NEED FOR SIDEWALL PASSIVATION IS JUST AS PROMINENT FOR TRENCH ETCH AS FOR ANY APPLICATION 4HE PASSIVATION DETERMINES THE SLOPE OF THE SIDEWALL AND IT HELPS WITH OTHER ASPECTS OF SHAPING THE TRENCH BOTTOM AND TOP EDGES 4HE PASSIVATION PRODUCED AT TRENCH ETCH IS VERY UNUSUAL IN THAT IT IS NOT AN ORGANIC MATERIAL 4HE ADDITION OF OXYGEN TO THE SILICON ETCH RECIPE PRODUCES A SILICON OXYGEN CHLORINE BYPRODUCT THAT IS NOT VOLATILE 4HIS COMPOUND IS PRESENT IN SMALL AMOUNTS WHEN SIMILAR CHEMICAL COMBINATIONS ARE USED FOR OTHER APPLICATIONS BUT HERE THERE IS SO MUCH SILICON TO BE REMOVED THAT USEFUL QUANTITIES OF THE COMPOUND ARE AVAILABLE 4HE AMOUNT PRODUCED IS EASILY CONTROLLED BY SIMPLY ADJUSTING THE AMOUNT OF OXYGEN USED IN THE ETCH RECIPE 4HE INORGANIC PASSIVANT REQUIRES A WET DIP IN DILUTE HYDROmUORIC ACID (& TO REMOVE IT AFTER PROCESSING
#HAPTER )SOLATE !CTIVE !REAS 3HALLOW 4RENCH )SOLATION %XAMPLE OF 3ILICON %TCH #HEMISTRY
3IS #LG /G m 3I#LG 3I/#LXS
&IGURE #OMPLETED 4RENCH WITH (ARD -ASK 3TILL IN 0LACE
)N THIS EXAMPLE SILICON COMBINES WITH CHLORINE AND OXYGEN TO FORM SILICON TETRA CHLORIDE AND SILICON OXYCHLORIDE &LUORINE IS TOO AGGRESSIVE TO BE USED FOR SILICON ETCH AND PRODUCES AN ISOTROPIC PROlLE #HLORINE ETCHES ANISOTROPICALLY BUT STILL HAS A HIGH ETCH RATE SO IT IS PREFERRED FOR THIS APPLICATION (ERE IS THE COMPLETED TRENCH 4HE SHAPE WILL VARY SOMEWHAT DEPENDING ON THE PART BEING MADE BUT THIS GENERALIZATION SHOWS THE PRINCIPAL FEATURES 4HE SIDEWALL SLOPE SHOULD BE CLOSE TO VERTICAL SO THAT SPACE IS CONSERVED 3LIGHT BOTTOM ROUNDING NOT SHOWN IN &IGURE IS IMPORTANT TO ENSURE THAT THE TRENCH IS EASILY AND COMPLETELY lLLED WITH OXIDE LEAVING NO VOIDS THAT MIGHT TRAP CONTAMINANTS AND CAUSE A RELIABILITY ISSUE 4HE TOP EDGES OF THE TRENCH ARE ALSO SLIGHTLY ROUNDED ALSO NOT SHOWN IN lGURE TO MINIMIZE A CURRENT LEAKAGE PROBLEM 3HARP EDGES ON A CONDUCTOR CAUSE THE ELECTRIC lELD TO INTENSIFY AND MAY CREATE STRIPS AT THE EDGES OF THE TRANSISTOR WHICH REMAIN CONDUCTIVE EVEN WHEN THE TRANSISTOR SHOULD BE TURNED OFF
3%#4)/.
&ILL 4RENCHES WITH 3ILICON $IOXIDE $ElNITION 4HE 4RENCH &ILL 0ROCESS CONSISTS OF TWO PARTS &IRST THE TRENCHES ARE LINED WITH THERMAL OXIDE 3ECOND THE BULK OF THE TRENCH IS lLLED WITH DEPOSITED #6$ OXIDE 0URPOSE /XIDE IS THE INSULATING MATERIAL THAT PROVIDES THE ELECTRICAL ISOLATION BE TWEEN TRANSISTORS 4RANSISTORS ARE PACKED AS CLOSELY TOGETHER ON A CHIP AS THEY CAN BE 7ITHOUT GOOD ELECTRICAL ISOLATION THEY WOULD ELECTRICALLY INTERFERE WITH EACH OTHER AND THE CHIP WOULD NOT WORK $ISCUSSION 4HE TWO STEP PROCESS FOR TRENCH lLL IS NECESSARY FOR SEVERAL REASONS 4HE THIN THERMAL OXIDE LINER GROWN lRST ELECTRICALLY STABILIZES THE SILICON SURFACE )T ALSO ROUNDS OFF THE SHARP CORNERS WHICH CREATE THE ELECTRICAL PROBLEMS DISCUSSED EARLIER
&IGURE /XIDE $EPOSITED TO &ILL 4RENCHES
#HAPTER )SOLATE !CTIVE !REAS 3HALLOW 4RENCH )SOLATION 4HE BULK OF THE OXIDE lLL IS DONE WITH A #6$ OXIDE %ACH TYPE OF OXIDE HAS DIFFERENT GAP lLL CHARACTERISTICS AND PRODUCES OXIDES WITH VARYING PROPERTIES 6OID FOR MATION MUST BE AVOIDED TO PREVENT TRAPPED CONTAMINANTS AND PRODUCTION OF PARTS WITH VARYING ELECTRICAL PROPERTIES 4HE NATURE OF THE lLL OXIDE WILL ALSO AFFECT THE STRESSES PRODUCED IN THE SILICON AT THE TRENCH SIDEWALLS DURING OXIDE DENSIlCATION ANNEALS AND OTHER THERMAL CYCLES IN WAFER FABRICATION 4HESE STRESSES CAN RESULT IN INCREASED PN JUNCTION LEAKAGE IN THE TRANSISTORS )N ADDITION THE CHARACTERISTICS OF THE lLL OXIDE WILL AFFECT THE #-0 STEP !N EXAMPLE OF A DEPOSITION TECHNOLOGY THAT CAN lLL TRENCHES WITH GOOD QUALITY VOID FREE OXIDE IS HIGH DENSITY PLASMA ($0 #6$ ($0 COMBINES DEPOSITION WITH A SMALL ETCHING COMPONENT IN THE PROCESS 4HE DETAILS OF THIS TECHNOLOGY CAN BE FOUND IN SOME OF THE REFERENCES IN THE "IBLIOGRAPHY 7OLF 'HANDHI 2EFER TO #HAPTER FOR A DISCUSSION OF THERMAL OXIDE GROWTH AND 3ECTION OF THIS CHAPTER FOR #6$ PROCESSES
3%#4)/.
#HEMICAL -ECHANICAL 0OLISHING #-0 TO 2EMOVE %XCESS /XIDE $ElNITION #HEMICAL MECHANICAL POLISHING IS A PROCESS THAT GRADUALLY REMOVES MATE RIAL FROM THE WAFER BY A COMBINATION OF PHYSICAL ABRASION AND CHEMICAL ACTION THAT IS USUALLY ASSISTED BY CHEMICAL REACTION 0URPOSE 4HE PURPOSE OF #-0 IS TO REMOVE MATERIAL FROM THE WAFER SURFACE WITHOUT DAMAGING THE DEVICES BEING BUILT ON THE WAFER 0LANARIZING mATTENING THE WAFER SURFACE IS REQUIRED FOR SOME APPLICATIONS AND A SIDE BENElT FOR OTHERS 3LURRY $ISPENSER
0OLISHING (EAD
7AFER 0OLISHING 0AD
&IGURE #-0 4OOL
$ISCUSSION )N THE 34) PROCESS THE SURFACE OF THE WAFER IS QUITE UNEVEN AFTER THE OXIDE TRENCH lLL 2ECALL THAT THE NITRIDEOXIDE HARD MASK MUST BE REMOVED TO UNCOVER THE AREAS WHERE THE TRANSISTORS WILL BE BUILT "UT lRST THE UNWANTED DEPOSITED OXIDE PILED ON TOP OF THESE AREAS MUST BE REMOVEDAND WITHOUT REMOVING THE OXIDE IN THE TRENCHES #-0 CAN DO THAT EFFECTIVELY AND LEAVE THE SURFACE WELL PLANARIZED 4HE NEED FOR A mAT SURFACE ON THE WAFER HAS LED TO THE USE OF #-0 AT SEVERAL PLAC ES IN THE CHIPMAKING PROCESS )T HAS REPLACED PLASMA OR WET ETCH WHICH WAS FORMERLY
#HAPTER )SOLATE !CTIVE !REAS 3HALLOW 4RENCH )SOLATION THE ONLY lLM REMOVAL METHOD AVAILABLE #LEARLY THE CHEMICAL REMOVAL OF A lLM WILL BE NEARLY CONFORMAL AND ALTHOUGH MANY CLEVER SCHEMES WERE TRIED ETCH COULD NEVER DO AN ADEQUATE JOB OF PLANARIZATION 4HE ORIGINAL USE OF #-0 IN WAFER FABRICATION WAS TO PLANARIZE THE SURFACE AS AN AID TO PHOTOLITHOGRAPHY 4HAT APPLICATION AND SEVERAL OTHERS WILL BE DISCUSSED IN LATER CHAPTERS 0ROCESS &LOW 0OLISH SILICON DIOXIDESILICON NITRIDE WITHOUT BREAKING THROUGH THE NITRIDE 0OST #-0 RINSEDRY #HEMICAL MECHANICAL POLISHING MAY SEEM LIKE A VERY NEW AND SOPHISTICATED TECHNOL OGY BUT IT IS ACTUALLY BASED UPON A VERY OLD PROCESS 4HE FUNDAMENTAL PROCESS IS USED FOR LENS GRINDING AND HAS BEEN IN USE FOR CENTURIES 4HE USE OF #-0 FOR POLISHING PLATE GLASS GOES BACK A CENTURY OR MORE )N THE EARLY YEARS OF THE INDUSTRY THE BARE STARTING WAFERS NEEDED FOR CHIP FABRICATION WERE POLISHED USING SUCCESSIVELY lNER GRADES OF ABRASIVE PARTICLES )N THE S CHEMICAL MECHANICAL POLISHING WAS DEVELOPED FOR SILICON WAFERS 4HE INTRODUCTION OF #-0 RESULTED IN LESS DAMAGE TO THE CRYSTAL STRUCTURE AT THE WAFER SURFACE THAN WITH ABRASIVE ONLY POLISHING 2EMEMBER THAT DEVICES ARE BUILT IN A VERY SHALLOW LAYER AT THE WAFER SURFACE AND THIS DAMAGE CAN EASILY HARM DEVICE PERFOR MANCE IN VARIOUS WAYS NOTABLY BY INCREASING JUNCTION LEAKAGE CURRENTS )N THE S #-0 FOUND ITS WAY INTO THE WAFER FABRICATION CYCLE lRST TO PLANARIZE IRREGULAR SURFACES TO ASSIST PHOTOLITHOGRAPHIC PATTERNING OF SMALL FEATURES AND THEN FOR SEVERAL OTHER APPLICATIONS AS WE WILL SEE LATER #-0 )NTRODUCED TO THE &AB %XPERIENCED ENGINEERS REMEMBER THE lRST TIME THAT #-0 WAS INTRODUCED TO FAB PROCESSING 5NTIL THAT TIME IT WAS ABSOLUTELY FORBIDDEN TO TOUCH THE FRONT OF THE WAFER BECAUSE IT WOULD KILL THE DEVICES AND REDUCE YIELD )T WAS A SHOCK TO HEAR THAT THE WAFER COVERED WITH PARTIALLY COMPLETED CHIPS WAS TO BE PLACED FACE DOWN ON A GRINDING WHEEL AND SLURRY WOULD BE USED TO REMOVE THE lLM %VERYONE WAS SURE THAT THE ENTIRE WAFER WOULD BE RUINED BY THE POLISHING OR BY THE HUGE NUMBER OF PARTICLES LEFT BEHIND AFTERWARD 4HAT THE OPPOSITE RESULT CAME ABOUT IS VERY FORTUNATE BECAUSE #-0 SOLVES MANY PROCESSING PROBLEMS IN THE FAB
#HEMICAL -ECHANICAL 0OLISHING #-0 TO 2EMOVE %XCESS /XIDE #-0 0RINCIPLES 4HE #-0 TOOL MUST REMOVE THE lLM AS FAST AS POSSIBLE WITHOUT LEAVING A ROUGH DAMAGED SURFACE BEHIND !S IT TURNS OUT THE BEST WAY TO DO IT OFTEN INVOLVES USING A VERY SMALL AMOUNT OF CHEMICAL TO REACT WITH A VERY THIN LAYER OF THE SURFACE OF THE lLM DISSOLUTION 4HAT HELPS THE ABRASIVE PARTICLES TO CUT AND PULL AWAY MICROSCOPIC PARTICLES OF THE lLM FROM THE SURFACE )N ADDITION SOME METALS POLISH EASIER IF THEIR SURFACE IS OXIDIZED THE OXIDE FORM OF THE METAL IS EASIER FOR THE ABRASIVE TO REMOVE WITHOUT DAMAGING THE UNDERLYING WAFER )N OTHER CASES ONLY $) WATER IS USED AS THE LIQUID COMPONENT OF THE SLURRY 4HERE ARE A WIDE VARIETY OF MECHANISMS INVOLVED AND THE TECHNOLOGY IS CHANGING VERY RAPIDLY .EVERTHELESS THE PRINCIPAL lLM REMOVAL MECHANISM REMAINS THE PHYSICAL ACTIVITY OF THE ABRASIVE (OW )TS $ONE #-0 IS REALLY TRICKY 4HERE IS A LOT GOING ON &IRST HERE IS A LIST OF THE MAIN COMPONENTS OF THE #-0 PROCESS
4HE 0AD 4HE 3LURRY A 4HE !BRASIVE 0ARTICLES B 4HE ,IQUID #OMPONENTS
4HE LIQUID COMPONENT OF THE SLURRY WILL TYPICALLY CONTAIN DEIONIZED $) WATER AN ACID A BASE AN OXIDIZER OR SOME COMBINATION OF THOSE FOUR 4HE LIQUID OFTEN DISSOLVES A SO CALLED MONOLAYER OR TWO OF MATERIAL )T ALSO CARRIES THE ABRASIVE TO THE WAFER AND CARRIES THE PARTICLES AWAY FROM THE WAFER ,ET US NOT FORGET ABOUT HEATTHE POLISH RATE IS VERY TEMPERATURE DEPENDENT 4HE LIQUID HELPS CARRY AWAY THE HEAT GENERATED BY THE ABRASIVE POLISHING 4HE ABRASIVE IS ALSO HIGHLY SPECIALIZED -ANY MATERIALS ARE AVAILABLE TO USE BUT THESE THREE DOMINATE THE PRACTICE TODAY SILICON DIOXIDE ALUMINUM OXIDE ALUMINA AND CERIUM OXIDE )T MAY COME AS A SURPRISE BUT THE POLISHING PAD IS A VERY COMPLICATED AND SPECIAL IZED MATERIAL !GAIN THERE ARE SEVERAL CHOICES FOR THE PAD MATERIAL BUT POLYPROPYLENE DOMINATES THE INDUSTRY AT THIS TIME %NTHUSIASTIC EXPERIMENTATION IS CURRENTLY TAKING PLACE AND NEW PAD MATERIALS COULD EMERGE ON PRODUCTION TOOLS AT ANY TIME ! TYPICAL #-0 TOOL WILL HAVE MANY PROCESS VARIABLES OFTEN EIGHTEEN OR MORE THAT ALL HAVE TO BE ADJUSTED TO OPTIMIZE THE PROCESS 3OME OF THE MOST IMPORTANT ARE THE AMOUNT OF PRESSURE PUSHING THE WAFER AGAINST THE PAD THE SLURRY mOW RATE THE PAD SPEED THE PERCENT SOLIDS IN THE SLURRY AND ON AND ON
#HAPTER )SOLATE !CTIVE !REAS 3HALLOW 4RENCH )SOLATION
&IGURE 0OST #-0 #LEAN 4OOL
4HE POST #-0 CLEAN IS ALMOST AS CHALLENGING AS THE #-0 PROCESS ITSELF !LL OF THE PARTICLES THAT WERE DELIBERATELY GENERATED DURING THE POLISH MUST BE REMOVED 4HE LIQUIDS THAT ARE USED FOR THAT PURPOSE ARE MUCH THE SAME AS THE SLURRY BUT WITHOUT THE ABRASIVE COMPONENT 4HE SPECIAL CHARACTERISTICS OF THE PARTICULATE MATERIALS CAN BE USED TO AID IN RE MOVING THEM &OR EXAMPLE THE 34) POLISH IS PRIMARILY AN OXIDE POLISH 2ECALL THAT THE OXIDE OR GLASS PARTICLES ARE GOOD ELECTRICAL INSULATORS 4HAT ALSO MEANS THAT THEY WILL HOLD A STATIC ELECTRICAL CHARGE 7HEN 3I/ PARTICLES ARE PLACED IN A BASIC SOLU TION THEY TAKE ON A NEGATIVE ELECTRICAL CHARGE !MMONIA A FAMILIAR BASE IS A FAVORITE COMPONENT IN THE CLEANING SOLUTION )F ALL OF THE PARTICLES HAVE THE SAME CHARGE THEY REPEL EACH OTHER )N ADDITION THE REMAINING OXIDE ON THE WAFER SURFACE TAKES ON THE SAME NEGATIVE CHARGE !LL OF THIS ELECTRICAL REPULSION MAKES IT MUCH EASIER TO REMOVE THE PARTICLES THEY DO NOT TEND TO AGGLOMERATE AND REDEPOSIT ON THE WAFER NOR DO THEY STICK TO THE WAFER SURFACE 4HE POST #-0 CLEAN IS FOLLOWED BY A $) WATER RINSE AND HOT NITROGEN GAS DRYING OPERATION 4HE WAFERS ARE THEN READY FOR THE NEXT PROCESSING STEP
&IGURE &ILLED 4RENCHES AFTER #-0
3%#4)/.
7ET %TCH 2EMOVAL OF 3ILICON .ITRIDE AND 0AD /XIDE $ElNITION 7ET %TCH IS THE USE OF LIQUID CHEMICALS TO REMOVE MATERIAL FROM THE WAFER SURFACE 0URPOSE 4HIS STEP REMOVES THE REMAINING SILICON NITRIDE AND THE PAD OXIDE FROM THE WAFER WHILE LEAVING THE UNDERLYING SILICON UNDAMAGED $ISCUSSION 7ET CHEMICALS SUCH AS PHOSPHORIC ACID FOR NITRIDE ETCH AND DILUTE HYDROmUORIC ACID FOR OXIDE ETCH WILL REMOVE SPECIlC lLMS WITH VERY HIGH SELECTIVITY TO OTHER lLMS )N OTHER WORDS THE NITRIDE AND PAD OXIDE CAN BE STRIPPED OFF WITHOUT DAMAGING THE UNDERLYING SILICON SUBSTRATE 4HAT IS VERY IMPORTANT BECAUSE THE SURFACE OF THE 3I WAFER BELOW THE NITRIDE IS WHERE THE TRANSISTORS ARE TO BE BUILT 4HAT SURFACE MUST BE KEPT IN NEAR PERFECT CONDITION 4HE AUTOMATED WET BENCH SEQUENTIALLY PUTS THE WAFERS IN ACID BATHS AND $) WATER RINSE BATHS 0ROCESSING TIME IS CAREFULLY CONTROLLED !UTOMATED TOOLS ARE A MAJOR IMPROVEMENT TO SAFETY IN THE FAB &AB PERSONNEL ARE NO LONGER REQUIRED TO CONSTANTLY COME IN CLOSE PROXIMITY TO THE PROCESSING CHEMICALS 4HE LIQUID CHEMICALS CAN BE VERY DANGEROUS &OR EXAMPLE HYDROmUORIC ACID (& ATTACKS THE BONES WITHOUT BURNING THE SKIN SO A PERSON IS OFTEN UNAWARE OF ACCIDENTAL EXPOSURE UNTIL SOME TIME HAS PASSED 0HOSPHORIC ACID IS HEATED TO ABOUT # AND A FAVORITE PHOTORESIST STRIPPING SOLUTION A MIX OF SULFURIC ACID AND HYDROGEN PEROXIDE TO ABOUT # 4HESE ACIDS AND OXIDIZERS ARE DANGEROUS AT ROOM TEMPERATURE BUT ARE EVEN MORE SO AT HIGH TEMPERATURE
#HAPTER )SOLATE !CTIVE !REAS 3HALLOW 4RENCH )SOLATION
3PIN 2INSE$RYER 7AFERS IN CARRIER ARE ROTATED IN AN ENCLOSED CHAMBER WHILE WATER RINSED AND AIR OR NITROGEN DRIED
&IGURE 3PIN 2INSER $RYER
!FTER PROCESSING THE WAFERS GO INTO A SPIN RINSER DRYER AS SHOWN IN &IGURE 4HE TOOL SPINS THE WAFERS RINSES THEM WITH $) WATER AND THEN DRIES THEM IN HOT NITRO GEN GAS
&IGURE #OMPLETED /XIDE &ILLED 4RENCHES
4HE WAFERS MAY NOW PROCEED TO THE NEXT MAJOR OPERATION IN THE MANUFACTURING PROCESS THE BUILDING OF THE TRANSISTORS
#(!04%2
"UILDING THE 4RANSISTORS
This Page Intentionally Left Blank
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)NTRODUCTION )N THIS CHAPTER YOU WILL LEARN v (OW THE TRANSISTORS ARE BUILT v (OW THE lELD EFFECT TRANSISTOR WORKS v 4HE IMPORTANCE OF HIGH K MATERIALS FOR THE GATE DIELECTRIC v 0USHING THE LIMITS OF TECHNOLOGY TO MAKE FASTER PARTS v (OW THE LIGHTLY DOPED DRAIN ,$$ IS FORMED AND WHY IT IS NEEDED 6OLTAGE ON GATE CREATES SOURCE TO DRAIN CONDUCTING CHANNEL
'ATE
#URRENT /UT
#URRENT )N
3OURCE
$RAIN
&IGURE #-/3 4RANSISTOR
#HAPTER "UILDING THE 4RANSISTORS $ElNITION ! -ETAL /XIDE 3EMICONDUCTOR &IELD %FFECT 4RANSISTOR -/3&%4 IS THE FUNDAMENTAL ELECTRICAL COMPONENT OF THE #-/3 CHIP 4HE ACTION OF THE TRANSIS TOR IS CONTROLLED BY AN ELECTRIC lELD !S MENTIONED PREVIOUSLY THE hMETALv IN THE NAME REFERS TO THE EARLIEST CHIPS THAT USED ALUMINUM INSTEAD OF THE POLYCRYSTALLINE SILICON IN USE TODAY AS THE GATE ELECTRODE 4HE OXIDE AND SEMICONDUCTOR ELEMENTS OF THE TRANSISTOR ARE FAMILIAR TO THE READER BY THIS TIME 0URPOSE 4HE -/3&%4 IS VERY VERSATILE AND OFFERS MANY OPTIONS TO THE CIRCUIT DE SIGNER &OR THIS DISCUSSION THE -/3&%4 IS USED AS A SWITCH -/3&%4S AND /THER 4RANSISTORS )N #HAPTER IT WAS POINTED OUT THAT THE hCOMPUTER CHIPv WOULD BE THE FOCUS OF THIS DISCUSSION BECAUSE THAT TYPE OF CHIP CLEARLY ILLUSTRATES THE FUNCTION OF A LARGE PERCENTAGE OF THE PARTS MADE TODAY )T IS IMPORTANT TO BEAR IN MIND THAT THERE ARE MANY DIFFERENT KINDS OF TRANSISTORS USED IN OTHER TYPES OF CHIPS AND ELECTRICAL COMPONENTS THAT WILL NOT BE DISCUSSED IN THIS TEXT 4HE MOST NOTABLE EXAMPLE IS THE BIPOLAR TRANSISTOR THAT CAN BE USED FOR MANY APPLICATIONS )N FACT NEARLY ALL THE CHIPS MADE IN THE lRST TEN YEARS OF )# MANUFACTURING WERE BASED ON BIPOLAR TRANSISTORS THE lRST KIND OF TRANSISTOR INVENTED )T CAN ACT AS A SWITCH AS AN AMPLIlER OR PERFORM OTHER SPECIALIZED FUNCTIONS 3OME TITLES FOR FURTHER READING ARE MENTIONED IN THE APPENDIX
4RANSISTOR "UILDING 0ROCESS &LOW
4HIN lLM FORMATION A 'ATE DIELECTRIC OXIDATION B $EPOSIT POLYCRYSTALLINE SILICON C $EPOSIT NITRIDE CAP FOR HARD MASK
0OLY GATE FORMATION USING HARD MASK A 0HOTOLITHOGRAPHY PROCESS TO PATTERN RESIST B 4RIM RESIST IN ETCHER C %TCH NITRIDE HARD MASK D %TCH POLY LINES
)NTRODUCTION
,IGHTLY DOPED DRAIN ,$$ FORMATION A 3HALLOW LOW DOSE DOPANT IMPLANT B &ORM SPACERS I $EPOSIT NITRIDE II %TCH SPACERS C (IGH DOSE DOPANT IMPLANT D 240 ANNEAL
3ALICIDE FORMATION A 3PUTTER COBALT B 240 REACTION FORMING SILICIDE C 3TRIP RESIDUAL COBALT D !NNEAL SILICIDE FORMS LOW RESISTANCE SILICIDE
+EY 0OINTS IN THE 4RANSISTOR "UILDING 0ROCESS %ACH OF THE FOLLOWING POINTS WILL BE EXPLAINED IN THE APPROPRIATE SECTIONS OF THIS CHAPTER (IGH K DIELECTRIC MATERIALS ARE NEEDED TO REPLACE THERMAL OXIDE AS THE GATE DIELECTRIC 2ESIST TRIMMING IS OFTEN USED TO REDUCE THE WIDTH OF THE POLY LINE BECAUSE SOME STEPPERS CURRENTLY IN PRODUCTION CANNOT PRINT A SMALL ENOUGH FEATURE ! HARD MASK IS SOMETIMES REQUIRED BECAUSE RESIST TRIMMING ERODES THE RESIST MASK 4HE LIGHTLY DOPED DRAIN ,$$ PROCESS THAT PRODUCES A GRADED DOPING PROlLE FOR THE SOURCE AND DRAIN IS REQUIRED TO MINIMIZE POTENTIAL RELIABILITY PROBLEMS 3ILICIDATION OF CONTACT SURFACES IS NECESSARY FOR LOW RESISTANCE CONNECTIONS TO THE SOURCE DRAIN AND GATE )T ALSO INCREASES THE ELECTRICAL CONDUCTIVITY IN THOSE REGIONS SPEEDING UP THE CHIP $ISCUSSION "ECAUSE THE -/3&%4 IS THE HEART OF THE CHIP A SHORT DISCUSSION OF SOME OF THE PAR TICULARS REGARDING IT IS IN ORDER 4HE FOCUS OF THIS DISCUSSION WILL CONTINUE TO BE ON THE N CHANNEL -/3&%4 IN THE ROLE AS A SWITCHING COMPONENT OF A GENERALIZED COMPUTER CHIP -/3&%4S lND USES IN A VERY BROAD RANGE OF CHIP TYPES BUT THIS DISCUSSION WILL BE LIMITED TO ITS PRIMARY FUNCTION IN THE DIGITAL COMPUTER lELD
#HAPTER "UILDING THE 4RANSISTORS 'ATE 'ATE DIELECTRIC
N TYPE DRAIN
N TYPE SOURCE P 4YPE 3ILICON SUBSTRATE
&IGURE 4HE N CHANNEL -/3&%4 #ROSS 3ECTION
)N THIS CHAPTER THE -/3&%4 WILL BE BUILT )T IS WIDELY RECOGNIZED AS THE WORK HORSE OF THE ELECTRONICS INDUSTRY "ECAUSE -/3&%4S WILL SWITCH ON AND OFF AT GREAT SPEED WHILE USING RELATIVELY LITTLE POWER THEY CAN BE USED IN DIGITAL LOGIC CIRCUITS OF ALL SORTS 4ODAYS COMPUTER TECHNOLOGY HAS BEEN BUILT ON THE ADVANCES IN -/3&%4 PERFORMANCE !LTHOUGH THIS DISCUSSION IS LIMITED TO THE USE OF -/3&%4S IN COMPUTER APPLICA TIONS THE READER IS REMINDED THAT THESE TRANSISTORS ARE ALSO WIDELY USED AS AMPLIlERS AND OTHER SPECIALIZED COMPONENTS THAT ARE BEYOND THE SCOPE OF THIS BOOK "EAR IN MIND THAT #-/3 TECHNOLOGY REQUIRES BOTH N CHANNEL AND P CHANNEL -/3&%4S IN COMBINATION 4HESE PAIRS OF TRANSISTORS WILL BE SHOWN IN THE lGURES BEGINNING WITH THE LAST GRAPHIC IN #HAPTER &OR MANUFACTURING PURPOSES THE 6
6
%LECTRONS ATTRACTED TO SILICON SURFACE FORM CHANNEL
3OURCE
E E E E
N
P 3ILICON
E E E E
$RAIN
N
3OURCE
#URRENT CANNOT FLOW SOURCE TO DRAIN
E E E E
N
E
P 3ILICON
E E E E
$RAIN
N
#URRENT CAN FLOW SOURCE TO DRAIN
&IGURE 4HE N CHANNEL -/3&%4 3WITCHING !CTION
)NTRODUCTION P CHANNEL DEVICE IS MADE GENERALLY THE SAME WAY AS THE N CHANNEL BUT THE DOPANTS ARE CHANGED TO REVERSE ALL OF THE POLARITIES 4HE TRANSISTOR SHOWN IN &IGURE IS CALLED AN N CHANNEL TRANSISTOR SINCE IN THIS FORM OF THE DEVICE A POSITIVE VOLTAGE ON THE GATE ATTRACTS ELECTRONS NEGATIVE CHARGE CARRIERS TO THE SILICON SURFACE UNDER THE GATE THE GATE DIELECTRIC WILL NOT ALLOW THE ELECTRONS TO PASS THROUGH IT SO THEY ACCUMULATE AT THE INTERFACE )F THE VOLTAGE APPLIED IS GREATER THAN WHAT IS CALLED THE THRESHOLD VOLTAGE ENOUGH ELECTRONS WILL ACCUMULATE TO FORM A CONDUCTING CHANNEL BETWEEN THE SOURCE AND DRAIN OF THE TRANSISTOR .OW A CURRENT WILL mOW BETWEEN THE SOURCE AND DRAIN TURNING THE SWITCH hONv 7ITH NO VOLT AGE ON THE GATE NO CHANNEL IS FORMED AND THE TRANSISTOR IS hOFFv $IGITAL ,OGIC .OTE )N A SIMPLE DIGITAL CHIP LIKE A $2!- WHERE THE CHARGE OR LACK OF CHARGE ON A CAPACITOR REPRESENTS EACH BIT OF INFORMATION THE /&& POSITION IS CONVEN TIONALLY INTERPRETED IN DIGITAL LOGIC AS A ZERO IN BINARY ARITHMETIC THE /. STATE IS CONVENTIONALLY A BINARY ONE 4HINGS GET MORE INVOLVED WITH #-/3 TECHNOLOGY WHERE MORE THAN ONE TRANSISTOR IS INVOLVED IN PRODUCING EACH DIGITAL BIT OF INFORMATION ,OGIC CIRCUITS FOR EXAMPLE ASSIGN A LOW AND HIGH VOLTAGE LEVEL RELATIVE TO SOME REFERENCE VOLTAGE TO REPRESENT ZERO AND ONE
4HE NAME hlELD EFFECT TRANSISTORv MAKES IT CLEAR THAT THE ELECTRIC lELD FORMED BETWEEN THE GATE AND SUBSTRATE SILICON IS EXACTLY WHAT MAKES THE DEVICE WORK 4HE ELECTRIC lELD ATTRACTS THE APPROPRIATELY CHARGED PARTICLES EITHER ELECTRONS OR hHOLES v TO FORM THE CONDUCTING CHANNEL THAT IN ESSENCE OPERATES THE SWITCH 7HEN THE VOLTAGE TO THE GATE IS TURNED OFF THE ELECTRIC lELD FORMED BY THE GATE COLLAPSES THE CHARGES mOW AWAY AND THE CHANNEL DISAPPEARS !NOTHER NAME FOR THE CHANNEL IS hSURFACE INVERSION LAYERv BECAUSE FOR OUR EXAMPLE THE PRESENCE OF ALL THE NEGATIVE CHARGES PULLED INTO THAT VERY THIN SURFACE REGION INVERTS THE RATIO OF HOLES TO ELECTRONS THERE MAJORITYMINORITY CHARGE CARRI ERS )N OTHER WORDS THE ELECTRONS HELD IN THE CHANNEL lLL THE P TYPE HOLES WITH PLENTY LEFT OVER TO MAKE THE CHANNEL N TYPE !S LONG AS THERE IS A LARGE ENOUGH VOLTAGE ON THE GATE THE CHANNEL REMAINS N TYPE AND CURRENT CAN mOW BETWEEN THE N TYPE SOURCE AND DRAIN BECAUSE THEY ARE NOW CONNECTED BY A CONTINUOUS PIECE OF N TYPE CONDUCTING MATERIAL 4HE WIDTH OF THE GATE LINE OR hSTRIPEv IS OFTEN CONSIDERED THE MOST IMPORTANT DIMENSION ON THE CHIP 4HAT DIMENSION IS THE DElNING ONE FOR A SPECIlC hTECHNOLOGY NODEv )N OTHER WORDS WHEN SOMEONE SAYS h NANOMETER TECHNOLOGY v THEY ARE REFERRING TO THE WIDTH OF THE GATE LINE 3OME CONFUSION DOES EXIST WITH THE
#HAPTER "UILDING THE 4RANSISTORS TERMINOLOGY BECAUSE OCCASIONALLY THE ACTUAL CHANNEL LENGTH A SMALLER DIMENSION IS BEING REFERENCED 4HIS ISSUE WILL BE EXPLAINED IN MORE DETAIL IN 3ECTION 4RANSISTOR PERFORMANCE IS CONSIDERED BY MANY TO BE THE DRIVING FORCE BEHIND ALL THE TECHNOLOGICAL DEVELOPMENT ASSOCIATED WITH COMPUTER CHIPS &ASTER SWITCHING SPEEDS MEANS FASTER COMPUTERS 7HAT ACCOUNTS FOR THE SPEED OF A TRANSISTOR 3EVERAL FACTORS ARE IMPORTANT IN THE SPEED OF OPERATION OF A TRANSISTOR 4HE CHANNEL LENGTH IS OFTEN THE lRST THING THAT COMES TO MIND 3INCE THE CHANNEL ELECTRICALLY CON NECTS THE SOURCE TO THE DRAIN THE SHORTER THE CHANNEL THE FASTER THE CHIP 4HE PRINCIPLE AT WORK HERE IS THAT A SHORT CHANNEL WILL FORM FASTER THAN A LONG ONE WHEN THE VOLTAGE IS APPLIED TO THE GATE )N ADDITION A SHORTER CHANNEL WILL HAVE LOWER RESISTANCE AN IMPORTANT CIRCUIT SPEED FACTOR /F COURSE THE CHANNEL CAN BECOME TOO SHORT AND THEN IT WILL NO LONGER BE ABLE TO PREVENT CURRENT FROM mOWING FROM SOURCE TO DRAIN WHEN THE GATE VOLTAGE IS TURNED OFF 4HE GATE STRIPE WAS ABOUT MICRONS WIDE IN EARLY CHIPS .OW IT IS LESS THAN MICRONS NM DOWN BY A FACTOR OF !NOTHER FACTOR THAT IS PUSHING THE LIMITS OF TECHNOLOGY IS THE THICKNESS OF THE GATE DIELECTRIC 2EDUCING THE ELECTRICAL RESISTANCE OF ALL PARTS OF THE TRANSISTOR AND ALL OF THE INTERCONNECTIONS ON THE CHIP TOO WILL INCREASE CHIP SPEED 2EDUCTION OF PARASITIC CAPACITANCES IN THE CIRCUIT IS A SPEED FACTOR THAT WILL BE EXPLAINED IN TWO UPCOMING SECTIONS ! 0ERSPECTIVE ON #HIP 3PEED .OT ALL CHIPS NEED TO BE STATE OF THE ART WITH VERY SMALL GATE DIMENSIONS AND VERY THIN GATE DIELECTRICS ,OWER PERFORMANCE TECHNOLOGIES ARE PERFECTLY ADEQUATE FOR MANY APPLICATIONS -AXIMUM PERFORMANCE IS REQUIRED FOR HIGH END COMPUTERS AND SERVERS ,OWER PERFORMANCE IS lNE FOR TELEPHONES LAPTOP COMPUTERS AND PORTABLE ELECTRONIC DEVICES THE ROUTINE hSLOWv LOGIC APPLICATIONS ,OWER SPEED MEANS LOWER POWER CONSUMPTION LONGER BATTERY LIFE AND COMPARATIVELY LOWER PRICE
3%#4)/.
4HIN &ILM &ORMATION 'ATE $IELECTRIC /XIDATION $ElNITION 4HE 'ATE $IELECTRIC IS A LAYER OF ELECTRICALLY INSULATING MATERIAL SAND WICHED BETWEEN THE GATE POLY AND THE SILICON SUBSTRATE 4O DATE IT HAS BEEN MADE ALMOST EXCLUSIVELY OF SILICON DIOXIDE 0URPOSE 4HE GATE DIELECTRIC INSULATES THE GATE ELECTRODE FROM THE SILICON SUBSTRATE $ISCUSSION 4HE GATE DIELECTRIC THAT IS CURRENTLY USED IN MANUFACTURING IS MADE OF THERMALLY GROWN SILICON DIOXIDE SILICA )T IS TYPICALLY GROWN IN AN 240 SYSTEM USING OXYGEN AND DIFFERS SOMEWHAT FROM THE THERMAL OXIDE DISCUSSED IN #HAPTER 3MALL AMOUNTS OF NI TROGEN ARE OFTEN INCORPORATED INTO THE lLM TO IMPROVE LONG TERM RELIABILITY AND REDUCE LEAKAGE CURRENTS 4HE GATE DIELECTRIC IS THE THINNEST lLM ON THE WAFER AND HAS THE MOST CRITICAL RE QUIREMENTS FOR COMPOSITION INTEGRITY AND THICKNESS 4HERMAL OXIDE IS AMORPHOUS 4HE THREE DIMENSIONAL STRUCTURE IS A RANDOM COMBINATION OF TETRAHEDRA AND TRIANGLES MADE OF SILICON DIOXIDE WITH EXTRA OXYGEN IONS JOINING THE SILICA POLYHEDRA 4HIS COMPLI CATED STRUCTURE IS EXPLAINED IN 'HANDHI SEE THE "IBLIOGRAPHY 4HE GATE OXIDE THICKNESS HAS BEEN SCALED DOWN OVER THE YEARS TO IMPROVE CHIP PERFORMANCE 7ITH A THINNER GATE OXIDE MORE CONDUCTING CHARGES ARE ATTRACTED INTO THE CHANNEL REDUCING ITS RESISTANCE AND SPEEDING UP THE CHIP /XIDE THICKNESSES IN THE REGION OF ª OR NM ARE CURRENTLY IN USE 4HESE lLMS ARE ONLY A FEW ATOMIC LAYERS THICK APPROACHING THE POINT WHERE EVEN SILICON DIOXIDE IS NO LONGER A GOOD ENOUGH INSULATOR AND TOO MUCH CURRENT CAN LEAK THROUGH BETWEEN THE GATE AND THE SUBSTRATE
#HAPTER "UILDING THE 4RANSISTORS $ElNITION K IS THE DIELECTRIC CONSTANT A DIMENSIONLESS QUANTITY THAT SERVES AS A WAY OF COMPARING ONE OF THE INSULATING CHARACTERISTICS OF VARIOUS MATERIALS K IS DElNED AS THE AMOUNT THAT THE CAPACITANCE INCREASES COMPARED TO VACUUM IN A CAPACITOR WHEN THAT MATERIAL IS USED AS THE DIELECTRIC )T MUST BE DETERMINED EXPERIMEN TALLY FOR EACH MATERIAL "Y DElNITION VACUUM SERVES AS THE REFERENCE 4HE VALUE OF K FOR VACUUM IS UNITY THE LOWEST POSSIBLE VALUE FOR K K FOR AIR VARIES ONLY SLIGHTLY FROM VACUUM $ElNITION (IGH K 'ATE $IELECTRICS INCREASE THE AMOUNT OF CHARGE THAT WILL ACCU MULATE IN THE CHANNEL FOR A GIVEN DIELECTRIC THICKNESS AND APPLIED GATE VOLTAGE LOWERING THE TRANSISTORS hONv RESISTANCE AND SPEEDING UP THE CHIP (IGH K MATERIALS IMPROVE ON SILICON DIOXIDE BY ALLOWING THE USE OF A THICKER lLM WITHOUT CHANGING THE PERFORMANCE OF THE TRANSISTOR 4HICKER lLMS WILL REDUCE OR ELIMINATE LEAKAGE CURRENTS THROUGH THE DIELECTRIC !LTHOUGH SOME CHIPS WILL TOLER ATE A MODERATE LEAKAGE CURRENT IT INCREASES THE POWER CONSUMPTION SO IT IS ALWAYS UNDESIRABLE 4O ILLUSTRATE SILICON DIOXIDE HAS A K OF ABOUT )F A SUITABLE REPLACEMENT MATERIAL COULD BE FOUND WITH A K OF THE SAME ELECTRICAL PERFORMANCE WOULD BE SEEN IN THE CHIP BUT THE GATE DIELECTRIC COULD BE TWICE A THICK 4HAT WOULD RESULT IN REDUCED POWER CONSUMPTION BECAUSE OF REDUCED LEAKAGE CURRENT
&IGURE 'ATE $IELECTRIC ON 7AFER
4HIN &ILM &ORMATION /VERVIEW OF (IGH K $IELECTRICS 3I/ K
(IGH K $IELECTRIC K
$OUBLING THE K ALLOWS THE THICKNESS OF THE DIELECTRIC TO BE DOUBLED 4HE TRANSISTOR PERFORMS THE SAME BUT WITH LESS CURRENT LEAKAGE BETWEEN THE GATE AND THE SILICON SUBSTRATE
&IGURE (IGH K $IELECTRIC VS 3ILICON $IOXIDE 4HERE ARE MANY HIGH K MATERIALS WITH SOME OF THE REQUIRED PROPERTIES TO BE POTENTIAL CANDIDATES TO REPLACE SILICON DIOXIDE AS A GATE DIELECTRIC 4HESE MATERIALS ARE MOSTLY OXIDES OR SILICATES OF CERTAIN METALS 5NFORTUNATELY MOST OF THEM HAVE A SERIOUS FAILING /NE COMMON PROBLEM IS THAT SOME WILL REACT WITH THE SILICON WAFER OR POLYSILICON GATE TO FORM A LAYER OF SILICON DIOXIDE AT THE INTERFACES THAT EXCESSIVELY LOWERS THE OVERALL K OF THE lLM !NOTHER FREQUENT PROBLEM CONCERNS THE ELECTRICAL CHARGE THAT IS USUALLY FORMED AT THE WAFERDIELECTRIC INTERFACE ! LAYER OF CHARGE HERE IS EQUIVALENT TO HAVING A PERMANENT BUILT IN VOLTAGE ON THE GATE (IGH LEVELS OF CHARGE WHICH OCCUR WITH SOME DIELECTRICS AFFECT THE THRESHOLD VOLTAGE OF A TRANSISTOR VERY STRONGLY BUT LOW LEVELS OF CHARGE CAN BE TOLERATED 4HIS SURFACE STATE CHARGE AS IT IS CALLED RESULTS FROM THE DISCONTINUITY IN THE CHEMICAL BONDING AT THE INTERFACE BETWEEN THE SILICON AND VARIOUS DIELECTRICS !T THE SILICONSILICON DIOXIDE INTERFACE A RELATIVELY SMALL AMOUNT OF POSITIVE CHARGE IS ALWAYS FORMED 7HEN -/3 TECHNOLOGY WAS lRST INTRODUCED A GREAT DEAL OF WORK WAS DONE TO DEVELOP A PROCESS THAT WOULD CONSISTENTLY PRODUCE THE SAME LOW LEVEL OF CHARGE SO THAT THE DEVICE ENGINEERS COULD CORRECT FOR THAT CHARACTERISTIC 4HIS WELL UNDERSTOOD AND WELL BEHAVED SILICONOXIDE INTERFACE IS NOT PROVING EASY TO DUPLICATE WITH HIGH K lLMS (IGH K DIELECTRICS THAT HAVE SHOWN PROMISE INCLUDE THE OXIDES AND SILICATES OF HAFNIUM AND ZIRCONIUM BUT MANY OTHER MATERIALS ARE BEING INVESTIGATED AND MUCH WORK WILL BE NEEDED TO ACCOMPLISH THIS MAJOR CHANGE IN THE TECHNOLOGY
#HAPTER "UILDING THE 4RANSISTORS
0OLYCRYSTALLINE 3ILICON 0OLY $EPOSITION $ElNITION 0OLYCRYSTALLINE 3ILICON IS A FORM OF SILICON THAT IS DEPOSITED ON THE WAFER 5NLIKE THE WAFER AND EPITAXIAL SILICON WHICH ARE SINGLE CRYSTAL FORMS OF SILICON THE POLY IS MADE UP OF GRAINS %ACH GRAIN IS A CRYSTALLITE A TINY CRYSTAL OF SILICON
4HE POLY lLM THICKNESS IS COMMONLY AROUND !NGSTROMS THICK )T IS DEPOS ITED USING ,0#6$ TECHNOLOGY
!N IMPORTANT THING TO REMEMBER ABOUT POLY IS THAT IT WILL BE DOPED TO MAKE IT A RELATIVELY GOOD CONDUCTOR OF ELECTRICITY 0OLYCRYSTALLINE 3ILICON &ILM #HARACTERISTICS v 3TANDARD ,0#6$ DEPOSITION AT ABOUT # v 'RAINS BECOME SMALLER AS DEPOSITION TEMPERATURE IS DECREASED v !T SOME LOWER TEMPERATURE AMORPHOUS SILICON IS FORMED NO CRYSTAL STRUCTURE 2EACTIVE GASES
4HERMAL #6$
,AYER DEPOSITS ON HEATED WAFER
6ACUUM PUMP
! PROCESS USING CHEMICAL REACTIONS IN GASES TO DEPOSIT LAYERS OF SOLID MATERIAL
%XAMPLE REACTION 3I( GAS m 3I SOLID ( GAS &IGURE #HEMICAL 6APOR $EPOSITION
4HIN &ILM &ORMATION
&IGURE 0OLY $EPOSITION .OTES ON 'ATE %LECTRODE -ATERIALS 0OLYCRYSTALLINE SILICON IS PREFERRED FOR THE GATE MATERIAL FOR SEVERAL REASONS )T WILL WITHSTAND HIGH TEMPERATURES SEEN IN SUCCEEDING PROCESSING STEPS )N ADDITION THE POLYGATE OXIDE INTERFACE IS WELL UNDERSTOOD AND CONVENTIONAL FAB PROCESSES PRODUCE CONSISTENT RESULTS 4HE POLY IS DOPED HEAVILY FOR LOW RESISTANCE TO CURRENT mOW $OPED POLY IS lNE BY ITSELF AS THE GATE MATERIAL FOR LOWER PERFORMANCE CHIPS (IGH PERFOR MANCE CHIPS USE HEAVILY DOPED POLY WITH SILICIDE ON TOP 4HIS APPLICATION IS DISCUSSED IN 3ECTION 4HE lRST GATES WERE MADE OF A METAL USUALLY ALUMINUM BUT MOLYBDENUM WAS USED A LITTLE TOO 3ECTION HAS MORE TO SAY ABOUT THIS TECHNOLOGY 0OLY REPLACED METAL FOR REASONS MENTIONED ABOVE (OWEVER METAL GATES MAY RETURN TO THE INDUSTRY SOON FOR USE IN VERY HIGH SPEED CHIPS $EVELOPMENT WORK IS UNDERWAY
#HAPTER "UILDING THE 4RANSISTORS
.ITRIDE #AP $EPOSITION 4HE NITRIDE CAP IS STANDARD 0%#6$ NITRIDE THE SAME HARD MASK PROCESS AS FOUND IN #HAPTER .ITRIDE #AP
0OLYSILICON
'ATE /XIDE
&IGURE #OMPLETED 'ATE &ILM 3TACK
3%#4)/.
0OLY 'ATE &ORMATION 0OLY 'ATE &ORMATION 0ROCESS &LOW 0HOTORESIST 0ATTERNING
0LASMA %TCH A 2ESIST 4RIM B .ITRIDE (ARD -ASK %TCH C 0OLY %TCH
0HOTORESIST 0ATTERNING 4HE lRST STEP IN THE POLY GATE FORMATION PROCESS IS RESIST PATTERNING AT PHOTO 3EE #HAPTER FOR A REVIEW OF PHOTOLITHOGRAPHY 0USHING THE LIMITS OF TECHNOL OGY IS VIVIDLY ILLUSTRATED HERE 0RODUCING TODAYS FAST CHIPS WITH TINY GEOMETRIES REQUIRES GOING BEYOND THE CURRENT CAPABILITIES OF PHOTOLITHOGRAPHY IN MANUFAC TURING 4HE DETAILS ARE DISCUSSED IN THE NEXT SECTION UNDER RESIST TRIMMING
)NITIAL 7IDTH $ESIRED 7IDTH
0OLYSILICON
3ILICON 7AFER
&IGURE 'ATE &ILM 3TACK WITH 0ATTERNED 2ESIST
#HAPTER "UILDING THE 4RANSISTORS
0LASMA %TCH $ElNITION 2ESIST 4RIMMING IS THE PROCESS OF USING AN OXYGEN PLASMA TO ETCH THE PATTERNED RESIST AND THEREBY REDUCE THE SIZE OF THE PATTERN FEATURES 0URPOSE )N ORDER TO MAKE SHORTER CHANNEL LENGTHS AND THEREFORE FASTER PARTS THE POLY LINEWIDTH DIMENSION MUST BE REDUCED $ISCUSSION 2ESIST TRIMMING HAS BEEN USED FOR MANY YEARS AND IS STILL GOING STRONG IN PRODUCTION TODAY .EW STEPPER TECHNOLOGY CONTINUES TO INNOVATE ALWAYS IMPROVING THE ABILITY TO PATTERN SMALLER FEATURES "UT ONRUSHING DEMAND FOR SHRINKING DIMENSIONS AND FASTER CHIPS REQUIRES A FULL ENGINEERING BAG OF TRICKS 2ESIST TRIM IS AN IMPORTANT ONE (ERE IS A SIMPLE EXAMPLE OF THE NEED FOR RESIST TRIMMING -ANY STEPPERS USE A LIGHT WAVELENGTH OF NANOMETERS ¾ n M OR BILLIONTHS OF A METER LONG 4HE BEST LENS SYSTEMS CAN THEORETICALLY RESOLVE A FEATURE THAT IS ONE HALF OF A WAVELENGTH IN SIZE OR IN THIS CASE NM &OR REFERENCE THAT MAY ALSO BE EXPRESSED AS MICRONS 4HAT IS THE ABSOLUTE LIMIT OF THE FEATURE SIZE THAT CAN BE PRODUCED IN THE RESIST .EW SCANNER AND STEPPER TECHNOLOGY HAS FOUND SOME OTHER CLEVER WAYS OF PUSHING THIS BOUNDARY BUT FOR THE SAKE OF THIS SIMPLIlED EXAMPLE THOSE INNOVATIONS WILL BE OVERLOOKED (OW CAN A GATE POLY LINE OF NM BE MADE THEN )T IS DONE BY FOOLING -OTHER .ATURE AND USING THE ETCHER TO ETCH AWAY THE RESIST LINES UNTIL THEY MATCH THE DESIRED DIMENSION /F COURSE THE RESIST IS BADLY ERODED BY THE TRIMMING SO IT CANNOT SERVE AS A PROPER MASK FOR ETCHING THE POLY 4HE ETCH MASKING PROBLEM IS SOLVED IN THE SAME WAY THAT IT WAS FOR 34) DISCUSSED IN #HAPTER WITH THE USE OF A NITRIDE HARD MASK 5PDATE ON 3TEPPER 4ECHNOLOGY .EW STEPPER TECHNOLOGY USING THE SHORTER WAVELENGTH OF NM IS INCREAS INGLY AVAILABLE TODAY FOR STATE OF THE ART DEVICES AT THE NM NODE 3TEPPERS USING NM TECHNOLOGY ARE SLOWLY ENTERING PRODUCTION 4HERE HAVE BEEN LARGE DIFlCULTIES IN PUSHING THE TECHNOLOGY TOWARD THE 8 RAY WAVELENGTHS OF LIGHT MOSTLY AS REGARDS THE COMPLEXITY OF MAKING PRODUCTION WORTHY PHOTORESIST ANDOR LENS SYSTEMS WITH SUFlCIENT CAPABILITIES 'REAT STRIDES ARE BEING MADE IN OTHER WAYS 3TEPPERS EMPLOYING PHASE SHIFT MASKS AND THE NEW IMMERSION TECHNOLOGY WHERE THE STEPPER OBJECTIVE LENS IS IMMERSED IN LIQUID THAT CONTACTS THE WAFER SURFACE HAVE GREATLY IMPROVED PHOTOS CAPABILITIES .EXT GENERATION LITHOGRAPHY .', IS A PROGRAM TO DEVELOP A LITHOGRAPHY TECHNOLOGY UTILIZING ELECTRON BEAMS E BEAM
0OLY 'ATE &ORMATION %VEN WITH ALL OF THIS INCREDIBLE TECHNOLOGICAL PROGRESS RESIST TRIMMING IS GOING TO BE WITH US FOR A WHILE
.ITRIDE
0OLYSILICON
3ILICON 7AFER
&IGURE 2ESIST 4RIMMING 3EQUENCE
4HE RESIST TRIMMING IS DONE IN A PLASMA ETCHER MOST OFTEN USING AN OXYGEN PLASMA 4HE OXYGEN PLASMA OXIDIZES BURNS THE RESIST PRIMARILY FORMING THE VOLATILE PRODUCTS CARBON DIOXIDE AND WATER VAPOR 4HE WAFER ENTERS THE PLASMA ETCHER AND THE RESIST IS TRIMMED .EXT THE NITRIDE HARD MASK IS ETCHED FOLLOWED BY THE POLY LINE )T IS ALL DONE IN THE SAME CHAMBER
.ITRIDE (ARD -ASK 0OLYSILICON
3ILICON 7AFER
&IGURE .ITRIDE %TCHED TO &ORM (ARD -ASK
#HAPTER "UILDING THE 4RANSISTORS MOST OF THE TIME )N OTHER CASES A CLUSTER TOOL MAY BE EMPLOYED #LUSTER TOOLS ARE MACHINES EQUIPPED WITH MULTIPLE PROCESSING STATIONS SUCH AS ETCH REACTORS AND DEPO SITION CHAMBERS THAT ALLOW THE WAFERS TO GO THROUGH MULTIPLE PROCESSING STEPS WITHOUT BREAKING VACUUM +EEPING THE WAFERS UNDER VACUUM ELIMINATES MOST SOURCES OF PAR TICULATE AND ATMOSPHERIC CONTAMINATION 3ILICON NITRIDE IS ETCHED USING THE ETCH CHEMISTRY DISCUSSED IN #HAPTER 4HE NITRIDE IS QUITE THIN SO THE TRIMMED RESIST MASK IS SUFlCIENT TO MASK THE ETCH 4HE POLY ETCH IS PERFORMED USING THE CHLORINEBROMINE ETCH CHEMISTRY DISCUSSED IN #HAPTER 4HIS IS THE MOST CRITICAL ETCH IN THE ENTIRE PROCESS 4WO OF THE MOST IMPORTANT REQUIREMENTS OF THE ETCH ARE v %TCH STOP ON THIN GATE OXIDE v 6ERTICAL SIDEWALLS ON THE POLY LINES 4HE GATE OXIDE IS SO THIN THAT GREAT CARE MUST BE EXERCISED TO NOT BREAK THROUGH IT 4HE PRESERVATION OF THE OXIDE lLM ON EITHER SIDE OF THE GATE IS FOR THE PROTECTION OF THE SILICON WAFER SURFACE DIRECTLY UNDERNEATH 3INCE THE SOURCE AND DRAIN WILL BE FORMED THERE THE SILICON SURFACE SHOULD NOT BE DAMAGED 4HE POLY FEATURES SHOULD HAVE VERTICAL SIDEWALLS TO BE SURE OF PRODUCING THE NARROWEST USEFUL POLY LINE 4HE POLY IS A CONDUCTOR )T MUST HAVE A SUFlCIENTLY LARGE CROSS SECTIONAL AREA SO THAT IT MINIMALLY RESISTS CURRENT mOW THROUGH IT (OWEVER IT MUST BE NARROW SO THAT IT FORMS THE SHORTEST POSSIBLE CHANNEL 3O A WELL SHAPED RECTANGULAR CROSS SECTION IS DESIRABLE !NY REMAINING RESIST IS STRIPPED OFF AFTER POLY ETCH
&IGURE #OMPLETED 0OLY 'ATE %TCH
3%#4)/.
3OURCE$RAIN &ORMATION 0ROCESS &LOW FOR ,IGHTLY $OPED $RAIN ,$$ &ORMATION 3HALLOW )MPLANT 3PACER &ORMATION A $EPOSIT SILICON NITRIDE B %TCH SILICON NITRIDE (IGH $OSE )MPLANT !NNEAL
)NTRODUCTION $ElNITION 4HE 3OURCE AND $RAIN ARE THE NAMES OF THE DOPED REGIONS AT EITHER END OF THE CHANNEL 4HEY ARE CREATED BY APPROPRIATELY DOPING THE SILICON SUBSTRATE IN THOSE REGIONS TO MAKE IT HIGHLY CONDUCTIVE IN ACCORDANCE WITH THE DESIGN SPECIl CATIONS OF THE TRANSISTOR )T IS ALWAYS NECESSARY TO ADD EXTRA DOPANT TO CHANGE THE DOPANT PROlLE OF THE DESIRED REGION FROM P TYPE TO N TYPE OR VICE VERSA &IGURES AND IN THIS CHAPTER SHOW THE SOURCE AND DRAIN 0URPOSE 4HE SOURCE AND DRAIN ARE TWO OF THE ELECTRODES IN THE TRANSISTOR %LECTRICAL CONNECTIONS ARE MADE TO THESE ELECTRODES AS WELL AS TO THE GATE AND SUBSTRATE MAKING THE TRANSISTOR A PART OF THE CIRCUITRY OF THE CHIP !S DISCUSSED EARLIER IN THE CHAPTER CURRENT mOWS BETWEEN THE SOURCE AND DRAIN WHEN A SUITABLE VOLTAGE IS APPLIED TO THE GATE
#HAPTER "UILDING THE 4RANSISTORS $ElNITION ! ,IGHTLY $OPED $RAIN ,$$ HAS SPECIALLY SHAPED DOPED REGIONS FORM ING THE SOURCE AND THE DRAIN THAT OPTIMIZE THE PERFORMANCE AND RELIABILITY OF A CHIP )N FACT BOTH THE SOURCE AND DRAIN HAVE A LIGHTLY DOPED REGION IN SPITE OF THE NAME 0URPOSE 4HE ,$$ HELPS TO SOLVE A RELIABILITY PROBLEM THAT WAS ENCOUNTERED AS THE CHANNEL LENGTH BECAME SHORTER WITH THE CONTINUED SHRINKING OF THE CHIP $ISCUSSION 4HE ,$$ IS A TWO IMPLANT PROCESS THAT POSITIONS LIGHTLY DOPED AREAS AT EITHER END OF THE CHANNEL 4HE MORE HEAVILY DOPED AREAS ARE NEEDED TO MINIMIZE THE RESISTANCE BETWEEN THE ENDS OF THE CHANNEL AND THE SOURCE AND DRAIN CONTACTS AND ALSO TO GIVE LOW CONTACT RESISTANCE TO THE METAL CONNECTIONS 4HE LIGHT DOPING AT EITHER END OF THE CHANNEL REDUCES THE ACCELERATION OF ELECTRONS OR HOLES BEING DRAWN INTO THE DRAIN FROM THE END OF THE CHANNEL "EFORE THE ADOPTION OF THIS INNOVATION SOME ELECTRONS WERE ACCELERATED TO HIGH ENOUGH VELOCITIES THAT THEY WOULD DAMAGE THE GATE DIELECTRIC 4HIS EFFECT WAS KNOWN AS THE hHOT ELECTRONv PROBLEM 4HE PROBLEM IS MUCH LESS SERIOUS IN THE CASE OF HOLES IN P CHANNEL TRANSISTORS $ElNITION ! 3ELF !LIGNED 'ATE IS THE NAME OF THE SOURCE DRAIN AND GATE ELECTRODES THAT WERE FORMED USING THE 3ELF !LIGNMENT 0ROCESS 4HE SELF ALIGNMENT PROCESS CREATES THE SOURCE AND DRAIN ON EITHER SIDE OF THE GATE IN PRECISELY THE CORRECT POSITIONS +EY 0OINT 4HE TRICK TO MAKING A SELF ALIGNED GATE IS TO ETCH THE POLY LINE BEFORE IMPLANTING THE SOURCEDRAIN 4HE POLY LINE ACTS AS A PERFECTLY PLACED IMPLANT MASK SO THE DOPANT GOES EXACTLY WHERE IT SHOULD 0URPOSE 4HE SELF ALIGNED PROCESS PUTS THE THREE COMPONENTS IN EXACTLY THE RIGHT PLACE RELATIVE TO EACH OTHER 4HE SPEED AND RELIABILITY OF THE CHIP ARE MAXIMIZED IN THIS WAY $ISCUSSION 3ELF ALIGNED GATE IS SOMETHING OF A MISNOMER ! MORE CORRECT LABEL MIGHT BE hSELF ALIGNED SOURCEDRAIN v SINCE THE FUNCTION OF THE PROCESS IS TO ALIGN THE SOURCE AND DRAIN NOT THE GATE 4HE NAME SEEMS TO BE A THROWBACK TO THE PROBLEM OF ALIGNING THE GATE EARLY IN THE INDUSTRYS HISTORY 4HE POSITIONING OF THE SOURCE DRAIN AND GATE ELECTRODES IS OBVIOUSLY VERY CRITICAL )N EARLY ALUMINUM GATE TECHNOLOGY THE GATES WERE ADDED AFTER THE SOURCES AND DRAINS
3OURCE$RAIN &ORMATION WERE FORMED 4HE ALIGNMENT WAS DONE IN THE ALUMINUM PATTERNING STEP AND SOME AMOUNT OF MISALIGNMENT WAS EXPECTED !S COMPENSATION WIDE GATE STRIPES WERE USED TO ENSURE THAT THE WHOLE SOURCE TO DRAIN REGION WAS COVERED (OWEVER THE EXTRA OVER LAP ON ONE SIDE OR THE OTHER HURT THE PERFORMANCE OF THE CHIP BY SLOWING IT DOWN
3HALLOW )MPLANT 4HE WAFERS lRST GO TO ION IMPLANTATION FOR THE SHALLOW IMPLANT SHOWN IN &IGURE &OR TECHNOLOGIES WITH GATES IN THE REGION OF NM THE DEPTH OF THE SHALLOW IMPLANT IS ABOUT NM OR LESS INTO THE SILICON SUBSTRATE WHICH MAY ALSO BE EXPRESSED AS !NGSTROMS TO ALLOW US TO COMPARE TO AN ADJACENT STRUCTURE 4HIS IMPLANT LAYER IS ABOUT OF THE THICKNESS OF THE GATE POLY WHICH IS AROUND !NGSTROMS THICK "UT IT IS OVER TEN TIMES THICKER THAN THE GATE DIELECTRIC AT n !NGSTROMS 4HE POSITION OF THE DOPANT SPECIES IS VERY WELL DElNED AT THIS POINT 4HE ANNEAL STEP LATER IN THE PROCESS CHANGES THE SHAPE AND SLIGHTLY EXPANDS THE BOUNDARIES OF THE DOPANT
,OW ENERGY IMPLANTS
&IGURE 3HALLOW )MPLANT 3ELF !LIGNED 'ATE ! THIN SCREENING OXIDE ON THE SILICON OMITTED FOR SIMPLICITY
3PACER &ORMATION $ElNITION ! 3PACER IS AN IMPLANT MASK 0URPOSE 4HE SPACERS COVER NARROW REGIONS ON EITHER SIDE OF THE POLY LINE BLOCK ING THE HIGH DOSE IMPLANT THAT FORMS THE BULK OF THE SOURCE AND DRAIN 4HE SMALL SHALLOW IMPLANT REGIONS THAT ARE PROTECTED BY THE SPACERS CALLED THE SOURCEDRAIN EXTENSIONS CONTACT THE ENDS OF THE CHANNEL
#HAPTER "UILDING THE 4RANSISTORS 4HIS CLEVER DEVICE IS A SIMPLE SOLUTION TO THE NEED FOR ,$$S .ITRIDE OR OXIDE WILL BOTH WORK AS THE SPACERS BUT NITRIDE IS MOST COMMON )N EITHER CASE THE SPACERS ARE PERMANENTLY LEFT IN PLACE
.ITRIDE $EPOSITION
&IGURE #ONFORMAL .ITRIDE &ILM
! SILICON NITRIDE lLM IS DEPOSITED NEXT 4HE NITRIDE LAYER FOLLOWS THE CONTOURS OF THE WAFER SURFACE AND IS ABOUT THE SAME THICKNESS AS THE POLY !S SHOWN IN &IGURE THE CONFORMAL lLM WILL BE TWICE AS THICK AT THE ABRUPT STEPS FOUND AT THE EDGES OF THE POLY LINES 4HIS THICKNESS VARIATION OCCURS AT JUST THE RIGHT SPOT AND IS THE KEY INGREDIENT IN MAKING THE SPACERS !NISOTROPIC ETCH BACK FORMS SPACERS
.ITRIDE ETCHED AWAY 3PACERS REMAIN
&IGURE 3PACER %TCH
4HE SPACER ETCH IS A RATHER SIMPLE ONE !FTER THE NITRIDE IS DEPOSITED THE WAFER CAN IMMEDIATELY GO TO THE ETCHER 4HERE IS NO PATTERNING INVOLVED 4HE ONE IMPORTANT FAC TOR IN SPACER ETCH IS THE UNIFORMITY OF ETCH 4HE lLM MUST BE REMOVED FROM ALL PARTS OF THE WAFER AT EXACTLY THE SAME RATE SO THAT ALL TRANSISTORS HAVE THE SAME SIZE AND SHAPE OF SPACERS
3OURCE$RAIN &ORMATION
(IGH $OSE )MPLANT 4HE HIGH DOSE IMPLANT FOLLOWS THE SPACER FORMATION 4HIS IMPLANT IS NECESSARY TO CREATE A LOW RESISTANCE PATH BETWEEN THE ENDS OF THE CHANNEL AND THE SOURCE AND DRAIN CONTACTS AND TO ASSIST IN FORMING LOW RESISTANCE CONTACTS FOR CONNECTIONS THAT WILL BE MADE TO THE SOURCE AND DRAIN )N !PPENDIX ! SOME OF THE DOPING CHARACTERISTICS OF SILICON ARE DISCUSSED 2ECALL THAT WITH DOPANT CONCENTRATIONS IN THE REGION OF ONE PART PER MILLION THAT THE CONDUC TIVITY OF SILICON ROSE SEVERAL ORDERS OF MAGNITUDE RELATIVE TO INTRINSIC SILICON 4YPICALLY MAXIMUM CONDUCTIVITY IS NEEDED FOR THE SOURCE AND DRAIN SO HIGH DOPING CONCENTRA TIONS WILL BE USED !RSENIC IS THE PREFERRED DOPANT FOR N TYPE SOURCEDRAIN BECAUSE IT IS A SLOWER DIF FUSER IN SILICON THAN PHOSPHOROUS "ORON IS THE ONLY VIABLE DOPANT CHOICE FOR MAKING P TYPE MATERIAL UNFORTUNATELY IT DIFFUSES JUST AS FAST AS PHOSPHORUS SO PROCESSING ADJUSTMENTS MUST BE MADE
3PACERS PROTECT THESE REGIONS 3LIGHTLY HIGHER ENERGY DEPTH STILL MICRON
&IGURE (IGH $OSE )MPLANT
!NNEAL $ElNITION !NNEAL IS A HIGH TEMPERATURE TREATMENT THAT IS USED IN THIS CASE TO REPAIR SILICON CRYSTAL DAMAGE ACTIVATE DOPANTS AND DISTRIBUTE DOPANTS WITHIN THE SILICON !NNEALING IS COMMONLY DONE IN A RAPID THERMAL PROCESSOR 240 4HE PROCESS IS CALLED A SPIKE ANNEAL BECAUSE THE WAFER IS NOT HELD AT THE HIGH TEMPERATURE BUT RATHER
#HAPTER "UILDING THE 4RANSISTORS HEATED TO A PEAK AND THEN QUICKLY COOLED 4HE TEMPERATURE RAMPING RATE IS ONE OF THE CRITICAL PROCESS PARAMETERS 4HE PEAK TEMPERATURE MAY EXCEED # "EFORE ANNEALING THE DOPANTS ARE ELECTRICALLY INACTIVE $URING IMPLANT THE SILICON CRYSTAL LATTICE IS BROKEN UP AND THE DOPANTS AND SILICON ATOMS ARE RANDOMLY ORDERED 4HE ANNEAL RECONSTRUCTS THE CRYSTAL WITH DOPANT ATOMS SUBSTITUTING FOR SOME OF THE SILICON ATOMS IN THE LATTICE /NCE THIS ORDERLY STRUCTURE IS PRODUCED THE ELECTRONS OR HOLES ARE RELEASED FROM THE DOPANT ATOMS AND ARE ABLE TO MOVE INDEPENDENTLY WITHIN THE SOLID .OW THE DOPANTS ARE SAID TO BE ACTIVATED !S SHOWN IN &IGURE THE DOPANTS MOVE SOMEWHAT FROM THEIR ORIGINAL POSI TIONS CREATING A CHANGED DOPANT PROlLE 4HIS NATURAL DIFFUSION IS A WELL UNDERSTOOD PHENOMENON AND MUST BE CAREFULLY CONTROLLED )T IS A GOOD WAY TO SHORTEN THE CHANNEL TO A SMALL DEGREE $OPANT ATOMS DRIVEN IN SLIGHTLY IN ALL DIRECTIONS
,IGHTLY DOPED 3$ EXTENSIONS JUST UNDER EDGES OF GATE
&IGURE 240 3OURCE$RAIN !NNEAL $UAL $OPED 0OLY %ARLY IN THE HISTORY OF THE INDUSTRY THE GATE POLY WAS DOPED HEAVILY N TYPE FOR BOTH N CHANNEL AND P CHANNEL TRANSISTORS 4HE THINKING AT THE TIME WAS THAT THE HIGHER CONDUCTIVITY OF THE N TYPE VERSUS P TYPE MATERIAL WOULD IMPROVE THE SPEED OF THE CHIP .OW IN HIGH PERFORMANCE CHIPS N CHANNEL GATES ARE N DOPED AND P CHANNEL GATES ARE P DOPED )N #-/3 TECHNOLOGY THE N AND P TYPE TRANSISTORS WORK IN PAIRS CALLED COMPLEMENTARY PAIRS "ECAUSE OF THE EFFECT ON THE TRANSISTORS THRESHOLD VOLTAGE A 0-/3 TRANSISTOR WORKS BETTER IF THE GATE IS P DOPED 4HE "IBLIOGRAPHY CONTAINS SOME SUGGESTIONS FOR FURTHER READING ON THE FUNCTIONING OF SEMICONDUCTOR DEVICES
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3ALICIDE &ORMATION $ElNITION ! 3ILICIDE IS A CHEMICAL COMPOUND MADE OF SILICON AND A METAL 0URPOSE 3ILICIDES HAVE BEEN USED FOR MANY YEARS BECAUSE THEY IMPROVE THE CONDUC TIVITY OF THE GATE ELECTRODE AND REDUCE THE CONTACT RESISTANCE SPEEDING UP THE CHIP $ElNITION 0OLYCIDE IS THE NAME OF A STACK OF TWO lLMS SILICIDE ON POLYSILICON $ISCUSSION 4HE USE OF THE POLYCIDE lLM STACK GIVES THE BEST OF BOTH WORLDS 4HE POLYGATE OXIDE INTERFACE IS WELL UNDERSTOOD AND ROBUST 4HE POLY IS EASY TO PROCESS AND TOLERATES HIGH TEMPERATURES "UT THE POLY EVEN HEAVILY DOPED IS NOT AN EXCEPTIONALLY GOOD CONDUC TOR -ANY SILICIDES HAVE RESISTIVITIES THAT ARE MUCH LOWER THAN DOPED POLY THEIR USE WILL SIGNIlCANTLY INCREASE CHIP SPEED !ND THE SILICIDE WILL TOLERATE HIGH TEMPERATURES ENCOUNTERED IN PROCESSING TOO $ElNITION 3ALICIDE IS THE SHORT NAME FOR SELF ALIGNED SILICIDE )N THIS PROCESS THE SILICIDE MATERIAL ONLY FORMS IN EXACTLY THE RIGHT PLACES IN THE TRANSISTORS $ElNITION 3PUTTERING A COMMON TYPE OF 0HYSICAL 6APOR $EPOSITION 06$ IS THE PROCESS OF PHYSICALLY BOMBARDING A TARGET SOURCE WITH ARGON IONS WHICH KNOCK OFF ATOMS FROM THE TARGET SOME OF WHICH lND THEIR WAY TO THE WAFER AND STICK TO IT
#HAPTER "UILDING THE 4RANSISTORS !RGON
-ETAL ATOMS DEPOSIT ON WAFER
!RGON IONS STRIKE COBALT TARGET EJECTING ATOMS
6ACUUM PUMP (IGH VOLTAGE ? POWER SUPPLY
&IGURE 3PUTTERING (ISTORICAL .OTES ON 0OLYCIDE &OR MANY YEARS THE RESISTANCES OF POLY GATES AND INTERCONNECTIONS WAS RE DUCED BY FORMING A LAYER OF A SILICIDE ON THE POLY BEFORE THE GATE MASK WAS PATTERNED )N THESE SO CALLED POLYCIDE LAYERS THE VERY LOW RESISTANCE SILICIDE ON THE POLY BRINGS THE RESISTANCES DOWN TO MUCH LOWER LEVELS THAN IS POSSIBLE WITH POLY ALONE 4HE TUNGSTEN OR TITANIUM SILICIDES WHICH WERE COMMONLY USED CAN BE FORMED BY lRST DEPOSITING A THIN lLM OF METAL ON THE POLY 4HEN IN A HIGH TEMPERATURE STEP REACTION BETWEEN THE METAL AND SOME OF THE POLY PRODUCES THE SILICIDE LAYER -ORE COMMONLY HOWEVER SILICIDE lLMS HAVE BEEN DEPOSITED OVER THE POLY USING #6$ PROCESSES )N CURRENT HIGH PERFORMANCE CHIPS SILICIDE LAYERS ARE USED ON THE SOURCES AND DRAINS OF THE TRANSISTORS AS WELL AS ON THE GATES )MPROVED ELECTRICAL CONDUCTION IN THE lLM IS A MAJOR BENElT !NOTHER SIGNIlCANT IMPROVEMENT IS THE REDUCTION IN CONTACT RESISTANCE 4YPICALLY COBALT OR NICKEL SILICIDES ARE NOW PREFERRED AND ARE NOT FORMED UNTIL AFTER THE SOURCES AND DRAINS HAVE BEEN IMPLANTED
3ALICIDE &ORMATION
3PUTTER #OBALT #OBALT IS A WIDELY USED METAL IN CURRENT SILICIDATION PROCESSES .OTICE THAT THE SPUTTERED COBALT COVERS THE WHOLE WAFER BUT THE ONLY PLACES THAT SILICIDE WILL FORM ARE THE EXPOSED SILICON SOURCEDRAINGATE AREAS 4HE SILICIDE WILL NOT FORM ON THE OXIDE OR NITRIDE 4HE SILICIDE IS TRULY hSELF ALIGNEDv #OBALT LAYER
&IGURE #OBALT 3PUTTERED ON 4RANSISTOR
240 2EACTION &ORMING 3ILICIDE 4HE SILICIDE WILL FORM WHEN THE COBALT REACTS WITH THE EXPOSED SILICON !LL THAT NEED BE DONE IS TO RAISE THE TEMPERATURE OF THE WAFER TO THE REACTION POINT AND LEAVE IT THERE LONG ENOUGH FOR THE REACTION TO HAPPEN (OWEVER HIGH TEMPERATURE IS A RISK TO THE STRUCTURES ALREADY COMPLETED ON THE WAFER .O SILICIDE FORMED ON NITRIDE AND OXIDE
&IGURE 3ILICIDE &ORMED ON 3OURCE $RAIN AND 'ATE
4HE RAPID THERMAL PROCESSOR COMES TO THE RESCUE 4HE VALUE OF THE 240 IS ESPE CIALLY IMPORTANT AT THIS TIME BECAUSE THE SOURCEDRAIN IMPLANTS ARE ALREADY IN PLACE
#HAPTER "UILDING THE 4RANSISTORS AND HAVE BEEN ANNEALED 4HOSE STRUCTURES WOULD BE DAMAGED IF SUBJECTED TO A HIGH TEMPERATURE FOR TOO LONG A PERIOD
3TRIP 2ESIDUAL #OBALT 4HE UNREACTED COBALT MUST BE REMOVED SINCE IT IS A CONDUCTOR AND WOULD SHORT OUT ALL OF THE TRANSISTORS IF IT WERE LEFT ON THE CHIP ! WET ETCHING PROCEDURE IS USED 4HE COMBINATION MAY CONTAIN AN ACID OR AMMONIUM HYDROXIDE HYDROGEN PEROXIDE AND $) WATER OR SOME SIMILAR CONCOCTION
!NNEAL THE 3ILICIDE $ElNITION !NNEALING IS A HIGH TEMPERATURE TREATMENT THAT REARRANGES THE STRUCTURE OF A MATERIAL 0URPOSE 4HE SILICIDE ANNEALING TREATMENT LOWERS THE RESISTIVITY OF THE COBALT SILICIDE lLM /NE MORE STEP REMAINS IN THE -/3&%4 MAKING PROCESS 4HE SILICIDE REQUIRES A HIGH TEMPERATURE TREATMENT CALLED AN ANNEAL 4HIS TREATMENT IS USUALLY DONE IN AN 240 SYSTEM !NNEALS FOR SILICIDES OFTEN TAKE ONLY ABOUT ONE MINUTE AT AROUND # 4HE ANNEAL REARRANGES THE ATOMIC STRUCTURE OF THE MATERIAL CREATING A LOWER RESISTANCE lLM OFTEN ADJUSTING THE METAL TO SILICON RATIO 4HE WAFERS MAY NOW PROCEED TO THE NEXT MAJOR OPERATION IN THE MANUFACTURING PROCESS MAKING ELECTRICAL CONNECTIONS TO THE TRANSISTORS P #HANNEL TRANSISTOR
N #HANNEL TRANSISTOR
N 7ELL
P 7ELL
P 3OURCE AND $RAIN
N 3OURCE AND $RAIN
&IGURE 4HE #OMPLETED #-/3 4RANSISTORS
#(!04%2
&IRST ,EVEL -ETALLIZATION
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)NTRODUCTION )N THIS CHAPTER YOU WILL LEARN v 7HY BARRIER LAYERS ARE NEEDED v 4HE IMPORTANCE OF PLANARITY v #ONNECTING THE TRANSISTOR TO THE REST OF THE CIRCUIT v -ETALLIZATION TECHNOLOGY v 4HE IMPORTANCE OF LOW K DIELECTRICS /BJECTIVE OF &IRST ,EVEL -ETALLIZATION TO ELECTRICALLY CONNECT THE SOURCE DRAIN AND GATE ELECTRODES OF EACH TRANSISTOR TO OTHER ELEMENTS OF THE CHIP CIRCUIT &IRST ,EVEL -ETALLIZATION 0ROCESS &LOW .ITRIDE AND OXIDE DEPOSITIONS
A 0%#6$ 3I. BARRIER LAYER
B #6$ "03' OR 03'
#-0 PLANARIZATION OF OXIDE 0ATTERN AND ETCH CONTACT HOLES 4UNGSTEN PLUG PROCESS
A $EPOSIT 4I4I. BARRIERGLUE LAYERS
B #6$ TUNGSTEN
C #-0 EXCESS TUNGSTEN
#HAPTER &IRST ,EVEL -ETALLIZATION )NTERMETAL DIELECTRIC )-$ AND 4RENCH %TCH
A $EPOSIT )-$ LOW K DIELECTRIC
B 0ATTERN AND ETCH TRENCHES
#OPPER PROCESS
A 4A4A. BARRIER LAYER
B 3PUTTER
C %LECTROPLATE
D #-0 EXCESS COPPER
E 3I# BARRIER LAYER DEPOSITION
+EY 0OINTS IN THE &IRST ,EVEL -ETALLIZATION 0ROCESS "ARRIER LAYERS ARE NEEDED TO PREVENT A VARIETY OF PROBLEMS !DHESION OR hGLUEv LAYERS ARE USED FOR MAKING THE lLMS STICK TOGETHER 0LANARIZATION IS REQUIRED BY PHOTOLITHOGRAPHY TECHNOLOGY 4UNGSTEN #6$ IS REQUIRED TO lLL HIGH ASPECT RATIO CONTACT HOLES ,OW K DIELECTRIC MATERIALS ARE REPLACING DEPOSITED OXIDE AS THE INTERMETAL DIELECTRIC )-$ #OPPER WIRING FOR INTERCONNECTIONS IS REQUIRED FOR STATE OF THE ART DEVICES %ACH OF THESE POINTS WILL BE EXPLAINED IN THE APPROPRIATE SECTIONS OF THIS CHAPTER $ISCUSSION &IRST LEVEL METALLIZATION HAS CHANGED DRASTICALLY IN RECENT YEARS 4HIS PROCESSING STEP IS DOMINATED BY NEW TECHNOLOGY AND NEW MATERIALS &OR MANY YEARS ELECTRICAL CONNECTIONS TO THE SOURCE DRAIN AND GATE OF EACH TRANSISTOR WERE MADE WITH ALUMINUM THE SAME ALUMINUM lLM THAT WAS PATTERNED AND ETCHED TO FORM THE INTERCONNECTING WIRING BETWEEN THE DEVICES ON THE CHIPS 4HIS ALUMINUM TECHNOLOGY IS STILL WIDELY USED TODAY FOR EARLIER GENERATION CHIPS )NDEED MANY CHIP DESIGNS ENJOY DECADES OF CONTINUED USE SEE &IGURE !S DEVICE DIMENSIONS DECREASED OVER THE YEARS THE DEPTH OF THE PN JUNCTION ALSO DECREASED 7ITH SHALLOWER JUNCTIONS A PROBLEM CALLED JUNCTION SPIKING AROSE 7HEN
)NTRODUCTION ALUMINUM COMES IN CONTACT WITH SILICON SOME OF THE SILICON WILL DISSOLVE IN THE ALU MINUM THIS PHENOMENON FORMS WHAT IS CALLED A SOLID SOLUTION 4HE ALUMINUMSILICON ALLOY WILL IN TURN MOVE INTO THE AREAS VOIDED OF SILICON 7ITH SHALLOW PN JUNCTIONS THESE hSPIKESv COULD BE LONG ENOUGH TO PENETRATE THROUGH THE JUNCTION SHORTING IT OUT 4HE SHORTS WILL PREVENT THE CHIP FROM OPERATING !LUMINUM 3ILICON DIOXIDE
/XIDE
N TYPE 3ILICON
P TYPE
!LUMINUM ALLOY SPIKE SHORTS THROUGH PN JUNCTION
&IGURE *UNCTION 3PIKING
4HE PROBLEM WAS lRST ADDRESSED BY USING ALUMINUM WITH A SMALL AMOUNT OF SILICON ADDED TO IT n TYPICALLY 4HE IDEA WAS THAT IF THE ALUMINUM WAS ALREADY SATURATED WITH SILICON IT WOULD NOT DISSOLVE SILICON FROM THE CONTACT AREAS 4HIS WORKED TO SOME DEGREE BUT AS JUNCTION DEPTHS BECAME STILL SHALLOWER IT BECAME NECESSARY TO TAKE FURTHER STEPS 3OON A THIN DIFFUSION BARRIER LAYER WAS DEPOSITED ON THE WAFERS PRIOR TO ALUMINUM DEPOSITION TO COMPLETELY PREVENT CONTACT BETWEEN THE ALUMINUM AND THE SILICON !NOTHER NEED FOR BARRIER LAYERS IS THE PREVENTION OF THE MOVEMENT OF MOBILE CON TAMINANTS THROUGH THE CHIP 4HESE CONTAMINANTS CAN MIGRATE THROUGH SILICON AND THE lLMS FORMED ON THE CHIP AND COULD RUIN THE CHIP -ORE ON THIS TOPIC WILL APPEAR IN THE FOLLOWING SECTIONS 4HE THICKNESS OF THE ALUMINUM METAL lLM WAS ABOUT ONE MICRON IN /NLY ONE LAYER OF METAL LINES WAS NEEDED TO CONNECT ALL OF THE CIRCUIT ELEMENTS AT THAT TIME 4HE COMPLEXITY DEVICE DENSITY AND SMALL FEATURE SIZES CHARACTERISTIC OF TODAYS CHIPS REQUIRES MANY LAYERS OF METAL TO MAKE ALL OF THE CONNECTIONS &OR THESE MULTILEVEL METAL CHIPS THE THICKNESSES ARE NEARER TO MICRON FOR THE LOWER LEVELS AND AROUND ONE MICRON FOR THE TOP LEVELS WHERE RELATIVELY HIGH CURRENTS ARE CARRIED AROUND THE
#HAPTER &IRST ,EVEL -ETALLIZATION CHIP (OWEVER THE METAL LINE WIDTHS HAVE SHRUNK TO ONE ONE HUNDREDTH OF THEIR WIDTH 4HAT SHRINKAGE EXACERBATED THE FOLLOWING PROBLEM !LUMINUM AND OTHER METALS SUFFER FROM A PROBLEM CALLED ELECTROMIGRATION 4HE ELECTRICAL CURRENT mOWING THROUGH THE ALUMINUM WIRE WILL SOMETIMES CARRY A FEW ATOMS OF THE ALUMINUM RIGHT ALONG WITH IT %NOUGH ATOMS CAN BE MOVED TO PRODUCE VOIDS AND EVENTUALLY COMPLETE BREAKS IN THE WIRES )T IS INTERESTING THAT A mOW OF ELECTRONS CAN MOVE LARGE NUMBERS OF METAL ATOMS AROUND )N THE CASE OF ALUMINUM ONE ATOM WEIGHS ABOUT TIMES AS MUCH AS ONE ELECTRON 4HE DAMAGE DONE BY A HURRICANE OR TORNADO IS A SIMILAR PHENOMENON WIND IS PREDOMINANTLY NOTHING MORE THAN FAST MOVING NITROGEN AND OXYGEN MOLECULES INDIVIDUALLY TINY COMPARED TO THE HUGE STRUCTURES THAT CAN BE DEMOLISHED BY THEIR CUMULATIVE ENERGY
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.ITRIDE AND /XIDE $EPOSITIONS .ITRIDE $EPOSITION $ElNITION ! "ARRIER ,AYER IS A lLM OR STACK OF lLMS THAT ACTS AS A BARRIER AGAINST THE DIFFUSION OF ATOMS OR MOLECULES THROUGH IT 0URPOSE "ARRIER LAYERS PERFORM A VARIETY OF FUNCTIONS &OR EXAMPLE THEY CAN BE USED TO BLOCK SILICON ATOMS FROM DISSOLVING IN ALUMINUM THEY WILL KEEP MOBILE ION CONTAMINATION FROM MIGRATING THROUGH THE CHIP PROTECT THE COMPLETED WAFER FROM AIR AND MOISTURE IN THE ATMOSPHERE AND MAY ALSO ACT AS A GLUE TO HOLD TWO STACKED lLMS TOGETHER $ISCUSSION 3ILICON NITRIDE IS A WIDELY USED BARRIER LAYER AND IS ALSO INCORPORATED INTO COMBINA TIONS OF lLMS USED AS BARRIERS OR GLUE LAYERS 4HE USE OF NITRIDE AS A HARD MASK AND AN IMPLANT MASK HAVE BEEN DISCUSSED PREVIOUSLY )T IS A DIELECTRIC MATERIAL THAT IS CRITICAL TO CHIPMAKING 4HE COMPLETED CHIPS ARE OFTEN PROTECTED BY A BARRIER OF 0%#6$ SILICON NITRIDE 4HE 0%#6$ TECHNIQUE PRODUCES A NITRIDE LAYER CONTAINING A LOT OF HYDROGEN UNLIKE THE ,0#6$ 3I. DISCUSSED EARLIER IN #HAPTER 4HE CHEMICAL FORMULA FOR THIS lLM IS OFTEN WRITTEN AS 3I. 4HE 0%#6$ NITRIDE IS STILL A TOUGH DIELECTRIC AND PERFECTLY CA PABLE OF DOING THE JOB OF A BARRIER LAYER BUT MAY BE DEPOSITED AT A LOWER TEMPERATURE )F NOT FOR THE LOWER TEMPERATURE DEPOSITION IT COULD NOT BE USED BECAUSE THE HIGHER TEMPERATURE METHOD WOULD CAUSE DESTRUCTIVE CHEMICAL AND METALLURGICAL REACTIONS IN THE CHIP WIRING !FTER THE lRST LEVEL OF METAL WIRING IS IN PLACE NO TEMPERATURES HIGHER THAN ABOUT # CAN BE USED
#HAPTER &IRST ,EVEL -ETALLIZATION /NE OF THE APPLICATIONS FOR BARRIER LAYERS COMES FROM THE USE OF COPPER TECHNOL OGY FOR THE METAL INTERCONNECTS 4HE DANGER OF COPPER CONTAMINATING THE DEVICES WILL BE DISCUSSED IN THE UPCOMING SECTION ON COPPER DEPOSITION !NOTHER IMPORTANT TASK FOR THE BARRIER LAYER IS TO KEEP THE DOPANTS IN THE DOPED OXIDE FROM MIGRATING INTO THE UNDERLYING LAYERS AND CHANGING THE DOPING PROlLES REVIEW #HAPTER OF THE CONDUCTING REGIONS OF THE TRANSISTORS 4HE NEXT LAYER TO BE DISCUSSED IN THE PROCESS IS OFTEN A DEPOSITED OXIDE DOPED WITH BORON AND PHOSPHO ROUS 3OME MOVEMENT OF DOPANTS FROM THIS LAYER INTO ADJACENT REGIONS IS POSSIBLE &OR A DISCUSSION OF NITRIDE DEPOSITION REVIEW #HAPTER
3ILICON NITRIDE LAYER
&IGURE .ITRIDE "ARRIER ,AYER
/XIDE $EPOSITION $ElNITION 4HE 0RE -ETAL $IELECTRIC 0-$ IS THE THICK INSULATING LAYER DEPOSITED TO COVER THE TRANSISTORS BEFORE THE lRST LEVEL OF METAL WIRING IS FORMED 0URPOSE 4HE PRE METAL DIELECTRIC PREVENTS ELECTRICAL SHORTS BETWEEN THE CONDUCTING ELEMENTS OF THE TRANSISTORS AND THE WIRES THAT CONNECT THE TRANSISTORS TO THE REST OF THE CIRCUIT )T IS RELATIVELY THICK TO REDUCE ELECTRICAL INTERACTION BETWEEN THE WIRING AND THE DEVICES BELOW 4HE PRIMARY CONCERN IS PARASITIC CAPACITANCE THE TEN DENCY FOR NEARBY CONDUCTORS TO INTERACT WHEN THEY ARE CARRYING A CURRENT 0ARASITIC CAPACITANCE DELAYS THE TRANSMISSION OF SIGNALS THROUGH THE CIRCUIT WIRING IT IS DISCUSSED LATER IN THE CHAPTER $ISCUSSION 4HE PRE METAL DIELECTRIC IS A #6$ OXIDE THAT IS DOPED WITH PHOSPHOROUS OR WITH BOTH BORON AND PHOSPHOROUS 4HE NAMES OF THESE lLMS ARE PHOSPHOSILICATE GLASS 03'
.ITRIDE AND /XIDE $EPOSITIONS AND BOROPHOSPHOSILICATE GLASS "03' 4HE HEAVILY DOPED "03' HAS BEEN USED FOR DECADES AS THE PRE METAL DIELECTRIC BECAUSE IT WILL MELT OR hmOWv AT A COMPARATIVELY LOW TEMPERATURE 4HIS PROPERTY WAS USED TO GET A SMOOTHER mATTER COATING OVER THE TRANSISTORS WHICH MADE IT EASIER TO DEPOSIT UNIFORM CONFORMAL METAL LAYERS ON THE GLASS 4HE USE OF #-0 AND TUNGSTEN #6$ TECHNOLOGY HAVE ELIMINATED THE ABOVE CON CERNS FOR STATE OF THE ART CHIPS SO 03' IS A GOOD REPLACEMENT lLM )T HAS NO BORON SO THE RISK OF MIGRATING DOPANTS IS REDUCED (OWEVER "03' IS STILL WIDELY USED BECAUSE IT IS A WELL UNDERSTOOD lLM 4HERE IS A GOOD REASON TO KEEP THE PHOSPHOROUS IN THE OXIDE lLM ! PHOSPHOROUS DOPED GLASS IS AN EXCELLENT hGETTERv OF SODIUM )N OTHER WORDS THE lLM WILL TRAP AND HOLD SODIUM IONS THAT MIGRATE INTO IT 3ODIUM IS A VERY COMMON MOBILE ION CONTAMI NANT ESPECIALLY CONSIDERING THAT IT IS IN EVERYONES BODY AND ALL OVER THE SKIN /UR PRESENCE IS DANGEROUS TO THE WAFER 2EVIEW #HAPTER AND FOR MORE INFORMATION ON #6$ PROCESSES
"OROPHOSPHOSILICATE 'LASS 03' OR "03'
&IGURE #ROSS 3ECTION AFTER /XIDE $EPOSITION
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#-0 0LANARIZATION $ElNITION 0LANARIZATION IS THE PROCESS OF MAKING THE SURFACE OF THE WAFER AS mAT OR PLANAR AS POSSIBLE 0URPOSE 4HE BUMPS ON THE SURFACE OF THE WAFER CAN BE ROUGHLY AS HIGH AS THE DEPTH OF FOCUS OF THE STEPPERS IN STATE OF THE ART TOOLS 4HE STEPPER IS UNABLE TO LOOK DOWN AT THE WAFER SURFACE AND FOCUS ON ALL POINTS OF THE WAFER TO PRINT THE NEXT PATTERNIN THIS CASE THE CONTACT HOLES 7ITHOUT PLANARIZATION THE HOLES AT SOME POINTS ON THE WAFER WOULD BE OUT OF FOCUS RESULTING IN A POORLY DElNED PATTERN OR NO PATTERN AT ALLIN THE RESIST MASK
)N FOCUS
/UT OF FOCUS
"03'
&IGURE )LLUSTRATION OF 3TEPPER &OCUS 0ROBLEM
#HAPTER &IRST ,EVEL -ETALLIZATION $ISCUSSION (ISTORICALLY PLANARIZATION IS THE lRST APPLICATION OF #-0 EVER USED ON THE FRONT OF THE WAFER AFTER DEVICE STRUCTURES WERE FORMED -ANY INDUSTRY PROFESSIONALS SUBSTITUTED hPLANARIZATIONv FOR hPOLISHINGv WHEN USING THE TERM #-0 BECAUSE IT WAS THE lRST AND FOR A LONG TIME THE ONLY #-0 APPLICATION PERFORMED IN THE FAB 7ITH SO MANY POL ISHES BEING USED TODAY THAT TERMINOLOGY ERROR HAS DISAPPEARED &OR A #-0 REVIEW SEE #HAPTER 3ECTION 4HE PROCESS IS AN OXIDE POLISH MUCH LIKE THE ONE USED FOR POLISHING THE DEPOSITED OXIDE AT 34) 0LANARITY WAS ONE OBJECTIVE OF THAT APPLICATION AS IT IS HERE )N THIS CASE THE POLISHING OPERATION ONLY REMOVES THE BUMPS FROM THE OXIDE LAYER AND DOES NOT REMOVE ALL OF THE OXIDE #AREFUL PROCESS CONTROL IS IMPORTANT SINCE IT IS NECESSARY TO LEAVE SUFlCIENT OXIDE THICKNESS FOR INSULATING PURPOSES 2ECALL THAT THE 34) PROCESS POLISHED OFF THE EXCESS OXIDE AND STOPPED ON THE NITRIDE LAYER UNDERNEATH 2EVIEW #HAPTER FOR MORE DETAILS ABOUT #-0 AND OXIDE POLISHING
"03'
&IGURE 0LANARIZED "03'
3%#4)/.
0HOTO%TCH FOR #ONTACT (OLES #ONTACT (OLE 0HOTOLITHOGRAPHY $ElNITION ! #ONTACT (OLE IS THE HOLE THAT IS ETCHED COMPLETELY THROUGH THE PRE METAL DIELECTRIC AND THE NITRIDE BARRIER BELOW IT 4HE CONTACT HOLES WILL BE lLLED WITH METAL MAKING ELECTRICAL CONNECTION TO THE SOURCE DRAIN AND GATE OF EACH TRANSISTOR AND TO ANY OTHER POINTS ON THE SILICON SURFACE OR CONDUCTING FEATURES WHERE CON NECTIONS ARE NEEDED 3EE #HAPTER FOR A REVIEW OF PHOTOLITHOGRAPHY $ISCUSSION 4HIS PATTERNING PROCESS IS MUCH LIKE ALL OF THE OTHER RESIST MASK APPLICATIONS DISCUSSED PREVIOUSLY 4HE PHOTOMASK FOR CONTACT HOLE ETCH IS INTERESTING BECAUSE IT IS USUALLY COM PRISED OF LARGE ARRAYS OF TINY HOLES )T IS NOT UNCOMMON FOR THE PATTERNED RESIST TO HAVE OPENINGS TO THE UNDERLYING OXIDE THAT AMOUNTS TO ONLY ABOUT OF THE TOTAL SURFACE AREA OF THE WAFER 4HERE ARE MILLIONS OF HOLES IT IS TRUE BUT EACH ONE IS VERY VERY SMALL 0ROCESSING PROBLEMS ARISE BECAUSE OF THE EXTREMELY SMALL DIAMETER OF THE CONTACT OPENINGS 4HE DEVELOPER SOLUTION MUST BE ABLE TO PENETRATE ALL THE WAY TO THE BOTTOM WHILE DISSOLVING THE EXPOSED RESIST BUT SURFACE TENSION INHIBITS THAT ACTION 3URFAC TANTS WETTING AGENTS REDUCE SURFACE TENSION IN LIQUIDS AND MUST BE ADDED TO THE DEVELOPER TO BE SURE THAT THE SOLUTION DISSOLVES ALL OF THE EXPOSED RESIST TO CREATE THE CONTACT HOLES 3URFACTANTS MUST ALSO BE USED FOR THE $) WATER RINSE !LL OF THE RESIDUAL DEVEL OPER SOLUTION MUST BE RINSED OUT OF THE HOLES OR A SCUM IS LEFT BEHIND 4HE SCUM WILL INHIBIT THE ABILITY OF THE ETCH CHEMICALS TO CONTACT THE OXIDE AND THE PATTERN MAY NOT BE PROPERLY ETCHED INTO THE lLM
#HAPTER &IRST ,EVEL -ETALLIZATION
&IGURE #ONTACT (OLE 2ESIST 0ATTERN
#ONTACT %TCH $ElNITION ! (IGH !SPECT 2ATIO #ONTACT (!2# IS A CONTACT HOLE THAT IS VERY DEEP COMPARED WITH ITS DIAMETER !N ASPECT RATIO IS OFTEN FOUND IN STATE OF THE ART CONTACTS !SPECT 2ATIO IS SIMPLY THE RATIO OF THE DEPTH TO THE DIAMETER OF THE HOLE ! HIGH ASPECT RATIO MEANS THAT THE DEPTH OF THE HOLE IS LARGE AS COMPARED TO THE DIAMETER OF THE HOLE $ISCUSSION #ONTACT ETCH IS PRIMARILY AN OXIDE ETCH WHICH CLOSELY RESEMBLES THE PREVIOUS EXAM PLES )T IS GENERALLY mUORINE BASED WITH ADDITIONAL CHEMICAL COMPONENTS THAT PRODUCE THE IMPORTANT SIDEWALL PASSIVATION DEPOSITS 4HE PROCESS IS OFTEN A TWO STEP ETCH BECAUSE THE NITRIDE lLM UNDERNEATH THE PRE METAL DIELECTRIC MUST BE REMOVED FROM THE BOTTOM OF THE CONTACT HOLE FOR THE ELECTRICAL CONNECTION TO BE MADE 3ILICON NITRIDE IS ETCHED WITH A SIMILAR CHEMISTRY TO THAT USED FOR THE OXIDE GLASS 4HE ETCH REQUIREMENTS ARE NECESSARILY STRICT FOR THESE HOLES 4HE SIDEWALLS MUST BE VERTICAL OR NEARLY SO BECAUSE THEY ARE ALL SO CLOSE TOGETHER THAT ANY LARGE DEGREE OF SLOPING COULD CAUSE TWO HOLES TO MEET AND SHORT OUT WHEN lLLED WITH METAL )N ADDITION A SLOPED SIDEWALL WOULD PRODUCE A SMALLER OPENING AT THE BOTTOM REDUCING
0HOTO%TCH FOR #ONTACT (OLES THE SIZE OF THE CONTACT AREA CAUSING INCREASED ELECTRICAL RESISTANCE 3O THE AMOUNT OF SIDEWALL PASSIVATION PRODUCED IN THE ETCH CHEMISTRY IS CAREFULLY REGULATED !S ONE WOULD EXPECT THE HIGH ASPECT RATIO HOLES OF SUCH TINY DIAMETERS CREATE CHEMICAL TRANSPORTATION PROBLEMS GETTING THE REACTANT CHEMICALS INTO THE HOLES WHILE REMOVING THE PRODUCTS OF REACTION FROM THE HOLES ALL THE WHILE PASSIVATING THE SIDE WALLS WITH LARGE ORGANIC MOLECULES )T IS NO EASY TASK 2EENTRANT PROlLES UNDERCUTTING WOULD ALSO BE A KILLER DEFECT BECAUSE THE HOLE COULD NOT RELIABLY BE lLLED WITH METAL !NY VOIDS IN THE DEVICES CAN TRAP AIR AND MOIS TURE AND BECOME A RELIABILITY PROBLEM !FTER ETCHING THROUGH THE NITRIDE IT IS IMPORTANT TO STOP THE ETCH WITHOUT REMOV ING MUCH OF THE SILICON 4HE SURFACE OF THE SILICON SOURCE DRAIN AND GATE ELECTRODES IS THE CONTACT POINT FOR THE METAL INTERCONNECTS )N ORDER FOR GOOD ELECTRICAL CONTACT TO BE MADE IT IS BEST IF THE SILICON IS UNDAMAGED /NLY A VERY SMALL AMOUNT OF SILICON ERO SION CAN BE TOLERATED
&IGURE #OMPLETED #ONTACT %TCH
#HAPTER &IRST ,EVEL -ETALLIZATION (ISTORICAL 0ERSPECTIVE ON !SPECT 2ATIO )T IS INTERESTING TO NOTE THAT WHILE DEVICE GEOMETRIES HAVE SHRUNK DRAMATICALLY WITH TIME THE THICKNESS OF THE LAYERS IN DEVICE FABRICATION HAVE DECREASED QUITE LITTLE 4HE lLM THICKNESSES HAVE REMAINED ABOUT THE SAME FOR CIRCUIT PERFORMANCE REASONS 4O MAXIMIZE CIRCUIT SPEED AND MINIMIZE POWER CONSUMPTION INTERCONNECTION RESISTANCES AND STRAY CAPACITANCES MUST BE KEPT AS LOW AS POSSIBLE 4HAT REQUIRES RATHER THICK INSULATING lLMS SEPARATING CONDUCTING LAYERS !LSO THE METAL FOR WIRING HAS REMAINED THICK TO MINIMIZE THE CIRCUIT INTERCONNECTION RESISTANCES 4HE ASPECT RATIO HAS INCREASED DRAMATICALLY BECAUSE THE FEATURES ON THE CHIP HAVE BEEN PUSHED CLOSER AND CLOSER TOGETHER WHILE THE lLM THICKNESS HAS NOT CHANGED MUCH 9EARS AGO THE DIAMETER OF THE CONTACT HOLE WAS ABOUT THE SAME AS THE OXIDE lLM THICKNESS GIVING AN ASPECT RATION OF ONE OR LESS 4ODAY THE lLM THICKNESS IS ABOUT THE SAME BUT THE HOLES DIAMETER HAS BEEN REDUCED TO LESS THAN A TENTH OF ITS EARLIER DIAMETER %IGHT TO ONE ASPECT RATIOS ARE COMMON NOW
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4UNGSTEN 0LUG 0ROCESS $EPOSIT 4I4I. "ARRIER'LUE ,AYERS $ElNITION ! 'LUE ,AYER OR !DHESION ,AYER IS A lLM THAT BONDS WELL TO TWO OTHER lLMS ON THE CHIP HOLDING THEM TOGETHER $ISCUSSION 4HE JUNCTION SPIKING STORY IN 3ECTION REFERS TO THIS STEP IN THE PROCESS 4UNGSTEN PLUGS HAVE REPLACED THE ALUMINUM IN THE CONTACT HOLES BUT BARRIER LAYERS ARE AS IMPOR TANT AS EVER !N EARLY BARRIER MATERIAL WAS A SPUTTERED lLM OF TITANIUMTUNGSTEN 4HIS lLM WAS USUALLY A MIXTURE OF TITANIUM AND TUNGSTEN SPUTTERED FROM A TARGET OF THAT COMPOSITION ,ATER TITANIUM NITRIDE 4I. WAS FOUND TO BE A MORE EFFECTIVE DIFFU SION BARRIER AND HAS BEEN VERY WIDELY USED EVER SINCE 5SUALLY A THIN lLM OF TITANIUM IS DEPOSITED BEFORE THE 4I. TO REDUCE CONTACT RESISTANCE 4ITANIUM IS A VERY REACTIVE METAL AND WILL BREAK THROUGH ANY THIN NATIVE OXIDE lLM THAT GROWS READILY ON THE EXPOSED SILICON CONTACT AREAS 4ITANIUM ALSO STICKS TO THE OXIDE lLM VERY WELL )T IS EASY TO FORGET THAT THE lLMS MAY BE INCOMPATIBLE AND DELAMINATE PEEL OFF 4HE NEED FOR A hGLUE LAYERv OR hADHE SION LAYERv IS ALWAYS A CONCERN IN THE LAYERING PROCESS 4ITANIUM IS DEPOSITED USING SPUTTERING 06$ 4HERE ARE BOTH 06$ AND #6$ PRO CESSES FOR THE DEPOSITION OF 4I.
#HAPTER &IRST ,EVEL -ETALLIZATION 4ITANIUM .ITRIDE
4ITANIUM
&IGURE "ARRIER ,AYER $EPOSITION .OT SHOWN IN LATER lGURES FOR SIMPLICITY
4UNGSTEN #6$ )T IS VERY DIFlCULT TO lLL (!2# HOLES WITH SPUTTERED ALUMINUM -UCH WORK HAS BEEN DONE ON ALUMINUM SPUTTER TECHNOLOGY IN AN ATTEMPT TO OVERCOME THIS LIMITATION BUT SUCCESS HAS BEEN VERY LIMITED 4HE DIFlCULTY LIES IN THE NATURE OF SPUTTERING 4HE NATURALLY RANDOM SCATTERING OF !L ATOMS RAINING DOWN IN A 06$ SYSTEM WILL COVER THE SURFACE OF THE WAFER BUT WHEN SMALL HOLES ARE TO BE lLLED THE METHOD IS UNRELIABLE AS SHOWN IN &IGURE
&IGURE -ETAL 3PUTTER $EPOSITION 0ROBLEMS IN 3MALL 'EOMETRY (OLES
4UNGSTEN 0LUG 0ROCESS 4HE SOLUTION TO THE PROBLEM WAS TO CHANGE THE DEPOSITION METHOD TO #6$ AND CHANGE THE METAL TO TUNGSTEN SINCE THERE WERE MANY PROBLEMS WITH ALUMINUM #6$ 4UNGSTEN 7 DEPOSITION IS AN ,0#6$ PROCESS 4HE lLM FORMS ON ALL WAFER SURFACES AND SEEMS TO GROW UP FROM THE BOTTOM AND OUTWARD FROM THE WALLS OF THE CONTACT HOLES RATHER UNIFORMLY REGARDLESS OF THE ORIENTATION OR SHAPE OF THE SURFACE 4HE MOLECULES OF PROCESS GASES MOVE AROUND RAPIDLY IN ALL DIRECTIONS AND CAN EAS ILY ENTER SMALL HOLES AND REACT ON ALL OF THE SURFACES 4HE INTERESTING CHARACTERISTIC OF #6$ 7 IS THE FORMATION OF A SEAM THAT RUNS UP THE CENTER OF THE PLUG AND IS CLEARLY VISIBLE AFTER #-0
&IGURE 4UNGSTEN #6$ &ILM $EPOSITION
N CHANNEL TRANSISTOR
P CHANNEL TRANSISTOR
&IGURE ! #OMPLEMENTARY 0AIR OF 4RANSISTORS WITH 4UNGSTEN $EPOSITED TO &ILL #ONTACT (OLES
#HAPTER &IRST ,EVEL -ETALLIZATION
4UNGSTEN #-0 4HE TUNGSTEN THAT lLLS THE CONTACT HOLE IS CALLED A PLUG #-0 REMOVES THE EXCESS 7 FROM THE DEPOSITION LEAVING THE PLUGS BEHIND 4HE POLISH MUST ALSO REMOVE THE 4I4I. BARRIER LAYER BECAUSE IT IS ALSO CONDUCTIVE AND WOULD CAUSE ALL OF THE CONTACTS TO SHORT OUT 4HEREFORE THE POLISH STOPS ON OXIDE THE PRE METAL DIELECTRIC 4HE TUNGSTEN POLISH IS THE lRST METAL POLISH IN THE PROCESS mOW -ETALS PRESENT SOME INTERESTING CHALLENGES AND CAN BE TRICKY TO REMOVE WITH #-0 ! TYPICAL SLURRY CONTAINS AN ABRASIVE OF SILICA OR ALUMINA IN $) WATER 4HE INCLUSION OF AN ACID AND AN OXIDIZER IN THE SLURRY IS SOMETIMES APPLICABLE BUT CONTROL OF THE SURFACE REMOVAL CAN BE MORE DIFlCULT WITH A METAL lLM 4HERE EXISTS GREAT VARIETY IN #-0 SLURRIES 2ECALL FROM EARLIER DISCUSSIONS OF #-0 THAT THE PRIMARY lLM REMOVAL MECHANISM IS ABRASION NO MATTER WHAT LIQUID COMPONENTS ARE USED IN THE SLURRY -ETAL DEFECTS SUCH AS SPALLING AND VOIDS FROM RIPPED OFF PIECES OF METAL ARE A COMMON CONCERN
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&IGURE #OMPLETED 4UNGSTEN 0LUGS
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,OW K $IELECTRIC 0ROCESS $EPOSIT ,OW K $IELECTRIC &ILM $ElNITION ,OW K $IELECTRIC -ATERIALS ARE ELECTRICAL INSULATORS WITH RELATIVELY LOW DI ELECTRIC CONSTANTS 4HE LOWEST VALUE OF K IS VACUUM WHERE K AIR IS ONLY SLIGHTLY HIGHER THAN 3ILICON DIOXIDE THE ORIGINAL INTERMETAL DIELECTRIC )-$ HAS A K OF ABOUT 4HE OBJECTIVE IS TO lND PRODUCTION WORTHY MATERIALS WITH VALUES BELOW AND AS CLOSE TO AS POSSIBLE $ElNITION )NTERMETAL $IELECTRIC )-$ IS THE TERM FOR THE INSULATING LAYERS SEPARAT ING THE INTERCONNECTING METAL WIRING PATTERNS )T IS ALSO KNOWN AS THE )NTERLEVEL $IELECTRIC ),$ %VEN THOUGH THIS lRST LOW K lLM COULD BE CONSIDERED TO BE PART OF A PRE METAL DI ELECTRIC lLM STACK IT IS OFTEN THE SAME MATERIAL AS THE LATER INTERMETAL DIELECTRIC LAYERS ON THE WAFER SO THE TERM )-$ WILL BE USED HERE AS WELL $ISCUSSION 4HE )-$ IS AN IMPORTANT INSULATOR )T SEPARATES AND INSULATES ALL OF THE INTERCONNECT ING METAL WIRES ON THE CHIP 4HERE IS MORE GOING ON HERE THAN MEETS THE EYE HOWEVER %VEN THOUGH THE METAL LINES ARE SEPARATED BY INSULATOR THEY STILL COMMUNICATE WITH EACH OTHER BECAUSE THEY SENSE EACH OTHERS ELECTRIC lELDS ! PARASITIC CAPACITANCE CAN FORM AT EVERY PLACE THAT THE WIRES ON DIFFERENT LEVELS IN THE STACK CROSS OVER EACH OTHER OR ANYWHERE THAT WIRES COME CLOSE TOGETHER 4HESE COUNTLESS MICROSCOPIC CAPACITORS CUMULATIVELY SLOW DOWN THE CHIP BECAUSE THEY MUST BE CHARGED AND DISCHARGED EVERY TIME A SWITCHING OPERATION OCCURS
#HAPTER &IRST ,EVEL -ETALLIZATION 0ARASITIC #APACITANCE ! CAPACITOR IN ITS MOST FUNDAMENTAL FORM IS A CHARGE STORAGE DEVICE )MAG INE TWO WIRES CONNECTED TO THE POLES OF A BATTERY THAT ARE EACH ATTACHED TO A COIN )F THE TWO COINS ARE HELD WITH INSULATING MATERIAL FACING AND CLOSE TO EACH OTHER WITHOUT TOUCHING CHARGES FROM THE BATTERY WILL mOW INTO THEM AND BE HELD THERE INDElNITELY THIS ARRANGEMENT CONSTITUTES A CAPACITOR -OVE THE COINS FAR AWAY FROM EACH OTHER AND THE CHARGES WILL mOW BACK INTO THE BATTERY "UT DISCONNECT ONE OR BOTH OF THE WIRES WHEN THE COINS ARE CLOSE TOGETHER AND THE CAPACITOR WILL REMAIN CHARGED "ETTER NOT TO TOUCH THEM 5SING NONTECHNICAL TERMINOLOGY PARASITIC CAPACITANCE IS A PHENOMENON THAT OCCURS EVERYWHERE IN THE CHIP THAT CONDUCTORS ARE POSITIONED RELATIVELY CLOSE TO ONE ANOTHER !LTHOUGH THERE IS INSULATING MATERIAL SEPARATING THESE CONDUCTORS THEY WEAKLY INTERACT 4HE VOLTAGE THAT CAN BE FELT BETWEEN THEM ATTRACTS AND HOLDS A SMALL NUMBER OF CHARGES 4HE EFFECT IS THE SAME AS HAV ING A SMALL CAPACITOR IN THE CIRCUIT -ANY TYPES OF CHIPS WILL HAVE MILLIONS OF CROSSING POINTS IN THE WIRING 4HE PROBLEM WITH PARASITIC CAPACITANCE IS THAT EVERY TIME A TRANSISTOR TURNS ON THE ELECTRICAL CURRENT IN THE WIRE CARRYING THAT SIGNAL MUST CHARGE UP ALL OF THE PARASITIC CAPACITORS IN THE WIRE BEFORE THE SIGNAL CAN PASS -ANY TYPES OF CHIPS SWITCH ON AND OFF MILLIONS OF TIMES A SECOND .EEDLESS TO SAY THIS ISSUE SLOWS THE CHIP DOWN 4HE LAYERS OF WIRING IN A CHIP GENERALLY FORM A CRISSCROSS PATTERN WHICH HELPS TO MINIMIZE THE EFFECT OF EACH INTERACTION POINT )N ADDITION THE PARASITIC CAPACITANCE PROBLEM COULD BE REDUCED BY INCREASING THE SPACING BETWEEN LINES IN THE SAME LEVEL AND BY USING THICKER )-$ LAYERS (OWEVER MOVING THE LINES FARTHER APART WOULD INCREASE THE CHIP SIZE TOO MUCH )N ADDITION THERE IS A LIMIT TO THE lLM THICKNESS AND THE ABILITY OF ETCH TO CUT HOLES IN THE lLM FOR THE INTERCONNECTIONS &URTHER IMPROVEMENTS IN CHIP SPEED REQUIRE LOWER ING THE K VALUE OF THE )-$
4HE DISCUSSION OF HIGH K DIELECTRICS SHOWED HOW THOSE MATERIALS HELP MORE CHARGES TO FORM IN THE CHANNEL BECAUSE OF A STRONG INTERACTION BETWEEN THE GATE AND THE SUBSTRATE SURFACE )T IS EXACTLY THE OPPOSITE EFFECT THAT IS DESIRED HERE ,OW K MATERIALS IMPROVE THE SPEED OF THE CHIP BY MINIMIZING THE INTERACTION BETWEEN ADJA CENT CONDUCTORS 3ILICON DIOXIDE WAS THE STANDARD )-$ FOR MANY YEARS BUT LOWER K MATERIALS ARE REPLACING IT 4HERE ARE MANY CANDIDATES FOR REPLACING SILICON DIOXIDE AS THE )-$
,OW K $IELECTRIC 0ROCESS ! WIDE VARIETY OF DIELECTRICS WITH K VALUES IN THE TO LEVEL HAVE BEEN INVES TIGATED FOR MANY YEARS 3OME ARE INORGANIC SOME ORGANIC AND SOME ARE IN BETWEEN -ATERIALS CALLED ORGANO SILICATE GLASSES /3' OR CARBON DOPED OXIDES #$/ WITH K VALUES OF TO HAVE RECEIVED A LOT OF ATTENTION 4HESE MATERIALS ARE CHEMICALLY SIMILAR TO SILICON DIOXIDE WHICH MAKES THEM RELATIVELY EASY TO INTEGRATE INTO THE MAN UFACTURING PROCESS 3OME ARE DEPOSITED IN CONVENTIONAL #6$ SYSTEMS THAT ALSO OFFER THE POSSIBILITY OF DEPOSITING SILICON CARBIDE BARRIER LAYERS IN THE SAME PROCESS STEP /THER TYPES OF #$/ CALLED SPIN ON DIELECTRIC 3/$ OR SPIN ON GLASS 3/' ARE APPLIED BY SPINNING THEM ON LIKE PHOTORESIST FOLLOWED BY A LOW TEMPERATURE CURING CYCLE 4HERE ARE INORGANIC CARBON FREE VERSIONS OF THE SPIN ON MATERIALS AS WELL 4HE ALL ORGANIC DIELECTRICS ARE BASICALLY SPECIAL PLASTICS 4HEY ARE SPUN ON AND CURED 4HEY REQUIRE MUCH DIFFERENT PROCESSING THAN THE SILICON OXIDE BASED MATERI ALS AND THIS HAS DISCOURAGED SOME COMPANIES FROM WORKING WITH THEM ALTHOUGH ONE MAJOR COMPANY HAS BEEN USING ONE OF THEM FOR SEVERAL YEARS &OAMS THAT ARE MADE FROM THE KINDS OF MATERIALS DESCRIBED ABOVE OFFER GREAT PROMISE BECAUSE THEIR K VALUES APPROACH 4HIS LOW K VALUE IS FOUND BY AVERAGING THE VALUES OF THE BULK MATERIAL AND THAT OF THE GAS IN THE PORES OR BUBBLES THAT FORM IN THE BULK MATERIAL &OAMS HOWEVER PRESENT MANY PROCESS DIFlCULTIES AND DO NOT STAND UP WELL TO #-0 )T APPEARS THAT IT WILL BE SOME TIME BEFORE PRACTICAL FOAMS ARE DEVELOPED &LUORINATED SILICATE GLASS &3' HAS BEEN WIDELY USED TO REPLACE SILICON DIOXIDE AND HAS SERVED THE INDUSTRY WELL DOWN TO THE NMn NM TECHNOLOGY RANGE )T IS CLEAR THAT NEW MATERIALS WILL BE NEEDED FOR THE NEXT TECHNOLOGY NODE OF NM AND BEYOND #URRENTLY SOME OF THE ORGANO SILICATE GLASSES AND ORGANICS HAVE ENTERED PRO DUCTION 4HE NAME hORGANO SILICATE GLASSv INDICATES THAT THERE ARE STRONGLY ORGANIC COMPONENTS IN THE lLM (OWEVER THESE MATERIALS CAN BE ETCHED WITH PLASMA
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&IGURE ,OW K )-$ &ILM $EPOSITION
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#HAPTER &IRST ,EVEL -ETALLIZATION CHEMISTRIES SIMILAR TO THOSE USED FOR SILICON DIOXIDE 4HAT CHARACTERISTIC AS WELL AS THEIR ABILITY TO STAND UP TO #-0 MAKE THEM VERY PRODUCTION WORTHY MATERIALS -OST EVERY LOW K )-$ HAS A DIFFERENT DEPOSITION AND ETCH PROCESS 4HIS FASCINAT ING AREA OF TECHNOLOGICAL DEVELOPMENT IS CHANGING RAPIDLY 4HE READER CAN ENJOY MANY OTHER SOURCES OF INFORMATION TO MONITOR THESE ADVANCES IN CHIPMAKING
4RENCH 0HOTOLITHOGRAPHY AND %TCH 4RENCHES FORMED IN THE )-$ lLM ARE TO BE lLLED WITH COPPER IN A hSINGLE DAMASCENE PROCESSv SEE #HAPTER FOR A MORE COMPLETE DISCUSSION OF THIS TERMINOLOGY 4HIS PROCESS FORMS CONDUCTING WIRES IN MUCH THE SAME WAY THAT A DECORATIVE METAL INLAY IS DONE 4HE TRENCHES ARE FORMED BY AN ETCH PROCESS OVER THE TUNGSTEN PLUGS THAT ARE TO BE ELECTRICALLY CONNECTED 4HE TRENCHES ARE THEN lLLED WITH METAL 4HE EXCESS METAL IS POLISHED OFF WITH #-0 LEAVING A CONDUCTING hWIREv IN THE TRENCH %ARLIER TECHNOL OGY FORMED THE CONDUCTING WIRES BY ETCHING ALUMINUM LINES ON TOP OF THE )-$ SEE &IGURE !LUMINUM )NTERCONNECTION WIRING PATTERN SITS ON TOP OF INSULATING SURFACE
E
RFAC
SU
ON PE
#OPPER )NTERCONNECTION WIRING PATTERN RECESSED INTO THE INSULATING SURFACE USING DUAL DAMASCENE PROCESS
I
STR NUM
MI
!LU
3U INSU RFACE O LATIN F OX G LA IDE O YER R ON W OTHER AFER
H ENC
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#O
0LUGS MAKE CONTACT TO TRANSISTORS OR WIRING BELOW
s
!LUMINUM WIRING STILL WIDELY USED BUT BEING REPLACED BY COPPER
&IGURE #OPPER $AMASCENE
4HE PHOTOLITHOGRAPHY PROCESS IS STRAIGHTFORWARD 4HE CHALLENGES FOR PHOTO AT THIS LEVEL ARE ALIGNMENT OF THE PATTERN AND CREATING A MASK TO ETCH THIN TRENCHES 4HE TRENCHES MUST BE POSITIONED PRECISELY OVER TOP OF THE TUNGSTEN PLUGS A JOB MADE HARDER BECAUSE OF THE NARROWNESS OF THE TRENCHES
,OW K $IELECTRIC 0ROCESS 4HE ETCH PRESENTS MANY CHALLENGES AS WELL )F THE LOW K MATERIAL IS AN INORGANIC lLM THEN THE ETCH IS SIMILAR TO A STANDARD OXIDE ETCH /RGANIC LOW K MATERIALS CAN BE MUCH MORE DIFlCULT TO PROCESS AND REQUIRE A HARD MASK BECAUSE THE ORGANIC LOW K IS CHEMICALLY SIMILAR TO THE RESIST ETCHING IT WILL ALSO ETCH THE RESIST MASK AT A RATHER RAPID RATE /THER TYPES OF INNOVATIVE lLMS REQUIRE HIGHLY SPECIALIZED CHEMISTRY AND TOOLS "ECAUSE OF THE DIFFERENCES IN LOW K MATERIALS THERE IS NO STANDARD PROCESS THAT HAS BEEN ADOPTED BY THE INDUSTRY AS YET 4HIS IS ONE OF THE MOST EXCITING EXAMPLES OF 2$ GOING ON IN THE INDUSTRY TODAY AND WILL PRODUCE MANY FASCINATING ADVANCES AS THE WORK PROCEEDS
A 6IEW OF TRENCHES FROM ABOVE
4RENCH
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B #ROSS SECTION WITH FOUR TRANSISTORS
&IGURE #OMPLETED 4RENCHES
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#OPPER &IRST ,EVEL )NTERCONNECTION 0ROCESS 4A4A. "ARRIER ,AYER $EPOSITION #OPPER IS A VERY DANGEROUS CONTAMINANT IN SILICON DEVICES (OW CAN IT BE USED SAFELY IN MAKING A CHIP 4HE STORY OF COPPERS ENTRY INTO THE CHIPMAKING PROCESS IS ONE OF ACUTE PARANOIA #OPPER OTHER COMMON METALS SODIUM AND IN FACT A LARGE PORTION OF THE PERIODIC TABLE WILL CONTAMINATE THE CHIPS AND KILL THE DEVICES 'REAT CARE IN MANUFACTURING IS REQUIRED 4HE MOTIVATION TO INTEGRATE COPPER IS VERY HIGH #OPPER IS A BETTER CONDUCTOR THAN ALUMINUM AND INCIDENTALLY HAS A LOW RATE OF ELECTROMIGRATION 4HE CHIPS WILL CER TAINLY BE FASTER AND MORE RELIABLE WITH COPPER RIGHT /NLY IF THE COPPER CAN BE KEPT AWAY FROM THE TRANSISTORS )T IS STILL THE PRACTICE IN MANY FABS TO COMPLETE THE CHIPS UP TO THE POINT WHERE THEY ARE READY FOR COPPER DEPOSITION AND THEN THE WAFERS LEAVE THE hFRONT END OF THE ;MANUFACTURING= LINE v NEVER TO RETURN 4HE COPPER MUST BE KEPT AWAY FROM THE WAFERS IN THE EARLY STAGES OF THE PROCESS TO ENSURE THAT THEY ARE NOT CONTAMINATED 4ERMINOLOGY !CRONYMS ABOUND IN THE SEMICONDUCTOR INDUSTRY &%/, STANDS FOR hFRONT END OF THE LINEv AND "%/, STANDS FOR hBACK END OF THE LINEv &%/, IS DElNED AS THE PROCESSING STEPS THAT BEGIN WITH THE STARTING SILICON WAFER THROUGH AND INCLUDING CONTACT ETCH !LL OF THE PROCESSING STEPS AFTER CONTACT ETCH UNTIL THE WAFER LEAVES THE FAB ARE DONE IN THE "%/, 4HIS TERMINOLOGY EMPHASIZES THE DIFFERENCE IN THE PROCESSING STEPS INVOLV ING METAL DEPOSITION AND ALL THOSE PRIOR TO THE INTRODUCTION OF METAL ON THE
#HAPTER &IRST ,EVEL -ETALLIZATION WAFER -ANY METALS PARTICULARLY COPPER ARE DANGEROUS CONTAMINANTS AND CANNOT BE ALLOWED TO CONTACT UNPROTECTED SURFACES IN THE LAYERS CONTAINING THE TRANSISTORS
"ARRIER LAYERS MUST COMPLETELY SEAL IN THE COPPER TO PREVENT IT FROM MIGRATING IN ANY DIRECTION &OR THE WALLS OF THE COPPER lLLED HOLES AND TRENCHES A BARRIER LAYER IS DEPOSITED BEFORE THE COPPER IS DEPOSITED ,ATER A BARRIER LAYER IS NEEDED TO COVER THE TOP OF THE COPPER lLLED TRENCHES THE PROCESS IS DISCUSSED IN #HAPTER #URRENTLY THE MOST WIDELY USED BARRIER LAYER FOR HOLES AND TRENCHES IS A TANTALUMTANTALUM NITRIDE COMBINATION OF lLMS 4A DOES NOT REACT WITH #U AND FORMS STRONG METAL METAL BONDS SO IT IS A GOOD GLUE LAYER 4A. BLOCKS THE DIFFUSION OF CONTAMINANTS SO IT IS A GOOD BAR RIER MATERIAL 4HE TWO lLMS FORM AN ALMOST IDEAL COMPOSITE 4A AND 4A. ARE DEPOSITED USING 06$ TECHNOLOGY $EVELOPMENT WORK IS SHOWING PROMISE FOR 4A. DEPOSITION USING A NEW TECHNOLOGY CALLED ATOMIC LAYER DEPOSITION !,$ )T PRODUCES A lLM WITH EXCELLENT CONFORMALITY ALLOWING IT TO BE AS THIN AS POSSIBLE WITH MUCH LOWER RESISTANCE TO CURRENT mOW !,$ IS A METHOD OF ASSEMBLING lLMS A FEW ATOMS AT A TIME INTO LAYERS WHOSE THICKNESS MAY BE SPECIlED IN NUMBERS OF ATOMIC LAYERS 4HESE lLMS ARE OF EXCELLENT INTEGRITY AND STRUCTURE !,$ WILL BE AN INTERESTING TOPIC FOR FUTURE DISCUSSION AS IT MOVES INTO PRODUCTION 4A4A. LINER
#OPPER MUST BE ENCAPSULATED TO PREVENT OUT DIFFUSION
&IGURE $EPOSITED "ARRIER ,AYER
#OPPER &IRST ,EVEL )NTERCONNECTION 0ROCESS
3PUTTER #OPPER #U #OPPER TRENCH lLL IS A TWO STEP PROCESS 4HE OPTIMUM WAY OF DEPOSITING THE BULK OF THE MATERIAL IS ELECTROPLATING "UT THAT PRESENTS A PROBLEM %LECTROPLATING REQUIRES AN UNBROKEN lLM OF COPPER ON THE WAFER A CONDUCTING COATING IS REQUIRED FOR PLATING TO OCCUR 3O A SEED LAYER IS NEEDED 4HE SEED LAYER IS DEPOSITED ON THE WAFER USING THE FAMILIAR 06$ METHOD #AREFUL SPUTTERING WILL COAT ALL OF THE SURFACES WITH A THIN #U lLM INCLUDING THE INTERIORS OF THE SMALL TRENCHES #OPPER 3EED ,AYER
4A4A. LINER
7AFER 3URFACE
&IGURE #U 3EED ,AYER
%LECTROPLATE #OPPER #U %LECTROPLATING WAS FOUND TO WORK BETTER THAN SPUTTERING TO COMPLETELY lLL THE SMALL FEATURES ON THE WAFER 4HE WAFER WITH THE CONDUCTING SEED LAYER ACTS AS THE CATHODE IN THE ELECTROPLATING BATH #OPPER PLATES OUT ON THE SEED LAYER COVERING ALL THE SURFACES OF THE WAFER %LECTROPLATING HAS BEEN USED FOR MANY YEARS BY THE PRINTED CIRCUIT BOARD INDUSTRY TO FORM METAL WIRES AND INTERCONNECTS 4HE TECHNIQUE IS SO WELL DEVELOPED IT COULD BE INTRODUCED TO THE FAB FOR COPPER DEPOSITION AT LOW COST WITH HIGH THROUGHPUT &IGURE ILLUSTRATES THE OPERATION OF THE PLATING BATH )N PRACTICE THE WAFER IS HELD HORI ZONTALLY AND THE SOLUTION MOVES PAST IT FOR BETTER OVERALL DEPOSITION CHARACTERISTICS
#HAPTER &IRST ,EVEL -ETALLIZATION
#!4(/$% /BJECT TO BE PLATED CONNECTED TO NEGATIVE OF POWER SUPPLY
#U 3/
!./$% ! COPPER PLATE CONNECTED POSITIVE OF LOW VOLTAGE POWER SUPPLY
#U
3/
#OPPER 3ULFATE 3OLUTION
3ULFATE IONS FLOW TO ANODE COPPER ATOMS GO INTO SOLUTION AS COPPER IONS
#OPPER IONS ATTRACTED TO THE CATHODE DEPOSIT ON IT AS COPPER ATOMS
&IGURE %LECTROCHEMICAL $EPOSITION %LECTROPLATING
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&IGURE #OPPER $EPOSITED TO &ILL 4RENCHES #OPPER ALSO PLATES ON THE TOP SURFACES
#OPPER #-0 4HE EXCESS COPPER IS POLISHED OFF IN MUCH THE SAME WAY AS THE TUNGSTEN 4HIS METAL POLISH IS SOMEWHAT DIFFERENT FROM THE 7 BECAUSE THE MATERIAL CHARACTERISTICS ARE DIF FERENT #U POLISHING IS PERHAPS THE MOST DEMANDING #-0 PROCESS IN USE TODAY 4HE POLISH MUST REMOVE THE CONDUCTIVE 4A4A. LAYER UNDER THE COPPER AND STOP ON THE )-$ #ONSIDERING THAT IT CAN BE A RELATIVELY SOFT OR MECHANICALLY WEAK LOW K MATERIAL OTHER PROBLEMS MAY APPEAR FOR THE #-0 ENGINEER IN PRESERVING THE INTEGRITY OF THE lLM
#OPPER &IRST ,EVEL )NTERCONNECTION 0ROCESS #OPPER CONNECTIONS BETWEEN TUNGSTEN PLUGS
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&IGURE #OMPLETED &IRST ,EVEL -ETAL
4HE WAFERS MAY NOW PROCEED TO THE NEXT MAJOR OPERATION IN THE MANUFACTURING PROCESS MULTILEVEL METALLIZATION
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#(!04%2
-ULTILEVEL -ETAL )NTERCONNECTS AND $UAL $AMASCENE
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)NTRODUCTION )N THIS CHAPTER YOU WILL LEARN v (OW MULTILEVEL INTERCONNECTS ARE MADE v (OW THE DUAL DAMASCENE PROCESS WORKS v (OW THE lNISHED CHIP IS PROTECTED FROM THE ENVIRONMENT -ULTI ,EVEL -ETALLIZATION 0ROCESS &LOW $EPOSIT THE 3ILICON #ARBIDE 3I# "ARRIER ,AYER $EPOSIT LOW K )-$
$UAL $AMASCENE 0ROCESS A -ASK AND ETCH VIAS HARD MASK PROCESS B 2EMASK AND ETCH TRENCHES C $EPOSIT 4A4A. BARRIER LAYERS D 3PUTTER COPPER SEED LAYER E %LECTROPLATE COPPER F #-0 TO REMOVE EXCESS COPPER G "UILD ADDITIONAL LAYERS I $EPOSIT 3I# BARRIER LAYER II 2EPEAT DUAL DAMASCENE PROCESS
&ORM "ONDING 0ADS A -ETAL DEPOSITION B 0HOTOETCH FOR BONDING PADS
#HAPTER -ULTILEVEL -ETAL )NTERCONNECTS AND $UAL $AMASCENE &INAL 0ASSIVATION 0ROCESS A $EPOSIT lNAL PASSIVATION B 0HOTOETCH FOR BONDING PADS +EY 0OINTS IN THE -ULTI ,EVEL -ETALLIZATION 0ROCESS 4HE DAMASCENE PROCESS IS NECESSARY FOR COPPER TECHNOLOGY #OPPER REQUIRES THE USE OF EFFECTIVE BARRIER lLMS ,OW K DIELECTRIC MATERIALS ARE REPLACING DEPOSITED OXIDE AS THE INTERMETAL DIELECTRIC ! HARD IMPERMEABLE COATING MUST COVER THE lNISHED CHIP FOR PROTECTION FROM CONTAMINANTS %ACH OF THESE POINTS WILL BE EXPLAINED IN THE APPROPRIATE SECTIONS OF THIS CHAPTER $ISCUSSION -AKING ALL OF THE REQUIRED ELECTRICAL CONNECTIONS ON THE CHIP CANNOT BE DONE WITH ONLY ONE LAYER OF METAL hWIRESv 7ITH HUNDREDS OF MILLIONS OF TRANSISTORS AND COUNTLESS OTHER COMPONENTS ON THE CHIP THE WIRING HAS BECOME VERY COMPLEX )T IS COMMON FOR EIGHT TO TEN CRISSCROSSING LAYERS OF METAL TO BE NECESSARY FOR STATE OF THE ART CHIPS &ORTUNATELY EACH LAYER IS CONSTRUCTED IN ESSENTIALLY THE SAME WAY SO THIS CHAPTER WILL SUFlCE IN DESCRIBING THAT PROCESS "EAR IN MIND THAT THE METAL WIRES GET THICKER IN THE UPPER INTERCONNECTION LEVELS BECAUSE THEY NEED TO CARRY MORE CURRENT /RIGINALLY THERE WERE TWO APPROACHES TO CHOOSE FROM IN CONSTRUCTING THE DUAL DAMASCENE STRUCTURE /NE APPROACH USED A SILICON NITRIDE LAYER POSITIONED IN THE CENTER OF THE )-$ 4HAT LAYER WAS CALLED THE ETCH STOP AND WAS USED TO ENSURE THAT THE TRENCH ETCH STEP DID NOT PENETRATE TOO FAR INTO THE )-$ AND THAT THE TRENCH HAD A mAT BOTTOM 4HE TROUBLE WITH THAT DESIGN WAS THE HIGH K VALUE OF THE NITRIDE IT RAISED THE OVERALL K VALUE OF THE )-$ STACK REDUCING THE EFFECTIVENESS OF THE LOW K )-$ !S A RESULT THE NITRIDE ETCH STOP IS NOT OFTEN USED #ONTROL OF THE TRENCH DEPTH IS HANDLED WITH A WELL DESIGNED ETCH PROCESS 4HE DEPTH IS IMPORTANT BECAUSE IT AFFECTS THE THICKNESS AND THEREFORE THE RESISTANCE OF THE COPPER WIRE THAT IS FORMED WITHIN THE TRENCH !LSO THE TRENCH MUST BE KEPT A MINIMUM DISTANCE FROM THE UNDERLYING CONDUCTORS IN ORDER TO MINIMIZE ELECTRICAL INTERACTION 4HE CHIP DESIGNER WILL SPECIFY THE DIMENSIONAL TOLERANCE USED BY MANU FACTURING SEE #HAPTER
)NTRODUCTION 4HE lNAL PASSIVATION OF THE CHIP WILL ALSO BE DISCUSSED IN THIS CHAPTER !T THE END OF THE MANUFACTURING PROCESS THE CHIP MUST BE PROTECTED FROM ENVIRONMENTAL CONTAM INATION BEFORE IT CAN LEAVE THE CLEANROOM 4HE WAFER IS COATED WITH A TOUGH COVERING THAT SUPPLIES THE NEEDED PROTECTION "UT IF THE CHIP IS COVERED IN A TOUGH PROTECTIVE lLM HOW ARE THE ELECTRICAL CONNECTIONS ATTACHED TO IT 4HE ANSWER TO THAT QUESTION IS FOUND IN 3ECTION
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$EPOSIT "ARRIER ,AYER AND )NTERMETAL $IELECTRIC !FTER THE COPPER #-0 STEP DISCUSSED AT THE END OF #HAPTER BARE COPPER IS EXPOSED AT THE TOP OF THE TRENCHES 4O PREVENT COPPER FROM MIGRATING INTO THE LOW K DIELECTRIC LAYER THAT WILL BE DEPOSITED ON TOP OF IT A DIFFUSION BARRIER IS NEEDED 0%#6$ SILICON NITRIDE HAS BEEN USED FOR MANY YEARS AS THE BARRIER LAYER AT THIS POINT IN THE PROCESS (OWEVER IT IS AN IMPORTANT ISSUE TO KEEP THE OVERALL K VALUE FOR THE lLM STACK AS LOW AS POSSIBLE 4HE K VALUE FOR 3I. IS ABOUT FOR THIS APPLICATION 3O A CHANGE IS OFTEN MADE IN BARRIER LAYER MATERIALS ! FAMILIAR EXAMPLE OF A MATERIAL THAT IS OFTEN USED TO REPLACE SILICON NITRIDE IS SILICON CARBIDE 3I# 3I# IS USUALLY DEPOSITED USING A #6$ PROCESS 4HIS lLM IS MUCH LIKE SOME OF THE OTHER lLMS DISCUSSED EARLIER IN THE TEXT IN THAT ITS COMPOSITION MAY NOT BE VERY CLOSE TO CONVENTIONAL 3I# PRODUCED IN HIGHER TEMPERATURE REACTIONS .EVERTHELESS IT WORKS WELL AS A BARRIER LAYER AND CAN BE DEPOSITED AT THE REQUIRED LOWER TEMPERATURE 3ILICON #ARBIDE "ARRIER ,AYER
P 7ELL
N 7ELL
P 7ELL
&IGURE 3I# "ARRIER ,AYER
N 7ELL
#HAPTER -ULTILEVEL -ETAL )NTERCONNECTS AND $UAL $AMASCENE 3I# HAS A LOWER K THAN 3I. BETWEEN AND SO IT IMPROVES THE PERFORMANCE OF THE CHIP )N ADDITION IT IS AT LEAST AS GOOD A DIFFUSION BARRIER AS 3I. )T STICKS WELL TO MANY )-$S AND TO COPPER SO IT WILL NOT CAUSE THE lLM STACK TO DELAMINATE 3I.3I# BARRIER LAYER DEPOSITED BEFORE SECOND LOW K
&IGURE 3ECOND )-$ $EPOSITION
4HE SAME LOW K MATERIAL IS OFTEN USED FOR THE SECOND AND SUBSEQUENT )-$S "UT SOMETIMES IT IS ADVANTAGEOUS TO USE A DIFFERENT MATERIAL 3EE #HAPTER FOR A DISCUSSION OF THIS DEPOSITION AND LOW K )-$S
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$UAL $AMASCENE 0ROCESS )NTRODUCTION $ElNITION $UAL $AMASCENE $$ IS THE NAME OF A PROCESS FOR MAKING METAL INTER CONNECTIONS THAT IS REMINISCENT OF THE METAL INLAY TECHNIQUES USED IN THE -IDDLE %AST SINCE THE MIDDLE AGES 4HE NAME ORIGINATES IN $AMASCUS THE CAPITAL OF MODERN 3YRIA 0URPOSE 4HE DUAL DAMASCENE PROCESS IS NEEDED FOR COPPER TECHNOLOGY 6ERY lNE METAL WIRES CANNOT BE ETCHED IN COPPER AS THEY WERE IN ALUMINUM BECAUSE THERE IS NO PRACTICAL ETCH PROCESS AVAILABLE FOR COPPER ! MAJOR CONSTRAINT IS THE VOLATILITY OF THE REACTION PRODUCTS )F THE CHEMICAL REACTION IN THE ETCHER PRODUCES CHEMICALS THAT COAT THE WAFER AND BIND TO THE SURFACE RATHER THAN EVAPORATING OFF THE SURFACE THEN NEW REACTANT IS BLOCKED FROM REACHING THE lLM TO BE ETCHED 4HE ETCH STOPS WITHOUT TRANSFERRING THE DESIRED PATTERN &OR EXAMPLE CHLORINE GAS IS OFTEN USED TO ETCH METALS IN PLASMA ETCHERS IT WILL ATTACK THE COPPER BUT THE RESULTING COPPER CHLORIDE PRODUCT OF REACTION WILL NOT READILY EVAPORATE $ISCUSSION 4HE SAME APPROACH IS USED FOR DUAL DAMASCENE AS THAT DISCUSSED IN #HAPTER FOR SINGLE DAMASCENE A TRENCH IS lLLED WITH COPPER AND THE EXCESS COPPER IS POLISHED OFF WITH #-0 "UT IN THE SINGLE DAMASCENE EXAMPLE THE CONTACT HOLES WERE ALREADY lLLED WITH TUNGSTEN (OW IS THE CONNECTION TO THE LOWER METAL LAYER MADE WITH DUAL DAMASCENE 4HE ORIGIN OF THE NAME hDUALv DAMASCENE IS THE ANSWER 4WO PROCESS STEPS MUST BE PERFORMED ONE TO MAKE HOLES IN THE )-$ THE VIAS SO THAT THE COPPER CONNECTIONS
#HAPTER -ULTILEVEL -ETAL )NTERCONNECTS AND $UAL $AMASCENE TO THE UNDERLYING METAL LAYER CAN BE MADE AND A SECOND STEP TO MAKE THE TRENCH THAT WILL BE lLLED WITH COPPER 4HE NEXT SECTION BEGINS THE DISCUSSION OF THIS SEQUENCE OF STEPS 4HE TWO PHOTOETCH STEPS IN THE DUAL DAMASCENE PROCESS CAN BE PERFORMED IN ANY ORDER TRENCH lRST THEN VIA OR VIA lRST THEN TRENCH (OWEVER THE VIA lRST PROCESS IS PREFERRED BECAUSE OF PATTERNING DIFlCULTIES IN THE TRENCH lRST METHOD /THER CREATIVE SEQUENCES OF STEPS HAVE ALSO BEEN TRIED WITHOUT MUCH SUCCESS 4HE VIA lRST PROCESS WILL BE DISCUSSED HERE
6IA 0HOTO%TCH $ElNITION ! 6IA IS A HOLE MADE IN THE )-$ SIMILAR TO THE CONTACT HOLE DISCUSSED IN #HAPTER 4HE NAME WAS TAKEN FROM THE PRINTED CIRCUIT BOARD INDUSTRY WHERE A SIMILAR STRUCTURE IS USED ON 0# BOARDS 0URPOSE 4HE VIA WILL BE lLLED WITH METAL IN ORDER TO MAKE ELECTRICAL CONNECTION TO THE UNDERLYING METAL INTERCONNECT LAYER 4HE HOLE IS NOT UNLIKE THE CONTACT HOLE EXCEPT THAT THE ETCH STOPS ON COPPER RATHER THAN ON SILICON $ISCUSSION "EFORE DISCUSSING THE PARTICULARS OF VIA PHOTO AND ETCH IT SHOULD BE NOTED THAT IF THE )-$ IS AN ORGANIC MATERIAL OR ANY OTHER VULNERABLE lLM THEN A HARD MASK MUST BE USED !S EXPLAINED IN #HAPTER THE PHOTORESIST AND ORGANIC )-$S ARE VERY SIMILAR IN CHEMICAL PROPERTIES AND WILL ETCH AT SIMILAR RATES IN THE SAME ETCH ENVIRONMENT 4HAT WOULD DAMAGE OR DESTROY THE MASK BEFORE THE PATTERN WAS CORRECTLY REPRODUCED IN THE lLM 3HOULD A HARD MASK BE NEEDED A DEPOSITION STEP WOULD PRECEDE THE PHOTOETCH SEQUENCE 4YPICALLY SILICON NITRIDE WOULD BE USED AS THE MASKING MATERIAL 4HEN AN ETCH STEP TO MAKE THE HARD MASK WOULD PRECEDE THE )-$ ETCH 4HE CHALLENGE OF THE VIA lRST $$ PROCESS IS THAT THE VIA HOLES MUST BE ETCHED THROUGH A VERY THICK )-$ lLM .OT ONLY DOES THE THICKNESS OF THE )-$ UNDERNEATH THE COPPER INTERCONNECTS NEED TO BE LARGE ENOUGH TO SUFlCIENTLY INSULATE THE STACKED LAYERS OF CONDUCTOR THE THICKNESS OF THE METAL CONTAINED IN THE TRENCH IS ADDED TO THE )-$ THICKNESS 4HE RESULT IS A VERY HIGH ASPECT RATIO HOLE 4HE PHOTOETCH PROCESS IS MUCH LIKE THE CONTACT RECIPE FOR INORGANIC )-$ MATERI ALS /RGANICS REQUIRE MUCH DIFFERENT ETCH RECIPES AND WILL OFTEN INCLUDE OXYGEN AS ONE
$UAL $AMASCENE 0ROCESS OF THE COMPONENTS 4HE HARD MASK MATERIAL USED FOR THE ORGANICS IS OFTEN 3I. OR AN OXIDE SO THE FAMILIAR mUORINE CHEMISTRY WILL PRODUCE THE HARD MASK 4HE ETCH CHEMISTRY WILL DIFFER SOMEWHAT FROM CONTACT ETCH BECAUSE OF THE DIFFER ENT UNDERLYING MATERIAL AND THE SOMETIMES HIGHER ASPECT RATIO )N ADDITION THERE ARE SO MANY CHOICES FOR LOW K )-$S THAT THE ETCH CHEMISTRY CAN POTENTIALLY BE VERY DIFFERENT )T MUST NOT BE OVERLOOKED THAT THE 3I# BARRIER LAYER COVERING THE COPPER AT THE BOTTOM OF THE VIA MUST ALSO BE REMOVED 4HE ELECTRICAL CONNECTION BETWEEN COPPER LAYERS WOULD BE POOR OR NONEXISTENT IF THIS lLM WERE LEFT IN PLACE
&IGURE (!2 6IA #ROSS 3ECTION &IGURE (!2 VIA #ROSS 3ECTION
4RENCH 0HOTO%TCH 4HIS OPERATION IS A DUPLICATE OF THE ONE DESCRIBED IN #HAPTER 4HE WAFER RETURNS TO PHOTO IS AGAIN COATED WITH RESIST EXPOSED AND DEVELOPED TO PRODUCE THE TRENCH PATTERN .OTICE THAT THE VIAS ARE PRESENT ON THE WAFER )T IS DELIBERATE THAT THEY lLL PARTIALLY WITH PHOTORESIST 4HE RESIST hPLUGv PROTECTS THE UNDERLYING lLM FROM POSSIBLE EROSION OR DAMAGE DURING THE TRENCH ETCH 4HE RESIST IN THE VIAS IS REMOVED DURING THE POST ETCH CLEAN
#HAPTER -ULTILEVEL -ETAL )NTERCONNECTS AND $UAL $AMASCENE
&IGURE $$ VIA 4RENCH &ORMATION
$EPOSIT "ARRIER ,AYERS 4HE TANTALUM AND TANTALUM NITRIDE BARRIER STACK IS THE STANDARD FOR LINING THE VIAS AND TRENCHES !T THIS POINT IT CAN BE SEEN THAT THE TRENCHES AND VIAS ARE COMPLETELY COATED WITH BARRIER MATERIALS .OTE THAT THESE LAYERS ARE DEPICTED IN THE ENLARGED VIEW OF &IGURE 4A4A. WILL SEPARATE THE #U FROM THE )-$ 3I# COVERS THE TOP OF THE UNDERLYING COPPER AND WILL BE DEPOSITED ON TOP OF THIS LAYER OF COPPER SHORTLY
3PUTTER #OPPER 4HE SEED LAYER OF #U IS SPUTTERED EXACTLY AS DESCRIBED IN #HAPTER
%LECTROPLATE #OPPER 4HE SAME ELECTROPLATING PROCESS DESCRIBED IN #HAPTER IS USED HERE
$UAL $AMASCENE 0ROCESS
&IGURE "ULK #OPPER $EPOSITION !DDITIONAL DETAIL SHOWN IN &IGURE
#-0 TO 2EMOVE %XCESS #OPPER 4HIS COPPER POLISH IS THE SAME AS PERFORMED IN #HAPTER 4HE POLISH STOPS ON THE )-$ 2EMEMBER THAT THE 4A4A. BARRIER LAYER UNDER THE COPPER MUST BE POLISHED OFF THE TOP OF THE )-$ SO THAT ALL OF THE #U INTERCONNECTS ARE NOT SHORTED TOGETHER
&IGURE #OMPLETED $$ !DDITIONAL DETAIL SHOWN IN &IGURE
#HAPTER -ULTILEVEL -ETAL )NTERCONNECTS AND $UAL $AMASCENE
$EPOSIT 3I# "ARRIER ,AYER 4HE TOP SEAL ON THE COPPER IS DONE WITH SILICON CARBIDE AS BEFORE
3I. ETCH STOP OFTEN USED
3I.3I# BARRIER LAYERS
4A4A. LINER
#OPPER MUST BE ENCAPSULATED TO PREVENT OUT DIFFUSION
&IGURE #OMPLETED $$ WITH 3I# "ARRIER ,AYER
"UILD !DDITIONAL ,AYERS 4HE CREATION OF MULTIPLE METAL LAYERS IS SIMPLY A REPEAT OF THE PREVIOUS STEPS
&IGURE -ULTIPLE -ETAL ,AYERS #ROSS 3ECTION )"-
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&ORM "ONDING 0ADS $ElNITION "ONDING 0ADS ARE LARGE PADS OF METAL THAT ARE THE END CONNECTION OF ALL THE CHIP CIRCUITRY 0URPOSE 4HE METAL WIRES FROM THE CHIP PACKAGE ARE ATTACHED TO THE BONDING PADS 4HE PADS ARE TYPICALLY ¾ MICRONS SO THEY ARE VERY LARGE COMPARED TO MOST OF THE OTHER FEATURES CREATED ON THE CHIP $ISCUSSION 4HE BONDING PADS ARE GENERALLY MADE OF ALUMINUM OR COPPER AND SOMETIMES ALUMI NUM DEPOSITED ON TOP OF COPPER "ONDING TO THE ALUMINUM PADS USING THE STANDARD GOLD OR ALUMINUM WIRES FROM THE CHIP PACKAGE WORKS VERY WELL 7IRE BONDING IS DISCUSSED IN THE NEXT CHAPTER
&IGURE 4YPICAL "ONDING 0ADS 3EMICONDUCTOR 0ICTURE $ICTIONARY
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&INAL 0ASSIVATION 0ROCESS $EPOSIT &INAL 0ASSIVATION 4HE lNAL PROTECTIVE PASSIVATION lLM IS COMMONLY A STACK OF TWO lLMS ! LAYER OF 03' IS PUT DOWN lRST FOLLOWED BY SILICON NITRIDE (ISTORICALLY EITHER OF THOSE lLMS HAVE BEEN USED INDEPENDENTLY BUT THE TREND HAS BEEN TO COMBINE THE STRENGTHS OF BOTH BY SIMPLY STACKING THEM UP NITRIDE ON TOP OF 03' 4HE 03' lLM ACTS SOMETHING LIKE THE PAD OXIDE SEEN IN #HAPTER 4HE EXPANSION AND CONTRACTION OF THE CHIP CANNOT BE ALLOWED TO CRACK THE HARD NITRIDE LAYER SO THE OXIDE RELIEVES THE STRESS 3I. IS DEPOSITED ON TOP OF THE 03' )T IS A GOOD SCRATCH PROTECTOR AS WELL AS A TOUGH BARRIER TO CONTAMINANTS LIKE SODIUM AND OTHER ALKALI IONS 3ILICON OXYNITRIDE IS SOMETIMES USED AS THE lNAL PASSIVANT )T IS A lLM WITH A mEX IBLE COMPOSITION SOMEWHERE BETWEEN OXIDE AND NITRIDE
0HOTO%TCH FOR "ONDING 0ADS 4HE BONDING PAD PATTERN IS ESPECIALLY IMPORTANT BECAUSE THE PASSIVATING lLM MUST ONLY BE REMOVED FROM THE TOP CENTRAL PORTION OF THE PAD WHILE EXCLUDING THE PAD EDGES 4HE PASSIVATION MUST OVERLAP THE EDGES OF THE PADS IN ORDER TO MAINTAIN THE PROTECTIVE SEAL THAT PROTECTS THE CHIP %NVIRONMENTAL CONTAMINANTS WILL DRASTICALLY REDUCE THE USEFUL LIFE OF A CHIP
#HAPTER -ULTILEVEL -ETAL )NTERCONNECTS AND $UAL $AMASCENE
&IGURE "ONDING 0AD /PENINGS 3EMICONDUCTOR 0ICTURE $ICTIONARY
4HE WAFERS ARE READY FOR THE LAST SEQUENCE OF STEPS LEADING TO COMPLETION 4EST !SSEMBLY
#(!04%2
4EST AND !SSEMBLY
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)NTRODUCTION )N THIS CHAPTER YOU WILL LEARN v 4HE WAYS IN WHICH WAFERS AND CHIPS ARE TESTED v (OW THE CHIPS ARE PACKAGED v 7HY DIFFERENT TYPES OF PACKAGING MATERIAL ARE USED #HAPTER INTRODUCED THE hBACK ENDv PROCESSING TOPICS THAT ARE EXPANDED IN THIS CHAPTER 4ESTING AND PACKAGING lNISH OFF THE JOB OF MAKING THE END PRODUCT A RELIABLE USEFUL ELECTRONIC COMPONENT 4EST AND !SSEMBLY IS A VERY LARGE SEGMENT OF THE INDUSTRY BUT A DETAILED DISCUS SION IS BEYOND THE SCOPE OF THIS BOOK 4HE READER IS INVITED TO ENJOY A MORE THOROUGH TREATMENT OF THIS TOPIC IN SEVERAL OF THE WORKS REFERENCED IN THE "IBLIOGRAPHY
&IGURE 0ACKAGED #HIPS ,ID REMOVED FROM LARGE PIN GRID ARRAY )NTEL 0ENTIUM TO SHOW DIE INSIDE
#HAPTER 4EST AND !SSEMBLY 4ERMINOLOGY 2EMINDER (ERE IS ANOTHER INSTANCE OF TERMINOLOGY THAT MAY BE CONFUSING BECAUSE OF A LACK OF CONSISTENCY FROM FAB TO FAB !S MENTIONED IN #HAPTER THE TERM hBACK END OF LINE v OR "%/, IS SOMETIMES USED TO REFER TO THE FAB OPERA TIONS THAT BEGIN WITH lRST METAL 4HAT DISTINCTION IS BECOMING MORE COMMON TODAY SINCE THE USE OF COPPER HAS FORCED SUCH A DISTINCT BREAK IN PROCESSING PROCEDURES WHEN IT COMES TIME TO DEPOSIT THE COPPER (OWEVER THE TEST AND ASSEMBLY PART OF CHIPMAKING HAS BEEN CALLED THE BACK END FOR MOST OF ITS HISTORY SO THAT TERMINOLOGY WILL CONTINUE TO BE USED HERE !NOTHER TERMINOLOGY CONFUSION RESULTS FROM THE DIFFERING TESTS THAT ARE DONE TO THE LARGE VARIETY OF DEVICE TYPES MANUFACTURED IN THE INDUSTRY 3OME MANUFAC TURING LINES WILL LUMP OPERATIONS TOGETHER AT LEAST AS FAR AS TERMINOLOGY GOES IF NOT IN ACTUAL PROCEDURES !N EXAMPLE OF A TERM WITH VARIABLE MEANING IS hE TEST v WHICH WILL BE DISCUSSED SHORTLY % TEST IS OFTEN A NICKNAME FOR hELECTRI CAL TESTv 3OME COMPANIES PERFORM THE OPERATION THAT THEY CALL E TEST AS PART OF WAFER SORT PROBE 3OME USE THE TERM TO REFERENCE ONLY PARAMETRIC TESTING STILL OTHERS USE IT TO DESCRIBE BOTH PARAMETRIC TEST AND WAFER SORT 3OME COMPANIES DO NOT USE THE TERM AT ALL 3O BE PREPARED FOR THE NEED FOR CLARIlCATION 4HIS DISCUSSION WILL USE THE STANDARDIZED TEXTBOOK TERMINOLOGY
7HY PERFORM THE EXTENSIVE TESTING THAT IS DESCRIBED IN THE NEXT SECTION )N LIGHT OF ALL THE RIGOROUS CHECKS AND SOPHISTICATED PROCEDURES EMPLOYED IN THE MANUFACTURING PROCESS IS CHIP RELIABILITY AND LONGEVITY AN ISSUE 4HE ANSWER TO THAT QUESTION IS AN EMPHATIC hYESv )T IS HOPED THAT THE READER HAS BY NOW SOME APPRECIATION OF THE DIFlCULTY OF MAKING THESE DEVICES WITH THEIR UNIMAGINABLY TINY COMPONENTS 4HE PROBABILITY FOR IMPERFECTIONS IS HIGH #ONSIDERING THE CRITICAL FUNCTIONS PERFORMED TODAY BY MANY CHIPS UNRELIABLE PRODUCTS WOULD TOO OFTEN RISK LIVES )N ADDITION COMPUTERS ARE INDISPENSABLE TO lNANCIAL INSTITUTIONS COM MERCE AND INDUSTRY THE COST TO BUSINESSES OF POOR QUALITY CHIPS WOULD BE ENORMOUS -ILITARY APPLICATIONS OF SEMICONDUCTOR DEVICES EXPAND THE NECESSITY OF RELIABILITY 4HE SO CALLED MIL SPEC REQUIRES ELECTRONIC COMPONENTS PURCHASED BY THE MILITARY TO TOLERATE THE MOST EXTREME CONDITIONS IMAGINABLE 3OME CHIPS MUST CONTINUE TO FUNCTION EVEN AFTER EXPOSURE TO THE ELECTROMAGNETIC BURST RADIATION FROM AN ATOMIC EXPLOSION 4HE TESTING PROCESS IS IMPORTANT FOR ANOTHER REASON )T PROVIDES CRITICAL FEEDBACK INFORMATION TO THE MANUFACTURING ENGINEERS AND THE DESIGN ENGINEERS ABOUT THE QUAL ITY OF THEIR WORK -ANY DETAILS ABOUT THE PROCESS OF DESIGNING AND MAKING CHIPS ARE IMPROVED BASED UPON TEST DATA )NDEED AN IDEA MAY LOOK GOOD ON PAPER AND SEEM TO BE EASY TO MANUFACTURER BUT IF THE CHIPS DONT WORK ITS ALL FOR NAUGHT
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7AFER AND #HIP 4ESTING 7AFER AND $IE 4ESTS )N LINE 0ARAMETRIC 7AFER 3ORT &INAL &UNCTIONAL
)N LINE 0ARAMETRIC 4EST %ACH STAGE IN THE MANUFACTURING PROCESS INCLUDES MEASUREMENTS AND TESTS 4HIS MONI TORING IS DONE USING PRODUCT WAFERS AND ALSO THROUGH THE USE OF SPECIALLY PREPARED MONITORS CALLED BY VARIOUS NAMES SUCH AS PILOT WAFERS TEST WAFERS OR MONITOR WAFERS 4HESE CHECKS MUST BE DONE TO ENSURE THAT THE DESIGN SPECIlCATIONS ARE CORRECTLY FOL LOWED AND THAT THE MANUFACTURING TOOLS ARE PERFORMING PROPERLY 4HE TERM hPARAMETRICv REFERS TO THE hPARAMETERSv THAT ARE MEASURED DURING THE TESTING PROCESS 0ARAMETERS ARE THE MEASURABLE OR QUANTIlABLE CHARACTERISTICS THAT ARE SPECIlED BY THE DESIGN ENGINEERS )N LINE TESTING MAY INCLUDE A VITALLY IMPORTANT SET OF ELECTRICAL MEASUREMENTS OFTEN CALLED E TEST THAT ARE MADE BEFORE THE WAFERS ARE SENT ON TO WAFER PROBE $OZ ENS OF BASIC MEASUREMENTS ARE MADE ON INDIVIDUAL TRANSISTORS AND OTHER TEST STRUCTURES IN TEST PATTERNS DESIGNED INTO THE hSCRIBE LINES v THE SPACES BETWEEN THE CHIPS 3OME SIMPLE EXAMPLES OF THE TESTS MADE ARE 'ATE OXIDE BREAKDOWN VOLTAGE PN JUNCTION BREAKDOWN VOLTAGES
#HAPTER 4EST AND !SSEMBLY 4RANSISTOR THRESHOLD VOLTAGES #ONTACT RESISTANCES METAL TO SILICON 'ATE LINE RESISTANCE 4HE RESULTS OF THIS TEST ARE VERY IMPORTANT IN ENSURING THAT THE WAFERS ARE BEING PROCESSED CORRECTLY AND IN PROVIDING FEEDBACK TO THE FAB ENGINEERS OF THE NEED FOR ANY ADJUSTMENTS )F THE PARAMETERS MEASURED AT THIS POINT ON A WAFER DO NOT MEET SPECIlCATIONS THAT WAFER WILL BE REJECTED TO AVOID THE SUBSTANTIAL TIME AND COST OF THE FUNCTIONAL TEST IN WAFER SORT 3UCH WAFERS MAY RECEIVE EXTENSIVE FAILURE ANALYSIS TO lND THE SOURCE OF THE PROBLEMS
7AFER 3ORT 0ROBE 7AFER SORT OR PROBE IS A FUNCTIONAL TEST THAT IS DONE TO EVERY DIE ON THE WAFER AT THE END OF THE MANUFACTURING PROCESS WHILE THE WAFER IS STILL INTACT %ACH DIE IS TESTED WITH A PROBE THAT HAS MANY TINY ELECTRODES ! COMPUTERIZED SYSTEM PERFORMS THE TESTS ON THE CHIP AND COLLECTS STATISTICAL DATA ON THE PRODUCT 4HE TEST SYSTEM KEEPS A MAP OF PASSED AND FAILED DIE ON EVERY WAFER &AILED DIE ARE IDENTIlED IN A COMPUTER MAP OR MARKED WITH AN INK DOT THEY ARE SAID TO BE hINKED OUTv !FTER THE WAFERS ARE SEPARATED INTO INDIVIDUAL CHIPS A SPECIAL TOOL LIFTS OFF THE GOOD DIE AND PLACES THEM IN CHIP PACKAGES &AILED DIE ARE IGNORED BY THE TOOL
&IGURE 0ROBE #ARD OR 7AFER "EING 0ROBED
7AFER AND #HIP 4ESTING ! FAMILIAR TERM RELATED TO PROBE IS hSORT YIELDv 3ORT YIELD IS SIMPLY THE RATIO OF THE NUMBER OF FUNCTIONAL DIE TO THE TOTAL POSSIBLE NUMBER OF DIE 4HIS YIELD lGURE HAS ENORMOUS IMPACT ON A COMPANY BECAUSE IT DIRECTLY EVALUATES THE EFFECTIVENESS OF ITS MANUFACTURING LINE )T IS POSSIBLE FOR A MATURE PRODUCT COMING FROM A TOP QUALITY MANUFACTURING LINE TO SEE SORT YIELDS IN EXCESS OF (OWEVER SOME PRODUCTS ARE SIMPLY TOO DIFlCULT TO MANUFACTURE AND NEVER GET ANYWHERE NEAR THAT lGURE (ISTORICAL #HANGE IN 3ORT 9IELD !S RECENTLY AS TWENTY YEARS AGO IT WAS POSSIBLE FOR A NEW PRODUCT INTRODUCED TO THE MANUFACTURING LINE lRST SILICON TO HAVE A SORT YIELD OF ZERO IN THE lRST MANUFACTURING ATTEMPT /F COURSE IT DIDNT ALWAYS HAPPEN BUT IT WAS STILL EXPENSIVE AND RISKY TO INTRODUCE NEW PRODUCTS IN THOSE DAYS 4IMES ARE SOMEWHAT BETTER TODAY )T IS COMMON TO SEE OR BETTER SORT YIELD FOR lRST SILICON -ANUFACTURING PRACTICES HAVE BECOME STANDARDIZED YIELD MANAGEMENT PROCEDURES ESTABLISHED AND DESIGN RULES ADJUSTED TO MATCH THE ABILITY OF MANUFACTURING TO PRODUCE A WORKING lNISHED PRODUCT (OWEVER NEW UNTESTED TECHNOLOGY CARRIES THE SAME RISK AS EVER AND CERTAINLY COSTS A LOT MORE )T MAY TAKE THREE TO lVE YEARS OF DEVELOPMENT BEFORE TEST CHIPS INDICATE THAT IT IS POSSIBLE TO ATTEMPT lRST SILICON
&INAL &UNCTIONAL 4EST &INAL FUNCTIONAL TESTING IS ACCOMPLISHED AFTER THE CHIPS ARE PACKAGED 4HE NEXT SECTION DISCUSSES THE PROCESS OF CHANGING THE WAFERS INTO INDIVIDUAL ELECTRONIC COMPONENT PARTS )T WILL BE CLEAR FROM THAT DISCUSSION THAT SEVERAL ADDITIONAL POTENTIAL SOURCES OF DAMAGE ARE ADDED DURING ASSEMBLY AND PACKAGING )N ADDITION SOME TESTS CANNOT BE DONE UNTIL THE CHIP IS PACKAGED NOTABLY HIGH SPEED TESTING 3O lNAL FUNCTIONAL TESTING IS ESSENTIAL TO ENSURE THAT THE PRODUCT THAT IS SHIPPED TO THE CUSTOMER IS INDEED FUNC TIONAL AND RELIABLE 3OME TYPES OF ELECTRONIC COMPONENTS ARE BOTH ELECTRICALLY AND THERMALLY STRESSED BEFORE TESTING 4HIS PROCESS IS CALLED BURN IN AND IS USED TO ELIMINATE MARGINAL PARTS THAT MADE IT UP TO THIS POINT 4HE CHIPS ARE PLUGGED INTO SPECIAL SOCKETS THAT MOUNT IN OVENS 4HE ELECTRICAL AND THERMAL CYCLING CAN GO ON FOR DAYS OR WEEKS 4HIS OPERATION FORCES ANY WEAK CHIPS TO FAIL /F COURSE NOT ALL TYPES OF CHIPS REQUIRE BURN IN 4HE lNAL TESTING REGIMEN IS DESIGNED TO ENSURE THAT THE lNISHED PRODUCT MEETS THE PRODUCT SPECIlCATIONS )T WILL ALSO WEED OUT ANY CHIPS THAT WERE DAMAGED DURING THE PACKAGING OPERATION
#HAPTER 4EST AND !SSEMBLY -ANY CHIPS ARE DESIGNED WITH REDUNDANCY IN THE MEMORY ARRAYS 4HIS CLEVER SCHEME ALLOWS THE MANUFACTURER TO BLOW FUSES AT lNAL TEST TO REMOVE DAMAGED OR IMPERFECT SECTIONS FROM THE CIRCUIT THE FUSE REROUTES THE CIRCUIT AND BYPASSES THE BAD SECTIONS 4HE CHIP IS STILL FULLY FUNCTIONAL AND CAN BE SOLD FOR A GOOD PRICE (OWEVER THE HIGHEST PRICE STILL GOES TO THE PERFECT CHIP THAT TESTS OUT WITH THE FASTEST SPEED 4HE CATEGORIZING OF THE CHIPS IS A PROCESS CALLED BINNING 4HERE IS A hBIN v OR CATEGORY FOR PERFECT PARTS AND ANOTHER FOR REPAIRED PARTS EVEN NONFUNCTIONAL PARTS HAVE A BIN DEPENDING ON THE TYPE OF FAILURE FOUND DURING TESTING 4HE lNAL TEST PROCESS ASSIGNS ALL OF THE CHIPS TO THE APPROPRIATE BIN
3%#4)/.
!SSEMBLY AND 0ACKAGING "ACK %ND 0ROCESS &LOW $IE SEPARATION $IE ATTACH AND BOND PAD CONNECTION %NCAPSULATION %LECTRICAL TESTING 0ACK AND SHIP
$IE 3EPARATION !FTER THE WAFERS ARE PROBED AND LEAVE THE FAB ANOTHER OPERATION IS COMMONLY PER FORMED THAT GRINDS THE BACKS OF THE WAFERS CALLED NOT SURPRISINGLY BACK GRINDING OR BACK LAPPING )T THINS THE SILICON SUBSTRATE WHICH HELPS TO KEEP THE lNAL PACKAGE AS SMALL AS POSSIBLE AND IS OFTEN IMPORTANT IN MAXIMIZING HEAT CONDUCTION OUT OF THE CHIP &OLLOWING BACK GRINDING THE WAFERS ARE MOUNTED ON SPECIAL ADHESIVE SHEETS OF PLASTIC HELD IN A FRAME 4HE FRAME lTS INTO A SPECIAL MACHINE THAT WILL SAW THE INDIVID UAL DIE CHIPS APART 2ECALL THAT THE CHIPS ARE SEPARATED BY A SPACE CALLED THE SCRIBE LINE OR STREET 4HE DIE SEPARATION IS DIMENSIONALLY MATCHED TO THE SAW DICING TOOL SO THE SAW BLADE WILL NOT DAMAGE THE PARTS 4HE DICING SAW USES A DIAMOND IMPREGNATED BLADE THAT SPINS AT ABOUT RPM 4HE ENTIRE PROCESS REQUIRES PRECISE ALIGNMENT OF THE SAW BLADE AND INVOLVES MANY OTHER STEPS 4HE BLADE PENETRATES THE WAFER BUT DOES NOT CUT THROUGH THE PLASTIC 7HEN THE DICING IS COMPLETED THE ADHESIVE ON THE PLASTIC HOLDS ALL OF THE INDIVIDUAL DIE IN PLACE TO MAKE IT EASIER TO PUT THEM INTO THEIR INDIVIDUAL PACKAGES
#HAPTER 4EST AND !SSEMBLY
&IGURE $ICING 3AW 3%-)
$IE !TTACH AND "OND 0AD #ONNECTION 4HE DIE ARE READY TO BE MOUNTED ON THE SUBSTRATE PORTION OF THE PACKAGE 4HIS OPERA TION IS CALLED DIE ATTACH OR DIE BONDING ! SPECIAL MACHINE LIFTS EACH DIE FROM THE PLASTIC USING A VACUUM HANDLING ARM AND PLACES IT ON THE PACKAGE SUBSTRATE PICK AND PLACE 4HIS IS THE MACHINE MENTIONED EARLIER THAT IGNORES THE BAD DIE 4HE CHIP IS ATTACHED TO THE PACKAGE WHICH HAS BEEN PREPARED WITH ADHESIVE OFTEN EPOXY BUT SOMETIMES OTHER ATTACHMENTS LIKE A SPECIAL SOLDER OF GOLD GERMANIUM ALLOY IS USED
&IGURE $UAL IN ,INE 0ACKAGE 3%-)
!SSEMBLY AND 0ACKAGING 4HE DUAL IN LINE PACKAGE IS THE MOST COMMON PACKAGE TYPE AND CONTAINS A LEAD FRAME TO WHICH THE CHIP IS ATTACHED 4HE LEAD FRAME IS A MOUNTING THAT HAS THE APPROPRIATE NUMBER AND CONlGURATION OF WIRES CALLED hLEADS v TO ATTACH TO OTHER ELEC TRICAL DEVICES CIRCUIT BOARDS AND THE LIKE -AKING THE ELECTRICAL CONNECTIONS BETWEEN THE BONDING PADS ON THE CHIP AND THE LEADS ON THE PACKAGE IS DONE IN SEVERAL DIFFERENT WAYS 4HE MOST FAMILIAR IS THE WIRE BONDING METHOD WHERE TINY GOLD OR ALUMINUM WIRES ARE ATTACHED TO THE BONDING PADS AND TO CONNECTION POINTS ON THE LEADS 2ECALL THAT THE BONDING PADS ARE VERY SMALL REGARDLESS OF THE FACT THAT THEY ARE THE LARGEST FEATURES THAT ARE FOUND ON THE CHIP 4HE GOLD WIRE IS ATTACHED USING THERMOCOMPRESSION ULTRASONIC OR THERMOSONIC TECHNIQUES !LUMINUM IS ATTACHED WITH THE ULTRASONIC TECHNIQUE &OR EXAMPLE THE GOLD WIRE IS THREADED THROUGH A TUNGSTEN CARBIDE CAPILLARY 4HE WIRE EXTENDING PAST THE END OF THE CAPILLARY IS EXPOSED TO A HYDROGEN mAME AND MELTED INTO A BALL 4HE BALL IS THEN PRESSED ONTO THE BOND PAD WHILE ULTRASONICALLY EXCITING BOTH THE WIRE AND THE PAD HEATING BOTH TO ABOUT # AND FORMING THE BOND THERMOCOMPRES SION BONDING 4HE CAPILLARY THEN LOOPS THE WIRE TO THE ATTACHMENT POINT ON THE LEAD 4HE WIRE IS PRESSED AGAINST THE CONTACT POINT WHILE EXCITING THE WIRE WITH ULTRASONICS FORMING A WEDGE BOND 4HE WIRE IS EASILY BROKEN OFF AT THE WEDGE BOND AND THE CAPIL LARY MOVES TO THE NEXT PAD TO CONTINUE THE PROCESS
(YDROGEN FLAME
4UNGSTEN CARBIDE CAPILLARY !L
!U WIRE 7IRE n !U ONLY 3UBSTRATE #
A
$IE
$IE B
C
"OND
$IE D
&IGURE 4HERMOCOMPRESSION "ALL7EDGE "ONDING OF 'OLD 7IRE 'HANDHI
7IRE BONDING IS FULLY AUTOMATED AND THE SPEED OF THE TOOL IS INCREDIBLE 4HE CON NECTIONS ARE DONE FASTER THAN THE EYE CAN SEE 3OME CHIP TYPES ARE CONlGURED SUCH THAT WIRE BONDING IS IMPRACTICAL OR IMPOS SIBLE 4HERE IS ALSO THE CASE OF CERTAIN HIGH PIN COUNT CHIPS THAT MAKE WIRE BONDING DIFlCULT /NE ALTERNATIVE IS THE TAPE AUTOMATED BONDING 4!" METHOD 4!" REQUIRES THE FABRICATION OF SOLDER BUMPS ON THE BOND PADS A PROCESS REQUIRING SEVERAL STEPS
#HAPTER 4EST AND !SSEMBLY THAT IS DONE BEFORE DICING )N ADDITION THE TAPE UNDERGOES FABRICATION TO PRODUCE THE METAL LINES WIRES THAT MATCH THE BOND PAD PATTERN ON THE CHIP 4HEN PRIOR TO DIE AT TACH THE CHIP IS BONDED TO THE TAPE USING THERMOCOMPRESSION .EXT INSTEAD OF USING A SEPARATE DIE ATTACH STEP THE ENTIRE CHIP IS ENCAPSULATED !CTUALLY A LARGE GROUP OF CHIPS ARE ENCAPSULATED WHILE STILL ON A CONTINUOUS STRIP OF TAPE !FTER PACKAGING THEY ARE CUT APART &LIP CHIP BONDING IS ANOTHER METHOD THAT REQUIRES THE PRODUCTION OF SOLDER BUMPS 4HE SOLDER BUMPS USED FOR THIS APPLICATION ARE MADE OF A METAL ALLOY WITH A MELT ING POINT THAT BEST lTS THE PROCESS REQUIREMENTS 4HE ENTIRE CHIP CAN BE COVERED WITH BONDING PADS RATHER THAN THE RESTRICTION OF SOME TYPES OF PROCESSES THAT ONLY ALLOW PADS ALONG THE EDGES OF THE CHIP 4HE DEVICE IS SOLDERED DIRECTLY TO THE PACKAGE SUB STRATE
%NCAPSULATION %NCAPSULATION IS THE PROCESS OF PLACING CHIPS IN PROTECTIVE PACKAGES -ANY PACKAGES ARE AVAILABLE FOR CHIPS 4HE INTENDED USE OF THE PART IS KEY IN DECIDING HOW TO ENCAP SULATE IT -ILITARY HARDWARE WILL BE EXPOSED TO HARSH ENVIRONMENTS SO TOUGH PACKAGING MATERIALS ARE USED 3IMPLE PLASTIC PACKAGES SUCH AS THE DUAL IN LINE PACKAGE SUFlCE FOR MANY CHIPS -ETAL CERAMIC PLASTIC AND COMPOSITE PACKAGING MATERIALS ARE ALL WIDELY USED 4HE PACKAGING MATERIAL IS MATCHED TO THE CHIP FUNCTION )F NECESSARY THE PACKAGE DISSIPATES EXCESS HEAT TO SOME EXTENT BUT SOME PACKAGES MUST BE PLACED IN CONTACT WITH AN ADDITIONAL LARGE HEAT SINK SOME MICROPROCESSORS EVEN NEED A BUILT IN FAN 4HE PACKAGE MUST PROTECT THE CHIP FROM MOISTURE DUST AND OTHER ENVIRONMENTAL CONTAMINANTS 3OME PACKAGES ARE DESIGNED TO BLOCK RADIATION OF CERTAIN TYPES AND THE PACKAGE CAN AFFECT THE ELECTRICAL PROPERTIES OF THE CHIP SO COMPATIBILITY IS NECESSARY %NCAPSULATION IS A PROCESS THAT VARIES ENORMOUSLY WITH THE PACKAGE TYPE #ERAMIC PACKAGES ARE PROCESSED QUITE DIFFERENTLY FROM PLASTIC PACKAGES WHICH ARE DIFFERENT FROM COMPOSITE PACKAGES 4HE READER IS INVITED TO REFER TO THE BIBLIOGRAPHY FOR SUG GESTIONS FOR FURTHER READING ON THESE PROCESSES .OW THAT lNAL FUNCTIONAL TESTING AND PACKAGING IS COMPLETE THE PACKAGES ARE LABELED 4HE PARTS ARE THEN PACKED IN SHIPPING CONTAINERS AND SENT TO STORES OR CUSTOM ERS 4HE ENTIRE CHIPMAKING PROCESS IS NOW COMPLETE
!00%.$)8
! 3CIENCE /VERVIEW
This Page Intentionally Left Blank
)NTRODUCTION 4HE SEMICONDUCTOR MANUFACTURING INDUSTRY IS INTERDISCIPLINARY IN THE EXTREME 0RIN CIPLES OF PHYSICS CHEMISTRY MATERIALS SCIENCE ELECTRICAL ENGINEERING MECHANICAL ENGINEERING AND OTHER DISCIPLINES ARE ALL AN INTEGRATED PART OF THE JOB OF MAKING CHIPS $URING THE MANY YEARS THAT WE THE AUTHORS HAVE TAUGHT SEMINARS TO SEMICONDUC TOR PROFESSIONALS WE HAVE LEARNED THAT THE SCIENTIlC BACKGROUND KNOWLEDGE OF OUR STUDENTS HAS VARIED WIDELY )T HAS BEEN A CHALLENGE TO OFFER COURSES THAT ARE APPEAL ING TO THE GENERAL AUDIENCE WHILE MAINTAINING A QUALITY OF CONTENT THAT EXPANDS THE STUDENTS HORIZONS )T HAS BEEN ESSENTIAL TO INCLUDE A SCIENCE OVERVIEW TO PUT EVERYONE ON THE SAME PAGE SO TO SPEAK WHERE SCIENCE VOCABULARY AND SCIENCE PRINCIPLES ARE CONCERNED )N THIS APPENDIX YOU WILL lND ALL OF THE ESSENTIAL SCIENTIlC CONCEPTS THAT ARE NEEDED TO UNDERSTAND THE DISCUSSION FOUND IN THE TEXT /F COURSE MANY READERS ARE NOT IN NEED OF ALL THE SECTIONS OF THIS TUTORIAL &EEL FREE TO REVIEW ONLY THE MATERIAL THAT IS NEW AND INFORMATIVE TO YOU 4HIS APPENDIX INCLUDES RELEVANT DISCUSSIONS OF v !TOMIC 4HEORY ATOMS MOLECULES IONS STATES OF MATTER v #HEMICAL PRINCIPLES FOR SEMICONDUCTOR MANUFACTURING v 3OME CHARACTERISTICS OF SOLIDS v 3OME USEFUL CONCEPTS ABOUT ELECTRICITY )NTEGRATED CIRCUITS ARE VERY SMALL )N FACT THE COMPONENT PARTS OF THESE ELECTRI CAL DEVICES ARE ALMOST AS SMALL AS IT IS POSSIBLE TO MAKE THEM AND STILL USE EXISTING TECHNOLOGY WHICH DEALS WITH BULK MATERIALS
!PPENDIX ! 3CIENCE /VERVIEW 7ITH THESE FACTS IN MIND IT SEEMS LIKE A HELPFUL IDEA FOR US TO BEGIN OUR DISCUSSION OF CHIPMAKING WITH A REVIEW OF SOME OF THE PRINCIPLES THAT MAKE IT ALL POSSIBLE
3%#4)/.
!TOMS AND -OLECULES 4HE !TOM 7HAT )S !N !TOM !N ATOM IS THE SMALLEST UNIT OF AN ELEMENT )T IS MADE UP OF ELECTRONS THAT SURROUND A NUCLEUS MADE OF PROTONS AND NEUTRONS EXCEPT FOR HYDROGEN THE ONLY ATOM WITH NO NEUTRONS 4HE RADIUS OF A TYPICAL ATOM IS ABOUT ONE !NGSTROM UNIT ONE TEN BILLIONTH OF A METER 4HE /XFORD !MERICAN $ICTIONARY SAYS THAT AN ATOM IS hTHE SMALLEST PARTICLE OF A CHEMICAL ELEMENT THAT CAN TAKE PART IN A CHEMICAL REACTIONv (OWEVER NOT ALL ATOMS WILL TAKE PART IN A CHEMICAL REACTION SO PERHAPS IT IS POSSIBLE TO BE A BIT MORE EXPLICIT /NE FRESHMAN CHEMISTRY TEXT "ROWN ,E-AY SEE "IBLIOGRAPHY DElNES AN ATOM AS hTHE SMALLEST UNIT OF AN ELEMENT THAT CAN COMBINE WITH OTHER ELEMENTSv !GAIN THAT DElNITION LEAVES OUT SOME NECESSARY INFORMATION )T IS TRUE THAT MOST ATOMS WILL COM BINE TO FORM COMPOUNDS AND MOLECULES BUT NOT ALL OF THEM WILL DO SO NATURALLY 4HE REAL SECRET OF THE NATURE OF THE ATOM IS IN THE NUMBER OF PROTONS IN ITS NUCLEUS !NY CHANGE IN THE NUMBER OF PROTONS AND THE CHEMICAL CHARACTERISTICS OF THE MATERIAL BECOME VERY DIFFERENT 4HAT FACT HELPS US WRITE A MORE GENERALIZED DElNITION OF AN ATOM $ElNITION !N ATOM IS THE SMALLEST UNIT OF AN ELEMENT THAT STILL HAS ALL OF THE SAME CHEMICAL CHARACTERISTICS OF THE ELEMENT !NY ATTEMPT TO MAKE AN ATOM INTO A SMALLER BIT OF MATTER WOULD CHANGE THE CHEMICAL PROPERTIES BECAUSE IT WOULD REQUIRE REMOVING NUCLEAR PARTICLES PROTONS AND
!PPENDIX ! 3CIENCE /VERVIEW NEUTRONS !S WE SHALL SEE LATER SOME ELECTRONS CAN BE REMOVED OR ADDED MAKING AN ION OR SHARED IN CHEMICAL BONDS WITHOUT ALTERING THE BASIC CHEMICAL CHARACTERISTICS OF THE ATOM )F YOU DIVIDED A PIECE OF AN ELEMENT LIKE ALUMINUM !L INTO SMALLER AND SMALLER BITS EVENTUALLY YOU WOULD PRODUCE THE SMALLEST BIT OF ALUMINUM THAT IS STILL CHEMI CALLY IDENTIlABLE AS ALUMINUM AN ATOM OF !L 4HE NUCLEUS OF THE ATOM CONTAINS THE PROTONS POSITIVE CHARGE AND NEUTRONS NO CHARGE EXCEPT FOR HYDROGEN THE ODDBALL WHICH HAS ONLY ONE PROTON IN ITS NUCLEUS %LECTRONS NEGATIVE CHARGE SURROUND THE NUCLEUS AND ARE MOST EASILY PICTURED AS IF THEY WERE PLANETS ORBITING THE NUCLEUS SOMETHING LIKE THE WAY THAT PLANETS ORBIT THE SUN IN OUR SOLAR SYSTEM )T IS INTERESTING TO NOTE THAT THE ELECTRON IS VERY VERY SMALL )T IS MORE THAN TIMES LIGHTER THAN A PROTON 0ROTONS AND NEUTRONS WEIGH ALMOST EXACTLY THE SAME AMOUNT 0LANETARY /RBITS
.E
3UN
NUCLEUS
)LLUSTRATES ONE MODEL OF HOW ELECTRONS ORBIT THE NUCLEUS
&IGURE ! B &ILLED %LECTRON /RBITALS FOR .EON
&IGURE ! A 3IMPLIlED 3OLAR 3YSTEM
!TOMS AND -OLECULES
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&IGURE ! 0ERIODIC 4ABLE OF THE %LEMENTS !BBREVIATED
(ERE IS AN ABBREVIATED VERSION OF THE 0ERIODIC 4ABLE OF THE %LEMENTS 4HIS ABBRE VIATED TABLE INCLUDES MOST OF THE NATURALLY OCCURRING ELEMENTS AND ALL OF THE ELEMENTS THAT WE WILL BE DISCUSSING IN THIS BOOK 3EVERAL GROUPS OF ELEMENTS WILL BE DISCUSSED IN THIS BOOK 4HE COLUMNS THAT MAKE UP THE 0ERIODIC 4ABLE CONTAIN FAMILIES OF CHEMICALS THE ELEMENTS WITH SIMILAR CHEMI CAL PROPERTIES 4HESE FAMILIES ARE CALLED 'ROUPS 3EVERAL GROUPS ARE OF PARTICULAR INTEREST TO THIS DISCUSSION 'ROUP 6))) IS CALLED THE NOBLE GASES 4HIS FAMILY OF CHEMICALS IS ESSENTIALLY NON REACTIVE !LSO CALLED THE INERT GASES THESE ELEMENTS DO NOT PARTICIPATE IN ANY CHEMICAL REACTIONS THAT ARE OF INTEREST TO US IN THE SEMICONDUCTOR INDUSTRY THEY ARE STILL HELPFUL IN CREATING THE STRUCTURES ON THE WAFER BECAUSE OF THEIR PHYSICAL PROPERTIES SO WE USE SOME OF THESE GASES EXTENSIVELY 'ROUP 6)) CALLED THE HALOGENS IS VERY DIFFERENT FROM 'ROUP 6))) 4HIS FAMILY OF CHEMICALS INCLUDES SOME OF THE MOST REACTIVE SUBSTANCES IN THE UNIVERSE 4HE HIGH DEGREE OF REACTIVITY IS A GREAT HELP IN MAKING CHIPS AND SEVERAL OF THESE CHEMICALS ARE USED IN CHIP FABRICATION 'ROUPS ))) AND 6 ARE INTERESTING BECAUSE SOME SEMICONDUCTOR MATERIALS ARE PRO DUCED IN CHEMICAL COMBINATIONS OF ELEMENTS FROM THESE TWO FAMILIES 4HESE ARE NOT SURPRISINGLY REFERRED TO AS )))n6 SEMICONDUCTORS
!PPENDIX ! 3CIENCE /VERVIEW /F COURSE 'ROUP )6 IS VERY INTERESTING BECAUSE IT CONTAINS SILICON THE MOST FAMIL IAR SEMICONDUCTOR AS WELL AS GERMANIUM THE ELEMENT USED TO MAKE THE lRST TRANSISTOR AND THE lRST GENERATION OF SEMICONDUCTOR PRODUCTS 7E WILL BE POINTING OUT THE PROPERTIES OF MANY ELEMENTS FROM THE 0ERIODIC 4ABLE THROUGHOUT OUR DISCUSSIONS )T IS VERY INTERESTING TO NOTE THAT ELEMENTS FARTHER TO THE LEFT SIDE OF THE TABLE ARE OFTEN HIGHLY DAMAGING CONTAMINANTS THAT CAN RUIN THE DEVICES THAT WE ARE MAKING EVEN IN TRACE AMOUNTS
n %LECTRON 6ACANCY
(YDROGEN
&LUORINE
0ROTON %LECTRON
0ROTONS %LECTRONS .EUTRONS
&IGURE ! ( !TOM AND & !TOM
-OLECULES $ElNITION ! MOLECULE IS MADE UP OF ATOMS THAT ARE BOUND TOGETHER 4HE PREVIOUSLY DESCRIBED DElNITION FOR ATOMS APPLIES TO MOLECULES WITH ONLY ONE SMALL CHANGE h! MOLECULE IS THE SMALLEST FUNDAMENTAL UNIT OF A CHEMICAL COMPOUND THAT STILL RE TAINS ALL OF THE CHEMICAL CHARACTERISTICS OF THE CHEMICAL COMPOUNDv 7HILE SOME COMPOUNDS ARE VERY NONREACTIVE THEY ARE NEVERTHELESS COMPOSED OF ATOMS SO WE WONT SPLIT HAIRS THIS TIME $ElNITION ! CHEMICAL COMPOUND IS MADE UP OF TWO OR MORE ATOMS THAT ARE BOUND TOGETHER BY CHEMICAL BONDS ! COMPOUND MADE UP OF A VARIETY OF ELEMENTS WILL HAVE DISTINCTLY DIFFERENT CHEMICAL PROPERTIES THAN THE SEPARATE ELEMENTS OF WHICH IT IS COMPOSED
!TOMS AND -OLECULES
(
(
/ &IGURE ! (/ -OLECULE
/RGANIC -OLECULES /RGANIC MOLECULES ARE DElNED AS CHEMICAL COMPOUNDS IN WHICH CARBON ATOMS ARE A PRINCIPLE COMPONENT 4HERE ARE A VERY FEW CARBON COMPOUNDS THAT ARE NOT ORGANIC SUCH AS CARBON DIOXIDE AND SILICON CARBIDE 3UFlCE IT TO SAY THAT THERE ARE OTHER RULES THAT DElNE ORGANIC COMPOUNDS THAT ARE BEYOND THE SCOPE OF THIS DISCUSSION 7HY CALL THEM hORGANICv YOU MAY ASK !LL LIVING THINGS ARE PRIMARILY COMPOSED OF THESE SPECIAL CARBON COMPOUNDS 4HE INTERESTING THING ABOUT SOME ORGANIC MOL ECULES IS IN THE WAY THEY TEND TO FORM LONG CHAINS CALLED POLYMERS 4HESE CHAINS ARE MADE OF MANY MULTIPLES OF A BASIC BUILDING BLOCK CALLED A MONOMER &IGURES ! AND ! SHOW THE MONOMER AND POLYMER OF TWO FAMILIAR hPLASTICSv THAT YOU HAVE AROUND THE HOUSE PLASTICS ARE MADE OF ORGANIC MOLECULES TOO -ONOMER %THYLENE 0OLYMER 0OLYETHYLENE ( ( L L # # L L ( (
( ( ( ( ( L L L L L
# # # # # L L L L L ( ( ( ( (
&IGURE ! %THYLENE AND 0OLYETHYLENE
!PPENDIX ! 3CIENCE /VERVIEW 4ETRAFLUOROETHYLENE 0OLYTETRAFLUORETHYLENE 4EFLON & & L L # # L L & &
& & & & & L L L L L
# # # # # L L L L L & & & & &
&IGURE ! 4ETRAmUOROETHYLENE 4EmON® 3TATES OF -ATTER -ATTER COMES IN SEVERAL FORMS CALLED STATES %VERYONE IS FAMILIAR WITH THE THREE MOST COMMON STATES SOLID LIQUID AND GAS 4HERE ARE TWO OTHERS THE PLASMA STATE AND THE "OSE %INSTEIN #ONDENSATE 0LASMA WILL BE DISCUSSED IN THIS SECTION 4HE "OSE %INSTEIN #ONDENSATE IS REALLY RARE AND HARD TO PRODUCE PUTTING IT BEYOND THE SCOPE OF THIS TEXT )F YOU REFERENCE THE 0ERIODIC 4ABLE YOU MAY NEED TO LOOK AT A COMPLETE VERSION FOR THIS JUST TO BE SURE AND LOOK FOR ELEMENTS THAT OCCUR NATURALLY OR CAN BE RElNED AND REMAIN IN THEIR ELEMENTAL FORM AT ROOM TEMPERATURE IN AIR FOR SOME PERIOD OF TIME YOU WILL SEE AN AMAZING THING THERE ARE ONLY TWO LIQUIDS MERCURY AND BROMINE /+ GALLIUM MELTS AT # SO ITS A LIQUID ON A HOT DAY TOO ,OOK FOR ELEMENTS THAT ARE TYPICALLY FOUND IN THE GASEOUS STATE AND ONLY THE SIX NOBLE GASES PLUS lVE OTHER MATERIALS ARE INCLUDED )T IS INTERESTING THAT SO MANY LIQUID AND GASEOUS COMPOUNDS EXIST WHEN SO FEW ELEMENTS NATURALLY OCCUR IN THOSE STATES ! SUBSTANCE SUCH AS WATER IS OFTEN FOUND IN ALL THREE COMMON STATES SIMUL TANEOUSLY ! GLASS OF ICE WATER WILL HAVE SOLID WATER LIQUID WATER AND ALSO SOME EVAPORATION WILL FORM GASEOUS WATER WATER VAPOR THAT ESCAPES FROM THE SURFACE OF THE LIQUID (OW IS IT THAT ICE CUBES CAN DISAPPEAR FROM THE FREEZER OF YOUR FROST FREE REFRIGERATOR 4HEY SUBLIME OR PASS DIRECTLY FROM SOLID TO GAS PHASE )T HAPPENS BECAUSE THE FREEZER REMOVES ALMOST ALL OF THE HUMIDITY WATER VAPOR FROM THE AIR INSIDE )T ALLOWS THE MOLECULES OF WATER TO LEAVE THE SURFACE OF THE ICE WITHOUT NEEDING TO MELT THE ICE lRST
3%#4)/.
'ASES &ACTS ABOUT 'ASES $ElNITION ! 'AS IS A mUID COMPRISED OF A COLLECTION OF ATOMS OR MOLECULES THAT ARE RELATIVELY FAR APART 4O DESCRIBE A GAS AT ANY POINT IN TIME IT IS NECESSARY TO SPECIFY THREE QUANTITIES VOLUME PRESSURE AND TEMPERATURE $ElNITION ! &LUID IS A SUBSTANCE THAT CAN mOW AND WILL CONFORM TO THE BOUNDARIES OF A CONTAINER IN WHICH IT IS CONlNED &LUIDS DIFFER FROM SOLIDS IN THAT THEIR MOLECULES HAVE NO LONG RANGE ORDER -ORE ON &LUIDS ! mUID mOWS BECAUSE IT CANNOT WITHSTAND A FORCE THAT IS TANGENTIAL TO ITS SUR FACE 4HAT KIND OF A FORCE IS CALLED A SHEARING STRESS )T CAN BE SAID THAT A mUID IS A SUBSTANCE THAT mOWS BECAUSE IT CANNOT WITHSTAND A SHEARING STRESS )T CAN EXERT A FORCE THAT IS PERPENDICULAR TO ITS SURFACE HOWEVER
!LL lVE OF THE GASEOUS ELEMENTS THAT ARE NOT NOBLE GASES OCCUR AS DIATOMIC MOLECULES IN NATURE 4WO OF THE ATOMS OF THE GAS COMBINE SHARING AN ELECTRON IN A CHEMICAL BOND 4HAT IS WHY THE COMMON WAY OF WRITING THE CHEMICAL SYMBOL FOR THESE GASES LOOKS LIKE THIS ( . / & AND #L /F COURSE THE NOBLE GASES ARE NOT CHEMICALLY REACTIVE SO THEY DO NOT READILY COMBINE WITH EACH OTHER OR ANY OTHER SUB STANCE /XYGEN CAN FORM THE TRIATOMIC MOLECULE / OZONE UNDER CERTAIN CONDITIONS 4O THE PHYSICIST GASES ARE COMPRESSIBLE mUIDS 4HE STUDY OF mUIDS INCLUDES BOTH LIQUIDS AND GASES BUT BECAUSE GASES ARE COMPRESSIBLE THEY TEND TO BE A BIT MORE COM PLICATED IN THE PHYSICAL SENSE AND HAVE GOTTEN QUITE A LOT MORE ATTENTION THAN LIQUIDS 4HE FAVORITE UNIT OF PRESSURE USED IN THE CHIP INDUSTRY IS THE 4ORR NAMED AFTER 'ALILEOS PERSONAL SECRETARY %VANGELISTA 4ORRICELLI WHO IS CREDITED WITH INVENTING THE
!PPENDIX ! 3CIENCE /VERVIEW BAROMETER SEE #HAPTER )T IS THE SAME UNIT AS THE MILLIMETER OF MERCURY 4ORRICELLI FOUND THAT THE COLUMN OF MERCURY (G IN HIS BAROMETER WAS ON AVERAGE MILLI METERS HIGH AT SEA LEVEL %VEN THOUGH THE METRIC SYSTEM WAS INVENTED SEVERAL HUNDRED YEARS AFTER 4ORRICELLIS DEATH WE MUST USE IT HERE BECAUSE NO ONE WOULD RECOGNIZE THE MEASUREMENT SYSTEM USED IN THOSE DAYS 4ABLE ! &ACTS ABOUT 'ASES 2 2 2 2 2
*% ( *$&)'! (" '( ))+( &(( $$ *&(( +" %*"$ * (& ) &%*"%) ''(&."$* #/ 3 $"##"&%"##"&%'(*" # )& ) ) &+)'(*" # )( "% &%)*%*$&*"&% 1&%)*%*#/ &##" "% -"*! !&*! (% !$ (-##) 1 $) *(&&$* $' (*+( */'" #''(&."$* , ( )' 1 % ( ) * $' (*+( "% ( ) ), #& "*/ %( *!*! , ( ")*% '(*" # *(, #) *- % &##")"&%) -"*!%&*! ('(*" # ''(&."$* $ % ( '*!) &(!/ (& %$&# +# )*#&-'( ))+( "% *! (% +) "%$%/ !"''(& )) ) 1 &(( 0$$$"##"$ * ( 1 $ 0$$ 1 $ 0 $
)ONS $ElNITION !N )ON IS A PARTICLE THAT HAS AN ELECTRICAL CHARGE !N ION HAS EITHER LOST OR GAINED ONE OR MORE ELECTRONS RESULTING IN AN EXCESS OF NEGATIVE OR POSITIVE ELECTRICAL CHARGE 2EMEMBER THAT THE ELECTRON IS THE NEGATIVE CHARGE CARRIER AND THE PROTON IN THE NUCLEUS CARRIES THE POSITIVE CHARGE
0LASMA $ElNITION 0LASMA IS AN IONIZED GAS -ANY PEOPLE ARE SURPRISED TO LEARN THAT THE PLASMA STATE IS THE MOST COMMON STATE OF MATTER IN THE UNIVERSE 4HE SUN AND STARS ARE MOSTLY PLASMA AND INTERSTELLAR SPACE HAS LOTS OF PLASMA TOO #OLD $ARK -ATTER IS A NEW ARRIVAL ON THE THEORETICAL SCENE AND NOBODY KNOWS EXACTLY WHAT IT IS YET SO WE WILL ONLY DISCUSS hNORMALv MATTER HERE 0LASMA IS USED EXTENSIVELY IN THE SEMICONDUCTOR MANUFACTURING PROCESS SO IT IS IMPORTANT TO KNOW SOMETHING ABOUT THIS UNFAMILIAR STATE OF MATTER
'ASES 4ABLE ! &ACTS ABOUT 0LASMA / / / / / /
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&REE 2ADICALS $ElNITION ! &REE 2ADICAL IS A HIGHLY REACTIVE FRAGMENT OF A MOLECULE THAT HAS ONE OR MORE hFREEv OR UNPAIRED ELECTRONS ! FREE RADICAL IS A HIGHLY REACTIVE SUBSTANCE )F A #& MOLECULE IS DECOMPOSED IN A PROCESSING REACTOR WHICH IS A COMMON ACTIVITY IN THE CHIP MAKING PROCESS IT MIGHT PRODUCE FREE RADICALS LIKE #& #& #& 4O MAKE MATTERS EVEN MORE COMPLICATED THE FREE RADICALS CAN BECOME IONIZED TOO )N ADDITION FREE RADICALS CAN BE IN AN EXCITED STATE AS DESCRIBED IN THE NEXT SECTION
%XCITED 3TATES $ElNITION !TOMS OR MOLECULES ARE IN AN %XCITED 3TATE IF THEY HAVE EXTRA ENERGY ADDED TO THEM !N EXAMPLE WILL HELP TO EXPLAIN EXCITED STATES (EATING A MATERIAL IS ONE WAY OF ADDING ENERGY TO IT )N MANY PLASMA REACTORS THE GAS MOLECULES ARE HEATED BY USING AN ELECTRIC lELD TO ACCELERATE STRAY ELECTRONS CAUSING THEM TO COLLIDE WITH OTHER PARTICLES
!PPENDIX ! 3CIENCE /VERVIEW 4HE COLLISIONS TRANSFER ENERGY HEAT TO THE PARTICLES OF GAS CAUSING ELECTRONS TO MOVE FURTHER AWAY FROM THE NUCLEUS OR TO BREAK AWAY ENTIRELY 7HEN THE ELECTRONS GIVE UP THEIR EXTRA ENERGY COOL DOWN THEY RADIATE IT IN THE FORM OF LIGHT AND MOVE CLOSER TO THE NUCLEUS AGAIN #HEMICAL REACTIONS HAPPEN MUCH MORE RAPIDLY WITH THE CHEMICALS IN AN EXCITED STATE (OWEVER IF A MOLECULE IS NOT INVOLVED IN A REACTION THE EXTRA ENERGY IS USUALLY GIVEN UP RATHER QUICKLY &OR EXAMPLE A GAS MAY GLOW EMITTING A CHARACTERISTIC COLOR 4HE EXTRA ENERGY IS BEING GIVEN UP AS PHOTONS OF LIGHT FOR EXAMPLE A NEON SIGN "UT AS LONG AS THE ENERGY IS BEING ADDED TO THE GAS ITS ATOMS OR MOLECULES WILL BECOME EXCITED EMIT LIGHT AND DROP TO A LOWER ENERGY LEVEL BECOME EXCITED AGAIN GIVING UP THE ENERGY OVER AND OVER 3INCE FAST PROCESSING TIME IS IMPORTANT IN ANY MANUFACTURING ENVIRONMENT THE USE OF CHEMICALS IN AN EXCITED STATE IS OF GREAT HELP IN THE CHIPMAKING PROCESS
3%#4)/.
#HEMISTRY )NTRODUCTION 4HE CHEMISTRY INVOLVED IN CHIPMAKING IS RELATIVELY STRAIGHTFORWARD 4HE NUMBER OF CHEMICALS USED IN THE MANUFACTURING PROCESS IS FAIRLY LIMITED AS ARE THE TYPES OF REAC TIONS (OWEVER A LARGE NUMBER OF ELEMENTS AND COMPOUNDS ARE OF IMPORTANCE TO THE DISCUSSION OF THE SUBJECT 3O RATHER THAN TRY TO SUMMARIZE AN ENTIRE CHEMISTRY COURSE THIS DISCUSSION WILL BE CONlNED TO ONLY THE TOPICS INVOLVED IN MAKING CHIPS ! FEW EXAMPLES ARE GIVEN FOR EACH TOPIC TO SERVE AS A FAMILIARIZATION AND REVIEW #HEMICAL REACTIONS ARE PRIMARILY NEEDED FOR MAKING THE SILICON WAFERS DEPOSIT ING lLMS ON THE WAFERS AND ETCHING THE PATTERNS INTO THE lLMS %XAMPLES OF DEPOSITION CHEMISTRY AND PLASMA ETCH CHEMISTRY WILL BE DISCUSSED 4HE FOLLOWING DElNITION IS OFFERED FOR THE SAKE OF COMPLETENESS $ElNITION #HEMISTRY IS THE STUDY OF MATTER AND THE MANY WAYS IN WHICH IT CAN CHANGE
4HIN &ILM $EPOSITION #HEMISTRY 3ILICON TECHNOLOGY IS THE FOCUS OF THIS BOOK ,ET US BEGIN WITH AN EXAMPLE OF A CHEMI CAL REACTION INVOLVING SILICON
3I / m 3I/
4HIS SIMPLE CHEMICAL EQUATION SHOWS SILICON REACTING WITH OXYGEN TO FORM SILICON DIOXIDE 4HE MATERIALS ON THE LEFT SIDE OF THE ARROW ARE CALLED THE REACTANTS THE PLUS SIGN MEANS hREACTS WITHv 4HE ARROW MEANS hPRODUCESv 4HE PRODUCTS FORMED IN THE REACTION ARE TO THE RIGHT OF THE ARROW
!PPENDIX ! 3CIENCE /VERVIEW +EY 0OINT 4HE RATE OF REACTION WILL INCREASE IF ENERGY IS ADDED %NERGY IS OFTEN ADDED BY HEATING THE REACTANTS BUT OTHER METHODS ARE AVAILABLE 4HIS OXIDATION REACTION WILL HAPPEN SPONTANEOUSLY IN THE AIR AT ATMOSPHERIC PRES SURE AND ROOM TEMPERATURE (OWEVER THE REACTION GOES EXTREMELY SLOWLY UNDER THOSE CONDITIONS )N ORDER TO SPEED IT UP AND THEREBY IMPROVE THROUGHPUT THE NUMBER OF WAFERS PROCESSED PER HOUR THE PROCESS IS DONE AT HIGH TEMPERATURE )N THE CASE OF THE GROWTH OF SACRIlCIAL OXIDE DONE EARLY IN THE PROCESS THE WAFER WILL TYPICALLY BE HEAT ED TO MORE THAN # IN A FURNACE )NERT GAS IS USED TO mUSH THE FURNACE WHEN IDLE !FTER LOADING WAFERS INSIDE THE CHAMBER IS EVACUATED PRIOR TO INTRODUCING OXYGEN &OR SOME THICKER OXIDE GROWTH STEPS USED IN CHIP FABRICATION WATER VAPOR IS USED INSTEAD OF OXYGEN 3URPRISINGLY IT GIVES A FASTER OXIDATION RATE (ERE IS THE REACTION WITH WATER VAPOR 3I (/ m 3I/ ( 4HE HYDROGEN COMES OFF AS A GAS ,ETTERS IN PARENTHESIS OCCASIONALLY APPEAR IN THE EQUATION TO SHOW THE STATE OF EACH SPECIES 4HE USUAL DESIGNATIONS ARE SOLID S LIQUID L AND GAS G "ALANCED #HEMICAL %QUATIONS )N THE REACTION ABOVE A hv APPEARS IN FRONT OF THE WATER COMPONENT AND A hv IS FOUND IN FRONT OF THE HYDROGEN TERM 4HESE FACTORS ARE NEEDED TO BALANCE THE CHEMICAL EQUATION ! BALANCED EQUATION HAS THE SAME NUMBER OF ATOMS OF EACH ELEMENT ON BOTH SIDES OF THE ARROW &OR BREVITY MANY CHEMICAL EQUATIONS ARE PRESENTED IN THEIR UNBALANCED FORM
!N EXAMPLE OF A DEPOSITED lLM IS SILICON NITRIDE /NE COMMON CHEMICAL VAPOR DEPOSITION #6$ METHOD FOR DEPOSITING THIS lLM IS COMBINING AMMONIA GAS .( WITH THE VAPOR OF A LIQUID TRICHLOROSILANE 3I(#L .( 3I(#L m 3I. (#L 4HIS REACTION REQUIRES A TEMPERATURE OF ABOUT # ABOVE RED HEAT ,ATER IN THE PROCESS LOWER TEMPERATURES OF DEPOSITION ARE REQUIRED 4HEN AN ALTERNATIVE REACTION CAN BE USED REACTING SILANE 3I( AND AMMONIA 3I( .( m 3IX.Y (Z
#HEMISTRY 5SING THE ENERGY OF A PLASMA THIS REACTION CAN BE DONE AT AROUND # 4HE COMPOSITION AND PROPERTIES OF THIS NITRIDE lLM ARE CONSIDERABLY DIFFERENT FROM THE HIGHER TEMPERATURE lLM BUT ARE STILL ACCEPTABLE FOR SOME APPLICATIONS 7HY NOT JUST REACT SILICON AND NITROGEN "ECAUSE THE REACTION REQUIRES A TEM PERATURE OF n# TO TAKE PLACE 4HAT HIGH TEMPERATURE IS INCOMPATIBLE WITH THE PROCESS RESTRICTIONS AS DISCUSSED IN THE TEXT !NOTHER SMALL DIFlCULTY ARISES WHEN NITRIDE IS NEEDED IN THE PROCESS USUALLY ALL OF THE SILICON IS COVERED UP BY OTHER lLMS SO NONE IS AVAILABLE TO REACT WITH THE NITROGEN TO FORM NITRIDE #6$ TO THE RESCUE
0LASMA %TCH #HEMISTRY 0LASMA PROCESSING IS WIDELY USED IN CHIPMAKING 4HE PLASMA PRODUCES MANY HIGHLY REACTIVE SPECIES )N ESSENCE THE PRODUCTION OF A PLASMA ADDS ENERGY TO THE GASEOUS CHEMICALS THROUGH THE USE OF AN ELECTRIC lELD 4HE INCREASED RATE OF REACTION IS ONE OF SEVERAL ADVANTAGES DISCUSSED IN THE TEXT 0LASMA TOOLS ARE USED FOR BOTH DEPOSITION AND ETCH /NLY THE ETCH EXAMPLES ARE PRESENTED HERE %TCHING SILICON IS NECESSARY TO MAKE THE FEATURES ON THE CHIP #HLORINE IS OFTEN USED TO ETCH SILICON 3IS #LG m 3I#LG 4HE SOLID SILICON REACTS WITH THE GASEOUS CHLORINE TO PRODUCE GASEOUS SILICON TETRA CHLORIDE 4HE FUNCTIONING OF THE ETCH REACTOR IS DESCRIBED IN #HAPTER +EY 0OINT 0LASMA ETCH REACTIONS MUST PRODUCE VOLATILE PRODUCTS OF REACTION OR THE RE ACTANT CHEMICALS WILL BE BLOCKED FROM REACHING THE WAFER AND THE REACTION WILL STOP /FTEN THE ETCH REACTION WILL INCLUDE A COMPONENT THAT WILL BE LEFT BEHIND AS A SOLID ON THE WAFER SURFACE 4HIS EXAMPLE SHOWS A PARTIAL SAMPLING OF HOW MUCH IS GOING ON INSIDE MANY PLASMA REACTORS #& &REON ® AND #(& &REON ® ARE THE TWO REACTANTS WITH SILICON DIOXIDE 3I/S #&G #(&G m 3I&G #/G #/G #&XS (&G &G )N THIS EXAMPLE THE SILICON DIOXIDE REACTS WITH mUORINE PRODUCED IN THE PLASMA GIVING SILICON TETRAmUORIDE A GAS 4HE #&X IN THE EQUATION REPRESENTS VARIOUS CARBON mUORINE POLYMERS PRODUCED IN THE REACTION 4HESE POLYMERS ARE SOLIDS AND DEPOSIT ON THE WAFER SURFACE FORMING A PASSIVATION LAYER THAT IS ESSENTIAL TO THE PROCESS 4HE COMPLEXITY OF THE PLASMA CHEMISTRY IS DISCUSSED EXTENSIVELY IN #HAPTERS AND 4HIS EXTENSIVE AND INCOMPLETE EQUATION IS SHOWN TO INDICATE THE COMPLEXITY OF THE REACTION
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3OLIDS $ElNITION ! 3OLID IS A MATERIAL THAT HOLDS ITS SHAPE AND VOLUME AND TENDS TO RESIST PHYSICAL DEFORMITY 4HE PARTICLES THAT MAKE UP A SOLID ARE IN A lXED POSITION WITH IN THE MATERIAL OFTEN IN AN ORDERED ARRANGEMENT AND ARE RELATIVELY CLOSE TOGETHER 4HE ATOMS AND MOLECULES STILL VIBRATE BUT DO NOT LEAVE THEIR POSITIONS WITHIN THE SOLID
%LECTRICAL 0ROPERTIES OF 3OLIDS #ONDUCTORS AND )NSULATORS $ElNITION ! #ONDUCTOR IS A MATERIAL THAT READILY CONDUCTS ELECTRICITY %LECTRICAL CON DUCTORS ALSO TEND TO CONDUCT HEAT WELL -ATERIAL 0ROPERTIES )T IS TYPICAL TO DISCUSS THE PROPERTIES OF A MATERIAL IN TERMS OF ITS RESISTIVITY AND THE RECIPROCAL QUANTITY CONDUCTIVITY 2ESISTIVITY IS A PROPERTY OF A MATERIAL )T IS DElNED AS THE ELECTRIC lELD INTENSITY AT A SPECIlC POINT IN THE MATERIAL DIVIDED BY THE CURRENT DENSITY AT THAT POINT 4HE UNITS OF RESISTIVITY ARE OHM METERS HOWEVER IT IS FAR MORE CONVENIENT TO CONVERT TO OHM CENTIMETERS FOR USE IN THE SEMICONDUCTOR INDUSTRY AND OTHER INDUSTRIES 4HE OHM CENTIMETER IS THE RESISTANCE MEASURED ON OPPOSITE FACES OF A ONE CENTIMETER CUBE OF THE MATERIAL OF INTEREST
$ElNITION !N )NSULATOR IS A VERY POOR CONDUCTOR OF ELECTRICITY )NSULATORS ARE SAID TO BE HIGHLY RESISTIVETHAT IS THEY RESIST THE mOW OF CURRENT 4HE BEST INSULATOR IS A VACUUM
!PPENDIX ! 3CIENCE /VERVIEW
3EMICONDUCTORS $ElNITION ! 3EMICONDUCTOR IS A MATERIAL WITH ELECTRICAL PROPERTIES MIDWAY BETWEEN A CONDUCTOR AND AN INSULATOR 3EMICONDUCTOR MATERIALS READILY CHANGE ELECTRICAL PROPERTIES WITH THE ADDITION OF IMPURITIES CALLED DOPANTS )N KEEPING WITH THE FOCUS OF THIS BOOK SILICON WILL BE THE PRIMARY TOPIC OF DISCUS SION IN THIS SECTION 4ABLE ! &ACTS ABOUT 3EMICONDUCTORS ) ) )
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3EMICONDUCTOR DEVICES ARE MADE PRIMARILY BY DOPING THE SEMICONDUCTING MATERIAL TO ADJUST ITS ELECTRICAL PROPERTIES 4HE SEMICONDUCTOR MAY BE DOPED WITH IMPURITIES THAT PROVIDE EXTRA MOBILE NEGATIVE CHARGES ELECTRONS TO THE MATERIAL MAKING IT hN TYPEv OR THE IMPURITIES MAY BE SHORT OF ELECTRONS AND THEREBY PROVIDE APPARENT MOBILE POSITIVE CHARGES HOLES TO MAKE THE MATERIAL hP TYPEv 4HE P TYPE MATERIAL IS TREATED AS IF IT HAD ACTUAL POSITIVE CHARGE CARRIERS EVEN THOUGH THE ACTUAL PHYSICAL SITU ATION IS A hLACK OF NEGATIVE CHARGESv
3OLIDS $OPING RAISES THE CONDUCTIVITY OF SILICON TO A LEVEL WHERE IT IS CONSIDERED TO BE AN ELECTRICAL CONDUCTOR &IGURE ! SO IT CAN BE USED TO CARRY CURRENT (OWEVER ITS CONDUCTIVITY IS STILL FOUR ORDERS OF MAGNITUDE BELOW THAT OF A METAL SUCH AS COPPER A PARTICULARLY GOOD CONDUCTOR
PN *UNCTIONS $ElNITION ! PN *UNCTION IS SINGLE PIECE OF SEMICONDUCTOR MATERIAL THAT HAS BEEN SELECTIVELY DOPED SUCH THAT ADJACENT REGIONS OF N TYPE AND P TYPE MATERIAL ARE FORMED )T IS AN EXAMPLE OF A SOLID STATE DEVICE 4HE TERM SOLID STATE ORIGINATED WHEN TRANSISTORS MADE FROM SEMICONDUCTING MATERIALS REPLACED VACUUM TUBES -ETALLURGICAL *UNCTION
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&IGURE ! PN *UNCTION
4HE MAGIC OF SOLID STATE DEVICES IS REVEALED IN THE PN JUNCTION 7HEN ADJACENT REGIONS OF OPPOSITELY DOPED SILICON ARE FORMED AN INTERESTING PHENOMENON OCCURS !T THE INTERFACE A THIN AREA CALLED THE DEPLETION REGION FORMS 4HE DEPLETION REGION IS SO CALLED BECAUSE IT IS DEPLETED OF CHARGES THAT ARE FREE TO MOVE )N THIS CONDITION IT CANNOT CONDUCT A CURRENT IN THE USUAL WAY (OWEVER IF THE PROPER VOLTAGE IS APPLIED AS SHOWN IN &IGURE ! A CURRENT WILL mOW QUITE EASILY 4HE PN JUNCTION CAN SERVE AS A RECTIlER A DEVICE THAT ALLOWS CURRENT TO mOW ONLY ONE DIRECTION THROUGH IT &IGURE ! ILLUSTRATES THE FUNCTIONING OF THE JUNCTION RECTI lER .OTE THAT THE DEPLETION REGION GROWS MUCH WIDER WITH A REVERSE BIAS RESISTING THE mOW OF CURRENT THROUGH THE DEVICE IN THAT DIRECTION
!PPENDIX ! 3CIENCE /VERVIEW 6EXT
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&IGURE ! *UNCTION 2ECTIlER &ORWARD AND 2EVERSE "IASED
-ANY SOLID STATE DEVICES ARE MADE BY COMBINING PN JUNCTIONS IN CREATIVE WAYS )N THIS BOOK A -/3&%4 WAS MADE ONE EXAMPLE OF COMBINING TWO PN JUNCTIONS NEAR TO EACH OTHER
3%#4)/.
%LECTRICITY %LECTRIC AND -AGNETIC &IELDS %LECTRIC #HARGES AND &IELDS $ElNITION %LECTRIC #HARGE IS AN INTRINSIC PROPERTY OF MATTER 3INCE MATTER IS MADE UP OF ATOMS THAT CONTAIN ELECTRONS NEGATIVE AND PROTONS POSITIVE THE CHARGES ARE ALWAYS THERE -ANY NATURAL AND ARTIlCIAL CONDITIONS EXIST WHICH ALLOW US TO WORK WITH CHARGES USUALLY ELECTRONS AND TO TAKE ADVANTAGE OF THE ENERGY AVAILABLE $ElNITION !N %LECTRIC &IELD EXISTS IN THE REGION AROUND A CHARGED PARTICLE OR A GROUP OF CHARGES )T DESCRIBES THE AMOUNT OF FORCE EXERTED ON OTHER CHARGES THAT ENTER THE REGION 4HE lELD IS INVISIBLE TO EVERYTHING EXCEPT ANOTHER CHARGED PARTICLE %LECTRIC &IELD 3TRENGTH 4HE ELECTRIC lELD STRENGTH IS THE FORCE EXERTED ON A TEST CHARGE AT A GIVEN POINT WITHIN THE lELD 4HE lELD STRENGTH DECREASES RATHER RAPIDLY WITH DISTANCE AS THE TEST CHARGE IS MOVED AWAY FROM THE SOURCE OF THE lELD THIS IS AN EXAMPLE OF THE INVERSE SQUARE LAW WHERE THE lELD STRENGTH FALLS OFF AS THE INVERSE SQUARE OF THE DISTANCE FROM THE SOURCE INCREASES ! DIFFERENT SITUATION EXISTS IN A PARALLEL PLATE CAPACITOR 4HE ELECTRIC lELD IS UNIFORM BETWEEN THE CAPACITOR PLATES EXCEPT AT THE EDGES BUT THAT CAN BE CONVENIENTLY IGNORED 4HE PARALLEL PLATE CAPACITOR IS A FAMILIAR EXAMPLE USED THROUGHOUT THE TEXT
!PPENDIX ! 3CIENCE /VERVIEW &IELD 4HEORY &IELD THEORY EXPLAINS THE hACTION AT A DISTANCEv EFFECT EXPERIENCED BY CHARGED OBJECTS THEY EXERT A FORCE ON EACH OTHER LIKE CHARGES REPEL AND UNLIKE CHARGES ATTRACT FROM RELATIVELY FAR AWAY "EFORE &IELD 4HEORY WAS FORMULATED MANY SCIENTISTS THOUGHT THAT AN UNSEEN mUID CALLED ETHER EXISTED THAT TRANSMITTED THE ELECTRICAL FORCE FROM ONE OBJECT TO THE OTHER ,ATE IN THE .INETEENTH #ENTURY -ICHELSON AND -ORLEY PROVED THAT THERE IS NO ETHER AND PAVED THE WAY FOR ELECTRIC lELD THEORY
%LECTRIC #URRENT $ElNITION !N %LECTRIC #URRENT IS THE mOW OF ELECTRIC CHARGES ! NET mOW IN ONE DIRECTION OF ANY CHARGED PARTICLES COULD BE CALLED AN ELECTRIC CURRENT BUT FOR PRACTICAL REASONS THIS DISCUSSION WILL BE CONlNED TO THE mOW OF ELECTRONS USUALLY WITHIN A CONDUCTING MEDIUM /NE CONFUSING ISSUE THAT SHOULD BE MENTIONED IS THAT THE CONVENTION ADOPTED FOR CURRENT mOW IN AN ELECTRIC CIRCUIT IS FROM THE POSITIVE POLE OF THE SOURCE SUCH AS A BAT TERY TO THE NEGATIVE POLE 4HE ACTUAL MOVEMENT OF THE ELECTRONS GOES IN THE OPPOSITE DIRECTION (OWEVER EVERYTHING STILL WORKS INCLUDING THE MATH IF THE PRETENCE OF mOW ING POSITIVE CHARGES IS MAINTAINED $O NOT CONFUSE CONVENTIONAL ELECTRIC CURRENT WITH SAY THE MOVEMENT OF POSITIVE IONS WITHIN A PLASMA A REAL EXAMPLE OF THE MOVEMENT OF POSITIVE CHARGES 4HE PHYS ICS IS USUALLY QUITE DIFFERENT FROM THAT NEEDED FOR THIS DISCUSSION AND A LOT HARDER #URRENT mOW IS OFTEN COMPARED TO THE mOW OF WATER THROUGH A PIPE AND THE ANAL OGY IS QUITE ACCURATE IN MANY WAYS &OR EXAMPLE ELECTRIC CURRENT IS ANALOGOUS TO THE VOLUME OF WATER mOWING THROUGH A PIPE #ONDUCTING WIRES OR OTHER MATERIALS ARE ANALOGOUS TO THE PIPE )F THE PIPE IS TOO SMALL FOR THE AMOUNT OF WATER BEING FED INTO IT THEN IT SLOWS THE mOW JUST AS A lNE WIRE WILL RESIST A HIGH ELECTRICAL CURRENT mOW A hRESISTORv IS OFTEN MADE OF lNE WIRE $ElNITION ! 0OTENTIAL $IFFERENCE OR A 6OLTAGE MUST EXIST IN ORDER FOR ELECTRONS TO mOW 4HE POTENTIAL DIFFERENCE IS THE EQUIVALENT OF PRESSURE IN A PIPE THAT PUSHES WATER THROUGH IT 4HE WATER WILL NOT mOW WITHOUT PRESSURE TO PUSH IT AND NEITHER WILL ELECTRONS mOW WITHOUT A POTENTIAL DIFFERENCE
%LECTRICITY %LECTRIC AND -AGNETIC &IELDS
-AGNETIC &IELD $ElNITION ! -AGNETIC &IELD IS SIMILAR TO AN ELECTRIC lELD IT IS AN INTRINSIC PROPERTY OF CHARGED PARTICLES (OWEVER IT ALSO EXISTS IN THE REGION AROUND A PERMANENT MAGNET A MATERIAL WITH ITS ELECTRONS LINED UP IN lXED POSITIONS OR IN A CONDUCTOR WITH CURRENT mOWING THROUGH IT %LECTROMAGNETS SUCH AS METAL BARS WITH CURRENT CARRYING WIRE WRAPPED AROUND THEM ACT JUST LIKE PERMANENT BAR MAGNETS -AGNETIC lELDS INTERACT WITH CHARGED PARTICLES SOMEWHAT DIFFERENTLY THAN ELECTRIC lELDS 4HESE DIFFERENCES WILL BE POINTED OUT IN THE DISCUSSIONS OF THE TOOLS THAT USE MAGNETIC lELDS
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" 0LASMA %TCH 3UPPLEMENT TO #HAPTER
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0LASMA %TCHER 4HEORY 0LASMA IS AN IONIZED GAS (OW DOES AN ETCH REACTOR MAKE A GAS INTO A PLASMA &REE ELECTRONS IN A PLASMA REACTOR ARE ACCELERATED BY AN ELECTRIC lELD THEY COLLIDE WITH ELECTRONS ORBITING THE NUCLEI OF ATOMS AND MOLECULES KNOCKING SOME OF THEM OFF AND PRODUCING THE CASCADE EFFECT +NOCKING OFF AN ELECTRON WILL PRODUCE A POSITIVE ION OR ONE OF THE OTHER COMPONENTS OF THE PLASMA DISCUSSED BELOW )N OTHER CASES AN ATOM OR MOLECULE OF GAS WILL TRAP A FREE ELECTRON PRODUCING A NEGATIVE ION &IGURE " ATTEMPTS TO SHOW THE COMPLICATED hCHEMICAL SOUPv THAT EXISTS IN A PLASMA REACTOR /F COURSE ELECTRONS COLLIDE WITH EVERYTHING IN THE PLASMA REACTOR INCLUDING THE REACTOR WALLS 4HOSE COLLISIONS DO NOT CONTRIBUTE MUCH OF ANYTHING TO MAKING THE PLAS MA SO THEY WILL NOT BE DISCUSSED HERE 3EVERAL INTERESTING REFERENCES MAY BE FOUND IN THE BIBLIOGRAPHY THAT FULLY DISCUSS PLASMA PHYSICS AND CHEMISTRY +EY 0OINT 0LASMA IS PRODUCED ENTIRELY BY ELECTRON COLLISIONS 4HAT KEY POINT IS A BIT SURPRISING WHEN ONE CONSIDERS THAT AN ELECTRON IS MORE THAN TIMES LIGHTER THAN A PROTON OR NEUTRON THE COMPONENTS OF THE NUCLEUS SEE !PPENDIX ! -ANY OF THE ATOMS IN THE PLASMA ARE FAIRLY MASSIVE WITH NUMEROUS PRO TONS AND NEUTRONS IN THE NUCLEUS 7HY DONT THE NUCLEI DOMINATE THE COLLISIONS RATHER THAN ELECTRONS 4HERE ARE A COUPLE OF REASONS 4HE lRST REASON IS JUST A PART OF THE AMAZING NATURE OF ATOMS THEMSELVES )T HAS BEEN SAID THAT IF AN ATOM WERE THE SIZE OF A CATHEDRAL THE NUCLEUS WOULD BE NO BIGGER THAN A mYBUT A mY THAT WEIGHS THOUSANDS OF TIMES MORE THAN THE CATHEDRAL !LL OF THAT EXTRA SPACE IS THE DOMAIN OF THE ELECTRONS BELONGING TO THAT ATOM 4HE CHANCES ARE MUCH GREATER FOR ELECTRON COLLISIONS THAN FOR AN ELECTRON NUCLEUS COLLISION
!PPENDIX " 0LASMA %TCH 3UPPLEMENT TO #HAPTER 3ECOND THE ELECTRONS ARE EXTREMELY LIGHT COMPARED TO THE IONS BECAUSE THE NUCLEI OF THE IONS ARE SO MASSIVE 0LASMA REACTORS ARE DESIGNED TO TAKE ADVANTAGE OF THAT FACT AND REALLY PUT THE POWER INTO WHIPPING THE ELECTRONS AROUND !CCELERATING THE IONS IS IMPORTANT TOO FOR SOME APPLICATIONS BUT THE PURPOSE IN THAT CASE IS TO BOMBARD THE WAFER NOT TO MAKE PLASMA !NOTHER INTERESTING THING HAPPENS IN A PLASMA 4HE ELECTRON COLLISIONS PRODUCE IONS BUT ALSO BREAK UP MOLECULES INTO THEIR COMPONENT PARTS OF ATOMS RADICALS EXCIT ED STATES AND SO ON 4HE GAS MOLECULES ARE BOUND TOGETHER BY COVALENT BONDS WHICH CONSIST OF TWO SHARED ELECTRONS FOR EACH BOND THERE ARE DOUBLE AND TRIPLE BONDS FOR SOME MOLECULES )F ONE OR MORE OF THOSE ELECTRONS IS KNOCKED AWAY THEN SOMETIMES RATHER THAN PRODUCING AN ION THE BOND WILL BE BROKEN AND THE MOLECULE COMES APART 4HIS ACTION PRODUCES THE hCHEMICAL SOUPv THAT EXISTS INSIDE THE ETCH REACTOR &IGURE " ILLUSTRATES SOME OF THE CHEMICAL COMPOSITION OF THE PLASMA 3I/ #& #(& m 3I& #/ 0ASSIVATING 0OLYMER #OATING
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&IGURE " #HEMICAL 3OUP IN A 0LASMA #HEMICAL 2EACTIONS 4HE EASE WITH WHICH A CHEMICAL REACTION TAKES PLACE DEPENDS A LOT UPON THE STRENGTH OF THE BONDS HOLDING THE REACTANTS TOGETHER &OR EXAMPLE THE STRENGTH OF THE CHEMICAL BONDS HOLDING THE SILICON TO THE OXYGEN IN SILICON DIOXIDE IS MORE THAN DOUBLE THE STRENGTH OF THE BOND HOLDING THE SILICON ATOMS TO EACH OTHER IN SINGLE CRYSTAL SILICON .EEDLESS TO SAY SILICON DIOXIDE ETCHES MUCH MORE SLOWLY THAN SILICON IN A GIVEN SET OF CONDITIONS )N THIS SECTION THE METHODS USED TO INCREASE THE ETCH RATE OF SILICON DIOXIDE ARE DISCUSSED
3%#4)/.
0LASMA %TCH 0ROCESS 2EQUIREMENTS 3EVERAL TYPES OF ETCH REACTORS ARE USED IN MANUFACTURING TODAY SEE #HAPTER %TCH TECHNOLOGIES ARE REFERRED TO BY THE REACTION CHAMBER DESIGNS THEY USE PARALLEL PLATE INDUCTIVELY COUPLED %#2 ETC (OWEVER NO MATTER WHAT APPROACH IS USED THE SAME RESULT MUST BE PRODUCED ON THE WAFER (ERE ARE SOME OF THE PLASMA ETCH PROCESS REQUIREMENTS (ERE ARE SOME OF THE PLASMA ETCH PROCESS REQUIREMENTS v (IGH %TCH 2ATE FOR (IGH 4HROUGHPUT 4IME IS MONEY ON THE MANUFACTURING LINE 4HE RATE AT WHICH WAFERS MOVE THROUGH THE LINE MUST BE MAXIMIZED v 5NIFORMITY ! HIGHLY UNIFORM RATE OF lLM REMOVAL ACROSS THE WAFERS SURFACE IS IMPORTANT SO THAT THE ETCH IS COMPLETED AT ALL POINTS ON THE WAFER AT ALMOST THE SAME INSTANT 4HERE IS USUALLY SOME DEGREE OF ATTACK OF THE UNDERLYING lLM IF THE lLM OF INTEREST IS CLEARED FASTER AT ONE REGION ON THE WAFER THEN MORE OF THE UNDERLYING lLM WILL BE REMOVED FROM THAT AREA WHILE THE ETCH IS COMPLETED ON THE REST OF THE WAFER 4HERE IS A STRONG POSSIBILITY OF DAMAGING THE DEVICES IN THAT REGION BECAUSE OF OVER ETCHING v 3ELECTIVITY 4HE OBJECTIVE IS TO ETCH THE lLM OF INTEREST AND NOT ATTACK ANY OTHER lLMS ON THE WAFER 5NFORTUNATELY THAT IS RARELY POSSIBLE 3TRATEGIES THAT WILL MINIMIZE THE ATTACK OF THE UNDERLYING lLM AND THE MASKING MATERIAL WILL BE DISCUSSED FOR EACH ETCH v 3IDEWALL 0ROlLE #ONTROL 4HE ABILITY TO CONTROL THE SHAPE OF THE FEATURES BEING ETCHED IS CRITICAL FOR MOST ETCHES 4HE SIDEWALL SLOPE AND OTHER KEY SHAPES WILL BE DISCUSSED FOR EACH APPLICATION
!PPENDIX " 0LASMA %TCH 3UPPLEMENT TO #HAPTER 4HERE ARE MANY ADDITIONAL REQUIREMENTS SPECIlC TO PARTICULAR APPLICATIONS 4HESE ARE USUALLY THE HIGHEST PRIORITY 4HE REFERENCES IN THE "IBLIOGRAPHY OFFER IDEAS FOR FURTHER READING
"IBLIOGRAPHY
#ROPPER 7ILLIAM ( 'REAT 0HYSICISTS 4HE ,IFE AND 4IMES OF ,EADING 0HYSICISTS FROM 'ALILEO TO (AWKING .EW 9ORK /XFORD 5NIVERSITY 0RESS 3ZE 3- 0HYSICS OF 3EMICONDUCTOR $EVICES 3ECOND %DITION *OHN 7ILEY 3ONS (ALLIDAY $AVID 2OBERT 2ESNICK AND *EARL 7ALKER &UNDAMENTALS OF 0HYSICS %XTENDED &IFTH %DITION *OHN 7ILEY 3ONS "ROWN 4HEODORE , AND ( %UGENE ,E-AY *R #HEMISTRY THE #ENTRAL 3CIENCE 0RENTICE (ALL )NC 4HE /XFORD !MERICAN $ICTIONARY AND ,ANGUAGE 'UIDE /XFORD 5NIVERSITY 0RESS 7OLF 3 -ICROCHIP -ANUFACTURING ,ATTICE 0RESS 3ZE 3- 6,3) 4ECHNOLOGY "ELL 4ELEPHONE ,ABORATORIES )NCORPORATED 'HANDHI 3ORAB + 6,3) &ABRICATION 0RINCIPLES 3ILICON AND 'ALLIUM !RSENIDE *OHN 7ILEY SONS )NC 3EMICONDUCTOR )NTEGRATED #IRCUIT &ABRICATION 4ECHNIQUES &AIRCHILD #ORPORATION -ANOS $ENNIS - AND $ANIEL , &LAMM 0LASMA %TCHING !N )NTRODUCTION !CADEMIC 0RESS )NC ,IEBERMAN -ICHAEL ! AND !LLAN * ,ICHTENBERG 0RINCIPLES OF 0LASMA $IS CHARGES AND -ATERIALS 0ROCESSING *OHN 7ILEY 3ONS )NC
"IBLIOGRAPHY #HAPMAN "RIAN 'LOW $ISCHARGE 0ROCESSES 3PUTTERING AND 0LASMA %TCHING *OHN 7ILEY 3ONS )NC 2OSSNAGEL 3TEPHEN - *EROME * #UOMO AND 7ILLIAM $ 7ESTWOOD (ANDBOOK OF 0LASMA 0ROCESSING 4ECHNOLOGY &UNDAMENTALS %TCHING $EPOSITION AND 3UR FACE )NTERACTIONS .OYES 0UBLICATIONS (EYNES -ICHAEL AND !NNE + -ILLER )NTEGRATED #IRCUIT 3YNOPSIS 4HIRD %DITION 3EMICONDUCTOR 3ERVICES (EYNES -ICHAEL AND !NNE + -ILLER 3EMICONDUCTOR 4ERMINOLOGY n 'RAPHIC 'LOSSARY OF 4ERMS &OURTH %DITION 3EMICONDUCTOR 3ERVICES -AKING THE -ICROCHIP !T THE ,IMITS ))) 6IDEO 4RAINING #OURSE 3EMICONDUCTOR 3ERVICES %VANS + ! -ILLER AND 0 6AN :ANT #LEANROOM 4ECHNOLOGY -ANUAL 3ECOND %DITION 3EMICONDUCTOR 3ERVICES 6AN :ANT 0ETER -ICROCHIP &ABRICATION &IFTH %DITION -C'RAW (ILL 'ISE 0ETER % "LANCHARD 2ICHARD 3EMICONDUCTOR AND )NTEGRATED #IRCUIT &ABRI CATION 4ECHNIQUES 2ESTON 0UBLISHING #OMPANY )NC 6AN .OSTRANDS 3CIENTIlC %NCYCLOPEDIA &IFTH %D ,ITTON %DUCATIONAL 0UBLISH ING )NC #2$ (ANDBOOK OF #HEMISTRY AND 0HYSICS TH %D n #2# 0RESS )NC 0LUMMER *AMES $ $EAL -ICHAEL $ 'RIFlN 0ETER " 3ILICON 6,3) 4ECHNOL OGY 0RENTICE (ALL )NC 4HE 3EMICONDUCTOR 0ICTURE $ICTIONARY $- $ATA )NC
)NDEX
3YMBOLS
#
($0 #6$
CHEMICAL COMPOUND CHEMICAL MECHANICAL POLISHING #-0 CHEMICAL VAPOR DEPOSITION #6$ CHEMISTRY CLEANROOM #-/3 DEVICES COMPLEMENTARY METAL OXIDE SEMICONDUCTOR #-/3 COMPOUND SEMICONDUCTORS COMPUTER AIDED DESIGN #!$ CONTACT HOLE
! ACTIVATED ACTIVE AREA ADHESION LAYER ADSORBED AFTER DEVELOP INSPECTION !$) !NGSTROM !NGSTROM UNIT ANNEAL SPIKE ANNEALING ASHING ASPECT RATIO ATOMIC LAYER DEPOSITION !,$ AUTOMATED MATERIAL HANDLING SYSTEMS !-(3
" BACK GRINDING BACK LAPPING BARRIER LAYER BINNING BIT BONDING PADS BUNNY SUIT BYTE
$ DEIONIZED WATER $) WATER DELAMINATE PEEL OFF DEPLETION REGION DESIGN ENGINEER DESIGN RULES DESIGN RULE CHECKS $2# DESIGN RULE SETS DESIGN VERIlCATION DIE ATTACH DIE BONDING DIELECTRICS HIGH K LOW K DIFFUSION DOPANTS ACTIVATED
)NDEX N TYPE P TYPE DRY ETCHING DUAL DAMASCENE $$ DYNAMIC RANDOM ACCESS MEMORY $2!-
% EFmUENT ELECTRIC CHARGE ELECTRIC CURRENT ELECTRIC lELD ELECTROCHEMICAL DEPOSITION %#$ ELECTROMAGNET ELECTROMIGRATION ELECTRONICS GRADE SILICON %'3 ELECTROPLATING ENCAPSULATION EPITAXIAL SILICON EPI EXCITED STATE EXPOSURE EXPOSURE lELD
& FABRICATION AREA lELD EFFECT TRANSISTOR lNAL TEST mIP CHIP BONDING mUID FOUNDRY FUNCTION TEST
' GAS GATE DIELECTRIC GERMANIUM 'E GETTER GLUE LAYER
( HALOGENS HARD MASK HIGH K DIELECTRICS HIGH K GATE DIELECTRICS HIGH ASPECT RATIO CONTACT (!2#
) )))n6 SEMICONDUCTORS IMPLANT MASK INERT GASES INGOT INLINE PACKAGE INTEGRATED CIRCUIT )# INTERLEVEL DIELECTRIC ),$ INTERMETAL DIELECTRIC )-$ INVERSE SQUARE LAW IN SPEC ISOTROPIC
* JUNCTION SPIKING
+ K IS THE DIELECTRIC CONSTANT
, LATCH UP LAYOUT DESIGNER LAYOUT ENGINEER LAYOUT VERSUS SCHEMATIC ,63 LIGHTLY DOPED DRAIN ,$$ LIGHT EMITTING DIODES ,%$S LITHOGRAPHY LOGIC ENGINEER LOW K DIELECTRICS LOW K DIELECTRIC MATERIALS LOW PRESSURE #6$ ,0#6$
MAGNETIC lELD METAL INTERCONNECTS METAL OXIDE SEMICONDUCTOR lELD EFFECT TRANSISTOR -/3&%4 MICRON MICROPROCESSORS MIL SPEC MILITARY APPLICATIONS MOLECULE MONITOR WAFERS -OORES ,AW
)NDEX .
2
N TYPE NATIVE OXIDE NEW PRODUCT PLAN .00 NOBLE GASES
RAPID THERMAL PROCESSOR 240 REACTANTS RECTIlER REENTRANT PROlLES UNDERCUTTING RESIST TRIMMING RETICLE
0 P TYPE PAD OXIDE PARALLEL PLATE CAPACITOR PARASITIC CAPACITANCE PASSIVATION PELLICLES PHASE SHIFT MASK PHASE SHIFT MASK CHECK PHOTOLITHOGRAPHY PHOTOMASK PHOTORESIST RESIST RETICLE PHOTOMASKRETICLE PHOTORESIST RESIST PHOTORESIST ASHING PURPOSE PHOTORESIST STRIPPING PHYSICAL VAPOR DEPOSITION 06$ PILOT WAFERS PLANARIZATION PLASMA PLASMA ENHANCED #6$ 0%#6$ PLASMA ETCH PLUG PN JUNCTION POLYCIDE POLYCRYSTALLINE POLY POTENTIAL DIFFERENCE PRE METAL DIELECTRIC 0-$ PROBE PRODUCT DElNITION PROTECTIVE PASSIVATION
1 QUARTZ QUARTZ GLASS
3 SACRIlCIAL OXIDE SALICIDE SCANNING ELECTRON MICROSCOPES 3%- SCHEMATIC SCRIBE LINE SCRUBBERS SELF ALIGNED GATE SEMICONDUCTOR SHALLOW TRENCH SHALLOW TRENCH ISOLATION 34) SHEARING STRESS SIDEWALL PASSIVATION SILICA SILICIDES SILICON 3I POLYCRYSTALLINE POLY SINGLE CRYSTAL SILICON DIOXIDE SILICON NITRIDE NITRIDE SILICON ON INSULATOR 3/) SIMULATIONS SINGLE CRYSTAL SOFTWARE ENGINEERS SOLID STATE DEVICE SOURCE AND DRAIN SPACER SPECIlCATIONS SPIKE ANNEAL SPIN ON DIELECTRIC 3/$ SPIN ON GLASS 3/' SPUTTERING STANDARD MECHANICAL INTERFACE 3-)& STATIC RANDOM ACCESS MEMORY 32!- STEP AND REPEAT REDUCTION PROJECTION PRINTING STEP AND SCAN STEPPER
)NDEX STREET SUBSTRATE SURFACTANTS
4 TAPEOUT TAPE AUTOMATED BONDING 4!" TEST WAFERS THERMAL BUDGET THERMAL OXIDATION OF SILICON THERMAL OXIDE THROUGHPUT TRENCH ETCH TRENCH lLL PROCESS
5 UNDERCUTTING
6 VERTICAL LAMINAR mOW 6,& VIA
7 WAFER SORT WELL WELL DIFFUSION WELL DRIVE IN WET ETCH
9 YELLOW ROOM
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