Communication Systems and Information Technology, Volume 4

Lecture Notes in Electrical Engineering Volume 100

Ming Ma (Ed.)

Communication Systems and Information Technology Selected Papers from the 2011 International Conference on Electric and Electronics (EEIC 2011) in Nanchang, China on June 20-22, 2011, Volume 4

ABC

Ming Ma NUS ACM Chapter 81 Victoria Street, Singapore 188065, Singapore E-mail: [email protected]

ISBN 978-3-642-21761-6

e-ISBN 978-3-642-21762-3

DOI 10.1007/978-3-642-21762-3 Lecture Notes in Electrical Engineering

ISSN 1876-1100

Library of Congress Control Number: 2011929654 c 2011 Springer-Verlag Berlin Heidelberg  This work is subject to copyright. All rights are reserved, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilm or in any other way, and storage in data banks. Duplication of this publication or parts thereof is permitted only under the provisions of the German Copyright Law of September 9, 1965, in its current version, and permission for use must always be obtained from Springer. Violations are liable to prosecution under the German Copyright Law. The use of general descriptive names, registered names, trademarks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. Typeset & Cover Design: Scientific Publishing Services Pvt. Ltd., Chennai, India. Printed on acid-free paper 987654321 springer.com

EEIC 2011 Preface

The present book includes extended and revised versions of a set of selected papers from the International Conference on Electric and Electronics (EEIC 2011), held on June 20–22, 2011, which is jointly organized by Nanchang University, Springer, and IEEE IAS Nanchang Chapter. The goal of EEIC 2011 is to bring together the researchers from academia and industry as well as practitioners to share ideas, problems and solutions relating to the multifaceted aspects of Electric and Electronics. Being crucial for the development of Electric and Electronics, our conference encompasses a large number of research topics and applications: from Circuits and Systems to Computers and Information Technology; from Communication Systems to Signal Processing and other related topics are included in the scope of this conference. In order to ensure high-quality of our international conference, we have high-quality reviewing course, our reviewing experts are from home and abroad and low-quality papers have been refused. All accepted papers will be published by Lecture Notes in Electrical Engineering (Springer). EEIC 2011 is sponsored by Nanchang University, China. Nanchang University is a comprehensive university which characterized by "Penetration of Arts, Science, Engineering and Medicine subjects, Combination of studying, research and production". It is one of the national "211" Project key universities that jointly constructed by the People's Government of Jiangxi Province and the Ministry of Education. It is also an important base of talents cultivation, scientific researching and transferring of the researching accomplishment into practical use for both Jiangxi Province and the country. Welcome to Nanchang, China. Nanchang is a beautiful city with the Gan River, the mother river of local people, traversing through the whole city. Water is her soul or in other words water carries all her beauty. Lakes and rivers in or around Nanchang bring a special kind of charm to the city. Nanchang is honored as 'a green pearl in the southern part of China' thanks to its clear water, fresh air and great inner city virescence. Long and splendid history endows Nanchang with many cultural relics, among which the Tengwang Pavilion is the most famous. It is no exaggeration to say that Tengwang Pavilion is the pride of all the locals in Nanchang. Many men of letters left their handwritings here which tremendously enhance its classical charm. Noting can be done without the help of the program chairs, organization staff, and the members of the program committees. Thank you. EEIC 2011 will be the most comprehensive Conference focused on the various aspects of advances in Electric and Electronics. Our Conference provides a chance for academic and industry professionals to discuss recent progress in the area of Electric and Electronics. We are confident that the conference program will give you detailed insight into the new trends, and we are looking forward to meeting you at this worldclass event in Nanchang.

EEIC 2011 Organization

Honor Chairs Prof. Chin-Chen Chang Prof. Jun Wang

Feng Chia University, Taiwan Chinese University of Hong Kong, HongKong

Scholarship Committee Chairs Chin-Chen Chang Jun Wang

Feng Chia University, Taiwan Chinese University of Hong Kong, HongKong

Scholarship Committee Co- chairs Zhi Hu Min Zhu

IEEE IAS Nanchang Chapter, China IEEE IAS Nanchang Chapter, China

Organizing Co-chairs Jian Lee Wensong Hu

Hubei Normal University, China Nanchang University, China

Program Committee Chairs Honghua Tan

Wuhan Institute of Technology, China

Publication Chairs Wensong Hu Zhu Min Xiaofeng Wan Ming Ma

Nanchang University, China Nanchang University, China Nanchang University, China NUS ACM Chapter, Singapore

Contents

The Design and Implementation of DDR PHY Static Low-Power Optimization Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wei Ge, Mengnan Zhao, Cheng Wu, Jun He Design on Triple Bi-directional DC/DC Converter Used for Power Flow Control of Energy Storage in Wind Power System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Yanlei Zhao, Naiyong Xia, Housheng Zhang ESL Based SoC System Bandwidth Estimation Method . . . . . . . . Zhen Xie, Xinning Liu, Weiwei Shan, Wei Ge Cellular Automaton for Super-Paramagnetic Clustering of Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Zhang Botao, Zhang Shuqiang, Yu Zhongqiu Embedded Memory Wrapper Based on IEEE 1500 Standard . . . . Maryam Songhorzadeh, Rahebeh Niaraki Asli A SVPWM Control Strategy for Neutral Point Potential Compensation in Three-Level Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . Jinsong Kang, Yichuan Niu Process Mining: A Block-Structured Mining Approach . . . . . . . . . Yan-liang Qu, Tie-shi Zhao China RoHS: How the Changing Regulatory Landscape Is Affecting Process Equipment Reliability . . . . . . . . . . . . . . . . . . . . . . . . Chris Muller, Henry Yu Building Process Models Based on Interval Logs . . . . . . . . . . . . . . . . Yan-liang Qu, Tie-shi Zhao

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Fostering a Management Model of Librarians at Vocational College e-Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ling-Feng Hsieh, Mu-Chen Wu, Jiung-Bin Chin

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Extension 2D to 3D of FAN Transform in Image . . . . . . . . . . . . . . . . Fan Jing, Xuan Ying, Li Honglian

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A Design of Low Cost Infrared Multi-touch System . . . . . . . . . . . . . Juan Wu, Yao-hui Hu, Guo-qiang Lv, Jing Yin

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A Review of Research on Network-on-Chip Simulator . . . . . . . . . . 103 Haiyun Gu Design Methodology of Dynamically Reconfigurable Network-on-Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Haiyun Gu Numerical Simulation Study on a Flat-Plate Solar Air Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Wenfang Li, Shuhui Xu, Haiguang Dong, Jun You Artificial Immune for Harmful Information Filtering . . . . . . . . . . . . 125 Yan Sun, Xue guang Zhou Identification and Pre-distortion for GaN-PA . . . . . . . . . . . . . . . . . . . 133 Yuanming Ding, Yan Wang, Akira Sano On-Line Monitoring System of Methane Reaction Generator . . . 141 Ma Baoji Security Flaws in Two RFID Lightweight Authentication Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Wang Shaohui Study on Mechanical Parameters in Finite Element Analysis of Children’s Orbital-Bone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Weiyuan Lu, Zhixiang Liu, Xiuqing Qian, Tingting Ning, Huagang Yan 3D Model Retrieval Based on Multi-View SIFT Feature . . . . . . . . 163 Shungang Hua, Qiuxin Jiang, Qing Zhong Current Issues and Future Trends in Analysis of Automotive Functional Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Chunyang Mu, Xing Ma, Hongxing Ma, Xianlian Huang, Ling Zhang, Rong Fan Development of an Automatic Steering System for Electric Power Steering (EPS) System Using Fuzzy Control Theory . . . . . 179 Tao Hong, Xijun Zhao, Yong Zhai

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Design and Implementation of Interactive Digital Shadow Simulation System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Qian Li, Qing-yi Hua, Jun Feng, Wei Niu, Hao Wang, Jie Zhong Weighing Machine Modifications for Purblind and Sightless People . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Vladimir Kasik, Martin Stankus Active RFID Based Infant Security System . . . . . . . . . . . . . . . . . . . . . 203 Lin Lin, Nan Yu, Tao Wang, Changan Zhan Modified Segmentation Prony Algorithm and Its Application in Analysis of Subsynchronous Oscillation . . . . . . . . . . . . . . . . . . . . . . 211 Yujiong Gu, Dongchao Chen, Tiezheng Jin, Zhizheng Ren Group Control Strategy of Welding Machine Based on Improved Active Set Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Chen Shujin, Zhang Junjun Simulation and Experiment Research on the Effects of DC-Bias Current on the 500kV Power Transformer . . . . . . . . . . . . . 227 Feng-hua Wang, Jun Zhang, Cheng-yu Gu, Zhi-jian Jin A HID Lamp Model in Simulink Based on the Principle of Electric Arc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Xiaohan Guan, Zhongpeng Li Coordinated Control for Complex Dynamic Interconnected Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Xin-yu Ouyang, Xue-bo Chen Study on Calibration of Transfer Character of Ultrasonic Transducer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Qiufeng Li, Quanhong Zhang, Min Zhao, Lihua Shi A Novel Non-contact Pulse Information Detection Method Based on the Infrared Sequence Images . . . . . . . . . . . . . . . . . . . . . . . . . 259 Weibin Zhou, Bin Jing, Dian Qu, Guihong Yuan, Chunyan Wang, Haiyun Li A Method of Neurons Classification and Identification . . . . . . . . . . 267 Xingfu Li, Donghuan Lv A Broadband Image-Rejection Sub-harmonically Pumped Mixer MMIC for Ka-band Applications . . . . . . . . . . . . . . . . . . . . . . . . 275 Fang-Yue Ma, Yang-Yang Peng, Xiao-Ying Wang, Wen-Quan Sui

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Study of Phase-Shift Laser Ranging on Travelling Crane Anti-collision System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 Bisheng Cao, Zhou Wan, Zhongguo Jing, Xin Xiong Bearing Condition Monitoring and Fault Diagnosis of a Wind Turbine Using Parameter Free Detection . . . . . . . . . . . . . . . . . . . . . . . 289 Shenggang Yang, Xiaoli Li, Ming Liang An Approach of K-Barrier Coverage of WSN for Mine . . . . . . . . . 295 Qianping Wang, Liangying Wang, Rui Zhou, Dong Jiang Design and Implementation of Intrusion Detection System . . . . . 303 Tai-ping Mo, Jian-hua Wang Self Tuning PID Controller for Main Steam Temperature in the Power Plant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 Amin Aeenmehr, Alireza Sina A Novel Transformerless Single-Phase Three-Level Photovoltaic Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 Xiaoguang Yang, Youhua Wang Image Reconstruction Algorithm Based on Fixed-Point Iteration for Electrical Capacitance Tomography . . . . . . . . . . . . . . . . 325 Cuihuan Li, Xiaoguang Yang, Youhua Wang Research on Data Preprocessing in Exam Analysis System . . . . . 333 Ming-hua Zhu The Development and Application of Environmental Art Project Which Based on Semiotics in Information Age . . . . . . . . . 339 Ke Zuo Rotor Time Constant Estimation for the Vector Controlled Induction Motor Drive Based on MARS Scheme . . . . . . . . . . . . . . . 345 Hua Li, Shunyuan Zhou Small-World Request Routing System in CDNs . . . . . . . . . . . . . . . . . 353 Lan Li Experimental Study on Simulated Cerebral Edema Detection with PSSMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 Gui Jin, Mingxin Qin, Chao Wang, Wanyou Guo, Lin Xu, Xu Ning, Jia Xu, Dandan Gao Medium Choice of Chinese Consumers in Obtaining Advertising Information about Minitype Automobile . . . . . . . . . . . 369 Dao-ping Chen

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The Finite Element Modeling for Mechanical Feature Analysis of Human Lumbar L4-L5 Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 Juying Huang, Haiyun Li, Hao Wu Hybrid Control Using Sampling PI and Fuzzy Control Methods for Large Inertia and Time Delay System . . . . . . . . . . . . . 387 Jia Xie, Shengdun Zhao, Zhenghui Sha, Jintao Liang An Operator Controllable Authentication and Charging Solution for Application Store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 Jianbing Xing, Zhaoxia Li, Xiongwei Jia, Zizhi Qiao A Modified Kalman Filter for Non-gaussian Measurement Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 Muhmmad J. Mirza A Novel Framework for Active Detection of HTTP Based Attacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 Liang Jie, Sun Jianwei, Hu Changzhen Model Predictive Control for Single Phase Inverters . . . . . . . . . . . . 419 Yecheng Lv, Ningxiang Xie, Kai Wang Evaluation Method and Standard on Maintainability of Cockpit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 Junwei Zhao, Lin Zhou, Haitao Zhao, Xuming Mao, Youchao Sun Smart Mobile User Adaptive System with Autonomous Sensor Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 Ondrej Krejcar, Robert Frischer Reduction of Player’s Weight by Active Playing Using Motion Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 Ondrej Krejcar, Dalibor Janckulik Use of Neural Networks Library for Material Defect Detection Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 Ondrej Krejcar Multi-sensor Measurement Fusion via Adaptive State Estimator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 Li-Wei Fong A Simple Automatic Outlier Regions Detection . . . . . . . . . . . . . . . . . 463 Kitti Koonsanit The Feature Parameters Algorithm of Digital Signal in Circuit Based on Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 Xiaodong Ma, Guangyan Zhao, Yufeng Sun

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Research of Stereo Matching Based on Improved Median Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 Huiyan Jiang, Rui Gao, Xiaojie Liu Generating Method of Three-Phase Voltage Sag in EV Charging System Performance Testing . . . . . . . . . . . . . . . . . . . . . . . . . . 487 Xiaoming Yue, Hui Fan, Jin Pan, Xiaoguang Hao, Zhimeng Zhang Improved Predictive Control of Grid-Connected PV Inverter with LCL Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 Huijie Xue, Wei Feng, Zilong Yang, Chunsheng Wu, Honghua Xu Study on Application of Demand Prognosticating Model Based on Grey Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 Han Qingtian, Li Lian, Zhang Yi Research on Bayes Reliability Assessment for Test Data . . . . . . . . 509 Han Qingtian, Li Lian, Cui Jia Improved Particle Swarm Optimization by Updating Constraints of PID Control for Real Time Linear Motor Positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 Ying-Hao Li, Yi-Cheng Huang, Jen-Ai Chao Small Form-Factor Driver for Power LEDs Powered with One Element Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 Garate Jose Ignacio, de Diego Jose Miguel, Araujo Jose Angel The Empirical Analysis of the Impact of Industrial Structure on Carbon Emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 Mei Liao, Tianhao Wu An Ant-Routing Algorithm for Wireless Sensor Networks . . . . . . 541 Pengliu Tan, Xiaojun Deng Transient Sensitivity Computations for Large-Scale MOSFET Circuits Using Waveform Relaxation and Adaptive Direct Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 Chen Chun-Jung Incremental Circuit Simulation for Large-Scale MOSFET Circuits with Interconnects Using Iterated Timing Analysis . . . . 557 Chen Chun-Jung Inversion of Array Lateral-Logging Based on LSSVM . . . . . . . . . . . 563 Yu Kong, Li Zhang, Linwei Feng, Yueqin Dun

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Voice Recognition Based on the Theory of Transmission Wave and LSSVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569 Yu Kong, Yue Min, Jing Xiao Design of a Two-Phase Adiabatic Content-Addressable Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 Meng-Chou Chang, Yen-Ting Kuo Branch Importance Assessment under Cut-Off Power Flow Based on EM Clustering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 Feng Yuan, Wang Li-ming, Xia Li, Bu Le-ping, Shao Ying Knowledge Discovery of Energy Management System Based on Prism, FURIA and J48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 Feng Yuan, Xia Li, Wang Li-ming, Pu Le-ping, Shao Ying Study on the Medium-Term and Long-Term Forecast Technology of Wind Farm Power Generation . . . . . . . . . . . . . . . . . . . 601 Yang Gao, Li Liu, Guoyan Liang, Shihai Ma, Chenwei Tian Optimal Space Vector Modulation Control for Three-Phase Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 Su Xiaofang, Rao Binbin, Li Shijie, Zheng Ruilan Optimal Dead-Time Elimination for Voltage Source Inverters . . . 617 Su Xiaofang, Rao Binbin, Zeng Yongsheng Research of the Influence Factors in Single-Phase Inverter Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 Xiaofang Su, Binbin Rao, Chong Chen, Junbo Liu The Inspiration of the Economic Restructuring in Ruhr of Germany to the Sustainable Development of Mining Cities in Henan Province of China . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633 Wang Liping Design of Metal Pipe Defect Detection Device Based on Electromagnetic Guided Wave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 Shuwang Chen, Deliang Li, Zhangsui Xu Implement of Explosion-Proof and Intrinsic Safe Model Mult-protocol Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645 Ming-san Ouyang, Cheng-jie Zhu, Zhe Liang The Application in Mobile Computing of Spatial Association Rules Mining Algorithm Based on Separating Support Items . . . 651 Gang Fang

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Automatic Test Case Generation for Web Applications Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 Lulu Sun, Junyi Li, Shenglan Liu Design of Holmium Laser Treatment Instrument Control System Based on STM32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667 Youjie Zhou, Chunhua Xiong, Changbo Lu Research on Attribute Granular Computing and Its Fuzzification Method Based on Qualitative Mapping . . . . . . . . . . . . 673 Ru Qi Zhou, Yi Lin Wu, Yi Qun Chen A CT Image Denoise Method Using Curvelet Transform . . . . . . . 681 Junmin Deng, Haiyun Li, Hao Wu Research System Optimization of the Wireless Mesh Networks Based on WLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689 Jin Wen Stabilization Control of Chaotic System Based on LaSalle Invariant Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697 Chunchao Shi, Yanqiu Che, Jiang Wang, Xile Wei, Bin Deng, Chunxiao Han Parameter Estimation in a Class of Chaotic System via Adaptive Steady State Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 Chunchao Shi, Yanqiu Che, Chunxiao Han, Jiang Wang, Bin Deng, Xile Wei Algorithms of 3D Segmentation and Reconstruction Based on Teeth CBCT Images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713 Wenjun Zhang A Calculation Method for Series Lagging Correction Based on Root Locus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721 Li Wang The Computer Simulation and Real-Time Control for the Inverted Pendulum System Based on PID . . . . . . . . . . . . . . . . . . . . . . 729 Yong Xin, Bo Xu, Hui Xin, Jian Xu, Lingyan Hu Application of Fractal Dimension in Analysis of Soil Micro Pores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737 Shu-hua Zhang Assessment of Loess Collapsibility with GRNN . . . . . . . . . . . . . . . . . 745 Shu-hua Zhang

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Grey Comprehensive Relational Analysis of Fighting Efficiency Influencing Factors of AEW Radar . . . . . . . . . . . . . . . . . . . 753 Guangdong Liang, Guangshan Lu, An Zhang, Yanbin Shi Diesel Misfire Fault Diagnosis Using Vibration Signal over Cylinder Head . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761 Liu Li-tian, Liao Hong-yun, Chen Xiang-long, Feng Yong-min, Xiao Yun-kui Proof of a Conjecture about k-Graceful Graph . . . . . . . . . . . . . . . . . . 769 Li Wuzhuang, Yan Qiantai High Dynamic GPS Signal Analysis and Acquisition Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773 Xiaoming Han, Guangyu Zheng, Shusheng Peng On the Mutual Information and Capacity of Coded MIMO with Interference Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781 Haitao Li, Haiying Yuan Interdisciplinary Education Model of Fashion Marketing and E-Commerce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789 Zhaoyan, Renli Research on the Image Registration Algorithm Based on Regional Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795 Xiaoyan Cao, Xiangxin Shao, Xinying Li, Chunying Wang, Yan Zhou Accurate Curvature Approximation of 3-Dimension Discrete Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803 Shilin Zhou, Jianping Yin, Xiaolin Yang, Junyun Wu The Research of a Symmetrical Component Method and Dynamic Reactive Power Compensation of Electric Arc Furnace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811 Xuezhe Che, Fenglong Shen, Jianhui Wang Numerical Simulation of Electrokinetic Flow in a Nanotube with Variable Physical Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819 Davood D. Ganji, Mofid Gorji-Bandpy, Mehdi Mostofi Physical Properties of Camellia Oleifera Heated by Micro-wave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827 Jian Zhou, Lijun Li, Yihua Hu, Ke Cheng, Zhiming Yang, Ye Xue Research on Trust-Based Dynamic Role Access Control Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833 Dongping Hu, Guohua Cui, Aihua Yin, Liang Chen

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Design of Special Welding Machine Based on Open CNC System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839 Haibo Lin Optimization Algorithm on the Intelligence Schedule of Pubic Traffic Vehicles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845 Cui Yonghong, Wang Qingrong The Criterion of Intrinsic Safe Circuit Characteristic Based on Electric Arc Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853 Ligong Wang Multiple View Locality Preserving Projections with Pairwise Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859 Xuesong Yin, Qi Huang, Xiaodong Chen Analysis of E-SCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867 Huang Hua, Peng Cong Information Sharing of Partnership in Supply Chain and Enhancement of Core Competitiveness of Enterprises . . . . . . . . . . . 875 Huang Hua, Peng Cong Novel Spatial Diversity Equalizer Suitable for 16-QAM Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885 Rao Wei Fuzzy Logic Controller for a Pneumatic Rotary Actuator . . . . . . . 893 Logah Perumal Evolutionary Neural Network Based on Immune Continuous Ant Colony Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903 Gao Wei Reliable and Delay-Efficient Routing Algorithm in Wireless Sensor Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911 Mohammad Ali Jabraeil Jamali, Adel Fathi, Javad Pashaei Interfacial Impedance Sensor Employing Bio-activated Microbeads and NiHCF-Coated Interdigitated Microelectrodes: A Model Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921 Nuno M.M. Pires, Tao Dong, Zhaochu Yang, Lei Zhang An Improved Fp-Tree Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929 Haijun Zhang, Changchang Zhang, Bo Zhang

Contents

XIX

A Decoupling Method for Evaluating Lightning-Induced Overvoltages on One Certain Line of an Overhead Transmission Lines System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937 Dongming Li, Cheng Wang, Xiaohu Liu Power Flow Calculation in the Voltage Output Stage . . . . . . . . . . . 945 Sun Qiuye, Li Zhongxu, Ma Dazhong, Zhou Jianguo Research on Trajectory Control of Polishing Robot Based on Secondary Deceleration and Dynamic Model . . . . . . . . . . . . . . . . . . . 953 Tongying Guo, Languang Zhao, Haichen Wang Security of Industrial Control System . . . . . . . . . . . . . . . . . . . . . . . . . . . 959 Peng Jie, Liu Li The Application of Automatic Control Theory in Software Engineering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965 Wensong Hu, Xingui Yang, Min Zhu, Yan Zhang Portable MIT-BIH Physiological Signal Playback System Based on Android . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969 Wensong Hu, Li Ming, Min Zhu, Linglin Xia The Application of Network Model on Power Station . . . . . . . . . . . 975 Min Zhu, Wensong Hu, Yan Zhang The Application of Algorithm in Power Station . . . . . . . . . . . . . . . . . 981 Min Zhu, Wensong Hu, Yan Zhang The Application of IP/UDP Protocols in 51 Microcontrollers . . . 987 Wensong Hu, Yuyuan Zhu, Min Zhu, Ke Zuo A Collaborative Filtering Recommendation Algorithm Based on User Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993 Daner Chen The Personalized Recommendation Algorithm Based on Item Semantic Similarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999 Yulong Ying Application Research of Four-Branch Antenna Design by Improved Orthogonal Multi-objective Evolutionary Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005 Jincui Guo, Xiaojuan Zhao, Jinxin Zou

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Research on Aviation Forewarning Systems Based on Business Intelligence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013 Liu Yongjun, Hu Qing, Ruan Wenjuan The Need for Teleradiology System in Medical Remote-Diagnosis Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021 Mohammad H. Al-Taei, Ziyad T. Abdul-Mehdi, Subhi H. Hamdoon The Clustering Methods Based on the Most Similar Relation Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027 Yan Yu, Wei Hong Xu, Yu Shan Bai, Min Zhu Author Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035

The Design and Implementation of DDR PHY Static * Low-Power Optimization Strategies Wei Ge1, Mengnan Zhao1, Cheng Wu1, and Jun He2 1 National ASIC System Engineering Research Center, Southeast University, Nanjing 210096 People's Republic of China {duiker,zmn,wcccc}@seu.edu.cn 2 Huawei Technol. Co., Ltd., Nanjing, China [email protected]

，

Abstract. The static power of DDR PHY has increasingly become the limit of the low-power application of system-on-a-chip (SoC). An optimization of static power based on "behavior" and "state" of DDR PHY static power is proposed, considering the design principle and physical properties. Experimental results show that the proposed optimization strategy can achieve the highest 59.12% reduction in work mode and only 0.723uW power consumption in sleep mode. Keywords: DDR PHY, DDR PAD, Static Power, UPF.

1 Introduction The power consumption of DDR controller has been drawn more and more attention while providing faster transfer rate and higher data bandwidth. At present, low power consumption of DDR PHY research has the following two aspects. 1) Improve the control logic to minimize the number of row opens and closes, and lower the energy consumption during read/write operations [1]. Reshape the memory traffic to coalesce short idle periods into longer ones, thus enabling existing techniques to effectively exploit idleness in the memory [2]. 2) Improve the design of DDR PHY by using the direct clock pulses to latch the data, without a need for additional pulse generator circuitry for the clock signal, which lowers the clock dynamic power consumption by factor of 2x [3]. Employ a clock branch-sharing scheme to reduce the number of clocked transistors in the design. The newly proposed design also employs conditional discharge and split-patch techniques to further reduce switching activity and short-circuit currents, respectively [4]. The research above optimized the access method and the structure design, but did not consider the DDR PHY static power of activities and non-activities. We propose innovatively low-power strategies based on "behavior" and "state" which effectively reduce the DDR PHY static power consumption of activities and nonactivities. *

This work was sponsored by the National Scientific Foundation of China (Grant No. 61006029) and Jiangsu Scientific Foundation (Grant No. BK2010165).

M. Ma (Ed.): Communication Systems and Information Technology, LNEE 100, pp. 1–6. springerlink.com © Springer-Verlag Berlin Heidelberg 2011

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2 Design Principle In order to reduce the DDR PHY static power consumption in work mode and support the ultra-low-power mode, both the DDR PAD and the DDR PHY need to be optimized according to different "behavior" and "state". 2.1 Principle of DDR PHY Low-Power Based on Behavior DDR PHY does the jobs of exchanging data with external chip, multilevel conversion, DQS phase shift, etc., and its static Power consumption is mainly comprised of Leakage Power, which does not change with frequency. Static power consumption formula is expressed as:

Psta = Vdd * I SUB

，which I

SUB

W =C V e L 2 ox th

VGS −VT nVth

(1)

From the formula (1), the static power would be close to zero by cutting off the Vdd, thus greatly reducing the static power consumption of DDR PHY.

Fig. 1. Optimization design of DDR PAD

DDR PAD shows high static power consumption under no flipping circumstances. Therefore, the control signals OutputShutDown (OSD) and InputShutDown (ISD) are added to cut off the DDR PAD output and input leakage paths respectively, as shown in figure (1). So that, the leakage current will decrease to nearly zero. 2.2 Principle of DDR PHY Low-Power Based on State The UPF language provides a new way to specify the power requirements of a design and specifies how to create a power supply network to each design element, the behavior of supply nets with respect to each other, and how the logic functionality is extended to support dynamic power switching to design elements.

The Design and Implementation of DDR PHY Static Low-Power Optimization Strategies

3

In order to switch chip from sleep mode to work mode rapidly, the DDR controller should be special designed. "Sub Power Domain" need to be controlled respectively, as shown in figure (2), DDR PHY Domain (DDRPD) and DDR Retention Domain (DDRRD) separated from the power network on chip are provided different power domain optimization methods by the controller in the Always on Domain (AOD).

Fig. 2. DDR PHY power domain design base on UPF

It makes ultra-low-power available by designing different working states for each power domain: 1. NORMAL: each power domain works normally. DDR PHY reduces power consumption through frequencies adjusting. 2. STOP: the kernel of SoC is powered down, and DDRPD power domain works normally, meanwhile the DLL of DDR PHY (Delay Locked Loop) works in Bypass Mode. 3. SLEEP: only AOD and DDRRD power domain are active, DDR PHY offers the least control signals, to ensure the data integrity of the external memory chip.

3 Implementation of Low-Power Design 3.1 DDR PAD Static Optimization Strategy Based on Behavior Based on the design of the DDR interface timing specified in JEDEC specifications, we propose various optimization strategies for different behavior (command, data) operations, which control the switch of DDR PAD static leakage path. For the unidirectional command signals, CMD_OSD always shut down the input channel, and the output path is switched by the CMD_ISD signal when the command is valid. For the bidirectional data signals, DATA_OSD and DATA_ISD make effect only in the valid data operating phase. In order to realize these functions, low-power control logic is added to generate the control signals (OSD and ISD), which make relative responses according to each DDR operation such as read, write, refresh, activate, etc. At the same time, considering the recovery time of PADs after enabling OSD and ISD, there must be enough margin to satisfy the various frequencies requirement in different working states. Figure (3) shows the HSIM simulation result of OSD and ISD under the condition of tsmc 65nm standard library (1.2v Core Vdd, 1.8v PAD Vdd, 25°C). After the validation of OSD and ISD, the PAD current between the power (vmvddq) and ground (vmvssq) changes correspondingly. When the OSD and ISD are valid, the data transfers between

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the chip external and the pad internal. On the contrary, the data path is been cut off. There is a slight current disturbance, which will not impact the function.

Fig. 3. HSIM simulation of DDR PAD

3.2 DDR PHY Power Management Based on State In NORMAL mode, the DDR PHY works normally in SoC. In STOP and SLEEP mode, the external memory chip enters the Self Refresh or Power Down mode, and the DDR PHY need guarantee the control signals (CKE, RESETB) valid to avoid data loss. The kernel of SoC is powered down in STOP mode, so the registers in the DDR PHY are used for latching the command and data signals. In SLEEP mode, except the AOD and DDRRD power domains, the logic of the DDR PHY controller and most of the IO PADs are powered down. For this reason, the signal control and isolation should be taken into consideration in the DDRRD power domain. The detail design of DDRRD is shown in Figure (4). The independent power supply network is separated by ISOLATION PAD, so the DDRRD can work without being influenced when other parts of the chip are powered down. The RETLEC PAD provides internal control signal in SLEEP mode, which automatically lapses when the chip wakes up. The CKE PAD and RESETB PAD provide the necessary control signals for the external memory chip.

Fig. 4. PAD placement of DDR Retention Domain

The Design and Implementation of DDR PHY Static Low-Power Optimization Strategies

5

4 Design Result The DDR PHY static power consumption optimization strategies, based on “behavior” and “state”, can significantly reduce power consumption in work and standby modes. By using tsmc 65nm standard library and Prime Time PX power analysis tools, we can obtain DDR PHY power consumption simulation results in Table (1). The available work modes are defined as follows: SLEEP: the power domains except the AOD and DDRRD are powered down and the chip is in “sleep” state. STOP: the kernel is powered down, only the necessary interrupt applications are reserved to wake up the system. IDLE: the kernel clock is gated, and the chip enters the standby state. NOMAL: chip works normally, typical applications of computing and display work properly. FASTHOT: chip works in high speed, most of the scientific computing, image processing and display applications occupy the memory bandwidth as much as possible. Table 1. DDR PHY power consumption comparison in defferent mode

STATE SLEEP STOP IDLE NORMAL FASTHOT

DDR_PHY_OLD(mW) NULL NULL 227.73 314.84 385.92

DDR_PHY(mW) 0.000723 3.6 92.95 218.4 312

Optimization(%) NULL NULL 59.18 30.63 19.15

Through the above comparison of power consumption simulation in different modes, we can see that the power optimization of the DDR PHY changes antilinear with increasing of the memory access load. The power optimization ratio in FASTHOT mode and IDLE mode are up to 19.15%and 59.18%. Through the low-power domain design based on the “state”, power consumption on DDR PHY just reaches 3.6mW in STOP mode, and ultra-low-power of 0.723uW in SLEEP mode.

5 Conclusions This paper proposed static low-power optimization strategies based on “behavior” and “state”, which effectively reduce the power consumption of DDR PHY in both working state and sleep state. The simulation results show that the strategies not only improve the DDR PHY power characteristic in different operation modes (19.15%~59.18%), but also provide ultra-low-power application methods for SoC (only 0.723uW in SLEEP mode).

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References 1. Dongwook, L., Sungjoo, Y., Kiyoung, C.: Entry control in network-on-chip for memory power reduction. In: International Symposium on Low Power Electronics and Design (ISLPED), pp. 171–176. ACM/IEEE (2008) 2. Hai, H., Shin, K.G., Lefurgy, C., Keller, T.: Improving energy efficiency by making DRAM less randomly accessed. In: International Symposium on Low Power Electronics and Design, pp. 393–398 (2005) 3. Devarapalli, S.V., Zarkesh-Ha, P., Suddarth, S.C.: A robust and low power dual data rate (DDR) flip-flop using c-elements. In: 11th International Symposium on Quality Electronic Design, pp. 147–150 (2010) 4. Peiyi, Z., McNeely, J., Golconda, P., Bayoumi, M.A., Barcenas, R.A., Weidong, K.: LowPower Clock Branch Sharing Double-Edge Triggered Flip-Flop. IEEE Transaction on Very Large Scale Integration (VLSI) Systems 15, 338–345 (2007)

Design on Triple Bi-directional DC/DC Converter Used for Power Flow Control of Energy Storage in Wind Power System* Yanlei Zhao, Naiyong Xia, and Housheng Zhang School of Electrical and Electronic Engineering, Shandong University of Technology Zhangdian District, Zibo, Shandong Province, China [email protected]

Abstract. A triple bi-directional DC/DC converter used for power flow control of energy storage in wind power system is designed. Firstly, the paper analyzes energy flow characteristic of wind power system containing hybrid energy storage (the battery and the supercapacitor). Secondly, working principle of the triple bi-directional DC/DC converter is explained and mathematical model is constructed. Then, based on the model, control unit consisting of voltage outer loop and current inner loop is designed. To ensure the consistency of working state of batteries in parallel, a novel current-sharing strategy is proposed based on battery SOC (state of charge). To realize energy distribution between the battery and the supercapacitor, a one-order low pass filter is used to detach the low frequency component in feedback voltage. The simulation results show that the converter can effectively regulate the load voltage and reasonably distribute the power between both energy storage elements. Keywords: wind power system; energy storage; power flow optimization; bidirectional DC/DC converter.

1 Introduction The ransom fluctuation of output power of wind power system changes grid power flow frequently in terms of direction and size, which will lead to voltage instability, frequency fluctuation and some other power quality problems, threaten the security and stability of power system. Consequently, wind power penetration level in power grid is confined. Equipping with certain amount of energy storage in wind power system can resolve the problems mentioned above. Battery energy storage system has been widely used in renewable energy sources power system, which can smooth power fluctuation of the generation system, enhance dispatching ability of the generation system, improve static and dynamic characteristic of the grid[1]. However, the battery, if solely used in wind power system, has its inherent shortcomings: Firstly, the battery charges and discharges continually, which reduces *

Project Supported by National Natural Science Foundation of China (50807034).

M. Ma (Ed.): Communication Systems and Information Technology, LNEE 100, pp. 7–14. springerlink.com © Springer-Verlag Berlin Heidelberg 2011

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cycle life of the battery; secondly, the battery has small power density and low dynamic response speed, so the battery has no method to compensate many dynamic power quality problems occurring in short time span. The supercapacitor, as a new fast energy storage element, has high power density and long cycle life[2]. The supercapacitor, combinated with the traditional battery and used for power conditioning or power flow optimization in wind power system, can take full advantage of the battery’s superiority of high energy density and the supercapacitor’s superiority of high power density. As a result, energy storage unit in wind power system can be optimized in respects of its performance and cost. The combination of the supercapacitor and the battery generally has three patterns, including direct parallel connection, parallel connection through the inductor and parallel connection through the power converter (DC-DC converter)[3]. With regard to the first two hybrid energy storage types of direct parallel connection and of parallel connection through the inductive, their port voltages vary in wide range in the process of charging and discharging. More adverse is, the energy distribution between two energy storage elements can not be controlled flexibly, so that it’s difficult to fully play the both ones’ respective advantages. While the energy storage unit of parallel connection through power converter can easily control energy flow between both energy storage elements, so the capacity and the performance of energy storage unit can be flexibly optimized. Power converters used in the hybrid energy storage system can be divided into two types: the one of unilateral energy flow and the one of bidirectional energy flow. For power flow optimization and control of wind power system, the energy flow between energy storage unit (DC link) and the public power grid (AC Link) is two-way, correspondingly, the current of the DC-DC converter used in hybrid energy storage unit is also bidirectional. On the basis of the energy flow characteristic in wind power system containing power flow optimization by virtue of hybrid energy storage, the paper designs a triple bi-directional DC/DC converter used for energy flow control of the hybrid energy storage unit.

2 Energy Flow Characteristic in Wind Power System Containing Power Flow Optimization The ultimate goal of power flow optimization of wind power system is to restrain the power fluctuation, which is based on the balances of the active power as well as the reactive power. Therefore, the fundamental functions of power flow optimization system have two: one is to smooth the active power flowing into the grid in real time; another is to compensate reactive power flowing into the grid in real time. According to these basic functions, the overall layout of the wind power system containing power flow optimization is shown in Figure 1. Suppose, in the whole wind power system, output power of wind generation is denoted as PWG ; charging( or discharging) power of energy storage unit is denoted as PS , of which, charging( or discharging) power of the supercapacitor is denoted as

PC , the battery PB ; the power flowing into the grid is denoted as PG . Because of

Design on Triple Bi-directional DC/DC Converter

9

randomness and uncertainty of wind energy, PWG is obviously randomly fluctuant. If, without any compensation,

PWG is directly transported into the grid, the voltage, the

frequency and some other parameters of the local grid are will be influenced negatively. Fluctuations components in wind energy of above 1Hz can be absorbed by the inertia of generation system, while the components of 0.01Hz ~ 1Hz have the maximum impact on the grid in terms of the voltage, the frequency and other performances[4]. And the ones of below 0.01Hz directly affect the capacity reliability of generation system. To restrain the negative impact of wind power, its power flow optimization system should smooth the active power injected into the power grid. That is to say, of the output power of the wind generation system, only the components of relatively low frequency(lower than 0.01Hz) is transported into the public grid, while the higher frequency components should be absorbed by the energy storage. Apparently that the power absorbed by energy storage is PS = PWG − PG , which may be flexibly controlled by a four-quadrant DC-AC converter. Power Grid Grid Voltage

Wind Power System output current

Wind Power System

Wind Power System gridconnected Converter

Power Flow Optimization Control Strategy

Controller)

Control Strategy for Power Flow of Energy Storage

Battery State of Charge(SOC)

Storage Battery

Four-quadrant converter (Power Flow Optimization

Bi-direction DC converter Power Flow of Energy Storage

DC Voltage

Super-Capacitor

Fig. 1. The overall layout of the wind power system containing power flow optimization

Of two energy storage elements, the supercapacitor has high power density and lower energy density; while the battery has low power density, high energy density and short cycle life. Hence, in the process of power flow optimization, the charging (discharging) times of the battery should be reduced to less as far as possible. That is,

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the relatively lower frequency components of the wind power are taken by the battery, while the remaining higher frequency components are borne by the supercapacitor. The energy between the two energy storage devices is controlled by the bi-directional DC-DC converter designed by the paper.

3 Design on Triple Bi-directional DC/DC Converter 3.1 Working Principle and Small-Signal Model In the wind power system of comparatively large power, the batteries generally need to be paralleled to meet the power demand. Due to individual differences in feature, the charging (discharging) current of various sub-unit may be different, which easily lead to the problems of over-charge or under charge. Obviously, the number of directly parallel individuals is larger, the imbalance problem is more serious. To reduce the number of batteries directly in parallel and to ease the charging (discharging) imbalance problem, in this paper, the triple two-way DC-DC converter is adopted, which can decrease the number of batteries directly in parallel and flexibly control charging (discharging) currents of the three groups of batteries. At the same time, multiple combinations of the conversion circuit can increase the transmission power and reduce current ripple as well as the filter components (inductors, capacitors) parameters. The topology of the converter is shown by Fig. 2.

vo v1i

v 2i

v 3i

Fig. 2. The topology of the triple two-way DC-DC converter

The control of the converter is based on PWM. The switches S1~S6 and D1~D6 are composed of power electronics device such as IGBT and diode. If the switches S1, S3, S5 operate in PWM mode, and the switches S2, S4, S6 are always off, the converter runs in Buck chopper mode. While the switches S2, S4, S6 operate in PWM mode, and the switches S1, S3, S5 are always off, the converter runs in Boost chopper mode. When the switching state of S1, S3, S5 and the ones of S2, S4, S6 are opposite each other, and all operate in PWM mode, the converter is in the unified working mode, i.e. Buck-Boost chopper. In a switching cycle of Buck-Boost chopper, its inductor current may be two-way, which can increase response speed[5], so the third mode is chosen in the paper.

Design on Triple Bi-directional DC/DC Converter

11

Because the topology and the control method of three sub-units are identical in the triple converter, as for modeling and analysis, only an independent sub-unit is taken into account. An independent bi-directional DC-DC converter sub-unit is shown in Fig. 3.

L

vo

S1

i

C

S2

vi

R

Fig. 3. An independent bi-directional DC-DC converter ∧

L

Vo d (t ) −

+

D′ :1

+

vˆi (t )

+

∧

i (t )

Idˆ (t )

C

R

vˆo (t ) −

Fig. 4. Small signal AC equivalent circuit model of Buck-Boost

In Fig. 3, vi , i , vo and R respectively stand for the battery voltage, the battery current, the supercapacitor voltage and the equivalent load resistance. By virtue of average switch modeling method, the small signal AC linear equivalent circuit model of Buck-Boost can be obtained and shown as Fig. 4. In Fig. 4, d (t ) is the duty ratio of the bottom switch (S2), D is the value of ∧

d (t ) in quiescent operation point, and d (t ) is the perturbation of d (t ) . ∧

Based on the linear equivalent circuit, the transfer function of duty cycle

d ( s ) to

∧

output voltage

vo ( s) Gvd ( S ) =

vˆo ( S ) dˆ ( S ) vˆi ( S )=0

=

D′Vo (1 − LCS 2 +

LS ) RD′2

L S + D′2 R

(1)

3.2 Control Strategy According to the overall structure of wind power system with energy storage, the energy exchange between power flow optimization system and the public grid can be reflected in the fluctuation of the DC bus voltage. If the relatively low frequency components of PS is expected to be absorbed by the battery, the lower frequency

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components of the DC bus instantaneous voltage should be detached by a low pass filter and be stabilized to a given value. Considering response speed, an one-order low pass filter is chosen in the paper. To ensure that the battery absorbs the relatively lower frequency energy fluctuation, firstly, the voltage regulation control loop for the low frequency components of transient DC bus voltage is necessary, which ensure super-capacitor voltage is constant at the low frequency. To guarantee the charge state of three paralleled battery groups are identical, this paper proposed a current-sharing strategy based on the battery SOC (state of charge). For the battery, SOC

=

QC

QI

, where: QC is the residual capacity,

QI is the rated

capacity under a constant discharge current. In the process of current-sharing, for an independent sub-unit of the triple converter, the SOC of the corresponding battery group is higher, its average inductor current is larger, Conversely, the SOC lower, the current smaller. As a result, this can make the SOC of three battery groups tend to no difference. On the basis mentioned above, the paper proposes the control strategy of triple bidirectional DC-DC converter consisting of voltage outer loop and current inner loop, whose structure is shown as Fig. 5.

I ref

1 SOC1 I ref ∑ SOCi

LS ) RD′2 L LCS 2 + S + D′2 R D′Vo (1 −

kip s + kii s

i =1, 2,3

ki * U dc

kup s + kui s

I ref

3 I ref

SOC3

∑ SOC

i =1, 2,3

LS ) RD′2 L LCS 2 + S + D′2 R D′Vo (1 −

kip s + kii s

i

ki 1 1+τ 2s

ku

Fig. 5. The control structure of triple bi-directional DC-DC converter

According to [6], the parameter of the regulator

kip , kii , kup and kui can be

determined.

4 Simulation Results Based on Matalab / Smulink, the triple bi-directional DC converter is simulated. In the converter, the nominal voltage of the battery is 72V, the expected voltage of the supercapacitor (load voltage) is 200V, kip = 10 , kii = 60 , kup = 6

Design on Triple Bi-directional DC/DC Converter

and

13

kui = 10 , SOC1 = SOC2 = SOC3 , τ 2 = 0.01 . When the equivalent load

current (discharging current) varied in the case shown by

Fig. 6. (A) Charging current of the supercapacitor (B) Real voltage of the supercapacitor

Fig. 7. The currents of three sub-units of triple bi-directional DC-DC converter

Fig. 6 (A), under the control strategy proposed by the paper, the real-time voltage of the supercapacitor is illustrated as Fig. 6 (B), and the currents of three sub-units are shown as Fig. 7. Seen from the two figures, the relatively lower frequency components of load current (power) are undertaken by the battery, while the remaining higher frequency

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components are undertaken by the supercapacitor. The simulation results indicate that the converter can not only reasonably distribute the power between two energy storage elements but effectively regulate the load voltage.

5 Conclusions The design on a triple bi-directional DC/DC converter used for power flow control of energy storage in wind power system are discussed. The paper designs control unit of the converter with voltage outer loop and current inner loop, which includes a novel current-sharing strategy based on battery SOC and uses a one-order low pass filter to detach the low frequency component in feedback voltage. The simulation results show that the converter can effectively regulate the load voltage and reasonably distribute the power between both energy storage elements with comparatively good static and dynamic characteristic.

Acknowledgments This paper and its related research are supported by National Natural Science Foundation of China (50807034) and Support Program for Young Teachers Development of Shandong University of Technology.

References 1. Yang, Z., Shen, C., Zhang, L., et al.: Integration of a StaCom and Battery Energy System Storage. IEEE Trans on Power System 16(2), 254–260 (2001) 2. Andrew, B.: Ultracapacitors: Why, How, and Where is the Technology. Journal of Power Sources 91, 37–50 (2000) 3. Tang, X., Qi, Z.: Study on the Ultracapacitor/Battery Hhybrid System. Chinese Journal of Power Sources 30(11), 933–936 (2006) 4. Luo, C., Ooi, B.-T.: Frequency Deviation of Thermal Power Plants Due to Wind Farms. IEEE Trans. on Energy Conversion 21(3), 708–716 (2006) 5. Wang, Z., Liu, J.: Power Electronics Technology. China Machine Press (May 2009) 6. Xu, D.: PowervElectronics System Modeling and Control. China Machine Press (January 2006)

ESL Based SoC System Bandwidth Estimation Method* Zhen Xie, Xinning Liu, Weiwei Shan, and Wei Ge National ASIC System Engineering Research Center, Southeast University, Nanjing 210096 People's Republic of China {xz,xinning.liu,wwshan,duiker}@seu.edu.cn

，

Abstract. The increasing complexity of system-on-a-chip (SoC) design is challenging the design engineers to estimate the system bandwidth. A method of SoC system bandwidth estimation based on electronic-system-level (ESL) is proposed, which estimates the system bandwidth by transaction-level-modeling (TLM) and analysis depended on simulation. Compared with the traditional RTL simulation, the estimation is effective and the simulation speed is more than two orders of magnitude faster. Keywords: ESL, SoC, TLM, Bandwidth estimation.

1 Introduction Bandwidth is always one of the bottlenecks in system-on-a-chip (SoC) systems. The increasing complexity of SoC design is challenging the design engineers to estimate the bandwidth. If the bandwidth is unable to well fit the requirement, the designer can modify the architecture in the early stage of the product development cycle, thus reducing the potential risk of system re-design [1]. In [2], the authors used statistical models to calculate execution cycles for bus traffic analysis and system performance estimation. However, the main drawback of static analysis is the lack of dynamic analysis information, such as bus contention, arbitration, dynamic scheduling, etc [3]. So some designers explore architecture by dynamic simulation at register-transfer-level (RTL). While this was possible for designs that were relatively simple, exploring complex SoC designs at RTL is an intimidating prospect. The speed of RTL simulation is too slow to allow adequate coverage of the large design space. Besides, making small changes in the design will probably require considerable re-engineering effort due to the complex nature of these systems [4]. To overcome these limitations, system designers should raise the level of abstraction, which gives an early estimation of the system characteristics before committing to RTL development. In this paper, a method of SoC system bandwidth estimation based on electronicsystem-level (ESL) is proposed, which estimates the system bandwidth by transaction-level-modeling (TLM) and analysis depended on simulation. In Section 2, basic principles of ESL design methodology are introduced. In Section 3, the process that *

This work was sponsored by the National Scientific Foundation of China (Grant No. 61006029) and Jiangsu Scientific Foundation (Grant No. BK2010165)

M. Ma (Ed.): Communication Systems and Information Technology, LNEE 100,. pp. 15–21. springerlink.com © Springer-Verlag Berlin Heidelberg 2011

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using the method based on ESL to model the target system is described. In Section 4, the analysis depended on simulation and the bandwidth estimation of the target system are given. Section 5 is the conclusion.

2 Principles of ESL Design Methodology In current SoC design, the model established at the level of algorithm-and-function (ALF) is lack of timing information, and has little relationship with the system structure and implementation, which cannot be used to estimate the system performance. While the RTL model needs to focus on details of signal processing and design implementation, the speed of modeling and simulation is slow. ESL design methodology introduces a new level, transaction level, between ALF and RTL to abstract systems. Transaction-level-modeling (TLM) provides software and hardware engineers a virtual platform for the exploration of architecture and embedded software development.

Fig. 1. Comparison of the three modeling methods

ESL design methodology enables SoC designers to describe the system abstractly, with no need to prematurely be involved in the specific of implementation. Through ESL design methodology, designers can model the system in the early stage, explore the system architecture and guarantee the advancement. So that the risk of re-design due to performance cannot meet the requirement is reduced. In this paper, the architects view TLM is proposed, which has enough timing information and is mainly used for architecture exploration. Modules of the system will be abstracted as bus, memory or device to simulate system load. This method considerably reduces the workload required in the modeling, and greatly speeds up the system simulation.

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Fig. 2. Architects view TLM

3 Modeling of the Target System In this paper, ESL design methodology is used to analyze the performance, estimate the bandwidth by TLM on the ESL design platform, and optimize the architecture during the research to meet the requirement. 3.1 General Situation of the Target System The block diagram of the target system is shown at Fig. 3. 1. The system uses DDR2-800 as memory, data bus width is 32-bits, main timing parameters are CL=4, tRCD=4; 2. The interface frequency of AXI based LCDC, VPU and DDR2 is 200 MHz; 3. LCDC supports resolution up to 1920x1080 at refresh rate of 60Hz, and has three overlays, considering the worst case, bandwidth demand is about 1200 MB/s; 4. VPU accesses data every 4085ns, bandwidth demand is up to 900 MB/s, of which 700 MB/s is read access and 200 MB/s is write access. A rough estimate, LCDC and VPU consume 65% of the peak bandwidth. However, because of the complexity of access to DDR2, evaluation for the bandwidth is difficult. DDR2 storage can be divided into bank, row and column. According to the current and previous access addresses of the bank and row, access to DDR2 can be classified as continuous access and with-precharge access. Time spans of the two types of access are different. LCDC and VPU simultaneously request transaction whose required address is a random variable. On the other hand, bus transfer and arbitration will consume some bandwidth. So in fact, the bandwidth consumed by the two modules will significantly exceed 65%. To evaluate the bandwidth effectively, a correction factor must be involved.

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Fig. 3. The block diagram of the target system

However, due to the randomness of data access, evaluation of the factor is a great challenge. Using ESL design methodology, modeling the target system abstractly, and depending on the ESL design platform, the factor and the system bandwidth can be obtained accurately. 3.2 Modeling of the Target System To estimate the system bandwidth, the amount of data transfer is concerned, while data content and processing are not cared. Architects view TLM can greatly speed up the modeling, and evaluate the system bandwidth effectively. 1. Data access to DDR2 takes 38 bus cycles for data transfer in the bus. The depth of task buffer in the DDR2 controller is 16. LCDC owns higher priority than VPU. Considering the two types of access, continuous access needs 2 bus cycles to complete burst-4 operation, while with-precharge access takes 4 bus cycles. 2. LCDC will request access to DDR2 when any of the three overlay FIFOs is not full. If data of continuous access belong to the same overlay, access is continuous access. Otherwise access is with-precharge access. 3. VPU will always request access to DDR2, which is continuous access. Because LCDC and VPU request access simultaneously, access may be interrupted by each other, continuous access may be interrupted to become with-precharge access often. Thus, the access to DDR2 is similar to a random process. Taking the advantage of the ESL design platform, the actual situation of access to DDR2 can be simulated and analyzed. Thus the system bandwidth can be evaluated effectively. The system model built in the ESL design platform is shown at Fig.4.

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Fig. 4. The system model built in the ESL design platform

4 Simulation and Analysis Result The simulation result of the target system model in the ESL design platform is shown in Table 1. Because of the existence of the with-precharge access, the utilization of the system bandwidth rises significantly. When LCDC is not optimized, the utilization of bandwidth is about 83%, the system bandwidth margin is about 17%. Table 1. The contrast of the Utilization of system bandwidth between ideal estimation and actual simulation (LCDC is not optimized)

The utilization of system bandwidth

Ideal estimation

Actual simulation

62%

83%

LCDC can be optimized to effectively improve the utilization of system bandwidth by arranging the continuous access and reducing the number of with-precharge accesses. On the other hand, the more continuous accesses, the requirement of FIFO depth is higher. The depth of FIFO will affect the implementation area, so there should be a trade-off between the bandwidth and the area. The simulation results of LCDC with different transmission modes are shown at Fig.5. Through optimizing the LCDC design, the utilization of system bandwidth drops from 83% to 64%, in the worst case the margin of system bandwidth is still about 36%, which can meet the requirement.

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Fig. 5. The simulation results of LCDC with different transmission modes

Fig.5 also shows the utilization of system bandwidth and the requirement of FIFO depth drops and rises in an exponential manner. Comparing Case 4 with Case 3, the utilization of system bandwidth drops by only 2%, but the requirement of FIFO depth rises by 24. Thus it is reasonable to access data belong to the same overlay 3 times continuously. In the late stage of the development, RTL simulation results show that, when LCDC accesses data belong to the same overlay 3 times continuously, the requirement of FIFO depth is 27, and the utilization of system bandwidth is 76%. These are in agreement with ESL simulation results, indicating the efficiency of the ESL based SoC system bandwidth estimation method. The time spent on ESL simulation and RTL simulation of the target system is shown in Table 2. Compared with the traditional RTL simulation, the time is reduced from 33 hours to 9 minutes, more than two orders of magnitude shorter. Table 2. The time spent on ESL simulation and RTL simulation of the target system

The time spent on data output of 24 frames of 800x640 image

ESL simulation About 9 minutes

RTL simulation About 33 hours

5 Conclusions In this paper, a method of SoC system bandwidth estimation based on ESL is proposed, which estimates the system bandwidth by TLM and analysis depended on simulation. Compared with the traditional RTL simulation, the estimation is effective

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and the simulation speed is more than two orders of magnitude faster. Practice shows that the effective use of ESL design methodology can improve system performance and success rate of the implementation. With the improvement of complexity in SoC designs, the introduction of ESL design methodology has become an irresistible trend, and strongly promotes the development of SoC designs.

References 1.

2.

3.

4.

Ruei-Xi, C., Wei, Z., Qinyi, L., Fan, J.: Efficient H.264 Architecture Using Modular Bandwidth Estimation. In: International Conference on Embedded Software and Systems, pp. 277–282 (2008) Cho, Y.S., Choi, E.J., Cho, K.R.: Modeling and analysis of the system bus latency on the SoC platform. In: International Workshop on System-Level Interconnect Prediction, pp. 67–74. ACM, New York (2006) Zhe-Mao, H., Jen-Chieh, Y., Chuang, I.Y.: An accurate system architecture refinement methodology with mixed abstraction-level virtual platform. In: Design, Automation & Test in Europe Conference & Exhibition, pp. 568–573 (2010) Shin, C., Grun, P., Romdhane, N., Lennard, C., Madl, G., Pasricha, S., Dutt, N., Noll, M.: Enabling heterogeneous cycle-based and event-driven simulation in a design flow integrated using the SPIRIT consortium specifications. Des. Autom. Embed. Syst. 11, 119–140 (2007)

Cellular Automaton for Super-Paramagnetic Clustering of Data Zhang Botao, Zhang Shuqiang, and Yu Zhongqiu Institute of Science, Information Engineering University, 450001 Zhengzhou, China [email protected], [email protected]

Abstract. Using the basic idea of Super-paramagnetic Clustering (SPC), we propose a cellular automaton approach for data clustering: A data set is regarded as a Potts magnetic system and a short-range interaction is introduced between the neighboring spins. Let the system evolve automatically under the function of the spin-spin interaction and the thermal motion. Finally, at a proper temperature the system will reach the super-paramagnetic phase, in which the spins (data points) will form into a number of ‘magnetic domains’ (data clusters). We apply this method to some data sets with different structures and get satisfactory results. Keywords: Data clustering, Potts magnetic system, Cellular Automaton.

1 Introduction Data clustering is a basic technique in data analyzing and in a variety of scientific and engineering fields. It is widely used in the fields such as pattern recognition, artificial intelligence, computer image processing, biology, astrophysics, etc. [1]. The general definition of data clustering is as follows: partition N points given in the feature space of the data into M different groups so that two points that belong to the same group are, in some sense, more similar than two points that belong to different ones [1]. The procedure of the traditional and typical clustering methods is as follows: firstly some knowledge about the clusters’ structure is assumed (e.g. each cluster is represented by a center and some point around it), and then the similarity between data points is calculated. Finally, partition data points into different clusters according to their similarity. It should be noted that, in the above procedure a successful clustering is based on a priori knowledge and a correct assumption about the structure of data set. That is, in the traditional procedure, some external factors is imposed to the set structure no matter it is right or not. In 1996, Eytan Domany presented a new approach for clustering: Super-paramagnetic Clustering (SPC)[2-4]. The basic idea of SPC is to build clusters naturally by utilizing the physical properties of an inhomogeneous ferromagnetic model. Here a Potts spin variable is assigned to each data point and a short range-interaction is introduced. Thus, the Potts spins will evolve automatically under the function of the spin-spin interaction and the thermal motion. At a proper temperature, the system will reach the super-paramagnetic M. Ma (Ed.): Communication Systems and Information Technology, LNEE 100, pp. 23–29. springerlink.com © Springer-Verlag Berlin Heidelberg 2011

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phase. Spins with strong interaction to each other will form a magnetic domain in which all spins have a same state. This magnetic domain is thus corresponding to a data cluster. Domany explored a way to identify the magnetic domain by using Monte Carlo procedure [5]. Domany’s idea inspires us to consider a “Cellular Automaton (CA) for data clustering”. Contrast to the Monte Carlo procedure, the CA model is a dynamic model and is based on the spatial sequences [6], which is very similar to the procedure of magnetizing of a Potts system. Furthermore, CA model may be run on the special CA machine. Thus, we expect to build a CA model to realize SPC in a more useful way. In the following sections we first introduce the idea of the Super-paramagnetic Clustering (Sec2), and then describe the CA model for data clustering and corresponding algorithm (Sec3). In Sec4 we apply the method to two data sets with different typical structures. At last in Sec5 we give some conclusions and discussions.

2 The Idea of SPC A data point is a Potts spin when the data set is regarded as inhomogeneous Potts system. The spin-spin correlations (presented by the coupling function J) let the uniformity of the system but thermal motion destroys it. The magnetic domain will be formed and separated from others in the super-paramagnetic phase. This is the data clusters. Here, the coupling function J represents the similarity between data points. The closer two points are to each other, the more they ‘like’ to belong to the same class. Obviously, J is some positive decreasing function of the distance, which is chosen as follows [2]: 2

d 1 J i = exp(− i 2 ) K 2a

(1)

Where a stands for the average nearest-neighbor distance. K is the average number of neighbors per set. The thermal motion will destroy the “bonds” among spins. At the low temperature enough, all spins of the system are in the same state, Obviously, the temperature plays the role of clustering resolution here.

3 The Simulation of Cellular Automaton Clustering In this section we propose a Cellular Automaton [8] model for the clustering of data. 3.1 Model Firstly, we consider the effect of the interaction Ji and the temperature T by setting a link between the center site and its neighbor i [5]. The probability that a spin can’t link up with its neighborhood i is as follows:

Cellular Automaton for Super-Paramagnetic Clustering of Data

Pni = exp(−

25

Ji ) T

(2)

and the probability of linking-up is:

Pbi = 1 − Pni = 1 − exp(−

Ji ) T

(3)

The next state of a site is determined by the configuration of the links between the site and its neighbors. The model is described as follows: The possible states of each lattice site (spin, data point) is s (s=1, 2,... , q). In order to apply the method to different dimension data sets especially in high dimension data sets, we use the mutual K-nearest-Neighbor[9] which is defined as follows: two points, A and B, are defined as neighbors if they have a mutual neighborhood value K; that is ,if A is one of the K nearest neighbors of B and vice-versa. This definition ensures that the local interaction is symmetric; the number of bonds of any site is less than K. In general the value of K determines the range of interactions between a site and its neighbors. The rules are defined as: (i) If a site doesn’t link up with all of its neighbors, it updates its state randomly with probability Pn. otherwise it will be ‘magnetized’ by its linked neighbors with probability 1 –Pn (converts its state to the state of one of its linked neighbors), Here Pn is the probability of the configuration of a site with no links (see Fig 1 (a)): K

K

Pn = ∏ Pni = exp(−

∑J

i =1

ķ

ķ

Ĵ

Ĵ

Ĺ

Ĺ (a)

Ĺ

T

i

ķ Ĺ

(4)

)

ķ

Ĵ Ĺ

(b)

i =1

ķ

Ĵ Ĺ

(c)

（）

Ĺ

Ĵ Ĺ

(d)

Fig. 1. An example of realized configurations. a a site with no link, of s=1, c d e a site with links of s=3

（ ）、（ ）、（ ）

Ĺ

Ĺ (e)

（b） a site with a link

(ii) If a site has links with its neighbors with state s, it will be ‘magnetized’ to the state s with probability Ps. Suppose it has m neighbors with state s, Ps is the combined probability of the configurations the site and its neighbors with state s:

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K

m

Ps = [1 − exp( −

∑ Ji i =1

T

)] ⋅ exp( −

∑J j =m

T

j

)

(5)

Here, the configurations that a site links up with different states are forbidden, because it is impossible that a site be ‘magnetized’ by different states simultaneously. Fig 1 shows all the realized configurations of a site with three neighbors. 3.2 Algorithms At a proper range of T, the steps of the procedures of data clustering are: (i) Find out the neighbors of each site (Sec 3.1.2), and calculate K , di and Ji; (ii) Generate an initial configuration randomly; (iii) Calculate the converted probability of each site to different possible states; (iv) Update the states of all sites according to the above probabilities; (v) Repeat steps (iii) and (iv), until the system goes to stable; (vi) Class the sites (data points) with the same state into a cluster.

4 Tests 4.1 Random Numbers of the Two-Dimensional Normal Distribution This is a group of artificial data. Two groups of random numbers, which are evenly distributed in angle and normally distributed in radial, are generated by random number generator. This is a dataset of two natural kinds and two class central coincide annular, including 100 data points of average radius of 0.5 and 200 data points of average radius of 2. Clustering parameters are chosen to be: q = 15, K = 8. Figure 2 to figure 5 give four clustering results from low to high temperature (resolution). When the temperature is very low, the system is in ferromagnetic phase, all the datum being grouped into one cluster (figure 2). When the temperature increases to about 0.007, the system will experience a phase change, and the data points will be split into two clusters (figure 3). Then, when the temperature increases to about 0.1, the outer data class is further divided into two mass, and all the data is divided into three clusters (figure 4) , because there is an area of low density both above and below the outer datum. When the temperature continues to increase, the data mass continuously split, until the system turns into the paramagnetic phase (figure 5). As far as the natural class of the datum is concerned, proper clustering happens at an interval of T = 0.005 to 0.009.

Cellular Automaton for Super-Paramagnetic Clustering of Data

Fig. 2. T=0.001 into one cluster

，the data points are grouped

Fig. 4. T=0.01, all the data is divided into three clusters

Fig. 3. T=0.007 two clusters

27

，the data points are split into

，

Fig. 5. T=0.5 paramagnetic phase

4.2 Iris Data Iris data is a complete data set, including 150 samples of each Iris species (50 samples each), got by Fisher in 1936 after he collected the four features (the length and width of calyx leaves and the length and width of petals)of three different Iris genus(Iris Setosa, Iris Versicolor & Iris Virginica) . In the feature space, Iris Setosa and the samples of the other two species separate linearly, and the samples of Iris Versicolor and Iris Virginica have a little overlap. Clustering parameters are chosen to be: q = 15, K = 35. After a clustering test on this data set, we found that a roughly correct classification can be obtained at the interval of T = 0.01 to 0.1, and the clustering effect is the most stable when T≈0.018.At this time, the data were divided into three clusters, the samples of Iris Setosa being correctly divided but the samples of Iris Versicolor and Iris Virginica is more or less wrongly divided. Repeated testing results show that the number of wrong division is 5 to 25. Figure 6 shows the projection of the four-dimensional Iris number upon the first dimension and the fourth dimension. This is the best example of clustering, only 5 data

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Fig. 6. The projection of the Iris number upon the first dimension and the fourth dimension. T =0.018, five wrongly divided points are marked by rectangular square full sample.

being wrongly divided (see the five rectangular squares in Figure 6). In most tests, the number of wrong division is 13 or so. It shows in the chart that there are probably less than 50 samples in each cluster, which is the result of projection overlap of the data points.

5 Conclusions and Remarks We’ve constructed the “Cellular Automaton for data clustering” with the help of the similarities between super-paramagnetic phase formation and data clustering in the inhomogeneous Potts magnetic system. This method is based on the density of data points, which is suitable for different structure data set, and there is no need to make assumption about the data structure. In the clustering process, the rules of Cellular Automaton has played a decisive role, it provides a dynamic mechanism, letting the data points joint with each other according to their similarity. And the introduction of thermal motion functions as a kind of adjustment, letting the data point make multiple and repeated choices. The system will eventually evolve into a relatively stable configurations, and it has little to do with the initial configuration. This work is just a preliminary realization of clustering, and some questions need further research or optimization, including clustering stability, similarity and the best functional relation of the distance between data points, the best Cellular Automaton rules and the objective method to determine a candidate neighbor number K, etc.

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References 1. 2. 3. 4. 5. 6. 7. 8. 9.

Theodoridis, S., Koutroumbas, K.: Pattern Recognition. Publishing House of Electronics Industry, BeiJing (2010) Blatt, M., Wiseman, S., Domany, E.: Super-paramagnetic Clustering of Data. Physical Review Letters 76, 3251–3254 (1996) Blatt, M., Wiseman, S., Domany, E.: Data Clustering Using a Model Granular Magnet. Neural Computation 9, 1805–1842 (1997) Domany, E.: Superparamagnetic Clustering of Data-The Definitive Solution of an Ill-Posed Problem. Physica A 263, 158–169 (1999) Wang, S., Swendsen, R.H.: Cluster Monte Carlo alg. Physica A 167, 565 (1990) Dan Mueller, D.C., Chen, K., et al.: Solving the advection-diffusion equations in biological contexts using the cellular Potts model. Physical Review E 72(4), 1–10 (2005) Wu, F.Y.: The Potts model. Reviews of Modern Physics 54(1), 235–265 (1982) Zhang, B.T., Liu, C.H.: Cluster-approximation mean field theory of a class of cellular automation models. Physical Review E 59(5), 4939–4944 (1999) Blatt, M., Wiseman, S., Domany, E.: Clustering data through an analogy to the Potts model. In: Touretzky, D.S., Mozer, M.C., Hasselmo, M.E. (eds.) Advances in Neural Information Processing Systems, vol. 8, MIT Press, Cambridge (1996)

Embedded Memory Wrapper Based on IEEE 1500 Standard Maryam Songhorzadeh and Rahebeh Niaraki Asli Guilan University Guilan, Rasht, Iran [email protected]

Abstract. IEEE Std 1500 defines a modular and scalable test interface for embedded cores of a system-on-chip (SoC) which simplify test challenges. In this paper, we present a specialized wrapper compatible with IEEE Std 1500 to implement at-speed testing for embedded memory cores. The proposed embedded memory wrapper (EMW) supports test diagnosis with reasonable area overhead which makes it suitable for memory BIST applications. All required test control signals of EMW is generated on-chip by a single centralized memory Built-In-Self Test (BIST) controller. The BIST controller can be used in a hierarchical test design and implement parallel test to handle multiple test wrappers concurrently. Simulation and synthesis results on a group of embedded memory cores confirm that the proposed wrapper has been effectively reduces the test time and area overhead. Keywords: Embedded memory testing; System-on-a-Chip (SoC); Built-in-SelfTest (BIST); IEEE Std 1500; at -speed testing.

1 Introduction Today, the fast innovation in VLSI technology enables the design of complex system on a single chip. Although system chips offer advantages such as higher performance, lower power consumption and smaller volume and weight, the recent methods of design like synchronous production of different cores and using reusable and heterogeneous IP cores, poses new test constraints to the test community [1]. On the other hand, basic features of testability like controllability and observability are hard to achieve because direct access to core ports is virtually impossible [1]-[3]. To address these problems, IEEE Std 1500 was proposed which defines a scalable structure for independent, modular test development and test application for embedded design blocks. This standard also enables testing the external logic surrounding cores [4]-[6]. One of the core types which occupy a significant amount of SOCs is memory cores. The high density of embedded memory cores make them more prone to manufacturing defects than other types of on-chip circuitries. Since direct access to memory ports is virtually impossible and at-speed testing is difficult to achieve, BIST is a more practical method to test and diagnose embedded memories [7], [8]. But a M. Ma (Ed.): Communication Systems and Information Technology, LNEE 100, pp. 31–39. springerlink.com © Springer-Verlag Berlin Heidelberg 2011

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serial BIST like BIST based on IEEE std 1500, has a long and unacceptable test and diagnosis time, because this standard can’t implement a parallel test and manage multiple cores concurrently. Considering all these issues, several BIST schemes using IEEE Std 1500 serial links has been proposed [8]-[12]. In [8], a modular test wrapper for small wide memories has been introduced. The interfaces between the memories and BIST circuit are based on IEEE std 1500. This scheme allows for at-speed test at low area overhead. In [9]-[11], a serial test interface based on IEEE 1500 for small memories has been proposed. But the area overhead of the IEEE std 1500 wrappers is high. On the other hand, testing multiple memories using a serial BIST based on IEEE std 1500 requires a long and intolerable test time. In [12], another wrapper based on IEEE std 1500 is introduced which is in complete accordance with the standard but has no modification and optimization for memory testing, so it can’t support at-speed and parallel test. In this paper, the structure of a wrapper based on IEEE Std 1500 for Built-In SelfTest of embedded memory cores is proposed. The proposed structure is capable of implementing at-speed test and also supports diagnosis which is an important requirement in repairing procedure. By using a centralized BIST controller to generate control signals of the wrapper, the proposed scheme can be imported in a hierarchical test methodology and handle multiple test wrappers concurrently. On the other hand, the area overhead of the design is improved comparing the existing schemes. The organization of this paper is as follows: An overview of the general specification of the scheme is first given in section 2. In section 3 we propose different operational modes of the wrapper and Section 4 is allocated to the results of simulation and synthesis on a group of embedded memory cores. The paper is concluded in section 5.

2 Embedde Memory Wrapper (EMW) Figure 1 shows a memory core surrounded by the proposed IEEE-1500-compliant wrapper called EMW. The structure is composed of a Wrapper Instruction Register (WIR) circuitry, a Wrapper Boundary Register (WBR), a Wrapper Bypass register

Fig. 1. The overall structure of the IEEE-1500-compliant wrapper (EMW)

Embedded Memory Wrapper Based on IEEE 1500 Standard

33

(WBY), a Wrapper Data Register (WDR) and two multiplexers. All components of EMW are specialized for memory testing while adopt with IEEE Std 1500. In the reminder of this section, we introduce each part in detail. 2.1 WIR Circuit Figure 2 shows the structure of the proposed WIR circuit. It is composed of three main parts: WIR controller, WIR register and selector. According to IEEE Std 1500, WIR circuit must produce the signals required for controlling the other components of the wrapper and this can be done through initializing the wrapper serial port and WIR register.

Fig. 2. Structure of the proposed WIR circuit

WIR Controller. WIR controller generates control signals of the wrapper. From hierarchical point of view, this controller is the last level of test hierarchy. The BIST controller constitutes the upper level controller and generates all of the wrapper serial port signals and an additional signal for parallel shift. The BIST controller initializes input signals to the WIR controller and shifts the necessary instructions to WIR register through WSI signal. When there is no instruction to shift, WSI signal is used to transfer the related data of the current mode. Generating the input signals of WIR controller through the BIST controller can help producing a hierarchical test structure in which a memory BIST controller manages all WIR controllers of the wrappers. This relation can reduce test complexity while causes higher compatibility between the two controllers. On the other hand, the test methodology which also affects the wrapper will be more flexible because the BIST controller is completely definable by designer. WIR Register. In IEEE Std 1500, WIR register receives required instructions and test data. The 3 bit register proposed in figure 3 is in complete accordance with the standard and composes of two stages: shift and update. WIR_WSI is the serial input which shifts data and instructions to WIR register. After shifting operation, the contents of shift register are loaded into the update register. WIR_controller produces WIR_shift and WIR_update control signals.

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Fig. 3. Structure of WIR Register

WIR Selector. WIR selector is another part of WIR circuit. It is used to connect WSI signal to any of the wrapper registers. Based on the IEEE Std 1500, only one register can be set between the WSI and WSO signals. The selector circuit separates the respective register and connects WSI signal to it. 2.2 Wrapper Boundary Register (WBR) WBR is an important element of IEEE Std 1500 which has the responsibility of applying test and functional stimulus to the core and receiving the core responses. Figure 4 shows the proposed structure of WBR which is specialized for embedded

Fig. 4. The proposed structure for Wrapper Boundary Register (WBR)

Embedded Memory Wrapper Based on IEEE 1500 Standard

35

Fig. 5. The proposed structure for WBR input cell

Fig. 6. The proposed structure for WBR output cell

memory core BIST applications and composed of several input and output cells, multiplexers and some glue logics. The operation of input and output cells is controlled by control signals from memory BIST controller. Figures 5 and 6 show input and output cell architectures, respectively. Each cell has two data and test input and output ports and can be set in three different operational modes. CFI and CFO ports are used to receive and shift out the functional data, while the CTI and CTO ports are allocated to receive and shift out the test data. There are three control signals for controlling the operation of the cells: WBR_s_shift, WBR_p_shift and WBR_capture. WBR_s_shift and WBR_capture signals are derived from the shiftWR and captureWR signals of WSP respectively and WBR_p_shift is resulted from an optional signal called WPP_shift which is added to WSP port for enabling parallel shift of WBR cells. Table 1 shows the value of each control signal in different operational modes. Table 1. Control signals of WBR Mode Functional Internal Test External Test

WBR_S_shift

WBR_P_shift

WBR_capture

0 0 1

0 1 0

0 1 1

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One of the most important issues in memory testing is at-speed test to detect delay faults. BIST architectures based on IEEE Std 1500 need many clock cycles to shift in test commands, update operation to the memory and capture and shift out the memory responses. In the proposed architecture, due to parallel operation of WBR cells, the test data is sent to the memory in each clock cycle, and the memory outputs is compared in real time. So by such an approach, the new test data is applied to the memory in each clock cycle. This time scheduling not only reduces test time, but also applies valid data to memory in each cycle. To realize the approach, a design like figure 4 is used. As can be seen, a 2-to-1 multiplexer is set between two input cells. One input of this multiplexer is used only for parallel test and the other comes from CTO of the previous cell. WBR_s_shift and WBR_p_shift signals control multiplexers and set WBR in appropriate configuration. 2.3 Wrapper Bypass Register (WBY) WBY is a one bit register sets between WSI and WSO signals and bypasses the wrapper in functional mode. WBY block diagram with input and output signals is shown in figure 7. WIR controller produces the only control signal of WBY which is called WBY_shift.

Fig. 7. WBY structure

2.4 Wrapper Data Register (WDR)

WDR is an optional register of IEEE std 1500 which shifts test outputs. When the memory is under test, WDR is set between WSI and WSO signals and shifts the diagnosis information out. The volume and content of this data is dependent on the structure of the designed BIST. WIR controller generates WDR_shift control signal.

Fig. 8. WDR structure

3 Operational Modes of EMW Functional mode: In this mode, the wrapper is bypassed and the memory implements the functional operation. The instruction code of this mode is 111. According to figure 3, when the reset signal is enabled, this value is loaded in the update register of WIR and

Embedded Memory Wrapper Based on IEEE 1500 Standard

37

WBY is set between WSI and WSO signals. According to figure 4, the three control signals WBR_p_shift, WBR_s_shift and WBR_capture are all set to 0 and the functional data can be shifted through the paths WFI_n into input_n and output_n into WFO_n for input and output cells respectively. Internal test mode: This mode is assigned to testing the memory and has an instruction code of 001. When the wrapper sets in this mode, the test data is shifted to the input cells through WPI parallel port and the memory responses are also shifted out from the memory through WPO parallel port. WDR is set between WSI and WSO signals and shifts the test results out. The values of the control signals are shown in table 1. External test mode: In external test mode, the logic surrounded the memory core is tested by shifting 010 to WIR. The values of the control signals change as shown in table 1. By setting WBR_s_shift and WBR_capture to 1 and WBR_p_shift to 0, WBR configures as a scan chain and sets between WSI and WSO signals. So applying the test data through WFI or receiving the response through WFO from the logics surrounding the memory, can be done by setting the WBR_capture to 0.

4 Simulation and Synthesis Results To evaluate the design, EMW has been simulated and synthesized with Xilinx 11.1 for memories with different configurations. It is synthesized using Xilinx 11.1 with 0.18 CMOS standard cell library. At first, EMW is simulated for a 16K×16 SRAM to measure test time. Table 2 shows the results of the synthesis for some march algorithms with different length. The proposed structure guarantees an at-speed test with the 147.1MHz clock frequency and it has an access time of 6.8 ns which are results from the synthesis. To evaluate the area overhead of the proposed approach, EMW is synthesized with Xilinx 11.1 and the results are compared with [12]. The wrapper structure of [12] is completely designed based on IEEE std 1500 without any modification. In this structure, WSP of the wrapper comes from a TAP controller and not from any the memory BIST controller, so the test procedure has less flexibility compared to the proposed structure. Table 3 summarizes the results on area overhead for different blocks in EMW and [12]. These wrappers are both synthesized for a 16K×16 SRAM and using 0.18 CMOS standard cell library. The results show the area overhead of the EMW is 120.79% improved compared to [12]. Also to evaluate the area overhead of the proposed wrapper for different memories, it is simulated and synthesized using Xilinx 11.1 for memories with various size and configurations. The memories are high density embedded SRAMs and EMW structure are synthesized using 0.18um CMOS standard cell library. Table 4 summarizes the synthesis results of area overhead of the proposed wrapper. In this table a N×W memory configuration denotes a memory with N words and each word has W bits. As can be seen, by increasing the size of the memory, the area overhead is significantly decreasing. Because by changing the configuration of the memory, only the number of the input and output cells of the WBR needs to be changed and the rest of the structure is the same for memories with different configuration and due to the results of table 3, WBR has the most area overhead.

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M. Songhorzadeh and R.N. Asli Table 2. Test time for three different algorithm using EMW on a 16×16K SRAM March Algorithm March RABL [13] March BDN [14] March LR [15]

Test Time 7.616 ms 4.787 ms 3.046 ms

Table 3. Wrapper area overhead compared to [12] Wrapper Components WBY WDR WBR WIR circuit Total(Wrapper 16K×16) optimization

# of gates in Proposed Wrapper 16 50 864 426 1356

# of gates in Previous Wrapper NR* NR NR NR 2994 120.79%

Table 4. Wrapper area overhead for different memory sizes Memory size

EMW Number of gates

4 K×16 16 K×16 4 K×32 16 K×32 4 K×64 16 K×64

1320 1356 1896 1932 3048 3084

EMW area (mm2) 0.0136 0.0146 0.0196 0.0200 0.0316 0.0319

Area Overhead 3.59% 0.96% 2.59% 0.66% 2.08% 0.52%

5 Conclusion The structure of an at-speed Embedded Memory Wrapper (EMW) has been proposed. The proposed EMW structure is based on IEEE Std 1500 and suitable for Built-In Self-Test applications. One of the main issues in memory testing is at-speed test to detect delay faults and in the proposed wrapper this feature is realized by using parallel ports for input and output cells of the introduced embedded memory BIST wrapper boundary (MBWBR). Also diagnosis can be supported by shifting the diagnostic information out through WDR. The results shows EMW structure also has reasonable area overhead. Also any number of wrappers in EMW structure can receives their control signals from one memory BIST controller so the presented structure has the capability of diagnosis and parallel testing of multiple wrappers concurrently. In the future, we hope to develop a MBWBR which can share between multiple identical memories to reduce the area overhead of EMW.

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References 1. Hong Fang, B.: Embedded Memory BIST for Systems-on-a-Chip. MS Thesis, McMaster University, Hamilton, Ontario,Canada (2003) 2. Larsson, A.: Test Optimization for Core-based System-on-Chip. PHD Thesis, Linköpings university (2008) 3. Naddeau-Dosite, B., Adham, M.I.S., Abbott, R.: Improved Core Isolation and Access for Hierarchical Embedded Test, vol. 26(1), pp. 18–25. IEEE Computer Society Press, Los Alamitos (2009) 4. Wang, L., et al.: Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard. In: International Test Conference 2008 (ITC 2008), pp. 1–9 (2008) 5. Li, J., et al.: A Hierarchical Test Methodology for Systems on Chip. IEEE Micro 22(5), 69–81 (2002) 6. IEEE Computer Society, IEEE Standard Testability Method for Embedded Core-based Integrated Circuits- IEEE Std 1500TM-2005. IEEE, New York (2005) 7. Dean Adams, R.: High Performance Memory Testing:Design Principles, Fault Modeling and Self –Test. Kluwer Academic Publishers, New York (2005) 8. Aitken, R.C.: A Modular Wrapper Enabling High Speed BIST and Repair for Small Wide Memories. In: International Test Conference (ITC 2004), pp. 997–1005 (2004) 9. Vadeau-Dostie, B., Silburt, A., Agarwal, V.K.: A serial interfacing technique for external and built-in self-testing of embedded memories. IEEE Design & Test of Computers 7(2), 5–64 (1990) 10. Jone, W.B., Huang, D.C., Wu, S.C., Lee, K.J.: An efficient bist method for small buffers. In: Proc. IEEE VLSI Test Symp (VTS), pp. 246–251 (1999) 11. Huang, D.C., Jone, W.B.: A Parallel Built-in Self-Diagnostic Method for Embedded Memory Arrays. IEEE Trans. Computer-Aided Designed of Integrated Circuits and Systems 21(4), 44–465 (2002) 12. Squillero, G., Rebaudengo, M.: Test Techniques for Systems-on-a-Chip, Politecnico di Torino (2005) 13. Benso, A., Bosio, A., Di Carlo, S., Di Natale, G., Prinetto, P.: Automatic March Tests Generations for Static Linked Faults in SRAMs. In: Proceedings Design, Automation and Test in Europe DATE 2006, pp. 1–6 (2006) 14. Bosio, A., Natale, G.D.: March Test BDN: A new March Test for Dynamic Faults. In: IEEE International Conference on Automation, Quality and Testing, Robotics, AQTR 2008, pp. 85–89 (2008) 15. Van de Goor, A.J.: March LR: A test for realistic linked faults. In: Proc. IEEE VLSI Test Symp., pp. 272–280 (1996)

A SVPWM Control Strategy for Neutral Point Potential Compensation in Three-Level Inverter Jinsong Kang and Yichuan Niu Tongji University, College of Electronic and Information Engineering, 200092 Shanghai, China

Abstract. This paper introduces the topology of three-level inverter and analyses its operational process. According to the analysis, traditional SVPWM control strategy will cause neutral point potential shifting, thereby an improved control strategy is designed to solve the potential shifting by resynthesizing vectors in particular sectors. This control strategy reduces the neutral current to a value near zero to compensate the neutral point potential shifting. Simulation and experiment have verify the effect of this SVPWM control strategy. Keywords: three-level neutral point potential SVPWM.

1 Introduction Three-level inverter is widely applied in frequency control for high power scale, utility systems and rail transit etc. In comparison with traditional two-level inverter, three-level inverter possesses the advantages such as lower output voltage harmonics and lower switching loss, besides the electrical stress of power electronic devices is also minimized. Two dominant kinds of topology for three-level inverter are diode clamped and capacitor clamped between which the diode clamped is the most common topology in pragmatic use. Control strategies for three-level inverter could also be divided into three parts: single-pulse control method, PWM control based on carrier wave and space vector pulse width modulation (SVPWM). Because of easier implement in program and a higher DC voltage utilization, SVPWM is applied more extensively. Besides, neutral point potential balancing in three-level inverter needs to be taken into account and realized by modulating operating period of voltage vectors, thereby the mid-point voltage of capacitor can be stabilized.[1] Based on the operational principle of diode clamped three-level inverter (hereinafter referred to as the three-level inverter), this paper focuses on SVPWM control strategy and neutral point potential compensation for three-level inverter. It, starting from the voltage space vector distribution, analyzes the influence for neutral point voltage induced by voltage vector, thus a SVPWM control strategy based on vector synthesis is promoted and its effectiveness is verified by simulations.

2 Analysis of Three-Level Inverter Topology A three-phase three-level inverter topology is shown in Fig. 1. Each phase has four main switching devices, four freewheeling diodes and two clamping diodes. DC rail M. Ma (Ed.): Communication Systems and Information Technology, LNEE 100, pp. 41–48. springerlink.com © Springer-Verlag Berlin Heidelberg 2011

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voltage is divided into two levels by two series capacitors C1 and C2. When power electronic devices VTa1 and VTa2 are conducting, the output voltage of terminal A is UDC/2, while VTa2 and VTa3 are conducting, the output voltage is 0. The conduction of VTa3 and VTa4 means the output voltage has its magnitude of -UDC/2.[2]

Fig. 1. Main circuit of diode clamped three-level inverter

In Fig. 1, the capacitor mid-point O is considered to be the reference neutral point, while point O’ is the mid-point of three-phase load. The relations between phase voltage of three-phase load and output voltage of inverter are

：

⎧U a = U A − U O ' ⎪ ⎨U b = U B − U O ' ⎪U = U − U ⎩ c C O'

(1) D

On the basis of space vector theory, introduce complex operator g( g = e j120 )into these equations, and combine the three-phase voltage equations. Then the vector representation of load phase voltage could be derived as Uref : U ref =

2 (U a + gU b + g 2U c ) 3

2 = [(U A − U O '' ) + g (U B − U O '' ) + g 2 (U C − U O '' )] 3 2 = (U A + gU B + g 2U C ) = u sα + ju sβ 3

In α and β stationary coordinates system,

(2)

usα and usβ are expressed as:

2 1 1 (U A − U B − U C ) 3 2 2 1 = (U B − U C ) 3

u sα = u sβ

(3)

Therefore, the 27 switching states known as output voltage vectors in stationary coordinates for three-phase three-level inverter are shown in Fig. 2(a).

A SVPWM Control Strategy for Neutral Point Potential Compensation

43

β

β

α

α

a. Space vector diagram

b. Vector synthesis in sector I

Fig. 2. Voltage space vector of three-level inverter

There are 19 voltage space vectors valid in the total 27, the other 8 vectors are redundant vectors. According to their magnitude, all space vectors can be divided into four categories: large vectors, medium vectors, small vectors and zero vectors. The 6 large vectors with a magnitude of 2U DC / 3 are: PNN, PPN, NPN, NPP, NNP, PNP. The 6 medium vectors are: PON, PNO, ONP, NOP, NPO, OPN which possess a magnitude of 3U DC / 3 . There are 6 groups of small vectors, each group has 2 vectors with a magnitude of U DC / 3 : (PPO, OON), (POO, ONN), (POP, ONO), (OPP, NNO), (OPP, NOO), (OPO, NON). The three zero vectors are: OOO, PPP and NNN.[5]

3 Neutral Point Potential Balancing of Three-Level Inverter In the operational process of three-level inverter, the inaccuracy of output voltage is caused by the non-conformity in charging and discharging of capacitors, which due to the discrepancy between the current flows into and out of the capacitors. [3] The heterogeneous influences upon neutral point potential may vary with the different vectors. Large vectors connect the phase terminals either to the positive or the negative dc rail. They do not cause the potential shifting in neutral point. The potential in each phase of three-phase load is equal in the 3 switching states of zero vectors. Even when all the loads are connecting to neutral point simultaneously, it will not cause the potential ripple. But, in medium vectors and small vectors, there is at least one phase connected to neutral point while others connected to the dc rail. Thus, the current flows through neutral point causing the unbalancing of neutral point potential in a form of potential ripple that fluctuates around the zero potential over time in a cycle. Fig. 3. shows the analysis of medium vector PON and small vectors POO, ONN. Equivalent circuits are given in Fig. 3, in order to explicate the cause of neutral point potential. iO represents neutral point current, while it is assumed the direction that the current flows out of neutral point is positive. As it's shown in Fig. 3(a), when the medium vector PON is on, neutral point current equals to the phase B load current, that is iO＝ib. When ib>0, capacitor C1 is charging, hence its voltage UC1 increases; while capacitor C2 is discharging, its voltage UC2 decreases.

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a. PON

b. POO

c. ONN

Fig. 3. Equivalent circuit of voltage vectors β NPN

NON NPO

Ⅲ

OPN

Ⅱ

ξ

OPO

OON

PPO

NNN

NPP

OPP

NOO NOP

Ⅳ NNO

NNP

OOP

PPN

PON

Ⅰ

POO

ONN

PPP POP

Ⅵ

α

PNO

ONO

ONP

PNN

Ⅴ

OOO

PNP

Fig. 4. Voltage space vectors with UDC/4 under neutral point potential shifting

Thereby, neutral point potential UO＝(UC2-UC1)/2 will decrease. Similarly, when ib<0, capacitor C1 is discharging, thus UC1 decreases; meanwhile capacitor C2 is charging, its voltage UC2 increases causing neutral point potential UO increases. In Fig. 3(b), neutral point current equals to the sum of load current in phase B and phase C when small vector POO is turning on, that is iO＝ib+ic=-ia. Realizing that when small vector ONN is on, as it is shown in Fig. 3(c), neutral point current equals to the load current of phase A, that is iO＝ia, the conclusion can be made that this small vector has an opposite effect upon neutral point potential in comparison of the previous analysis. Thus, it is neutral point current which contribute the primary cause to the neutral point potential shifting. Moreover neutral point current depends on three-phase load. Further analysis of neutral current shows that: current caused by medium vector can lead to fluctuation around the neutral potential, and quadrature axis will derive more low-frequency ripple than direct axis. Besides, the reactive component of small vector does not affect the neutral point potential, for that its integration is null during a cycle. On the other hand, due to its nonzero integration of active component, the neutral point potential will shift. By assuming the neutral point potential has shifted, the amount of valid voltage space vectors will increase up to 24, which is shown in Fig. 4. Both large vectors and

A SVPWM Control Strategy for Neutral Point Potential Compensation

45

zero vectors remain unchanged. Although the amount of medium vectors is unchanged, the direction and magnitude will alter. They deflect a clockwise angle of ξ degree in sector II, sector IV and sector VI, while in sector I, sector III and sector V, they deflect a anticlockwise degree of ξ. The 6 increments in small vectors remain the same direction, but their magnitudes change significantly in the form of that P vectors will be halved and N vectors will increase by half.

4 An Improved SVPWM Control Strategy An improved SVPWM control strategy utilizes redundancy of vectors to synthesize the output voltage space vectors and the neutral point potential shifting can also be compensated by this strategy. The directions of output voltage vectors are unchangeable, but their magnitudes are adjustable.

a. Improved space vector coordinates

b. Vector synthesis in sector ĉ

Fig. 5. Improved space vector coordinates and vector synthesis in sector

Ⅰ

From the previous analysis, the conclusion is that the two redundant small vectors in the same group have opposite effects upon neutral point potential, thereby the neutral point potential shifting is able to compensate by regulating the operating period of each small vector. For instance, the small vector ONN leads the neutral current iO= ia, while the small vector in the same group POO causes iO=-ia, hence the synthetic small vector is: U10 = (OOP + ONN ) / 2 . If there is serious neutral point potential shifting, it can be balanced by the operating periods of OPP and ONN in this cycle. The effects made by medium vectors alone will surely cause the neutral point potential shifting, however, small vectors can be introduced in order to balance the potential by reducing the neutral point current to zero for that the load current of every phase is remaining constantly during a relatively short sampling time. Use medium vector PON as an example. It will affect the neutral point potential by bringing load current ib out of it. When the small vectors ONN and POO are added, they will cause the corresponding currents ia and ib, thus the final output voltage vector is a synthetic vector: U20 = (PON +ONN + PPO)/3 , which is able to compensate the neutral potential shifting.

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Ⅰ for improved SVPWM control strategy

Table 1. Operating period of vectors in sector Region 1

T00 [1 2msin(S / 3 T )]Ts T10 2m sin(S / 3 T )TS

Region 2 Region 3 Region 4 Region 5

T10 [2  3mcosT  3msinT]Ts

T10

[2  3m cosT  3m sinT ]Ts

T11 [2  2 3m cos T ]Ts T20

T11

T 20

[

3 m cos T  1 ] T s

[2  2 3m cosT ]Ts T21

T11 [2msinT ]Ts

T21 [3m sinT ]Ts [ 3 3 m cos T  3 m sin T  3]T s

T21 [3 3 mcosT  3 msinT]Ts T22 [ 3 mcosT  3 msinT 1]Ts 2 2 2 2

3 3 m cos T  3 m sin T ]T T [ 3 mcosT  3 msinT 1]T [ 3m cosT  1]Ts T21 [3  22 s s 2 2 2 2

Large vectors and zero vectors are not necessary to synthesize, because they have no influence on neutral point potential. Fig. 5(a) shows all the voltage space vectors of improved SVPWM control strategy in coordinates of α and β, while Fig. 5(b) is the synthesis of vectors in sector Ⅰ. Table 1 illustrates the operating period of vectors in sectorⅠ. The regions of other sectors are similar to sector Ⅰ. In region 1 of sector Ⅰ, three basic vectors are U00, U10, U11 and their operating periods are T00, T10, T11. The switching sequence can be derived (the initial small vector is negative): ONN→OON→OOO→POO→PPO→PPO→POO→OOO→OON→ONN, while their operating periods are: T10/4→T11/4→T00/2→→T10/4→T11/4→T11/4→T10/4→T00/2→T11/4→T10/4.

5 Analysis of Simulation and Experiment Simulation is constructed in MATLAB. Assume that the DC voltage is UDC=1000V, the value of capacitor in DC link is 2000uf, the parameter of three-phase load is a motor with a power scale of 20 kW. The result of simulation about motor start is presented in Fig. 6. Fig. 6(a), showing waveforms of load phase voltage and load lineto-line voltage as well as neutral point potential of capacitor, is derived by traditional SVPWM control strategy with a modulation ratio m=0.8. It can be spotted that the neutral point potential suffers a relatively serious fluctuation caused by medium vectors. The potential shifting causes the inaccuracy of output voltage vectors both in phase voltage and line-to-line voltage. Fig. 6(b) shows the waveforms of load phase voltage, load line-to-line voltage and neutral point potential in improved SVPWM

(a)Traditional SVPWM

(b)Improved SVPWM

Fig. 6. Traditional SVPWM and improved SVPWM control strategy with m=0.8

A SVPWM Control Strategy for Neutral Point Potential Compensation

47

control strategy with a modulation ratio m=0.8. Obviously, the neutral point potential shifting is compensated by the control strategy and does not ripple at a large fluctuation.

Fig. 7. Neutral point potential in different control strategy with m=0.8

Fig. 7. is the waveform under different control strategies in different period. Period from 0 to 0.1 seconds uses mode 1 in traditional control strategy, while period from 0.1 to 0.3 seconds uses mode 2 in traditional control strategy. From 0.3 seconds on, the improved control strategy for compensating the neutral point potential is introduced. The waveform demonstrates the eminent effect of this control strategy.

(a) Driving signals of VTa1 and VTa3

(b) Driving signals of VTa2 and VTa4

Fig. 8. Driving signals of phase A in improved SVPWM

Fig. 9. Line-to-line voltage and current of phase A

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Fig. 8. and Fig. 9. show waveforms under experiment of improved SVPWM control strategy. Driving signals of VTa1 and VTa3 are shown in Fig. 8(a), and driving signals of VTa2 and

VTa4 are shown in Fig. 8(b). In Fig.9, line-to-line voltage possesses an outline of staircase which is familiar with the single-pulse control strategy. The phase current waveform is nearly sinusoidal, and the identical phase of voltage and current indicates the power factor is 1.

6 Conclusion This paper has researched SVPWM control strategy about compensation of neutral point potential shifting base on diode clamped three-level inverter. It is definite that the traditional control strategy has little effect about the compensation for neutral point potential shifting. Thus, the improved SVPWM control strategy based on vector synthesis is broached and is designed to reduce the potential shifting of capacitor. From the result of simulation, neutral point potential shifting is compensated and the output voltage vectors are more accurate than before. Besides, this improved control strategy can also be applied in multi-level inverters.

References 1.

2. 3.

4. 5. 6. 7.

8.

9.

Holtz, J., Oikonomou, N.: Neutral Point Potential Balancing Algorithm at Low Modulation Index for Three-Level Inverter Medium-Voltage Drives. IEEE Transactions on Industry Applications 43(3), 761–768 (2007) Kang, J.S., Wu, Y., Zhang, Y., Tao, S.G.: Carrier-PWM Control Strategies of Three-level Converters. Journal of Tongji University(Natural Science) 38(1), 124–129 (2010) Celanovic, N., Boroyevich, D.: A Comprehensive Study of Neutral-point Voltage Balancing Problem in Three-level Neutral-point-clamped Voltage Source PWM Inverters. IEEE Transaction on Power Electronics 15(2), 242–249 (2000) Wu, B.: High-Power Converters and AC Drives. Wiley-IEEE Press (2006) Kang, J.S., Zhang, Y.: Multi-level Converter Applied to Wind Power Generation System. Proceedings of the CSEE 24 (2009) Bose, B.K.: Modern Power Electronics and AC Drives. Prentice-Hall, Englewood Cliffs (2001) Song, W.X., Cao, D.P., Qiu, J.Y., Chen, C., Chen, G.C.: Study on the control strategy of three-level PWM rectifier based on SVPWM. In: IEEE 6th International Power Electronics and Motion Control Conference, IPEMC, vol. 1622 (2009) Kocalmis, A., Sunter, S.: Simulation of a Space Vector PWM Controller for a ThreeLevel Voltage-fed Inverter Motor Drive. In: 32th IEEE Indstrial Electronic Coference, pp. 1915–1920 (2006) Xia, L., Xu, G.Q., Hu, B., Kang, J.S.: Simulation Research on Clamped Topology Multilevel Converters. Mechatronics 13(1), 56–60 (2008)

Process Mining: A Block-Structured Mining Approach Yan-liang Qu* and Tie-shi Zhao College of Mechanical Engineering , Yanshan University , Qinhuangdao 066004, China [email protected]

Abstract. Constructing process models from scratch is a complicated timeconsuming task that often requires high expertise. And there are discrepancies between the actual workflow processes and the processes as perceived by the management. Therefore, techniques for discovering process models have been developed. Process mining just attempts to improve this by automatically generating a process model from sets of systems’ executions. In this paper, a block structured process mining approach from audit logs to support process discovery is designed. Compare with other algorithms, the result of this approach is more visible and understanding of process model. This approach is used to a widely commercial tool for the visualization and analysis of process model. Keywords: Process mining; Process logs; Process models; Block-structured Mining.

1 Introduction Today, Setting up and maintaining a process management system requires process models which prescribe how business processes should be managed by the system [1,2,3]. Typically, the user is required to provide these models. Constructing process models from scratch is a difficult and error-prone task that often requires high expertise. An alternative way of constructing process models from scratch is to extract them from event-based data captured in form of logs from running business processes. The goal of discovering models is to extract process models for business processes from such logs [4,5,6,7]. In this paper, a block-structured process mining approach from audit logs to support process modeling is designed. Process mining includes three steps: preprocessing of logs, process mining and reasonable validation of model. Our research focuses on the process mining step and its interfaces to the preceding and subsequent steps. In the first step, the logs are filtered and noise removed to provide a pure and simple log (i.e. audit logs). The second step is the core step of mining. The remainder of this paper is organized as follows: first, we introduce the related works and preliminaries (Section 2), describe in more detail of the approach (Section 3) and then give an application of securities trade (Section 4). To conclude we provide pointers to related work and give some final remarks. *

Corresponding author.

M. Ma (Ed.): Communication Systems and Information Technology, LNEE 100, pp. 49–56. springerlink.com © Springer-Verlag Berlin Heidelberg 2011

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2 Related Work and Preliminaries In fact the idea of deducing the process model from logs is not new. In 1995, Pro. Jonathan. E.Cook firstly put forward the idea in software engineering area[8]. In 1998, Rakesh Agrawal firstly applied the idea in workflow modeling area[9]. However, until recent years this modeling technology is paid more attention and gradually becomes a new modeling research direction. Gudio Schimm has developed a mining tool (Process Miner) suitable for discovering hierarchically structured workflow processes[10,11]. Joachim Herbst and Dimitris Karagiann applied inductive approach and machine learning method in workflow mining[12,13]. W.M.P van der Aalst and his research team do much research work in workflow mining[14,15]. They have designed several different workflow mining algorithms, which include formal algorithms ( α , α+ , β ) and heuristic algorithm. And they firstly put forward Workflow nets (WF-nets), creatively mapping workflow management concepts onto Pertri nets. A workflow process is designed to handle similar cases. Cases are handled by executing tasks in a specific order. The workflow process model specifies which tasks need to be executed and in what order. Tasks are modeled by transitions and causal dependencies are modeled by places and arcs. Figure 1 is a working example of WF-nets.

Fig. 1. An example of WF-nets

A workflow log is a sequence of events. For reasons of simplicity we assume that there is just one workflow process. Note that this is not a limitation since the case identifiers can be used to split the workflow log into separate workflow logs for each process. Therefore, we can consider a workflow log as a set of event sequences where each event sequence is simply a sequence of task identifiers. Formally, W⊆T+ where W is a workflow log and T is the set of tasks. An example event sequence of Figure 1 is given below: A,O,E,I,J,E,I,J,E,I,P,H Definition 2.1. Let W be a workflow log over T, i.e., W⊆T+. Let a, b ∈T: – a >>W b task a followed by task b directly or indirectly – a >W b if and only if there is a trace σ = t1t2t3 . . . tn−1 and i ∈ {1, . . . , n−2} such that σ∈ W and ti = a and ti+1 = b – a →W b if and only if a >W b and b ≯W a – a W b if and only if a >W b and b >W a

‖

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3 The Block-Structured Mining Method Because the flow of tasks is to be portrayed, control-flow mining techniques need to support the correct mining of the common blocks (e.g., control-flow constructs) that appear in process models. These blocks are: sequences, parallels, alternatives, loops, and non-free-choice, invisible tasks and duplicate tasks. In structured WF-nets, there are only four blocks: sequences, parallels, alternatives and loops. The block-structured mining method is focus on the four blocks above. Of cause, the approach is also helpful to other algorithms that face other blocks. 3.1 Route of the Mining Approach For four blocks: sequences, parallels, alternatives and loops, four mining algorithms are designed. The idea is: aim directly at logs, four mining algorithms are applied circulative in order and found blocks to make logs shrink through replace. The approach show in the below: Do while { do while{ algorithmsⅠ /* Sequence blocks mining } until can’t find new mining blocks do while{ algorithmsⅡ /* Alternative blocks mining } until can’t find new mining blocks do while{ algorithmsⅢ /* Loop blocks mining } until can’t find new mining blocks do while{ algorithmsⅣ /* Parallel blocks mining do mining sequence blocks in parallel blocks mining alternative blocks in parallel blocks } until can’t find new mining blocks } until can’t find new mining blocks Each out loop, one or a few blocks can be found. Through substitution, logs can get shrink and simplifying logs is as the basic data sets for the next loop. 3.2 Four Algorithms Algorithm I: Sequence blocks mining There are many sequence blocks in logs. Sequence blocks can be divided two kinds: explicit and implicit. Explicit sequence constructs can be shown in the logs conspicuously. Some sequence constructs is difficult to be found intuitionally due to the disturbing of other tasks (i.e., tasks in parallel). Next is the explicit sequence blocks mining algorithm. Implicit sequence blocks will be given in parallel blocks mining algorithm.

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Input: logs W, m cases, W={σ1, σ2,…,σm,}, n tasks, T={ t1,t2,t3, . . . tn } Output: a set of new tasks T’, a set of new cases W’ For each pair ∈T×T and a!=b { If a→wb //exist sequence relation between a and b { Found sequence block B=ab Replace ab(series) with B in each case Modify task set T: add B, drop tasks a,b Record B=a+b in document table } } Algorithm II: Alternative blocks mining Alternative construct has two characteristics. First, each alternative block has one start task and one end task in process model. Second, there is only one task between start task and end task. Also, alternative blocks can be divided two kinds: explicit and implicit. Explicit alternatives constructs can be shown in the logs conspicuously. Some alternatives constructs is difficult to be found intuitionally due to the disturbing of other tasks (i.e., tasks in parallel). Next is the explicit alternatives blocks mining algorithm. Implicit sequence blocks will be given in parallel blocks mining algorithm. Input: logs W, m cases, W={σ1, σ2,…,σm}, n tasks, T={ t1,t2,t3, . . . tn } Output: a set of new tasks T’, a set of new cases W’ For each pair ∈T×T and a!=b { Sign=.T. A=Φ Forσ=σ1 to σm { If exist si=a in σ =s1s2s3… { If si+2=b A=A {si+1} Else {sign=.F. Break For } If exist si=b in σ =s1s2s3… { If si-2=a A=A∪{si-1} Else {sign=.F. Break For} }

∪

If sign and |A|>1 //a is start task and b is end task in alternative block. // the elements in set P are alternative items. { B=a+A+b Replace aAb(series) with B in each case Modify T, add B, drop tasks a,b

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Record B=a+A+b in document table } } Algorithm III: Loop blocks mining After running of algorithmⅠand algorithmⅡ, loop constructs have only two kinds in Figure 2 at this time. The length of loop is 0 or 1. So, algorithmsⅢ is composed of part1 and part2.

Fig. 2. Two Kinds of Loop Constructs

Part1: mining loop construct C1 Input: logs W, m cases, W={σ1, σ2,…,σm}, n tasks, T={ t1,t2,t3, . . . tn } Output: a set of new tasks T’, a set of new cases W’ For each t∈T { Sign=.F. For σ = σ1 to σm If exist si=t in σ=s1s2s3… { If si+1=t { Sign=.T. Break For } } If sign{ B=ttt… Replace ttt… with B in each case Modify T, add B, drop task t Record B=t in document table } } Part2: mining loop construct C2 Input: logs W, m cases, W={σ1, σ2,…,σm}, n tasks, T={ t1,t2,t3, . . . tn } Output: a set of new tasks T’, a set of new cases W’ For each t∈T { Sign=.F. L=Φ Forσ=σ1 to σm If exist si=t in σ =s1s2s3… { If si+1<>t and si+2=t {

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Sign=.T. L=L si+1 }

∪

} If sign{ B=t+L Replace t+L with B in each case Modify T, add B, drop tasks t,L Record B=t+L in document table } } Algorithm IV: Parallel blocks mining Firstly, it is necessary to part the parallel tasks. The key of partition is to create the equivalence classes of parallel tasks. It assumes that A={T1,T2,…} is a equivalence classes of parallel tasks. ∀ x1,x2∈Ti, x1 wx2. The algorithm of equivalence classes of parallel tasks:

‖

(1) Let T’ be the set of parallel tasks and R be the set of parallel tasks relations on logs W. T’=Φ; R=Φ.

‖

(2) ∀ a,b∈T, if a Wb then R=R∪(a,b),T’=T’∪{a}∪{b} (3) Extended relation R until make R be a equivalence relation. It is easy to make R satisfy reflexive, symmetric and transitive. (4) Partition equivalence classes T’/R.

∀ a∈T’, set Ti=[a]R={x|x∈T,a

‖

w

x}

So, A=T’/R={T1,T2,…}. Ti is a equivalence class that is the set of all elements that are related to a task a. In other words, the tasks in the set of parallel tasks may be not parallel tasks. Maybe, there exist sequence or alternative relations. For example, it is in Figure 3.

Fig. 3. An example of parallel constructs.

Logs are {BCFDG, BCDFG, BDCFG}. Tasks CFD are parallel tasks. But task C never appears in the behind of task F. So there has the sequence relation between C and F. Next is the rule to find out sequence relation among parallel tasks equivalence classes of A:

∀ Ti∈A, a, b∈Ti if a>>b then the relation of a and b is sequence. Also, there is the rule to find out alternative relation among parallel tasks equivalence classes of A: ∀ Ti∈A, a, b∈Ti if a>>b & b>>a then the relation of a and b is alternative.

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Also, parallel construct have one characteristic. Each parallel block has one start task and one end task in process model. Input: logs W, m cases, W={σ1, σ2,…,σm}, n tasks, T={ t1,t2,t3, . . . tn }, A={T1,T2,…} is the equivalence classes of parallel tasks on W. Output: a set of new tasks T’, a set of new cases W’ For ∀ m, n∈T { Sign=.T. TS=Φ Forσ=σ1 to σm { If tasks(σ,m, n)<>Φ and ∃ Ti∈A,tasks(σ,m, n) ∈Ti { do case TS=Φ: TS=tasks(σ,m, n); TS<>tasks(σ,m, n): Sign=.F.; break for; Endcase } Else { Sign=.F.; Break for;} } If sign { Found parallel block B=mSn Replace mSn with B in each case Modify task set T: add B, drop tasks m, S, n Record B=m+S+n in document table } } Function Tasks(σ,a, b): caseσ= t1t2t3…tn, σ∈W. Exists a=ti,b=tj,i>j then Tasks(σ,a, b)={ti+1,ti+2,…,tj-1}

4 Conclusion In this paper we have presented an approach on discovering process models from process logs. This approach has been validated using logs of transactional information systems. It shows that the approach has an obvious advantage in getting the reasonable, security and understandable model Process mining is not restricted to creating new formal process models. Any organization's process will evolve over time, and thus their process models will need to evolve as well. Methods for discovery process may give a process engineer clues as to when and in what direction the process model should evolve, based on data from the currently executing process. While we have focused here on the use of these methods for generating process models, we also believe that they are useful in visualizing the data collected on a process. An engineer may simply be interested in a way to better understand the current process, as captured by the event data. Discovering patterns of behavior may be of help.

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References 1. van der Aalst, W.M.P., van Hee, K.M.: Workow Management: Models, Methods, and Systems. MIT press, Cambridge (2002) 2. Fischer, L. (ed.): Workow Handbook 2001, Workow Management Coalition. Future Strategies, Lighthouse Point, Florida (2001) 3. Herbst, J.: A machine learning approach to workflow management. In: Lopez de Mantaras, R., Plaza, E. (eds.) ECML 2000. LNCS (LNAI), vol. 1810, pp. 183–194. Springer, Heidelberg (2000) 4. Agrawal, R., Gunopulos, D., Leymann, F.: Mining Process Models from Workflow Logs. In: Sixth International Conference on Extending Database Technology, pp. 469–483 (1998) 5. van der Aalst, W.M.P., van Dongen, B.F., Herbst, J., Maruster, L., Schimm, G., Weijters, A.J.M.M.: Workflow Mining: A Survey of Issues and Approaches. Data and Knowledge Engineering 47(2), 237–267 (2003) 6. van der Aalst, W.M.P., Weijters, A.J.M.M., Maruster, L.: Workow Mining: Which Processes can be Rediscovered, WP 74. BETA Working Paper Series. Eindhoven University of Technology, Eindhoven (2002) 7. Hammori, M., Herbst, J., Kleiner, N.: Interactive workflow mining. In: Desel, J., Pernici, B., Weske, M. (eds.) BPM 2004. LNCS, vol. 3080, pp. 211–226. Springer, Heidelberg (2004) 8. Cook, J.E.: Process Discoverying and Validation through Event-Data Analysis. Technical Report CU-CS-817-96, University of Colorado, Boulder, Colorado, Novermber (1996) 9. Agrawal, R., Gunopulos, D., Leymann, F.: Mining process models from workflow logs. In: Sixth International Conference on Extending Database Technology, pp. 469–483 (1998) 10. Schimm, G.: Generic linear business process modeling. In: Mayr, H.C., Liddle, S.W., Thalheim, B. (eds.) ER Workshops 2000. LNCS, vol. 1921, pp. 31–39. Springer, Heidelberg (2000) 11. Schimm, G.: Process miner - A tool for mining process schemes from event-based data. In: Flesca, S., Greco, S., Leone, N., Ianni, G. (eds.) JELIA 2002. LNCS (LNAI), vol. 2424, p. 525. Springer, Heidelberg (2002) 12. Herbst, J., Karagiannis, D.: Integrating machine learning and workflow management to support acquisition and adaptation of workflow models. International Journal of Intelligent Systems in Accounting, Finance and Management 9, 67–92 (2000) 13. Herbst, J.: Dealing with concurrency in workflow induction. In: Baake, U., Zobel, R., AlAkaidi, M. (eds.) European Concurrent Engineering Conference. Society of Computer Simulation (SCS), Europe (2000) 14. van der Aalst, W.M.P., Weijters, A.J.M.M., Maruster, L.: Workflow Mining: Discovering Process Models from Event Logs. IEEE Transactions on Knowledge and Data Engineering (12), 369–378 (2004) 15. de Medeiros, A.K.A., van der Aalst, W.M.P., Weijters, A.J.M.M.T.: Workflow mining: Current status and future directions. In: Chung, S., Schmidt, D.C. (eds.) CoopIS 2003, DOA 2003, and ODBASE 2003. LNCS, vol. 2888, pp. 389–406. Springer, Heidelberg (2003)

China RoHS: How the Changing Regulatory Landscape Is Affecting Process Equipment Reliability Chris Muller1,* and Henry Yu2 2

1 Purafil, Inc., 2654 Weaver Way, Doraville, GA 30340 USA Purafil Asia, Room 602B, Tengda Plaza, Haidian District, Beijing 100044 China [email protected]

Abstract. In 2006, China promulgated a law entitled “Administration on the Control of Pollution Caused by Electronic Information Products.” The purpose of this law is similar to that of the European Union’s RoHS Directive (2002/95/EC, “restriction of the use of certain hazardous substances in electrical and electronic equipment”). These regulations require the elimination of lead in electronic products and manufacturers now have to comply with RoHS if they want to continue to do business in the EU and China. Corrosion-induced failures were frequent in industrial process control systems even before RoHS regulations with a typical failure mechanism being the reaction of atmospheric sulfur with exposed metals. Corrosion can occur quite rapidly in humid environments especially in the presence of small amounts of atmospheric sulfur and chlorides resulting in e.g., intermittent equipment malfunctions, unplanned shutdowns, or failure of critical systems. This paper will discuss issues related to RoHS compliance, and China RoHS in particular, and the resulting potential for corrosion-related problems. Air quality and failure analysis data will be presented from several sites in China illustrating the fact that in addition to industrial environments, corrosive environments exist in locations that would otherwise be considered benign if not for the changes in electronic equipment mandated by RoHS legislation. Keywords: China RoHS, copper corrosion, corrosion control, electronic equipment, ISA Standard 71.04-1985, process controls, reactivity monitoring, reliability, RoHS, silver corrosion.

1 Introduction In 1998, the European Union (EU) discovered that alarmingly large amounts of hazardous waste were being dumped into landfill sites. Trends also indicated that the volumes were likely to grow 3-5 times faster than average municipal waste. This highlighted a massive, and growing, source of environmental contamination. In order to address these issues, the member states of the EU decided to create the Waste Electrical and Electronics Equipment (WEEE, 2002/96/EC) directive, whose purpose was to: *

Corresponding author.

M. Ma (Ed.): Communication Systems and Information Technology, LNEE 100, pp. 57–69. springerlink.com © Springer-Verlag Berlin Heidelberg 2011

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Improve manufacturers’ designs to reduce the creation of waste, Make manufacturers responsible for certain phases of waste management, Separate collections of electronic waste (from other types of waste), and Create systems to improve treatment, refuse, and recycling of WEEE.

The WEEE directive laid the groundwork for additional legislation and a proposal called EEE (Environment of Electrical & Electronics Equipment) was also introduced along the same lines. However, now this policy is generally referred to as the RoHS Directive and is often referred to as “Lead-Free” legislation. This is not a very accurate nickname, because it extends to other pollutants as well. The European Union (EU) directive 2002/95/EC “on the Restriction of the use of certain Hazardous Substances in electrical and electronic equipment” or RoHS was implemented in July 2006. This directive applies to electrical and electronic equipment designed for use with a voltage rating not exceeding 1,000 volts for alternating current and 1,500 volts for direct current. The requirements of this directive are applicable to the member states of the European Union. The purpose of the directive is to restrict the use of hazardous substances in electrical and electronic equipment and to contribute to the protection of human health and the environmentally sound recovery and disposal of waste electrical and electronic equipment. The EU's RoHS Directive restricts the use of six substances in electrical and electronic equipment: mercury (Hg), lead (Pb), hexavalent chromium (Cr(VI)), cadmium (Cd), polybrominated biphenyls (PBB) and polybrominated diphenyl ethers (PBDE). In order to comply with the EU ROHS legislation, all of these substances must either be removed, or must be reduced to within maximum permitted concentrations, in any products containing electrical or electronic components that will be sold within the European Union. Manufacturers have made significant investments in new processes that will eliminate these substances – especially lead. All applicable products in the EU market must now pass RoHS compliance. In short, RoHS impacts the entire electronics industry and compliance violations are costly – product quarantine, transport, rework, scrap, lost sales and man-hours, legal action, etc. Non-compliance also reflects poorly on brand and image and undercuts ongoing environmental and “due diligence” activities.

2 RoHS – The EU and Beyond Companies selling a broad range of electrical goods in the EU must now conform to WEEE and those same companies must also conform to RoHS. WEEE and RoHS rules, while laid down at the European level, are put into law at the national level. When exporting to Europe, it is essential to comply with national law in each relevant country.1 The EU law simply serves as a template for national laws, which may differ considerably. At the end of February 2006, China promulgated a law entitled “Administration on the Control of Pollution Caused by Electronic Information Products.” The purpose of 1

Croatia, Norway, and Switzerland are not part of the EU. They may nevertheless have legislation implementing EU WEEE and RoHS rules, or similar legislation.

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this law is similar to that of the European Union’s so-called RoHS Directive (2002/95/EC, “restriction of the use of certain hazardous substances in electrical and electronic equipment”). In fact, the Chinese law is simply called “China RoHS” in the industry. While there is some commonality between the RoHS requirements in the EU and those in China, there are also significant differences that must be recognized and dealt with. However, in both instances these RoHS regulations require the elimination of lead in electronic products and manufacturers have to comply with RoHS if they want to continue in to do business in the EU and China. Many consider China RoHS regulations to be considerably more restrictive than those passed in the EU. As described by a potentially-impacted customer: “Without exemptions, it is impossible to build a compliant board” [1]. Although, the regulations are different and are based on different processes, the aims are similar. Convergence of the regulations is not foreseen at present, as it would require high-level negotiations between the EU and China and changes of approach [2]. Some of the key differences between China RoHS and EU RoHS [3]: ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ

The scope is different. The requirements are different. There are no exemptions ... yet. Labels, marks, and disclosure are required. The concept of "Put on the market" is different. The penalties are different. The responsibilities dictated by the law are different. Material testing down to the homogeneous materials in every single part you use to build your product may be required. The regulation has been in force since March 1, 2007. You will have to design labels and issue change orders in order to comply. The standards that you have to comply with just became available in finalized versions.

RoHS regulations are also either in effect or pending in many countries – including Argentina, Australia, Brazil, Japan, Korea, Taiwan, and the United States.

3 Unintended Consequences An aim shared by almost all RoHS legislation is the elimination of lead in electronic products. Thus the main issue for the electronics industry became the use of lead in the manufacture of components and circuit board assemblies. A printed circuit board, or PCB, is used to mechanically support and electrically connect electronic components using conductive pathways, or traces, laminated onto a non-conductive substrate. Alternative names are printed wiring board (PWB), and etched wiring board. A PCB populated with electronic components is a printed circuit assembly (PCA), also known as a printed circuit board assembly). All PCBs have conducting layers on their surface typically made of thin copper foil. If the copper is left unprotected, it will oxidize and deteriorate. Traditionally, any exposed copper was plated with lead (-based) solder by the hot air solder leveling (HASL) process.

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HASL has been working well for many years, is the predominant surface finish used in the industry, and is also the cheapest PCB available. Now RoHS essentially makes PCBs using the HASL process obsolete. Failure modes on other common leadfree PCB finishes such as Organic Solder Preservative (OSP) and electroless-nickel immersion gold (ENIG) make these technologies undesirable. As a result, alternatives such as immersion silver (ImmAg) and organically coated copper (OCC) are currently used as board finishes. Due to inherent processing difficulties with OCC boards, ImmAg boards are becoming the standard PCB finish in the electronics industry [4]. Immersion silver would seem to have a bright future under RoHS [5]. It is easy to apply to the boards, relatively inexpensive, and usually performs well. While ENIG presently has a larger market share, over the past 12 months more immersion silver process lines have been installed in PCB facilities than any other finish. However, some manufacturers have complained about issues with corrosion. If severe enough, this could lead to shorts and ultimate failure of the board. The Internationsl Society for Automation (ISA) Standard 71.04 [6] classifies several levels of environmental severity for electrical and electronic systems: G1, G2, G3 and GX, providing a measure of the corrosion potential of an environment (Table 1). G1 is benign and GX is open-ended and the most severe. Table 1. Classification of Reactive Environments Class G1

Severity Copper Level Reactivity2 Mild

G2 Moderate

G3

Harsh

GX

Severe

Comments

An environment sufficiently well-controlled such that corrosion is not a factor in determining equipment reliability. An environment in which the effects of corrosion are measurable <1000Å and corrosion may be a factor in determining equipment reliability. An environment is which there is a high probability that corrosive attack will occur. These harsh levels should prompt further <2000Å evaluation resulting in environmental controls or specially designed and packaged equipment. An environment in which only specially designed & packaged equipment would be expected to survive. Specifications for ≥2000Å equipment in this class are a matter of negotiation between user & supplier. <300Å

In a study performed by Rockwell Automation [7] looking at lead-free finishes, four alternate PCB finishes were subjected to an accelerated mixed flowing gas corrosion test. Important findings can be summarized as follows: 1) The immersion gold (ENIG) and immersion silver (ImmAg) surface finishes failed early in the testing. These coatings are the most susceptible to corrosion failures and are expected to be much more susceptible than traditional HASL coatings. The use of these two coatings may make the PCB the weak link with regard to the sensitivities of the electronic devices to corrosion. 2

Corrosion is reported as angstroms (Å) normalized to a 30-day exposure.

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2) None of the coatings can be considered immune from failure in an ISA Class G3 environment. 3) The gold and silver coatings could not be expected to survive a mid to high Class G2 environment based on these test results. A leading world authority on RoHS, ERA Technology, has also reported that, “Recent research has shown that printed circuit boards made using lead-free materials can be more susceptible to corrosion than their tin/lead counterparts.” Industry is working diligently to address these concerns but they cannot be addressed overnight. The Reliability and Failure Analysis group at ERA Technology has diagnosed failures in electronic devices due to interaction with low levels of gaseous sulfides – failures that caused both a financial impact to the manufacturers and safety issues with their customers. Recent work showed that corrosion could occur even with measured hydrogen sulfide levels as low as 0.2µg/m3 (0.14 ppb). Another reference describes the formation of a 200 angstrom (20 nanometers) thick layer of silver sulfide in 100 hours at a concentration of just 100µg/m3 (72 ppb) [8]. This is the equivalent of an ISA Class G3 severity level.

4 The Reality of RoHS Corrosion-induced failures have been and continue to be frequent in electronics products used in industrial environments. A typical failure mechanism of electronic systems in these environments is the reaction of atmospheric sulfur with exposed metals – particularly copper and silver. These metals are found in PCB traces, integrated circuit (IC) leads and device terminations. Copper sulfide (Cu2S) or silver corrosion products can grow and creep across surfaces such as IC packages and PCB substrates. Historically, the use of silver in electronic assemblies has been a reliability risk unless the silver is protected from the environment. Silver creep corrosion (electromigration) can occur quite readily in humid environments especially in the presence of small amounts of atmospheric sulfur and chlorides which are common in many paper mill environments. More than twenty years ago manufacturers of distributed control systems (DCS) such as Digital Equipment Corporation (DEC), ABB, and Honeywell described their concerns regarding equipment corrosion in research documents, technical papers, and site planning guides. These companies also provided guidance in terms of environmental conditions necessary to protect their computer equipment (Figure 1) [9]. Manufacturers of industrial computer equipment still specify the control of corrosive gases in their site planning guides and/or the terms and conditions necessary to maintain warranties and service contracts. Even in environments previously considered benign with regards to electronics corrosion serious problems as a direct result of RoHS compliance are being reported. One failure mechanism caused by the lead-free transition was not foreseen by the industry. It was soon discovered that lead-free products with an immersion silver (ImmAg) surface finish will creep corrode in what some electronic equipment manufacturers consider to be high sulfur environments (ISA Class G2 or higher). The

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Fig. 1. Copper corrosion rate distribution guidelines [9].

majority of creep corrosion failures occurred on hard disk drives (HDD), graphic cards, and motherboards in desktop or workstation systems (only those with ImmAg PCB finish were affected). Echoing the study by Rockwell, Hewlett Packard documented several case studies where creep corrosion of ImmAg finish caused failures of computer systems in high sulfur environments (Mazurkiewicz 2006). It was stated that sulfur-based corrosion failures increased dramatically upon introduction of ImmAg surface finish on computer products (due to ROHS requirements). Alcatel-Lucent also has experience with this issue in a paper detailing their work with mixed flowing gas testing of various lead-free surface finishes and their resistance to creep corrosion [10]. Analysis revealed the corrosion products to be copper sulfide (Cu2S) and silver sulfide (Ag2S). High amounts of Cu2S typically indicate the presence of active sulfur compounds such as elemental sulfur (S), hydrogen sulfide (H2S), or organic sulfur

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compounds such as mercaptans. Ag2S can also be formed by these contaminants but can also be formed by exposure to sulfur oxide (SOx) contamination. The most common failures are with the most common components, with the highest incidence of failures being found in capacitors, plastic encapsulated microcircuits (PEMs) and printed circuit boards (PCBs). A University of Maryland study of field failures from 70 companies revealed 30% of ALL failures were capacitors – mainly MLCCs (multilayer chip capacitors) [11].

5 RoHS and Reliability The requirement for corrosion control in industrial environments remains constant. However, more companies are now taking a much closer look at developing or updating specifications due to the changes made by controls manufacturers to comply with the RoHS restrictions on the use of lead. This includes specifying an ISA Class G1 environment for control rooms, etc., where in the past a Class G2 environment was considered acceptable. Specifications are also now showing up requiring the measurement and quantification of silver corrosion rates and the related corrosion products. With many control systems manufacturers opting to use the ImmAg process for their PCBs and other electrical components, and the fact that silver is much more sensitive to lower levels of corrosive gases, we have already seen increased concerns over equipment reliability. As the National Reliability Manager for one pulp and paper manufacturer described it, “The ISA Standard is becoming irrelevant because it does not take into account silver corrosion. All of the new equipment purchased over the last year contains silver and the failure rate for some components is now being measured in months instead of years.” 5.1 Problems with RoHS-Compliant Equipment A recycled paper mill began a project in 2006 to replace obsolete equipment that could no longer be supported (no manufacturer technical support, lack of spares, etc.) with new DCS and programmable logic controls (PLCs). The original hardware had been installed for 15 years and had proven to be reliable and robust. One contributing factor to this was the fact that many of the locations where this equipment had been installed were classified as ISA Class G1 for copper. However, the corresponding silver corrosion rates were up to 20x higher and essentially all of the silver corrosion reported from the analysis of corrosion classification coupon (CCCs) collected over several years was due to sulfur corrosion. This presented some concern based on changes to the equipment due to RoHS compliance. Before starting the replacement program, mill staff was very aware of copper corrosion and the reliability risks associated with exceeding the ISA severity levels specified by the equipment manufacturers. Routine CCC monitoring results showed that copper corrosion was significant but not extreme in many locations; however, the corresponding silver corrosion rates were routinely much higher. On average the silver corrosion rate was 10x that for the corresponding G1 copper rate [12].

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Within three months of replacing the old systems, the mill began experiencing frequent failures of the input/output (I/O) stations installed on the process fieldbus (PROFIBUS).3 A lot of work was put into making the PROFIBUS installations errorfree, and the architectures were reengineered to follow the core rules precisely (i.e., the systems were pulled back to very simple, straight-line installations). These I/O stations or nodes have a number of I/O modules attached to them and communicate the inputs and outputs over the PROFIBUS with the DCS. Since the problems were intermittent and symptoms appeared related to PROFIBUS communication or installation, a full diagnostic process was implemented to capture any and all information about each failure. This included examination of the hardware, the hardware location, its position on the bus, architectures, and software settings. Through systematic investigation and analysis, several potential causes were eliminated and root cause analysis for the remaining issues was performed. Mill staff recognized that the resistance of a choke installed on the base unit of the I/O station to eliminate signal noise was increasing and on failed units was a high or open circuit. Ironically enough this choke was only installed to meet other European legislation pertaining to radio frequency interference (RFI) emissions. The critical issue identified pertaining to this choke was that it is an electronic chip design with a very thin layer of silver on the IC legs in compliance with the lead-free regulations of RoHS. Corrosion of this silver layer destroyed the choke’s connection to the printed circuit and hence the high resistance. Consultation with the manufacturer confirmed the presence of silver on the chokes. The mill was already in the process of installing air cleaning equipment to remove corrosive gases from the air and reduce the rates of copper corrosion, however, the extremely short time to failure for these silver-containing components accelerated this effort in order to prevent additional failures. Staff is confident that these failures were purely the results of RoHS compliance and the use of silver. The lack of information and warnings by the supplier regarding potential issues related to their RoHS compliance programs is troubling considering that even when presented with this evidence, they still concluded these failures were due to “installation errors.” 5.2 Potential Problems Exist Everywhere CCC data from many different locations throughout China show the same trend of environments being classified as an ISA Class G1 for copper but having silver corrosion rates much higher. This indicates serious cause for concern for any electronic equipment using an ImmAg surface finish specifically or any silver or silver-plated components in general. Another contributing factor to concerns over the increased use of silver in industrial applications is that even with tightened control requirements for other environmental parameters (e.g., temperature and humidity) and the positive effect this has on the rate of copper corrosion, silver can still exhibit high rates of corrosion even in well-controlled environments. Closer examination of this CCC database shows that in industrial locations reported as ISA Class G1 for copper corrosion, the 3

PROFIBUS is the dominant fieldbus, with more than 4.8 million of these installed in the process industries by the end of 2008. Utilizing a single-cable “bus” structure, fieldbus eliminates hardwiring in the automation of production lines (http://www.profibus.com/).

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corresponding silver corrosion rate can be up to 10x higher (Table 2). Furthermore, every CCC analyzed shows evidence of sulfur contamination (as Ag2S). In urban locations for many commercial applications such as bank data centers, financial institutions call centers, telecommunications switch centers, and many others, the ratio of silver corrosion to copper corrosion can also be 10:1. On average, however, the amount of silver corrosion measured is 4-5x that of the copper corrosion reported (Table 3) [13]. Contaminant gases containing sulfur, such as SO2 (sulfur dioxide) and H2S, are the most common gases in paper mills, refineries, chemical plants, etc. that cause hardware corrosion and corrosion control in industrial environments is acknowledged as a requirement to assure electrical and electronic equipment reliability. One example of component failure is from sulfur gases entering a component package and attacking the silver resulting in the formation of Ag2S. The mechanical pressure created by the Ag2S formation inside the package damaged its mechanical integrity Table 2. Pulp and Paper Mill CCC Data4 [13]

Location

Area/Room

DC Drive Room Australia DC Drive Rm MCC AHU Room Austria DCS Room Electrical Room Control Room Brazil Operations Room MCC DCS Room China Wet End Control Computer Room DCS Cabinet Finland MCC Control Room Mechanical Room Holland Server Room Splicer Room Control Room Japan IPC Room DCS Room DCS Panel MCC Room Korea PLC Panel Electrical Room USA Wet End Drives Control Room 4

Cu2S 0 0 0 0 182 115 192 205 0 182 182 124 0 0 0 0 0 0 0 0 215 187 204 102 172 196 175

Copper Corrosion CuCu2O Total Unk 101 0 101 142 0 142 112 0 112 180 0 180 78 0 260 46 0 161 101 0 293 88 0 293 125 0 125 104 0 286 78 0 260 44 0 168 118 0 118 106 0 106 150 0 150 68 0 68 78 0 78 105 0 105 173 0 173 231 0 231 62 0 277 61 0 248 56 0 260 50 0 160 34 0 206 81 0 277 86 0 261

Silver Corrosion AgISA Total AgCl Ag2S Unk Class G1 0 1,259 0 1,259 G1 0 2,455 0 2,455 G1 0 2,356 0 2,356 G1 0 3,142 0 3,142 G1 0 3,491 0 3,491 G1 0 1,582 0 1,582 G1 0 1,042 0 1,042 G1 0 1,234 0 1,234 G1 0 948 0 948 G1 0 1,022 0 1,022 G1 0 1,118 0 1,118 G1 0 5,467 0 5,467 G1 0 1,636 0 1,636 G1 0 2,634 0 2,634 G1 0 2,796 0 2,796 G1 0 2,182 0 2,182 G1 0 1,964 0 1,964 G1 0 1,145 0 1,145 G1 0 1,497 0 1,497 G1 0 2,145 0 2,145 G1 0 1,038 0 1,038 G1 0 1,848 0 1,848 G1 0 1,810 0 1,810 G1 0 1,155 0 1,155 G1 35 1,315 0 1,340 G1 0 1,565 0 1,565 G1 0 5,073 0 5,073

The total corrosion measured is actually the sum of individual corrosion films: Cu2S = copper sulfide, Cu2O = copper oxide, CuUnk = copper unknowns, AgCl = silver chloride, Ag2S = silver sulfide, AgUnk = silver unknowns. All data is normailzed to a 30-day exposure.

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Location Bank Headquarters – Tianjin Bank – Beijing Financial Services Co. – Beijing Electronics Co. HQ – Shanghai Financial Services Co. – Shanghai Bank – Shanghai (1) Financial Institution – HK Banking Co. – Shanghai Bank – Shenzhen Investment Co. – Beijing Financial Services Co. – Beijing Bank – Shanghai (1) Banking Company – HK Bank – Shenzhen Industrial Co. HQ – Dong Ying Bank – Jinan Electronics Co. HQ – Zhuhai Bank – Beijing Bank HQ – Tianjin Bank – Shanghai (2)

Cu2S 0 0 110 92 70 0 143 139 159 0 248 258 230 265 299 334 0 426 415 587

Cu2O Cu-Unk Total 69 0 69 75 0 75 40 0 150 88 0 180 121 0 191 205 0 205 69 0 212 90 0 229 91 0 250 268 0 268 67 0 315 89 0 347 121 0 351 91 0 356 80 0 379 75 0 409 465 0 465 85 0 511 179 0 594 180 0 767

G1 copper coupon average G2 copper coupon average

Silver Corrosion ISA Class AgCl Ag2S Ag-Unk Total G1 0 623 0 623 G1 0 636 0 636 G1 0 1,680 0 1,680 G1 0 2,421 0 2,421 G1 0 1,253 145 1,398 G1 0 1,309 0 1,309 G1 0 1,434 0 1,434 G1 0 491 0 491 G1 0 909 0 909 G1 835 96 96 1,027 G2 0 1,666 0 1,666 G2 0 1,047 0 1,047 G2 0 1,476 0 1,476 G2 0 3,200 0 3,200 G2 0 1,603 0 1,603 G2 0 1,833 0 1,833 G2 0 1,549 0 1,549 G2 0 861 0 861 G2 0 1,122 0 1,122 G2 45 1,742 0 1,787

183 G1 silver coupon average 449 G2 silver coupon average

2,128 1,501

and caused the device to fail [14]. This and other failure mechanisms are becoming common occurrences when using RoHS-compliant electronic equipment and components produced using the ImmAg process, and to a lesser degree, the ENIG process. To maintain a high level of equipment dependability and availability, it should be understood that these are dynamic environments where many maintenance operations, infrastructure upgrades, and equipment change activities occur on a regular basis. Airborne contaminants harmful to sensitive electronic devices can be introduced into the operating environment in many ways in addition to the ventilation system. For instance, chlorine can be emitted from PVC insulation use on wires and cables if temperatures inside the DCS cabinets get too high. However, it is still the outdoor ambient air used for cooling and pressurization that remains the primary source of corrosive contaminants and it should be cleaned before its introduction into the control room environment. With the changes to process control equipment due to the RoHS directives, plant managers and operators should include an environmental contamination monitoring and control section as part of an overall site planning, risk management, mitigation, and improvement plan. Included in this plan should be considerations for the assessment of the outdoor air and indoor environment with regards to corrosion potential. ISA Standard 71.04 can be used to provide site-specific data on the types and levels of gaseous contamination and the amount of corrosion being formed. CCCs can be used as a survey tool to

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establish baseline data necessary to determine if and what type of environmental controls are needed. The second part of the plan should be the development and specification of a specific contamination control strategy. Corrosion in an indoor environment is most often caused by a short list of chemical contaminants or combinations of contaminants. The contaminants present in a specific room are highly dependant on the controls put in place to mitigate them. Most often this would involve the selection and application of the appropriate chemical filtration systems to clean both the outdoor ventilation air as well as the indoor air. The final part of the plan would be to establish a real-time environmental monitoring program based on the severity levels established in the ISA Standard. Real-time Atmospheric Corrosion Monitors (ACMs) or Continuous Corrosion Transmitters (CCTs) can provide accurate and timely data on the performance of the chemical filtration system as well as the room air quality [15]. The absence of gaseous contamination controls can be the result of a lack of knowledge and education. Often the relationship between corrosion levels and hardware failures in control rooms is overlooked or unknown. However, due to the continuing efforts of companies like ABB, Dell, Honeywell, HP, IBM, Rockwell, Siemens, and others, this knowledge gap is shrinking and successful corrosion monitoring and control programs are being developed and implemented – assuring reliable operation of process measurement and control equipment. New manufacturing techniques using much thinner conductive components than in previous generations of this equipment, the use of silver as a primary surface finish, and the lack of silver standards from ISA are all contributing factors to an increased risk for electronic process measurement and control equipment used in a paper mill environment. Further, the general lack of information from manufacturers regarding the changes made for RoHS compliance and any resulting reliability issues means that environmental monitoring and contamination control will be mandatory to assure reliable performance and profitable operations.

6 Ongoing and Future Work The amount of corrosion forming over any given period is a primary indicator of how well-controlled an environment may be. It has been proven that if an environment exhibits a reactivity rate of <300Å / 30 days for each copper (ISA Class G1) – without evidence of sulfur contamination (as Cu2S) and silver corrosion – without chlorine contamination (as AgCl) – there is little else that can be done, economically, to improve the environment. Examination of corrosion data from copper and silver CCCs makes it more and more apparent that one cannot accurately determine the true corrosive potential of an environment when following the current methodology of ISA Standard 71.04. This copper-only corrosion monitoring will not and cannot conclusively determine the presence or absence of environmental chlorine or sulfur oxides, and it only provides circumstantial evidence of whether silver corrosion is occurring or not. The fact that the ISA Standard does not take silver corrosion into account when assigning severity levels poses a serious dilemma for those charged with the operation

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and maintenance of critical process control equipment. If monitoring indicates a Class G1 environment (for copper) but there are high levels of silver corrosion, does one go about their business and assume that the environment poses no threat to their electronic equipment? Or do they use silver corrosion monitoring as evidence of an increased risk potential for those components that are now RoHS compliant? These questions are being asked and many are working to provide the answers. The authors are involved with current efforts to update the ISA Standard to include silver corrosion monitoring as a requirement in developing environmental severity levels. The first changes will most likely be to require the use of both copper and silver for environmental assessments with the silver data used both qualitatively (e.g., sulfides present/absent, chlorides present/absent) and quantitatively. Additionally, the Ag2S/Cu2S ratio can be used to indicate humidity effects. 6.1 RoHS Is Here to Stay RoHS costs have been conservatively estimated at $8B industry-wide, yet whether restricting the use of these substances yields even $8B worth of positive environmental impact is questionable [16]. However, the fact remains that there is a perceived environmental benefit to eliminating the lead in the HASL process. Manufacturers of electrical and electronic equipment have to comply if they want to continue to do business in the EU, China, and other countries, and many have taken the ImmAg route as their path to compliance. This has taken care of one issue but has presented new challenges with regards to equipment reliability. Assuring long-term equipment reliability requires working with plant personnel to quantify the corrosive potential of an environment towards the various types of electronic equipment in use, providing engineered solutions for gaseous contaminant control, and ongoing monitoring of the controlled environment to assure compliance with standards and specifications. The successful application of such a corrosion control program in pulp and paper mills, refineries, chemical plants, and many other industrial settings will protect critical process measurement and control equipment and assure profitable manufacturing operations.

References 1. Dills, J.: China RoHS Phase 2: Hard Data Reveals a Red Flag (2007), http://www.emsnow.com/npps/story.cfm?id=24880 2. Barker, C., Xing, W.: Comparative Study of European and Chinese Environmental Measures Restricting Hazardous Substances in Electrical and Electronic Equipment, EUChina Trade Project (2007), http://www.rohs-international.com/site_files/rohsinternational.com/RoHS_Comparative_Study_Final_Report_EN.pdf 3. Kirschner, M.: RohS in China. Conformity Magazine (2006), http://www.conformity.com/PDFs/A07/A07_F25.pdf 4. Mazurkiewicz, P.: Accelerated Corrosion of Printed Circuit Boards due to High Levels of Reduced Sulfur Gasses in Industrial Environments. In: Proceedings of the 32nd International Symposium for Testing and Failure Analysis, Austin, Texas, November 12-16, pp. 469–473 (2006)

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5. UYEMURA International Corporation: Printed Circuit Boards: Final Finish Options (2008), http://www.uyemura.com/library-2.htm 6. ISA: Standard ISA-71.04-1985 – Environmental Conditions for Process Measurement and Control Systems: Airborne Contaminants, International Society for Automation, Research Triangle Park, North Carolina (1985) 7. Veale, R.: Reliability of PCB Alternate Surface Finishes in a Harsh Industrial Environment. In: Proceedings of SMTA International, Rosemont (Chicago), Illinois, September 25-29, pp. 494–499 (2005) 8. Guide to the Compliance with the RoHS Directive [9] Digital Equipment Corporation, Copper Corrosion Rate Distribution Guidelines (2007), http://www.era.co.uk/index.asp 9. Reid, M., Punch, J., Ryan, C., et al.: The Corrosion of Electronic Resistors. IEEE Transactions: Components and Packaging Technologies 30(4), 666–672 (2007) 10. Center for Advanced Life Cycle Engineering, CALCE Long-Term Pb-Free Study (2008), http://www.calce.umd.edu/lead-free/longterm.htm 11. Crosley, G., Muller, C.: How the Changing Regulatory Landscape is Affecting Equipment Reliability, TAPPI EPE Conference (2009) (in print) 12. Purafil .:Corrosion Classification Coupon (CCC) Database (2009) (unpublished data) 13. Anon .: ASHRAE Datacom Series: Particulate and Gaseous Contamination in Datacom Environments (2008) (unpublished) 14. Purafil .: Environmental Monitoring & Assessment Tools (2009a), http://www.purafil.com/products/monitoring.aspx 15. EuroAsia Semiconductor, Substance Regulations, more law! (2006), http://www.euroasiasemiconductor.com/news_full.php?id=7447

Building Process Models Based on Interval Logs Yan-liang Qu* and Tie-shi Zhao College of Mechanical Engineering,Yanshan University, Qinhuangdao 066004, China [email protected]

Abstract. Contemporary process management systems are driven by explicit process models, i.e., a workflow design is required in order to enact a given workflow process. Constructing process models is a complicated and timeconsuming task that requires high expertise. Therefore, techniques for discovering process models have been developed. In this paper, we extend the execution of an activity as a time interval, and present a new method for synthesizing process models from sets of systems’ audit log. A process model graph (directed graph) generated by the method for a process captures all its executions and dependencies that are present in the audit log, and preserves existing parallel. We compare the model graphs generated by the method (interval) to non-interval methods. The observation is that the graphs are more faithful, the number of excess and missing edges is consistently smaller and it depends on the size and quality of the log. Keywords: Process discovery; Process management; Logs; Process models.

1 Introduction Today, process management systems (i.e., workflow management systems) are applied in many organizations. Setting up and maintaining a process management system requires process models which prescribe how business processes should be managed by the system [1]. Typically, the user is required to provide these models. Constructing process models from scratch is a difficult and error-prone task that often requires high expertise. An alternative way of constructing process models from scratch is to extract them from event-based data captured in form of logs from running business processes. The goal of discovering models is to extract process models for business processes from such logs [2,3,4,5]. We assume that the execution of process instances from which we have captured a log is controlled by knowledge that only the actors have in mind. This process-related knowledge is called the implicit model. In the case that a log does not cover all possible ways of executing a process, the discovering process model may be different from the implicit model due to the fact that it contains dependencies between activities which are not part of the implicit model. The obvious limitation of discovering process models is that the quality of a discovering model, with respect to *

Corresponding author.

M. Ma (Ed.): Communication Systems and Information Technology, LNEE 100, pp. 71–78. springerlink.com © Springer-Verlag Berlin Heidelberg 2011

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its implicit model, depends on how much the log covers the implicit model. Also, its characteristic of being the most specific can only be related to the log, not to the implicit model itself. On the other hand, many organizations that run their systems using legacy applications do not have a model of the processes within the organizations [1]. Current tools for model detection operate on the resource level only. Thus, there is a need for tools to build business process level models rather than the resource level. There are few methods for constructing a business process model from information stored in a workflow log (a collection of process execution logs). In this paper, the interval model is introduced. the idea of interval model is unlike the event-based models in which the execution of an activity is represented as a single event, we view the execution of an activity as a time interval based on its starting and ending events that are present in the workflow log. So we can recognize concurrent activities with a single process execution, since intersecting intervals in a process execution represent concurrent activities. In event based models concurrent activities cannot be recognized in a single process execution. In addition, based on the data in a log of some workflow systems we can recognize conditions that specify when activities are immediately concurrent (i.e., modeled as AND-join from some activity in the model). Given a workflow log we show that compared with the event based approach, the interval approach permit the reconstruction of a more accurate process model graph.

2 Related Studies The topic of process discovery is not new [2,3,4,5,6]. Compared to existing work, our work can be viewed as an extension to the event based approach taken by [2,8]. They use a single event to denote the execution of an activity and reconstruct a directed acyclic graph as the model. In [6] Cook and Wolf searched for software processes by investigating events in concurrent environment. They present three methods for process discovery: neural networks, a purely algorithmic approach, Markovian approach. However, they do not provide an approach to generate explicit process models. W.M.P van der Aalst and their research team do much research work in workflow mining. They have designed several different workflow mining algorithms, which include formal algorithms (α, α+ , β ) and heuristic algorithm. The limitations of the α algorithm are loops, invisible tasks and duplicate tasks. In [9] the method is based on time interval. The algorithm is complex and difficult to realize. In [8] Joachim Herbst and Dimitris Karagiann applied inductive approach and machine learning method in workflow mining. However the algorithm only deduced workflow models with sequential structure.. A comprehensive survey on process discovery techniques is presented in [3].

3 Interval Model The workflow’ log contains the recorded basic information that refers to process executions. Each execution of a process is composed of executed activities ordered on

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a time axis. Although in different systems the structure forms of the log are different,the recorded basic information nearly same. For each process instance (execution), logged records contain the following events of an activity: {ready, started, restarted, ended normally, force finished, terminated}. Each record in the log contains additional data such as: time, process name, process ID (an execution), Activity name, Activity ID, and User ID. Some other systems generate richer audit trails that contain more events per executed activity. One example is the MQWorkflow Audit trail that follows the WFMC audit standard and provides logs that contain start and stop events for each activity (in addition to other events), the details of the running business process instance, and its business process template. Life-span. The life-span of an executed activity is to be the time interval from its start event to its termination event. Extended life-span. The extended life-span of an executed activity is to be the time interval from its ready event to its termination event. Since many legal executions may not be present in the log and since parallel activities appear sequentially in an execution, some none dependent activities can be considered as dependent with respect to the log. In a given process log W over T (T is the set of activities of process) ,let a, b∈ T,we can get: a wb: Activities a and b are concurrent activities if one of the following conditions is satisfied: (3-1) ∃a,b in two executions belong W and two executions over the same activities: in one execution: a appears before b; in other execution: a appears after b (3-2) in one execution: aextended life-span∩bextended life-span≠null a→w b: activity b is not a successor of a if for every execution in W at most one of a or b is present. A consistent workflow graph of a given process log is optimal if it has the smallest number of excess and absent edges (with respect to the original model graph) over all consistent workflow graphs defined by that log.

‖

4 Interval Method for Generating a Process Model Graph The interval method is divided into two steps: Step 1: generating process execution graphs A graph is generated for each execution (execution graph). The interleaving of intervals in a single execution makes this graph non-trivial. During this step we keep information of overlap intervals. Next, a single graph is generated for all the execution graphs that have the same set of activities. Step 2: combining execution graphs Combining executions graphs is done in step2. The reason for combining first executions that run over the same set of activities stems from the observation that, in general, they were all run on a single subset of the workflow graph (i.e., the

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parameters for the business process that was used to select the participating edges were the same). Thus, the resulting graph corresponds to a flow graph. So in the end, the process model graph is generated by combining graphs that are generated from the process executions in the log.

Ⅰ

4.1 Algorithm for Step 1 Input: an execution E from a process log where activity events are sorted based on time. Output: an execution graph 1. Scan E from left to right ,find out all pairs of set :,,…, ,set Ai is continuous finished events, set Bi is continuous ready events; 2. Add to the graph each node for each different activity (not distinguish ready state and finished state) in A1,A2,…,An,B1,B2, …,Bn. For every pair (i=1,2, …,n), add edges from each node in Ai to every node in Bi . Fig. 1 is a sample of original workflow graph and following is its three executions where Ti to a ready event and Ti’ is a terminated event.

Fig. 1. An sample of original workflow graph

1. (T1,T1’,T2,T3,T4,T3’,T5,T6,T2’,T7,T4’,T7’,T8,T5’,T6’,T8’,T9,T9’) 2. (T1,T1’,T3,T2,T4,T2’,T7,T3’,T4’,T5,T6,T8,T7’,T5’,T6’,T8’,T9,T9’) 3. (T1,T1’,T3,T3’,T5,T6,T6’,T8,T8’,T5’,T9,T9’)

Ⅰ

For execution 1,we run algorithm : First we get pairs of set: <{T1},{T2,T3,T4}>,<{T3},{T5,T6}>,<{T2},{T7}>,<{T4,T7},{T8}>,<{T5,T6,T8},{T9}> then we can get:

Fig. 2. Execution graph for execution 1

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Also, algorithm applied on execution2 and 3. Fig. 3 shows the result.

Fig. 3. Execution graphs for execution 2 and 3

Because from a single execution we could not be able to find all the available parallel. And at this stage, there may have redundant edges that may be removed when combining the graph with other execution graphs on the same set of activities. 4.2 Step2: Combining Execution Graphs First we combine execution graphs that have the same set of activities. We refer to the new graph as the reconstructed flow graph. In the step 1 we also generated a set of pairs that comprise the “forbidden” edges. If two activities overlap then there is a pair (forbidden edge) in this set. For example, in execution 1 we can get forbidden edges: (T2,T3),(T2,T4), (T2,T5), (T2,T6), (T3,T4), (T4,T5),(T4,T6), (T4,T7), (T5,T6),(T5,T7) ,(T5,T8) ,(T6,T7) ,(T6,T8); In execution 2:(T3,T2),(T3,T4), (T3,T7), (T2,T4), (T4,T7), (T7,T5),(T7,T6), (T7,T8), (T5,T6),(T5,T8) ,(T6,T8) ; In execution 3:(T5,T6),(T5,T8) ; So, in the example, the resulting flow graphs of executions 1 and 2 are given in Fig. 4. We can see that the edges (T7,T8) (T4,T5) (T4,T6) are removed because they are forbidden edges of executions 1 and 2.

Fig. 4. The resulting flow graph of executions 1 and 2

Now we merge all flow graphs to get the merged flow graph. Fig. 5 is the result of the sample. Edge (T3, T8) is a excess edge. At this merge stage, some of the nodes are changed to have an OR semantics. The merge is carried out in a similar way to the previous step but the forbidden set is now empty. As a result there may exist strongly connected cycles in the merged flow graph. So in the last step, it is necessary to break

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Fig. 5. The resulting flow graph of executions 1,2 and 3

the strongly connected components in the merged flow graph and get the finial workflow graph.

Ⅱ

Algorithm for Breaking Strongly Connected Components Given a merged flow graph G = (V, E). N(G): the set of nodes in G; A(G): the set of G’s edges( included in or out edges). Gscc={C1,C2,…,Ck} is the set of strongly connected components in G. For each C∈Gscc , N(C)=Sc Bc Ic Oc satisfied Sc Bc Ic Oc=null The set of nodes Sc is defined as :

∪ ∪∪ ∩ ∩∩ S ={v | v∈N(C)∧A(v) ⊆A(C)} c

The set of nodes Bc is defined as : Bc={v | v∈N(C)

∧ ∃ s,t∈{N(G)-N(C)}∧<s, v>∈A(C)∧∈A(C)}

The set of nodes Sc is defined as :

{

Ic={v | v∈ N(C)-N(Bc)}

∧ ∃ s∈{N(G)-N(C)}∧<s, v>∈A(v)}

The set of nodes Sc is defined as :

∧ ∃ t∈{N(G)-N(C)}∧∈A(v)}

Oc={v | v∈{N(C)-N(Bc)} do

The edges in A(Bc), the edges going from N(Bc) to N(Ic) and the edges going from N(Sc) to N(Ic) are removed ( The reason of moved edges is that there have no depended relations between them.). So the time complexity of the algorithm is O(e·V2),where e is the number of execution and V is the number of different activities in the log.

5 Experiment Results For comparing different algorithms, a process graph generator was designed and used it to generate a process graph and a set of legal flow subgraphs. Executions were made from the flow graphs to serve as input to the algorithms. We tested two algorithms. The interval algorithm (Interval Sorted) and the Non-Interval algorithm. We show the average percentage of missing and excess edges for each of the two algorithms as function of the size of the log.

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In Fig. 6 each input graph has 15 nodes.

Fig. 6. Comparing the algorithm on logs from graph with 15 nodes

The average missing edges percentage of each of the two algorithms is relatively stable and is independent with the log size. The Interval algorithm gives the best results (between 10% and 9%). The average excess edges percentage is relatively stable for the Non-Interval algorithm. the interval algorithms are more sensitive to the size of the logs. For more experiments and details see [11,12]. One issue of concern is the percentage of missing edges. All two algorithms miss some portion of the original edges. This portion does not depend on the number of executions. Interval algorithms are more accurate (in resemblance to the original model) than the Non-Interval.

6 Conclusion In this paper an approach on discovering process models from time-based logs is introduced .This approach has been validated using logs of transactional information systems such as MQWorkflow. The process model graph generated is more faithful in the sense that the number of excess and missing edges is consistently small and is depends on the size and quality of the logs. Process discovery is not restricted to creating new formal process models. Any organization's process will evolve over time, and thus their process models will need to evolve as well. Methods for discovery process may give a process engineer clues as to when and in what direction the process model should evolve, based on data from the currently executing process. Whilst we have focused here on the use of these methods for generating graphical process models, we also believe that they are useful in visualizing the data collected on a process. An engineer may simply be interested in a way to better understand the current process, as captured by the event data. Discovering patterns of behavior may be of help.

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References 1. van der Aalst, W.M.P., van Hee, K.M.: Workow Management: Models, Methods, and Systems. MIT press, Cambridge (2002) 2. Agrawal, R., Gunopulos, D., Leymann, F.: Mining process models from workflow logs. In: Schek, H.-J., Saltor, F., Ramos, I., Alonso, G. (eds.) EDBT 1998. LNCS, vol. 1377, pp. 469–483. Springer, Heidelberg (1998) 3. van der Aalst, W.M.P., van Dongen, B.F., Herbst, J., Maruster, L., Schimm, G., Weijters, A.J.M.M.: Workflow Mining: A Survey of Issues and Approaches. Data and Knowledge Engineering 47(2), 237–267 (2003) 4. van der Aalst, W.M.P., Weijters, A.J.M.M., Maruster, L.: Workow Mining: Which Processes can be Rediscovered? BETA Working Paper Series, WP, vol. 74. Eindhoven University of Technology, Eindhoven (2002) 5. Hammori, M., Herbst, J., Kleiner, N.: Interactive workflow mining. In: Desel, J., Pernici, B., Weske, M. (eds.) BPM 2004. LNCS, vol. 3080, pp. 211–226. Springer, Heidelberg (2004) 6. Cook, J.E., Wolf, A.L.: Discovering Models of Software Processes from Event-Based Data. ACM Transactions on Software Engineering and Methodology 7(3), 215–249 (1998) 7. van der Aalst, W.M.P., van Dongen, B.F.: Discovering workflow performance models from timed logs. In: Han, Y., Tai, S., Wikarski, D. (eds.) EDCIS 2002. LNCS, vol. 2480, pp. 45–63. Springer, Heidelberg (2002) 8. Herbst, J., Karagiannis, D.: An inductive approach to the acquisition and adaptation of workflow models. In: Proceedings of the IJCAI 1999 Workshop on intelligent Workflow and Process Management: The new frontier for AI in Business, Stockholm, Sweden, pp. 52–57 (1999) 9. Golani, M., Pinter, S.S.: Generating a process model from a process audit log. In: van der Aalst, W.M.P., ter Hofstede, A.H.M., Weske, M. (eds.) BPM 2003. LNCS, vol. 2678, pp. 136–151. Springer, Heidelberg (2003) 10. Măruşter, L., Weijters, A.J.M.M.T., van der Aalst, W.M.P., van den Bosch, A.: Process mining: Discovering direct successors in process logs. In: Lange, S., Satoh, K., Smith, C.H. (eds.) DS 2002. LNCS, vol. 2534, pp. 364–373. Springer, Heidelberg (2002) 11. Feng, C.: Workflow Mining Algorithm Research on Time-based Log.Master thesis, Shandong University (2006) 12. Cui, Y-s.: Workflow Management with Openness and Flexibility. Master thesis,Shandong University (2004)

Fostering a Management Model of Librarians at Vocational College e-Libraries Ling-Feng Hsieh1, Mu-Chen Wu2, and Jiung-Bin Chin1,3 1

Department of Transportation Technology and Logistics Management, Chung Hua University 2 Department of Technology Management, Chung Hua University Director of Library and Department of Health Business Administration, Hungkuang University 3 Department of Hospitality Management, Hungkuang University, No.34, Chung-Chie Rd., Shalu, Taichung County, 433, Taiwan [email protected]

Abstract. The most serious difficulty in human resources confronted by the vocational college e-libraries of today in Taiwan are resulted from extreme shortage in number of librarians of various libraries, room for improvement in librarian quality and the lack of performance fostering system for librarians. The paper tries to combine innovative human resource practices and systems of business circle in USA and a concept of competency introduced by the business circle of USA, UK and Japan consecutively, conducts in-depth discussion in terms of the effect of human resources at vocational college e-libraries in Taiwan; and plans to propose human resources management strategies that are beneficial to vocational college e-libraries in Taiwan, so as to achieve a purpose of fostering the performance of library affairs to expect to create new opportunities for future development of vocational college e-libraries. Keywords: Innovative Human Resource Practices and Systems, Competency, Vocational College e-Library.

1 Introduction The vocational colleges in Taiwan nowadays face acute competition and are in an era of rapid change in technology, an innovative thinking and reform is inevitably necessary to cater the trend in order to face various harsh challenges. The library on the one hand plays a role to support class activity and academic research in campus, it on the other hand, plays an extremely important “service” unit in various schools; undertaking great task of “information services” required by teachers and students of entire school. In order to cater information technology that changes with each passing day and strong pressure of competition from libraries of same kind, the vocational college e-libraries of today have to apply many management concepts of business circle to foster the performance of library affairs, in which the authors’ more than a decade experience in vocational college e-libraries has enabled a profound understanding to them that human resource related issues are the biggest problems for M. Ma (Ed.): Communication Systems and Information Technology, LNEE 100, pp. 79–86. springerlink.com © Springer-Verlag Berlin Heidelberg 2011

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such kind of library to manage. The paper tries to further discuss the innovative human resource practices and systems of business circle in USA from various perspectives, with various concepts of competency added on to conduct a discussion. Lastly, it plans to propose human resource management strategies that are beneficial to vocational college e-libraries in Taiwan by referring to authors’ 10 years experience in actual participation in vocational college e-library affairs, so as to achieve a purpose of fostering the performance of library affairs to expect to create new opportunities for future development of vocational college e-libraries.

2 Literature Review 2.1 Innovative Human Resource Practices and Systems Perspective Ichniowski et al. (1996) has summed up the meaning of innovative human resource management is to look for higher level of freedom to work, enhance level and scope of employee participation in decision making and foster employee-employer collaboration within an organization. These systems include workplace innovation, profit sharing to employees and job security [1]. According to Huselid (1995), those create High Performance Work Practices are named as Innovative Human Resource Practices and Systems, and the elaboration of so-called High Performance Work Practices includes comprehensive personnel recruitment, selection and training process; official platform for information sharing, attitude towards work evaluation, position design, complaint handling process and employee management participation plan; performance evaluation, promotion & incentive remuneration system policies and processes to reward employees who report outstanding performance [2]. According to Ichniowski et al. (1995), Innovative Human Resource Practices and Systems extensively refer to various non-conventional work practices applied by the business circle of USA, which are all non-conventional work practices that differ from “conventional work practices such as narrow job descriptions that are in direct proportion with salary level, serious cut between worker and supervisor responsibilities, decision right only limited to management level, official channel is required to achieve communication and solve conflict” [3]. Hsu Lien-en, Kang Shuo-fu (1998) pointed that, most of the outcomes of empirical studies have led to a fact that the facilitation of employee’s participation in decision making, enhancement of employee’s capability or creation of high performance working environments all support the theory of Innovative Human Resource Practices and Systems comparatively, where contributions in reduction in staff turnover, enhancement of business productivity and increase in financial performance are recognized especially. However, it will subject to the effects of factors such as system uncertainty, undefined system combination relationship, organization inertia, distrustful employee-employer relationship, features of industrial technology and industry competition environment while implementing Innovative Human Resource Practices and Systems [4,5]. Pfeffer (1994) has once proposed that the Innovative Human Resource Practices and Systems have many positive effects on the business management including : 1.

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Cautious election of employees, 2. Long-term employment, 3. Relative high salary, 4. Employee participation, 5. Training and development, 6. Job rotation, 7. Bonus and reward, 8. Information sharing, 9. Gap shortening, 10. Regular measurement [6]. 2.2 Competency Perspective A general understanding on the competency studied by McClelland (1973) since 1970s is action characteristics of high achiever in terms of job function. The high achievers here refer to people who are steady and always report high performance. The most significant definition of competency in USA refers to personal characteristics that are highly associated with excellent and sustainable job performance [7]. The concept of competency proposed by Mirable (1997) covers knowledge, skills, ability and other characteristics, which are the so-called KSAOs [8]. Lee You-ting and Wu Wei-wen (2003) have consolidated a trend of development for competency as follows: [9]Generally speaking, competency is originated from McBer Consultancy Company founded by McClelland under the commission of United States Department of State in 1970s and began a study on the performance difference of diplomats. There are applications and promotions of competency devoted by McLagan after the mid-1980s, which were respectively applied to manpower recruitment and competency development of human resource management field. Besides, having a lasting achievement, Spencer has developed a competency dictionary with standard scale, which helps evaluate level of competency. A truly growing stage of competency comes after the mid-1990s, with important catalyst comes from the “Competence at work: Model for superior performance” announced by Mr. & Mrs. Spencer (1993), in which a wave of fever in competency adoption has raised among the enterprises [10]. To sum up impartially, it should be feasible for enterprises to apply a concept of competency to recruitment or selection, education training or competency development, human resource appraisal by looking from the experiences of UK, USA and Japan, while it is more difficult to apply the concept to salary or remuneration. Schoonover, Stephen C. (1998) has proposed that the human resource competency required for future success can be divided into: core competencies, level-specific competencies and role-specific competencies according to a “Human Resource Competencies for the Year 2000: The Wake-up Call” [11].

3 The Applications of Two Perspectives in Vocational College e-Libraries According to various discussions mentioned above, it is known that “Innovative Human Resource Practices and Systems” and competency concepts were highly attended to and practically adopted by the business circle, however, the budget amount the librarian number of vocational college e-library are far less than general university libraries, providing service quality and reader demand that have no difference to general university libraries in reality. Therefore, an introduction of novel and effective human resource practices and systems and concepts to vocational

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college e-libraries in Taiwan will be extremely urgent and important issue. Being part of the members who actually works for the vocational college, the authors shall consider how to apply the Innovative Human Resource Practices and Systems and competency concepts to the human resource practices of vocational college e-libraries effectively and practically, and try to discuss and propose feasible suggestions from below few directions: 3.1 An Angle of Management Philosophy The librarian in the library is one of the key factors that affects human resource management, they have to develop unique management philosophy upon specific targets set upon his/her own departments, which are described briefly as below: 1. Abandon authority of leaders and supervisors. 2. Empower staff with greater rights and responsibilities. 3. Empower staff with higher level of freedom to work. 4. Share a chance of leadership with staff. 5. Provide channels to communicate and solve conflicts. 3.2 Features of Department Culture The management of vocational college e-libraries shall establish specific department culture of their own, the essence of this culture should cover employee’s employment security, sharing of employee’s welfare, complete employment system for the employees, diverse training systems for existing and new employees, staff incentive remuneration system, staff job rotation system, incessant innovation of workplace, immediate problem solving ability, establishment of problem solving team, suggestions hearing from employees, mission related systems establishment by role and responsibility, a concept of library is a “work team”. The library will be attended to and recognized more if vocational college e-libraries possess the culture characteristics of this department to provide professional, swift and correct service quality through kind, proactive and active service attitudes. 3.3 Division of Job and the Innovation The vocational college e-libraries in Taiwan are extremely short of manpower in overall, especially the large-scale book procurement, book inventory checking, book numbering, book processing, data input, book on the shelf, shelf location adjustment and other bulky and trivial tasks. The author has realized that a fence between departments shall be broken and shall subject to no original department structure and workplace limitation as long as it involves the whole library, massive and complicated business. An innovative way of temporary mission grouping and project team establishment shall be fully adopted so as to jointly accomplish the tasks of entire library as there is certain timeline for project team establishment normally, therefore the library should have a managerial and forming system to keep the original organization structure exist as remained to sustain high work efficiency. 3.4 Work Team Learning The vocational college e-librarians are unable to deal with the challenges of rapid change in external and internal environments individually, they need to rely on a

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complete work team, and a concept of teamwork, division of job and innovation adopted and encouraged by Innovative Human Resource Practices and Systems will all foster the performance of library. Therefore, a learning-based organization is required for the vocational college e-libraries in terms of establishing an effective and innovative work team, the librarians shall try the five core disciplines of learningbased organization, to proceed from change of mental model, how to learn anytime anywhere, fostering self competency, develop systematic thinking in a novel way and learn self-breakthrough. 3.5 Cautious Selection and Employment of Librarian The guidelines to select and employ the librarians of vocational college e-library are complied with the Innovative Human Resource Practices and Systems and competency concepts. First of all, the library shall conduct “work analysis” upon the job function of each librarian, i.e. requirements of academic and work experiences, level of job title, authority, expertise & competencies and function by responsibility are criteria of human resource planning to the library, which is also a benchmark for the library to select librarians. Moreover, more and more new librarians selected by vocational college e-libraries nowadays are the so-called “new generation”. This fresh new force within the library refers to people born after 1970s or even after 1980s. According to the study by Wu Mei-lien (2005), the new generation reports low stability in work moods comparatively, a weak sense of connection to the organizations or institutions, emphasizes on egoism, reports lower level of commitment to the organization, is short of thinking and reports stronger subjectivity. Therefore, the libraries have to effectively utilize the characteristics of this new generation, with sufficient freedom and flexibility, compliments and encouragement and in-depth understanding rendered through education training, respect & care, to turn their disadvantages into advantages, which will definitely better expert the manpower of vocational college e-libraries [12]. 3.6 Job Rotation of Librarians The librarians of vocational college e-libraries are universally insufficient; therefore, the library should simplify its business and introduce job rotation system. The job rotation of librarians helps reinforce absorption of diverse experience of librarians among various departments of libraries, and enables understanding between departments and experience sharing; while a faster speed of rotation to work under other departments that causes inability to explore a full view of various job functions should be avoided. 3.7 Training and Development of Librarians Another point to highlight the application of Innovative Human Resource Practices and Systems to the vocational college e-libraries is the continuing education of librarians, which can be considered in terms of following directions:

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1. Design the tour training to enable a comprehensive and clear understanding to the new joined librarians who just enter a professional workplace. 2. Establish a monitoring system; minimize the scope of gap between theory and practice through experience sharing from senior librarians. 3. Accomplish the framework of professional discussion; establish an issue that could enable parallel conversation individually, public discussion on the subject with jointly interest, as well as a professional conversation system that stimulates mutual practices. 4. Reinforce management competencies, for example: human resource management, communication and negotiation skills, use of budgets &funds and capability in decision making and analysis etc. 5. Establish an information update system to precisely take control of expertise and development and movement of information technologies. 6. Acquire information skills, according to Huang Cheng-chun (2000), the librarians of vocational college e-libraries should reinforce network transmission know-how, computer software application and computer hardware maintenance and other information related skills [13]. 3.8 Incentive System of Librarians The vocational college e-library is intrinsically a non-profit organization, in which the incentives to motivate the librarians should combine the goal of library with the goal of individual in one upon following methods: 1. Suggest the school to provide special reward to librarians who report outstanding performance. 2. Provide librarians a better quality, comfortable and pleasant working environment. 3. Provide librarians a fair and smooth promotion procedure. 4. Establish a set of comprehensive further study and learning system for librarians. 5. The school should give more respect, consideration and recognition to the librarians. 3.9 Performance Evaluation of Librarians Performance enhancement of employee and organization is one of the purposes of Innovative Human Resource Practices and Systems and competency concepts. Although the knowledge, competency, skill, performance and level of effort of individual librarian differ from one another, a proper measure for performance evaluation is required to enable more understanding of librarians to the management, and to award them and provide suggestion to their advantages and disadvantages in terms of work, so as to enable good interaction to each other, in which this outcome of performance evaluation can be regarded as an indicator to staff promotion, job transfer, disposal, discharge, training and development; however, they should pay attention to and work hard to establish a set of subjective performance evaluation criteria that comply with the times and shall respect personal differences and encourage exceptional outstanding performance of each individual in order to achieve the purpose of performance evaluation.

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3.10 Problem Solving Skill There are many new ways for vocational college e-libraries to execute the missions; including work team, job rotation, problem solving team, employee’s suggestions and quality related missions, the vocational college e-libraries nowadays should introduce training through a manner of “case study” under a circumstance of extreme manpower shortage, have the librarians developed a deep thought on the questions, propose solutions to the questions, choose solutions and analyze the outcomes of decision makings to foster the quality of librarian and adapt-ability for immediate problem solving.

4 Conclusions There will be tougher challenges for various organizations to face when stepping into the 21st century, in which the human resource will be the most valuable asset to various organizations and there has no exception to the library unit of course. The vocational college e-libraries in Taiwan are now facing challenges such as social environment that varies from minute to minute, a more acute competition between schools, rapid change in information technology and increasing reader demand and a difficulty in manpower shortage generally. Therefore, various libraries should effectively adopt Innovative Human Resource Practices and Systems and competency concepts, and introduce related effective strategies that fully implement to daily library affairs. To sum up, a difficulty in manpower shortage will certainly be solved if vocational college e-libraries fully implement the viewpoints and methods of Innovative Human Resource Practices and Systems and competency concepts, where the library staff will be responsible for the tasks that suit themselves and will be able to create action features and competencies with high performance for the library. The library staff will eventually exert the human resource function of vocational college e-libraries to a level of perfection and create opportunities for the development of vocational college e-libraries!

References 1. Ichniowski, C., Kochan, T.A., Levine, D., Olson, S., Strauss, G.: What Works at Work: Overview and Assessment. Industrial Relations 35(3), 299–333 (1996) 2. Huselid, M.A.: The Impact of Human Resource Management Practices on Turnover, Productivity, and Corporate Financial Performance. Academy of Management Journal 38(3), 635–672 (1995) 3. Ichniowski, C., Shaw, K., Crandall, R.W.: Old Dogs and New Tricks: Determinants of the Adoption of Productivity-Enhancing Work Practices. Brookings Papers on Economic Activity, 1–65 (1995) 4. Hsu, L.A., Kang, S.F.: Innovative Human Resource Practices and Systems (Part I). Employee-Employer Relationship Monthly 17(7), 432–438 (1998) 5. Hsu, L.A., Kang, S.F.: Innovative Human Resource Practices and Systems (Part II). Employee-Employer Relationship Monthly 17(7), 491–495 (1998)

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6. Pfeffer, J.: Competitive Advantage through People: Unleashing the Power of the Work Force. Harvard Business School Press, Boston (1994) 7. McClelland, D.C.: Testing for Competence Rather Than for Intelligence. American Psychologist 28(1), 1–24 (1973) 8. Mirable, R.: Everything You Wanted to Know about Competency Modeling. Training and Development 51(8), 73–77 (1997) 9. Lee, Y.T., Wu, W.W.: A Competency Driven Human Resource Management. Princeton, Taipei (2003) 10. Spencer, L.M., Spencer, S.M.: Competence at Work: Model for Superior Performance. John Wiley & Sons, New York (1993) 11. Schoonover, S.C.: Human Resource Competencies for the Year 2000: The Wake-up Call. Alexandria. Society of Human Resource Management, VA (1998) 12. Wu, M.L.: Human Resource Management: Theories and Practices. Best-Wise, Taipei (2005) 13. Huang, C.C.: A Pushing Hand of Human Resource Revolution: E-Learning. Management Magazine 315, 78–79 (2005)

Extension 2D to 3D of FAN Transform in Image Fan Jing, Xuan Ying, and Li Honglian Optoelectronics Information and Communication Engineering College Beijing Information Science and Technology University [email protected]

Abstract. FAN Transform-set was introduced in paper[1], however, Arnold transform only becomes a special case, the encrypted ability was enhanced since the types of transform was expanded. The factor in FAN Transform is generally significant increase than that is in Arnold, so FAN Transform has a better effect which reduces the computation load. On the basis of paper [1], we extended FAN Transform from 2D to 3D, even to ND. The extension not only complements the theory of FAN Transform, but also extends the application of FAN Transform. In the digital watermarking technology, we adopt FAN Transform to Scrambling the image, since the type of transformation is infinite, we can choose one type to scramble at will, this will enhance the ability of encryption, improve the security. This paper mainly explains the principles of multi-dimensional FAN, and tested the practicability of multi-dimensional FAN by computer. Keywords: Image Scrambling, FAN Transform, N-dimensional.

1 Introduction As an encryption technology, image scrambling has become one of the important means of digital image transmission and security storage. The so-called scrambling make use of the character that the digital image has number arrays, disorganizing the location of image pixels or color to make it into disorder, which can not be identified as the original one. As the image watermarking represents the watermarking of copyright information, scrambling can remove the correlation of watermark image pixel and scattering the distribution of bit errors during the watermark pre-processing and post-processing stage, further, enhance the robustness of the watermark. In image encryption technology, the scrambling technique mainly concerned the strength of the encryption or decryption. However the watermarking technology put emphasizes on: image scrambling has the best results as well as possible. Cost (time and computation) of image scrambling and recovery is as low as possible. Nowadays, people often use Arnold transform, magic square transform, fractal Hilbert curve, Gray code conversion, chaotic sequence and so on. Arnold transform algorithm is easy to achieve, applying in the digital watermarking fields now. But Arnold transform gives only one form, which reduces their security, we can resume the image if we do Arnold Transform step by step. Paper [1] analyzes the principles of FAN Transform expanded the types of Arnold transform, improving the strength of encryption. We introduce multi-dimensional FAN Transform on the basis of FAN Transform in this paper,

①

②

M. Ma (Ed.): Communication Systems and Information Technology, LNEE 100, pp. 87–94. springerlink.com © Springer-Verlag Berlin Heidelberg 2011

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extending FAN Transform from 2D to 3D, even to ND. The extension not only complements the theory of FAN Transform, but also extends the application of FAN Transform.

2

Dimensional Extension of FAN Transform

The definition of normal 2D FAN Transform-sets: ' ⎛ x⎞ ⎛t00 t01⎞⎛ x ⎞ ⎛ N⎞ ⎟⎟⎜⎜ ' ⎟⎟ + K⎜⎜ ⎟⎟ mod N ⎜⎜ ⎟⎟ = ⎜⎜ y t t ⎝ ⎠ ⎝ 10 11⎠⎝ y ⎠ ⎝ N⎠

(1)

K = Max [ABS (t 00 ), ABS (t 01 ), ABS (t10 ), ABS (t11 )]

(2)

Which,

t00,t01,t10,t11 are integer x’, y’ is the pixel coordinates of the original image, x, y is the transformed pixel coordinates of the new image, N is the side of rectangular image(the amount of pixels in one line)

t 00 × t11 − t 01 × t10 = ± 1

and

(3)

formula (3) is the necessary and sufficient condition of FAN Transform. The Inverse FAN Transform below:

⎛ x ' ⎞ ⎛ r00 ⎜ ⎟=⎜ ⎜ y' ⎟ ⎜r ⎝ ⎠ ⎝ 10 Which,

r01 ⎞⎛ x ⎞ ⎛N⎞ ⎟⎟⎜⎜ ⎟⎟ + K ⎜⎜ ⎟⎟ r11 ⎠⎝ y ⎠ ⎝N⎠

mod N

K = Max [ ABS (r00 ), ABS (r01 ), ABS (r10 ), ABS (r11 )]

r00 =

t11　 t 00 × t11 − t 01 × t10

r10 =

− t10 t00 × t11 − t01 × t10

， ，

r01 =

− t 01 t 00 × t11 − t 01 × t10

r11 =

t00 t00 × t11 − t01 × t10

(4)

， (5)

(6)

The principle of 2D FAN Transform also applicable to 3D and even ND. The definition of three-dimensional image of FAN Transform below: ' ⎛ x ⎞ ⎛ t 00 t 01 t 02 ⎞⎛⎜ x ⎞⎟ ⎛N⎞ ⎜ ⎟ ⎜ ⎟ ' ⎜ ⎟ ⎜ y ⎟ = ⎜ t10 t11 t12 ⎟⎜ y ⎟ + K ⎜ N ⎟ mod N ⎜ z ⎟ ⎜t ⎟⎜ ⎟ ⎜N⎟ ⎝ ⎠ ⎝ 20 t 21 t 22 ⎠⎜⎝ z' ⎟⎠ ⎝ ⎠

(7)

Extension 2D to 3D of FAN Transform in Image

89

Which, K is a positive integer, it makes the coordinate value to be a positive value when do Mod operation. t00,t01, t02,t10,t11,t12,t20,t21,t22 are integers. x’, y’, z’ is the pixel coordinates of the original image, x, y, z is the transformed pixel coordinates of the new image, N is the side of square 3D image(the amount of pixels of one side).And

t 00 t11t 22 + t 01t12t 20 + t10 t 21t 02 − t 01t10 t 22 − t 00t12 t 21 − t 02 t11t 20 = ± 1

(8)

In formula (8),the expression on the left of the equal sign is the value of the

t 00

t 01

t 02

t10 t 20

t11 t 21

t12 t 22

determinant: recorded as |T|. The formula above can be recorded as:

，

(9)

|T| = ±1 Now, the inverse FAN Transform below: ⎛ x ' ⎞ ⎛ r00 ⎜ ⎟ ⎜ ⎜ y ' ⎟ = ⎜ r10 ⎜ ⎟ ⎜ ⎜ z' ⎟ ⎝ r20 ⎝ ⎠

r01 r02 ⎞⎛ x ⎞ ⎛N⎞ ⎟⎜ ⎟ ⎜ ⎟ r11 r12 ⎟⎜ y ⎟ + K ⎜ N ⎟ ⎜N⎟ r21 r22 ⎟⎠⎜⎝ z ⎟⎠ ⎝ ⎠

mod N

(10)

Which, K is a positive integer, it makes the coordinate value to be a positive value when do Mod operation.

t t −t t r00 = 11　22 12 21 |T | r10 =

t12　t 20 − t10t 22 |T |

r20 =

t10　 t 21 − t11t 20 |T |

， ， ，

r01 =

t 02t 21 − t01t 22 |T |

r11 =

t 00t 22 − t02t 20 |T |

r21 =

t 01t 20 − t 00t 21 |T |

， ， ，

r02 =

t01t12 − t02t11 |T |

(11)

r12 =

t10t 02 − t 00t12 |T |

(12)

r22 =

t00t11 − t01t10 |T |

(13)

if and only if |T| = ±1,the factor of each inverse transform matrix is integer. So |T| = ±1

(14)

Formula (14) is the necessary and sufficient condition of all of the R array factors are integers. According to the definition above, we can give four 3D FAN Transform examples easily:

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F. Jing, X. Ying, and L. Honglian ⎛1 ⎜ T = ⎜1 ⎜1 ⎝

．

1⎞ ⎟ 2⎟ 3 ⎟⎠

1 2 2

⎛ 2 ⎜ R = ⎜− 1 ⎜ 0 ⎝

− 1

0 ⎞ ⎟ − 1⎟ 1 ⎟⎠

2 − 1

This is an Arnold Transform expanded to 3D and its inverse transform matrix.

2

3

4

．

． ．

⎛1 ⎜ T = ⎜2 ⎜2 ⎝

1⎞ ⎟ 1⎟ 1 ⎟⎠

1 2 1

⎛ 1 ⎜ R = ⎜ 0 ⎜− 2 ⎝

⎛3 ⎜ T = ⎜2 ⎜1 ⎝

2 2 1

1⎞ ⎟ 1⎟ 1 ⎟⎠

⎛ 1 ⎜ R = ⎜−1 ⎜ 0 ⎝

⎛1 ⎜ T = ⎜1 ⎜1 ⎝

1 2 1

1⎞ ⎟ 1⎟ 2 ⎟⎠

⎛ 3 ⎜ R = ⎜−1 ⎜−1 ⎝

No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

t00 1 1 3 1 3 2 2 2 1 2 1 1 1 2 1 1 1 2 2 1 1 2 2 1

t01 1 1 2 2 2 2 1 1 1 1 1 1 1 2 1 1 1 2 1 1 1 2 1 1

t02 1 1 1 3 2 3 2 2 1 1 2 1 1 1 2 1 1 1 2 2 1 1 2 2

− 1⎞ ⎟ 1 ⎟ 0 ⎟⎠

0 −1 1

−1

0 ⎞ ⎟ − 1⎟ 2 ⎟⎠

2 −1 −1 1 0

− 1⎞ ⎟ 0 ⎟ 1 ⎟⎠ T10 1 2 2 1 2 1 1 2 1 1 1 1 2 1 1 1 2 1 1 1 2 1 1 1

t11 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 2 2 2 2

t12 2 1 1 2 1 2 2 1 1 1 1 1 1 1 2 1 1 1 2 1 1 1 2 1

T20 1 3 1 1 2 2 2 3 2 1 1 1 2 1 1 1 2 2 1 1 2 2 1 1

t21 2 2 1 1 1 1 2 2 1 1 1 1 1 1 1 2 1 1 1 2 1 1 1 2

t22 3 1 1 1 2 2 3 2 1 1 1 2 1 1 1 2 2 1 1 2 2 1 1 2

The table below gave some examples of 3D FAN Transform matrixes: As to be requested that |T| = ±1,so if we find an appropriate transform matrix T, then its transport matrix S = TT meets the conditions of |S| = ±1, while the transport matrix

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and the re-transposing matrix of S also meet the conditions of FAN Transform, all of them can be the transform matrixes of FAN Transform. This is to say, if we just find a 3D FAN Transform matrix that is equals to finding four different FAN Transform matrixes. Taking a look at the table above again, in fact, it consists of six kinds of transform matrixes and their eighteen kinds of transport matrixes. Expanding to ND Arnold Transform further: ⎡ x1 ⎤ ⎡1 ⎢ x ⎥ ⎢1 ⎢ 2⎥ ⎢ ⎢. ⎥ = ⎢1 ⎢ ⎥ ⎢ ⎢. ⎥ ⎢. ⎢⎣ xn ⎥⎦ ⎣⎢1

1 1 . 1⎤ 2 2 . 2⎥ ⎥ 2 3 . 3⎥ ⎥ . . . .⎥ 2 3 . n⎦⎥

⎡ x1' ⎤ ⎡N ⎤ ⎢ ' ⎥ ⎢N ⎥ ⎢ x' 2 ⎥ ⎢ ⎥ ⎢. ⎥ + K ⎢. ⎥ mod N ⎢ ⎥ ⎢ ⎥ ⎢. ⎥ ⎢. ⎥ ⎢x' ⎥ ⎢⎣ N ⎥⎦ ⎣ 'n ⎦

(13)

And there are FAN Transform-sets which expanded to ND: ⎡x1 ⎤ ⎡t11 t12 ⎢x ⎥ ⎢t t ⎢ 2 ⎥ ⎢ 21 22 ⎢. ⎥ = ⎢ . . ⎢ ⎥ ⎢ ⎢. ⎥ ⎢ . . ⎢⎣xn ⎥⎦ ⎢⎣tn1 tn2

. . . . .

' . t1n ⎤ ⎡x1 ⎤ ⎡N⎤ ⎥ ⎢ . t2n ⎥ ⎢x''2 ⎥ ⎢N⎥ ⎢ ⎥ ⎥ . . ⎥ ⎢. ⎥ + K⎢. ⎥ mod N ⎥⎢ ⎥ ⎢ ⎥ . . ⎥ ⎢. ⎥ ⎢. ⎥ . tnn ⎥⎦ ⎢x''n ⎥ ⎢⎣N⎥⎦ ⎣ ⎦

(14)

Which, K is a positive integer, it makes the coordinate value to be a positive value when do Mod operation. The ND FAN Transform can be set up only if the determinant made up by matrix T meets the condition of |T| = ±1. The Inverse FAN Transform below:

⎡x'1 ⎤ ⎡r11 ⎢'⎥ ⎢ ⎢x 2 ⎥ ⎢r21 ⎢. ⎥ = ⎢ . ⎢ ⎥ ⎢ ⎢. ⎥ ⎢ . ⎢x' ⎥ ⎢r ⎣ n ⎦ ⎣ n1

r12 . . r1n ⎤ r22 . . r2n ⎥ ⎥ . . . .⎥ ⎥ . . . .⎥ rn2 . . rnn⎥⎦

⎡x1 ⎤ ⎡N⎤ ⎢ ⎥ ⎢ ⎥ ⎢x'2 ⎥ ⎢N⎥ ⎢. ⎥ + K⎢. ⎥ mod N ⎢ ⎥ ⎢ ⎥ ⎢. ⎥ ⎢. ⎥ ⎢x ⎥ ⎢N⎥ ⎣ 'n ⎦ ⎣ ⎦

(16)

Which, matrix R is the inverse matrix of matrix T, and all the elements of matrix T and matrix R are integers.

3

The Simulated Result of 3D FAN Transform

An example of a 16 long side gradient color square below:

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Fig. 1.

Do FAN Transform once with the 3D Transform matrix (1, 1, 1, 1, 2, 2, 1, 2, 3), the result below:

Fig. 2.

Then, do three times FAN Transform, the result is:

Fig. 3.

An example of a 32 long side gradient color square below:

Fig. 4.

Extension 2D to 3D of FAN Transform in Image

93

Do FAN Transform once with the 3D Transform matrix (1, 1, 1, 1, 2, 2, 1, 2, 3), the result below:

Fig .5.

Then, do twice FAN transform, the result is:

Fig. 6.

As we can seen from the scramble result, it is very difficult to indentify the original image.

4 Summary In this paper, we discuss the FAN scrambling transform-sets which contain infinite kinds of transform matrixes based on dimensional expanding, 3D FAN Transform can be applied to 3D image scrambling encryption, and simulated on microcomputer. It is illustrated that the FAN Transform expanding from 2D to multi- dimensional is rational, and analyzed the property of 3D Transform matrix. The restoration of spontaneous circulation (ROSC) frequency of multi- dimensional FAN Transform equals to the frequency of 2D FAN Transform and Arnold Transform, there is no analytical expressions at present, it is remained to be studied in the further.

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Aknowledgement This research is supported by National Special Important Science & Technology Research Program (No.2009ZX05042-002-04) and Supported by Human Resources Plan of Beijing Municipal Education Commission (Grant No. PHR200907219)

References 1. Jing, F., Honglian, L.: Image Scrambling By FAN Transform. In: The 2nd International Conference on Image Analysis and Signal Processing, April 9-11 (2010) 2. Wang, X., et al.: Information Hiding Techniques and Applications, pp. 85–109. Mechanical Industry Press, Beijing (2001) 3. Xiong, C., Zou, J.: Digital Image Scrambling Sampling Techniques and Analysis of Results. North China University Journal 14(3), 5–12 (2002) 4. Qiuqi, R.: Digital Image Processing. Publishing House of Electronics Industry, Beijing (2001) 5. Jia, S., Huang, R., Wen, X., Ye, W.: Scrambling and chaos based encryption of digital image watermarking technology research. Journal of Beijing Normal University 41(2), 146–149 (2005) 6. Qi, D., Li, T., Zhang, Z.: A new image scrambling transformation and its application in image information hiding China science(E), vol. 30(5), pp. 440–447 (2000) 7. Ding, W., Yan, W., Qi, D.: Scrambling and integration based on digital image hiding technology and applications. Chinese Journal of Image and Graphics 5A(8), 644–649 (2000) 8. Sun, X., Lu, L.: Arnold Transform in Digital Image Watermarking in applied research. Information Technology (October 2006) 9. Zou, J., Tie, X.: The two dimensional digital image transformation and its cyclical Arnold. Journal of North China University 12 (March 2000) 10. Kong, T., Zhang, Q.: New algorithm of Arnold inverse transform. Software Journal 15(10), 1558–1564 (2004) 11. Tan, Y., Liang, X., Zhang, J., Liu, K.: Scrambling Technology Based on Arnold Transform. Microcomputer Information 22(12-3), 74–76 (2006)

A Design of Low Cost Infrared Multi-touch System Juan Wu1,2,3, Yao-hui Hu1,3, Guo-qiang Lv1,3, and Jing Yin1,2,3 1

Key Laboratory of Special Display Technology, Ministry of Education, Hefei Anhui 230009, China 2 School of Instrument Science and Opto-electronic Engineering, Hefei University of Technology, Hefei Anhui 230009, China 3 Academe of Opto-electronic Technology, Hefei University of Technology, Hefei Anhui 230009, China [email protected], [email protected], [email protected], [email protected]

Abstract. This paper discusses a implementing scheme of infrared multi-touch system. In this scheme, we first employ a preprocessing which combined meanmedian filter with weighted recursive filter. And then the algorithm of mass center is adopted to get the precise position where users touched. Afterwards, we discuss a gesture identification method for multi-touch which is suitable for infrared touch panels. At last, we set up a experiment platform based on C8051F340 to implement and test this algorithm. The result shows that, a infrared multi-touch system is achieved which has the advantage of simple, accurate coordinates, and smooth moving. Keywords: infrared touch panel; filtering; multi-touch; C8051F340.

1 Introduction In recent years, multi-touch as a nature Human Computer Interaction device, with its convenience and nature gesture gets more and more attention. At present, the common used multi-touch can be falled into two broad categories based on the method of recognition and interpreting multiple simultaneous touches[1, 2]. One is sensor based, and the other is based on Computer-Vision. Sensor based touch screen can be divided into resistive touch screen, capacitive touch screen, surface acoustic wave and infrared touch screen [3, 4, 5]. In the mode of realization, computer-vision based system, because of containing a camera, costs high and has a complicate structure[6, 7]. Infrared touch panel, compared with the other sensor based systems, has the advantage of high translucent, long working life for not afraid of scratching, has cost performance especially in large-size display [8]. This article discusses a implementing method of infrared touch pannel, which has the feature of simple structure, high anti-interference, move smooth. In this paper, first, we analysis the touch signal, study preprocessing algorithms for touch signal and technique for implementing multi-touch. Then, we employ a low-cost MCU C8051F340 to build an experimental platform for realizing with this method. Finally, the experimental results of this system are analyzed and discussed. M. Ma (Ed.): Communication Systems and Information Technology, LNEE 100, pp. 95–101. springerlink.com © Springer-Verlag Berlin Heidelberg 2011

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2 Algorithm for Implementation Infrared touch panel arranges transmitters and receivers in parallel forming a infrared array, and the receivers sense infrared light from transimitters reflected by a finger. Whenever a finger on the screen, infrared light in certain area is not able to receive the light from the tansmitters, and it will each generate a maximum value on the x-axis and y-axis see Fig.1. Based on this, following coordinate resolution, we display the touched points on screen. In system realization, touch panel exists unstable coordinates, whose influence is not obvious in single touch, however, when used for multi-touch, especially for fast moving fingers, leading to gesture recognition errors. We believe that there are two main causes:

Fig. 1. Theory of infrared touch panel

1. Infrared light of the receivers is sensitive to the fingers movement, so it may swing with a subtle change of the fingers, especially serious when fingers just go on or will soon leave. Therefore, the sampling of touch information has sudden impulse disturbance and periodic interference. Particularly for touch panel must have quick reasponse to user’s actions, so the sampling frequence is high, and coordinates vibrate. 2. Physical coordinates are deside by the number of sensors and the extender position in the corresponding sensor. However, single touch coordinates only judged by the number of sensors, touched or untouched which has low resolution. When the number of sensors is low, mouse jump phenomenon is serious. Hence, even if the sensors closely packed, the display resolution cannot meet the requirements, for that the width of a sensor is 5mm, 8.6mm high, and 940nm wave length. 2.1 Signal Preprocessing we have to increase sampling frequency to satisfy rapidly changing fingers, as exsiting impulse and periodic interference at the same time, a suitable preprocessing algorithm is demanded. The preprocessing presented in this paper, first is to return all the sampling value to zero, that means each sensor subtract its DC element. Then adopt a filter method which combined mean-median filter with weighted recursive filter, to eliminate signal interference, compensate mouse drift. After pretreatment, we employ mass center theory to compute coordinates in order to process the final touch events, such as gesture arithmetic.

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Mean-median filter is a neutralized filtering method which mixed median filter and arithmetic mean, plays a good effect to sudden impluse disturbance. Its main idea is ordering the sampling data X1, X2, …, Xn by size, X1< X2<… <Xn. Remove the maximum and minimum, and we compute arithmetic mean with the rest data. With function(1) we are able to get the result.

x = ( x2 + x3 + ... + xN −1 ) /( N − 2)

(1)

Weigted recursive filter is improvement of recursive filter. It gives different weight to continuous sampling data of each sensor, the later sampling data is, the bigger weight given. Filter algorithm for N-sampling can be seen in function (2). x=C1x1+ C2x2+ …+ CNxN

，

(2)

Where C0 C1,… , Cn are constant, denote the weight of sampling data Xi, the bigger Ci is, the more contribution to the process. Due to cutting down rounding errors and increasing mouse send times, we choose four times for mean-media filter and three for recursive filter, where the constant we select C0=1/4 C1=1/4 C2=1/2. Here we get the balance of frequence of coordinates sending and data wave, according to the experiment data.. This algorithm combines the advantage of median filter and recursive filter, benefits to sudden pulse disturbance and periodic interference.

，

，

2.2 Coordinate Resolving Carefully observe the characteristics of sampled data, we found one finger may block up to four sensors at one time, and varied to each sensor. In this paper, we separate mapping process into quantization and mass center calculate. Quantization means that touch signal is divided by the correspoding sensor data when completely blocked, the percentage of full touched is got. Mass center is an illusion point where quality converge. First, on the basis of many experiment, we select a threshold to determine the position of touched sensor k. And then calculate the quantization of the sensor k, k-1, k-2, k-3 respectively. We can achieve the precise location of touched point from function (3), if we see the width of each sensor as 1.

x = k − 1 + ( data[k ] − data[k − 1] + data[k + 1] + data[k + 2]) / 2

(3)

Where k indicates the kth sensor is touched, and data[k] is its quatization value. Due to the linear relationship of sensor and resolution, we use the touched center x from function (3) to obtain coordinates as function(4). With the same method, Y coordinates are achieved. X=xRes*x/N

(4)

Where xRes is the resolution of X-axis on the display, and N is the sensor number on horizontal axis. 2.3 Multi-touch Gesture Recognition Gesture can be classified into single touch and multi-touch[10]. In single touch, which only has one touched point, we can realize click, double click, and drag. Multi-touch

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in this paper is multi-touch gesture, we control the graphical interface including move, zoom, rotation and scroll using two fingers. However, when there are two fingers touched, each axis has two touched points, which make up four points see Fig.2, and we can not deside which two are the exact touch points, leading to gesture recognition error. Some system cite time sequence to distinguish, believe that one finger always after the other[9], yet there is always the situation that touching at the same time, here we only judge by guessing. In this paper, we recognize gestures by movements of the coordinates in the up left corner and down right corner in a touch circle see Fig.3, which is the average time that fingers stay on the touch panal according to peoples normal habit. Next, we will introduce the judge process and parameter in detail.

Fig. 2. Coordinates exsiting false touched points

Fig. 3. Gesture recogniton

A: Zoom When the two touched points move closer or further to each other, and the rate of its Euclidean distance change exceeds our threshold, we see it as zoom. We use the change trend of maximum and minimum coordinates in a touch cycle, mentioned above, to calculate the zoom ratio. If the Euclidean distance becomes bigger, we zoom in the picture, otherwise zoom out. The width and height after transform can be obtain by function (6,7). Fig.4(a) clearly shows the disposition of zoom in, where A(xa ya), B(xb yb), is the coordinates before judgement, and C(xc yc), D(xd yd) are the latest coordinates.

，

，

，

，

Width = WidthPr e + ( xc − xa ) + ( xb − xd )

(6)

Height = Heigh Pr e + ( y c − y a ) + ( y b − y d )

(7)

B: Rotation When one touch anchors as focus position, while the other rotating around the focus point is detected, as Euclidean distance invariant, we see it rotation. However rotation a picture is not as obvious as it might seem at first because of the two false touched point. It not only contains the judge of rotation, but also rotation angle compute. We use curve fitting error and Euclidean distance to identify. In order to obtain the accurate rotation angle, we adopt trigonomrtric function (8) as Fig.4(b) shows. Follow this, we can rotate a picture in any angle with 0-360o.

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（ ）Zoom in (b) Rotation

Fig. 4. Multi-touch gesture recognition a

cosA=(a2+b2+c2)/2ab Where a, b are the Euclidean distance before rotate and after rotate, and rotation angle.

(3) A is the

C: Movement or scolling It will be move or scroll, when all touched points close to each other and move as a whole on the panel. The dragging distance is equal to the movement of touched points.

3 Experimental Platform In order to verify the feasibility of this scheme, in this section, we choose low cost MCU C8051F340 to set up a test platform. The main parameters of the MCU: 8051compatible microcontroller core, up to 48 MIPS; true 10-Bit 200Ksps ADC; 1KB USB FIFO RAM, support full speed transfer of 12Mbps; 64KB FLASH, 4KB RAM; precision internal calibrated 12 MHz oscillator and 4x clock multiplier. We designed a multi-touch system to apply to 15-inch LCD(4:3). Touch panel parameters: 63 sets of infrared LEDs on horizontal axis, 51 sets on longitudinal axis. Horizontal and vertical infrared LEDs form an orthogonal array in front of the display. We employ the algorithm including preprocessing, coordinates resolving introduced above to deal with the touch signal after A/D conversion. The results are sending to the host, which is Pentium 4 processor, 3.0GHZ, and 256MB memory. In the host computer, we develop a test software using VC for receiving and displaying the data from MCU, showing the function of multi-touch.

4 Result and Discussion In the test software, we give the same width to each sensor on x-axis, and draw sampling data on y-axis, received from MCU. Fig.5 shows the wave when one finger touched. The first half wave in x-axis shows the sampling value of horizontal, and the last is the data on vertical axis. Through the original data Fig.5(a), we see that the

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Fig. 5. Sample value one finger touched (a) original data (b) data after preprocessing

value of each sensor has great difference to each other, touch signal vibrates and it can not fully express touch information. After returning to zero and filter, we can see the data wave shows in Fig 5(b). There are only minor changes, untouched sensor close to zero, and the peaks can be fully show the touch information. We join all the touched coordinates in VC, with a staight line see Fig.6, after coordinates mapping. Among them, Fig.5(a) is the coordinates result that with the original data, existing obvious mapping errors. After preprocess without mass center theory, we get the touch path as Fig.5(b). Here serious mistakes disappeared, yet the movement error is still big, can not say touch path accurately. Fig5(c) is obtained follow the program discussed in this paper. In this picture, we can see the program not only remedy jitter, but also make move much more smooth. Success rate of coordinates sending can respectively be 95 times/sec and 89 times/sec for without filter and after preprocesing.

Fig. 6. Touch path (a) without filter (b) without mass center algorithm (c)result in this paper

When used for multi-touch, gesture recognition errors caused by mistake coordinates is obvious, and low-resolution add the opportunity of recognition error. Experiments show that the pretreatment and coordinates resolution method discussed in this paper, enhanced the application of infrared touch panel in multi-touch.

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5 Conclusion This article discussed a implementation program for infrared multi-touch. In the program, we preprocessed the signal data of sensor first of all, which including return to zero, mean-median fiter and weighted-recursive filter. Then centroid principle is adopted to compute touch center. Afterwards, from gesture recognition, we achieved click/double click/drag in single touch, and zoom/rotation/move in multi-touch. Finally, low-cost C8051F340 as the experimental platform, built a infrared multitouch system for 15-inch LCD, and developed a test, observe software using VC in host computer to verify the feasibility of this program. Experimental results show that the program implements a cost-effective system, which has the ability that simple, accurate coordinates, and smooth moving, successful coordinates delivery rate up to 89 times/sec. Besides that it can response to touch command quickly and accurately in multi-touch.

References 1. Buxton, B.: Multi-Touch systems that i have known and loved. J. Microsoft Research (2009) 2. Chang, R., Wang, F., You, P.: A Survey on the Development of Multi-touch Technology. In: J. Asia-Pacific Conference on Wearable Computing Systems, pp. 363–366 (2010) 3. Rekimoto, J.: Smartskin: an infrastructure for freehand manipulation on interactive surfaces. In: J. Proceedings of the SIGCHI conference on Human factors in computing systems: Changing our world, changing ourselves. CHI 2002, pp. 113–120. ACM Press, New York (2002) 4. Dietz, P., Leigh, D.: Diamondtouch: a multi-user touch technology. In: Proceedings of the 14th annual ACM symposium on User interface software and technology, UIST 2001, Orlando, Florida, November 11 - 14, pp. 219–226. ACM Press, New York (2001) 5. Apple iPhone, http://www.apple.com/iphone/technology/ 6. Han, J.Y.: Low-cost multi-touch sensing through Frustrated Total Internal Reflection. In: Proceedings of the 18th Annual ACM Symposium on User Interface Software and Technology, pp. 115–118. ACM Press, New York (2005) 7. Morrison, G.D.: A camera-based input device for large interactive displays. J. Computer Graphics and Applications 25(4), 52–57 (2005) 8. Lee, B., Hong, I., Uhm, Y., Park, S.: The Multi-Touch System with High Applicability using Tri-axial Coordinate Infrared LEDs. J. IEEE Transactions on Consumer Electronics. 55(4), 2416–2424 (2009) 9. Bérard, F., Laurillau, Y.: Single user multitouch on the DiamondTouch from 2 x 1D to 2D. In: J. Proceedings of the ACM International Conference on Interactive Tabletops and Surfaces ITS 2009, pp. 1–8. ACM, New York (2009) 10. Kim, S.-G., Kim, J.-W., Bae, K.-T., Lee, C.-W.: Multi-touch interaction for table-top display. In: Pan, Z., Cheok, D.A.D., Haller, M., Lau, R., Saito, H., Liang, R. (eds.) ICAT 2006. LNCS, vol. 4282, pp. 1273–1282. Springer, Heidelberg (2006)

A Review of Research on Network-on-Chip Simulator Haiyun Gu College of Information Engineering, Shanghai Maritime University, Shanghai 200135, China [email protected]

Abstract. The huge design space of Network-on-Chip raise the need of simulators for NoC to efficiently evaluate the performance and select the optimal architecture. This paper presents a review of research on NoC simulators, differentiates the current approaches into three categories: regular network simulators, dedicated NoC simulators, and full-system simulators. We compares the current NoC simulators according to topologies, routing and switching algorithms, traffic models, and discuss the open issues and developing trends in this field. Keywords: NoC, simulator, traffic model.

1 Introduction The amount of hardware resources on a single chip continues to increase. SoCs (System-on-Chips) will integrate hundreds of heterogenous IPs. It is not an easy task to connect all those IPs together and meet the high communication demands. Moreover, the interconnet’s area and power become more significant compared to the transistor’s. The major challenge to SoC designers shifts from computation to communication. NoC (Network-on-Chip), borrowing the communication technologies from the wide area computer networks, is a promising approach to providing a high performance interconnection architecture on a chip. Previous works proposed many different forms of NoC, such as mesh, torus, bipolar tree, application-specific toplogy, etc., along with different routing algorithms and strategies. So it is difficult to select the right form of NoC for a particular design. This raise the need of simulators for NoC to efficiently evaluate the performance and select the optimal interconnection network.. Currently we can mainly differentiate three categories of NoC simulators. The first category is regular network simulators, borrowing from the computer and communication network, such as NS-2[1,2], opnet[3], and OMNET++[4], utilizing the similarities that exist between general networks and NoC. The second category includes several dedicated NoC simulator, such as Nostrum[5], Noxim[6], Nirgam[7], NoCSEP[8], and a JAVA NoC simulator[9]. Most of them implement a high-level representation of NoC, modeling data at message level, providing a set of architectures and protocols, and evaluating the network with the chosen traffic pattern in terms of latency and throughput. Besides, Orion[10] and Ocin_tsim[11] concentrate on the power and area simulation of NoC. DRAGOON[12] proposed a simulator for M. Ma (Ed.): Communication Systems and Information Technology, LNEE 100, pp. 103–110. springerlink.com © Springer-Verlag Berlin Heidelberg 2011

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dynamically reconfigurable NoC. The third category integrates a NoC model into a full-system simulator. GARNET[13] is a NoC model integrated into GEMS, which is a simulation platform for CMPs. All three categories of NoC simulators have their advantages and limits. This paper presents a review of current research on NoC simulators. In section 2, 3, and 4, we compare the existing three categories NoC simulators, and discuss several open issues organized on three aspects: the hardware architecture, the routing protocol, and the traffic pattern. Finally we conclude the current research state of NoC simulator, and suggest the trends in this field.

2 Regular Network Simulators The primary difference between NoCs and general networks is in the size of the two. Because of small dimensions, NoC don't have enough resources for NIC or buffer, but it do have large bandwidth for communication compared to general networks. It means that easier protocols need to be designed for NoCs which require minimum logic and memory resources. ï NS-2, OPNET and OMNET++ are open source, object-oriented and discrete event driven network simulators written in C++. They are very common and widely used tool to simulate computer and communication networks. There are some previous works using these network simulators to evaluate NoC. Because it has been shown that on-chip traffic can exhibit self-similarity, which is also referred as LRD (long-range dependence) [14], [1] used a long-range dependent traffic model to simulate a 8*8 mesh NoC with NS-2. It is convenient for NS-2 to generate arbitrary kind of traffic. The used routing algorithm is Dijkstra’s SPF (Shortest Path First). The simulation results just showed the common relations among loss rate, buffersize and delay. [2] considered about the permanent or transient failures of the communication links under the deep submicron technology, modified the NS-2 simulator to assess their fault tolerant routing protocol, which included a low cost, efficient and fast packet retransmission mechanism to deal with transient faults in NoCs, and a dynamic routing protocol suitable for NoCs in order to deal with permanent faults occuring on-chip. [3] used OPNET to analyse the latency and power of a 4*4 mesh NoC with XY routing, uniform traffic model, and multiple topologies. [4] simulated a 2D torus NoC by OMNET++ choosing wormhole switching and exponential traffic model. Regular network simulators usually have a huge variety of protocols and various topologies can be created with little effort, but they cann’t deal with the logic gates. Although it is simple to simulate a NoC at behaviour level, but it is impossible to obtain a structual or physical design view of NoC by using the regular network simulators.

3 Dedicated NoC simulators Regular network simulators are targeted towards the simulation of large networks with complicated protocols, and the traffic models in them are not representative for

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on-chip traffic. Researchers in NoC field are motivated to develop several dedicated NoC simulators. Nostrum[5], Noxim[6], and Nirgam[7] are open code simulators written in SystemC. They provided configuration commands to define the architecture of NoC (mesh, torus, tree, ring), the routing algorithm (XY routing, source routing, adaptive routing), flow control (wormhole, deflection), and traffic model (possion, burst, on/off, CBR, and input trace). The evaluation standards include the latency, the throughput and the link utilization. Figure 1 shows a typical evaluation flow of NoC simulator.

Fig. 1. A typical evaluation flow of NoC simulator

NoCSEP[8] means the “NoC centric System Exploration Platform”. The special feature of this work is to introduce a quasi-formal description language called “Parallel Application Communication Mechanism Description Language” (PACMDL) to describe the task-graph features of any parallel application. PACMDL was used to drive the application traffic generator which was represented by thread modeling in Fig. 2.

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Fig. 2. Application modeling of NoCSEP

So, NoCSEP can use the application-driven traffic model to simulate the parameterized NoC. Apparently that is very useful to optimize the design of application specific NoCs. [9] proposed a dedicated NoC simulator written in Java, which processes the messages at flit level, implements routing policies and flow control, and collects measurement data. Fig. 3 shows the block diagram of this Java NoC simulator. The paper gave the simulation results of mesh topopogy NoC, with wormhole routing and uniform traffic. It was claimed that Java brought the advantage of portability to this NoC simulator. The dedicated NoC simulators parameterize the NoC at a high level and provide the evaluation of features such as different topologies, variable buffer size, link utilization, routing stratgies, and traffic models. Besides all these dedicated NoC simulators we discussed above, there are several special NoC simulators which respectively enhanced these abstract simulators above in different aspects: ORION[10] intoduced a power and area models for NoC, which has been widely used for early-stage NoC power estimation in literature and industry. Ocin_tsim[11] proposed a DVFS (dynamic voltage frequency scaling) aware NoC simulator with an ORION instance for each node to compute the per-node power consumption. GARNET[13] also incorporates ORION 2.0 power models for power estimation.

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Fig. 3. Block diagram of Java NoC simulator

Fig. 4. Conception flow of DRAGOON

DRAGOON[12] is a dynamically reconfigurable architecture compliant generator and simulator of network. It was used to generate and simulate the DRAFT, a fat-tree topology NoC which can be dynamically reconfigurable depending on the partial reconfiguration capacity of its underlying Xillinx Virtex 5 FPGA. Fig. 4 shows the flow of DRAGOON.

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4 Full-System Simulator A major challenge when designing a NoC simulator is to achieve the right balance between the level of abstraction, and the accuracy and the speed of simulation. Most dedicated NoC simulators used stand-alone models to evaluate the performance of the interconnect architecture, not the performance of the full system. [13] proposed GARNET, a detailed cycle-accurate interconnection network model, to enhance the GEMS full-system simulation platform for CMPs. GARNET model is highly parameterizable and flexible. Various network properties, such as number of VCs, buffer size, number of pipeline stages, flit size, etc., can be passed as parameters. The topology of GARNET is extracted from the GEMS, and can be arbitrary. With the integration of ORION into GARNET, GEMS with GARNET can report full-system power and performance results. Apparently full-system simulator can improve the simulation accuracy and efficiency, but GEMS is just used for CMPs. Similar design tools need to be developed for application specific MPSoCs.

Fig. 5. GEMS (with GARNET incorporated) overview

5 Conclusion To complete our investigation work on NoC simulators, a survey of some reseach and design methods for NoC simulators is presented in Table 1. In this paper, we classify the current research results on NoC simulators into three categories. Comparison of these simulators is done according to topologies, routing and switching algorithms, traffic models. The regular network simulators are flexible and complexed. The dedicated NoC simulators are specific, but the performance need to be improved. The full-system simulator is just for CMPs, similar development tools need to be invented for MPSoC. We should note that most simulations of NoC used

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Table 1. Survey of research of NoC simulators Category

Regular network simulators

Research

Language

topology

Routing, switching

Traffic model

NS-2 with LRD traffic model[1]

C++ and Otcl

mesh

Dijkstra’s SPF

LRD (long range dependence

NS-2 with fault tolerant routing[2]

C++ and Otcl

mesh

2D, 3D mesh, torus, ring, shared-bus OMNET++[4] C++ 2D torus SystemC and Mesh, torus, Nostrum[5] Python tree, ring

OPNEC-Sim[3]

Dedicated NoC simulators

Full-system simulator

C++

Dynamic routing Constant rate XY, adaptive Odd-Even

Uniform

Wormhole

Exponential

XY,VC

Constant rate

Noxim[6]

SystemC

mesh

XY, adaptive

Nirgam[7]

SystemC

Mesh, torus

Source, XY, adaptive, wormhole

NoCSEP[8]

SystemC

Mesh, ring, binary tree, multistage

XY, SPF, dedicated

Java NoC simulator[9]

Java

any

wormhole

DRAGOON [12]

SystemC, VHDL

Fat-tree

Turn-back algorithm

GARNET[13]

C++

any

XY, VC

Possion, burst, on/off Constant rate, burst, input trace Real application driven Uniform Uniform, normal, pareto on/off Uniform random, tornado

the traditional traffic model (uniform, normal, on/off). But NoC is a new class of networks. A traffic model which can reflect the behaviour of on-chip traffic is needed.

Acknowledgement This work is supported by the science & technology program of Shanghai Maritime University. The author is grateful for the anonymous reviewers who made constructive comments.

References 1. kos Hegedus, A., Maggio, G.M., Kocarev, L.: A ns-2 Simulator Utilizing Chaotic Maps for Network-on-Chip Traffic Analysis. ISCAS (4), 3375–3378 (2005) 2. Ali, M., Welzl, M., Hessler, S.: A Fault tolerant mechanism for handling Permanent and Transient Failures in a Network on Chip. In: ITNG 2007, pp. 1027–1032 (2007)

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3. Cai, J., Huang, G., Wang, S., et al.: OPNEC-Sim: An Efficient Simulation Tool for Network-on-Chip Communication and Energy Performance Analysis. In: ICSICT 2010, vol. 2, pp. 1892–1894 (2010) 4. Al-Badi, R., Al-Riyami, M., Alzeid, N.: A Parameterized NoC Simulator Using OMNet++. In: ICUMT 2009, pp. 1–7 (2009) 5. Lu, Z., Thid, R., Millberg, M., et al.: NNSE: Nostrum Network-on-Chip Simulation Environment. In: DATE 2005 University Booth Tool Demonstration (March 2005) 6. http://noxim.sourceforge.net/ 7. http://nirgam.ecs.soton.ac.uk/ 8. Chang, C.-F., Hsu, Y.: A System Exploration Platform for Network-on-Chip. In: ISPA 2010, pp. 359–366 (2010) 9. Grecu, C., Ivanov, A., Saleh, R., et al.: A Flexible Network-on-Chip Simulator for Early Design Space Exploration. In: MNRC 2008, pp. 33–36 (2008) 10. Kahng, A.B., Li, B., Peh, L.-S., Samadi, K.: ORION 2.0: A Power-Area Simulator for Interconnection Networks. In: DATE 2009 (2009) 11. Prabhu, S., Grot, B., Gratz, P.V., Hu, J.: Ocin tsim - DVFS Aware Simulator for NoCs. In: Proc. SAW 2010 (January 2010) 12. Devaux, L., Sassi, S.B., et al.: Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures. International Journal of Reconfigurable Computing (2010) 13. Kumar, A., Agarwal, N., Peh, L.-S., Jha, N.K.: A System-Level Perspective for Efficient NoC Design. In: IPDPS 2008 (2008) 14. Varatkar, G., Marculescu, R.: Traffic analysis for on-chip networks design of multimedia applications. In: Proc. of DAC, New Orleans, Louisiana (June 2002)

Design Methodology of Dynamically Reconfigurable Network-on-Chip Haiyun Gu College of Information Engineering, Shanghai Maritime University, Shanghai 200135, China [email protected]

Abstract. NoC (Network-on-Chip) is inherently suitable to the dynamic partial reconfiguration. DRNoC, combining these two promising technologies, will be a desirable platform for the next generation portable eletronic consuming products. Taking the irregular 2D mesh NoC as a study case, this paper discusses the design methodology of DRNoC, including the topology, router, mapping algorithm, routing algorithm, implementation and simulation of DRNoC. Keywords: NoC, dynamica reconfiguration, Xilinx FPGA

1 Introduction Semiconductor technology entered into the era of deep submicron. Interconnect design issues become more important than computation issues in the field of MPSoC and CMP. The performance, area, and power of on-chip communications deserve great attention. A number of research studies have demonstrated the feasibility and advantages of NoC over traditional bus-based architectures. As a packet switched on-chip network for connecting different kinds of IPs, NoC is inherently compatible with dynamical reconfiguration technology, which can greatly improve the system performance by implementing only the needed tasks intermittently. Because NoC is a layered modular network, which can provide a unified interface to different IPs. No direct comunication between modules, especially between dynamic modules and static modules, can satisfy the requirments of Xilinx DPR design methodology. As far as we know, Xilinx FPGAs (especially the Virtex 2 Pro, Virtex 4, Virtex 5, and Virtex 6) are the only ones that both provide sufficient programmable resources to implement complex applications and support the DPR paradigm[1]. In this paper, we will discuss the design issues of DRNoC, including network topology, router architecture, mapping algorithm, routing protocol, implementation and the simulation technology. Section 2 is a brief review of related work. Section 3 is about design issues of DRNoC, we will take our research case of 2D irrgular mesh DRNoC as an example. Section 4 is about the implementation and simulation of DRNoC. We will give the discussion and conclusion in the last section. M. Ma (Ed.): Communication Systems and Information Technology, LNEE 100, pp. 111–116. springerlink.com © Springer-Verlag Berlin Heidelberg 2011

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2 Related Work The realization of all DPR approaches strongly depends on the characteristics of the underlying hardware. The architecture of DRNoC is also constrained to the features of target FPGA. [2] presented DyNoC Dynamic Network on Chip , in which larger modules can be implemented on a set of neighbor PEs in a mesh topology. The routers inside the boundary of a module are useless. CoNoChi (Configurable Network-on-Chip)[3] propsed to divide the FPGA into rectangular subareas which can be configured as a switch, as a communication line or as part of a hardware module. Modules are connected to a switch through the interface. A switch can be dynamically inserted or deleted. So CoNoChi is a full customed communication architecture. DRAFT (Dynamic Reconfiguration Adapted Fat-Tree)[1] was implemented as a central column into the FPGA, in order to match the architecture of Xilinx Virtex 5 FPGA in which the center column contains I/Os and DPR ports (ICAP). Actually DRAFT itself was static, it can be seen as an independent core of network or even as an IP block connecting each part of the application. CuNoC (Communication Unit Network-on-Chip)[4] was composed of two types of CU: the classic CU and to-give-away CU (Cugw). Each CU was connected at least to one CU of different type as a back-up. Modules replaced one or several CUs according to its size. The CU does not have input/output buffers, but it has one for all 4 inputs.

（

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2 Design Issues of DRNoC Previous works proposed many different forms of NoC, such as mesh, torus, bipolar tree, application-specific toplogy, etc., along with different routing algorithms and strategies. To CMPs, it is reasonable to choose a regular topology NoC, such as mesh, torus, tree etc. But in DRNoC, hundreds of heterogenous IPs which may be vary significantly in size, will be integrated on one chip. So regular topology may suffer from area overhead. On the other hand, full-customed topology may cause much code rewriting work of simulator for the lack of flexibility. We try to get a tradeoff by choose an irregular 2D mesh topology, shown in Fig. 1. In [5], we presented the mathmetic model and mapping algorithm in details. Fig. 1 is a mapping result when using a hybrid objective function, compromising between the communication and area cost by a coefficient. Fig. 2 is a typical architecture of router in NoC. Because of small dimensions, NoC don't have enough resources for Network Interface Card or buffer, but it do have large bandwidth for communication compared to general networks. It means that easier protocols need to be designed for NoCs which require minimum logic and memory resources. Xilinx DPR design flow states that the communications between dynamic and static modules should be performed through a interface called Bus Macro, which uses eight 3-state buffers (TBUFs) hooked up in an arrangement that allows one bit of information to travel between static and dynamic modules[6]. DyNoC defined that the routers can be available as hard macro on the programmable chip, apparently the routers in DyNoC integrated the function of Bus Macros in Xilinx architectures.

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Fig. 1. Irregular 2D mesh NoC

Fig. 2. Router architecture in NoC

CoNoChi used a FIFO capable of storing a complete packet for input ports of the switch. The router in DRAFT connected the DPR modules through the Bus Macros provided by Xilinx. We used Dijkstra routing algorithm to find the shortest path between each pair of source and destination node in NoC. As shown in Fig. 3, each node stands for a router, each edge for the communication channel, and the weight of edge for

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∞ ∞

∞ ∞

∞

∞

∞

Fig. 3. Dijkstra SPF routing

communication cost. Speaking to the irregular 2D mesh, when some edges are covered by the resource module, just set the weights of these edges as infinity. Dynamic reconfiguration means a change of traffic at run-time. The path between source and destincation modules should be calculated at run-time with the consideration of network situations. So simple routing algorithm is more suitable to DRNoC than complexed ones. The congestion control and flow control are open issues that needs more attention. Most of current researches on DYNoC choosed adpative XY routing algorithm.

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4 Implementation and Simulation of DRNoC With the embedded hard and soft processor cores, current FPGAs can provide enough hardware resourecs for designers to implement a complete reconfigurable SoC. Xilinx suggested two flow of partial reconfiguration: module-based and difference based. The first approach is broadly used in DRNoC research. But till now no work really implements or simulates the administration of the whole dynamic reconfiguration process. One reason is that current DRNoC approaches are strong restricted to the characteristics of the underlying hardware (Xilinx FPGA). Another reason is the lack of automative development tools. Recently, [1] proposed DRAGOON to generate and simulate the DRAFT, a static fat-tree topology NoC which was claimed to be dynamically reconfigurable depending on the partial reconfiguration capacity of its underlying Xillinx Virtex 5 FPGA. A simulator of DRNoC which will be not stricted to the underlying hardware is needed. It has been shown that on-chip traffic can exhibit self-similarity, which is also referred as LRD (long-range dependence) [7], but most present simulation framework of NoC used the traditional traffic model (uniform, normal, on/off). Especially, there are three distinct types of communication in DRNoC: administration data, application data and configuration data. Obviously a traffic model which can reflect the behaviour of on-chip traffic of DRNoC is needed.

5 Conclusion In this paper, we discussed the design issues of DRNoC, its implementation and simulation. The irrgular 2D mesh topology is used as a study case. Comparing to the traditional computer or communication network, DRNoC has two distinct different characters: the lack of enough hardware resource, and the strong dependence on the underlying FPGA architectures. Definitely, DRNoC is a very potential technology for portable multemedia applications. More work needs to be done to increase the design efficiency of DRNoC. Acknowledgments. This work is supported by the science & technology program of Shanghai Maritime University. The author is grateful for the anonymous reviewers who made constructive comments.

References 1. Devaux, L., Sassi, S.B., et al.: Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures. International Journal of Reconfigurable Computing (2010) 2. Bobda, C., Ahmadinia, A., Majer, M., Teich, J., Fekete, S., Veen, J.v.d.: DyNoC: a dynamic infrastructure for communicationin dynamically reconfigurable devices. In: Proceedingsof the International Conference on Field Programmable Logicand Applications (FPL 2005), Tampere,Finland, pp. 153–158 (August 2005)

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3. Pionteck, T., Koch, R., Albrecht, C.: Applying partial reconfiguration to networks-onchips. In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL 06), pp. 155–160, Madrid, Spain (August 2006) 4. Jovanovic, S., Tanougast, C., et al.: CuNoC: A dynamic scalable communication structure for dynamically reconfigurable FPGAs. Microprocessors and Microsystems 33, 24–36 (2009) 5. Gu, H., Li, C., Sunshu: Research on Mapping Algorithm of irregular mesh NoC for Portable Multimedia Appliances. In: CCWMSN 2007 (2007) 6. Xilinx: Difference-Based Partial Reconfiguration, Application Note XAPP290 (2007) 7. Varatkar, G., Marculescu, R.: Traffic analysis for on-chip networks design of multimedia applications. In: Proc. of DAC, New Orleans, Louisiana (June 2002)

Numerical Simulation Study on a Flat-Plate Solar Air Collector Wenfang Li, Shuhui Xu, Haiguang Dong, and Jun You Beijing University of Civil Engineering and Architecture, 100044 Beijing, China [email protected]

Abstract. Solar air collector is a solar energy utilization device suitable for heating; a new solar air collector with cylindrical fin in the holes arranged in heat collecting plate was designed and studied. Three different structure of the new solar air collector were simulated. Flow patterns, temperature distribution, solar energy collecting efficiency were analyzed. Based on the simulation, solar air collector with optimal structure parameter was manufactured. The simulated results indicated that heat collecting plate with staggered holes arrangement is superior to that with lined holes arrangement, and collector with segment baffle to make the air flow in zigzag flow improved heat collecting efficiency. Heat collecting efficiency of the new designed collector is about 90%. Keywords: solar energy, air collector, numerical simulation, efficiency.

1 Introduction The major population of China lives in rural area, and the main energy consumption of rural house especially in northern China is heating house in winter. On the other hand, the solar resource in northern China is about 5 MKJ/m2·a, and sun shine hour is about 2000 hrs a year. To use solar energy for heating in northern China rural house is a good way to solve energy and environment problem, and the solar air collector is a simple way to use the solar energy. Solar air collector was studied both theoretically and experimentally. YAO Tao studied air collector efficiency with different material experimentally. The air collector includes vacuum glass, polycarbonate, single glass and double glass, and vacuum glass air collector has higher heat collecting efficiency [1]. ZHANG Liping designed a inclined solar air collector to improve the efficiency [2]. LUO Zanji etc al developed an air collector with vacuum glass tube, and the efficiency improved 30% [3]. N. N. Wadaskar also compared the efficiency of plate air collector and vacuum glass tube air collector, and the efficiency of vacuum glass tube air collector is higher 16.12% [4]. Suleyman Karsli compared the different structure of air collector of tube with fin, plate air collector and heat tube collector, and find the structure and solar radiation influence the efficiency [5]. Murat Caner etc al compared the curve and plate air collector experimentally, and simulated the heating characteristics of the air collector with artificial network model and Matlab [6]. B.M. Ramani studied the M. Ma (Ed.): Communication Systems and Information Technology, LNEE 100, pp. 117–123. springerlink.com © Springer-Verlag Berlin Heidelberg 2011

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porous media in air flow channel to improve the efficiency 20% ~ 25% theoretically and experimentally [7]. A simple low cost plate solar air collector was designed and simulated in this paper. Three different structure models of the new solar air collector were simulated. Flow patterns, temperature distribution, solar energy collecting efficiency were analyzed.

2 Model Establishment 2.1 Physical Model The size of the solar air collector is 1600 mm × 250 mm × 80 mm, it contains glass plate, heat plate, back plate and heat isolation walls, it was shown as Figure 1. Both sides of the heat plate was painted with selective absorb coating. The heat plate is made of aluminum, and holes were arranged in the plate, and a fin was made in every hole.

outlet double openings

equally distributed openings double openings inlet

(a)

(b)

Fig. 1. The structure of the solar air collector. (a) solar air collector; (b) heat plate, d1 = 10 mm, d2 = 15 mm.

Fig. 2. The heat plate holes with cylindrical fin.

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The cylindrical fin was made in every hole arranged in heat plate. The height of the fin is 10 mm, and all plate and fin was coated with selective absorb material, which was shown as Figure 2. 2.2 Mathematical Model For making the calculation convenient, some assumptions and simplification are based on the discussion of the air solar-collector system. A. air flow in constant temperature, low velocity, and uncompressible, satisfying the ideal gaseous state equations; B. air in room meets the Boussinesq assumptions; C. natural convection, forced convection and radiation heat transfer occurred simultaneously. k-ε two-equation turbulent model was used for simulation in the paper. Considering the air as incompressible turbulent flow, it could be described by Reynolds time-average equation and continuity equations, which are as follows in the Descartes rectangular coordinate system. Continuity equation

∂ρU i =0. ∂xi

(1)

⎡ ∂U i ∂U j ⎤ + ) ⎥ + ρβ gi (Tref − T ) . ⎢( μ + μt ) ( ∂x j ∂xi ⎥⎦ ⎢⎣

(2)

Momentum conservation equation

∂ρU i ∂ρU iU j ∂p ∂ + =− + ∂t ∂x j ∂xi ∂x j Energy conservation equation

∂ρ h ∂ρ hU j ∂ ⎡ λ μt ∂h ⎤ + = ) ⎢( + ⎥ + SH . ∂t ∂x j ∂x j ⎣⎢ c p Prt ∂x j ⎦⎥

(3)

where ui is velocity of xi, m/s; uj is velocity of xj, m/s; i = 1, 2, 3 are in the rectangular coordinate; ρ is the density of air, kg/m3; p is the pressure of air, Pa; μ and μt are laminar flow viscosity and turbulence viscosity, kg/(m⋅s); β is thermal expansion coefficient of air, 1/K; Tref is reference temperature, K; T is temperature of air, K; gi is acceleration of gravity, m/s2; h is specific enthalpy of air, J/kg; SH is heat source, W/m3; λ is thermal conductivity of air, W/(m⋅K); cp is specific heat at constant pressure, J/(kg⋅K); Prt is turbulence Prandtl number. k equation

ρ

∂k ∂k ∂ + ρU j = ∂t ∂x j ∂x j

⎡⎛ μt ⎢⎜ μ + σ k ⎣⎢⎝

∂U j ⎛ ∂U j ∂U i ⎞ ∂k ⎤ + ⎜ ⎥ + μt ⎟ ∂xi ⎜⎝ ∂xi ∂x j ⎠ ∂x j ⎦⎥

⎞ − ρε . ⎟⎟ ⎠

(4)

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ε equation ρ

∂ε ∂ε ∂ + ρU j = ∂t ∂x j ∂x j

⎡⎛ μt ⎞ ∂ε ⎤ C1 ∂U j ⎢⎜ μ + ⎥+ μ ⎟ σ ε ⎠ ∂x j ⎥⎦ k t ∂xi ⎢⎣⎝

⎛ ∂U j ∂U i + ⎜⎜ ∂x ∂x j ⎝ i

⎞ ε2 . (5) ⎟⎟ − C2 ρ k ⎠

Turbulence viscosity

μt = ρ Cμ

k2

ε

.

(6)

where Cμ = 0.09, C1 = 1.44, C2 = 1.92, σk = 1.0, σε = 1.3. 2.3 Boundary Condition

The simulation was conducted by solar radiation model with software Fluent 6.0. The average environment temperature is 268K, that is the average winter temperature in Beijing area. The glass plate is 3 mm thickness, density of the glass is ρ = 2220 kg/m3, cp = 830 kJ/(kg·K), λ = 1.15 W/(m·K).

3 Simulation Results Analysis In Figure 3 to Figure 5, it is can be found that when the air collector without baffles, the temperature of the heat collecting plate is high, but the temperature of the air in both channels are relatively low. When segment baffles are installed in the channel, the heat transfer of the plate and air was enhanced, and the air temperature increased. The optimal structure of the collector is the flat-plate arranged staggered holes and baffles in the air channel to enhance the solar radiation absorbing and heat transfer with air. There are two methods to evaluate the performance of the solar air collector. One of them is based on the temperature of air in inlet and outlet, Qd c p mΔt c p m (tout − tin ) . (7) = = Qs I⋅A I⋅A where Qd is the heat air obtained, Qs is the heat of solar radiation, m is the mass flow rate, kg/s; cp is specific heat of air, kJ/(kg·K); I is the solar radiation, W/m2; A is the area of the heat collector, tin is the temperature of air in the inlet, and tout is the temperature of air in the outlet. The second way of the air collector evaluation is based on the total heat flow rate of the air,

η1 =

η2 =

Qa .out − Qa .in . I⋅A

(8)

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(a)

(b)

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bution of the heat plate; (b) Temperature distribution of the side Fig. 3. (a) Temperature distrib wall; (c) Velocity distribution inside of the air collector.

The solar air collector designed d was simulated. Temperature distribution, velocity distribution was shown in Figure F 3 and Figure 4.

Fig. 4. Temperature distributiing on the solar air collector without baffle. line-1: heat colllect plate; line-2: front air channel;; line-3: back air channel.

Fig. 5. Temperature distributing on the solar air collector with segment baffle. line-1: hheat c line-3: back air channel. collect plate; line-2: front air channel;

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Fig. 6. Temperature distributing on the solar air collector with segment baffle. line-1: hheat c line-3: back air channel. collect plate; line-2: front air channel;

The efficiency and param meters of different structure are calculated in table 1. Table 1. The perfformance of three different types of solar air collector Mass Type flow kg/s

T. of inlet K

T. off outleet K

Heat flow Heat flow Solar of inlet of outlet radiation W W W/m2

Plate Solar area radiation m2 W

η %

1

0.03

283.2

288.7 74

-451.16

-261.57

592.2

0.4

236.9

0.800

2

0.03

283.2

289.0 05

-451.16

-248.53

592.2

0.4

236.9

0.866

3

0.03

283.2

290.9 94

-451.16

-235.92

592.2

0.4

236.9

0.899

Note: type 1 is the plate of holes aligned arrangement and without baffle; type 2 is a arrangement and with baffle; type 3 is holes w with holes with cylindrical fin aligned cylindrical fin staggered arrrangement and with baffle.

4 Conclusion Solar air collector with flatt heat collect plate arranged holes, it’s efficiency is abbout 80%. A better arrangemen nt holes increases 4% of the efficiency. Baffles in the air channel also enhance the heat h transfer of plate and air and increase the efficiency about 6%. The heat collect efficiency of the new designed flat plate is about 90%. w was supported in Science Research Project of Beijjing Acknowledgments. This work Municipal Education Com mmission (051100502), Funding Project for Academ mic Human Resources Develo opment in Institutions of Higher Learning Under the Jurisdiction of Beijing Municipality (PHR201007127), Beijing Characteriistic B Environment and Facilities Engineering and the Specialty Construction of Building Key Laboratory of Heating,, Ventilation and Air Conditioning in Beijing.

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References 1. Yao, T.: Study on the Solar Collector with the Novel Transparent Material. D. Tianjin University Master Thesis (2005) (in Chinese) 2. Zhang, L.P., Duan, Q.B.: Numerical Simulation on Solar Air Collector with Tilt TIM. J. Energy Conservation Technology 25, 128–129, 189 (2007) (in Chinese) 3. Luo, Z.J., Cheng, X.Y.: Solar Tubular Air Collector Combined with the Construction. In: China Solar Thermal Utilization Annual Meeting (in Chinese) 4. Wadaskar, N.N.: Experimental Investigation of Vacuum Tube Solar Collector. In: Second International Conference on Emerging Trends in Engineering and Technology, ICETET (2009) 5. Karsli, S.: Performance Analysis of New-design Solar Air Collectors for Drying Applications. J. Renewable Energy 32, 1645–1660 (2007) 6. Caner, M.: Investigation on Thermal Performance Calculation of Two Type Solar Air Collectors Using Artificial Neural Network. Expert Systems with Applications 38, 1668–1674 (2011) 7. Ramani, B.M.: Performance of a Double Pass Solar Air Collector. J. Solar Energy 84, 1929–1937 (2010)

Artificial Immune for Harmful Information Filtering Yan Sun and Xue guang Zhou College of Electronic Engineering, Naval University of Engineering, Wuhan, Hubei 430033, China [email protected], [email protected]

Abstract. Biologically-inspired methods such as evolutionary algorithms and neural networks are well suited to dynamic problems. Artificial immune systems are proving useful in the field of information filtering. We tackle this dynamic problem with IHIF, a harmful information filtering model inspired by the immune system. It is based on a self-organising antibody network that reacts to dynamic evolvement in order to define and preserve the features of harmful Web pages. The experiment results demonstrate IHIF’s ability to filter harmful information. Keywords: information security; artificial immune; harmful information; IHIF.

1 Introduction With the proliferation of harmful Internet content such as pornography, violence, and hate messages, network content security presents great challenges to our evolving information society and economy. Effective content-filtering systems are essential. Many Web-filtering systems are commercially available, and potential users can download trial versions from the Internet. However, the ever changing nature of the Web calls for new techniques designed to classify and filter Web sites and URLs automatically. Bio-inspired approaches are well suited to dynamic problems. Artificial immune systems which could discriminate between the host organism’s own molecules (“self”) and external pathogenic molecules (‘‘non-self’’) have applied to computer virus detection [1], spam email filtering [2-3], intrusion detection [4-5], collaborative filtering [6-7], etc., widely. In this paper, we investigate the problem of pornographic Web site classification and filtering. We propose using artificial immune to classify harmful Web pages during filtering. Unlike most commercial filtering products, which are mainly based on indicative keywords detection or manually collected black list checking, our solution, immune-based harmful information filtering (IHIF), is an automatic machine learning-based pornographic Web site classification and filtering system [8]. IHIF would first be trained to learn a class of harmful patterns. Next, use the trained IHIF to filter those which are similar to previous harmful examples. The rest of this paper is organized as follows. Section 2 investigates related work on harmful information filtering. Section 3 proposes the IHIF model. Section 4 describes key techniques of IHIF. Section 5 presents the experimental results. Finally, section 6 concludes this work. M. Ma (Ed.): Communication Systems and Information Technology, LNEE 100, pp. 125–131. springerlink.com © Springer-Verlag Berlin Heidelberg 2011

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2 Related Work Four approaches can be quote for harmful information filtering. The first one is the Platform for Internet Content Selection(PICS). The PICS is a set of specification for content-rating systems which is supported by Microsoft Internet Explorer, Netscape Navigator and other several Web filtering systems. PICS can only be used as supplementary means for Web content filtering because it is a voluntary self-labelling system freely rated to content provider [9]. The second approach is white-black list approach. White-black list approach allows Web sites on a white list access and block Web sites on a black list access. This approach is hard to construct and maintain the list timely. The third approach is keywords-based approach. If a page contains a certain number of forbidden keywords, it is considered harmful page. This approach is easy to block inoffensive Web pages which fight against violence or pornography [10]. The fourth approach is intelligent content analysis approach [11]. Intelligent content analysis filtering relies on machine learning. Semantic analysis, image processing and other technique can be applied in. Immune-based harmful information filtering we proposed belongs to intelligent content analysis filtering.

3 IHIF Model Design Fig.1 shows the architecture of our IHIF. It entails two processes: antibodies creation and harmful information filtering. In the antibodies generation process, a large sample of Web pages is used to generate mature cell. The harmful information filtering process then uses antibodies to identify harmful information.

Fig. 1. Immune-based harmful information filtering architecture

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Artificial immune systems are not meant to be accurate models of the biological immune system, but use relevant processes and concepts. In our IHIF, antigens are the word bags of Web pages including harmful and non-harmful Web pages. Antibodies consist of URL, title, keywords, update count, update time, abstract, opinion orientation degree, harmful degree and age of Web pages. Self consists of harmful Web pages while non-self consists of non-harmful Web pages. The main processes of IHIF are described as follows. It consists of 8 stages. (1) Choose certain harmful information dictionary according to requirement. (2) Generate the antigen according to the dictionary. (3) Compute the parameters of WebPages. (4) Generate the mature antigen by the strength threshold. (5) Compute affinity between antibody and antigen. (6) Filter the Webpage which include the certain harmful information by matching threshold. (7) Evolve the antigen according to the harmful information Webpage and memor