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© 1999, Cisco Systems, Inc.
LAN Switch Architectures and Performance Session 603
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603 1041_05F9_c2
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© 1999, Cisco Systems, Inc.
LAN Switch Architectures and Performance Session 603
603 1041_05F9_c2
© 1999, Cisco Systems, Inc.
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Agenda Introduction and Definition of Terms • • • • • • • 603 1041_05F9_c2
Queuing Models Switching Implementations Switching Fabrics Example—Catalyst 4000 Series Example—Catalyst 8500 Series Example—Catalyst 6000 Family Example—Catalyst 5000 Family 3
© 1999, Cisco Systems, Inc.
Objective
To understand the components of multilayer switching architectures, how the operate and how they are utilized in the Catalyst switch family
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Definition of Terms • Switching fabric—refers fabric to the “highway” the data takes to get from one port to another • Backplane—a Backplane series of electric traces located on the “back” of the chassis on which data is run; may also include the switching fabric • Queuing—buffer Queuing mechanisms used to control congestion 603 1041_05F9_c2
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Definition of Terms (Cont.)
• Local switching decision— decision Implementation in which switching decisions are made at the local port or line module • Local switching—Packets switching are switched on a switching fabric local to the module or line card 603 1041_05F9_c2
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Definition of Terms (Cont.)
• Oversubscription (blocking)— Condition in which the total bandwidth of the ports is greater than the capacity of the switching fabric • Non-blocking—Condition Non-blocking— in which the fabric contains more bandwidth than the sum total of all the ports 603 1041_05F9_c2
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Definition of Terms (Cont.)
• Head-of-line blocking—Where blocking congestion on an outbound port limits throughput to uncongested ports; completely different from over-subscription
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Layer 2 vs. Layer 3 Switching
Frame Packet
Routing Table
Packet
Packet
Frame Packet
Layer 3 Switching Layer 2 Switching
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Components of Multilayer Switch Architectures Line Line CardCard SiSi
• Congestion Management
LineLine CardCard SiSi
• Switching Decision
Line Line Card Card Si Si
• Switching Fabric
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Line Card
Si Si
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MultiGigabit Switch Fabric
Si Si
Line Card
Si Si
Line Card
Si Si
Line Card
CPU
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Agenda • • • • • • • • 603 1041_05F9_c2
Introduction and Definition of Terms Queuing Models Switching Implementations Switching Fabrics Example—Catalyst 4000 Series Example—Catalyst 8500 Series Example—Catalyst 6000 Family Example—Catalyst 5000 Family © 1999, Cisco Systems, Inc.
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Congestion Management
• Required when multiple ports are contending for the same port • Important if switch fabric is congested 603 1041_05F9_c2
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Dynamic Buffer Queuing Unused Memory Three 64–Byte Frame Uses 192 Bytes of Memory
One 256–Byte Frame Uses 256 Bytes of Memory
• Each buffer fixed in small increments (for example, 64 bytes each) • Allows for efficient use of buffers 603 1041_05F9_c2
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© 1999, Cisco Systems, Inc.
Fixed Buffer Queuing Wasted Memory One 64–Byte Frame Uses One 2000–Byte Buffer One 256–Byte Frame Uses One 2000–Byte Buffer
• Buffer length fixed in size (often to MTU) • Less expensive than custom controllers • Inefficient use of buffers 603 1041_05F9_c2
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Input Queuing
Input Port Data in
Output Port Switching Fabric
Buffer
• Packets buffered at the inbound port • Results in head of line blocking • Reduces throughput to 60% maximum 603 1041_05F9_c2
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© 1999, Cisco Systems, Inc.
Head of Line Blocking Congestion Forcing Mass Queuing at Inbound Port
Congested! Input Module to B
to A
to A
Output Port A Switching Fabric
Data to A and B Buffered at Inbound Port
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Output Port B
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Head of Line Blocking with Input Queuing
Switching Fabric
Data in
Traffic Destined for B
Traffic Destined for A
• Traffic for B cannot enter switching fabric due to data for “A” being ahead of it
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© 1999, Cisco Systems, Inc.
Output Queuing Input Port
Output Port
Data in Switching Fabric
Buffer
• Buffers at the output port • No head of line blocking • Can overflow buffers at peak bursts 603 1041_05F9_c2
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Output Queuing/Shared Buffer Data out to Port 1 Data out to Port 3
Data in
Data out to Port 9
Data out to Port 2
• Central pool of buffers shared between all ports • Maximum throughput with fewest buffers • No head of line blocking
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© 1999, Cisco Systems, Inc.
Multiple Queues per Port Critical Data, High Priority Data in Non-Critical Data, Low Priority
• Can be implemented in either output queuing or shared memory models • Support multiple service levels for QoS
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• Scheduling and/or congestion avoidance algorithm required © 1999, Cisco Systems, Inc.
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Agenda • • • • • • • • 603 1041_05F9_c2
Introduction and Definition of Terms Queuing Models Switching Implementations Switching Fabrics Example—Catalyst 4000 Series Example—Catalyst 8500 Series Example—Catalyst 6000 Family Example—Catalyst 5000 Family © 1999, Cisco Systems, Inc.
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Switching Implementations
• Describe where and how a switching decision is made Where: Locally or centrally How: Longest match, exact match
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Centralized Switching • Central forwarding table utilized
Central Switch ASIC
Forwarding or Routing Table 00-0e1-00-00-00-00 2/3
• Provides centralized control for switching and learning
Switching Fabric
• Lookup done is ASICs for fast processing • Can perform a Layer 2 or Layer 3 lookup 603 1041_05F9_c2
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© 1999, Cisco Systems, Inc.
Distributed Switching • Switching decision made locally by port or module
Forwarding or Routing Table CPU
• L2 and L3 tables must be synchronized to account for adds, moves or changes • Not routers on cards 603 1041_05F9_c2
00-0e1-00-00-00-00 2/3
Switching Fabric
Lookup Table
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Lookup Table
Lookup Table 24
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Route Caching (Flow-Based Switching) • Demand-based switching • Entry containing source, destination and/or Layer 4 information
Route Processor
Ethernet 1 FDDI 2 Ethernet 5 • • •
Central Routing Cache
Switching Fabric
• Flows are unidirectional 603 1041_05F9_c2
Routing Table A3 BB C1
Local Route Cache
Local Route Cache
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© 1999, Cisco Systems, Inc.
Route Caching (Flow-Based Switching) Route Processor
• First packet processed switched by route processor • Flow cache enabled (centrally and/or locally) 603 1041_05F9_c2
Routing Table A3 BB C1
Ethernet 1 Gig E-net 1/0 Fast Ethernet 2/0 • • •
Central Routing Cache
Switching Fabric
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Local Route Cache
Local Route Cache
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Route Caching (Flow-Based Switching) • Subsequent packets in that flow switched via route cache • Flow cache decision made centrally and/or locally
Route Processor
Ethernet 1 Gig E-net 1/0 Fast Ethernet 2/0 • • •
Central Routing Cache SA C1
DA BB
Interface FF 2/0
Switching Fabric Local Route Cache
• All packets switched at Layer 3 603 1041_05F9_c2
Routing Table A3 BB C1
Local Route Cache
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Cisco Express Forwarding (FIB-Based Switching) Routing Protocols OSPF, IGRP Inject Routes EIGRP, RIP, into the BGP, IS-IS Routing
Route Processor
Routing Table A3 BB C1
Ethernet 1 Gig E-net 1/0 Fast Ethernet 2/0 • • •
Table
Forwarding Information SA Base
C1
• Topology-based switching
Interface FF 2/0
Switching Fabric
• Cache pre-populated based on routing table, not traffic 603 1041_05F9_c2
DA BB
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Local FIB
Local FIB
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Cisco Express Forwarding (FIB-Based Switching) Route Processor
• FIB calculated based on routing table entries, not traffic flows • FIB can be kept central or distributed 603 1041_05F9_c2
Routing Table A3 BB C1
Ethernet 1 Gig E-net 1/0 Fast Ethernet 2/0 • • •
Forwarding Information SA Base
DA BB
C1
Interface FF 2/0
Switching Fabric Local FIB
Local FIB
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Cisco Express Forwarding (FIB-Based Switching) • Packet enters router • No process switching necessary • Decision made locally or centrally irregardless of switching fabric 603 1041_05F9_c2
Route Processor
Routing Table A3 BB C1
Ethernet 1 Gig E-net 1/0 Fast Ethernet 2/0 • • •
Forwarding Information SA Base
C1
DA BB
Interface FF 2/0
Switching Fabric
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Local FIB
Local FIB
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Agenda • • • • • • • • 603 1041_05F9_c2
Introduction and Definition of Terms Queuing Models Switching Implementations Switching Fabrics Example—Catalyst 4000 Series Example—Catalyst 8500 Series Example—Catalyst 6000 Family Example—Catalyst 5000 Family 31
© 1999, Cisco Systems, Inc.
Single Bus FDDI Uplink Module
ATM Uplink Module CPU
Forwarding Table 00-0e1-00-00-00-00 2/3
Ethernet Switch Module
Fast Ethernet Switch Module
• One central fabric element • Each port must arbitrate for access • Broadcast and multicast easy • Oversubscription normal 603 1041_05F9_c2
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Unicast Switching over A Single Bus Forwarding Table Client A
Mod3/Port12
Client B
Mod5/Port2
…
Client A
Client B
• Data enters switched port • Bus arbitration takes place • Lookup in forwarding table performed • Packet sent to destination port 603 1041_05F9_c2
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Multicast/Broadcast over A Single Bus Multicast Table Multicast A Mod3/Port12 Mod3/Port12
…
Multicast Source
Client A
Client B
• Flooded data decreases end-station performance • Destination must be only those ports who need that traffic • Multicast or VLAN mechanism must limit traffic to certain ports 603 1041_05F9_c2
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Crossbar Fabrics • Multiple input buses allows for meshed fabric • Typically (but not always) nonblocking • Broadcast/multicast complex • More complex forwarding table lookup 603 1041_05F9_c2
Forwarding Table 00-0e1-00-00-00-00 2/3
CPU
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Unicast Switching over Crossbar Fabrics • Balanced traffic • Ports/modules have access to part of the crossbar • Multiple traffic streams simultaneously in fabric 603 1041_05F9_c2
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Multicast over a Crossbar
• Weakness in a crossbar architecture • Packet replication must occur, possible performance loss • Entire fabric must be “quiet” for multicast to occur 603 1041_05F9_c2
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© 1999, Cisco Systems, Inc.
Shared Memory Architecture Forwarding Table 00-0e1-00-00-00-00 2/3
CPU
Switching Core Module 1 Module 2
Module 3
Shared Memory Pool
Module 4
• Buffering internal to the switching fabric • Switching inputs to memory governed by ASICs • Uses high-speed memory and switching fabric 603 1041_05F9_c2
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Shared Memory Architecture Forwarding Table 00-0e1-00-00-00-00 2/3
CPU High-Speed Switching ASIC
Switching Core Module 1
Module 3
Shared Memory Pool
Module 2
Module 4
• Switching core performs lookup, resolves destination to pointers in memory, switches the packet 603 1041_05F9_c2
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Shared Memory Architecture Forwarding Table 00-0e1-00-00-00-00 2/3
CPU
Large Pool of Dynamically Assigned Buffers
Switching Core Module 1
Module 3
Shared Memory Pool
Module 2
Module 4
• Buffers either fixed or dynamic, less buffers needed if architecture is non-blocking 603 1041_05F9_c2
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Unicast Switching over A Shared Memory Fabric Forwarding Table
• Data enters switch module
00-0e1-00-00-00-00 2/3
• Switched into memory • Switching core evaluates and resolves destination
Switching Core
Module 1
Module 3
Shared Memory
• Packet switched to outgoing module 603 1041_05F9_c2
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Multicast/Broadcast Switching over a Shared Memory Fabric Forwarding Table
• Data enters switch module and is switched into memory
00-0e1-00-00-00-00 2/3
• MAC address lookup reveals packet to be broadcast/multicast
Switching Core
Module 3
Shared Memory
Module 2
Module 1
• Switching core identifies outgoing ports • Packet switched to outgoing multiple outgoing ports 603 1041_05F9_c2
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Local Switching Forwarding Table 00-0e1-00-00-00-00 2/3
Main Fabric Input
• • •
Local Bus
Packet Buffer
• Local switching fabric keeps local traffic off main fabric; increases switch bandwidth • Local architecture can be bus, crossbar or shared memory 603 1041_05F9_c2
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© 1999, Cisco Systems, Inc.
Agenda • • • • • • • • 603 1041_05F9_c2
Introduction and Definition of Terms Queuing Models Switching Implementations Switching Fabrics Example—Catalyst 4000 Series Example—Catalyst 8500 Series Example—Catalyst 6000 Family Example—Catalyst 5000 Family © 1999, Cisco Systems, Inc.
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The Catalyst 4000 Series • Extension of the Catalyst 5000 Family for mid-range wiring closets • Flexible modular configurations • Cost-effective, high-performance 10/100/1000 Ethernet switching • Enterprise software functionality 603 1041_05F9_c2
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Catalyst 4000 Family Features • Catalyst family software • Fast/Gigabit EtherChannel • IEEE 802.1Q support • Per-VLAN spanning tree • UplinkFast • Protocol filtering 603 1041_05F9_c2
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Catalyst 4912 and 2948G • Same architecture as the Catalyst 4000 • All ports access 24 gbps of shared memory • Catalyst 2948G—48 10/100 ports with two Gigabit Ethernet ports • Catalyst 4912—12 1000BaseX ports 603 1041_05F9_c2
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© 1999, Cisco Systems, Inc.
Catalyst 4000 Architecture Switch Controller
Forwarding Table 00-0e1-00-00-00-00 2/3
Line Card
Switching ASIC
Line Card
24 Gbps Shared Memory Fabric
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Catalyst 4000 Architecture Switch Controller
Forwarding Table 00-0e1-00-00-00-00 2/3
Line Card
Non-Blocking Switching Fabric Line Card
Switching ASIC 24 Gbps Shared Memory Fabric
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Catalyst 4000 Architecture 12 Gbps per Line Card
Switch Controller
Forwarding Table 00-0e1-00-00-00-00 2/3
Line Card
Switching ASIC
Line Card
24 Gbps Shared Memory Fabric
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Catalyst 4000 Port Interface— Gigabit Ethernet • 12 Gbps per line card
Non-Blocking Access into Fabric
Shared Memory Fabric
• No buffering or switching on line cards • All intelligence in switching core ASIC 603 1041_05F9_c2
Switching ASIC
GBIC GBIC GBIC GBIC GBIC GBIC
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Catalyst 4000 Port Interface— Fast Ethernet • Breakout ASIC connects 8 10/100 ports to single 1 Gbps fabric port
Breakout ASIC
Switching ASIC Shared Memory Fabric
• Non-blocking 10/100 • All switching on supervisor engine 603 1041_05F9_c2
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Catalyst 4000 Shared Memory 8 MB Shared Memory
Switch Controller
Switch Controller Forwarding Table 00-0e1-00-00-00-00 2/3
Line Card
Switching ASIC
Line Card
24 Gbps Shared Memory Fabric
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Catalyst 4000 Architecture Switch Controller
Switch Controller Forwarding Table 00-0e1-00-00-00-00 2/3
Line Card
Switching ASIC
Centralized Forwarding Engine
Line Card
24 Gbps Shared Memory Fabric
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Frame Switching in the Catalyst 4000 Switch Controller
Switch Controller Forwarding Table 00-0e1-00-00-00-00 2/3
Line Card
Switching ASIC
Line Card
24 Gbps Shared Memory Fabric
Packet Enters Switch, Stored in Memory 603 1041_05F9_c2
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© 1999, Cisco Systems, Inc.
Frame Switching in the Catalyst 4000 Switch Controller
Switch Controller Forwarding Table 00-0e1-00-00-00-00 2/3
Line Card
Switching ASIC
Switching Engine Consulted While Frame Is in Memory
Line Card
24 Gbps Shared Memory Fabric
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Frame Switching in the Catalyst 4000 Switch Controller
Switch Controller Forwarding Table
Destination Found, Packet Sent to Output Port
00-0e1-00-00-00-00 2/3
Line Card
Switching ASIC
Line Card
24 Gbps Shared Memory Fabric
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Catalyst 4003/4912 Performance
• 10/100 for 96 ports 14,285,760 packets per second (64 bytes)
• 1000BaseX for 12 ports 17,857,200 packets per second (64 bytes)
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Catalyst 2948G Performance
• 10/100 for 48 ports 7,142,880 packets per second (64 bytes)
• 1000BaseX for 2 ports 2,961,319 packets per second (64 bytes)
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© 1999, Cisco Systems, Inc.
Agenda • • • • • • • • 603 1041_05F9_c2
Introduction and Definition of Terms Queuing Models Switching Implementations Switching Fabrics Example—Catalyst 4000 Series Example—Catalyst 8500 Series Example—Catalyst 6000 Family Example—Catalyst 5000 Family © 1999, Cisco Systems, Inc.
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Catalyst 8500 Series Cisco IOS®
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Cisco Express Forwarding ™
Wire-Speed IP, IPX Switching
Cisco IOS Routing Protocols
Wire-Speed IP Multicast
Extensive QoS Capabilities
Multiservice Integration
Catalyst 8510 5 Slot
Catalyst 8540 13 Slot 61
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Catalyst 8510 Architecture
Route Processor
Routing Table/ FIB Table 00-0e1-00-00-00-00 2/3
Line Card
Line Card
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10 Gbps Shared Memory Fabric Si Si
Si Si
Si Si
Si Si
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Line Card
Line Card
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Catalyst 8540 Architecture Route Processor
Line Card Line Card Line Card Line Card 603 1041_05F9_c2
Si Si
Routing Table/ FIB Table 00-0e1-00-00-00-00 2/3
40 Gbps Shared Memory Fabric
Si Si
Si Si
Si Si
Si Si
Si Si
Si Si
Si Si
Line Card Line Card Line Card Line Card 63
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Catalyst 8500 Series Switch Fabric
Route Processor
Routing Table/ FIB Table
NonBlocking, Fabric
00-0e1-00-00-00-00 2/3
Line Card
Line Card
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10/40 Gbps Shared Memory Fabric Si Si
Si Si
Si Si
Si Si
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Line Card
Line Card
64
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Dynamic Buffering Architecture Dynamically Allocated Buffers in Fabric
Line Card
Si
Si
Line Card
Shared Memory Fabric
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Multiple Queues per Port Output Queues Serviced According to Priority
Queue 0–6,7 Queue 1–4,5 Queue 2–2,3
Si Si
Queue 3–0,1
Si Si
INT G1/0/0
Shared Memory Fabric
• Traffic in queue 1 destined for A will be serviced more often than queue 4 for B • User A will see less latency 603 1041_05F9_c2
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Weighted Round Robin in the Catalyst 8500 CSR
• Outbound scheduling algorithm • Service assigned via user-defined weights on outbound port • Scheduler enforces bandwidth requirements per queue
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Queue 0 Weight = w ToS = 6,7 Queue 1 Weight = x
ToS = 4,5
Queue 2 Weight = y ToS = 2,3 Queue 3 Weight = z
ToS = 0,1
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Catalyst 8500 Forwarding FIB Computed Centrally via Routing Protocols
Route Processor
Routing Table/ FIB Table 00-0e1-00-00-00-00 2/3
Shared Memory Fabric Line Card
Si Si
Si Si
Line Card
• Cisco IOS processor maintains routing table • Computes forwarding information base 603 1041_05F9_c2
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Catalyst 8500 Distributed FIB Route Processor
Routing Table/ FIB Table 00-0e1-00-00-00-00 2/3
FIB Downloaded to Line Cards Shared Memory Fabric Line Card
Si Si
Line Card
Si Si
Distributed FIB
Distributed FIB
• FIB performs longest match network address lookup in hardware 603 1041_05F9_c2
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© 1999, Cisco Systems, Inc.
Packet Switching in the Catalyst 8500 FIB Table Fast E-net 0/1 Fast E-net 3/6 Fast E-net 5/8
…
FIB Computed and Downloaded to Ports
A3 BB C1
Shared Memory Fabric Line Card
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Si Si
Line Card
Si Si
A3 BB
Fast E-net 0/1 Fast E-net 3/6
A3 BB
Fast E-net 0/1 Fast E-net 3/6
C1
Fast E-net 5/8 • • •
C1
Fast E-net 5/8 • • •
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Packet Switching in the Catalyst 8500 FIB Table Fast E-net 0/1 Fast E-net 3/6 Fast E-net 5/8
…
Packet Enters Switch, Switching Decision Made at Ingress Port
A3 BB C1
Shared Memory Fabric Line Card
Si Si
Line Card
Si Si
A3 BB
Fast E-net 0/1 Fast E-net 3/6
A3 BB
Fast E-net 0/1 Fast E-net 3/6
C1
Fast E-net 5/8 • • •
C1
Fast E-net 5/8 • • •
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Packet Switching in the Catalyst 8500 FIB Table A3 BB C1
Fast E-net 0/1 Fast E-net 3/6 Fast E-net 5/8
…
Packet Switched into Memory; Pointer Set to Outgoing Interface
Shared Memory Fabric Line Card
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Si Si
Line Card
Si Si
A3 BB
Fast E-net 0/1 Fast E-net 3/6
A3 BB
Fast E-net 0/1 Fast E-net 3/6
C1
Fast E-net 5/8 • • •
C1
Fast E-net 5/8 • • •
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Packet Switching in the Catalyst 8500 FIB Table A3 BB C1
Fast E-net 0/1 Fast E-net 3/6 Fast E-net 5/8
…
Frame Rewritten on Egress Port
Shared Memory Fabric Line Card
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Si Si
Line Card
Si Si
A3 BB
Fast E-net 0/1 Fast E-net 3/6
A3 BB
Fast E-net 0/1 Fast E-net 3/6
C1
Fast E-net 5/8 • • •
C1
Fast E-net 5/8 • • •
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Catalyst 8500 Series Performance • Fast Ethernet forwarding rate Catalyst 8510—4.76 million pps Catalyst 8540—19 million pps
• Gigabit Ethernet forwarding rate Catalyst 8510—5.77 million pps Catalyst 8540—23 million pps 603 1041_05F9_c2
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Agenda • • • • • • • • 603 1041_05F9_c2
Introduction and Definition of Terms Queuing Models Switching Implementations Switching Fabrics Example—Catalyst 4000 Series Example—Catalyst 8500 Series Example—Catalyst 6000 Family Example—Catalyst 5000 Family © 1999, Cisco Systems, Inc.
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The Catalyst 6000 Family • Gigabit multilayer switching from Cisco Systems: • Key features include: Wire-speed multilayer switching scalable to 256 Gbps Scalable IP and IPX routing performance to 150 million pps Multiprotocol Cisco IOS routing support for AppleTalk, DECnet, VINES QoS and voice support 603 1041_05F9_c2
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Catalyst 6000 Line Modules Media Module Options • 8-Port Gigabit Ethernet (GBIC support) • 16-Port Gigabit Ethernet • 48-Port 10/100 RJ-45 and Telco • 24-Port 100BaseFX (MT-RJ connector) • 24-Port 10BaseFL (future) • ATM OC-12 (future) Single port, MM or SM Traffic shaping Congestion control mechanisms
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AAL5 support for ABR, VBR, and UBR © 1999, Cisco Systems, Inc.
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Catalyst 6000 Family
• Port densities 384 10/100 ports 192 100BaseFX ports 130 1000BaseX ports 192 10BaseFL ports (future)
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Catalyst 6000 Series Architecture Multilayer Switching Module Layer 3 Switching Engine
Layer 3 Forwarding Table
PINNACLE ASIC
CPU
Multilayer Forwarding Table EARL Switching System
32 Gbps Switching Fabric Control Bus Results Bus
Feature Card Slot Fabric Arbitration Network Mgmt. NMP/MCP
512 KB PINNACLE Buffer ASIC 64 KB Buffer
COIL ASIC
Port 1–12
Supervisor Engine 603 1041_05F9_c2
512 KB PINNACLE Buffer ASIC
Port 1–4
10/100 Ethernet Module
Gigabit Ethernet Module 79
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Catalyst 6000 Series Architecture Layer 3 Integrated into EARL Switching System
Multilayer Forwarding Table EARL Switching System
32 Gbps Switching Fabric
Multilayer Switch Feature Card Fabric Arbitration Network Mgmt. NMP/MCP
Control Bus Results Bus 512 KB PINNACLE Buffer ASIC 64 KB Buffer
COIL ASIC
Port 1–12
Supervisor Engine 603 1041_05F9_c2
10/100 Ethernet Module
512 KB PINNACLE Buffer ASIC
Port 1–4
Gigabit Ethernet Module
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Catalyst 6500 Series Architecture Traces for Future Crossbar Fabric Multilayer Forwarding Table EARL Switching System
32 Gbps Switching Fabric
Multilayer Switch Feature Card Fabric Arbitration Network Mgmt. NMP/MCP
Control Bus Results Bus 512 KB PINNACLE Buffer ASIC 64 KB Buffer
COIL ASIC
Port 1–12
Supervisor Engine 603 1041_05F9_c2
512 KB PINNACLE Buffer ASIC
Port 1–4
10/100 Ethernet Module
Gigabit Ethernet Module 81
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Catalyst 6000 Series Architecture Centralized Switching Fabric Multilayer Forwarding Table EARL Switching System
32 Gbps Switching Fabric
Multilayer Switch Feature Card Fabric Arbitration Network Mgmt. NMP/MCP
Control Bus Results Bus 512 KB PINNACLE Buffer ASIC 64 KB Buffer
COIL ASIC
Port 1–12
Supervisor Engine 603 1041_05F9_c2
10/100 Ethernet Module
512 KB PINNACLE Buffer ASIC
Port 1–4
Gigabit Ethernet Module
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Catalyst 6000 Series Architecture
Multilayer Forwarding Table EARL Switching System
32 Gbps Switching Fabric
Multilayer Switch Feature Card Fabric Arbitration Network Mgmt. NMP/MCP
Control Bus Results Bus 512 KB PINNACLE Buffer ASIC 64 KB Buffer
COIL ASIC
Port 1–12
Supervisor Engine 603 1041_05F9_c2
512 KB PINNACLE Buffer ASIC
Port 1–4
10/100 Ethernet Module
Control Signals
Gigabit Ethernet Module 83
© 1999, Cisco Systems, Inc.
Catalyst 6000 Series Architecture
Multilayer Forwarding Table
Fabric Arbitration
EARL Switching System
32 Gbps Switching Fabric
Multilayer Switch Feature Card Fabric Arbitration Network Mgmt. NMP/MCP
Control Bus Results Bus 512 KB PINNACLE Buffer ASIC 64 KB Buffer
COIL ASIC
Port 1–12
Supervisor Engine 603 1041_05F9_c2
10/100 Ethernet Module
512 KB PINNACLE Buffer ASIC
Port 1–4
Gigabit Ethernet Module
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Catalyst 6000 Series Architecture
Multilayer Forwarding Table
Per-Port Buffering and ASICs
EARL Switching System
32 Gbps Switching Fabric
Multilayer Switch Feature Card Fabric Arbitration Network Mgmt. NMP/MCP
Control Bus Results Bus 512 KB PINNACLE Buffer ASIC 64 KB Buffer
COIL ASIC
Port 1–12
Supervisor Engine 603 1041_05F9_c2
10/100 Ethernet Module
512 KB PINNACLE Buffer ASIC
Port 1–4
Gigabit Ethernet Module
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Port ASIC Built-in Features • InterSwitch Link (ISL) and 802.1Q • In-line rewrite capability for Layer 3 and QoS reclassification • Fast and Gigabit EtherChannel • Four groups of RMON per port • Two queues per port • Four drop thresholds per port 603 1041_05F9_c2
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Catalyst 6000 Port ASICs— Gigabit Ethernet 32 Gbps Switching Fabric
512 KB Buffer per Port
PINNACLE ASIC
Port 1–4
512 KB Buffer per Port
PINNACLE ASIC
Port 5–8
Gigabit Ethernet Module
PINNACLE Controls DMA Access into Per-Port Memory and Performs Arbitration Requests 603 1041_05F9_c2
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Catalyst 6000 Port ASICs— 10/100 and 100BaseFX
Breakout ASICs: 1 Gbps to 12 10/100 Ports
PINNACLE ASIC
COIL ASIC
COIL ASIC
COIL ASIC
Buffering per 10/100 Port
COIL ASIC
Fast Ethernet Module
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Dual Queues and Buffer Allocation—Gigabit Ethernet Switching Fabric Dual Output Queues (Configurable)
Single Input Queue (Store and Forward Check and Arbitration Request)
PINNACLE ASIC
TX(high) 256 KB TX(low) 192 KB
RX 64 KB
Port 3/8
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Dual Queues and Buffer Allocation—Fast Ethernet Switching Bus
PINNACLE ASIC
COIL ASIC
Shared between 12 10/100 Ports TXhigh 256 KB TXlow 192 KB TXhigh 32 KB TXlow 24 KB
RX 64 KB
RX 8 KB
Port 4/48 Dedicated per Port 603 1041_05F9_c2
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QoS Mechanisms in Catalyst 6000 Switching Fabric Weighted Random Early Discard (WRED) Used within Queue for Congestion Avoidance
PINNACLE Low High Priority Queue Priority Queue 192 Kb 256 Kb
Weighted Round Robin Used To Schedule between Queues
PINNACLE WRR Queue Scheduler
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Catalyst 6000 Switching System Route Processor (Control Plane)
Layer Layer 22 Forwarding Forwarding Table Table
Layer Layer 33 Route Route Cache Cache (Forwarding (Forwarding Table) Table)
Access Access List List Table Table
Layer Layer 22 Forwarding Forwarding Engine Engine
Layer Layer 33 Forwarding Forwarding Engine Engine
Access Access List List Engine Engine
Multilayer Multilayer Switch Switch Feature Feature Card Card (Route (Route Processor) Processor)
EARL Switching System
32 Gbps Switching Fabric Results Bus 603 1041_05F9_c2
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Catalyst 6000 Switching System Route Processor (Control Plane)
Layer Layer 22 Forwarding Forwarding Table Table
Layer Layer 33 Route Route Cache Cache (Forwarding (Forwarding Table) Table)
Access Access List List Table Table
Layer Layer 22 Forwarding Forwarding Engine Engine
Layer Layer 33 Forwarding Forwarding Engine Engine
Access Access List List Engine Engine
Multilayer Multilayer Switch Switch Feature Feature Card Card (Route (Route Processor) Processor)
EARL Switching System
32 Gbps Switching Fabric
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Results Bus
Lookup and Forwarding ASICs
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EARL Hashing Algorithm
• Four pages of memory • Hashing algorithm
Page 3 Page 2 Page 1 Page 0 MAC Address
Color
Index
Control
• 128,000 maximum entries • Contains L2/L3/L4 information 603 1041_05F9_c2
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Frame Switching in the Catalyst 6000 Ingress Port Arbitrates, Places Frame on Fabric with SEQ
Multilayer Forwarding Table EARL Switching System
All Ports in the Catalyst 6000
32 Gbps Switching Fabric
Multilayer Switch Feature Card
Control Bus Results Bus 512 KB PINNACLE Buffer ASIC
Fabric Arbitration
64 KB Buffer
Network Mgmt. NMP/MCP
COIL ASIC
Port 1–12
Supervisor Engine 603 1041_05F9_c2
512 KB PINNACLE Buffer ASIC
Port 1–4
10/100 Ethernet Module
Gigabit Ethernet Module 95
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Frame Switching in the Catalyst 6000 Multilayer Forwarding Table EARL Switching System
EARL Makes Switching, Classification Decision
All Ports in the Catalyst 6000
32 Gbps Switching Fabric 32
Multilayer Switch Feature Card Fabric Arbitration Network Mgmt. NMP/MCP
Control Bus Results Bus 512 KB PINNACLE Buffer ASIC 64 KB Buffer
COIL ASIC
Port 1–12
Supervisor Engine 603 1041_05F9_c2
10/100 Ethernet Module
512 KB PINNACLE Buffer ASIC
Port 1–4
Gigabit Ethernet Module
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Frame Switching in the Catalyst 6000 All Ports in the Catalyst 6000
Multilayer Forwarding Table EARL Switching System
32 Gbps Switching Fabric
Multilayer Switch Feature Card Fabric Arbitration Network Mgmt. NMP/MCP
Control Bus Results Bus 512 KB PINNACLE Buffer ASIC 64 KB Buffer
COIL ASIC
Port 1–12
Supervisor Engine 603 1041_05F9_c2
10/100 Ethernet Module
512 KB PINNACLE Buffer ASIC
Port 1–4
Destination Receives Packet, Rewrites if Needed
Gigabit Ethernet Module
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Catalyst 6000 Performance
• Forwarding rate: 100 and 1000 Mbps Layer 2: 15 million packets per second Layer 3 (MSM): 5.2 million packets per second Layer 3 (MSFC): 15 million packets per second
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Agenda • • • • • • • • 603 1041_05F9_c2
Introduction and Definition of Terms Queuing Models Switching Implementations Switching Fabrics Example—Catalyst 4000 Series Example—Catalyst 8500 Series Example—Catalyst 6000 Family Example—Catalyst 5000 Family © 1999, Cisco Systems, Inc.
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The Catalyst 5000 Family • Powerful switching solutions: Multilayer, multiprotocol switching Complete Cisco IOS network services support Integration of gigabit/ATM/Layer 3 on a common platform High-density LAN aggregation 603 1041_05F9_c2
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Catalyst 5500 Architecture Single Bus Switching Fabric
Route Processor Buffer
Layer 2 Table Layer 3 Route Cache
BIGA ASIC
SAGE ASIC NetFlow Feature Card
BIGA ASIC
Buffer
SAGE ASIC
LCP
3.6 Gbps Switching Fabric
Bus Arbiter RMON Statistics
LCP
Network Mgmt. NMP/MCP
Supervisor Engine III 603 1041_05F9_c2
256 KB Buffer
SAINT ASIC
Port 8
256 KB Buffer
SAINT ASIC
Port 25
Ethernet Module 101
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Catalyst 5500 Architecture Route Processor
Central Bus Arbiter Buffer
Layer 2 Table Layer 3 Route Cache
BIGA ASIC
SAGE ASIC NetFlow Feature Card
BIGA ASIC
Buffer
SAGE ASIC
LCP
3.6 Gbps Switching Fabric
Bus Arbiter RMON Statistics Network Mgmt. NMP/MCP
Supervisor Engine III 603 1041_05F9_c2
LCP
256 KB Buffer
Port 8
SAINT ASIC
256 KB Buffer
Port 25
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SAINT ASIC
Ethernet Module 102
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Catalyst 5500 Architecture Route Processor
Layer 2 Table Layer 3 Route Cache
Per-Port ASICs and Buffering
Buffer
BIGA ASIC
BIGA ASIC
SAGE ASIC NetFlow Feature Card
Buffer
SAGE ASIC
LCP
3.6 Gbps Switching Fabric
Bus Arbiter RMON Statistics
LCP
Network Mgmt. NMP/MCP
Supervisor Engine III 603 1041_05F9_c2
256 KB Buffer
SAINT ASIC
Port 8
256 KB Buffer
SAINT ASIC
Port 25
Ethernet Module 103
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Catalyst 5500 Port Interface Results Bus Switching Fabric
Saint ASIC
DMA Engine CPU Interface
Rewrite Engine
Packet Buffer Transmit 224 Kb
10/100 MAC
Receive 32 Kb
Physical Layer Interface 603 1041_05F9_c2
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Catalyst 5500 Architecture
Layer 2 Table Layer 3 Route Cache
Central Switching and Classification Engine
Route Processor Buffer
BIGA ASIC
BIGA ASIC
SAGE ASIC NetFlow Feature Card
Buffer
SAGE ASIC
LCP
3.6 Gbps Switching Fabric
Bus Arbiter RMON Statistics Network Mgmt. NMP/MCP
Supervisor Engine III 603 1041_05F9_c2
LCP
256 KB Buffer
SAINT ASIC
256 KB Buffer
Port 8
SAINT ASIC
Port 25
Ethernet Module 105
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Components of Catalyst 5500 Multilayer Switching (MLS) MLS-SE—Switch Engine
MLS-RP— Route Processor
NFFC
or RSM
Cisco 7500 Series 7200 Series 4000 Series 3600
MLSP—Multilayer Switching Protocol for Router Registration with MLS-SE 603 1041_05F9_c2
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Multilayer Switching Protocol (MLSP) • Allows RSM, Cisco 7500, Cisco 4000, Cisco 3600 and Cisco 7200 series routers to provide route processing functionality • Used for router registration and services (i.e., access list) updates for NFFC • Not used in Layer 3 switching itself 603 1041_05F9_c2
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Frame Switching in the Catalyst 5500
Layer 2 Table Layer 3 Route Cache
Route Processor
Data Enters Port and Is Sent to All Ports in the Switch
Buffer
BIGA ASIC
SAGE ASIC NetFlow Feature Card
BIGA ASIC
Buffer
SAGE ASIC
LCP
3.6 Gbps Switching Fabric
Bus Arbiter RMON Statistics Network Mgmt. NMP/MCP
Supervisor Engine III 603 1041_05F9_c2
LCP
256 KB Buffer
Port 8
SAINT ASIC
256 KB Buffer
Port 25
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SAINT ASIC
Ethernet Module 108
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Frame Switching in the Catalyst 5500
Layer 2 Table Layer 3 Route Cache
Route Processor
NFFC Identifies Port-of-Exit and Policy
Buffer
BIGA ASIC
SAGE ASIC NetFlow Feature Card
BIGA ASIC
Buffer
SAGE ASIC
LCP
3.6 Gbps Switching Fabric
Bus Arbiter RMON Statistics Network Mgmt. NMP/MCP
Supervisor Engine III 603 1041_05F9_c2
LCP
256 KB Buffer
SAINT ASIC
Port 8
256 KB Buffer
SAINT ASIC
Port 25
Ethernet Module 109
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Frame Switching in the Catalyst 5500
Layer 2 Table Layer 3 Route Cache NetFlow Feature Card
Route Processor
If L3 Decision and No NFFC Entry Exists, Packet Goes to RSM
Buffer
BIGA ASIC
SAGE ASIC
BIGA ASIC
Buffer
SAGE ASIC
LCP
3.6 Gbps Switching Fabric
Bus Arbiter RMON Statistics Network Mgmt. NMP/MCP
Supervisor Engine III 603 1041_05F9_c2
LCP
256 KB Buffer
Port 8
SAINT ASIC
256 KB Buffer
Port 25
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SAINT ASIC
Ethernet Module 110
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Frame Switching in the Catalyst 5500
Layer 2 Table Layer 3 Route Cache
Route Processor
If NFFC Has Entry at L2 or L3, Outbound Port Keeps Frame; All Others Discard
NetFlow Feature Card
Buffer
BIGA ASIC
SAGE ASIC
BIGA ASIC
Buffer
SAGE ASIC
LCP
3.6 Gbps Switching Fabric
Bus Arbiter RMON Statistics Network Mgmt. NMP/MCP
Supervisor Engine III 603 1041_05F9_c2
LCP
256 KB Buffer
SAINT ASIC
Port 8
256 KB Buffer
SAINT ASIC
Port 25
Ethernet Module 111
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Frame Switching in the Catalyst 5500
Layer 2 Table Layer 3 Route Cache
Route Processor
Outbound Port Rewrites IP TOS and/or Dest Dest.. MAC Address
NetFlow Feature Card
Buffer
BIGA ASIC
SAGE ASIC
BIGA ASIC
Buffer
SAGE ASIC
LCP
3.6 Gbps Switching Fabric
Bus Arbiter RMON Statistics Network Mgmt. NMP/MCP
Supervisor Engine III 603 1041_05F9_c2
LCP
256 KB Buffer
Port 8
SAINT ASIC
256 KB Buffer
Port 25
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SAINT ASIC
Ethernet Module 112
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Catalyst 5000 Family Layer 2 Performance • Forwarding rate: 10 Mbps 2,200,000 pps aggregate
• Forwarding rate: 100 Mbps 2,200,000 pps aggregate
• Forwarding rate: 1000 Mbps 35.7 million pps (with local switching)
• Multicast forwarding rate: 100 Mbps 39.2 million pps 603 1041_05F9_c2
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Catalyst 5000 Series Layer 3 Forwarding Rates • Route Switch Module (RSM)— 175,000 pps • NetFlow Feature Card (NFFC-II)— 2.0 million pps • Total system throughput (including Catalyst 8510 SRP and line cards in the Catalyst 5500)—8 million pps 603 1041_05F9_c2
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Additional Talks • Router Architecture and Performance • Deploying Campus-Based Protocols • Deploying High-Availability Networks • Introduction to Campus QoS • Deploying IP Switching Protocols • Catalyst Product Updates 603 1041_05F9_c2
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Conclusion
A switch’s performance, scalability and features rely on critical elements within the architecture
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Please Complete Your Evaluation Form Session 603
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